0s autopkgtest [11:02:54]: starting date and time: 2025-05-06 11:02:54+0000 0s autopkgtest [11:02:54]: git checkout: 9986aa8c Merge branch 'skia/fix_network_interface' into 'ubuntu/production' 0s autopkgtest [11:02:54]: host juju-7f2275-prod-proposed-migration-environment-20; command line: /home/ubuntu/autopkgtest/runner/autopkgtest --output-dir /tmp/autopkgtest-work.n2qjaujo/out --timeout-copy=6000 --setup-commands /home/ubuntu/autopkgtest-cloud/worker-config-production/setup-canonical.sh --apt-pocket=proposed=src:gawk --apt-upgrade yosys --timeout-short=300 --timeout-copy=20000 --timeout-build=20000 --env=ADT_TEST_TRIGGERS=gawk/1:5.3.2-1 -- ssh -s /home/ubuntu/autopkgtest/ssh-setup/nova -- --flavor autopkgtest-ppc64el --security-groups autopkgtest-juju-7f2275-prod-proposed-migration-environment-20@bos03-ppc64el-1.secgroup --name adt-questing-ppc64el-yosys-20250506-074336-juju-7f2275-prod-proposed-migration-environment-20-ad3c206a-44df-4a60-ac60-fd010cacdeca --image adt/ubuntu-questing-ppc64el-server --keyname testbed-juju-7f2275-prod-proposed-migration-environment-20 --net-id=net_prod-proposed-migration-ppc64el -e TERM=linux --mirror=http://ftpmaster.internal/ubuntu/ 130s autopkgtest [11:05:04]: testbed dpkg architecture: ppc64el 130s autopkgtest [11:05:04]: testbed apt version: 3.0.0 130s autopkgtest [11:05:04]: @@@@@@@@@@@@@@@@@@@@ test bed setup 130s autopkgtest [11:05:04]: testbed release detected to be: None 131s autopkgtest [11:05:05]: updating testbed package index (apt update) 131s Get:1 http://ftpmaster.internal/ubuntu questing-proposed InRelease [110 kB] 132s Hit:2 http://ftpmaster.internal/ubuntu questing InRelease 132s Hit:3 http://ftpmaster.internal/ubuntu questing-updates InRelease 132s Hit:4 http://ftpmaster.internal/ubuntu questing-security InRelease 132s Get:5 http://ftpmaster.internal/ubuntu questing-proposed/main Sources [76.7 kB] 132s Get:6 http://ftpmaster.internal/ubuntu questing-proposed/multiverse Sources [27.3 kB] 132s Get:7 http://ftpmaster.internal/ubuntu questing-proposed/universe Sources [655 kB] 132s Get:8 http://ftpmaster.internal/ubuntu questing-proposed/main ppc64el Packages [143 kB] 132s Get:9 http://ftpmaster.internal/ubuntu questing-proposed/universe ppc64el Packages [666 kB] 132s Get:10 http://ftpmaster.internal/ubuntu questing-proposed/multiverse ppc64el Packages [18.1 kB] 132s Fetched 1696 kB in 1s (1784 kB/s) 133s Reading package lists... 134s autopkgtest [11:05:08]: upgrading testbed (apt dist-upgrade and autopurge) 134s Reading package lists... 134s Building dependency tree... 134s Reading state information... 135s Calculating upgrade...Starting pkgProblemResolver with broken count: 0 135s Starting 2 pkgProblemResolver with broken count: 0 135s Done 135s Entering ResolveByKeep 135s 136s Calculating upgrade... 136s The following package was automatically installed and is no longer required: 136s libsigsegv2 136s Use 'sudo apt autoremove' to remove it. 136s The following packages will be upgraded: 136s dhcpcd-base dirmngr gawk gir1.2-glib-2.0 gnupg gnupg-l10n gnupg-utils gpg 136s gpg-agent gpg-wks-client gpgconf gpgsm gpgv groff-base keyboxd 136s libglib2.0-0t64 libglib2.0-data libnuma1 libperl5.40 libpython3.12-minimal 136s libpython3.12-stdlib libpython3.12t64 libsemanage-common libsemanage2 136s libx11-6 libx11-data libxml2 numactl openssh-client openssh-server 136s openssh-sftp-server perl perl-base perl-modules-5.40 python3-dbus 136s python3-wadllib 136s 36 upgraded, 0 newly installed, 0 to remove and 0 not upgraded. 136s Need to get 26.5 MB of archives. 136s After this operation, 274 kB disk space will be freed. 136s Get:1 http://ftpmaster.internal/ubuntu questing/main ppc64el libperl5.40 ppc64el 5.40.1-3 [4949 kB] 137s Get:2 http://ftpmaster.internal/ubuntu questing/main ppc64el perl ppc64el 5.40.1-3 [262 kB] 137s Get:3 http://ftpmaster.internal/ubuntu questing/main ppc64el perl-base ppc64el 5.40.1-3 [1923 kB] 137s Get:4 http://ftpmaster.internal/ubuntu questing/main ppc64el perl-modules-5.40 all 5.40.1-3 [3217 kB] 137s Get:5 http://ftpmaster.internal/ubuntu questing-proposed/main ppc64el gawk ppc64el 1:5.3.2-1 [538 kB] 137s Get:6 http://ftpmaster.internal/ubuntu questing/main ppc64el openssh-sftp-server ppc64el 1:9.9p1-3ubuntu3.1 [43.4 kB] 137s Get:7 http://ftpmaster.internal/ubuntu questing/main ppc64el openssh-server ppc64el 1:9.9p1-3ubuntu3.1 [679 kB] 137s Get:8 http://ftpmaster.internal/ubuntu questing/main ppc64el openssh-client ppc64el 1:9.9p1-3ubuntu3.1 [1168 kB] 137s Get:9 http://ftpmaster.internal/ubuntu questing/main ppc64el libsemanage-common all 3.8.1-1 [7826 B] 137s Get:10 http://ftpmaster.internal/ubuntu questing/main ppc64el libsemanage2 ppc64el 3.8.1-1 [121 kB] 137s Get:11 http://ftpmaster.internal/ubuntu questing/main ppc64el gpg-wks-client ppc64el 2.4.4-2ubuntu24 [84.3 kB] 137s Get:12 http://ftpmaster.internal/ubuntu questing/main ppc64el dirmngr ppc64el 2.4.4-2ubuntu24 [390 kB] 137s Get:13 http://ftpmaster.internal/ubuntu questing/main ppc64el gpgsm ppc64el 2.4.4-2ubuntu24 [292 kB] 137s Get:14 http://ftpmaster.internal/ubuntu questing/main ppc64el gnupg-utils ppc64el 2.4.4-2ubuntu24 [123 kB] 137s Get:15 http://ftpmaster.internal/ubuntu questing/main ppc64el gpg-agent ppc64el 2.4.4-2ubuntu24 [275 kB] 137s Get:16 http://ftpmaster.internal/ubuntu questing/main ppc64el gpg ppc64el 2.4.4-2ubuntu24 [707 kB] 137s Get:17 http://ftpmaster.internal/ubuntu questing/main ppc64el gpgconf ppc64el 2.4.4-2ubuntu24 [115 kB] 137s Get:18 http://ftpmaster.internal/ubuntu questing/main ppc64el gnupg all 2.4.4-2ubuntu24 [359 kB] 137s Get:19 http://ftpmaster.internal/ubuntu questing/main ppc64el keyboxd ppc64el 2.4.4-2ubuntu24 [93.1 kB] 137s Get:20 http://ftpmaster.internal/ubuntu questing/main ppc64el gpgv ppc64el 2.4.4-2ubuntu24 [197 kB] 137s Get:21 http://ftpmaster.internal/ubuntu questing/main ppc64el dhcpcd-base ppc64el 1:10.1.0-10 [280 kB] 137s Get:22 http://ftpmaster.internal/ubuntu questing/main ppc64el gir1.2-glib-2.0 ppc64el 2.84.1-2 [184 kB] 137s Get:23 http://ftpmaster.internal/ubuntu questing/main ppc64el libglib2.0-0t64 ppc64el 2.84.1-2 [1803 kB] 137s Get:24 http://ftpmaster.internal/ubuntu questing/main ppc64el libglib2.0-data all 2.84.1-2 [53.2 kB] 137s Get:25 http://ftpmaster.internal/ubuntu questing/main ppc64el libxml2 ppc64el 2.12.7+dfsg+really2.9.14-0.4ubuntu0.1 [836 kB] 137s Get:26 http://ftpmaster.internal/ubuntu questing/main ppc64el python3-dbus ppc64el 1.4.0-1 [109 kB] 137s Get:27 http://ftpmaster.internal/ubuntu questing/main ppc64el groff-base ppc64el 1.23.0-8 [1110 kB] 137s Get:28 http://ftpmaster.internal/ubuntu questing/main ppc64el libnuma1 ppc64el 2.0.19-1 [27.9 kB] 137s Get:29 http://ftpmaster.internal/ubuntu questing/main ppc64el libx11-data all 2:1.8.12-1 [116 kB] 137s Get:30 http://ftpmaster.internal/ubuntu questing/main ppc64el libx11-6 ppc64el 2:1.8.12-1 [739 kB] 137s Get:31 http://ftpmaster.internal/ubuntu questing/main ppc64el numactl ppc64el 2.0.19-1 [43.2 kB] 137s Get:32 http://ftpmaster.internal/ubuntu questing/main ppc64el gnupg-l10n all 2.4.4-2ubuntu24 [66.8 kB] 137s Get:33 http://ftpmaster.internal/ubuntu questing-proposed/universe ppc64el libpython3.12t64 ppc64el 3.12.10-1 [2558 kB] 137s Get:34 http://ftpmaster.internal/ubuntu questing-proposed/universe ppc64el libpython3.12-stdlib ppc64el 3.12.10-1 [2105 kB] 138s Get:35 http://ftpmaster.internal/ubuntu questing-proposed/universe ppc64el libpython3.12-minimal ppc64el 3.12.10-1 [841 kB] 138s Get:36 http://ftpmaster.internal/ubuntu questing/main ppc64el python3-wadllib all 2.0.0-3 [36.3 kB] 138s Preconfiguring packages ... 138s Fetched 26.5 MB in 2s (14.9 MB/s) 138s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 107214 files and directories currently installed.) 138s Preparing to unpack .../libperl5.40_5.40.1-3_ppc64el.deb ... 138s Unpacking libperl5.40:ppc64el (5.40.1-3) over (5.40.1-2) ... 139s Preparing to unpack .../perl_5.40.1-3_ppc64el.deb ... 139s Unpacking perl (5.40.1-3) over (5.40.1-2) ... 139s Preparing to unpack .../perl-base_5.40.1-3_ppc64el.deb ... 139s Unpacking perl-base (5.40.1-3) over (5.40.1-2) ... 139s Setting up perl-base (5.40.1-3) ... 139s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 107214 files and directories currently installed.) 139s Preparing to unpack .../0-perl-modules-5.40_5.40.1-3_all.deb ... 139s Unpacking perl-modules-5.40 (5.40.1-3) over (5.40.1-2) ... 139s Preparing to unpack .../1-gawk_1%3a5.3.2-1_ppc64el.deb ... 139s Unpacking gawk (1:5.3.2-1) over (1:5.2.1-2build3) ... 139s Preparing to unpack .../2-openssh-sftp-server_1%3a9.9p1-3ubuntu3.1_ppc64el.deb ... 139s Unpacking openssh-sftp-server (1:9.9p1-3ubuntu3.1) over (1:9.9p1-3ubuntu3) ... 139s Preparing to unpack .../3-openssh-server_1%3a9.9p1-3ubuntu3.1_ppc64el.deb ... 140s Unpacking openssh-server (1:9.9p1-3ubuntu3.1) over (1:9.9p1-3ubuntu3) ... 140s Preparing to unpack .../4-openssh-client_1%3a9.9p1-3ubuntu3.1_ppc64el.deb ... 140s Unpacking openssh-client (1:9.9p1-3ubuntu3.1) over (1:9.9p1-3ubuntu3) ... 140s Preparing to unpack .../5-libsemanage-common_3.8.1-1_all.deb ... 140s Unpacking libsemanage-common (3.8.1-1) over (3.7-2.1build1) ... 140s Setting up libsemanage-common (3.8.1-1) ... 140s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 107216 files and directories currently installed.) 140s Preparing to unpack .../libsemanage2_3.8.1-1_ppc64el.deb ... 140s Unpacking libsemanage2:ppc64el (3.8.1-1) over (3.7-2.1build1) ... 140s Setting up libsemanage2:ppc64el (3.8.1-1) ... 140s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 107216 files and directories currently installed.) 140s Preparing to unpack .../0-gpg-wks-client_2.4.4-2ubuntu24_ppc64el.deb ... 140s Unpacking gpg-wks-client (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 140s Preparing to unpack .../1-dirmngr_2.4.4-2ubuntu24_ppc64el.deb ... 140s Unpacking dirmngr (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 140s Preparing to unpack .../2-gpgsm_2.4.4-2ubuntu24_ppc64el.deb ... 140s Unpacking gpgsm (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 140s Preparing to unpack .../3-gnupg-utils_2.4.4-2ubuntu24_ppc64el.deb ... 140s Unpacking gnupg-utils (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 140s Preparing to unpack .../4-gpg-agent_2.4.4-2ubuntu24_ppc64el.deb ... 140s Unpacking gpg-agent (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 140s Preparing to unpack .../5-gpg_2.4.4-2ubuntu24_ppc64el.deb ... 140s Unpacking gpg (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 140s Preparing to unpack .../6-gpgconf_2.4.4-2ubuntu24_ppc64el.deb ... 140s Unpacking gpgconf (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 140s Preparing to unpack .../7-gnupg_2.4.4-2ubuntu24_all.deb ... 140s Unpacking gnupg (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 140s Preparing to unpack .../8-keyboxd_2.4.4-2ubuntu24_ppc64el.deb ... 140s Unpacking keyboxd (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 140s Preparing to unpack .../9-gpgv_2.4.4-2ubuntu24_ppc64el.deb ... 140s Unpacking gpgv (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 140s Setting up gpgv (2.4.4-2ubuntu24) ... 140s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 107216 files and directories currently installed.) 140s Preparing to unpack .../00-dhcpcd-base_1%3a10.1.0-10_ppc64el.deb ... 140s Unpacking dhcpcd-base (1:10.1.0-10) over (1:10.1.0-8) ... 140s Preparing to unpack .../01-gir1.2-glib-2.0_2.84.1-2_ppc64el.deb ... 140s Unpacking gir1.2-glib-2.0:ppc64el (2.84.1-2) over (2.84.1-1) ... 140s Preparing to unpack .../02-libglib2.0-0t64_2.84.1-2_ppc64el.deb ... 140s Unpacking libglib2.0-0t64:ppc64el (2.84.1-2) over (2.84.1-1) ... 140s Preparing to unpack .../03-libglib2.0-data_2.84.1-2_all.deb ... 140s Unpacking libglib2.0-data (2.84.1-2) over (2.84.1-1) ... 140s Preparing to unpack .../04-libxml2_2.12.7+dfsg+really2.9.14-0.4ubuntu0.1_ppc64el.deb ... 140s Unpacking libxml2:ppc64el (2.12.7+dfsg+really2.9.14-0.4ubuntu0.1) over (2.12.7+dfsg+really2.9.14-0.4) ... 140s Preparing to unpack .../05-python3-dbus_1.4.0-1_ppc64el.deb ... 141s Unpacking python3-dbus (1.4.0-1) over (1.3.2-5build5) ... 141s Preparing to unpack .../06-groff-base_1.23.0-8_ppc64el.deb ... 141s Unpacking groff-base (1.23.0-8) over (1.23.0-7) ... 141s Preparing to unpack .../07-libnuma1_2.0.19-1_ppc64el.deb ... 141s Unpacking libnuma1:ppc64el (2.0.19-1) over (2.0.18-1build1) ... 141s Preparing to unpack .../08-libx11-data_2%3a1.8.12-1_all.deb ... 141s Unpacking libx11-data (2:1.8.12-1) over (2:1.8.10-2) ... 141s Preparing to unpack .../09-libx11-6_2%3a1.8.12-1_ppc64el.deb ... 141s Unpacking libx11-6:ppc64el (2:1.8.12-1) over (2:1.8.10-2) ... 141s Preparing to unpack .../10-numactl_2.0.19-1_ppc64el.deb ... 141s Unpacking numactl (2.0.19-1) over (2.0.18-1build1) ... 141s Preparing to unpack .../11-gnupg-l10n_2.4.4-2ubuntu24_all.deb ... 141s Unpacking gnupg-l10n (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 141s Preparing to unpack .../12-libpython3.12t64_3.12.10-1_ppc64el.deb ... 141s Unpacking libpython3.12t64:ppc64el (3.12.10-1) over (3.12.8-3) ... 141s Preparing to unpack .../13-libpython3.12-stdlib_3.12.10-1_ppc64el.deb ... 141s Unpacking libpython3.12-stdlib:ppc64el (3.12.10-1) over (3.12.8-3) ... 141s Preparing to unpack .../14-libpython3.12-minimal_3.12.10-1_ppc64el.deb ... 141s Unpacking libpython3.12-minimal:ppc64el (3.12.10-1) over (3.12.8-3) ... 141s Preparing to unpack .../15-python3-wadllib_2.0.0-3_all.deb ... 141s Unpacking python3-wadllib (2.0.0-3) over (2.0.0-2) ... 141s Setting up gawk (1:5.3.2-1) ... 141s Setting up openssh-client (1:9.9p1-3ubuntu3.1) ... 141s Setting up libpython3.12-minimal:ppc64el (3.12.10-1) ... 141s Setting up libglib2.0-0t64:ppc64el (2.84.1-2) ... 141s No schema files found: doing nothing. 141s Setting up libglib2.0-data (2.84.1-2) ... 141s Setting up libx11-data (2:1.8.12-1) ... 141s Setting up gnupg-l10n (2.4.4-2ubuntu24) ... 141s Setting up python3-wadllib (2.0.0-3) ... 142s Setting up dhcpcd-base (1:10.1.0-10) ... 142s Installing new version of config file /etc/dhcpcd.conf ... 142s Setting up gir1.2-glib-2.0:ppc64el (2.84.1-2) ... 142s Setting up libnuma1:ppc64el (2.0.19-1) ... 142s Setting up perl-modules-5.40 (5.40.1-3) ... 142s Setting up groff-base (1.23.0-8) ... 142s Setting up gpgconf (2.4.4-2ubuntu24) ... 142s Setting up libx11-6:ppc64el (2:1.8.12-1) ... 142s Setting up libxml2:ppc64el (2.12.7+dfsg+really2.9.14-0.4ubuntu0.1) ... 142s Setting up gpg (2.4.4-2ubuntu24) ... 142s Setting up gnupg-utils (2.4.4-2ubuntu24) ... 142s Setting up openssh-sftp-server (1:9.9p1-3ubuntu3.1) ... 142s Setting up python3-dbus (1.4.0-1) ... 142s Setting up gpg-agent (2.4.4-2ubuntu24) ... 142s Setting up libpython3.12-stdlib:ppc64el (3.12.10-1) ... 142s Setting up numactl (2.0.19-1) ... 142s Setting up openssh-server (1:9.9p1-3ubuntu3.1) ... 144s Setting up gpgsm (2.4.4-2ubuntu24) ... 144s Setting up libpython3.12t64:ppc64el (3.12.10-1) ... 144s Setting up libperl5.40:ppc64el (5.40.1-3) ... 144s Setting up dirmngr (2.4.4-2ubuntu24) ... 144s Setting up perl (5.40.1-3) ... 144s Setting up keyboxd (2.4.4-2ubuntu24) ... 144s Setting up gnupg (2.4.4-2ubuntu24) ... 144s Setting up gpg-wks-client (2.4.4-2ubuntu24) ... 144s Processing triggers for ufw (0.36.2-9) ... 144s Processing triggers for man-db (2.13.1-1) ... 145s Processing triggers for install-info (7.1.1-1) ... 146s Processing triggers for libc-bin (2.41-6ubuntu1) ... 146s Reading package lists... 146s Building dependency tree... 146s Reading state information... 147s Starting pkgProblemResolver with broken count: 0 147s Starting 2 pkgProblemResolver with broken count: 0 147s Done 147s Solving dependencies... 147s The following packages will be REMOVED: 147s libsigsegv2* 148s 0 upgraded, 0 newly installed, 1 to remove and 0 not upgraded. 148s After this operation, 96.3 kB disk space will be freed. 148s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 107216 files and directories currently installed.) 148s Removing libsigsegv2:ppc64el (2.14-1ubuntu2) ... 148s Processing triggers for libc-bin (2.41-6ubuntu1) ... 148s autopkgtest [11:05:22]: rebooting testbed after setup commands that affected boot 179s autopkgtest [11:05:53]: testbed running kernel: Linux 6.14.0-15-generic #15-Ubuntu SMP Sun Apr 6 14:52:42 UTC 2025 182s autopkgtest [11:05:56]: @@@@@@@@@@@@@@@@@@@@ apt-source yosys 187s Get:1 http://ftpmaster.internal/ubuntu questing/universe yosys 0.33-5build2 (dsc) [3069 B] 187s Get:2 http://ftpmaster.internal/ubuntu questing/universe yosys 0.33-5build2 (tar) [6161 kB] 187s Get:3 http://ftpmaster.internal/ubuntu questing/universe yosys 0.33-5build2 (tar) [2586 kB] 187s Get:4 http://ftpmaster.internal/ubuntu questing/universe yosys 0.33-5build2 (diff) [30.3 kB] 187s gpgv: Signature made Mon Apr 1 04:53:46 2024 UTC 187s gpgv: using RSA key A089FB36AAFBDAD5ACC1325069F790171A210984 187s gpgv: Can't check signature: No public key 187s dpkg-source: warning: cannot verify inline signature for ./yosys_0.33-5build2.dsc: no acceptable signature found 187s autopkgtest [11:06:01]: testing package yosys version 0.33-5build2 188s autopkgtest [11:06:02]: build not needed 226s autopkgtest [11:06:40]: test yosys-testsuite: preparing testbed 227s Reading package lists... 227s Building dependency tree... 227s Reading state information... 227s Starting pkgProblemResolver with broken count: 0 227s Starting 2 pkgProblemResolver with broken count: 0 227s Done 227s The following NEW packages will be installed: 227s cpp cpp-14 cpp-14-powerpc64le-linux-gnu cpp-powerpc64le-linux-gnu g++ g++-14 227s g++-14-powerpc64le-linux-gnu g++-powerpc64le-linux-gnu gcc gcc-14 227s gcc-14-powerpc64le-linux-gnu gcc-powerpc64le-linux-gnu iverilog libasan8 227s libcc1-0 libffi-dev libgcc-14-dev libgomp1 libisl23 libitm1 liblsan0 libmpc3 227s libncurses-dev libpkgconf3 libquadmath0 libreadline-dev libstdc++-14-dev 227s libtcl8.6 libtsan2 libubsan1 pkg-config pkgconf pkgconf-bin python3-click 227s tcl tcl-dev tcl8.6 tcl8.6-dev yosys yosys-abc yosys-dev zlib1g-dev 227s 0 upgraded, 42 newly installed, 0 to remove and 0 not upgraded. 227s Need to get 75.4 MB of archives. 227s After this operation, 273 MB of additional disk space will be used. 227s Get:1 http://ftpmaster.internal/ubuntu questing/main ppc64el libisl23 ppc64el 0.27-1 [882 kB] 230s Get:2 http://ftpmaster.internal/ubuntu questing/main ppc64el libmpc3 ppc64el 1.3.1-1build2 [62.1 kB] 230s Get:3 http://ftpmaster.internal/ubuntu questing/main ppc64el cpp-14-powerpc64le-linux-gnu ppc64el 14.2.0-19ubuntu2 [10.5 MB] 241s Get:4 http://ftpmaster.internal/ubuntu questing/main ppc64el cpp-14 ppc64el 14.2.0-19ubuntu2 [1036 B] 241s Get:5 http://ftpmaster.internal/ubuntu questing/main ppc64el cpp-powerpc64le-linux-gnu ppc64el 4:14.2.0-1ubuntu1 [5566 B] 241s Get:6 http://ftpmaster.internal/ubuntu questing/main ppc64el cpp ppc64el 4:14.2.0-1ubuntu1 [22.4 kB] 241s Get:7 http://ftpmaster.internal/ubuntu questing/main ppc64el libcc1-0 ppc64el 15-20250404-0ubuntu1 [48.6 kB] 241s Get:8 http://ftpmaster.internal/ubuntu questing/main ppc64el libgomp1 ppc64el 15-20250404-0ubuntu1 [168 kB] 241s Get:9 http://ftpmaster.internal/ubuntu questing/main ppc64el libitm1 ppc64el 15-20250404-0ubuntu1 [32.3 kB] 242s Get:10 http://ftpmaster.internal/ubuntu questing/main ppc64el libasan8 ppc64el 15-20250404-0ubuntu1 [3007 kB] 248s Get:11 http://ftpmaster.internal/ubuntu questing/main ppc64el liblsan0 ppc64el 15-20250404-0ubuntu1 [1374 kB] 250s Get:12 http://ftpmaster.internal/ubuntu questing/main ppc64el libtsan2 ppc64el 15-20250404-0ubuntu1 [2732 kB] 253s Get:13 http://ftpmaster.internal/ubuntu questing/main ppc64el libubsan1 ppc64el 15-20250404-0ubuntu1 [1232 kB] 254s Get:14 http://ftpmaster.internal/ubuntu questing/main ppc64el libquadmath0 ppc64el 15-20250404-0ubuntu1 [160 kB] 254s Get:15 http://ftpmaster.internal/ubuntu questing/main ppc64el libgcc-14-dev ppc64el 14.2.0-19ubuntu2 [1618 kB] 258s Get:16 http://ftpmaster.internal/ubuntu questing/main ppc64el gcc-14-powerpc64le-linux-gnu ppc64el 14.2.0-19ubuntu2 [20.6 MB] 280s Get:17 http://ftpmaster.internal/ubuntu questing/main ppc64el gcc-14 ppc64el 14.2.0-19ubuntu2 [540 kB] 281s Get:18 http://ftpmaster.internal/ubuntu questing/main ppc64el gcc-powerpc64le-linux-gnu ppc64el 4:14.2.0-1ubuntu1 [1226 B] 281s Get:19 http://ftpmaster.internal/ubuntu questing/main ppc64el gcc ppc64el 4:14.2.0-1ubuntu1 [5012 B] 281s Get:20 http://ftpmaster.internal/ubuntu questing/main ppc64el libstdc++-14-dev ppc64el 14.2.0-19ubuntu2 [2679 kB] 283s Get:21 http://ftpmaster.internal/ubuntu questing/main ppc64el g++-14-powerpc64le-linux-gnu ppc64el 14.2.0-19ubuntu2 [12.0 MB] 295s Get:22 http://ftpmaster.internal/ubuntu questing/main ppc64el g++-14 ppc64el 14.2.0-19ubuntu2 [23.0 kB] 295s Get:23 http://ftpmaster.internal/ubuntu questing/main ppc64el g++-powerpc64le-linux-gnu ppc64el 4:14.2.0-1ubuntu1 [966 B] 295s Get:24 http://ftpmaster.internal/ubuntu questing/main ppc64el g++ ppc64el 4:14.2.0-1ubuntu1 [1088 B] 295s Get:25 http://ftpmaster.internal/ubuntu questing/universe ppc64el iverilog ppc64el 12.0-2build2 [2459 kB] 299s Get:26 http://ftpmaster.internal/ubuntu questing/main ppc64el libncurses-dev ppc64el 6.5+20250216-2 [484 kB] 300s Get:27 http://ftpmaster.internal/ubuntu questing/main ppc64el libpkgconf3 ppc64el 1.8.1-4 [37.1 kB] 300s Get:28 http://ftpmaster.internal/ubuntu questing/main ppc64el libreadline-dev ppc64el 8.2-6 [230 kB] 300s Get:29 http://ftpmaster.internal/ubuntu questing/main ppc64el libtcl8.6 ppc64el 8.6.16+dfsg-1 [1201 kB] 302s Get:30 http://ftpmaster.internal/ubuntu questing/main ppc64el pkgconf-bin ppc64el 1.8.1-4 [22.5 kB] 302s Get:31 http://ftpmaster.internal/ubuntu questing/main ppc64el pkgconf ppc64el 1.8.1-4 [16.7 kB] 302s Get:32 http://ftpmaster.internal/ubuntu questing/main ppc64el pkg-config ppc64el 1.8.1-4 [7362 B] 302s Get:33 http://ftpmaster.internal/ubuntu questing/main ppc64el python3-click all 8.2.0+0.really.8.1.8-1 [80.0 kB] 302s Get:34 http://ftpmaster.internal/ubuntu questing/main ppc64el tcl8.6 ppc64el 8.6.16+dfsg-1 [14.8 kB] 302s Get:35 http://ftpmaster.internal/ubuntu questing/main ppc64el tcl ppc64el 8.6.16 [4084 B] 302s Get:36 http://ftpmaster.internal/ubuntu questing/main ppc64el zlib1g-dev ppc64el 1:1.3.dfsg+really1.3.1-1ubuntu1 [902 kB] 303s Get:37 http://ftpmaster.internal/ubuntu questing/main ppc64el tcl8.6-dev ppc64el 8.6.16+dfsg-1 [1229 kB] 304s Get:38 http://ftpmaster.internal/ubuntu questing/main ppc64el tcl-dev ppc64el 8.6.16 [5750 B] 304s Get:39 http://ftpmaster.internal/ubuntu questing/universe ppc64el yosys-abc ppc64el 0.33-5build2 [7747 kB] 310s Get:40 http://ftpmaster.internal/ubuntu questing/universe ppc64el yosys ppc64el 0.33-5build2 [3190 kB] 313s Get:41 http://ftpmaster.internal/ubuntu questing/main ppc64el libffi-dev ppc64el 3.4.7-1 [67.7 kB] 313s Get:42 http://ftpmaster.internal/ubuntu questing/universe ppc64el yosys-dev ppc64el 0.33-5build2 [88.4 kB] 313s Fetched 75.4 MB in 1min 25s (884 kB/s) 313s Selecting previously unselected package libisl23:ppc64el. 313s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 107209 files and directories currently installed.) 313s Preparing to unpack .../00-libisl23_0.27-1_ppc64el.deb ... 313s Unpacking libisl23:ppc64el (0.27-1) ... 313s Selecting previously unselected package libmpc3:ppc64el. 313s Preparing to unpack .../01-libmpc3_1.3.1-1build2_ppc64el.deb ... 313s Unpacking libmpc3:ppc64el (1.3.1-1build2) ... 313s Selecting previously unselected package cpp-14-powerpc64le-linux-gnu. 313s Preparing to unpack .../02-cpp-14-powerpc64le-linux-gnu_14.2.0-19ubuntu2_ppc64el.deb ... 313s Unpacking cpp-14-powerpc64le-linux-gnu (14.2.0-19ubuntu2) ... 313s Selecting previously unselected package cpp-14. 313s Preparing to unpack .../03-cpp-14_14.2.0-19ubuntu2_ppc64el.deb ... 313s Unpacking cpp-14 (14.2.0-19ubuntu2) ... 313s Selecting previously unselected package cpp-powerpc64le-linux-gnu. 313s Preparing to unpack .../04-cpp-powerpc64le-linux-gnu_4%3a14.2.0-1ubuntu1_ppc64el.deb ... 313s Unpacking cpp-powerpc64le-linux-gnu (4:14.2.0-1ubuntu1) ... 314s Selecting previously unselected package cpp. 314s Preparing to unpack .../05-cpp_4%3a14.2.0-1ubuntu1_ppc64el.deb ... 314s Unpacking cpp (4:14.2.0-1ubuntu1) ... 314s Selecting previously unselected package libcc1-0:ppc64el. 314s Preparing to unpack .../06-libcc1-0_15-20250404-0ubuntu1_ppc64el.deb ... 314s Unpacking libcc1-0:ppc64el (15-20250404-0ubuntu1) ... 314s Selecting previously unselected package libgomp1:ppc64el. 314s Preparing to unpack .../07-libgomp1_15-20250404-0ubuntu1_ppc64el.deb ... 314s Unpacking libgomp1:ppc64el (15-20250404-0ubuntu1) ... 314s Selecting previously unselected package libitm1:ppc64el. 314s Preparing to unpack .../08-libitm1_15-20250404-0ubuntu1_ppc64el.deb ... 314s Unpacking libitm1:ppc64el (15-20250404-0ubuntu1) ... 314s Selecting previously unselected package libasan8:ppc64el. 314s Preparing to unpack .../09-libasan8_15-20250404-0ubuntu1_ppc64el.deb ... 314s Unpacking libasan8:ppc64el (15-20250404-0ubuntu1) ... 314s Selecting previously unselected package liblsan0:ppc64el. 314s Preparing to unpack .../10-liblsan0_15-20250404-0ubuntu1_ppc64el.deb ... 314s Unpacking liblsan0:ppc64el (15-20250404-0ubuntu1) ... 314s Selecting previously unselected package libtsan2:ppc64el. 314s Preparing to unpack .../11-libtsan2_15-20250404-0ubuntu1_ppc64el.deb ... 314s Unpacking libtsan2:ppc64el (15-20250404-0ubuntu1) ... 314s Selecting previously unselected package libubsan1:ppc64el. 314s Preparing to unpack .../12-libubsan1_15-20250404-0ubuntu1_ppc64el.deb ... 314s Unpacking libubsan1:ppc64el (15-20250404-0ubuntu1) ... 314s Selecting previously unselected package libquadmath0:ppc64el. 314s Preparing to unpack .../13-libquadmath0_15-20250404-0ubuntu1_ppc64el.deb ... 314s Unpacking libquadmath0:ppc64el (15-20250404-0ubuntu1) ... 314s Selecting previously unselected package libgcc-14-dev:ppc64el. 314s Preparing to unpack .../14-libgcc-14-dev_14.2.0-19ubuntu2_ppc64el.deb ... 314s Unpacking libgcc-14-dev:ppc64el (14.2.0-19ubuntu2) ... 314s Selecting previously unselected package gcc-14-powerpc64le-linux-gnu. 314s Preparing to unpack .../15-gcc-14-powerpc64le-linux-gnu_14.2.0-19ubuntu2_ppc64el.deb ... 314s Unpacking gcc-14-powerpc64le-linux-gnu (14.2.0-19ubuntu2) ... 314s Selecting previously unselected package gcc-14. 314s Preparing to unpack .../16-gcc-14_14.2.0-19ubuntu2_ppc64el.deb ... 314s Unpacking gcc-14 (14.2.0-19ubuntu2) ... 314s Selecting previously unselected package gcc-powerpc64le-linux-gnu. 314s Preparing to unpack .../17-gcc-powerpc64le-linux-gnu_4%3a14.2.0-1ubuntu1_ppc64el.deb ... 314s Unpacking gcc-powerpc64le-linux-gnu (4:14.2.0-1ubuntu1) ... 314s Selecting previously unselected package gcc. 314s Preparing to unpack .../18-gcc_4%3a14.2.0-1ubuntu1_ppc64el.deb ... 314s Unpacking gcc (4:14.2.0-1ubuntu1) ... 314s Selecting previously unselected package libstdc++-14-dev:ppc64el. 314s Preparing to unpack .../19-libstdc++-14-dev_14.2.0-19ubuntu2_ppc64el.deb ... 314s Unpacking libstdc++-14-dev:ppc64el (14.2.0-19ubuntu2) ... 314s Selecting previously unselected package g++-14-powerpc64le-linux-gnu. 314s Preparing to unpack .../20-g++-14-powerpc64le-linux-gnu_14.2.0-19ubuntu2_ppc64el.deb ... 314s Unpacking g++-14-powerpc64le-linux-gnu (14.2.0-19ubuntu2) ... 315s Selecting previously unselected package g++-14. 315s Preparing to unpack .../21-g++-14_14.2.0-19ubuntu2_ppc64el.deb ... 315s Unpacking g++-14 (14.2.0-19ubuntu2) ... 315s Selecting previously unselected package g++-powerpc64le-linux-gnu. 315s Preparing to unpack .../22-g++-powerpc64le-linux-gnu_4%3a14.2.0-1ubuntu1_ppc64el.deb ... 315s Unpacking g++-powerpc64le-linux-gnu (4:14.2.0-1ubuntu1) ... 315s Selecting previously unselected package g++. 315s Preparing to unpack .../23-g++_4%3a14.2.0-1ubuntu1_ppc64el.deb ... 315s Unpacking g++ (4:14.2.0-1ubuntu1) ... 315s Selecting previously unselected package iverilog. 315s Preparing to unpack .../24-iverilog_12.0-2build2_ppc64el.deb ... 315s Unpacking iverilog (12.0-2build2) ... 315s Selecting previously unselected package libncurses-dev:ppc64el. 315s Preparing to unpack .../25-libncurses-dev_6.5+20250216-2_ppc64el.deb ... 315s Unpacking libncurses-dev:ppc64el (6.5+20250216-2) ... 315s Selecting previously unselected package libpkgconf3:ppc64el. 315s Preparing to unpack .../26-libpkgconf3_1.8.1-4_ppc64el.deb ... 315s Unpacking libpkgconf3:ppc64el (1.8.1-4) ... 315s Selecting previously unselected package libreadline-dev:ppc64el. 315s Preparing to unpack .../27-libreadline-dev_8.2-6_ppc64el.deb ... 315s Unpacking libreadline-dev:ppc64el (8.2-6) ... 315s Selecting previously unselected package libtcl8.6:ppc64el. 315s Preparing to unpack .../28-libtcl8.6_8.6.16+dfsg-1_ppc64el.deb ... 315s Unpacking libtcl8.6:ppc64el (8.6.16+dfsg-1) ... 315s Selecting previously unselected package pkgconf-bin. 315s Preparing to unpack .../29-pkgconf-bin_1.8.1-4_ppc64el.deb ... 315s Unpacking pkgconf-bin (1.8.1-4) ... 315s Selecting previously unselected package pkgconf:ppc64el. 315s Preparing to unpack .../30-pkgconf_1.8.1-4_ppc64el.deb ... 315s Unpacking pkgconf:ppc64el (1.8.1-4) ... 315s Selecting previously unselected package pkg-config:ppc64el. 315s Preparing to unpack .../31-pkg-config_1.8.1-4_ppc64el.deb ... 315s Unpacking pkg-config:ppc64el (1.8.1-4) ... 315s Selecting previously unselected package python3-click. 315s Preparing to unpack .../32-python3-click_8.2.0+0.really.8.1.8-1_all.deb ... 315s Unpacking python3-click (8.2.0+0.really.8.1.8-1) ... 315s Selecting previously unselected package tcl8.6. 315s Preparing to unpack .../33-tcl8.6_8.6.16+dfsg-1_ppc64el.deb ... 315s Unpacking tcl8.6 (8.6.16+dfsg-1) ... 315s Selecting previously unselected package tcl. 315s Preparing to unpack .../34-tcl_8.6.16_ppc64el.deb ... 315s Unpacking tcl (8.6.16) ... 315s Selecting previously unselected package zlib1g-dev:ppc64el. 315s Preparing to unpack .../35-zlib1g-dev_1%3a1.3.dfsg+really1.3.1-1ubuntu1_ppc64el.deb ... 315s Unpacking zlib1g-dev:ppc64el (1:1.3.dfsg+really1.3.1-1ubuntu1) ... 315s Selecting previously unselected package tcl8.6-dev:ppc64el. 315s Preparing to unpack .../36-tcl8.6-dev_8.6.16+dfsg-1_ppc64el.deb ... 315s Unpacking tcl8.6-dev:ppc64el (8.6.16+dfsg-1) ... 315s Selecting previously unselected package tcl-dev:ppc64el. 315s Preparing to unpack .../37-tcl-dev_8.6.16_ppc64el.deb ... 315s Unpacking tcl-dev:ppc64el (8.6.16) ... 315s Selecting previously unselected package yosys-abc. 315s Preparing to unpack .../38-yosys-abc_0.33-5build2_ppc64el.deb ... 315s Unpacking yosys-abc (0.33-5build2) ... 315s Selecting previously unselected package yosys. 315s Preparing to unpack .../39-yosys_0.33-5build2_ppc64el.deb ... 315s Unpacking yosys (0.33-5build2) ... 315s Selecting previously unselected package libffi-dev:ppc64el. 315s Preparing to unpack .../40-libffi-dev_3.4.7-1_ppc64el.deb ... 315s Unpacking libffi-dev:ppc64el (3.4.7-1) ... 315s Selecting previously unselected package yosys-dev. 315s Preparing to unpack .../41-yosys-dev_0.33-5build2_ppc64el.deb ... 315s Unpacking yosys-dev (0.33-5build2) ... 315s Setting up libncurses-dev:ppc64el (6.5+20250216-2) ... 315s Setting up yosys-abc (0.33-5build2) ... 315s Setting up libreadline-dev:ppc64el (8.2-6) ... 315s Setting up libgomp1:ppc64el (15-20250404-0ubuntu1) ... 315s Setting up python3-click (8.2.0+0.really.8.1.8-1) ... 316s Setting up libffi-dev:ppc64el (3.4.7-1) ... 316s Setting up iverilog (12.0-2build2) ... 316s Setting up libpkgconf3:ppc64el (1.8.1-4) ... 316s Setting up libquadmath0:ppc64el (15-20250404-0ubuntu1) ... 316s Setting up libmpc3:ppc64el (1.3.1-1build2) ... 316s Setting up libtcl8.6:ppc64el (8.6.16+dfsg-1) ... 316s Setting up pkgconf-bin (1.8.1-4) ... 316s Setting up libubsan1:ppc64el (15-20250404-0ubuntu1) ... 316s Setting up zlib1g-dev:ppc64el (1:1.3.dfsg+really1.3.1-1ubuntu1) ... 316s Setting up libasan8:ppc64el (15-20250404-0ubuntu1) ... 316s Setting up libtsan2:ppc64el (15-20250404-0ubuntu1) ... 316s Setting up libisl23:ppc64el (0.27-1) ... 316s Setting up libcc1-0:ppc64el (15-20250404-0ubuntu1) ... 316s Setting up liblsan0:ppc64el (15-20250404-0ubuntu1) ... 316s Setting up libitm1:ppc64el (15-20250404-0ubuntu1) ... 316s Setting up tcl8.6 (8.6.16+dfsg-1) ... 316s Setting up tcl8.6-dev:ppc64el (8.6.16+dfsg-1) ... 316s Setting up yosys (0.33-5build2) ... 316s Setting up pkgconf:ppc64el (1.8.1-4) ... 316s Setting up pkg-config:ppc64el (1.8.1-4) ... 316s Setting up cpp-14-powerpc64le-linux-gnu (14.2.0-19ubuntu2) ... 316s Setting up cpp-14 (14.2.0-19ubuntu2) ... 316s Setting up tcl (8.6.16) ... 316s Setting up libgcc-14-dev:ppc64el (14.2.0-19ubuntu2) ... 316s Setting up libstdc++-14-dev:ppc64el (14.2.0-19ubuntu2) ... 316s Setting up cpp-powerpc64le-linux-gnu (4:14.2.0-1ubuntu1) ... 316s Setting up gcc-14-powerpc64le-linux-gnu (14.2.0-19ubuntu2) ... 316s Setting up g++-14-powerpc64le-linux-gnu (14.2.0-19ubuntu2) ... 316s Setting up gcc-14 (14.2.0-19ubuntu2) ... 316s Setting up gcc-powerpc64le-linux-gnu (4:14.2.0-1ubuntu1) ... 316s Setting up tcl-dev:ppc64el (8.6.16) ... 316s Setting up cpp (4:14.2.0-1ubuntu1) ... 316s Setting up g++-14 (14.2.0-19ubuntu2) ... 316s Setting up yosys-dev (0.33-5build2) ... 316s Setting up g++-powerpc64le-linux-gnu (4:14.2.0-1ubuntu1) ... 316s Setting up gcc (4:14.2.0-1ubuntu1) ... 316s Setting up g++ (4:14.2.0-1ubuntu1) ... 316s update-alternatives: using /usr/bin/g++ to provide /usr/bin/c++ (c++) in auto mode 316s Processing triggers for libc-bin (2.41-6ubuntu1) ... 316s Processing triggers for man-db (2.13.1-1) ... 317s Processing triggers for install-info (7.1.1-1) ... 322s autopkgtest [11:08:16]: test yosys-testsuite: [----------------------- 322s + [ 1 -ge 1 ] 322s + testdir=. 322s + shift 322s + mkdir -p . 322s + cd . 322s + ln -sf /usr/bin/yosys . 322s + ln -sf /usr/bin/yosys-abc . 322s + ln -sf /usr/bin/yosys-config . 322s + sed -i s/^test:.*/test: $(EXTRA_TARGETS)/ Makefile 322s + make test CONFIG=gcc ABCPULL=0 322s mkdir -p share/include/kernel/ 322s cp "./"/kernel/yosys.h share/include/kernel/yosys.h 322s mkdir -p share/include/kernel/ 322s cp "./"/kernel/hashlib.h share/include/kernel/hashlib.h 322s mkdir -p share/include/kernel/ 322s cp "./"/kernel/log.h share/include/kernel/log.h 322s mkdir -p share/include/kernel/ 322s cp "./"/kernel/rtlil.h share/include/kernel/rtlil.h 322s mkdir -p share/include/kernel/ 322s cp "./"/kernel/binding.h share/include/kernel/binding.h 322s mkdir -p share/include/kernel/ 322s cp "./"/kernel/register.h share/include/kernel/register.h 322s mkdir -p share/include/kernel/ 322s cp "./"/kernel/cellaigs.h share/include/kernel/cellaigs.h 322s mkdir -p share/include/kernel/ 322s cp "./"/kernel/celltypes.h share/include/kernel/celltypes.h 322s mkdir -p share/include/kernel/ 322s cp "./"/kernel/celledges.h share/include/kernel/celledges.h 322s mkdir -p share/include/kernel/ 322s cp "./"/kernel/consteval.h share/include/kernel/consteval.h 322s mkdir -p share/include/kernel/ 322s cp "./"/kernel/constids.inc share/include/kernel/constids.inc 322s mkdir -p share/include/kernel/ 322s cp "./"/kernel/sigtools.h share/include/kernel/sigtools.h 322s mkdir -p share/include/kernel/ 322s cp "./"/kernel/modtools.h share/include/kernel/modtools.h 322s mkdir -p share/include/kernel/ 322s cp "./"/kernel/macc.h share/include/kernel/macc.h 322s mkdir -p share/include/kernel/ 322s cp "./"/kernel/utils.h share/include/kernel/utils.h 322s mkdir -p share/include/kernel/ 322s cp "./"/kernel/satgen.h share/include/kernel/satgen.h 322s mkdir -p share/include/kernel/ 322s cp "./"/kernel/qcsat.h share/include/kernel/qcsat.h 322s mkdir -p share/include/kernel/ 322s cp "./"/kernel/ff.h share/include/kernel/ff.h 322s mkdir -p share/include/kernel/ 322s cp "./"/kernel/ffinit.h share/include/kernel/ffinit.h 322s mkdir -p share/include/kernel/ 322s cp "./"/kernel/fstdata.h share/include/kernel/fstdata.h 322s mkdir -p share/include/kernel/ 322s cp "./"/kernel/mem.h share/include/kernel/mem.h 322s mkdir -p share/include/kernel/ 322s cp "./"/kernel/yw.h share/include/kernel/yw.h 322s mkdir -p share/include/kernel/ 322s cp "./"/kernel/json.h share/include/kernel/json.h 322s mkdir -p share/include/libs/ezsat/ 322s cp "./"/libs/ezsat/ezsat.h share/include/libs/ezsat/ezsat.h 322s mkdir -p share/include/libs/ezsat/ 322s cp "./"/libs/ezsat/ezminisat.h share/include/libs/ezsat/ezminisat.h 322s mkdir -p share/include/libs/fst/ 322s cp "./"/libs/fst/fstapi.h share/include/libs/fst/fstapi.h 322s mkdir -p share/include/libs/sha1/ 322s cp "./"/libs/sha1/sha1.h share/include/libs/sha1/sha1.h 322s mkdir -p share/include/libs/json11/ 322s cp "./"/libs/json11/json11.hpp share/include/libs/json11/json11.hpp 322s mkdir -p share/include/passes/fsm/ 322s cp "./"/passes/fsm/fsmdata.h share/include/passes/fsm/fsmdata.h 322s mkdir -p share/include/frontends/ast/ 322s cp "./"/frontends/ast/ast.h share/include/frontends/ast/ast.h 322s mkdir -p share/include/frontends/ast/ 322s cp "./"/frontends/ast/ast_binding.h share/include/frontends/ast/ast_binding.h 322s mkdir -p share/include/frontends/blif/ 322s cp "./"/frontends/blif/blifparse.h share/include/frontends/blif/blifparse.h 322s mkdir -p share/include/backends/rtlil/ 322s cp "./"/backends/rtlil/rtlil_backend.h share/include/backends/rtlil/rtlil_backend.h 322s mkdir -p share/include/backends/cxxrtl/ 322s cp "./"/backends/cxxrtl/cxxrtl.h share/include/backends/cxxrtl/cxxrtl.h 322s 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"./"/techlibs/efinix/brams_map.v share/efinix/brams_map.v 323s mkdir -p share/efinix 323s cp "./"/techlibs/efinix/gbuf_map.v share/efinix/gbuf_map.v 323s mkdir -p share/efinix 323s cp "./"/techlibs/efinix/brams.txt share/efinix/brams.txt 323s mkdir -p share/fabulous 323s cp "./"/techlibs/fabulous/cells_map.v share/fabulous/cells_map.v 323s mkdir -p share/fabulous 323s cp "./"/techlibs/fabulous/prims.v share/fabulous/prims.v 323s mkdir -p share/fabulous 323s cp "./"/techlibs/fabulous/latches_map.v share/fabulous/latches_map.v 323s mkdir -p share/fabulous 323s cp "./"/techlibs/fabulous/ff_map.v share/fabulous/ff_map.v 323s mkdir -p share/fabulous 323s cp "./"/techlibs/fabulous/ram_regfile.txt share/fabulous/ram_regfile.txt 323s mkdir -p share/fabulous 323s cp "./"/techlibs/fabulous/regfile_map.v share/fabulous/regfile_map.v 323s mkdir -p share/fabulous 323s cp "./"/techlibs/fabulous/io_map.v share/fabulous/io_map.v 323s mkdir -p share/fabulous 323s cp "./"/techlibs/fabulous/arith_map.v share/fabulous/arith_map.v 323s mkdir -p share/gatemate 323s cp "./"/techlibs/gatemate/reg_map.v share/gatemate/reg_map.v 323s mkdir -p share/gatemate 323s cp "./"/techlibs/gatemate/mux_map.v share/gatemate/mux_map.v 323s mkdir -p share/gatemate 323s cp "./"/techlibs/gatemate/lut_map.v share/gatemate/lut_map.v 323s mkdir -p share/gatemate 323s cp "./"/techlibs/gatemate/mul_map.v share/gatemate/mul_map.v 323s mkdir -p share/gatemate 323s cp "./"/techlibs/gatemate/arith_map.v share/gatemate/arith_map.v 323s mkdir -p share/gatemate 323s cp "./"/techlibs/gatemate/cells_sim.v share/gatemate/cells_sim.v 323s mkdir -p share/gatemate 323s cp "./"/techlibs/gatemate/cells_bb.v share/gatemate/cells_bb.v 323s mkdir -p share/gatemate 323s cp "./"/techlibs/gatemate/brams_map.v share/gatemate/brams_map.v 323s mkdir -p share/gatemate 323s cp "./"/techlibs/gatemate/brams.txt share/gatemate/brams.txt 323s mkdir -p share/gatemate 323s cp "./"/techlibs/gatemate/brams_init_20.vh share/gatemate/brams_init_20.vh 323s mkdir -p share/gatemate 323s cp "./"/techlibs/gatemate/brams_init_40.vh share/gatemate/brams_init_40.vh 323s mkdir -p share/gatemate 323s cp "./"/techlibs/gatemate/inv_map.v share/gatemate/inv_map.v 323s mkdir -p techlibs/gatemate 323s python3 techlibs/gatemate/make_lut_tree_lib.py 323s touch techlibs/gatemate/lut_tree_lib.mk 323s mkdir -p share/gatemate 323s cp techlibs/gatemate/lut_tree_cells.genlib share/gatemate/lut_tree_cells.genlib 323s mkdir -p share/gatemate 323s cp techlibs/gatemate/lut_tree_map.v share/gatemate/lut_tree_map.v 323s mkdir -p share/gowin 323s cp "./"/techlibs/gowin/cells_map.v share/gowin/cells_map.v 323s mkdir -p share/gowin 323s cp "./"/techlibs/gowin/cells_sim.v share/gowin/cells_sim.v 323s mkdir -p share/gowin 323s cp "./"/techlibs/gowin/cells_xtra.v share/gowin/cells_xtra.v 323s mkdir -p share/gowin 323s cp "./"/techlibs/gowin/arith_map.v share/gowin/arith_map.v 323s mkdir -p share/gowin 323s cp "./"/techlibs/gowin/brams_map.v share/gowin/brams_map.v 323s mkdir -p share/gowin 323s cp "./"/techlibs/gowin/brams.txt share/gowin/brams.txt 323s mkdir -p share/gowin 323s cp "./"/techlibs/gowin/lutrams_map.v share/gowin/lutrams_map.v 323s mkdir -p share/gowin 323s cp "./"/techlibs/gowin/lutrams.txt share/gowin/lutrams.txt 323s mkdir -p share/greenpak4 323s cp "./"/techlibs/greenpak4/cells_blackbox.v share/greenpak4/cells_blackbox.v 323s mkdir -p share/greenpak4 323s cp "./"/techlibs/greenpak4/cells_latch.v share/greenpak4/cells_latch.v 323s mkdir -p share/greenpak4 323s cp "./"/techlibs/greenpak4/cells_map.v share/greenpak4/cells_map.v 323s mkdir -p share/greenpak4 323s cp "./"/techlibs/greenpak4/cells_sim.v share/greenpak4/cells_sim.v 323s mkdir -p share/greenpak4 323s cp "./"/techlibs/greenpak4/cells_sim_ams.v share/greenpak4/cells_sim_ams.v 323s mkdir -p share/greenpak4 323s cp "./"/techlibs/greenpak4/cells_sim_digital.v share/greenpak4/cells_sim_digital.v 323s mkdir -p share/greenpak4 323s cp "./"/techlibs/greenpak4/cells_sim_wip.v share/greenpak4/cells_sim_wip.v 323s mkdir -p share/greenpak4 323s cp "./"/techlibs/greenpak4/gp_dff.lib share/greenpak4/gp_dff.lib 323s mkdir -p share/ice40 323s cp "./"/techlibs/ice40/arith_map.v share/ice40/arith_map.v 323s mkdir -p share/ice40 323s cp "./"/techlibs/ice40/cells_map.v share/ice40/cells_map.v 323s mkdir -p share/ice40 323s cp "./"/techlibs/ice40/ff_map.v share/ice40/ff_map.v 323s mkdir -p share/ice40 323s cp "./"/techlibs/ice40/cells_sim.v share/ice40/cells_sim.v 323s mkdir -p share/ice40 323s cp "./"/techlibs/ice40/latches_map.v share/ice40/latches_map.v 323s mkdir -p share/ice40 323s cp "./"/techlibs/ice40/brams.txt share/ice40/brams.txt 323s mkdir -p share/ice40 323s cp "./"/techlibs/ice40/brams_map.v share/ice40/brams_map.v 323s mkdir -p share/ice40 323s cp "./"/techlibs/ice40/spram.txt share/ice40/spram.txt 323s mkdir -p share/ice40 323s cp "./"/techlibs/ice40/spram_map.v share/ice40/spram_map.v 323s mkdir -p share/ice40 323s cp "./"/techlibs/ice40/dsp_map.v share/ice40/dsp_map.v 323s mkdir -p share/ice40 323s cp "./"/techlibs/ice40/abc9_model.v share/ice40/abc9_model.v 323s mkdir -p share/intel/common 323s cp "./"/techlibs/intel/common/m9k_bb.v share/intel/common/m9k_bb.v 323s mkdir -p share/intel/common 323s cp "./"/techlibs/intel/common/altpll_bb.v share/intel/common/altpll_bb.v 323s mkdir -p share/intel/common 323s cp "./"/techlibs/intel/common/brams_m9k.txt share/intel/common/brams_m9k.txt 323s mkdir -p share/intel/common 323s cp "./"/techlibs/intel/common/brams_map_m9k.v share/intel/common/brams_map_m9k.v 323s mkdir -p share/intel/common 323s cp "./"/techlibs/intel/common/ff_map.v share/intel/common/ff_map.v 323s mkdir -p share/intel/max10 323s cp "./"/techlibs/intel/max10/cells_sim.v share/intel/max10/cells_sim.v 323s mkdir -p share/intel/cyclone10lp 323s cp "./"/techlibs/intel/cyclone10lp/cells_sim.v share/intel/cyclone10lp/cells_sim.v 323s mkdir -p share/intel/cycloneiv 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"./"/techlibs/lattice/cells_sim_xo2.v share/lattice/cells_sim_xo2.v 323s mkdir -p share/lattice 323s cp "./"/techlibs/lattice/cells_sim_xo3.v share/lattice/cells_sim_xo3.v 323s mkdir -p share/lattice 323s cp "./"/techlibs/lattice/cells_sim_xo3d.v share/lattice/cells_sim_xo3d.v 323s mkdir -p share/lattice 323s cp "./"/techlibs/lattice/cells_bb_ecp5.v share/lattice/cells_bb_ecp5.v 323s mkdir -p share/lattice 323s cp "./"/techlibs/lattice/cells_bb_xo2.v share/lattice/cells_bb_xo2.v 323s mkdir -p share/lattice 323s cp "./"/techlibs/lattice/cells_bb_xo3.v share/lattice/cells_bb_xo3.v 323s mkdir -p share/lattice 323s cp "./"/techlibs/lattice/cells_bb_xo3d.v share/lattice/cells_bb_xo3d.v 323s mkdir -p share/lattice 323s cp "./"/techlibs/lattice/lutrams_map.v share/lattice/lutrams_map.v 323s mkdir -p share/lattice 323s cp "./"/techlibs/lattice/lutrams.txt share/lattice/lutrams.txt 323s mkdir -p share/lattice 323s cp "./"/techlibs/lattice/brams_map_16kd.v share/lattice/brams_map_16kd.v 323s mkdir -p share/lattice 323s cp "./"/techlibs/lattice/brams_16kd.txt share/lattice/brams_16kd.txt 323s mkdir -p share/lattice 323s cp "./"/techlibs/lattice/brams_map_8kc.v share/lattice/brams_map_8kc.v 323s mkdir -p share/lattice 323s cp "./"/techlibs/lattice/brams_8kc.txt share/lattice/brams_8kc.txt 323s mkdir -p share/lattice 323s cp "./"/techlibs/lattice/arith_map_ccu2c.v share/lattice/arith_map_ccu2c.v 323s mkdir -p share/lattice 323s cp "./"/techlibs/lattice/arith_map_ccu2d.v share/lattice/arith_map_ccu2d.v 323s mkdir -p share/lattice 323s cp "./"/techlibs/lattice/latches_map.v share/lattice/latches_map.v 323s mkdir -p share/lattice 323s cp "./"/techlibs/lattice/dsp_map_18x18.v share/lattice/dsp_map_18x18.v 323s mkdir -p share/nexus 323s cp "./"/techlibs/nexus/cells_map.v share/nexus/cells_map.v 323s mkdir -p share/nexus 323s cp "./"/techlibs/nexus/cells_sim.v share/nexus/cells_sim.v 323s mkdir -p share/nexus 323s cp "./"/techlibs/nexus/parse_init.vh share/nexus/parse_init.vh 323s mkdir -p share/nexus 323s cp "./"/techlibs/nexus/cells_xtra.v share/nexus/cells_xtra.v 323s mkdir -p share/nexus 323s cp "./"/techlibs/nexus/lutrams_map.v share/nexus/lutrams_map.v 323s mkdir -p share/nexus 323s cp "./"/techlibs/nexus/lutrams.txt share/nexus/lutrams.txt 323s mkdir -p share/nexus 323s cp "./"/techlibs/nexus/brams_map.v share/nexus/brams_map.v 323s mkdir -p share/nexus 323s cp "./"/techlibs/nexus/brams.txt share/nexus/brams.txt 323s mkdir -p share/nexus 323s cp "./"/techlibs/nexus/lrams_map.v share/nexus/lrams_map.v 323s mkdir -p share/nexus 323s cp "./"/techlibs/nexus/lrams.txt share/nexus/lrams.txt 323s mkdir -p share/nexus 323s cp "./"/techlibs/nexus/arith_map.v share/nexus/arith_map.v 323s mkdir -p share/nexus 323s cp "./"/techlibs/nexus/latches_map.v share/nexus/latches_map.v 323s mkdir -p share/nexus 323s cp "./"/techlibs/nexus/dsp_map.v share/nexus/dsp_map.v 323s mkdir -p share/quicklogic 323s cp "./"/techlibs/quicklogic/pp3_ffs_map.v share/quicklogic/pp3_ffs_map.v 323s mkdir -p share/quicklogic 323s cp "./"/techlibs/quicklogic/pp3_lut_map.v share/quicklogic/pp3_lut_map.v 323s mkdir -p share/quicklogic 323s cp "./"/techlibs/quicklogic/pp3_latches_map.v share/quicklogic/pp3_latches_map.v 323s mkdir -p share/quicklogic 323s cp "./"/techlibs/quicklogic/pp3_cells_map.v share/quicklogic/pp3_cells_map.v 323s mkdir -p share/quicklogic 323s cp "./"/techlibs/quicklogic/cells_sim.v share/quicklogic/cells_sim.v 323s mkdir -p share/quicklogic 323s cp "./"/techlibs/quicklogic/lut_sim.v share/quicklogic/lut_sim.v 323s mkdir -p share/quicklogic 323s cp "./"/techlibs/quicklogic/pp3_cells_sim.v share/quicklogic/pp3_cells_sim.v 323s mkdir -p share/quicklogic 323s cp "./"/techlibs/quicklogic/abc9_model.v share/quicklogic/abc9_model.v 323s mkdir -p share/quicklogic 323s cp "./"/techlibs/quicklogic/abc9_map.v share/quicklogic/abc9_map.v 323s mkdir -p share/quicklogic 323s cp "./"/techlibs/quicklogic/abc9_unmap.v share/quicklogic/abc9_unmap.v 323s mkdir -p share/sf2 323s cp "./"/techlibs/sf2/arith_map.v share/sf2/arith_map.v 323s mkdir -p share/sf2 323s cp "./"/techlibs/sf2/cells_map.v share/sf2/cells_map.v 323s mkdir -p share/sf2 323s cp "./"/techlibs/sf2/cells_sim.v share/sf2/cells_sim.v 323s mkdir -p share/xilinx 323s cp "./"/techlibs/xilinx/cells_map.v share/xilinx/cells_map.v 323s mkdir -p share/xilinx 323s cp "./"/techlibs/xilinx/cells_sim.v share/xilinx/cells_sim.v 323s mkdir -p share/xilinx 323s cp "./"/techlibs/xilinx/cells_xtra.v share/xilinx/cells_xtra.v 323s mkdir -p share/xilinx 323s cp "./"/techlibs/xilinx/lutrams_xcv.txt share/xilinx/lutrams_xcv.txt 323s mkdir -p share/xilinx 323s cp "./"/techlibs/xilinx/lutrams_xcv_map.v share/xilinx/lutrams_xcv_map.v 323s mkdir -p share/xilinx 323s cp "./"/techlibs/xilinx/lutrams_xc5v.txt share/xilinx/lutrams_xc5v.txt 323s mkdir -p share/xilinx 323s cp "./"/techlibs/xilinx/lutrams_xcu.txt share/xilinx/lutrams_xcu.txt 323s mkdir -p share/xilinx 323s cp "./"/techlibs/xilinx/lutrams_xc5v_map.v share/xilinx/lutrams_xc5v_map.v 323s mkdir -p share/xilinx 323s cp "./"/techlibs/xilinx/brams_xcv.txt share/xilinx/brams_xcv.txt 323s mkdir -p share/xilinx 323s cp "./"/techlibs/xilinx/brams_xcv_map.v share/xilinx/brams_xcv_map.v 323s mkdir -p share/xilinx 323s cp "./"/techlibs/xilinx/brams_defs.vh share/xilinx/brams_defs.vh 323s mkdir -p share/xilinx 323s cp "./"/techlibs/xilinx/brams_xc2v.txt share/xilinx/brams_xc2v.txt 323s mkdir -p share/xilinx 323s cp "./"/techlibs/xilinx/brams_xc2v_map.v share/xilinx/brams_xc2v_map.v 323s mkdir -p share/xilinx 323s cp "./"/techlibs/xilinx/brams_xc3sda.txt share/xilinx/brams_xc3sda.txt 323s mkdir -p share/xilinx 323s cp "./"/techlibs/xilinx/brams_xc3sda_map.v share/xilinx/brams_xc3sda_map.v 323s mkdir -p share/xilinx 323s cp "./"/techlibs/xilinx/brams_xc4v.txt share/xilinx/brams_xc4v.txt 323s mkdir -p share/xilinx 323s cp "./"/techlibs/xilinx/brams_xc4v_map.v share/xilinx/brams_xc4v_map.v 323s mkdir -p share/xilinx 323s cp "./"/techlibs/xilinx/brams_xc5v_map.v share/xilinx/brams_xc5v_map.v 323s mkdir -p share/xilinx 323s cp "./"/techlibs/xilinx/brams_xc6v_map.v share/xilinx/brams_xc6v_map.v 323s mkdir -p share/xilinx 323s cp "./"/techlibs/xilinx/brams_xcu_map.v share/xilinx/brams_xcu_map.v 323s mkdir -p share/xilinx 323s cp "./"/techlibs/xilinx/urams.txt share/xilinx/urams.txt 323s mkdir -p share/xilinx 323s cp "./"/techlibs/xilinx/urams_map.v share/xilinx/urams_map.v 323s mkdir -p share/xilinx 323s cp "./"/techlibs/xilinx/arith_map.v share/xilinx/arith_map.v 323s mkdir -p share/xilinx 323s cp "./"/techlibs/xilinx/ff_map.v share/xilinx/ff_map.v 323s mkdir -p share/xilinx 323s cp "./"/techlibs/xilinx/lut_map.v share/xilinx/lut_map.v 323s mkdir -p share/xilinx 323s cp "./"/techlibs/xilinx/mux_map.v share/xilinx/mux_map.v 323s mkdir -p share/xilinx 323s cp "./"/techlibs/xilinx/xc3s_mult_map.v share/xilinx/xc3s_mult_map.v 323s mkdir -p share/xilinx 323s cp "./"/techlibs/xilinx/xc3sda_dsp_map.v share/xilinx/xc3sda_dsp_map.v 323s mkdir -p share/xilinx 323s cp "./"/techlibs/xilinx/xc6s_dsp_map.v share/xilinx/xc6s_dsp_map.v 323s mkdir -p share/xilinx 323s cp "./"/techlibs/xilinx/xc4v_dsp_map.v share/xilinx/xc4v_dsp_map.v 323s mkdir -p share/xilinx 323s cp "./"/techlibs/xilinx/xc5v_dsp_map.v share/xilinx/xc5v_dsp_map.v 323s mkdir -p share/xilinx 323s cp "./"/techlibs/xilinx/xc7_dsp_map.v share/xilinx/xc7_dsp_map.v 323s mkdir -p share/xilinx 323s cp "./"/techlibs/xilinx/xcu_dsp_map.v share/xilinx/xcu_dsp_map.v 323s mkdir -p share/xilinx 323s cp "./"/techlibs/xilinx/abc9_model.v share/xilinx/abc9_model.v 323s cd tests/simple && bash run-test.sh "" 323s make[1]: Entering directory '/tmp/autopkgtest.qrrc6z/build.ei9/src/tests/simple' 323s + gcc -Wall -o /tmp/autopkgtest.qrrc6z/build.ei9/src/tests/tools/cmp_tbdata /tmp/autopkgtest.qrrc6z/build.ei9/src/tests/tools/cmp_tbdata.c 324s Test: arrays02 -> ok 327s Test: asgn_binop -> ok 327s Test: case_expr_extend -> ok 327s Test: case_expr_query -> ok 328s Test: defvalue -> ok 328s Test: implicit_ports -> ok 329s Test: lesser_size_cast -> ok 329s Test: local_loop_var -> ok 329s Test: macro_arg_spaces -> ok 330s Test: matching_end_labels -> ok 330s Test: memwr_port_connection -> ok 330s Test: unnamed_block_decl -> ok 331s Test: aes_kexp128 -> ok 331s Test: always01 -> ok 331s Test: always02 -> ok 332s Test: always03 -> ok 333s Test: arraycells -> ok 333s Test: arrays01 -> ok 333s Test: attrib01_module -> ok 334s Test: attrib02_port_decl -> ok 334s Test: attrib03_parameter -> ok 335s Test: attrib04_net_var -> ok 335s Test: attrib06_operator_suffix -> ok 336s Test: attrib08_mod_inst -> ok 336s Test: attrib09_case -> ok 337s Test: carryadd -> ok 337s Test: case_expr_const -> ok 337s Test: case_expr_non_const -> ok 348s Test: case_large -> ok 348s Test: const_branch_finish -> ok 348s Test: const_fold_func -> ok 349s Test: const_func_shadow -> ok 352s Test: constmuldivmod -> ok 353s Test: constpower -> ok 354s Test: dff_different_styles -> ok 355s Test: dff_init -> ok 358s Test: dynslice -> ok 358s Test: fiedler-cooley -> ok 359s Test: forgen01 -> ok 359s Test: forgen02 -> ok 360s Test: forloops -> ok 361s Test: fsm -> ok 361s Test: func_block -> ok 362s Test: func_recurse -> ok 362s Test: func_width_scope -> ok 363s Test: genblk_collide -> ok 363s Test: genblk_dive -> ok 363s Test: genblk_order -> ok 363s Test: genblk_port_shadow -> ok 367s Test: generate -> ok 367s Test: graphtest -> ok 367s Test: hierarchy -> ok 368s Test: hierdefparam -> ok 369s Test: i2c_master_tests -> ok 369s Test: ifdef_1 -> ok 369s Test: ifdef_2 -> ok 370s Test: localparam_attr -> ok 370s Test: loop_prefix_case -> ok 370s Test: loop_var_shadow -> ok 371s Test: loops -> ok 371s Test: macro_arg_surrounding_spaces -> ok 372s Test: macros -> ok 374s Test: mem2reg -> ok 374s Test: mem2reg_bounds_tern -> ok 375s Test: mem_arst -> ok 384s Test: memory -> ok 385s Test: module_scope -> ok 385s Test: module_scope_case -> ok 385s Test: module_scope_func -> ok 386s Test: multiplier -> ok 387s Test: muxtree -> ok 387s Test: named_genblk -> ok 388s Test: nested_genblk_resolve -> ok 388s Test: omsp_dbg_uart -> ok 394s Test: operators -> ok 395s Test: param_attr -> ok 395s Test: paramods -> ok 401s Test: partsel -> ok 402s Test: process -> ok 403s Test: realexpr -> ok 404s Test: repwhile -> ok 404s Test: retime -> ok 410s Test: rotate -> ok 411s Test: scopes -> ok 411s Test: signed_full_slice -> ok 412s Test: signedexpr -> ok 414s Test: sincos -> ok 415s Test: specify -> ok 415s Test: string_format -> ok 416s Test: subbytes -> ok 417s Test: task_func -> ok 417s Test: undef_eqx_nex -> ok 417s Test: usb_phy_tests -> ok 418s Test: values -> ok 419s Test: verilog_primitives -> ok 420s Test: vloghammer -> ok 421s Test: wandwor -> ok 422s Test: wreduce -> ok 422s make[1]: Leaving directory '/tmp/autopkgtest.qrrc6z/build.ei9/src/tests/simple' 422s cd tests/simple_abc9 && bash run-test.sh "" 422s ls: cannot access '*.sv': No such file or directory 422s make[1]: Entering directory '/tmp/autopkgtest.qrrc6z/build.ei9/src/tests/simple_abc9' 425s Test: abc9 -> ok 425s Test: aes_kexp128 -> ok 425s Test: always01 -> ok 426s Test: always02 -> ok 426s Test: always03 -> ok 426s Test: arraycells -> ok 426s Test: arrays01 -> ok 427s Test: attrib01_module -> ok 427s Test: attrib02_port_decl -> ok 427s Test: attrib03_parameter -> ok 428s Test: attrib04_net_var -> ok 428s Test: attrib06_operator_suffix -> ok 428s Test: attrib08_mod_inst -> ok 429s Test: attrib09_case -> ok 429s Test: carryadd -> ok 429s Test: case_expr_const -> ok 429s Test: case_expr_non_const -> ok 447s Test: case_large -> ok 447s Test: const_branch_finish -> ok 447s Test: const_fold_func -> ok 448s Test: const_func_shadow -> ok 451s Test: constmuldivmod -> ok 451s Test: constpower -> ok 452s Test: dff_different_styles -> ok 452s Test: dff_init -> ok 461s Test: dynslice -> ok 461s Test: fiedler-cooley -> ok 462s Test: forgen01 -> ok 462s Test: forgen02 -> ok 463s Test: forloops -> ok 463s Test: fsm -> ok 463s Test: func_block -> ok 464s Test: func_recurse -> ok 464s Test: func_width_scope -> ok 464s Test: genblk_collide -> ok 465s Test: genblk_dive -> ok 465s Test: genblk_order -> ok 465s Test: genblk_port_shadow -> ok 468s Test: generate -> ok 468s Test: graphtest -> ok 468s Test: hierarchy -> ok 469s Test: hierdefparam -> ok 469s Test: i2c_master_tests -> ok 469s Test: ifdef_1 -> ok 470s Test: ifdef_2 -> ok 470s Test: localparam_attr -> ok 470s Test: loop_prefix_case -> ok 470s Test: loop_var_shadow -> ok 471s Test: loops -> ok 471s Test: macro_arg_surrounding_spaces -> ok 471s Test: macros -> ok 472s Test: mem2reg -> ok 473s Test: mem2reg_bounds_tern -> ok 473s Test: mem_arst -> ok 477s Test: memory -> ok 478s Test: module_scope -> ok 478s Test: module_scope_case -> ok 478s Test: module_scope_func -> ok 479s Test: multiplier -> ok 480s Test: muxtree -> ok 480s Test: named_genblk -> ok 480s Test: nested_genblk_resolve -> ok 480s Test: omsp_dbg_uart -> ok 487s Test: operators -> ok 487s Test: param_attr -> ok 488s Test: paramods -> ok 494s Test: partsel -> ok 495s Test: process -> ok 495s Test: realexpr -> ok 496s Test: repwhile -> ok 496s Test: retime -> ok 498s Test: rotate -> ok 498s Test: scopes -> ok 502s Test: signed_full_slice -> ok 502s Test: signedexpr -> ok 502s Test: sincos -> ok 502s Test: string_format -> ok 502s Test: subbytes -> ok 503s Test: task_func -> ok 503s Test: undef_eqx_nex -> ok 504s Test: usb_phy_tests -> ok 504s Test: values -> ok 504s Test: verilog_primitives -> ok 505s Test: vloghammer -> ok 505s Test: wandwor -> ok 507s Test: wreduce -> ok 507s Test: arrays02 -> ok 509s Test: asgn_binop -> ok 509s Test: case_expr_extend -> ok 509s Test: case_expr_query -> ok 510s Test: defvalue -> ok 510s Test: implicit_ports -> ok 510s Test: lesser_size_cast -> ok 511s Test: local_loop_var -> ok 512s Test: macro_arg_spaces -> ok 512s Test: matching_end_labels -> ok 512s Test: memwr_port_connection -> ok 512s Test: unnamed_block_decl -> ok 512s make[1]: Leaving directory '/tmp/autopkgtest.qrrc6z/build.ei9/src/tests/simple_abc9' 512s cd tests/hana && bash run-test.sh "" 512s make[1]: Entering directory '/tmp/autopkgtest.qrrc6z/build.ei9/src/tests/hana' 516s Test: test_intermout -> ok 517s Test: test_parse2synthtrans -> ok 518s Test: test_parser -> ok 519s Test: test_simulation_always -> ok 520s Test: test_simulation_and -> ok 520s Test: test_simulation_buffer -> ok 521s Test: test_simulation_decoder -> ok 522s Test: test_simulation_inc -> ok 524s Test: test_simulation_mux -> ok 524s Test: test_simulation_nand -> ok 525s Test: test_simulation_nor -> ok 525s Test: test_simulation_or -> ok 526s Test: test_simulation_seq -> ok 529s Test: test_simulation_shifter -> ok 530s Test: test_simulation_sop -> ok 532s Test: test_simulation_techmap -> ok 534s Test: test_simulation_techmap_tech -> ok 534s Test: test_simulation_vlib -> ok 535s Test: test_simulation_xnor -> ok 535s Test: test_simulation_xor -> ok 535s make[1]: Leaving directory '/tmp/autopkgtest.qrrc6z/build.ei9/src/tests/hana' 535s cd tests/asicworld && bash run-test.sh "" 535s make[1]: Entering directory '/tmp/autopkgtest.qrrc6z/build.ei9/src/tests/asicworld' 536s Test: code_hdl_models_GrayCounter -> ok 536s Test: code_hdl_models_arbiter -> ok 547s Test: code_hdl_models_cam -> ok 547s Test: code_hdl_models_clk_div -> ok 548s Test: code_hdl_models_clk_div_45 -> ok 548s Test: code_hdl_models_d_ff_gates -> ok 549s Test: code_hdl_models_d_latch_gates -> ok 549s Test: code_hdl_models_decoder_2to4_gates -> ok 549s Test: code_hdl_models_decoder_using_assign -> ok 550s Test: code_hdl_models_decoder_using_case -> ok 550s Test: code_hdl_models_dff_async_reset -> ok 550s Test: code_hdl_models_dff_sync_reset -> ok 551s Test: code_hdl_models_encoder_4to2_gates -> ok 551s Test: code_hdl_models_encoder_using_case -> ok 552s Test: code_hdl_models_encoder_using_if -> ok 552s Test: code_hdl_models_full_adder_gates -> ok 552s Test: code_hdl_models_full_subtracter_gates -> ok 553s Test: code_hdl_models_gray_counter -> ok 553s Test: code_hdl_models_half_adder_gates -> ok 553s Test: code_hdl_models_lfsr -> ok 554s Test: code_hdl_models_lfsr_updown -> ok 554s Test: code_hdl_models_mux_2to1_gates -> ok 554s Test: code_hdl_models_mux_using_assign -> ok 555s Test: code_hdl_models_mux_using_case -> ok 555s Test: code_hdl_models_mux_using_if -> ok 555s Test: code_hdl_models_one_hot_cnt -> ok 556s Test: code_hdl_models_parallel_crc -> ok 556s Test: code_hdl_models_parity_using_assign -> ok 556s Test: code_hdl_models_parity_using_bitwise -> ok 557s Test: code_hdl_models_parity_using_function -> ok 557s Test: code_hdl_models_pri_encoder_using_assign -> ok 557s Test: code_hdl_models_rom_using_case -> ok 558s Test: code_hdl_models_serial_crc -> ok 558s Test: code_hdl_models_tff_async_reset -> ok 558s Test: code_hdl_models_tff_sync_reset -> ok 560s Test: code_hdl_models_uart -> ok 560s Test: code_hdl_models_up_counter -> ok 561s Test: code_hdl_models_up_counter_load -> ok 561s Test: code_hdl_models_up_down_counter -> ok 562s Test: code_specman_switch_fabric -> ok 562s Test: code_tidbits_asyn_reset -> ok 564s Test: code_tidbits_blocking -> ok 564s Test: code_tidbits_fsm_using_always -> ok 564s Test: code_tidbits_fsm_using_function -> ok 564s Test: code_tidbits_fsm_using_single_always -> ok 564s Test: code_tidbits_nonblocking -> ok 565s Test: code_tidbits_reg_combo_example -> ok 565s Test: code_tidbits_reg_seq_example -> ok 565s Test: code_tidbits_syn_reset -> ok 565s Test: code_tidbits_wire_example -> ok 566s Test: code_verilog_tutorial_addbit -> ok 566s Test: code_verilog_tutorial_always_example -> ok 566s Test: code_verilog_tutorial_bus_con -> ok 566s Test: code_verilog_tutorial_comment -> ok 567s Test: code_verilog_tutorial_counter -> ok 567s Test: code_verilog_tutorial_d_ff -> ok 567s Test: code_verilog_tutorial_decoder -> ok 568s Test: code_verilog_tutorial_decoder_always -> ok 568s Test: code_verilog_tutorial_escape_id -> ok 568s Test: code_verilog_tutorial_explicit -> ok 568s Test: code_verilog_tutorial_first_counter -> ok 569s Test: code_verilog_tutorial_flip_flop -> ok 569s Test: code_verilog_tutorial_fsm_full -> ok 569s Test: code_verilog_tutorial_good_code -> ok 570s Test: code_verilog_tutorial_if_else -> ok 570s Test: code_verilog_tutorial_multiply -> ok 570s Test: code_verilog_tutorial_mux_21 -> ok 570s Test: code_verilog_tutorial_n_out_primitive -> ok 571s Test: code_verilog_tutorial_parallel_if -> ok 571s Test: code_verilog_tutorial_parity -> ok 571s Test: code_verilog_tutorial_simple_function -> ok 571s Test: code_verilog_tutorial_simple_if -> ok 572s Test: code_verilog_tutorial_task_global -> ok 572s Test: code_verilog_tutorial_tri_buf -> ok 572s Test: code_verilog_tutorial_v2k_reg -> ok 572s Test: code_verilog_tutorial_which_clock -> ok 572s make[1]: Leaving directory '/tmp/autopkgtest.qrrc6z/build.ei9/src/tests/asicworld' 572s # +cd tests/realmath && bash run-test.sh "" 572s cd tests/share && bash run-test.sh "" 572s generating tests.. 572s running tests.. 577s [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41][42][43][44][45][46][47][48][49][50][51][52][53][54][55][56][57][58][59][60][61][62][63][64][65][66][67][68][69][70][71][72][73][74][75][76][77][78][79][80][81][82][83][84][85][86][87][88][89][90][91][92][93][94][95][96][97][98][99] 577s cd tests/opt_share && bash run-test.sh "" 577s generating tests.. 577s running tests.. 577s make[1]: Entering directory '/tmp/autopkgtest.qrrc6z/build.ei9/src/tests/opt_share' 621s [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41][42][43][44][45][46][47][48][49][50][51][52][53][54][55][56][57][58][59][60][61][62][63][64][65][66][67][68][69][70][71][72][73][74][75][76][77][78][79][80][81][82][83][84][85][86][87][88][89][90][91][92][93][94][95][96][97][98][99]make[1]: Leaving directory '/tmp/autopkgtest.qrrc6z/build.ei9/src/tests/opt_share' 621s 621s cd tests/fsm && bash run-test.sh "" 621s generating tests.. 621s PRNG seed: 5130840747951213405 621s running tests.. 621s make[1]: Entering directory '/tmp/autopkgtest.qrrc6z/build.ei9/src/tests/fsm' 622s [0]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 622s Users of state reg look like FSM recoding might result in larger circuit. 622s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 624s K[1]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 624s Users of state reg look like FSM recoding might result in larger circuit. 624s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 625s K[2]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 625s Users of state reg look like FSM recoding might result in larger circuit. 625s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 626s K[3]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 626s Users of state reg look like FSM recoding might result in larger circuit. 626s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 627s K[4]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 627s Users of state reg look like FSM recoding might result in larger circuit. 627s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 628s K[5]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 628s Users of state reg look like FSM recoding might result in larger circuit. 628s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 631s K[6]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 631s Users of state reg look like FSM recoding might result in larger circuit. 631s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 631s K[7]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 631s Users of state reg look like FSM recoding might result in larger circuit. 631s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 633s K[8]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 633s Users of state reg look like FSM recoding might result in larger circuit. 633s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 634s K[9]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 634s Users of state reg look like FSM recoding might result in larger circuit. 634s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 634s K[10]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 634s Users of state reg look like FSM recoding might result in larger circuit. 634s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 637s K[11]K[12]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 637s Users of state reg look like FSM recoding might result in larger circuit. 637s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 642s K[13]K[14]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 642s Users of state reg look like FSM recoding might result in larger circuit. 642s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 665s T[15]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 665s Users of state reg look like FSM recoding might result in larger circuit. 665s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 665s K[16]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 665s Users of state reg look like FSM recoding might result in larger circuit. 665s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 666s K[17]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 666s Users of state reg look like FSM recoding might result in larger circuit. 666s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 667s K[18]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 667s Users of state reg look like FSM recoding might result in larger circuit. 667s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 668s K[19]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 668s Users of state reg look like FSM recoding might result in larger circuit. 668s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 669s K[20]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 669s Users of state reg look like FSM recoding might result in larger circuit. 669s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 690s K[21]K[22]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 690s Users of state reg look like FSM recoding might result in larger circuit. 690s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 694s K[23]K[24]K[25]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 694s Users of state reg look like FSM recoding might result in larger circuit. 694s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 698s K[26]K[27]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 698s Users of state reg look like FSM recoding might result in larger circuit. 698s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 700s K[28]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 700s Users of state reg look like FSM recoding might result in larger circuit. 700s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 701s K[29]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 701s Users of state reg look like FSM recoding might result in larger circuit. 701s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 702s K[30]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 702s Users of state reg look like FSM recoding might result in larger circuit. 702s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 725s T[31]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 725s Users of state reg look like FSM recoding might result in larger circuit. 725s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 728s K[32]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 728s Users of state reg look like FSM recoding might result in larger circuit. 728s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 729s K[33]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 729s Users of state reg look like FSM recoding might result in larger circuit. 729s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 730s K[34]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 730s Users of state reg look like FSM recoding might result in larger circuit. 730s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 737s K[35]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 737s Users of state reg look like FSM recoding might result in larger circuit. 737s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 738s K[36]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 738s Users of state reg look like FSM recoding might result in larger circuit. 738s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 739s K[37]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 739s Users of state reg look like FSM recoding might result in larger circuit. 739s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 739s K[38]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 739s Users of state reg look like FSM recoding might result in larger circuit. 739s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 741s K[39]K[40]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 741s Users of state reg look like FSM recoding might result in larger circuit. 741s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 750s K[41]K[42]K[43]K[44]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 750s Users of state reg look like FSM recoding might result in larger circuit. 750s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 750s K[45]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 750s Users of state reg look like FSM recoding might result in larger circuit. 750s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 753s K[46]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 753s Users of state reg look like FSM recoding might result in larger circuit. 753s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 756s K[47]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 756s Users of state reg look like FSM recoding might result in larger circuit. 756s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 762s K[48]K[49]K 762s make[1]: Leaving directory '/tmp/autopkgtest.qrrc6z/build.ei9/src/tests/fsm' 762s cd tests/techmap && bash run-test.sh 762s make[1]: Entering directory '/tmp/autopkgtest.qrrc6z/build.ei9/src/tests/techmap' 764s Passed abc9.ys 764s Warning: wire '\Q' is assigned in a block at < ok 778s Test: firrtl_938 -> ok 778s Test: implicit_en -> ok 781s Test: issue00335 -> ok 782s Test: issue00710 -> ok 783s Test: no_implicit_en -> ok 784s Test: read_arst -> ok 785s Test: read_two_mux -> ok 786s Test: shared_ports -> ok 786s Test: simple_sram_byte_en -> ok 788s Test: trans_addr_enable -> ok 789s Test: trans_sdp -> ok 790s Test: trans_sp -> ok 791s Test: wide_all -> ok 792s Test: wide_read_async -> ok 793s Test: wide_read_mixed -> ok 794s Test: wide_read_sync -> ok 796s Test: wide_read_trans -> ok 797s Test: wide_thru_priority -> ok 798s Test: wide_write -> ok 798s make[1]: Leaving directory '/tmp/autopkgtest.qrrc6z/build.ei9/src/tests/memories' 798s Testing expectations for amber23_sram_byte_en.v .. ok. 798s Testing expectations for implicit_en.v .. ok. 798s Testing expectations for issue00335.v .. ok. 798s Testing expectations for issue00710.v .. ok. 798s Testing expectations for no_implicit_en.v .. ok. 798s Testing expectations for read_arst.v .. ok. 798s Testing expectations for read_two_mux.v .. ok. 798s Testing expectations for shared_ports.v .. ok. 799s Testing expectations for simple_sram_byte_en.v .. ok. 799s Testing expectations for trans_addr_enable.v .. ok. 799s Testing expectations for trans_sdp.v .. ok. 799s Testing expectations for trans_sp.v .. ok. 799s Testing expectations for wide_all.v .. ok. 799s Testing expectations for wide_read_async.v .. ok. 799s Testing expectations for wide_read_mixed.v .. ok. 799s Testing expectations for wide_read_sync.v .. ok. 799s Testing expectations for wide_read_trans.v .. ok. 799s Testing expectations for wide_thru_priority.v .. ok. 799s Testing expectations for wide_write.v .. ok. 799s cd tests/memlib && bash run-test.sh "" 799s make[1]: Entering directory '/tmp/autopkgtest.qrrc6z/build.ei9/src/tests/memlib' 801s Test: t_async_big -> ok 804s Test: t_async_big_block -> ok 804s Test: t_async_small -> ok 804s Test: t_async_small_block -> ok 804s Test: t_sync_big -> ok 805s Test: t_sync_big_sdp -> ok 806s Test: t_sync_big_lut -> ok 806s Test: t_sync_small -> ok 806s Test: t_sync_small_block -> ok 806s Test: t_sync_small_block_attr -> ok 807s Test: t_init_lut_zeros_zero -> ok 807s Test: t_init_lut_zeros_any -> ok 807s Test: t_init_lut_val_zero -> ok 807s Test: t_init_lut_val_any -> ok 807s Test: t_init_lut_val_no_undef -> ok 808s Test: t_init_lut_val2_any -> ok 808s Test: t_init_lut_val2_no_undef -> ok 808s Test: t_init_lut_x_none -> ok 808s Test: t_init_lut_x_zero -> ok 808s Test: t_init_lut_x_any -> ok 809s Test: t_init_lut_x_no_undef -> ok 809s Test: t_ram_18b2B -> ok 809s Test: t_ram_9b1B -> ok 809s Test: t_ram_4b1B -> ok 809s Test: t_ram_2b1B -> ok 810s Test: t_ram_1b1B -> ok 810s Test: t_init_9b1B_zeros_zero -> ok 810s Test: t_init_9b1B_zeros_any -> ok 810s Test: t_init_9b1B_val_zero -> ok 810s Test: t_init_9b1B_val_any -> ok 810s Test: t_init_9b1B_val_no_undef -> ok 811s Test: t_init_13b2B_val_any -> ok 811s Test: t_init_18b2B_val_any -> ok 811s Test: t_init_18b2B_val_no_undef -> ok 811s Test: t_init_4b1B_x_none -> ok 811s Test: t_init_4b1B_x_zero -> ok 812s Test: t_init_4b1B_x_any -> ok 812s Test: t_init_4b1B_x_no_undef -> ok 812s Test: t_clock_a4_wANYrANYsFalse -> ok 812s Test: t_clock_a4_wANYrNEGsFalse -> ok 812s Test: t_clock_a4_wANYrPOSsFalse -> ok 813s Test: t_clock_a4_wNEGrANYsFalse -> ok 813s Test: t_clock_a4_wNEGrPOSsFalse -> ok 813s Test: t_clock_a4_wNEGrNEGsFalse -> ok 813s Test: t_clock_a4_wPOSrANYsFalse -> ok 813s Test: t_clock_a4_wPOSrNEGsFalse -> ok 814s Test: t_clock_a4_wPOSrPOSsFalse -> ok 814s Test: t_clock_a4_wANYrANYsTrue -> ok 814s Test: t_clock_a4_wNEGrPOSsTrue -> ok 814s Test: t_clock_a4_wNEGrNEGsTrue -> ok 814s Test: t_clock_a4_wPOSrNEGsTrue -> ok 814s Test: t_clock_a4_wPOSrPOSsTrue -> ok 818s Test: t_unmixed -> ok 818s Test: t_mixed_9_18 -> ok 818s Test: t_mixed_18_9 -> ok 818s Test: t_mixed_36_9 -> ok 818s Test: t_mixed_4_2 -> ok 818s Test: t_tdp -> ok 818s Test: t_sync_2clk -> ok 818s Test: t_sync_shared -> ok 818s Test: t_sync_2clk_shared -> ok 818s Test: t_sync_trans_old_old -> ok 818s Test: t_sync_trans_old_new -> ok 818s Test: t_sync_trans_old_none -> ok 818s Test: t_sync_trans_new_old -> ok 818s Test: t_sync_trans_new_new -> ok 818s Test: t_sync_trans_new_none -> ok 818s Test: t_sp_nc_none -> ok 818s Test: t_sp_new_none -> ok 818s Test: t_sp_old_none -> ok 818s Test: t_sp_nc_nc -> ok 818s Test: t_sp_new_nc -> ok 819s Test: t_sp_old_nc -> ok 819s Test: t_sp_nc_new -> ok 819s Test: t_sp_new_new -> ok 819s Test: t_sp_old_new -> ok 819s Test: t_sp_nc_old -> ok 820s Test: t_sp_new_old -> ok 820s Test: t_sp_old_old -> ok 820s Test: t_sp_nc_new_only -> ok 820s Test: t_sp_new_new_only -> ok 820s Test: t_sp_old_new_only -> ok 820s Test: t_sp_nc_new_only_be -> ok 821s Test: t_sp_new_new_only_be -> ok 821s Test: t_sp_old_new_only_be -> ok 821s Test: t_sp_nc_new_be -> ok 821s Test: t_sp_new_new_be -> ok 821s Test: t_sp_old_new_be -> ok 822s Test: t_sp_nc_old_be -> ok 822s Test: t_sp_new_old_be -> ok 822s Test: t_sp_old_old_be -> ok 822s Test: t_sp_nc_nc_be -> ok 822s Test: t_sp_new_nc_be -> ok 823s Test: t_sp_old_nc_be -> ok 823s Test: t_sp_nc_auto -> ok 823s Test: t_sp_new_auto -> ok 823s Test: t_sp_old_auto -> ok 823s Test: t_sp_nc_auto_be -> ok 823s Test: t_sp_new_auto_be -> ok 823s Test: t_sp_old_auto_be -> ok 824s Test: t_sp_init_x_x -> ok 824s Test: t_sp_init_x_x_re -> ok 824s Test: t_sp_init_x_x_ce -> ok 824s Test: t_sp_init_0_x -> ok 824s Test: t_sp_init_0_x_re -> ok 825s Test: t_sp_init_0_0 -> ok 825s Test: t_sp_init_0_0_re -> ok 825s Test: t_sp_init_0_any -> ok 825s Test: t_sp_init_0_any_re -> ok 825s Test: t_sp_init_v_x -> ok 825s Test: t_sp_init_v_x_re -> ok 826s Test: t_sp_init_v_0 -> ok 826s Test: t_sp_init_v_0_re -> ok 826s Test: t_sp_init_v_any -> ok 826s Test: t_sp_init_v_any_re -> ok 826s Test: t_sp_arst_x_x -> ok 826s Test: t_sp_arst_x_x_re -> ok 827s Test: t_sp_arst_0_x -> ok 827s Test: t_sp_arst_0_x_re -> ok 827s Test: t_sp_arst_0_0 -> ok 827s Test: t_sp_arst_0_0_re -> ok 827s Test: t_sp_arst_0_any -> ok 828s Test: t_sp_arst_0_any_re -> ok 828s Test: t_sp_arst_0_init -> ok 828s Test: t_sp_arst_0_init_re -> ok 828s Test: t_sp_arst_v_x -> ok 828s Test: t_sp_arst_v_x_re -> ok 828s Test: t_sp_arst_v_0 -> ok 829s Test: t_sp_arst_v_0_re -> ok 829s Test: t_sp_arst_v_any -> ok 829s Test: t_sp_arst_v_any_re -> ok 829s Test: t_sp_arst_v_init -> ok 829s Test: t_sp_arst_v_init_re -> ok 829s Test: t_sp_arst_e_x -> ok 830s Test: t_sp_arst_e_x_re -> ok 830s Test: t_sp_arst_e_0 -> ok 830s Test: t_sp_arst_e_0_re -> ok 830s Test: t_sp_arst_e_any -> ok 830s Test: t_sp_arst_e_any_re -> ok 831s Test: t_sp_arst_e_init -> ok 831s Test: t_sp_arst_e_init_re -> ok 831s Test: t_sp_arst_n_x -> ok 831s Test: t_sp_arst_n_x_re -> ok 831s Test: t_sp_arst_n_0 -> ok 831s Test: t_sp_arst_n_0_re -> ok 832s Test: t_sp_arst_n_any -> ok 832s Test: t_sp_arst_n_any_re -> ok 832s Test: t_sp_arst_n_init -> ok 832s Test: t_sp_arst_n_init_re -> ok 832s Test: t_sp_srst_x_x -> ok 833s Test: t_sp_srst_x_x_re -> ok 833s Test: t_sp_srst_0_x -> ok 833s Test: t_sp_srst_0_x_re -> ok 833s Test: t_sp_srst_0_0 -> ok 833s Test: t_sp_srst_0_0_re -> ok 834s Test: t_sp_srst_0_any -> ok 834s Test: t_sp_srst_0_any_re -> ok 834s Test: t_sp_srst_0_init -> ok 834s Test: t_sp_srst_0_init_re -> ok 834s Test: t_sp_srst_v_x -> ok 834s Test: t_sp_srst_v_x_re -> ok 836s Test: t_sp_srst_v_0 -> ok 836s Test: t_sp_srst_v_0_re -> ok 836s Test: t_sp_srst_v_any -> ok 836s Test: t_sp_srst_v_any_re -> ok 836s Test: t_sp_srst_v_any_re_gated -> ok 836s Test: t_sp_srst_v_any_ce -> ok 836s Test: t_sp_srst_v_any_ce_gated -> ok 836s Test: t_sp_srst_v_init -> ok 836s Test: t_sp_srst_v_init_re -> ok 836s Test: t_sp_srst_e_x -> ok 837s Test: t_sp_srst_e_x_re -> ok 837s Test: t_sp_srst_e_0 -> ok 837s Test: t_sp_srst_e_0_re -> ok 837s Test: t_sp_srst_e_any -> ok 838s Test: t_sp_srst_e_any_re -> ok 838s Test: t_sp_srst_e_init -> ok 838s Test: t_sp_srst_e_init_re -> ok 838s Test: t_sp_srst_n_x -> ok 838s Test: t_sp_srst_n_x_re -> ok 839s Test: t_sp_srst_n_0 -> ok 839s Test: t_sp_srst_n_0_re -> ok 839s Test: t_sp_srst_n_any -> ok 839s Test: t_sp_srst_n_any_re -> ok 839s Test: t_sp_srst_n_init -> ok 840s Test: t_sp_srst_n_init_re -> ok 840s Test: t_sp_srst_gv_x -> ok 840s Test: t_sp_srst_gv_x_re -> ok 840s Test: t_sp_srst_gv_0 -> ok 840s Test: t_sp_srst_gv_0_re -> ok 841s Test: t_sp_srst_gv_any -> ok 841s Test: t_sp_srst_gv_any_re -> ok 841s Test: t_sp_srst_gv_any_re_gated -> ok 841s Test: t_sp_srst_gv_any_ce -> ok 841s Test: t_sp_srst_gv_any_ce_gated -> ok 841s Test: t_sp_srst_gv_init -> ok 842s Test: t_sp_srst_gv_init_re -> ok 842s Test: t_wren_a4d4_NO_BYTE -> ok 842s Test: t_wren_a5d4_NO_BYTE -> ok 842s Test: t_wren_a6d4_NO_BYTE -> ok 842s Test: t_wren_a3d8_NO_BYTE -> ok 843s Test: t_wren_a4d8_NO_BYTE -> ok 843s Test: t_wren_a4d4_W4_B4 -> ok 843s Test: t_wren_a4d8_W4_B4_separate -> ok 843s Test: t_wren_a4d8_W8_B4 -> ok 843s Test: t_wren_a4d8_W8_B4_separate -> ok 843s Test: t_wren_a4d8_W8_B8 -> ok 844s Test: t_wren_a4d8_W8_B8_separate -> ok 844s Test: t_wren_a4d2w8_W16_B4 -> ok 844s Test: t_wren_a4d2w8_W16_B4_separate -> ok 844s Test: t_wren_a4d4w4_W16_B4 -> ok 845s Test: t_wren_a4d4w4_W16_B4_separate -> ok 845s Test: t_wren_a5d4w2_W16_B4 -> ok 845s Test: t_wren_a5d4w2_W16_B4_separate -> ok 845s Test: t_wren_a5d4w4_W16_B4 -> ok 845s Test: t_wren_a5d4w4_W16_B4_separate -> ok 846s Test: t_wren_a4d8w2_W16_B4 -> ok 846s Test: t_wren_a4d8w2_W16_B4_separate -> ok 846s Test: t_wren_a5d8w1_W16_B4 -> ok 846s Test: t_wren_a5d8w1_W16_B4_separate -> ok 846s Test: t_wren_a5d8w2_W16_B4 -> ok 847s Test: t_wren_a5d8w2_W16_B4_separate -> ok 847s Test: t_wren_a4d16w1_W16_B4 -> ok 847s Test: t_wren_a4d16w1_W16_B4_separate -> ok 847s Test: t_wren_a4d4w2_W8_B8 -> ok 847s Test: t_wren_a4d4w2_W8_B8_separate -> ok 848s Test: t_wren_a4d4w1_W8_B8 -> ok 848s Test: t_wren_a4d4w1_W8_B8_separate -> ok 848s Test: t_wren_a4d8w2_W8_B8 -> ok 848s Test: t_wren_a4d8w2_W8_B8_separate -> ok 848s Test: t_wren_a3d8w2_W8_B8 -> ok 849s Test: t_wren_a3d8w2_W8_B8_separate -> ok 849s Test: t_wren_a4d4w2_W8_B4 -> ok 849s Test: t_wren_a4d4w2_W8_B4_separate -> ok 849s Test: t_wren_a4d2w4_W8_B4 -> ok 849s Test: t_wren_a4d2w4_W8_B4_separate -> ok 849s Test: t_wren_a4d4w4_W8_B4 -> ok 851s Test: t_wren_a4d4w4_W8_B4_separate -> ok 851s Test: t_wren_a4d4w4_W4_B4 -> ok 851s Test: t_wren_a4d4w4_W4_B4_separate -> ok 851s Test: t_wren_a4d4w5_W4_B4 -> ok 851s Test: t_wren_a4d4w5_W4_B4_separate -> ok 851s Test: t_geom_a4d64_wren -> ok 851s Test: t_geom_a5d32_wren -> ok 851s Test: t_geom_a5d64_wren -> ok 851s Test: t_geom_a6d16_wren -> ok 851s Test: t_geom_a6d30_wren -> ok 852s Test: t_geom_a6d64_wren -> ok 852s Test: t_geom_a7d4_wren -> ok 852s Test: t_geom_a7d6_wren -> ok 852s Test: t_geom_a7d8_wren -> ok 852s Test: t_geom_a7d17_wren -> ok 853s Test: t_geom_a8d4_wren -> ok 853s Test: t_geom_a8d6_wren -> ok 853s Test: t_geom_a9d4_wren -> ok 853s Test: t_geom_a9d8_wren -> ok 853s Test: t_geom_a9d5_wren -> ok 853s Test: t_geom_a9d6_wren -> ok 854s Test: t_geom_a3d18_9b1B -> ok 854s Test: t_geom_a4d4_9b1B -> ok 854s Test: t_geom_a4d18_9b1B -> ok 854s Test: t_geom_a5d32_9b1B -> ok 854s Test: t_geom_a6d4_9b1B -> ok 855s Test: t_geom_a7d11_9b1B -> ok 855s Test: t_geom_a7d18_9b1B -> ok 855s Test: t_geom_a11d1_9b1B -> ok 855s Test: t_wide_sdp_a6r1w1b1x1 -> ok 855s Test: t_wide_sdp_a7r1w1b1x1 -> ok 856s Test: t_wide_sdp_a8r1w1b1x1 -> ok 856s Test: t_wide_sdp_a6r0w0b0x0 -> ok 856s Test: t_wide_sdp_a6r1w0b0x0 -> ok 856s Test: t_wide_sdp_a6r2w0b0x0 -> ok 857s Test: t_wide_sdp_a6r3w0b0x0 -> ok 857s Test: t_wide_sdp_a6r4w0b0x0 -> ok 857s Test: t_wide_sdp_a6r5w0b0x0 -> ok 857s Test: t_wide_sdp_a6r0w1b0x0 -> ok 858s Test: t_wide_sdp_a6r0w1b1x0 -> ok 858s Test: t_wide_sdp_a6r0w2b0x0 -> ok 858s Test: t_wide_sdp_a6r0w2b2x0 -> ok 858s Test: t_wide_sdp_a6r0w3b2x0 -> ok 859s Test: t_wide_sdp_a6r0w4b2x0 -> ok 859s Test: t_wide_sdp_a6r0w5b2x0 -> ok 859s Test: t_wide_sdp_a7r0w0b0x0 -> ok 860s Test: t_wide_sdp_a7r1w0b0x0 -> ok 860s Test: t_wide_sdp_a7r2w0b0x0 -> ok 860s Test: t_wide_sdp_a7r3w0b0x0 -> ok 860s Test: t_wide_sdp_a7r4w0b0x0 -> ok 861s Test: t_wide_sdp_a7r5w0b0x0 -> ok 861s Test: t_wide_sdp_a7r0w1b0x0 -> ok 861s Test: t_wide_sdp_a7r0w1b1x0 -> ok 861s Test: t_wide_sdp_a7r0w2b0x0 -> ok 862s Test: t_wide_sdp_a7r0w2b2x0 -> ok 862s Test: t_wide_sdp_a7r0w3b2x0 -> ok 862s Test: t_wide_sdp_a7r0w4b2x0 -> ok 863s Test: t_wide_sdp_a7r0w5b2x0 -> ok 863s Test: t_wide_sp_mix_a6r1w1b1 -> ok 863s Test: t_wide_sp_mix_a7r1w1b1 -> ok 863s Test: t_wide_sp_mix_a8r1w1b1 -> ok 864s Test: t_wide_sp_mix_a6r0w0b0 -> ok 864s Test: t_wide_sp_mix_a6r1w0b0 -> ok 864s Test: t_wide_sp_mix_a6r2w0b0 -> ok 864s Test: t_wide_sp_mix_a6r3w0b0 -> ok 865s Test: t_wide_sp_mix_a6r4w0b0 -> ok 865s Test: t_wide_sp_mix_a6r5w0b0 -> ok 865s Test: t_wide_sp_mix_a6r0w1b0 -> ok 865s Test: t_wide_sp_mix_a6r0w1b1 -> ok 866s Test: t_wide_sp_mix_a6r0w2b0 -> ok 866s Test: t_wide_sp_mix_a6r0w2b2 -> ok 866s Test: t_wide_sp_mix_a6r0w3b2 -> ok 866s Test: t_wide_sp_mix_a6r0w4b2 -> ok 867s Test: t_wide_sp_mix_a6r0w5b2 -> ok 867s Test: t_wide_sp_mix_a7r0w0b0 -> ok 867s Test: t_wide_sp_mix_a7r1w0b0 -> ok 867s Test: t_wide_sp_mix_a7r2w0b0 -> ok 868s Test: t_wide_sp_mix_a7r3w0b0 -> ok 868s Test: t_wide_sp_mix_a7r4w0b0 -> ok 868s Test: t_wide_sp_mix_a7r5w0b0 -> ok 868s Test: t_wide_sp_mix_a7r0w1b0 -> ok 869s Test: t_wide_sp_mix_a7r0w1b1 -> ok 869s Test: t_wide_sp_mix_a7r0w2b0 -> ok 869s Test: t_wide_sp_mix_a7r0w2b2 -> ok 869s Test: t_wide_sp_mix_a7r0w3b2 -> ok 870s Test: t_wide_sp_mix_a7r0w4b2 -> ok 870s Test: t_wide_sp_mix_a7r0w5b2 -> ok 870s Test: t_wide_sp_tied_a6r1w1b1 -> ok 871s Test: t_wide_sp_tied_a7r1w1b1 -> ok 871s Test: t_wide_sp_tied_a8r1w1b1 -> ok 871s Test: t_wide_sp_tied_a6r0w0b0 -> ok 871s Test: t_wide_sp_tied_a6r1w0b0 -> ok 871s Test: t_wide_sp_tied_a6r2w0b0 -> ok 872s Test: t_wide_sp_tied_a6r3w0b0 -> ok 872s Test: t_wide_sp_tied_a6r4w0b0 -> ok 872s Test: t_wide_sp_tied_a6r5w0b0 -> ok 872s Test: t_wide_sp_tied_a6r0w1b0 -> ok 873s Test: t_wide_sp_tied_a6r0w1b1 -> ok 873s Test: t_wide_sp_tied_a6r0w2b0 -> ok 873s Test: t_wide_sp_tied_a6r0w2b2 -> ok 873s Test: t_wide_sp_tied_a6r0w3b2 -> ok 874s Test: t_wide_sp_tied_a6r0w4b2 -> ok 874s Test: t_wide_sp_tied_a6r0w5b2 -> ok 874s Test: t_wide_sp_tied_a7r0w0b0 -> ok 875s Test: t_wide_sp_tied_a7r1w0b0 -> ok 875s Test: t_wide_sp_tied_a7r2w0b0 -> ok 875s Test: t_wide_sp_tied_a7r3w0b0 -> ok 875s Test: t_wide_sp_tied_a7r4w0b0 -> ok 876s Test: t_wide_sp_tied_a7r5w0b0 -> ok 876s Test: t_wide_sp_tied_a7r0w1b0 -> ok 876s Test: t_wide_sp_tied_a7r0w1b1 -> ok 876s Test: t_wide_sp_tied_a7r0w2b0 -> ok 877s Test: t_wide_sp_tied_a7r0w2b2 -> ok 877s Test: t_wide_sp_tied_a7r0w3b2 -> ok 877s Test: t_wide_sp_tied_a7r0w4b2 -> ok 878s Test: t_wide_sp_tied_a7r0w5b2 -> ok 878s Test: t_wide_read_a6r1w1b1 -> ok 878s Test: t_wide_write_a6r1w1b1 -> ok 878s Test: t_wide_read_a7r1w1b1 -> ok 878s Test: t_wide_write_a7r1w1b1 -> ok 879s Test: t_wide_read_a8r1w1b1 -> ok 879s Test: t_wide_write_a8r1w1b1 -> ok 879s Test: t_wide_read_a6r0w0b0 -> ok 879s Test: t_wide_write_a6r0w0b0 -> ok 879s Test: t_wide_read_a6r1w0b0 -> ok 880s Test: t_wide_write_a6r1w0b0 -> ok 880s Test: t_wide_read_a6r2w0b0 -> ok 880s Test: t_wide_write_a6r2w0b0 -> ok 880s Test: t_wide_read_a6r3w0b0 -> ok 880s Test: t_wide_write_a6r3w0b0 -> ok 881s Test: t_wide_read_a6r4w0b0 -> ok 881s Test: t_wide_write_a6r4w0b0 -> ok 881s Test: t_wide_read_a6r5w0b0 -> ok 882s Test: t_wide_write_a6r5w0b0 -> ok 882s Test: t_wide_read_a6r0w1b0 -> ok 882s Test: t_wide_write_a6r0w1b0 -> ok 882s Test: t_wide_read_a6r0w1b1 -> ok 882s Test: t_wide_write_a6r0w1b1 -> ok 883s Test: t_wide_read_a6r0w2b0 -> ok 883s Test: t_wide_write_a6r0w2b0 -> ok 883s Test: t_wide_read_a6r0w2b2 -> ok 883s Test: t_wide_write_a6r0w2b2 -> ok 884s Test: t_wide_read_a6r0w3b2 -> ok 884s Test: t_wide_write_a6r0w3b2 -> ok 884s Test: t_wide_read_a6r0w4b2 -> ok 884s Test: t_wide_write_a6r0w4b2 -> ok 886s Test: t_wide_read_a6r0w5b2 -> ok 886s Test: t_wide_write_a6r0w5b2 -> ok 886s Test: t_wide_read_a7r0w0b0 -> ok 886s Test: t_wide_write_a7r0w0b0 -> ok 886s Test: t_wide_read_a7r1w0b0 -> ok 886s Test: t_wide_write_a7r1w0b0 -> ok 886s Test: t_wide_read_a7r2w0b0 -> ok 887s Test: t_wide_write_a7r2w0b0 -> ok 887s Test: t_wide_read_a7r3w0b0 -> ok 887s Test: t_wide_write_a7r3w0b0 -> ok 887s Test: t_wide_read_a7r4w0b0 -> ok 888s Test: t_wide_write_a7r4w0b0 -> ok 888s Test: t_wide_read_a7r5w0b0 -> ok 888s Test: t_wide_write_a7r5w0b0 -> ok 888s Test: t_wide_read_a7r0w1b0 -> ok 889s Test: t_wide_write_a7r0w1b0 -> ok 889s Test: t_wide_read_a7r0w1b1 -> ok 889s Test: t_wide_write_a7r0w1b1 -> ok 889s Test: t_wide_read_a7r0w2b0 -> ok 889s Test: t_wide_write_a7r0w2b0 -> ok 890s Test: t_wide_read_a7r0w2b2 -> ok 890s Test: t_wide_write_a7r0w2b2 -> ok 890s Test: t_wide_read_a7r0w3b2 -> ok 891s Test: t_wide_write_a7r0w3b2 -> ok 891s Test: t_wide_read_a7r0w4b2 -> ok 891s Test: t_wide_write_a7r0w4b2 -> ok 891s Test: t_wide_read_a7r0w5b2 -> ok 892s Test: t_wide_write_a7r0w5b2 -> ok 892s Test: t_quad_port_a2d2 -> ok 892s Test: t_quad_port_a4d2 -> ok 892s Test: t_quad_port_a5d2 -> ok 893s Test: t_quad_port_a4d4 -> ok 893s Test: t_quad_port_a6d2 -> ok 893s Test: t_quad_port_a4d8 -> ok 893s Test: t_wide_quad_a4w2r1 -> ok 893s Test: t_wide_oct_a4w2r1 -> ok 894s Test: t_wide_quad_a4w2r2 -> ok 894s Test: t_wide_oct_a4w2r2 -> ok 894s Test: t_wide_quad_a4w2r3 -> ok 894s Test: t_wide_oct_a4w2r3 -> ok 894s Test: t_wide_quad_a4w2r4 -> ok 894s Test: t_wide_oct_a4w2r4 -> ok 895s Test: t_wide_quad_a4w2r5 -> ok 895s Test: t_wide_oct_a4w2r5 -> ok 895s Test: t_wide_quad_a4w2r6 -> ok 895s Test: t_wide_oct_a4w2r6 -> ok 895s Test: t_wide_quad_a4w2r7 -> ok 896s Test: t_wide_oct_a4w2r7 -> ok 896s Test: t_wide_quad_a4w2r8 -> ok 896s Test: t_wide_oct_a4w2r8 -> ok 896s Test: t_wide_quad_a4w2r9 -> ok 896s Test: t_wide_oct_a4w2r9 -> ok 897s Test: t_wide_quad_a4w4r1 -> ok 897s Test: t_wide_oct_a4w4r1 -> ok 897s Test: t_wide_quad_a4w4r4 -> ok 897s Test: t_wide_oct_a4w4r4 -> ok 897s Test: t_wide_quad_a4w4r6 -> ok 897s Test: t_wide_oct_a4w4r6 -> ok 898s Test: t_wide_quad_a4w4r9 -> ok 898s Test: t_wide_oct_a4w4r9 -> ok 898s Test: t_wide_quad_a5w2r1 -> ok 898s Test: t_wide_oct_a5w2r1 -> ok 898s Test: t_wide_quad_a5w2r4 -> ok 899s Test: t_wide_oct_a5w2r4 -> ok 899s Test: t_wide_quad_a5w2r9 -> ok 899s Test: t_wide_oct_a5w2r9 -> ok 899s Test: t_no_reset -> ok 899s Test: t_gclken -> ok 901s Test: t_ungated -> ok 901s Test: t_gclken_ce -> ok 901s Test: t_grden -> ok 901s Test: t_grden_ce -> ok 901s Test: t_exclwr -> ok 901s Test: t_excl_rst -> ok 901s Test: t_transwr -> ok 901s Test: t_trans_rst -> ok 901s Test: t_wr_byte -> ok 901s Test: t_trans_byte -> ok 902s Test: t_wr_rst_byte -> ok 902s Test: t_rst_wr_byte -> ok 902s Test: t_rdenrst_wr_byte -> ok 902s make[1]: Leaving directory '/tmp/autopkgtest.qrrc6z/build.ei9/src/tests/memlib' 902s cd tests/bram && bash run-test.sh "" 902s generating tests.. 902s PRNG seed: 962275 902s running tests.. 902s make[1]: Entering directory '/tmp/autopkgtest.qrrc6z/build.ei9/src/tests/bram' 903s Passed memory_bram test 00_01. 904s Passed memory_bram test 00_02. 904s Passed memory_bram test 00_03. 905s Passed memory_bram test 00_04. 906s Passed memory_bram test 01_00. 906s Passed memory_bram test 01_02. 907s Passed memory_bram test 01_03. 908s Passed memory_bram test 01_04. 909s Passed memory_bram test 02_00. 909s Passed memory_bram test 02_01. 910s Passed memory_bram test 02_03. 911s Passed memory_bram test 02_04. 911s Passed memory_bram test 03_00. 913s Passed memory_bram test 03_01. 915s Passed memory_bram test 03_02. 916s Passed memory_bram test 03_04. 916s Passed memory_bram test 04_00. 917s Passed memory_bram test 04_01. 918s Passed memory_bram test 04_02. 919s Passed memory_bram test 04_03. 919s make[1]: Leaving directory '/tmp/autopkgtest.qrrc6z/build.ei9/src/tests/bram' 919s cd tests/various && bash run-test.sh 919s make[1]: Entering directory '/tmp/autopkgtest.qrrc6z/build.ei9/src/tests/various' 919s Warning: Wire abc9_test027.$abc$91$o is used but has no driver. 919s Passed abc9.ys 919s Passed aiger_dff.ys 919s Passed attrib05_port_conn.ys 919s Passed attrib07_func_call.ys 919s Passed autoname.ys 919s Passed blackbox_wb.ys 919s Passed bug1496.ys 919s Passed bug1531.ys 919s Passed bug1614.ys 919s Passed bug1710.ys 920s Warning: Yosys has only limited support for tri-state logic at the moment. (< svinterface1_tb.v:50: $finish called at 420000 (10ps) 984s svinterface1_tb.v:50: $finish called at 420000 (10ps) 984s ok 985s Test: svinterface_at_top -> svinterface_at_top_tb.v:61: $finish called at 420000 (10ps) 985s svinterface_at_top_tb_wrapper.v:61: $finish called at 420000 (10ps) 985s ERROR! 985s Test: load_and_derive ->ok 985s Test: resolve_types ->ok 985s cd tests/svtypes && bash run-test.sh "" 985s make[1]: Entering directory '/tmp/autopkgtest.qrrc6z/build.ei9/src/tests/svtypes' 985s Passed enum_simple.ys 985s Passed logic_rom.ys 985s < ok 1000s Test ../../techlibs/anlogic/cells_sim.v -> ok 1000s Test ../../techlibs/coolrunner2/cells_sim.v -> ok 1000s Test ../../techlibs/ecp5/cells_sim.v -> ok 1001s Test ../../techlibs/efinix/cells_sim.v -> ok 1001s Test ../../techlibs/gatemate/cells_sim.v -> ok 1001s Test ../../techlibs/gowin/cells_sim.v -> ok 1001s Test ../../techlibs/greenpak4/cells_sim.v -> ok 1001s Test ../../techlibs/ice40/cells_sim.v -DICE40_HX ->../../techlibs/ice40/cells_sim.v:2231: warning: Choosing typ expression. 1001s ../../techlibs/ice40/cells_sim.v:2231: warning: Choosing typ expression. 1001s ../../techlibs/ice40/cells_sim.v:2233: warning: Choosing typ expression. 1001s ../../techlibs/ice40/cells_sim.v:2233: warning: Choosing typ expression. 1001s ../../techlibs/ice40/cells_sim.v:2235: warning: Choosing typ expression. 1001s ../../techlibs/ice40/cells_sim.v:2235: warning: Choosing typ expression. 1001s ../../techlibs/ice40/cells_sim.v:2237: warning: Choosing typ expression. 1001s ../../techlibs/ice40/cells_sim.v:2237: warning: Choosing typ expression. 1001s ../../techlibs/ice40/cells_sim.v:2239: warning: Choosing typ expression. 1001s ../../techlibs/ice40/cells_sim.v:2239: warning: Choosing typ expression. 1001s ok 1001s Test ../../techlibs/ice40/cells_sim.v -DICE40_LP ->../../techlibs/ice40/cells_sim.v:2295: warning: Choosing typ expression. 1001s ../../techlibs/ice40/cells_sim.v:2295: warning: Choosing typ expression. 1001s ../../techlibs/ice40/cells_sim.v:2297: warning: Choosing typ expression. 1001s ../../techlibs/ice40/cells_sim.v:2297: warning: Choosing typ expression. 1001s ../../techlibs/ice40/cells_sim.v:2299: warning: Choosing typ expression. 1001s ../../techlibs/ice40/cells_sim.v:2299: warning: Choosing typ expression. 1001s ../../techlibs/ice40/cells_sim.v:2301: warning: Choosing typ expression. 1001s ../../techlibs/ice40/cells_sim.v:2301: warning: Choosing typ expression. 1001s ../../techlibs/ice40/cells_sim.v:2303: warning: Choosing typ expression. 1001s ../../techlibs/ice40/cells_sim.v:2303: warning: Choosing typ expression. 1001s ../../techlibs/ice40/cells_sim.v:2359: warning: Choosing typ expression. 1001s ../../techlibs/ice40/cells_sim.v:2359: warning: Choosing typ expression. 1001s ../../techlibs/ice40/cells_sim.v:2361: warning: Choosing typ expression. 1001s ../../techlibs/ice40/cells_sim.v:2361: warning: Choosing typ expression. 1001s ../../techlibs/ice40/cells_sim.v:2363: warning: Choosing typ expression. 1001s ../../techlibs/ice40/cells_sim.v:2363: warning: Choosing typ expression. 1001s ../../techlibs/ice40/cells_sim.v:2365: warning: Choosing typ expression. 1001s ../../techlibs/ice40/cells_sim.v:2365: warning: Choosing typ expression. 1001s ../../techlibs/ice40/cells_sim.v:2367: warning: Choosing typ expression. 1001s ../../techlibs/ice40/cells_sim.v:2367: warning: Choosing typ expression. 1001s ok 1001s Test ../../techlibs/ice40/cells_sim.v -DICE40_U -> ok 1001s Test ../../techlibs/intel/cyclone10lp/cells_sim.v -> ok 1001s Test ../../techlibs/intel/cycloneiv/cells_sim.v -> ok 1001s Test ../../techlibs/intel/max10/cells_sim.v -> ok 1001s Test ../../techlibs/intel/cycloneive/cells_sim.v -> ok 1001s Test ../../techlibs/intel_alm/cyclonev/cells_sim.v -> ok 1001s Test ../../techlibs/nexus/cells_sim.v -> ok 1001s Test ../../techlibs/quicklogic/cells_sim.v -> ok 1001s Test ../../techlibs/sf2/cells_sim.v -> ok 1001s Test ../../techlibs/xilinx/cells_sim.v -> ok 1001s Test ../../techlibs/common/simcells.v -> ok 1001s Test ../../techlibs/common/simlib.v -> ok 1001s cd tests/arch/ice40 && bash run-test.sh "" 1001s make[1]: Entering directory '/tmp/autopkgtest.qrrc6z/build.ei9/src/tests/arch/ice40' 1002s Passed add_sub.ys 1006s Passed adffs.ys 1006s Warning: Resizing cell port SSCounter6o.l0.I3 from 32 bits to 1 bits. 1006s Warning: Resizing cell port SSCounter6o.c0.CI from 32 bits to 1 bits. 1006s Warning: Resizing cell port SSCounter6o.lien.I0 from 32 bits to 1 bits. 1006s Warning: Resizing cell port SSCounter6o.lien.I1 from 32 bits to 1 bits. 1007s Passed bug1597.ys 1008s Passed bug1598.ys 1009s Passed bug1626.ys 1030s Passed bug1644.ys 1030s Passed bug2061.ys 1032s Passed counter.ys 1034s Passed dffs.ys 1043s Passed dpram.ys 1044s Passed fsm.ys 1044s Passed ice40_dsp.ys 1046s Passed ice40_opt.ys 1046s Passed ice40_wrapcarry.ys 1048s Passed latches.ys 1049s Passed logic.ys 1055s Passed macc.ys 1121s Passed memories.ys 1123s Passed mul.ys 1127s Passed mux.ys 1127s Warning: wire '\data' is assigned in a block at rom.v:10.5-10.15. 1127s Warning: wire '\data' is assigned in a block at rom.v:11.5-11.15. 1127s Warning: wire '\data' is assigned in a block at rom.v:12.5-12.15. 1127s Warning: wire '\data' is assigned in a block at rom.v:13.6-13.16. 1127s Warning: wire '\data' is assigned in a block at rom.v:14.6-14.16. 1127s Warning: wire '\data' is assigned in a block at rom.v:15.6-15.16. 1127s Warning: wire '\data' is assigned in a block at rom.v:16.11-16.21. 1128s Passed rom.ys 1129s Passed shifter.ys 1129s Warning: wire '\read_data' is assigned in a block at spram.v:19.3-19.25. 1131s Passed spram.ys 1132s Passed tribuf.ys 1132s make[1]: Leaving directory '/tmp/autopkgtest.qrrc6z/build.ei9/src/tests/arch/ice40' 1132s cd tests/arch/xilinx && bash run-test.sh "" 1132s make[1]: Entering directory '/tmp/autopkgtest.qrrc6z/build.ei9/src/tests/arch/xilinx' 1150s Warning: Whitebox '$paramod\FDRE\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. 1150s Warning: Whitebox 'FDSE' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. 1150s Warning: Whitebox '$paramod\FDRE_1\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. 1150s Warning: Whitebox '$paramod\FDSE_1\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. 1178s Passed abc9_dff.ys 1184s Warning: Shift register inference not yet supported for family xc3s. 1187s Passed add_sub.ys 1208s Passed adffs.ys 1214s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DIADI from 64 bits to 16 bits. 1214s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOADO from 64 bits to 16 bits. 1214s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOBDO from 64 bits to 16 bits. 1214s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOPADOP from 8 bits to 2 bits. 1214s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOPBDOP from 8 bits to 2 bits. 1214s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.WEA from 4 bits to 2 bits. 1225s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.WEBWE from 1 bits to 4 bits. 1230s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DIADI from 64 bits to 16 bits. 1230s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOADO from 64 bits to 16 bits. 1230s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOBDO from 64 bits to 16 bits. 1230s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOPADOP from 8 bits to 2 bits. 1230s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOPBDOP from 8 bits to 2 bits. 1230s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.WEA from 4 bits to 2 bits. 1230s Warning: Selection "asym_ram_sdp_read_wider" did not match any module. 1247s Passed asym_ram_sdp.ys 1253s Warning: Resizing cell port block_ram.memory.0.0.DIADI from 64 bits to 16 bits. 1253s Warning: Resizing cell port block_ram.memory.0.0.DOADO from 64 bits to 16 bits. 1253s Warning: Resizing cell port block_ram.memory.0.0.DOBDO from 64 bits to 16 bits. 1253s Warning: Resizing cell port block_ram.memory.0.0.DOPADOP from 8 bits to 2 bits. 1253s Warning: Resizing cell port block_ram.memory.0.0.DOPBDOP from 8 bits to 2 bits. 1253s Warning: Resizing cell port block_ram.memory.0.0.WEA from 4 bits to 2 bits. 1281s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DIADI from 64 bits to 16 bits. 1281s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOADO from 64 bits to 16 bits. 1281s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOBDO from 64 bits to 16 bits. 1281s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOPADOP from 8 bits to 2 bits. 1281s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOPBDOP from 8 bits to 2 bits. 1281s Warning: Resizing cell port distributed_ram_manual.memory.0.0.WEA from 4 bits to 2 bits. 1282s Passed attributes_test.ys 1287s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIADI from 64 bits to 16 bits. 1287s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOADO from 64 bits to 16 bits. 1287s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOBDO from 64 bits to 16 bits. 1287s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPADOP from 8 bits to 2 bits. 1287s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPBDOP from 8 bits to 2 bits. 1287s Warning: Resizing cell port sync_ram_sdp.memory.0.0.WEA from 4 bits to 2 bits. 1292s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIPADIP from 8 bits to 2 bits. 1315s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIADI from 64 bits to 32 bits. 1315s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIPADIP from 8 bits to 4 bits. 1315s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOADO from 64 bits to 32 bits. 1315s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOBDO from 64 bits to 32 bits. 1315s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPADOP from 8 bits to 4 bits. 1315s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPBDOP from 8 bits to 4 bits. 1346s Passed blockram.ys 1352s Passed bug1460.ys 1356s Passed bug1462.ys 1361s Passed bug1480.ys 1367s Passed bug1598.ys 1368s Warning: Wire top.\t is used but has no driver. 1368s Warning: Wire top.\in is used but has no driver. 1376s Passed bug1605.ys 1376s Passed bug3670.ys 1378s Passed counter.ys 1401s Passed dffs.ys 1419s Passed dsp_abc9.ys 1432s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef. 1432s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef. 1484s Passed dsp_cascade.ys 1489s Passed dsp_fastfir.ys 1496s Passed dsp_simd.ys 1502s Warning: Shift register inference not yet supported for family xc3se. 1506s Passed fsm.ys 1521s Passed latches.ys 1527s Passed logic.ys 1572s Warning: Shift register inference not yet supported for family xc3s. 1577s Passed lutram.ys 1589s Passed macc.ys 1598s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef. 1598s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef. 1600s Passed mul.ys 1600s Warning: Replacing memory \M with list of registers. See mul_unsigned.v:25 1611s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef. 1611s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef. 1616s Passed mul_unsigned.ys 1638s Passed mux.ys 1638s Warning: Shift register inference not yet supported for family xc3se. 1651s Passed mux_lut4.ys 1662s Passed nosrl.ys 1662s Passed opt_lut_ins.ys 1677s Passed pmgen_xilinx_srl.ys 1683s Warning: Resizing cell port priority_memory.mem.0.0.ADDRARDADDR from 16 bits to 15 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.0.ADDRBWRADDR from 16 bits to 15 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.0.DINADIN from 64 bits to 32 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.0.DINBDIN from 64 bits to 32 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.0.DINPADINP from 8 bits to 4 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.0.DINPBDINP from 8 bits to 4 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.0.DOUTADOUT from 64 bits to 32 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.0.DOUTBDOUT from 64 bits to 32 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.0.DOUTPADOUTP from 8 bits to 4 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.0.DOUTPBDOUTP from 8 bits to 4 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.0.WEBWE from 4 bits to 8 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.1.ADDRARDADDR from 16 bits to 15 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.1.ADDRBWRADDR from 16 bits to 15 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.1.DINADIN from 64 bits to 32 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.1.DINBDIN from 64 bits to 32 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.1.DINPADINP from 8 bits to 4 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.1.DINPBDINP from 8 bits to 4 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.1.DOUTADOUT from 64 bits to 32 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.1.DOUTBDOUT from 64 bits to 32 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.1.DOUTPADOUTP from 8 bits to 4 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.1.DOUTPBDOUTP from 8 bits to 4 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.1.WEBWE from 4 bits to 8 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.2.ADDRARDADDR from 16 bits to 15 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.2.ADDRBWRADDR from 16 bits to 15 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.2.DINADIN from 64 bits to 32 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.2.DINBDIN from 64 bits to 32 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.2.DINPADINP from 8 bits to 4 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.2.DINPBDINP from 8 bits to 4 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.2.DOUTADOUT from 64 bits to 32 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.2.DOUTBDOUT from 64 bits to 32 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.2.DOUTPADOUTP from 8 bits to 4 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.2.DOUTPBDOUTP from 8 bits to 4 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.2.WEBWE from 4 bits to 8 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.3.ADDRARDADDR from 16 bits to 15 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.3.ADDRBWRADDR from 16 bits to 15 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.3.DINADIN from 64 bits to 32 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.3.DINBDIN from 64 bits to 32 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.3.DINPADINP from 8 bits to 4 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.3.DINPBDINP from 8 bits to 4 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.3.DOUTADOUT from 64 bits to 32 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.3.DOUTBDOUT from 64 bits to 32 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.3.DOUTPADOUTP from 8 bits to 4 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.3.DOUTPBDOUTP from 8 bits to 4 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.3.WEBWE from 4 bits to 8 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.4.ADDRARDADDR from 16 bits to 15 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.4.ADDRBWRADDR from 16 bits to 15 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.4.DINADIN from 64 bits to 32 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.4.DINBDIN from 64 bits to 32 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.4.DINPADINP from 8 bits to 4 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.4.DINPBDINP from 8 bits to 4 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.4.DOUTADOUT from 64 bits to 32 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.4.DOUTBDOUT from 64 bits to 32 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.4.DOUTPADOUTP from 8 bits to 4 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.4.DOUTPBDOUTP from 8 bits to 4 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.4.WEBWE from 4 bits to 8 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.5.ADDRARDADDR from 16 bits to 15 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.5.ADDRBWRADDR from 16 bits to 15 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.5.DINADIN from 64 bits to 32 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.5.DINBDIN from 64 bits to 32 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.5.DINPADINP from 8 bits to 4 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.5.DINPBDINP from 8 bits to 4 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.5.DOUTADOUT from 64 bits to 32 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.5.DOUTBDOUT from 64 bits to 32 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.5.DOUTPADOUTP from 8 bits to 4 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.5.DOUTPBDOUTP from 8 bits to 4 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.5.WEBWE from 4 bits to 8 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.6.ADDRARDADDR from 16 bits to 15 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.6.ADDRBWRADDR from 16 bits to 15 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.6.DINADIN from 64 bits to 32 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.6.DINBDIN from 64 bits to 32 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.6.DINPADINP from 8 bits to 4 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.6.DINPBDINP from 8 bits to 4 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.6.DOUTADOUT from 64 bits to 32 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.6.DOUTBDOUT from 64 bits to 32 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.6.DOUTPADOUTP from 8 bits to 4 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.6.DOUTPBDOUTP from 8 bits to 4 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.6.WEBWE from 4 bits to 8 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.7.ADDRARDADDR from 16 bits to 15 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.7.ADDRBWRADDR from 16 bits to 15 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.7.DINADIN from 64 bits to 32 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.7.DINBDIN from 64 bits to 32 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.7.DINPADINP from 8 bits to 4 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.7.DINPBDINP from 8 bits to 4 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.7.DOUTADOUT from 64 bits to 32 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.7.DOUTBDOUT from 64 bits to 32 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.7.DOUTPADOUTP from 8 bits to 4 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.7.DOUTPBDOUTP from 8 bits to 4 bits. 1683s Warning: Resizing cell port priority_memory.mem.0.7.WEBWE from 4 bits to 8 bits. 1688s Warning: Resizing cell port priority_memory.mem.0.0.BWE_A from 8 bits to 9 bits. 1688s Warning: Resizing cell port priority_memory.mem.0.0.BWE_B from 8 bits to 9 bits. 1703s Warning: Resizing cell port sp_write_first.mem.0.0.BWE_A from 8 bits to 9 bits. 1708s Warning: Resizing cell port sp_read_first.mem.0.0.BWE_B from 8 bits to 9 bits. 1708s Passed priority_memory.ys 1713s Passed shifter.ys 1718s Passed tribuf.ys 1723s Passed xilinx_dffopt.ys 1723s Passed xilinx_dsp.ys 1723s Passed xilinx_srl.ys 1733s Passed macc.sh 1743s Passed tribuf.sh 1743s make[1]: Leaving directory '/tmp/autopkgtest.qrrc6z/build.ei9/src/tests/arch/xilinx' 1743s cd tests/arch/ecp5 && bash run-test.sh "" 1743s make[1]: Entering directory '/tmp/autopkgtest.qrrc6z/build.ei9/src/tests/arch/ecp5' 1744s Passed add_sub.ys 1747s Passed adffs.ys 1748s Passed bug1459.ys 1749s Passed bug1598.ys 1749s Passed bug1630.ys 1749s Warning: Literal has a width of 16 bit, but value requires 184 bit. (<>>/,/<<>>/ {print $0}' 2287s + iverilog -o iverilog-initial_display initial_display.v 2287s + ./iverilog-initial_display 2287s + diff yosys-initial_display.log iverilog-initial_display.log 2287s + test_always_display clk -DEVENT_CLK 2287s + local subtest=clk 2287s + shift 2287s + ../../yosys -p 'read_verilog -DEVENT_CLK always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk-1.v 2287s 2287s /----------------------------------------------------------------------------\ 2287s | | 2287s | yosys -- Yosys Open SYnthesis Suite | 2287s | | 2287s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2287s | | 2287s | Permission to use, copy, modify, and/or distribute this software for any | 2287s | purpose with or without fee is hereby granted, provided that the above | 2287s | copyright notice and this permission notice appear in all copies. | 2287s | | 2287s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2287s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2287s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2287s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2287s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2287s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2287s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2287s | | 2287s \----------------------------------------------------------------------------/ 2287s 2287s Yosys 0.33 (git sha1 2584903a060) 2287s 2287s 2287s -- Running command `read_verilog -DEVENT_CLK always_display.v; proc; opt_expr -mux_bool; clean' -- 2287s 2287s 1. Executing Verilog-2005 frontend: always_display.v 2287s Parsing Verilog input from `always_display.v' to AST representation. 2287s Generating RTLIL representation for module `\m'. 2287s Successfully finished Verilog frontend. 2287s 2287s 2. Executing PROC pass (convert processes to netlists). 2287s 2287s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2287s Cleaned up 0 empty switches. 2287s 2287s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2287s Removed a total of 0 dead cases. 2287s 2287s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2287s Removed 1 redundant assignment. 2287s Promoted 1 assignment to connection. 2287s 2287s 2.4. Executing PROC_INIT pass (extract init attributes). 2287s 2287s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2287s 2287s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2287s Converted 0 switches. 2287s 2287s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2287s Creating decoders for process `\m.$proc$always_display.v:4$1'. 2287s 2287s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2287s 2287s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2287s 2287s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2287s 2287s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2287s Removing empty process `m.$proc$always_display.v:4$1'. 2287s Cleaned up 0 empty switches. 2287s 2287s 2.12. Executing OPT_EXPR pass (perform const folding). 2287s Optimizing module m. 2287s 2287s 3. Executing OPT_EXPR pass (perform const folding). 2287s Optimizing module m. 2287s Removed 0 unused cells and 1 unused wires. 2287s 2287s -- Writing to `yosys-always_display-clk-1.v' using backend `verilog' -- 2287s 2287s 4. Executing Verilog backend. 2287s 2287s 4.1. Executing BMUXMAP pass. 2287s 2287s 4.2. Executing DEMUXMAP pass. 2287s Dumping module `\m'. 2287s 2287s End of script. Logfile hash: 0de35d2746, CPU: user 0.01s system 0.00s, MEM: 10.00 MB peak 2287s Yosys 0.33 (git sha1 2584903a060) 2287s Time spent: 36% 2x opt_expr (0 sec), 24% 1x clean (0 sec), ... 2287s + ../../yosys -p 'read_verilog yosys-always_display-clk-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk-2.v 2287s 2287s /----------------------------------------------------------------------------\ 2287s | | 2287s | yosys -- Yosys Open SYnthesis Suite | 2287s | | 2287s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2287s | | 2287s | Permission to use, copy, modify, and/or distribute this software for any | 2287s | purpose with or without fee is hereby granted, provided that the above | 2287s | copyright notice and this permission notice appear in all copies. | 2287s | | 2287s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2287s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2287s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2287s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2287s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2287s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2287s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2287s | | 2287s \----------------------------------------------------------------------------/ 2287s 2287s Yosys 0.33 (git sha1 2584903a060) 2287s 2287s 2287s -- Running command `read_verilog yosys-always_display-clk-1.v; proc; opt_expr -mux_bool; clean' -- 2287s 2287s 1. Executing Verilog-2005 frontend: yosys-always_display-clk-1.v 2287s Parsing Verilog input from `yosys-always_display-clk-1.v' to AST representation. 2287s Generating RTLIL representation for module `\m'. 2287s Successfully finished Verilog frontend. 2287s 2287s 2. Executing PROC pass (convert processes to netlists). 2287s 2287s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2287s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk-1.v:18$1'. 2287s Cleaned up 1 empty switch. 2287s 2287s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2287s Removed a total of 0 dead cases. 2287s 2287s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2287s Removed 1 redundant assignment. 2287s Promoted 1 assignment to connection. 2287s 2287s 2.4. Executing PROC_INIT pass (extract init attributes). 2287s 2287s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2287s 2287s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2287s Converted 0 switches. 2287s 2287s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2287s Creating decoders for process `\m.$proc$yosys-always_display-clk-1.v:18$1'. 2287s 2287s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2287s 2287s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2287s 2287s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2287s 2287s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2287s + diff yosys-always_display-clk-1.v yosys-always_display-clk-2.v 2287s + test_always_display clk_rst -DEVENT_CLK_RST 2287s + local subtest=clk_rst 2287s + shift 2287s + ../../yosys -p 'read_verilog -DEVENT_CLK_RST always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst-1.v 2287s Removing empty process `m.$proc$yosys-always_display-clk-1.v:18$1'. 2287s Cleaned up 0 empty switches. 2287s 2287s 2.12. Executing OPT_EXPR pass (perform const folding). 2287s Optimizing module m. 2287s 2287s 3. Executing OPT_EXPR pass (perform const folding). 2287s Optimizing module m. 2287s Removed 0 unused cells and 1 unused wires. 2287s 2287s -- Writing to `yosys-always_display-clk-2.v' using backend `verilog' -- 2287s 2287s 4. Executing Verilog backend. 2287s 2287s 4.1. Executing BMUXMAP pass. 2287s 2287s 4.2. Executing DEMUXMAP pass. 2287s Dumping module `\m'. 2287s 2287s End of script. Logfile hash: e35e8bb689, CPU: user 0.01s system 0.00s, MEM: 10.00 MB peak 2287s Yosys 0.33 (git sha1 2584903a060) 2287s Time spent: 35% 2x opt_expr (0 sec), 23% 1x clean (0 sec), ... 2287s 2287s /----------------------------------------------------------------------------\ 2287s | | 2287s | yosys -- Yosys Open SYnthesis Suite | 2287s | | 2287s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2287s | | 2287s | Permission to use, copy, modify, and/or distribute this software for any | 2287s | purpose with or without fee is hereby granted, provided that the above | 2287s | copyright notice and this permission notice appear in all copies. | 2287s | | 2287s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2287s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2287s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2287s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2287s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2287s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2287s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2287s | | 2287s \----------------------------------------------------------------------------/ 2287s 2287s Yosys 0.33 (git sha1 2584903a060) 2287s 2287s 2287s -- Running command `read_verilog -DEVENT_CLK_RST always_display.v; proc; opt_expr -mux_bool; clean' -- 2287s 2287s 1. Executing Verilog-2005 frontend: always_display.v 2287s Parsing Verilog input from `always_display.v' to AST representation. 2287s Generating RTLIL representation for module `\m'. 2287s Successfully finished Verilog frontend. 2287s 2287s 2. Executing PROC pass (convert processes to netlists). 2287s 2287s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2287s Cleaned up 0 empty switches. 2287s 2287s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2287s Removed a total of 0 dead cases. 2287s 2287s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2287s Removed 1 redundant assignment. 2287s Promoted 1 assignment to connection. 2287s 2287s 2.4. Executing PROC_INIT pass (extract init attributes). 2287s 2287s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2287s 2287s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2287s + ../../yosys -p 'read_verilog yosys-always_display-clk_rst-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst-2.v 2287s Converted 0 switches. 2287s 2287s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2287s Creating decoders for process `\m.$proc$always_display.v:7$1'. 2287s 2287s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2287s 2287s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2287s 2287s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2287s 2287s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2287s Removing empty process `m.$proc$always_display.v:7$1'. 2287s Cleaned up 0 empty switches. 2287s 2287s 2.12. Executing OPT_EXPR pass (perform const folding). 2287s Optimizing module m. 2287s 2287s 3. Executing OPT_EXPR pass (perform const folding). 2287s Optimizing module m. 2287s Removed 0 unused cells and 1 unused wires. 2287s 2287s -- Writing to `yosys-always_display-clk_rst-1.v' using backend `verilog' -- 2287s 2287s 4. Executing Verilog backend. 2287s 2287s 4.1. Executing BMUXMAP pass. 2287s 2287s 4.2. Executing DEMUXMAP pass. 2287s Dumping module `\m'. 2287s 2287s End of script. Logfile hash: c95608ddf0, CPU: user 0.01s system 0.00s, MEM: 10.00 MB peak 2287s Yosys 0.33 (git sha1 2584903a060) 2287s Time spent: 36% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ... 2287s 2287s /----------------------------------------------------------------------------\ 2287s | | 2287s | yosys -- Yosys Open SYnthesis Suite | 2287s | | 2287s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2287s | | 2287s | Permission to use, copy, modify, and/or distribute this software for any | 2287s | purpose with or without fee is hereby granted, provided that the above | 2287s | copyright notice and this permission notice appear in all copies. | 2287s | | 2287s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2287s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2287s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2287s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2287s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2287s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2287s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2287s | | 2287s \----------------------------------------------------------------------------/ 2287s 2287s Yosys 0.33 (git sha1 2584903a060) 2287s 2287s 2287s -- Running command `read_verilog yosys-always_display-clk_rst-1.v; proc; opt_expr -mux_bool; clean' -- 2287s 2287s 1. Executing Verilog-2005 frontend: yosys-always_display-clk_rst-1.v 2287s Parsing Verilog input from `yosys-always_display-clk_rst-1.v' to AST representation. 2287s Generating RTLIL representation for module `\m'. 2287s Successfully finished Verilog frontend. 2287s 2287s 2. Executing PROC pass (convert processes to netlists). 2287s 2287s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2287s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_rst-1.v:18$1'. 2287s Cleaned up 1 empty switch. 2287s 2287s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2287s + diff yosys-always_display-clk_rst-1.v yosys-always_display-clk_rst-2.v 2287s + test_always_display star -DEVENT_STAR 2287s + local subtest=star 2287s + shift 2287s + ../../yosys -p 'read_verilog -DEVENT_STAR always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star-1.v 2287s Removed a total of 0 dead cases. 2287s 2287s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2287s Removed 1 redundant assignment. 2287s Promoted 1 assignment to connection. 2287s 2287s 2.4. Executing PROC_INIT pass (extract init attributes). 2287s 2287s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2287s 2287s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2287s Converted 0 switches. 2287s 2287s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2287s Creating decoders for process `\m.$proc$yosys-always_display-clk_rst-1.v:18$1'. 2287s 2287s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2287s 2287s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2287s 2287s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2287s 2287s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2287s Removing empty process `m.$proc$yosys-always_display-clk_rst-1.v:18$1'. 2287s Cleaned up 0 empty switches. 2287s 2287s 2.12. Executing OPT_EXPR pass (perform const folding). 2287s Optimizing module m. 2287s 2287s 3. Executing OPT_EXPR pass (perform const folding). 2287s Optimizing module m. 2287s Removed 0 unused cells and 1 unused wires. 2287s 2287s -- Writing to `yosys-always_display-clk_rst-2.v' using backend `verilog' -- 2287s 2287s 4. Executing Verilog backend. 2287s 2287s 4.1. Executing BMUXMAP pass. 2287s 2287s 4.2. Executing DEMUXMAP pass. 2287s Dumping module `\m'. 2287s 2287s End of script. Logfile hash: faf50513c3, CPU: user 0.01s system 0.00s, MEM: 10.00 MB peak 2287s Yosys 0.33 (git sha1 2584903a060) 2287s Time spent: 33% 2x opt_expr (0 sec), 23% 1x clean (0 sec), ... 2287s 2287s /----------------------------------------------------------------------------\ 2287s | | 2287s | yosys -- Yosys Open SYnthesis Suite | 2287s | | 2287s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2287s | | 2287s | Permission to use, copy, modify, and/or distribute this software for any | 2287s | purpose with or without fee is hereby granted, provided that the above | 2287s | copyright notice and this permission notice appear in all copies. | 2287s | | 2287s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2287s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2287s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2287s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2287s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2287s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2287s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2287s | | 2287s \----------------------------------------------------------------------------/ 2287s 2287s Yosys 0.33 (git sha1 2584903a060) 2287s 2287s 2287s -- Running command `read_verilog -DEVENT_STAR always_display.v; proc; opt_expr -mux_bool; clean' -- 2287s 2287s 1. Executing Verilog-2005 frontend: always_display.v 2287s Parsing Verilog input from `always_display.v' to AST representation. 2287s Generating RTLIL representation for module `\m'. 2287s Successfully finished Verilog frontend. 2287s 2287s 2. Executing PROC pass (convert processes to netlists). 2287s + ../../yosys -p 'read_verilog yosys-always_display-star-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star-2.v 2287s + diff yosys-always_display-star-1.v yosys-always_display-star-2.v 2287s + test_always_display clk_en -DEVENT_CLK -DCOND_EN 2287s + local subtest=clk_en 2287s + shift 2287s + ../../yosys -p 'read_verilog -DEVENT_CLK -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_en-1.v 2287s 2287s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2287s Cleaned up 0 empty switches. 2287s 2287s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2287s Removed a total of 0 dead cases. 2287s 2287s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2287s Removed 1 redundant assignment. 2287s Promoted 1 assignment to connection. 2287s 2287s 2.4. Executing PROC_INIT pass (extract init attributes). 2287s 2287s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2287s 2287s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2287s Converted 0 switches. 2287s 2287s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2287s Creating decoders for process `\m.$proc$always_display.v:10$1'. 2287s 2287s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2287s 2287s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2287s 2287s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2287s 2287s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2287s Removing empty process `m.$proc$always_display.v:10$1'. 2287s Cleaned up 0 empty switches. 2287s 2287s 2.12. Executing OPT_EXPR pass (perform const folding). 2287s Optimizing module m. 2287s 2287s 3. Executing OPT_EXPR pass (perform const folding). 2287s Optimizing module m. 2287s Removed 0 unused cells and 1 unused wires. 2287s 2287s -- Writing to `yosys-always_display-star-1.v' using backend `verilog' -- 2287s 2287s 4. Executing Verilog backend. 2287s 2287s 4.1. Executing BMUXMAP pass. 2287s 2287s 4.2. Executing DEMUXMAP pass. 2287s Dumping module `\m'. 2287s 2287s End of script. Logfile hash: 7b2c5274a5, CPU: user 0.01s system 0.00s, MEM: 10.00 MB peak 2287s Yosys 0.33 (git sha1 2584903a060) 2287s Time spent: 36% 2x opt_expr (0 sec), 25% 1x clean (0 sec), ... 2287s 2287s /----------------------------------------------------------------------------\ 2287s | | 2287s | yosys -- Yosys Open SYnthesis Suite | 2287s | | 2287s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2287s | | 2287s | Permission to use, copy, modify, and/or distribute this software for any | 2287s | purpose with or without fee is hereby granted, provided that the above | 2287s | copyright notice and this permission notice appear in all copies. | 2287s | | 2287s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2287s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2287s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2287s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2287s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2287s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2287s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2287s | | 2287s \----------------------------------------------------------------------------/ 2287s 2287s Yosys 0.33 (git sha1 2584903a060) 2287s 2287s 2287s -- Running command `read_verilog yosys-always_display-star-1.v; proc; opt_expr -mux_bool; clean' -- 2287s 2287s 1. Executing Verilog-2005 frontend: yosys-always_display-star-1.v 2287s Parsing Verilog input from `yosys-always_display-star-1.v' to AST representation. 2287s Generating RTLIL representation for module `\m'. 2287s Successfully finished Verilog frontend. 2287s 2287s 2. Executing PROC pass (convert processes to netlists). 2287s 2287s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2287s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-star-1.v:18$1'. 2287s Cleaned up 1 empty switch. 2287s 2287s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2287s Removed a total of 0 dead cases. 2287s 2287s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2287s Removed 1 redundant assignment. 2287s Promoted 1 assignment to connection. 2287s 2287s 2.4. Executing PROC_INIT pass (extract init attributes). 2287s 2287s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2287s 2287s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2287s Converted 0 switches. 2287s 2287s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2287s Creating decoders for process `\m.$proc$yosys-always_display-star-1.v:18$1'. 2287s 2287s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2287s 2287s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2287s 2287s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2287s 2287s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2287s Removing empty process `m.$proc$yosys-always_display-star-1.v:18$1'. 2287s Cleaned up 0 empty switches. 2287s 2287s 2.12. Executing OPT_EXPR pass (perform const folding). 2287s Optimizing module m. 2287s 2287s 3. Executing OPT_EXPR pass (perform const folding). 2287s Optimizing module m. 2287s Removed 0 unused cells and 1 unused wires. 2287s 2287s -- Writing to `yosys-always_display-star-2.v' using backend `verilog' -- 2287s 2287s 4. Executing Verilog backend. 2287s 2287s 4.1. Executing BMUXMAP pass. 2287s 2287s 4.2. Executing DEMUXMAP pass. 2287s Dumping module `\m'. 2287s 2287s End of script. Logfile hash: 8979c5de0b, CPU: user 0.01s system 0.00s, MEM: 10.00 MB peak 2287s Yosys 0.33 (git sha1 2584903a060) 2287s Time spent: 35% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ... 2287s + ../../yosys -p 'read_verilog yosys-always_display-clk_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_en-2.v 2287s 2287s /----------------------------------------------------------------------------\ 2287s | | 2287s | yosys -- Yosys Open SYnthesis Suite | 2287s | | 2287s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2287s | | 2287s | Permission to use, copy, modify, and/or distribute this software for any | 2287s | purpose with or without fee is hereby granted, provided that the above | 2287s | copyright notice and this permission notice appear in all copies. | 2287s | | 2287s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2287s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2287s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2287s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2287s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2287s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2287s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2287s | | 2287s \----------------------------------------------------------------------------/ 2287s 2287s Yosys 0.33 (git sha1 2584903a060) 2287s 2287s 2287s -- Running command `read_verilog -DEVENT_CLK -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -- 2287s 2287s 1. Executing Verilog-2005 frontend: always_display.v 2287s Parsing Verilog input from `always_display.v' to AST representation. 2287s Generating RTLIL representation for module `\m'. 2287s Successfully finished Verilog frontend. 2287s 2287s 2. Executing PROC pass (convert processes to netlists). 2287s 2287s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2287s Cleaned up 0 empty switches. 2287s 2287s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2287s Removed a total of 0 dead cases. 2287s 2287s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2287s Removed 0 redundant assignments. 2287s Promoted 0 assignments to connections. 2287s 2287s 2.4. Executing PROC_INIT pass (extract init attributes). 2287s 2287s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2287s 2287s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2287s Converted 0 switches. 2287s 2287s 2287s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2287s Creating decoders for process `\m.$proc$always_display.v:4$1'. 2287s 1/1: $display$always_display.v:15$2_EN 2287s 2287s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2287s 2287s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2287s 2287s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2287s 2287s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2287s Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:4$1'. 2287s Removing empty process `m.$proc$always_display.v:4$1'. 2287s Cleaned up 1 empty switch. 2287s 2287s 2.12. Executing OPT_EXPR pass (perform const folding). 2287s Optimizing module m. 2287s 2287s 3. Executing OPT_EXPR pass (perform const folding). 2287s Optimizing module m. 2287s 2287s Removed 0 unused cells and 3 unused wires. 2287s 2287s -- Writing to `yosys-always_display-clk_en-1.v' using backend `verilog' -- 2287s 2287s 4. Executing Verilog backend. 2287s 2287s 4.1. Executing BMUXMAP pass. 2287s 2287s 4.2. Executing DEMUXMAP pass. 2287s Dumping module `\m'. 2287s 2287s End of script. Logfile hash: 4f8a3b339c, CPU: user 0.01s system 0.00s, MEM: 12.00 MB peak 2287s Yosys 0.33 (git sha1 2584903a060) 2287s Time spent: 38% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ... 2287s 2287s /----------------------------------------------------------------------------\ 2287s | | 2287s | yosys -- Yosys Open SYnthesis Suite | 2287s | | 2287s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2287s | | 2287s | Permission to use, copy, modify, and/or distribute this software for any | 2287s | purpose with or without fee is hereby granted, provided that the above | 2287s | copyright notice and this permission notice appear in all copies. | 2287s | | 2287s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2287s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2287s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2287s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2287s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2287s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2287s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2287s | | 2287s \----------------------------------------------------------------------------/ 2287s 2287s Yosys 0.33 (git sha1 2584903a060) 2287s 2287s 2287s -- Running command `read_verilog yosys-always_display-clk_en-1.v; proc; opt_expr -mux_bool; clean' -- 2287s 2287s 1. Executing Verilog-2005 frontend: yosys-always_display-clk_en-1.v 2287s Parsing Verilog input from `yosys-always_display-clk_en-1.v' to AST representation. 2287s Generating RTLIL representation for module `\m'. 2287s Successfully finished Verilog frontend. 2287s 2287s 2. Executing PROC pass (convert processes to netlists). 2287s 2287s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2287s Cleaned up 0 empty switches. 2287s 2287s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2287s Removed a total of 0 dead cases. 2287s 2287s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2287s Removed 0 redundant assignments. 2287s Promoted 0 assignments to connections. 2287s 2287s 2.4. Executing PROC_INIT pass (extract init attributes). 2287s 2287s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2287s 2287s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2287s Converted 0 switches. 2287s 2287s 2287s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2287s Creating decoders for process `\m.$proc$yosys-always_display-clk_en-1.v:18$1'. 2287s 1/1: $write$yosys-always_display-clk_en-1.v:20$2_EN 2287s 2287s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2287s 2287s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2287s 2287s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2287s 2287s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2287s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_en-1.v:18$1'. 2287s Removing empty process `m.$proc$yosys-always_display-clk_en-1.v:18$1'. 2287s Cleaned up 1 empty switch. 2287s 2287s 2.12. Executing OPT_EXPR pass (perform const folding). 2287s Optimizing module m. 2287s 2287s 3. Executing OPT_EXPR pass (perform const folding). 2287s Optimizing module m. 2287s 2287s Removed 0 unused cells and 3 unused wires. 2287s 2287s -- Writing to `yosys-always_display-clk_en-2.v' using backend `verilog' -- 2287s 2287s 4. Executing Verilog backend. 2287s 2287s 4.1. Executing BMUXMAP pass. 2287s 2287s 4.2. Executing DEMUXMAP pass. 2287s Dumping module `\m'. 2287s 2287s End of script. Logfile hash: 51e7fa3902, CPU: user 0.01s system 0.00s, MEM: 12.00 MB peak 2287s Yosys 0.33 (git sha1 2584903a060) 2287s Time spent: 36% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ... 2287s 2287s /----------------------------------------------------------------------------\ 2287s | | 2287s | yosys -- Yosys Open SYnthesis Suite | 2287s | | 2287s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2287s | | 2287s | Permission to use, copy, modify, and/or distribute this software for any | 2287s | purpose with or without fee is hereby granted, provided that the above | 2287s | copyright notice and this permission notice appear in all copies. | 2287s | | 2287s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2287s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2287s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2287s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2287s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2287s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2287s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2287s | | 2287s \----------------------------------------------------------------------------/ 2287s 2287s Yosys 0.33 (git sha1 2584903a060) 2287s 2287s 2287s -- Running command `read_verilog -DEVENT_CLK_RST -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -- 2287s 2287s 1. Executing Verilog-2005 frontend: always_display.v 2287s Parsing Verilog input from `always_display.v' to AST representation. 2287s Generating RTLIL representation for module `\m'. 2287s Successfully finished Verilog frontend. 2287s 2287s 2. Executing PROC pass (convert processes to netlists). 2287s 2287s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2287s Cleaned up 0 empty switches. 2287s 2287s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2287s Removed a total of 0 dead cases. 2287s 2287s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2287s Removed 0 redundant assignments. 2287s Promoted 0 assignments to connections. 2287s 2287s 2.4. Executing PROC_INIT pass (extract init attributes). 2287s 2287s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2287s 2287s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2287s Converted 0 switches. 2287s 2287s 2287s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2287s Creating decoders for process `\m.$proc$always_display.v:7$1'. 2287s 1/1: $display$always_display.v:15$2_EN 2287s 2287s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2287s 2287s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2287s 2287s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2287s 2287s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2287s + diff yosys-always_display-clk_en-1.v yosys-always_display-clk_en-2.v 2287s + test_always_display clk_rst_en -DEVENT_CLK_RST -DCOND_EN 2287s + local subtest=clk_rst_en 2287s + shift 2287s + ../../yosys -p 'read_verilog -DEVENT_CLK_RST -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst_en-1.v 2287s + ../../yosys -p 'read_verilog yosys-always_display-clk_rst_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst_en-2.v 2287s + diff yosys-always_display-clk_rst_en-1.v yosys-always_display-clk_rst_en-2.v 2287s + test_always_display star_en -DEVENT_STAR -DCOND_EN 2287s + local subtest=star_en 2287s + shift 2287s Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:7$1'. 2287s Removing empty process `m.$proc$always_display.v:7$1'. 2287s Cleaned up 1 empty switch. 2287s 2287s 2.12. Executing OPT_EXPR pass (perform const folding). 2287s Optimizing module m. 2287s 2287s 3. Executing OPT_EXPR pass (perform const folding). 2287s Optimizing module m. 2287s 2287s Removed 0 unused cells and 3 unused wires. 2287s 2287s -- Writing to `yosys-always_display-clk_rst_en-1.v' using backend `verilog' -- 2287s 2287s 4. Executing Verilog backend. 2287s 2287s 4.1. Executing BMUXMAP pass. 2287s 2287s 4.2. Executing DEMUXMAP pass. 2287s Dumping module `\m'. 2287s 2287s End of script. Logfile hash: f9b4876f33, CPU: user 0.01s system 0.00s, MEM: 12.00 MB peak 2287s Yosys 0.33 (git sha1 2584903a060) 2287s Time spent: 38% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ... 2287s 2287s /----------------------------------------------------------------------------\ 2287s | | 2287s | yosys -- Yosys Open SYnthesis Suite | 2287s | | 2287s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2287s | | 2287s | Permission to use, copy, modify, and/or distribute this software for any | 2287s | purpose with or without fee is hereby granted, provided that the above | 2287s | copyright notice and this permission notice appear in all copies. | 2287s | | 2287s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2287s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2287s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2287s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2287s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2287s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2287s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2287s | | 2287s \----------------------------------------------------------------------------/ 2287s 2287s Yosys 0.33 (git sha1 2584903a060) 2287s 2287s 2287s -- Running command `read_verilog yosys-always_display-clk_rst_en-1.v; proc; opt_expr -mux_bool; clean' -- 2287s 2287s 1. Executing Verilog-2005 frontend: yosys-always_display-clk_rst_en-1.v 2287s Parsing Verilog input from `yosys-always_display-clk_rst_en-1.v' to AST representation. 2287s Generating RTLIL representation for module `\m'. 2287s Successfully finished Verilog frontend. 2287s 2287s 2. Executing PROC pass (convert processes to netlists). 2287s 2287s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2287s Cleaned up 0 empty switches. 2287s 2287s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2287s Removed a total of 0 dead cases. 2287s 2287s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2287s Removed 0 redundant assignments. 2287s Promoted 0 assignments to connections. 2287s 2287s 2.4. Executing PROC_INIT pass (extract init attributes). 2287s 2287s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2287s 2287s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2287s Converted 0 switches. 2287s 2287s 2287s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2287s Creating decoders for process `\m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'. 2287s 1/1: $write$yosys-always_display-clk_rst_en-1.v:20$2_EN 2287s 2287s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2287s 2287s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2287s 2287s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2287s 2287s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2287s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'. 2287s Removing empty process `m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'. 2287s Cleaned up 1 empty switch. 2287s 2287s 2.12. Executing OPT_EXPR pass (perform const folding). 2287s Optimizing module m. 2287s 2287s 3. Executing OPT_EXPR pass (perform const folding). 2287s Optimizing module m. 2287s 2287s Removed 0 unused cells and 3 unused wires. 2287s 2287s -- Writing to `yosys-always_display-clk_rst_en-2.v' using backend `verilog' -- 2287s 2287s 4. Executing Verilog backend. 2287s 2287s 4.1. Executing BMUXMAP pass. 2287s 2287s 4.2. Executing DEMUXMAP pass. 2287s Dumping module `\m'. 2287s 2287s End of script. Logfile hash: 0c4b4eaa9c, CPU: user 0.00s system 0.01s, MEM: 12.00 MB peak 2287s Yosys 0.33 (git sha1 2584903a060) 2287s Time spent: 38% 2x opt_expr (0 sec), 21% 1x clean (0 sec), ... 2287s 2287s /----------------------------------------------------------------------------\ 2287s | | 2287s | yosys -- Yosys Open SYnthesis Suite | 2287s | | 2287s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2287s | | 2287s | Permission to use, copy, modify, and/or distribute this software for any | 2287s | purpose with or without fee is hereby granted, provided that the above | 2287s | copyright notice and this permission notice appear in all copies. | 2287s | | 2287s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2287s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2287s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2287s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2287s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2287s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2287s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2287s | | 2287s \----------------------------------------------------------------------------/ 2287s 2287s Yosys 0.33 (git sha1 2584903a060) 2287s 2287s 2287s -- Running command `read_verilog -DEVENT_STAR -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -- 2287s 2287s 1. Executing Verilog-2005 frontend: always_display.v 2287s Parsing Verilog input from `always_display.v' to AST representation. 2287s Generating RTLIL representation for module `\m'. 2287s Successfully finished Verilog frontend. 2287s 2287s 2. Executing PROC pass (convert processes to netlists). 2287s 2287s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2287s Cleaned up 0 empty switches. 2287s 2287s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2287s Removed a total of 0 dead cases. 2287s 2287s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2287s Removed 0 redundant assignments. 2287s Promoted 0 assignments to connections. 2287s 2287s 2.4. Executing PROC_INIT pass (extract init attributes). 2287s 2287s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2287s 2287s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2287s Converted 0 switches. 2287s 2287s 2287s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2287s Creating decoders for process `\m.$proc$always_display.v:10$1'. 2287s 1/1: $display$always_display.v:15$2_EN 2287s 2287s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2287s 2287s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2287s 2287s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2287s 2287s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2287s Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:10$1'. 2287s Removing empty process `m.$proc$always_display.v:10$1'. 2287s Cleaned up 1 empty switch. 2287s 2287s 2.12. Executing OPT_EXPR pass (perform const folding). 2287s Optimizing module m. 2287s 2287s 3. Executing OPT_EXPR pass (perform const folding). 2287s Optimizing module m. 2287s 2287s Removed 0 unused cells and 3 unused wires. 2287s 2287s -- Writing to `yosys-always_display-star_en-1.v' using backend `verilog' -- 2287s 2287s 4. Executing Verilog backend. 2287s 2287s 4.1. Executing BMUXMAP pass. 2287s 2287s 4.2. Executing DEMUXMAP pass. 2287s Dumping module `\m'. 2287s 2287s End of script. Logfile hash: d6a7335726, CPU: user 0.01s system 0.00s, MEM: 10.00 MB peak 2287s Yosys 0.33 (git sha1 2584903a060) 2287s Time spent: 38% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ... 2287s 2287s /----------------------------------------------------------------------------\ 2287s | | 2287s | yosys -- Yosys Open SYnthesis Suite | 2287s | | 2287s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2287s | | 2287s | Permission to use, copy, modify, and/or distribute this software for any | 2287s | purpose with or without fee is hereby granted, provided that the above | 2287s | copyright notice and this permission notice appear in all copies. | 2287s | | 2287s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2287s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2287s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2287s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2287s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2287s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2287s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2287s | | 2287s \----------------------------------------------------------------------------/ 2287s 2287s Yosys 0.33 (git sha1 2584903a060) 2287s 2287s 2287s -- Running command `read_verilog yosys-always_display-star_en-1.v; proc; opt_expr -mux_bool; clean' -- 2287s 2287s 1. Executing Verilog-2005 frontend: yosys-always_display-star_en-1.v 2287s Parsing Verilog input from `yosys-always_display-star_en-1.v' to AST representation. 2287s Generating RTLIL representation for module `\m'. 2287s Successfully finished Verilog frontend. 2287s 2287s 2. Executing PROC pass (convert processes to netlists). 2287s 2287s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2287s Cleaned up 0 empty switches. 2287s 2287s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2287s Removed a total of 0 dead cases. 2287s 2287s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2287s Removed 0 redundant assignments. 2287s Promoted 0 assignments to connections. 2287s 2287s 2.4. Executing PROC_INIT pass (extract init attributes). 2287s 2287s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2287s 2287s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2287s Converted 0 switches. 2287s 2287s 2287s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2287s Creating decoders for process `\m.$proc$yosys-always_display-star_en-1.v:18$1'. 2287s 1/1: $write$yosys-always_display-star_en-1.v:20$2_EN 2287s 2287s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2287s 2287s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2287s 2287s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2287s 2287s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2287s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-star_en-1.v:18$1'. 2287s Removing empty process `m.$proc$yosys-always_display-star_en-1.v:18$1'. 2287s Cleaned up 1 empty switch. 2287s 2287s 2.12. Executing OPT_EXPR pass (perform const folding). 2287s Optimizing module m. 2287s 2287s 3. Executing OPT_EXPR pass (perform const folding). 2287s + ../../yosys -p 'read_verilog -DEVENT_STAR -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star_en-1.v 2287s + ../../yosys -p 'read_verilog yosys-always_display-star_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star_en-2.v 2287s + diff yosys-always_display-star_en-1.v yosys-always_display-star_en-2.v 2287s + test_roundtrip dec_unsigned -DBASE_DEC -DSIGN= 2287s + local subtest=dec_unsigned 2287s + shift 2287s + ../../yosys -p 'read_verilog -DBASE_DEC -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-dec_unsigned-1.v 2287s Optimizing module m. 2287s 2287s Removed 0 unused cells and 3 unused wires. 2287s 2287s -- Writing to `yosys-always_display-star_en-2.v' using backend `verilog' -- 2287s 2287s 4. Executing Verilog backend. 2287s 2287s 4.1. Executing BMUXMAP pass. 2287s 2287s 4.2. Executing DEMUXMAP pass. 2287s Dumping module `\m'. 2287s 2287s End of script. Logfile hash: 18895a2046, CPU: user 0.00s system 0.01s, MEM: 10.00 MB peak 2287s Yosys 0.33 (git sha1 2584903a060) 2287s Time spent: 37% 2x opt_expr (0 sec), 21% 1x clean (0 sec), ... 2287s + ../../yosys -p 'read_verilog yosys-roundtrip-dec_unsigned-1.v; proc; clean' -o yosys-roundtrip-dec_unsigned-2.v 2287s 2287s /----------------------------------------------------------------------------\ 2287s | | 2287s | yosys -- Yosys Open SYnthesis Suite | 2287s | | 2287s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2287s | | 2287s | Permission to use, copy, modify, and/or distribute this software for any | 2287s | purpose with or without fee is hereby granted, provided that the above | 2287s | copyright notice and this permission notice appear in all copies. | 2287s | | 2287s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2287s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2287s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2287s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2287s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2287s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2287s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2287s | | 2287s \----------------------------------------------------------------------------/ 2287s 2287s Yosys 0.33 (git sha1 2584903a060) 2287s 2287s 2287s -- Running command `read_verilog -DBASE_DEC -DSIGN= roundtrip.v; proc; clean' -- 2287s 2287s 1. Executing Verilog-2005 frontend: roundtrip.v 2287s Parsing Verilog input from `roundtrip.v' to AST representation. 2287s Generating RTLIL representation for module `\m'. 2287s Successfully finished Verilog frontend. 2287s 2287s 2. Executing PROC pass (convert processes to netlists). 2287s 2287s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2287s Cleaned up 0 empty switches. 2287s 2287s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2287s Removed a total of 0 dead cases. 2287s 2287s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2287s Removed 1 redundant assignment. 2287s Promoted 1 assignment to connection. 2287s 2287s 2.4. Executing PROC_INIT pass (extract init attributes). 2287s 2287s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2287s 2287s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2287s Converted 0 switches. 2287s 2287s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2287s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2287s 2287s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2287s 2287s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2287s 2287s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2287s 2287s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2287s Removing empty process `m.$proc$roundtrip.v:3$1'. 2287s Cleaned up 0 empty switches. 2287s 2287s 2.12. Executing OPT_EXPR pass (perform const folding). 2287s Optimizing module m. 2287s Removed 0 unused cells and 1 unused wires. 2287s 2287s -- Writing to `yosys-roundtrip-dec_unsigned-1.v' using backend `verilog' -- 2287s 2287s 3. Executing Verilog backend. 2287s 2287s 3.1. Executing BMUXMAP pass. 2287s 2287s 3.2. Executing DEMUXMAP pass. 2287s Dumping module `\m'. 2287s 2287s End of script. Logfile hash: bfb187b86d, CPU: user 0.00s system 0.00s, MEM: 10.00 MB peak 2287s Yosys 0.33 (git sha1 2584903a060) 2287s Time spent: 29% 1x clean (0 sec), 19% 1x opt_expr (0 sec), ... 2288s 2288s /----------------------------------------------------------------------------\ 2288s | | 2288s | yosys -- Yosys Open SYnthesis Suite | 2288s | | 2288s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2288s | | 2288s | Permission to use, copy, modify, and/or distribute this software for any | 2288s | purpose with or without fee is hereby granted, provided that the above | 2288s | copyright notice and this permission notice appear in all copies. | 2288s | | 2288s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2288s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2288s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2288s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2288s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2288s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2288s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2288s | | 2288s \----------------------------------------------------------------------------/ 2288s 2288s Yosys 0.33 (git sha1 2584903a060) 2288s 2288s 2288s -- Running command `read_verilog yosys-roundtrip-dec_unsigned-1.v; proc; clean' -- 2288s 2288s 1. Executing Verilog-2005 frontend: yosys-roundtrip-dec_unsigned-1.v 2288s Parsing Verilog input from `yosys-roundtrip-dec_unsigned-1.v' to AST representation. 2288s Generating RTLIL representation for module `\m'. 2288s Successfully finished Verilog frontend. 2288s 2288s 2. Executing PROC pass (convert processes to netlists). 2288s 2288s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2288s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'. 2288s Cleaned up 1 empty switch. 2288s 2288s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2288s Removed a total of 0 dead cases. 2288s 2288s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2288s Removed 1 redundant assignment. 2288s Promoted 1 assignment to connection. 2288s 2288s 2.4. Executing PROC_INIT pass (extract init attributes). 2288s 2288s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2288s 2288s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2288s Converted 0 switches. 2288s 2288s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2288s Creating decoders for process `\m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'. 2288s 2288s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2288s 2288s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2288s 2288s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2288s 2288s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2288s Removing empty process `m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'. 2288s Cleaned up 0 empty switches. 2288s 2288s 2.12. Executing OPT_EXPR pass (perform const folding). 2288s Optimizing module m. 2288s Removed 0 unused cells and 1 unused wires. 2288s 2288s -- Writing to `yosys-roundtrip-dec_unsigned-2.v' using backend `verilog' -- 2288s 2288s 3. Executing Verilog backend. 2288s 2288s 3.1. Executing BMUXMAP pass. 2288s 2288s 3.2. Executing DEMUXMAP pass. 2288s Dumping module `\m'. 2288s 2288s End of script. Logfile hash: 4be9539e85, CPU: user 0.01s system 0.00s, MEM: 10.00 MB peak 2288s Yosys 0.33 (git sha1 2584903a060) 2288s Time spent: 29% 1x clean (0 sec), 18% 1x opt_expr (0 sec), ... 2288s 2288s /----------------------------------------------------------------------------\ 2288s | | 2288s | yosys -- Yosys Open SYnthesis Suite | 2288s | | 2288s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2288s | | 2288s | Permission to use, copy, modify, and/or distribute this software for any | 2288s | purpose with or without fee is hereby granted, provided that the above | 2288s | copyright notice and this permission notice appear in all copies. | 2288s | | 2288s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2288s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2288s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2288s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2288s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2288s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2288s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2288s | | 2288s \----------------------------------------------------------------------------/ 2288s 2288s Yosys 0.33 (git sha1 2584903a060) 2288s 2288s 2288s -- Running command `read_verilog -DBASE_DEC -DSIGN=signed roundtrip.v; proc; clean' -- 2288s 2288s 1. Executing Verilog-2005 frontend: roundtrip.v 2288s Parsing Verilog input from `roundtrip.v' to AST representation. 2288s Generating RTLIL representation for module `\m'. 2288s Successfully finished Verilog frontend. 2288s 2288s 2. Executing PROC pass (convert processes to netlists). 2288s 2288s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2288s Cleaned up 0 empty switches. 2288s 2288s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2288s Removed a total of 0 dead cases. 2288s 2288s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2288s Removed 1 redundant assignment. 2288s Promoted 1 assignment to connection. 2288s 2288s 2.4. Executing PROC_INIT pass (extract init attributes). 2288s 2288s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2288s 2288s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2288s Converted 0 switches. 2288s 2288s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2288s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2288s 2288s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2288s 2288s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2288s 2288s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2288s 2288s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2288s Removing empty process `m.$proc$roundtrip.v:3$1'. 2288s Cleaned up 0 empty switches. 2288s 2288s 2.12. Executing OPT_EXPR pass (perform const folding). 2288s Optimizing module m. 2288s Removed 0 unused cells and 1 unused wires. 2288s 2288s -- Writing to `yosys-roundtrip-dec_signed-1.v' using backend `verilog' -- 2288s 2288s 3. Executing Verilog backend. 2288s 2288s 3.1. Executing BMUXMAP pass. 2288s 2288s 3.2. Executing DEMUXMAP pass. 2288s Dumping module `\m'. 2288s 2288s End of script. Logfile hash: bbdfa5ca92, CPU: user 0.00s system 0.00s, MEM: 10.00 MB peak 2288s Yosys 0.33 (git sha1 2584903a060) 2288s Time spent: 29% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 2288s 2288s /----------------------------------------------------------------------------\ 2288s | | 2288s | yosys -- Yosys Open SYnthesis Suite | 2288s | | 2288s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2288s | | 2288s | Permission to use, copy, modify, and/or distribute this software for any | 2288s | purpose with or without fee is hereby granted, provided that the above | 2288s | copyright notice and this permission notice appear in all copies. | 2288s | | 2288s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2288s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2288s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2288s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2288s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2288s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2288s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2288s | | 2288s \----------------------------------------------------------------------------/ 2288s 2288s Yosys 0.33 (git sha1 2584903a060) 2288s 2288s 2288s -- Running command `read_verilog yosys-roundtrip-dec_signed-1.v; proc; clean' -- 2288s 2288s 1. Executing Verilog-2005 frontend: yosys-roundtrip-dec_signed-1.v 2288s Parsing Verilog input from `yosys-roundtrip-dec_signed-1.v' to AST representation. 2288s Generating RTLIL representation for module `\m'. 2288s Successfully finished Verilog frontend. 2288s 2288s 2. Executing PROC pass (convert processes to netlists). 2288s 2288s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2288s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'. 2288s Cleaned up 1 empty switch. 2288s 2288s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2288s Removed a total of 0 dead cases. 2288s 2288s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2288s Removed 1 redundant assignment. 2288s Promoted 1 assignment to connection. 2288s 2288s 2.4. Executing PROC_INIT pass (extract init attributes). 2288s 2288s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2288s 2288s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2288s Converted 0 switches. 2288s 2288s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2288s Creating decoders for process `\m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'. 2288s 2288s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2288s 2288s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2288s 2288s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2288s 2288s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2288s Removing empty process `m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'. 2288s Cleaned up 0 empty switches. 2288s 2288s 2.12. Executing OPT_EXPR pass (perform const folding). 2288s Optimizing module m. 2288s Removed 0 unused cells and 1 unused wires. 2288s 2288s -- Writing to `yosys-roundtrip-dec_signed-2.v' using backend `verilog' -- 2288s 2288s 3. Executing Verilog backend. 2288s 2288s 3.1. Executing BMUXMAP pass. 2288s 2288s 3.2. Executing DEMUXMAP pass. 2288s Dumping module `\m'. 2288s 2288s End of script. Logfile hash: b233de92a6, CPU: user 0.00s system 0.01s, MEM: 10.00 MB peak 2288s Yosys 0.33 (git sha1 2584903a060) 2288s Time spent: 29% 1x clean (0 sec), 19% 1x opt_expr (0 sec), ... 2288s + diff yosys-roundtrip-dec_unsigned-1.v yosys-roundtrip-dec_unsigned-2.v 2288s + iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned roundtrip.v roundtrip_tb.v 2288s + ./iverilog-roundtrip-dec_unsigned 2288s + iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned-1 yosys-roundtrip-dec_unsigned-1.v roundtrip_tb.v 2288s + ./iverilog-roundtrip-dec_unsigned-1 2288s + iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned-2 yosys-roundtrip-dec_unsigned-2.v roundtrip_tb.v 2288s + ./iverilog-roundtrip-dec_unsigned-1 2288s + diff iverilog-roundtrip-dec_unsigned.log iverilog-roundtrip-dec_unsigned-1.log 2288s + diff iverilog-roundtrip-dec_unsigned-1.log iverilog-roundtrip-dec_unsigned-2.log 2288s + test_roundtrip dec_signed -DBASE_DEC -DSIGN=signed 2288s + local subtest=dec_signed 2288s + shift 2288s + ../../yosys -p 'read_verilog -DBASE_DEC -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-dec_signed-1.v 2288s + ../../yosys -p 'read_verilog yosys-roundtrip-dec_signed-1.v; proc; clean' -o yosys-roundtrip-dec_signed-2.v 2288s + diff yosys-roundtrip-dec_signed-1.v yosys-roundtrip-dec_signed-2.v 2288s 2288s /----------------------------------------------------------------------------\ 2288s | | 2288s | yosys -- Yosys Open SYnthesis Suite | 2288s | | 2288s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2288s | | 2288s | Permission to use, copy, modify, and/or distribute this software for any | 2288s | purpose with or without fee is hereby granted, provided that the above | 2288s | copyright notice and this permission notice appear in all copies. | 2288s | | 2288s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2288s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2288s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2288s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2288s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2288s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2288s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2288s | | 2288s \----------------------------------------------------------------------------/ 2288s 2288s Yosys 0.33 (git sha1 2584903a060) 2288s 2288s 2288s -- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -- 2288s 2288s 1. Executing Verilog-2005 frontend: roundtrip.v 2288s Parsing Verilog input from `roundtrip.v' to AST representation. 2288s Generating RTLIL representation for module `\m'. 2288s Successfully finished Verilog frontend. 2288s 2288s 2. Executing PROC pass (convert processes to netlists). 2288s 2288s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2288s Cleaned up 0 empty switches. 2288s 2288s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2288s Removed a total of 0 dead cases. 2288s 2288s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2288s Removed 1 redundant assignment. 2288s Promoted 1 assignment to connection. 2288s 2288s 2.4. Executing PROC_INIT pass (extract init attributes). 2288s 2288s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2288s 2288s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2288s Converted 0 switches. 2288s 2288s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2288s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2288s 2288s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2288s 2288s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2288s 2288s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2288s 2288s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2288s Removing empty process `m.$proc$roundtrip.v:3$1'. 2288s Cleaned up 0 empty switches. 2288s 2288s 2.12. Executing OPT_EXPR pass (perform const folding). 2288s Optimizing module m. 2288s Removed 0 unused cells and 1 unused wires. 2288s 2288s -- Writing to `yosys-roundtrip-hex_unsigned-1.v' using backend `verilog' -- 2288s 2288s 3. Executing Verilog backend. 2288s 2288s 3.1. Executing BMUXMAP pass. 2288s 2288s 3.2. Executing DEMUXMAP pass. 2288s Dumping module `\m'. 2288s 2288s End of script. Logfile hash: 2377f2e106, CPU: user 0.01s system 0.00s, MEM: 10.00 MB peak 2288s Yosys 0.33 (git sha1 2584903a060) 2288s Time spent: 30% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 2288s 2288s /----------------------------------------------------------------------------\ 2288s | | 2288s | yosys -- Yosys Open SYnthesis Suite | 2288s | | 2288s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2288s | | 2288s | Permission to use, copy, modify, and/or distribute this software for any | 2288s | purpose with or without fee is hereby granted, provided that the above | 2288s | copyright notice and this permission notice appear in all copies. | 2288s | | 2288s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2288s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2288s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2288s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2288s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2288s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2288s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2288s | | 2288s \----------------------------------------------------------------------------/ 2288s 2288s Yosys 0.33 (git sha1 2584903a060) 2288s 2288s 2288s -- Running command `read_verilog yosys-roundtrip-hex_unsigned-1.v; proc; clean' -- 2288s 2288s 1. Executing Verilog-2005 frontend: yosys-roundtrip-hex_unsigned-1.v 2288s Parsing Verilog input from `yosys-roundtrip-hex_unsigned-1.v' to AST representation. 2288s Generating RTLIL representation for module `\m'. 2288s Successfully finished Verilog frontend. 2288s 2288s 2. Executing PROC pass (convert processes to netlists). 2288s 2288s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2288s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'. 2288s Cleaned up 1 empty switch. 2288s 2288s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2288s Removed a total of 0 dead cases. 2288s 2288s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2288s Removed 1 redundant assignment. 2288s Promoted 1 assignment to connection. 2288s 2288s 2.4. Executing PROC_INIT pass (extract init attributes). 2288s 2288s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2288s 2288s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2288s Converted 0 switches. 2288s 2288s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2288s Creating decoders for process `\m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'. 2288s 2288s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2288s 2288s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2288s 2288s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2288s 2288s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2288s Removing empty process `m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'. 2288s Cleaned up 0 empty switches. 2288s 2288s 2.12. Executing OPT_EXPR pass (perform const folding). 2288s Optimizing module m. 2288s Removed 0 unused cells and 1 unused wires. 2288s 2288s -- Writing to `yosys-roundtrip-hex_unsigned-2.v' using backend `verilog' -- 2288s 2288s 3. Executing Verilog backend. 2288s 2288s 3.1. Executing BMUXMAP pass. 2288s 2288s 3.2. Executing DEMUXMAP pass. 2288s Dumping module `\m'. 2288s 2288s End of script. Logfile hash: 06bfea69c8, CPU: user 0.00s system 0.01s, MEM: 10.00 MB peak 2288s Yosys 0.33 (git sha1 2584903a060) 2288s Time spent: 29% 1x clean (0 sec), 19% 1x opt_expr (0 sec), ... 2288s 2288s /----------------------------------------------------------------------------\ 2288s | | 2288s | yosys -- Yosys Open SYnthesis Suite | 2288s | | 2288s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2288s | | 2288s | Permission to use, copy, modify, and/or distribute this software for any | 2288s | purpose with or without fee is hereby granted, provided that the above | 2288s | copyright notice and this permission notice appear in all copies. | 2288s | | 2288s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2288s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2288s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2288s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2288s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2288s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2288s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2288s | | 2288s \----------------------------------------------------------------------------/ 2288s 2288s Yosys 0.33 (git sha1 2584903a060) 2288s 2288s 2288s -- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -- 2288s 2288s 1. Executing Verilog-2005 frontend: roundtrip.v 2288s Parsing Verilog input from `roundtrip.v' to AST representation. 2288s Generating RTLIL representation for module `\m'. 2288s Successfully finished Verilog frontend. 2288s 2288s 2. Executing PROC pass (convert processes to netlists). 2288s 2288s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2288s Cleaned up 0 empty switches. 2288s 2288s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2288s Removed a total of 0 dead cases. 2288s 2288s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2288s Removed 1 redundant assignment. 2288s Promoted 1 assignment to connection. 2288s 2288s 2.4. Executing PROC_INIT pass (extract init attributes). 2288s 2288s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2288s 2288s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2288s Converted 0 switches. 2288s 2288s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2288s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2288s 2288s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2288s + iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed roundtrip.v roundtrip_tb.v 2288s + ./iverilog-roundtrip-dec_signed 2288s + iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed-1 yosys-roundtrip-dec_signed-1.v roundtrip_tb.v 2288s + ./iverilog-roundtrip-dec_signed-1 2288s + iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed-2 yosys-roundtrip-dec_signed-2.v roundtrip_tb.v 2288s + ./iverilog-roundtrip-dec_signed-1 2288s + diff iverilog-roundtrip-dec_signed.log iverilog-roundtrip-dec_signed-1.log 2288s + diff iverilog-roundtrip-dec_signed-1.log iverilog-roundtrip-dec_signed-2.log 2288s + test_roundtrip hex_unsigned -DBASE_HEX -DSIGN= 2288s + local subtest=hex_unsigned 2288s + shift 2288s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-hex_unsigned-1.v 2288s + ../../yosys -p 'read_verilog yosys-roundtrip-hex_unsigned-1.v; proc; clean' -o yosys-roundtrip-hex_unsigned-2.v 2288s + diff yosys-roundtrip-hex_unsigned-1.v yosys-roundtrip-hex_unsigned-2.v 2288s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned roundtrip.v roundtrip_tb.v 2288s + ./iverilog-roundtrip-hex_unsigned 2288s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned-1 yosys-roundtrip-hex_unsigned-1.v roundtrip_tb.v 2288s + ./iverilog-roundtrip-hex_unsigned-1 2288s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned-2 yosys-roundtrip-hex_unsigned-2.v roundtrip_tb.v 2288s + ./iverilog-roundtrip-hex_unsigned-1 2288s + diff iverilog-roundtrip-hex_unsigned.log iverilog-roundtrip-hex_unsigned-1.log 2288s + diff iverilog-roundtrip-hex_unsigned-1.log iverilog-roundtrip-hex_unsigned-2.log 2288s + test_roundtrip hex_signed -DBASE_HEX -DSIGN=signed 2288s + local subtest=hex_signed 2288s + shift 2288s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-hex_signed-1.v 2288s + ../../yosys -p 'read_verilog yosys-roundtrip-hex_signed-1.v; proc; clean' -o yosys-roundtrip-hex_signed-2.v 2288s + diff yosys-roundtrip-hex_signed-1.v yosys-roundtrip-hex_signed-2.v 2288s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed roundtrip.v roundtrip_tb.v 2288s + ./iverilog-roundtrip-hex_signed 2288s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed-1 yosys-roundtrip-hex_signed-1.v roundtrip_tb.v 2288s + ./iverilog-roundtrip-hex_signed-1 2288s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed-2 yosys-roundtrip-hex_signed-2.v roundtrip_tb.v 2288s + ./iverilog-roundtrip-hex_signed-1 2288s + diff iverilog-roundtrip-hex_signed.log iverilog-roundtrip-hex_signed-1.log 2288s + diff iverilog-roundtrip-hex_signed-1.log iverilog-roundtrip-hex_signed-2.log 2288s + test_roundtrip oct_unsigned -DBASE_HEX -DSIGN= 2288s + local subtest=oct_unsigned 2288s + shift 2288s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-oct_unsigned-1.v 2288s + ../../yosys -p 'read_verilog yosys-roundtrip-oct_unsigned-1.v; proc; clean' -o yosys-roundtrip-oct_unsigned-2.v 2288s 2288s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2288s 2288s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2288s 2288s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2288s Removing empty process `m.$proc$roundtrip.v:3$1'. 2288s Cleaned up 0 empty switches. 2288s 2288s 2.12. Executing OPT_EXPR pass (perform const folding). 2288s Optimizing module m. 2288s Removed 0 unused cells and 1 unused wires. 2288s 2288s -- Writing to `yosys-roundtrip-hex_signed-1.v' using backend `verilog' -- 2288s 2288s 3. Executing Verilog backend. 2288s 2288s 3.1. Executing BMUXMAP pass. 2288s 2288s 3.2. Executing DEMUXMAP pass. 2288s Dumping module `\m'. 2288s 2288s End of script. Logfile hash: 824c3b1e65, CPU: user 0.00s system 0.00s, MEM: 10.00 MB peak 2288s Yosys 0.33 (git sha1 2584903a060) 2288s Time spent: 30% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 2288s 2288s /----------------------------------------------------------------------------\ 2288s | | 2288s | yosys -- Yosys Open SYnthesis Suite | 2288s | | 2288s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2288s | | 2288s | Permission to use, copy, modify, and/or distribute this software for any | 2288s | purpose with or without fee is hereby granted, provided that the above | 2288s | copyright notice and this permission notice appear in all copies. | 2288s | | 2288s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2288s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2288s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2288s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2288s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2288s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2288s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2288s | | 2288s \----------------------------------------------------------------------------/ 2288s 2288s Yosys 0.33 (git sha1 2584903a060) 2288s 2288s 2288s -- Running command `read_verilog yosys-roundtrip-hex_signed-1.v; proc; clean' -- 2288s 2288s 1. Executing Verilog-2005 frontend: yosys-roundtrip-hex_signed-1.v 2288s Parsing Verilog input from `yosys-roundtrip-hex_signed-1.v' to AST representation. 2288s Generating RTLIL representation for module `\m'. 2288s Successfully finished Verilog frontend. 2288s 2288s 2. Executing PROC pass (convert processes to netlists). 2288s 2288s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2288s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'. 2288s Cleaned up 1 empty switch. 2288s 2288s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2288s Removed a total of 0 dead cases. 2288s 2288s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2288s Removed 1 redundant assignment. 2288s Promoted 1 assignment to connection. 2288s 2288s 2.4. Executing PROC_INIT pass (extract init attributes). 2288s 2288s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2288s 2288s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2288s Converted 0 switches. 2288s 2288s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2288s Creating decoders for process `\m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'. 2288s 2288s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2288s 2288s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2288s 2288s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2288s 2288s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2288s Removing empty process `m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'. 2288s Cleaned up 0 empty switches. 2288s 2288s 2.12. Executing OPT_EXPR pass (perform const folding). 2288s Optimizing module m. 2288s Removed 0 unused cells and 1 unused wires. 2288s 2288s -- Writing to `yosys-roundtrip-hex_signed-2.v' using backend `verilog' -- 2288s 2288s 3. Executing Verilog backend. 2288s 2288s 3.1. Executing BMUXMAP pass. 2288s 2288s 3.2. Executing DEMUXMAP pass. 2288s Dumping module `\m'. 2288s 2288s End of script. Logfile hash: f18b3fa15b, CPU: user 0.00s system 0.01s, MEM: 10.00 MB peak 2288s Yosys 0.33 (git sha1 2584903a060) 2288s Time spent: 28% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... 2288s 2288s /----------------------------------------------------------------------------\ 2288s | | 2288s | yosys -- Yosys Open SYnthesis Suite | 2288s | | 2288s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2288s | | 2288s | Permission to use, copy, modify, and/or distribute this software for any | 2288s | purpose with or without fee is hereby granted, provided that the above | 2288s | copyright notice and this permission notice appear in all copies. | 2288s | | 2288s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2288s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2288s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2288s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2288s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2288s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2288s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2288s | | 2288s \----------------------------------------------------------------------------/ 2288s 2288s Yosys 0.33 (git sha1 2584903a060) 2288s 2288s 2288s -- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -- 2288s 2288s 1. Executing Verilog-2005 frontend: roundtrip.v 2288s Parsing Verilog input from `roundtrip.v' to AST representation. 2288s Generating RTLIL representation for module `\m'. 2288s Successfully finished Verilog frontend. 2288s 2288s 2. Executing PROC pass (convert processes to netlists). 2288s 2288s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2288s Cleaned up 0 empty switches. 2288s 2288s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2288s Removed a total of 0 dead cases. 2288s 2288s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2288s Removed 1 redundant assignment. 2288s Promoted 1 assignment to connection. 2288s 2288s 2.4. Executing PROC_INIT pass (extract init attributes). 2288s 2288s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2288s 2288s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2288s Converted 0 switches. 2288s 2288s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2288s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2288s 2288s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2288s 2288s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2288s 2288s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2288s 2288s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2288s Removing empty process `m.$proc$roundtrip.v:3$1'. 2288s Cleaned up 0 empty switches. 2288s 2288s 2.12. Executing OPT_EXPR pass (perform const folding). 2288s Optimizing module m. 2288s Removed 0 unused cells and 1 unused wires. 2288s 2288s -- Writing to `yosys-roundtrip-oct_unsigned-1.v' using backend `verilog' -- 2288s 2288s 3. Executing Verilog backend. 2288s 2288s 3.1. Executing BMUXMAP pass. 2288s 2288s 3.2. Executing DEMUXMAP pass. 2288s Dumping module `\m'. 2288s 2288s End of script. Logfile hash: b768358a65, CPU: user 0.01s system 0.00s, MEM: 10.00 MB peak 2288s Yosys 0.33 (git sha1 2584903a060) 2288s Time spent: 30% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... 2288s 2288s /----------------------------------------------------------------------------\ 2288s | | 2288s | yosys -- Yosys Open SYnthesis Suite | 2288s | | 2288s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2288s | | 2288s | Permission to use, copy, modify, and/or distribute this software for any | 2288s | purpose with or without fee is hereby granted, provided that the above | 2288s | copyright notice and this permission notice appear in all copies. | 2288s | | 2288s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2288s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2288s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2288s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2288s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2288s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2288s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2288s | | 2288s \----------------------------------------------------------------------------/ 2288s 2288s Yosys 0.33 (git sha1 2584903a060) 2288s 2288s 2288s -- Running command `read_verilog yosys-roundtrip-oct_unsigned-1.v; proc; clean' -- 2288s 2288s 1. Executing Verilog-2005 frontend: yosys-roundtrip-oct_unsigned-1.v 2288s Parsing Verilog input from `yosys-roundtrip-oct_unsigned-1.v' to AST representation. 2288s Generating RTLIL representation for module `\m'. 2288s Successfully finished Verilog frontend. 2288s 2288s 2. Executing PROC pass (convert processes to netlists). 2288s 2288s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2288s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'. 2288s Cleaned up 1 empty switch. 2288s 2288s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2288s Removed a total of 0 dead cases. 2288s 2288s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2288s Removed 1 redundant assignment. 2288s Promoted 1 assignment to connection. 2288s 2288s 2.4. Executing PROC_INIT pass (extract init attributes). 2288s 2288s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2288s 2288s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2288s Converted 0 switches. 2288s 2288s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2288s Creating decoders for process `\m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'. 2288s 2288s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2288s 2288s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2288s 2288s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2288s 2288s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2288s Removing empty process `m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'. 2288s Cleaned up 0 empty switches. 2288s 2288s 2.12. Executing OPT_EXPR pass (perform const folding). 2288s Optimizing module m. 2288s Removed 0 unused cells and 1 unused wires. 2288s 2288s -- Writing to `yosys-roundtrip-oct_unsigned-2.v' using backend `verilog' -- 2288s 2288s 3. Executing Verilog backend. 2288s 2288s 3.1. Executing BMUXMAP pass. 2288s 2288s 3.2. Executing DEMUXMAP pass. 2288s Dumping module `\m'. 2288s 2288s End of script. Logfile hash: 762621cd95, CPU: user 0.00s system 0.01s, MEM: 10.00 MB peak 2288s Yosys 0.33 (git sha1 2584903a060) 2288s Time spent: 29% 1x clean (0 sec), 19% 1x opt_expr (0 sec), ... 2288s 2288s /----------------------------------------------------------------------------\ 2288s | | 2288s | yosys -- Yosys Open SYnthesis Suite | 2288s | | 2288s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2288s | | 2288s | Permission to use, copy, modify, and/or distribute this software for any | 2288s | purpose with or without fee is hereby granted, provided that the above | 2288s | copyright notice and this permission notice appear in all copies. | 2288s | | 2288s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2288s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2288s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2288s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2288s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2288s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2288s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2288s | | 2288s \----------------------------------------------------------------------------/ 2288s 2288s Yosys 0.33 (git sha1 2584903a060) 2288s 2288s 2288s -- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -- 2288s 2288s 1. Executing Verilog-2005 frontend: roundtrip.v 2288s Parsing Verilog input from `roundtrip.v' to AST representation. 2288s Generating RTLIL representation for module `\m'. 2288s Successfully finished Verilog frontend. 2288s 2288s 2. Executing PROC pass (convert processes to netlists). 2288s 2288s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2288s Cleaned up 0 empty switches. 2288s 2288s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2288s Removed a total of 0 dead cases. 2288s 2288s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2288s Removed 1 redundant assignment. 2288s Promoted 1 assignment to connection. 2288s 2288s 2.4. Executing PROC_INIT pass (extract init attributes). 2288s 2288s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2288s 2288s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2288s Converted 0 switches. 2288s 2288s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2288s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2288s 2288s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2288s 2288s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2288s 2288s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2288s 2288s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2288s Removing empty process `m.$proc$roundtrip.v:3$1'. 2288s Cleaned up 0 empty switches. 2288s 2288s 2.12. Executing OPT_EXPR pass (perform const folding). 2288s Optimizing module m. 2288s Removed 0 unused cells and 1 unused wires. 2288s 2288s -- Writing to `yosys-roundtrip-oct_signed-1.v' using backend `verilog' -- 2288s 2288s 3. Executing Verilog backend. 2288s 2288s 3.1. Executing BMUXMAP pass. 2288s 2288s 3.2. Executing DEMUXMAP pass. 2288s Dumping module `\m'. 2288s 2288s End of script. Logfile hash: 7ec82b15e3, CPU: user 0.01s system 0.00s, MEM: 10.00 MB peak 2288s Yosys 0.33 (git sha1 2584903a060) 2288s Time spent: 31% 1x clean (0 sec), 19% 1x opt_expr (0 sec), ... 2288s + diff yosys-roundtrip-oct_unsigned-1.v yosys-roundtrip-oct_unsigned-2.v 2288s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned roundtrip.v roundtrip_tb.v 2288s + ./iverilog-roundtrip-oct_unsigned 2288s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned-1 yosys-roundtrip-oct_unsigned-1.v roundtrip_tb.v 2288s + ./iverilog-roundtrip-oct_unsigned-1 2288s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned-2 yosys-roundtrip-oct_unsigned-2.v roundtrip_tb.v 2288s + ./iverilog-roundtrip-oct_unsigned-1 2288s + diff iverilog-roundtrip-oct_unsigned.log iverilog-roundtrip-oct_unsigned-1.log 2288s + diff iverilog-roundtrip-oct_unsigned-1.log iverilog-roundtrip-oct_unsigned-2.log 2288s + test_roundtrip oct_signed -DBASE_HEX -DSIGN=signed 2288s + local subtest=oct_signed 2288s + shift 2288s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-oct_signed-1.v 2288s + ../../yosys -p 'read_verilog yosys-roundtrip-oct_signed-1.v; proc; clean' -o yosys-roundtrip-oct_signed-2.v 2288s + diff yosys-roundtrip-oct_signed-1.v yosys-roundtrip-oct_signed-2.v 2288s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed roundtrip.v roundtrip_tb.v 2288s + ./iverilog-roundtrip-oct_signed 2288s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed-1 yosys-roundtrip-oct_signed-1.v roundtrip_tb.v 2288s + ./iverilog-roundtrip-oct_signed-1 2288s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed-2 yosys-roundtrip-oct_signed-2.v roundtrip_tb.v 2288s + ./iverilog-roundtrip-oct_signed-1 2288s + diff iverilog-roundtrip-oct_signed.log iverilog-roundtrip-oct_signed-1.log 2288s + diff iverilog-roundtrip-oct_signed-1.log iverilog-roundtrip-oct_signed-2.log 2288s + test_roundtrip bin_unsigned -DBASE_HEX -DSIGN= 2288s + local subtest=bin_unsigned 2288s + shift 2288s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-bin_unsigned-1.v 2288s + ../../yosys -p 'read_verilog yosys-roundtrip-bin_unsigned-1.v; proc; clean' -o yosys-roundtrip-bin_unsigned-2.v 2288s 2288s /----------------------------------------------------------------------------\ 2288s | | 2288s | yosys -- Yosys Open SYnthesis Suite | 2288s | | 2288s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2288s | | 2288s | Permission to use, copy, modify, and/or distribute this software for any | 2288s | purpose with or without fee is hereby granted, provided that the above | 2288s | copyright notice and this permission notice appear in all copies. | 2288s | | 2288s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2288s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2288s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2288s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2288s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2288s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2288s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2288s | | 2288s \----------------------------------------------------------------------------/ 2288s 2288s Yosys 0.33 (git sha1 2584903a060) 2288s 2288s 2288s -- Running command `read_verilog yosys-roundtrip-oct_signed-1.v; proc; clean' -- 2288s 2288s 1. Executing Verilog-2005 frontend: yosys-roundtrip-oct_signed-1.v 2288s Parsing Verilog input from `yosys-roundtrip-oct_signed-1.v' to AST representation. 2288s Generating RTLIL representation for module `\m'. 2288s Successfully finished Verilog frontend. 2288s 2288s 2. Executing PROC pass (convert processes to netlists). 2288s 2288s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2288s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'. 2288s Cleaned up 1 empty switch. 2288s 2288s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2288s Removed a total of 0 dead cases. 2288s 2288s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2288s Removed 1 redundant assignment. 2288s Promoted 1 assignment to connection. 2288s 2288s 2.4. Executing PROC_INIT pass (extract init attributes). 2288s 2288s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2288s 2288s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2288s Converted 0 switches. 2288s 2288s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2288s Creating decoders for process `\m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'. 2288s 2288s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2288s 2288s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2288s 2288s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2288s 2288s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2288s Removing empty process `m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'. 2288s Cleaned up 0 empty switches. 2288s 2288s 2.12. Executing OPT_EXPR pass (perform const folding). 2288s Optimizing module m. 2288s Removed 0 unused cells and 1 unused wires. 2288s 2288s -- Writing to `yosys-roundtrip-oct_signed-2.v' using backend `verilog' -- 2288s 2288s 3. Executing Verilog backend. 2288s 2288s 3.1. Executing BMUXMAP pass. 2288s 2288s 3.2. Executing DEMUXMAP pass. 2288s Dumping module `\m'. 2288s 2288s End of script. Logfile hash: a747b9bd4f, CPU: user 0.01s system 0.00s, MEM: 10.00 MB peak 2288s Yosys 0.33 (git sha1 2584903a060) 2288s Time spent: 30% 1x clean (0 sec), 19% 1x opt_expr (0 sec), ... 2288s 2288s /----------------------------------------------------------------------------\ 2288s | | 2288s | yosys -- Yosys Open SYnthesis Suite | 2288s | | 2288s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2288s | | 2288s | Permission to use, copy, modify, and/or distribute this software for any | 2288s | purpose with or without fee is hereby granted, provided that the above | 2288s | copyright notice and this permission notice appear in all copies. | 2288s | | 2288s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2288s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2288s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2288s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2288s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2288s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2288s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2288s | | 2288s \----------------------------------------------------------------------------/ 2288s 2288s Yosys 0.33 (git sha1 2584903a060) 2288s 2288s 2288s -- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -- 2288s 2288s 1. Executing Verilog-2005 frontend: roundtrip.v 2288s Parsing Verilog input from `roundtrip.v' to AST representation. 2288s Generating RTLIL representation for module `\m'. 2288s Successfully finished Verilog frontend. 2288s 2288s 2. Executing PROC pass (convert processes to netlists). 2288s 2288s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2288s Cleaned up 0 empty switches. 2288s 2288s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2288s Removed a total of 0 dead cases. 2288s 2288s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2288s Removed 1 redundant assignment. 2288s Promoted 1 assignment to connection. 2288s 2288s 2.4. Executing PROC_INIT pass (extract init attributes). 2288s 2288s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2288s 2288s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2288s Converted 0 switches. 2288s 2288s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2288s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2288s 2288s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2288s 2288s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2288s 2288s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2288s 2288s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2288s Removing empty process `m.$proc$roundtrip.v:3$1'. 2288s Cleaned up 0 empty switches. 2288s 2288s 2.12. Executing OPT_EXPR pass (perform const folding). 2288s Optimizing module m. 2288s Removed 0 unused cells and 1 unused wires. 2288s 2288s -- Writing to `yosys-roundtrip-bin_unsigned-1.v' using backend `verilog' -- 2288s 2288s 3. Executing Verilog backend. 2288s 2288s 3.1. Executing BMUXMAP pass. 2288s 2288s 3.2. Executing DEMUXMAP pass. 2288s Dumping module `\m'. 2288s 2288s End of script. Logfile hash: 270b564880, CPU: user 0.00s system 0.01s, MEM: 10.00 MB peak 2288s Yosys 0.33 (git sha1 2584903a060) 2288s Time spent: 30% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 2288s 2288s /----------------------------------------------------------------------------\ 2288s | | 2288s | yosys -- Yosys Open SYnthesis Suite | 2288s | | 2288s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2288s | | 2288s | Permission to use, copy, modify, and/or distribute this software for any | 2288s | purpose with or without fee is hereby granted, provided that the above | 2288s | copyright notice and this permission notice appear in all copies. | 2288s | | 2288s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2288s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2288s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2288s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2288s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2288s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2288s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2288s | | 2288s \----------------------------------------------------------------------------/ 2288s 2288s Yosys 0.33 (git sha1 2584903a060) 2288s 2288s 2288s -- Running command `read_verilog yosys-roundtrip-bin_unsigned-1.v; proc; clean' -- 2288s 2288s 1. Executing Verilog-2005 frontend: yosys-roundtrip-bin_unsigned-1.v 2288s Parsing Verilog input from `yosys-roundtrip-bin_unsigned-1.v' to AST representation. 2288s Generating RTLIL representation for module `\m'. 2288s Successfully finished Verilog frontend. 2288s 2288s 2. Executing PROC pass (convert processes to netlists). 2288s 2288s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2288s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'. 2288s Cleaned up 1 empty switch. 2288s 2288s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2288s Removed a total of 0 dead cases. 2288s 2288s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2288s Removed 1 redundant assignment. 2288s Promoted 1 assignment to connection. 2288s 2288s 2.4. Executing PROC_INIT pass (extract init attributes). 2288s 2288s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2288s 2288s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2288s Converted 0 switches. 2288s 2288s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2288s Creating decoders for process `\m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'. 2288s 2288s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2288s 2288s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2288s 2288s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2288s 2288s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2288s Removing empty process `m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'. 2288s Cleaned up 0 empty switches. 2288s 2288s 2.12. Executing OPT_EXPR pass (perform const folding). 2288s Optimizing module m. 2288s Removed 0 unused cells and 1 unused wires. 2288s 2288s -- Writing to `yosys-roundtrip-bin_unsigned-2.v' using backend `verilog' -- 2288s 2288s 3. Executing Verilog backend. 2288s 2288s 3.1. Executing BMUXMAP pass. 2288s 2288s 3.2. Executing DEMUXMAP pass. 2288s Dumping module `\m'. 2288s 2288s End of script. Logfile hash: dc9f56cb10, CPU: user 0.00s system 0.01s, MEM: 10.00 MB peak 2288s Yosys 0.33 (git sha1 2584903a060) 2288s Time spent: 28% 1x clean (0 sec), 19% 1x opt_expr (0 sec), ... 2288s 2288s /----------------------------------------------------------------------------\ 2288s | | 2288s | yosys -- Yosys Open SYnthesis Suite | 2288s | | 2288s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2288s | | 2288s | Permission to use, copy, modify, and/or distribute this software for any | 2288s | purpose with or without fee is hereby granted, provided that the above | 2288s | copyright notice and this permission notice appear in all copies. | 2288s | | 2288s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2288s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2288s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2288s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2288s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2288s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2288s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2288s | | 2288s \----------------------------------------------------------------------------/ 2288s 2288s Yosys 0.33 (git sha1 2584903a060) 2288s 2288s 2288s -- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -- 2288s 2288s 1. Executing Verilog-2005 frontend: roundtrip.v 2288s Parsing Verilog input from `roundtrip.v' to AST representation. 2288s Generating RTLIL representation for module `\m'. 2288s Successfully finished Verilog frontend. 2288s 2288s 2. Executing PROC pass (convert processes to netlists). 2288s 2288s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2288s Cleaned up 0 empty switches. 2288s 2288s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2288s Removed a total of 0 dead cases. 2288s 2288s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2288s Removed 1 redundant assignment. 2288s Promoted 1 assignment to connection. 2288s 2288s 2.4. Executing PROC_INIT pass (extract init attributes). 2288s 2288s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2288s 2288s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2288s Converted 0 switches. 2288s 2288s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2288s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2288s 2288s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2288s 2288s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2288s 2288s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2288s 2288s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2288s Removing empty process `m.$proc$roundtrip.v:3$1'. 2288s Cleaned up 0 empty switches. 2288s 2288s 2.12. Executing OPT_EXPR pass (perform const folding). 2288s Optimizing module m. 2288s Removed 0 unused cells and 1 unused wires. 2288s 2288s -- Writing to `yosys-roundtrip-bin_signed-1.v' using backend `verilog' -- 2288s 2288s 3. Executing Verilog backend. 2288s 2288s 3.1. Executing BMUXMAP pass. 2288s 2288s 3.2. Executing DEMUXMAP pass. 2288s Dumping module `\m'. 2288s 2288s End of script. Logfile hash: 7709253822, CPU: user 0.01s system 0.00s, MEM: 10.00 MB peak 2288s Yosys 0.33 (git sha1 2584903a060) 2288s Time spent: 29% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 2288s 2288s /----------------------------------------------------------------------------\ 2288s | | 2288s | yosys -- Yosys Open SYnthesis Suite | 2288s | | 2288s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2288s | | 2288s | Permission to use, copy, modify, and/or distribute this software for any | 2288s | purpose with or without fee is hereby granted, provided that the above | 2288s | copyright notice and this permission notice appear in all copies. | 2288s | | 2288s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2288s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2288s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2288s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2288s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2288s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2288s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2288s | | 2288s \----------------------------------------------------------------------------/ 2288s 2288s Yosys 0.33 (git sha1 2584903a060) 2288s 2288s 2288s -- Running command `read_verilog yosys-roundtrip-bin_signed-1.v; proc; clean' -- 2288s 2288s 1. Executing Verilog-2005 frontend: yosys-roundtrip-bin_signed-1.v 2288s Parsing Verilog input from `yosys-roundtrip-bin_signed-1.v' to AST representation. 2288s Generating RTLIL representation for module `\m'. 2288s Successfully finished Verilog frontend. 2288s 2288s 2. Executing PROC pass (convert processes to netlists). 2288s 2288s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2288s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'. 2288s Cleaned up 1 empty switch. 2288s 2288s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2288s Removed a total of 0 dead cases. 2288s 2288s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2288s Removed 1 redundant assignment. 2288s Promoted 1 assignment to connection. 2288s 2288s 2.4. Executing PROC_INIT pass (extract init attributes). 2288s 2288s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2288s 2288s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2288s Converted 0 switches. 2288s 2288s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2288s Creating decoders for process `\m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'. 2288s 2288s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2288s 2288s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2288s 2288s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2288s 2288s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2288s Removing empty process `m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'. 2288s Cleaned up 0 empty switches. 2288s 2288s 2.12. Executing OPT_EXPR pass (perform const folding). 2288s Optimizing module m. 2288s Removed 0 unused cells and 1 unused wires. 2288s 2288s -- Writing to `yosys-roundtrip-bin_signed-2.v' using backend `verilog' -- 2288s 2288s 3. Executing Verilog backend. 2288s 2288s 3.1. Executing BMUXMAP pass. 2288s 2288s 3.2. Executing DEMUXMAP pass. 2288s Dumping module `\m'. 2288s 2288s End of script. Logfile hash: 7e2d8271c4, CPU: user 0.01s system 0.00s, MEM: 10.00 MB peak 2288s Yosys 0.33 (git sha1 2584903a060) 2288s Time spent: 28% 1x clean (0 sec), 18% 1x opt_expr (0 sec), ... 2288s + diff yosys-roundtrip-bin_unsigned-1.v yosys-roundtrip-bin_unsigned-2.v 2288s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned roundtrip.v roundtrip_tb.v 2288s + ./iverilog-roundtrip-bin_unsigned 2288s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned-1 yosys-roundtrip-bin_unsigned-1.v roundtrip_tb.v 2288s + ./iverilog-roundtrip-bin_unsigned-1 2288s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned-2 yosys-roundtrip-bin_unsigned-2.v roundtrip_tb.v 2288s + ./iverilog-roundtrip-bin_unsigned-1 2288s + diff iverilog-roundtrip-bin_unsigned.log iverilog-roundtrip-bin_unsigned-1.log 2288s + diff iverilog-roundtrip-bin_unsigned-1.log iverilog-roundtrip-bin_unsigned-2.log 2288s + test_roundtrip bin_signed -DBASE_HEX -DSIGN=signed 2288s + local subtest=bin_signed 2288s + shift 2288s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-bin_signed-1.v 2288s + ../../yosys -p 'read_verilog yosys-roundtrip-bin_signed-1.v; proc; clean' -o yosys-roundtrip-bin_signed-2.v 2288s + diff yosys-roundtrip-bin_signed-1.v yosys-roundtrip-bin_signed-2.v 2288s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed roundtrip.v roundtrip_tb.v 2288s + ./iverilog-roundtrip-bin_signed 2288s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed-1 yosys-roundtrip-bin_signed-1.v roundtrip_tb.v 2288s + ./iverilog-roundtrip-bin_signed-1 2288s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed-2 yosys-roundtrip-bin_signed-2.v roundtrip_tb.v 2288s + ./iverilog-roundtrip-bin_signed-1 2288s + diff iverilog-roundtrip-bin_signed.log iverilog-roundtrip-bin_signed-1.log 2288s + diff iverilog-roundtrip-bin_signed-1.log iverilog-roundtrip-bin_signed-2.log 2288s + test_cxxrtl always_full 2288s + local subtest=always_full 2288s + shift 2288s + ../../yosys -p 'read_verilog always_full.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_full.cc' 2288s 2288s /----------------------------------------------------------------------------\ 2288s | | 2288s | yosys -- Yosys Open SYnthesis Suite | 2288s | | 2288s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2288s | | 2288s | Permission to use, copy, modify, and/or distribute this software for any | 2288s | purpose with or without fee is hereby granted, provided that the above | 2288s | copyright notice and this permission notice appear in all copies. | 2288s | | 2288s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2288s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2288s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2288s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2288s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2288s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2288s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2288s | | 2288s \----------------------------------------------------------------------------/ 2288s 2288s Yosys 0.33 (git sha1 2584903a060) 2288s 2288s 2288s -- Running command `read_verilog always_full.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_full.cc' -- 2288s 2288s 1. Executing Verilog-2005 frontend: always_full.v 2288s Parsing Verilog input from `always_full.v' to AST representation. 2288s Generating RTLIL representation for module `\always_full'. 2288s Successfully finished Verilog frontend. 2288s 2288s 2. Executing PROC pass (convert processes to netlists). 2288s 2288s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2288s Cleaned up 0 empty switches. 2288s 2288s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2288s Removed a total of 0 dead cases. 2288s 2288s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2288s Removed 207 redundant assignments. 2288s Promoted 207 assignments to connections. 2288s 2288s 2.4. Executing PROC_INIT pass (extract init attributes). 2288s 2288s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2288s 2288s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2288s Converted 0 switches. 2288s 2288s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2288s Creating decoders for process `\always_full.$proc$always_full.v:3$1'. 2288s 2288s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2288s 2288s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2288s 2288s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2288s 2288s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2288s Removing empty process `always_full.$proc$always_full.v:3$1'. 2288s Cleaned up 0 empty switches. 2288s 2288s 2.12. Executing OPT_EXPR pass (perform const folding). 2288s Optimizing module always_full. 2288s Removed 0 unused cells and 207 unused wires. 2288s 2288s 3. Executing CXXRTL backend. 2288s 2288s 3.1. Executing HIERARCHY pass (managing design hierarchy). 2288s 2288s 3.1.1. Finding top of design hierarchy.. 2288s root of 0 design levels: always_full 2288s Automatically selected always_full as design top module. 2288s 2288s 3.1.2. Analyzing design hierarchy.. 2288s Top module: \always_full 2288s 2288s 3.1.3. Analyzing design hierarchy.. 2288s Top module: \always_full 2288s Removed 0 unused modules. 2288s 2288s 3.2. Executing FLATTEN pass (flatten design). 2288s 2288s 3.3. Executing PROC pass (convert processes to netlists). 2288s 2288s 3.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2288s Cleaned up 0 empty switches. 2288s 2288s 3.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2288s Removed a total of 0 dead cases. 2288s 2288s 3.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2288s Removed 0 redundant assignments. 2288s Promoted 0 assignments to connections. 2288s 2288s 3.3.4. Executing PROC_INIT pass (extract init attributes). 2288s 2288s 3.3.5. Executing PROC_ARST pass (detect async resets in processes). 2288s 2288s 3.3.6. Executing PROC_ROM pass (convert switches to ROMs). 2288s Converted 0 switches. 2288s 2288s 3.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2288s 2288s 3.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2288s 2288s 3.3.9. Executing PROC_DFF pass (convert process syncs to FFs). 2288s 2288s 3.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2288s 2288s 3.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2288s Cleaned up 0 empty switches. 2288s 2288s 3.3.12. Executing OPT_EXPR pass (perform const folding). 2288s Optimizing module always_full. 2288s 2288s 2288s 2288s End of script. Logfile hash: 6abd135c0a, CPU: user 0.03s system 0.00s, MEM: 12.00 MB peak 2288s Yosys 0.33 (git sha1 2584903a060) 2288s Time spent: 24% 2x read_verilog (0 sec), 23% 2x opt_expr (0 sec), ... 2288s + gcc -std=c++11 -o yosys-always_full -I../.. always_full_tb.cc -lstdc++ 2289s + ./yosys-always_full 2289s + iverilog -o iverilog-always_full always_full.v always_full_tb.v 2289s + ./iverilog-always_full 2289s + grep -v '\$finish called' 2289s + diff iverilog-always_full.log yosys-always_full.log 2289s + test_cxxrtl always_comb 2289s + local subtest=always_comb 2289s + shift 2289s + ../../yosys -p 'read_verilog always_comb.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_comb.cc' 2289s 2289s /----------------------------------------------------------------------------\ 2289s | | 2289s | yosys -- Yosys Open SYnthesis Suite | 2289s | | 2289s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2289s | | 2289s | Permission to use, copy, modify, and/or distribute this software for any | 2289s | purpose with or without fee is hereby granted, provided that the above | 2289s | copyright notice and this permission notice appear in all copies. | 2289s | | 2289s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2289s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2289s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2289s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2289s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2289s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2289s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2289s | | 2289s \----------------------------------------------------------------------------/ 2289s 2289s Yosys 0.33 (git sha1 2584903a060) 2289s 2289s 2289s -- Running command `read_verilog always_comb.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_comb.cc' -- 2289s 2289s 1. Executing Verilog-2005 frontend: always_comb.v 2289s Parsing Verilog input from `always_comb.v' to AST representation. 2289s Generating RTLIL representation for module `\top'. 2289s Generating RTLIL representation for module `\sub'. 2289s Successfully finished Verilog frontend. 2289s 2289s 2. Executing PROC pass (convert processes to netlists). 2289s 2289s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2289s Cleaned up 0 empty switches. 2289s 2289s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2289s Removed a total of 0 dead cases. 2289s 2289s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2289s Removed 0 redundant assignments. 2289s Promoted 4 assignments to connections. 2289s 2289s 2.4. Executing PROC_INIT pass (extract init attributes). 2289s Found init rule in `\top.$proc$always_comb.v:3$13'. 2289s Set init value: \b = 1'0 2289s Found init rule in `\top.$proc$always_comb.v:2$12'. 2289s Set init value: \a = 1'0 2289s 2289s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2289s 2289s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2289s Converted 0 switches. 2289s 2289s 2289s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2289s Creating decoders for process `\sub.$proc$always_comb.v:23$15'. 2289s 1/1: $display$always_comb.v:23$19_EN 2289s Creating decoders for process `\top.$proc$always_comb.v:3$13'. 2289s Creating decoders for process `\top.$proc$always_comb.v:2$12'. 2289s Creating decoders for process `\top.$proc$always_comb.v:8$1'. 2289s 2289s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2289s 2289s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2289s Creating register for signal `\top.\a' using process `\top.$proc$always_comb.v:8$1'. 2289s created $dff cell `$procdff$22' with positive edge clock. 2289s Creating register for signal `\top.\b' using process `\top.$proc$always_comb.v:8$1'. 2289s created $dff cell `$procdff$23' with positive edge clock. 2289s 2289s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2289s 2289s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2289s Found and cleaned up 1 empty switch in `\sub.$proc$always_comb.v:23$15'. 2289s Removing empty process `sub.$proc$always_comb.v:23$15'. 2289s Removing empty process `top.$proc$always_comb.v:3$13'. 2289s Removing empty process `top.$proc$always_comb.v:2$12'. 2289s Removing empty process `top.$proc$always_comb.v:8$1'. 2289s Cleaned up 1 empty switch. 2289s 2289s 2.12. Executing OPT_EXPR pass (perform const folding). 2289s Optimizing module sub. 2289s Optimizing module top. 2289s Removed 0 unused cells and 7 unused wires. 2289s 2289s 3. Executing CXXRTL backend. 2289s 2289s 3.1. Executing HIERARCHY pass (managing design hierarchy). 2289s 2289s 3.1.1. Finding top of design hierarchy.. 2289s root of 0 design levels: sub 2289s root of 1 design levels: top 2289s Automatically selected top as design top module. 2289s 2289s 3.1.2. Analyzing design hierarchy.. 2289s Top module: \top 2289s Used module: \sub 2289s 2289s 3.1.3. Analyzing design hierarchy.. 2289s Top module: \top 2289s Used module: \sub 2289s Removed 0 unused modules. 2289s 2289s 3.2. Executing FLATTEN pass (flatten design). 2289s Deleting now unused module sub. 2289s 2289s 2289s 3.3. Executing PROC pass (convert processes to netlists). 2289s 2289s 3.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2289s Cleaned up 0 empty switches. 2289s 2289s 3.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2289s Removed a total of 0 dead cases. 2289s 2289s 3.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2289s Removed 0 redundant assignments. 2289s Promoted 0 assignments to connections. 2289s 2289s 3.3.4. Executing PROC_INIT pass (extract init attributes). 2289s 2289s 3.3.5. Executing PROC_ARST pass (detect async resets in processes). 2289s 2289s 3.3.6. Executing PROC_ROM pass (convert switches to ROMs). 2289s Converted 0 switches. 2289s 2289s 3.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2289s 2289s 3.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2289s 2289s 3.3.9. Executing PROC_DFF pass (convert process syncs to FFs). 2289s 2289s 3.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2289s 2289s 3.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2289s Cleaned up 0 empty switches. 2289s 2289s 3.3.12. Executing OPT_EXPR pass (perform const folding). 2289s Optimizing module top. 2289s 2289s 2289s 2289s End of script. Logfile hash: 03fe26efda, CPU: user 0.01s system 0.00s, MEM: 12.00 MB peak 2289s Yosys 0.33 (git sha1 2584903a060) 2289s Time spent: 30% 2x opt_expr (0 sec), 20% 1x clean (0 sec), ... 2289s + gcc -std=c++11 -o yosys-always_comb -I../.. always_comb_tb.cc -lstdc++ 2290s + ./yosys-always_comb 2290s + iverilog -o iverilog-always_comb always_comb.v always_comb_tb.v 2290s + ./iverilog-always_comb 2290s + grep -v '\$finish called' 2290s + diff iverilog-always_comb.log yosys-always_comb.log 2290s + ../../yosys -p 'read_verilog always_full.v; prep; clean' -o yosys-always_full-1.v 2290s 2290s /----------------------------------------------------------------------------\ 2290s | | 2290s | yosys -- Yosys Open SYnthesis Suite | 2290s | | 2290s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2290s | | 2290s | Permission to use, copy, modify, and/or distribute this software for any | 2290s | purpose with or without fee is hereby granted, provided that the above | 2290s | copyright notice and this permission notice appear in all copies. | 2290s | | 2290s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2290s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2290s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2290s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2290s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2290s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2290s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2290s | | 2290s \----------------------------------------------------------------------------/ 2290s 2290s Yosys 0.33 (git sha1 2584903a060) 2290s 2290s 2290s -- Running command `read_verilog always_full.v; prep; clean' -- 2290s 2290s 1. Executing Verilog-2005 frontend: always_full.v 2290s Parsing Verilog input from `always_full.v' to AST representation. 2290s Generating RTLIL representation for module `\always_full'. 2290s Successfully finished Verilog frontend. 2290s 2290s 2. Executing PREP pass. 2290s 2290s 2.1. Executing HIERARCHY pass (managing design hierarchy). 2290s 2290s 2.2. Executing PROC pass (convert processes to netlists). 2290s 2290s 2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2290s Cleaned up 0 empty switches. 2290s 2290s 2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2290s Removed a total of 0 dead cases. 2290s 2290s 2.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2290s Removed 207 redundant assignments. 2290s Promoted 207 assignments to connections. 2290s 2290s 2.2.4. Executing PROC_INIT pass (extract init attributes). 2290s 2290s 2.2.5. Executing PROC_ARST pass (detect async resets in processes). 2290s 2290s 2.2.6. Executing PROC_ROM pass (convert switches to ROMs). 2290s Converted 0 switches. 2290s 2290s 2.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2290s Creating decoders for process `\always_full.$proc$always_full.v:3$1'. 2290s 2290s 2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2290s 2290s 2.2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2290s 2290s 2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2290s 2290s 2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2290s Removing empty process `always_full.$proc$always_full.v:3$1'. 2290s Cleaned up 0 empty switches. 2290s 2290s 2.2.12. Executing OPT_EXPR pass (perform const folding). 2290s Optimizing module always_full. 2290s 2290s 2.3. Executing OPT_EXPR pass (perform const folding). 2290s Optimizing module always_full. 2290s 2290s 2.4. Executing OPT_CLEAN pass (remove unused cells and wires). 2290s Finding unused cells or wires in module \always_full.. 2290s Removed 0 unused cells and 207 unused wires. 2290s 2290s 2290s 2.5. Executing CHECK pass (checking for obvious problems). 2290s Checking module always_full... 2290s Found and reported 0 problems. 2290s 2290s 2.6. Executing OPT pass (performing simple optimizations). 2290s 2290s 2.6.1. Executing OPT_EXPR pass (perform const folding). 2290s Optimizing module always_full. 2290s 2290s 2.6.2. Executing OPT_MERGE pass (detect identical cells). 2290s Finding identical cells in module `\always_full'. 2290s Removed a total of 0 cells. 2290s 2290s 2.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 2290s Running muxtree optimizer on module \always_full.. 2290s Creating internal representation of mux trees. 2290s No muxes found in this module. 2290s Removed 0 multiplexer ports. 2290s 2290s 2.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 2290s Optimizing cells in module \always_full. 2290s Performed a total of 0 changes. 2290s 2290s 2.6.5. Executing OPT_MERGE pass (detect identical cells). 2290s Finding identical cells in module `\always_full'. 2290s Removed a total of 0 cells. 2290s 2290s 2.6.6. Executing OPT_CLEAN pass (remove unused cells and wires). 2290s Finding unused cells or wires in module \always_full.. 2290s 2290s 2.6.7. Executing OPT_EXPR pass (perform const folding). 2290s Optimizing module always_full. 2290s 2290s 2.6.8. Finished OPT passes. (There is nothing left to do.) 2290s 2290s 2.7. Executing WREDUCE pass (reducing word size of cells). 2290s 2290s 2.8. Executing OPT_CLEAN pass (remove unused cells and wires). 2290s Finding unused cells or wires in module \always_full.. 2290s 2290s 2.9. Executing MEMORY_COLLECT pass (generating $mem cells). 2290s 2290s 2.10. Executing OPT pass (performing simple optimizations). 2290s 2290s 2.10.1. Executing OPT_EXPR pass (perform const folding). 2290s Optimizing module always_full. 2290s 2290s 2.10.2. Executing OPT_MERGE pass (detect identical cells). 2290s Finding identical cells in module `\always_full'. 2290s Removed a total of 0 cells. 2290s 2290s 2.10.3. Executing OPT_CLEAN pass (remove unused cells and wires). 2290s Finding unused cells or wires in module \always_full.. 2290s 2290s 2.10.4. Finished fast OPT passes. 2290s 2290s 2.11. Printing statistics. 2290s 2290s === always_full === 2290s 2290s Number of wires: 1 2290s Number of wire bits: 1 2290s Number of public wires: 1 2290s Number of public wire bits: 1 2290s Number of memories: 0 2290s Number of memory bits: 0 2290s Number of processes: 0 2290s Number of cells: 207 2290s $print 207 2290s 2290s 2.12. Executing CHECK pass (checking for obvious problems). 2290s Checking module always_full... 2290s Found and reported 0 problems. 2290s 2290s -- Writing to `yosys-always_full-1.v' using backend `verilog' -- 2290s 2290s 3. Executing Verilog backend. 2290s 2290s 3.1. Executing BMUXMAP pass. 2290s 2290s 3.2. Executing DEMUXMAP pass. 2290s Dumping module `\always_full'. 2290s 2290s End of script. Logfile hash: cfd5b76053, CPU: user 0.08s system 0.00s, MEM: 12.00 MB peak 2290s Yosys 0.33 (git sha1 2584903a060) 2290s Time spent: 21% 5x opt_expr (0 sec), 20% 4x opt_clean (0 sec), ... 2290s 2290s /----------------------------------------------------------------------------\ 2290s | | 2290s | yosys -- Yosys Open SYnthesis Suite | 2290s | | 2290s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2290s | | 2290s | Permission to use, copy, modify, and/or distribute this software for any | 2290s | purpose with or without fee is hereby granted, provided that the above | 2290s | copyright notice and this permission notice appear in all copies. | 2290s | | 2290s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2290s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2290s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2290s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2290s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2290s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2290s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2290s | | 2290s \----------------------------------------------------------------------------/ 2290s 2290s Yosys 0.33 (git sha1 2584903a060) 2290s 2290s 2290s -- Running command `read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc' -- 2290s 2290s 1. Executing Verilog-2005 frontend: display_lm.v 2290s + iverilog -o iverilog-always_full-1 yosys-always_full-1.v always_full_tb.v 2290s + grep -v '\$finish called' 2290s + ./iverilog-always_full-1 2290s + diff iverilog-always_full.log iverilog-always_full-1.log 2290s + ../../yosys -p 'read_verilog display_lm.v' 2290s + ../../yosys -p 'read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc' 2290s Parsing Verilog input from `display_lm.v' to AST representation. 2290s Generating RTLIL representation for module `\top'. 2290s Generating RTLIL representation for module `\mid'. 2290s Generating RTLIL representation for module `\bot'. 2290s %l: \bot 2290s %m: \bot 2290s Successfully finished Verilog frontend. 2290s 2290s 2. Executing CXXRTL backend. 2290s 2290s 2.1. Executing HIERARCHY pass (managing design hierarchy). 2290s 2290s 2.1.1. Finding top of design hierarchy.. 2290s root of 0 design levels: bot 2290s root of 1 design levels: mid 2290s root of 2 design levels: top 2290s Automatically selected top as design top module. 2290s 2290s 2.1.2. Analyzing design hierarchy.. 2290s Top module: \top 2290s Used module: \mid 2290s Used module: \bot 2290s 2290s 2.1.3. Analyzing design hierarchy.. 2290s Top module: \top 2290s Used module: \mid 2290s Used module: \bot 2290s Removed 0 unused modules. 2290s 2290s 2.2. Executing FLATTEN pass (flatten design). 2290s Deleting now unused module bot. 2290s Deleting now unused module mid. 2290s 2290s 2290s 2.3. Executing PROC pass (convert processes to netlists). 2290s 2290s 2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2290s Removing empty process `top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:0$3'. 2290s Cleaned up 0 empty switches. 2290s 2290s 2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2290s Removed a total of 0 dead cases. 2290s 2290s 2.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2290s Removed 1 redundant assignment. 2290s Promoted 1 assignment to connection. 2290s 2290s 2.3.4. Executing PROC_INIT pass (extract init attributes). 2290s 2290s 2.3.5. Executing PROC_ARST pass (detect async resets in processes). 2290s 2290s 2.3.6. Executing PROC_ROM pass (convert switches to ROMs). 2290s Converted 0 switches. 2290s 2290s 2.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2290s Creating decoders for process `\top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:11$1'. 2290s 2290s 2.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2290s 2290s 2.3.9. Executing PROC_DFF pass (convert process syncs to FFs). 2290s 2290s 2.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2290s 2290s 2.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2290s Removing empty process `top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:11$1'. 2290s Cleaned up 0 empty switches. 2290s 2290s 2.3.12. Executing OPT_EXPR pass (perform const folding). 2290s + gcc -std=c++11 -o yosys-display_lm_cc -I../.. display_lm_tb.cc -lstdc++ 2290s Optimizing module top. 2290s 2290s 2290s 2290s End of script. Logfile hash: 1b689717a7, CPU: user 0.01s system 0.00s, MEM: 12.00 MB peak 2290s Yosys 0.33 (git sha1 2584903a060) 2290s Time spent: 40% 1x opt_expr (0 sec), 12% 2x read_verilog (0 sec), ... 2290s + ./yosys-display_lm_cc 2290s + for log in yosys-display_lm.log yosys-display_lm_cc.log 2290s + grep '^%l: \\bot$' yosys-display_lm.log 2290s %l: \bot 2290s + grep '^%m: \\bot$' yosys-display_lm.log 2290s + for log in yosys-display_lm.log yosys-display_lm_cc.log 2290s + grep '^%l: \\bot$' yosys-display_lm_cc.log 2290s + grep '^%m: \\bot$' yosys-display_lm_cc.log 2290s %m: \bot 2290s %l: \bot 2290s %m: \bot 2290s 2290s Passed "make test". 2290s 2291s autopkgtest [11:41:05]: test yosys-testsuite: -----------------------] 2292s autopkgtest [11:41:06]: test yosys-testsuite: - - - - - - - - - - results - - - - - - - - - - 2292s yosys-testsuite PASS 2292s autopkgtest [11:41:06]: test ice: preparing testbed 2371s autopkgtest [11:42:25]: testbed dpkg architecture: ppc64el 2371s autopkgtest [11:42:25]: testbed apt version: 3.0.0 2372s autopkgtest [11:42:26]: @@@@@@@@@@@@@@@@@@@@ test bed setup 2372s autopkgtest [11:42:26]: testbed release detected to be: questing 2373s autopkgtest [11:42:27]: updating testbed package index (apt update) 2373s Get:1 http://ftpmaster.internal/ubuntu questing-proposed InRelease [110 kB] 2373s Hit:2 http://ftpmaster.internal/ubuntu questing InRelease 2373s Hit:3 http://ftpmaster.internal/ubuntu questing-updates InRelease 2373s Hit:4 http://ftpmaster.internal/ubuntu questing-security InRelease 2373s Get:5 http://ftpmaster.internal/ubuntu questing-proposed/multiverse Sources [27.3 kB] 2373s Get:6 http://ftpmaster.internal/ubuntu questing-proposed/universe Sources [595 kB] 2374s Get:7 http://ftpmaster.internal/ubuntu questing-proposed/main Sources [72.4 kB] 2374s Get:8 http://ftpmaster.internal/ubuntu questing-proposed/main ppc64el Packages [139 kB] 2374s Get:9 http://ftpmaster.internal/ubuntu questing-proposed/universe ppc64el Packages [601 kB] 2374s Get:10 http://ftpmaster.internal/ubuntu questing-proposed/multiverse ppc64el Packages [18.1 kB] 2375s Fetched 1563 kB in 2s (857 kB/s) 2375s Reading package lists... 2376s autopkgtest [11:42:30]: upgrading testbed (apt dist-upgrade and autopurge) 2376s Reading package lists... 2376s Building dependency tree... 2376s Reading state information... 2377s Calculating upgrade...Starting pkgProblemResolver with broken count: 0 2377s Starting 2 pkgProblemResolver with broken count: 0 2377s Done 2377s Entering ResolveByKeep 2377s 2377s Calculating upgrade... 2378s The following package was automatically installed and is no longer required: 2378s libsigsegv2 2378s Use 'sudo apt autoremove' to remove it. 2378s The following packages will be upgraded: 2378s dhcpcd-base dirmngr gawk gir1.2-glib-2.0 gnupg gnupg-l10n gnupg-utils gpg 2378s gpg-agent gpg-wks-client gpgconf gpgsm gpgv groff-base keyboxd 2378s libglib2.0-0t64 libglib2.0-data libnuma1 libperl5.40 libpython3.12-minimal 2378s libpython3.12-stdlib libpython3.12t64 libsemanage-common libsemanage2 2378s libx11-6 libx11-data libxml2 numactl openssh-client openssh-server 2378s openssh-sftp-server perl perl-base perl-modules-5.40 python3-dbus 2378s python3-wadllib 2378s 36 upgraded, 0 newly installed, 0 to remove and 0 not upgraded. 2378s Need to get 26.5 MB of archives. 2378s After this operation, 274 kB disk space will be freed. 2378s Get:1 http://ftpmaster.internal/ubuntu questing/main ppc64el libperl5.40 ppc64el 5.40.1-3 [4949 kB] 2383s Get:2 http://ftpmaster.internal/ubuntu questing/main ppc64el perl ppc64el 5.40.1-3 [262 kB] 2383s Get:3 http://ftpmaster.internal/ubuntu questing/main ppc64el perl-base ppc64el 5.40.1-3 [1923 kB] 2384s Get:4 http://ftpmaster.internal/ubuntu questing/main ppc64el perl-modules-5.40 all 5.40.1-3 [3217 kB] 2388s Get:5 http://ftpmaster.internal/ubuntu questing-proposed/main ppc64el gawk ppc64el 1:5.3.2-1 [538 kB] 2390s Get:6 http://ftpmaster.internal/ubuntu questing/main ppc64el openssh-sftp-server ppc64el 1:9.9p1-3ubuntu3.1 [43.4 kB] 2390s Get:7 http://ftpmaster.internal/ubuntu questing/main ppc64el openssh-server ppc64el 1:9.9p1-3ubuntu3.1 [679 kB] 2390s Get:8 http://ftpmaster.internal/ubuntu questing/main ppc64el openssh-client ppc64el 1:9.9p1-3ubuntu3.1 [1168 kB] 2392s Get:9 http://ftpmaster.internal/ubuntu questing/main ppc64el libsemanage-common all 3.8.1-1 [7826 B] 2392s Get:10 http://ftpmaster.internal/ubuntu questing/main ppc64el libsemanage2 ppc64el 3.8.1-1 [121 kB] 2392s Get:11 http://ftpmaster.internal/ubuntu questing/main ppc64el gpg-wks-client ppc64el 2.4.4-2ubuntu24 [84.3 kB] 2392s Get:12 http://ftpmaster.internal/ubuntu questing/main ppc64el dirmngr ppc64el 2.4.4-2ubuntu24 [390 kB] 2392s Get:13 http://ftpmaster.internal/ubuntu questing/main ppc64el gpgsm ppc64el 2.4.4-2ubuntu24 [292 kB] 2393s Get:14 http://ftpmaster.internal/ubuntu questing/main ppc64el gnupg-utils ppc64el 2.4.4-2ubuntu24 [123 kB] 2393s Get:15 http://ftpmaster.internal/ubuntu questing/main ppc64el gpg-agent ppc64el 2.4.4-2ubuntu24 [275 kB] 2393s Get:16 http://ftpmaster.internal/ubuntu questing/main ppc64el gpg ppc64el 2.4.4-2ubuntu24 [707 kB] 2394s Get:17 http://ftpmaster.internal/ubuntu questing/main ppc64el gpgconf ppc64el 2.4.4-2ubuntu24 [115 kB] 2394s Get:18 http://ftpmaster.internal/ubuntu questing/main ppc64el gnupg all 2.4.4-2ubuntu24 [359 kB] 2394s Get:19 http://ftpmaster.internal/ubuntu questing/main ppc64el keyboxd ppc64el 2.4.4-2ubuntu24 [93.1 kB] 2394s Get:20 http://ftpmaster.internal/ubuntu questing/main ppc64el gpgv ppc64el 2.4.4-2ubuntu24 [197 kB] 2395s Get:21 http://ftpmaster.internal/ubuntu questing/main ppc64el dhcpcd-base ppc64el 1:10.1.0-10 [280 kB] 2395s Get:22 http://ftpmaster.internal/ubuntu questing/main ppc64el gir1.2-glib-2.0 ppc64el 2.84.1-2 [184 kB] 2395s Get:23 http://ftpmaster.internal/ubuntu questing/main ppc64el libglib2.0-0t64 ppc64el 2.84.1-2 [1803 kB] 2397s Get:24 http://ftpmaster.internal/ubuntu questing/main ppc64el libglib2.0-data all 2.84.1-2 [53.2 kB] 2397s Get:25 http://ftpmaster.internal/ubuntu questing/main ppc64el libxml2 ppc64el 2.12.7+dfsg+really2.9.14-0.4ubuntu0.1 [836 kB] 2398s Get:26 http://ftpmaster.internal/ubuntu questing/main ppc64el python3-dbus ppc64el 1.4.0-1 [109 kB] 2398s Get:27 http://ftpmaster.internal/ubuntu questing/main ppc64el groff-base ppc64el 1.23.0-8 [1110 kB] 2399s Get:28 http://ftpmaster.internal/ubuntu questing/main ppc64el libnuma1 ppc64el 2.0.19-1 [27.9 kB] 2399s Get:29 http://ftpmaster.internal/ubuntu questing/main ppc64el libx11-data all 2:1.8.12-1 [116 kB] 2399s Get:30 http://ftpmaster.internal/ubuntu questing/main ppc64el libx11-6 ppc64el 2:1.8.12-1 [739 kB] 2399s Get:31 http://ftpmaster.internal/ubuntu questing/main ppc64el numactl ppc64el 2.0.19-1 [43.2 kB] 2399s Get:32 http://ftpmaster.internal/ubuntu questing/main ppc64el gnupg-l10n all 2.4.4-2ubuntu24 [66.8 kB] 2400s Get:33 http://ftpmaster.internal/ubuntu questing-proposed/universe ppc64el libpython3.12t64 ppc64el 3.12.10-1 [2558 kB] 2401s Get:34 http://ftpmaster.internal/ubuntu questing-proposed/universe ppc64el libpython3.12-stdlib ppc64el 3.12.10-1 [2105 kB] 2402s Get:35 http://ftpmaster.internal/ubuntu questing-proposed/universe ppc64el libpython3.12-minimal ppc64el 3.12.10-1 [841 kB] 2403s Get:36 http://ftpmaster.internal/ubuntu questing/main ppc64el python3-wadllib all 2.0.0-3 [36.3 kB] 2403s Preconfiguring packages ... 2403s Fetched 26.5 MB in 25s (1062 kB/s) 2403s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 107214 files and directories currently installed.) 2403s Preparing to unpack .../libperl5.40_5.40.1-3_ppc64el.deb ... 2403s Unpacking libperl5.40:ppc64el (5.40.1-3) over (5.40.1-2) ... 2404s Preparing to unpack .../perl_5.40.1-3_ppc64el.deb ... 2404s Unpacking perl (5.40.1-3) over (5.40.1-2) ... 2404s Preparing to unpack .../perl-base_5.40.1-3_ppc64el.deb ... 2404s Unpacking perl-base (5.40.1-3) over (5.40.1-2) ... 2404s Setting up perl-base (5.40.1-3) ... 2404s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 107214 files and directories currently installed.) 2404s Preparing to unpack .../0-perl-modules-5.40_5.40.1-3_all.deb ... 2404s Unpacking perl-modules-5.40 (5.40.1-3) over (5.40.1-2) ... 2404s Preparing to unpack .../1-gawk_1%3a5.3.2-1_ppc64el.deb ... 2404s Unpacking gawk (1:5.3.2-1) over (1:5.2.1-2build3) ... 2404s Preparing to unpack .../2-openssh-sftp-server_1%3a9.9p1-3ubuntu3.1_ppc64el.deb ... 2404s Unpacking openssh-sftp-server (1:9.9p1-3ubuntu3.1) over (1:9.9p1-3ubuntu3) ... 2404s Preparing to unpack .../3-openssh-server_1%3a9.9p1-3ubuntu3.1_ppc64el.deb ... 2405s Unpacking openssh-server (1:9.9p1-3ubuntu3.1) over (1:9.9p1-3ubuntu3) ... 2405s Preparing to unpack .../4-openssh-client_1%3a9.9p1-3ubuntu3.1_ppc64el.deb ... 2405s Unpacking openssh-client (1:9.9p1-3ubuntu3.1) over (1:9.9p1-3ubuntu3) ... 2405s Preparing to unpack .../5-libsemanage-common_3.8.1-1_all.deb ... 2405s Unpacking libsemanage-common (3.8.1-1) over (3.7-2.1build1) ... 2405s Setting up libsemanage-common (3.8.1-1) ... 2405s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 107216 files and directories currently installed.) 2405s Preparing to unpack .../libsemanage2_3.8.1-1_ppc64el.deb ... 2405s Unpacking libsemanage2:ppc64el (3.8.1-1) over (3.7-2.1build1) ... 2405s Setting up libsemanage2:ppc64el (3.8.1-1) ... 2405s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 107216 files and directories currently installed.) 2405s Preparing to unpack .../0-gpg-wks-client_2.4.4-2ubuntu24_ppc64el.deb ... 2405s Unpacking gpg-wks-client (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 2405s Preparing to unpack .../1-dirmngr_2.4.4-2ubuntu24_ppc64el.deb ... 2405s Unpacking dirmngr (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 2405s Preparing to unpack .../2-gpgsm_2.4.4-2ubuntu24_ppc64el.deb ... 2405s Unpacking gpgsm (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 2405s Preparing to unpack .../3-gnupg-utils_2.4.4-2ubuntu24_ppc64el.deb ... 2405s Unpacking gnupg-utils (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 2405s Preparing to unpack .../4-gpg-agent_2.4.4-2ubuntu24_ppc64el.deb ... 2405s Unpacking gpg-agent (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 2405s Preparing to unpack .../5-gpg_2.4.4-2ubuntu24_ppc64el.deb ... 2405s Unpacking gpg (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 2405s Preparing to unpack .../6-gpgconf_2.4.4-2ubuntu24_ppc64el.deb ... 2405s Unpacking gpgconf (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 2405s Preparing to unpack .../7-gnupg_2.4.4-2ubuntu24_all.deb ... 2405s Unpacking gnupg (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 2405s Preparing to unpack .../8-keyboxd_2.4.4-2ubuntu24_ppc64el.deb ... 2405s Unpacking keyboxd (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 2405s Preparing to unpack .../9-gpgv_2.4.4-2ubuntu24_ppc64el.deb ... 2405s Unpacking gpgv (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 2405s Setting up gpgv (2.4.4-2ubuntu24) ... 2405s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 107216 files and directories currently installed.) 2405s Preparing to unpack .../00-dhcpcd-base_1%3a10.1.0-10_ppc64el.deb ... 2405s Unpacking dhcpcd-base (1:10.1.0-10) over (1:10.1.0-8) ... 2405s Preparing to unpack .../01-gir1.2-glib-2.0_2.84.1-2_ppc64el.deb ... 2405s Unpacking gir1.2-glib-2.0:ppc64el (2.84.1-2) over (2.84.1-1) ... 2405s Preparing to unpack .../02-libglib2.0-0t64_2.84.1-2_ppc64el.deb ... 2405s Unpacking libglib2.0-0t64:ppc64el (2.84.1-2) over (2.84.1-1) ... 2405s Preparing to unpack .../03-libglib2.0-data_2.84.1-2_all.deb ... 2405s Unpacking libglib2.0-data (2.84.1-2) over (2.84.1-1) ... 2405s Preparing to unpack .../04-libxml2_2.12.7+dfsg+really2.9.14-0.4ubuntu0.1_ppc64el.deb ... 2405s Unpacking libxml2:ppc64el (2.12.7+dfsg+really2.9.14-0.4ubuntu0.1) over (2.12.7+dfsg+really2.9.14-0.4) ... 2405s Preparing to unpack .../05-python3-dbus_1.4.0-1_ppc64el.deb ... 2405s Unpacking python3-dbus (1.4.0-1) over (1.3.2-5build5) ... 2405s Preparing to unpack .../06-groff-base_1.23.0-8_ppc64el.deb ... 2405s Unpacking groff-base (1.23.0-8) over (1.23.0-7) ... 2405s Preparing to unpack .../07-libnuma1_2.0.19-1_ppc64el.deb ... 2405s Unpacking libnuma1:ppc64el (2.0.19-1) over (2.0.18-1build1) ... 2405s Preparing to unpack .../08-libx11-data_2%3a1.8.12-1_all.deb ... 2405s Unpacking libx11-data (2:1.8.12-1) over (2:1.8.10-2) ... 2406s Preparing to unpack .../09-libx11-6_2%3a1.8.12-1_ppc64el.deb ... 2406s Unpacking libx11-6:ppc64el (2:1.8.12-1) over (2:1.8.10-2) ... 2406s Preparing to unpack .../10-numactl_2.0.19-1_ppc64el.deb ... 2406s Unpacking numactl (2.0.19-1) over (2.0.18-1build1) ... 2406s Preparing to unpack .../11-gnupg-l10n_2.4.4-2ubuntu24_all.deb ... 2406s Unpacking gnupg-l10n (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 2406s Preparing to unpack .../12-libpython3.12t64_3.12.10-1_ppc64el.deb ... 2406s Unpacking libpython3.12t64:ppc64el (3.12.10-1) over (3.12.8-3) ... 2406s Preparing to unpack .../13-libpython3.12-stdlib_3.12.10-1_ppc64el.deb ... 2406s Unpacking libpython3.12-stdlib:ppc64el (3.12.10-1) over (3.12.8-3) ... 2406s Preparing to unpack .../14-libpython3.12-minimal_3.12.10-1_ppc64el.deb ... 2406s Unpacking libpython3.12-minimal:ppc64el (3.12.10-1) over (3.12.8-3) ... 2406s Preparing to unpack .../15-python3-wadllib_2.0.0-3_all.deb ... 2406s Unpacking python3-wadllib (2.0.0-3) over (2.0.0-2) ... 2406s Setting up gawk (1:5.3.2-1) ... 2406s Setting up openssh-client (1:9.9p1-3ubuntu3.1) ... 2406s Setting up libpython3.12-minimal:ppc64el (3.12.10-1) ... 2406s Setting up libglib2.0-0t64:ppc64el (2.84.1-2) ... 2406s No schema files found: doing nothing. 2406s Setting up libglib2.0-data (2.84.1-2) ... 2406s Setting up libx11-data (2:1.8.12-1) ... 2406s Setting up gnupg-l10n (2.4.4-2ubuntu24) ... 2406s Setting up python3-wadllib (2.0.0-3) ... 2406s Setting up dhcpcd-base (1:10.1.0-10) ... 2406s Installing new version of config file /etc/dhcpcd.conf ... 2406s Setting up gir1.2-glib-2.0:ppc64el (2.84.1-2) ... 2406s Setting up libnuma1:ppc64el (2.0.19-1) ... 2406s Setting up perl-modules-5.40 (5.40.1-3) ... 2406s Setting up groff-base (1.23.0-8) ... 2406s Setting up gpgconf (2.4.4-2ubuntu24) ... 2406s Setting up libx11-6:ppc64el (2:1.8.12-1) ... 2406s Setting up libxml2:ppc64el (2.12.7+dfsg+really2.9.14-0.4ubuntu0.1) ... 2406s Setting up gpg (2.4.4-2ubuntu24) ... 2406s Setting up gnupg-utils (2.4.4-2ubuntu24) ... 2406s Setting up openssh-sftp-server (1:9.9p1-3ubuntu3.1) ... 2406s Setting up python3-dbus (1.4.0-1) ... 2406s Setting up gpg-agent (2.4.4-2ubuntu24) ... 2407s Setting up libpython3.12-stdlib:ppc64el (3.12.10-1) ... 2407s Setting up numactl (2.0.19-1) ... 2407s Setting up openssh-server (1:9.9p1-3ubuntu3.1) ... 2408s Setting up gpgsm (2.4.4-2ubuntu24) ... 2408s Setting up libpython3.12t64:ppc64el (3.12.10-1) ... 2408s Setting up libperl5.40:ppc64el (5.40.1-3) ... 2408s Setting up dirmngr (2.4.4-2ubuntu24) ... 2408s Setting up perl (5.40.1-3) ... 2408s Setting up keyboxd (2.4.4-2ubuntu24) ... 2408s Setting up gnupg (2.4.4-2ubuntu24) ... 2408s Setting up gpg-wks-client (2.4.4-2ubuntu24) ... 2408s Processing triggers for ufw (0.36.2-9) ... 2408s Processing triggers for man-db (2.13.1-1) ... 2410s Processing triggers for install-info (7.1.1-1) ... 2410s Processing triggers for libc-bin (2.41-6ubuntu1) ... 2411s Reading package lists... 2411s Building dependency tree... 2411s Reading state information... 2411s Starting pkgProblemResolver with broken count: 0 2411s Starting 2 pkgProblemResolver with broken count: 0 2411s Done 2411s Solving dependencies... 2411s The following packages will be REMOVED: 2411s libsigsegv2* 2412s 0 upgraded, 0 newly installed, 1 to remove and 0 not upgraded. 2412s After this operation, 96.3 kB disk space will be freed. 2412s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 107216 files and directories currently installed.) 2412s Removing libsigsegv2:ppc64el (2.14-1ubuntu2) ... 2412s Processing triggers for libc-bin (2.41-6ubuntu1) ... 2412s autopkgtest [11:43:06]: rebooting testbed after setup commands that affected boot 2448s Reading package lists... 2449s Building dependency tree... 2449s Reading state information... 2449s Starting pkgProblemResolver with broken count: 0 2449s Starting 2 pkgProblemResolver with broken count: 0 2449s Done 2449s The following NEW packages will be installed: 2449s libtcl8.6 python3-click yosys yosys-abc 2449s 0 upgraded, 4 newly installed, 0 to remove and 0 not upgraded. 2449s Need to get 12.2 MB of archives. 2449s After this operation, 41.9 MB of additional disk space will be used. 2449s Get:1 http://ftpmaster.internal/ubuntu questing/main ppc64el libtcl8.6 ppc64el 8.6.16+dfsg-1 [1201 kB] 2450s Get:2 http://ftpmaster.internal/ubuntu questing/main ppc64el python3-click all 8.2.0+0.really.8.1.8-1 [80.0 kB] 2450s Get:3 http://ftpmaster.internal/ubuntu questing/universe ppc64el yosys-abc ppc64el 0.33-5build2 [7747 kB] 2454s Get:4 http://ftpmaster.internal/ubuntu questing/universe ppc64el yosys ppc64el 0.33-5build2 [3190 kB] 2456s Fetched 12.2 MB in 6s (1948 kB/s) 2456s Selecting previously unselected package libtcl8.6:ppc64el. 2456s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 107209 files and directories currently installed.) 2456s Preparing to unpack .../libtcl8.6_8.6.16+dfsg-1_ppc64el.deb ... 2456s Unpacking libtcl8.6:ppc64el (8.6.16+dfsg-1) ... 2456s Selecting previously unselected package python3-click. 2456s Preparing to unpack .../python3-click_8.2.0+0.really.8.1.8-1_all.deb ... 2456s Unpacking python3-click (8.2.0+0.really.8.1.8-1) ... 2456s Selecting previously unselected package yosys-abc. 2456s Preparing to unpack .../yosys-abc_0.33-5build2_ppc64el.deb ... 2456s Unpacking yosys-abc (0.33-5build2) ... 2456s Selecting previously unselected package yosys. 2456s Preparing to unpack .../yosys_0.33-5build2_ppc64el.deb ... 2456s Unpacking yosys (0.33-5build2) ... 2456s Setting up yosys-abc (0.33-5build2) ... 2456s Setting up python3-click (8.2.0+0.really.8.1.8-1) ... 2457s Setting up libtcl8.6:ppc64el (8.6.16+dfsg-1) ... 2457s Setting up yosys (0.33-5build2) ... 2457s Processing triggers for libc-bin (2.41-6ubuntu1) ... 2457s Processing triggers for man-db (2.13.1-1) ... 2466s autopkgtest [11:44:00]: test ice: [----------------------- 2466s 2466s /----------------------------------------------------------------------------\ 2466s | | 2466s | yosys -- Yosys Open SYnthesis Suite | 2466s | | 2466s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2466s | | 2466s | Permission to use, copy, modify, and/or distribute this software for any | 2466s | purpose with or without fee is hereby granted, provided that the above | 2466s | copyright notice and this permission notice appear in all copies. | 2466s | | 2466s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2466s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2466s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2466s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2466s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2466s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2466s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2466s | | 2466s \----------------------------------------------------------------------------/ 2466s 2466s Yosys 0.33 (git sha1 2584903a060) 2466s 2466s 2466s -- Running command `read_verilog debian/tests/design_ice.v; synth_ice40 -blif /tmp/autopkgtest.qrrc6z/autopkgtest_tmp/design_ice.blif' -- 2466s 2466s 1. Executing Verilog-2005 frontend: debian/tests/design_ice.v 2466s Parsing Verilog input from `debian/tests/design_ice.v' to AST representation. 2466s Generating RTLIL representation for module `\design_ice'. 2466s Successfully finished Verilog frontend. 2466s 2466s 2. Executing SYNTH_ICE40 pass. 2466s 2466s 2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v 2466s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation. 2466s Generating RTLIL representation for module `\SB_IO'. 2466s Generating RTLIL representation for module `\SB_GB_IO'. 2466s Generating RTLIL representation for module `\SB_GB'. 2466s Generating RTLIL representation for module `\SB_LUT4'. 2466s Generating RTLIL representation for module `\SB_CARRY'. 2466s Generating RTLIL representation for module `\SB_DFF'. 2466s Generating RTLIL representation for module `\SB_DFFE'. 2466s Generating RTLIL representation for module `\SB_DFFSR'. 2466s Generating RTLIL representation for module `\SB_DFFR'. 2466s Generating RTLIL representation for module `\SB_DFFSS'. 2466s Generating RTLIL representation for module `\SB_DFFS'. 2466s Generating RTLIL representation for module `\SB_DFFESR'. 2466s Generating RTLIL representation for module `\SB_DFFER'. 2466s Generating RTLIL representation for module `\SB_DFFESS'. 2466s Generating RTLIL representation for module `\SB_DFFES'. 2466s Generating RTLIL representation for module `\SB_DFFN'. 2466s Generating RTLIL representation for module `\SB_DFFNE'. 2466s Generating RTLIL representation for module `\SB_DFFNSR'. 2466s Generating RTLIL representation for module `\SB_DFFNR'. 2466s Generating RTLIL representation for module `\SB_DFFNSS'. 2466s Generating RTLIL representation for module `\SB_DFFNS'. 2466s Generating RTLIL representation for module `\SB_DFFNESR'. 2466s Generating RTLIL representation for module `\SB_DFFNER'. 2466s Generating RTLIL representation for module `\SB_DFFNESS'. 2466s Generating RTLIL representation for module `\SB_DFFNES'. 2466s Generating RTLIL representation for module `\SB_RAM40_4K'. 2466s Generating RTLIL representation for module `\SB_RAM40_4KNR'. 2466s Generating RTLIL representation for module `\SB_RAM40_4KNW'. 2466s Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. 2466s Generating RTLIL representation for module `\ICESTORM_LC'. 2466s Generating RTLIL representation for module `\SB_PLL40_CORE'. 2466s Generating RTLIL representation for module `\SB_PLL40_PAD'. 2466s Generating RTLIL representation for module `\SB_PLL40_2_PAD'. 2466s Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. 2466s Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. 2466s Generating RTLIL representation for module `\SB_WARMBOOT'. 2466s Generating RTLIL representation for module `\SB_SPRAM256KA'. 2466s Generating RTLIL representation for module `\SB_HFOSC'. 2466s Generating RTLIL representation for module `\SB_LFOSC'. 2466s Generating RTLIL representation for module `\SB_RGBA_DRV'. 2466s Generating RTLIL representation for module `\SB_LED_DRV_CUR'. 2466s Generating RTLIL representation for module `\SB_RGB_DRV'. 2466s Generating RTLIL representation for module `\SB_I2C'. 2466s Generating RTLIL representation for module `\SB_SPI'. 2466s Generating RTLIL representation for module `\SB_LEDDA_IP'. 2466s Generating RTLIL representation for module `\SB_FILTER_50NS'. 2466s Generating RTLIL representation for module `\SB_IO_I3C'. 2466s Generating RTLIL representation for module `\SB_IO_OD'. 2466s Generating RTLIL representation for module `\SB_MAC16'. 2466s Generating RTLIL representation for module `\ICESTORM_RAM'. 2466s Successfully finished Verilog frontend. 2466s 2466s 2.2. Executing HIERARCHY pass (managing design hierarchy). 2466s 2466s 2.2.1. Finding top of design hierarchy.. 2466s root of 0 design levels: design_ice 2466s Automatically selected design_ice as design top module. 2466s 2466s 2.2.2. Analyzing design hierarchy.. 2466s Top module: \design_ice 2466s 2466s 2.2.3. Analyzing design hierarchy.. 2466s Top module: \design_ice 2466s Removed 0 unused modules. 2466s 2466s 2.3. Executing PROC pass (convert processes to netlists). 2466s 2466s 2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2466s Cleaned up 0 empty switches. 2466s 2466s 2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2466s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243 in module SB_DFFNES. 2466s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236 in module SB_DFFNESS. 2466s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232 in module SB_DFFNER. 2466s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225 in module SB_DFFNESR. 2466s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222 in module SB_DFFNS. 2466s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219 in module SB_DFFNSS. 2466s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216 in module SB_DFFNR. 2466s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213 in module SB_DFFNSR. 2466s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205 in module SB_DFFES. 2466s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198 in module SB_DFFESS. 2466s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194 in module SB_DFFER. 2466s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187 in module SB_DFFESR. 2466s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184 in module SB_DFFS. 2466s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181 in module SB_DFFSS. 2466s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178 in module SB_DFFR. 2466s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175 in module SB_DFFSR. 2466s Marked 1 switch rules as full_case in process $proc$debian/tests/design_ice.v:6$1 in module design_ice. 2466s Removed a total of 0 dead cases. 2466s 2466s 2.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2466s Removed 8 redundant assignments. 2466s Promoted 23 assignments to connections. 2466s 2466s 2.3.4. Executing PROC_INIT pass (extract init attributes). 2466s Found init rule in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$246'. 2466s Set init value: \Q = 1'0 2466s Found init rule in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$242'. 2466s Set init value: \Q = 1'0 2466s Found init rule in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$235'. 2466s Set init value: \Q = 1'0 2466s Found init rule in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$231'. 2466s Set init value: \Q = 1'0 2466s Found init rule in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$224'. 2466s Set init value: \Q = 1'0 2466s Found init rule in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$221'. 2466s Set init value: \Q = 1'0 2466s Found init rule in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$218'. 2466s Set init value: \Q = 1'0 2466s Found init rule in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$215'. 2466s Set init value: \Q = 1'0 2466s Found init rule in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$212'. 2466s Set init value: \Q = 1'0 2466s Found init rule in `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 2466s Set init value: \Q = 1'0 2466s Found init rule in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 2466s Set init value: \Q = 1'0 2466s Found init rule in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$204'. 2466s Set init value: \Q = 1'0 2466s Found init rule in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$197'. 2466s Set init value: \Q = 1'0 2466s Found init rule in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$193'. 2466s Set init value: \Q = 1'0 2466s Found init rule in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$186'. 2466s Set init value: \Q = 1'0 2466s Found init rule in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$183'. 2466s Set init value: \Q = 1'0 2466s Found init rule in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$180'. 2466s Set init value: \Q = 1'0 2466s Found init rule in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$177'. 2466s Set init value: \Q = 1'0 2466s Found init rule in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$174'. 2466s Set init value: \Q = 1'0 2466s Found init rule in `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 2466s Set init value: \Q = 1'0 2466s Found init rule in `\design_ice.$proc$debian/tests/design_ice.v:3$2'. 2466s Set init value: \ready = 1'0 2466s 2466s 2.3.5. Executing PROC_ARST pass (detect async resets in processes). 2466s Found async reset \S in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'. 2466s Found async reset \R in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'. 2466s Found async reset \S in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222'. 2466s Found async reset \R in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216'. 2466s Found async reset \S in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'. 2466s Found async reset \R in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'. 2466s Found async reset \S in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184'. 2466s Found async reset \R in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178'. 2466s 2466s 2.3.6. Executing PROC_ROM pass (convert switches to ROMs). 2466s Converted 0 switches. 2466s 2466s 2466s 2.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2466s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$246'. 2466s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'. 2466s 1/1: $0\Q[0:0] 2466s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$242'. 2466s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236'. 2466s 1/1: $0\Q[0:0] 2466s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$235'. 2466s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'. 2466s 1/1: $0\Q[0:0] 2466s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$231'. 2466s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225'. 2466s 1/1: $0\Q[0:0] 2466s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$224'. 2466s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222'. 2466s 1/1: $0\Q[0:0] 2466s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$221'. 2466s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219'. 2466s 1/1: $0\Q[0:0] 2466s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$218'. 2466s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216'. 2466s 1/1: $0\Q[0:0] 2466s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$215'. 2466s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213'. 2466s 1/1: $0\Q[0:0] 2466s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$212'. 2466s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$211'. 2466s 1/1: $0\Q[0:0] 2466s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 2466s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$209'. 2466s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 2466s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'. 2466s 1/1: $0\Q[0:0] 2466s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$204'. 2466s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198'. 2466s 1/1: $0\Q[0:0] 2466s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$197'. 2466s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'. 2466s 1/1: $0\Q[0:0] 2466s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$193'. 2466s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187'. 2466s 1/1: $0\Q[0:0] 2466s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$186'. 2466s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184'. 2466s 1/1: $0\Q[0:0] 2466s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$183'. 2466s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181'. 2466s 1/1: $0\Q[0:0] 2466s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$180'. 2466s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178'. 2466s 1/1: $0\Q[0:0] 2466s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$177'. 2466s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175'. 2466s 1/1: $0\Q[0:0] 2466s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$174'. 2466s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$173'. 2466s 1/1: $0\Q[0:0] 2466s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 2466s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$171'. 2466s Creating decoders for process `\design_ice.$proc$debian/tests/design_ice.v:3$2'. 2466s Creating decoders for process `\design_ice.$proc$debian/tests/design_ice.v:6$1'. 2466s 1/2: $0\value[0:0] 2466s 2/2: $0\ready[0:0] 2466s 2466s 2.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2466s 2466s 2.3.9. Executing PROC_DFF pass (convert process syncs to FFs). 2466s Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'. 2466s created $adff cell `$procdff$433' with negative edge clock and positive level reset. 2466s Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236'. 2466s created $dff cell `$procdff$434' with negative edge clock. 2466s Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'. 2466s created $adff cell `$procdff$435' with negative edge clock and positive level reset. 2466s Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225'. 2466s created $dff cell `$procdff$436' with negative edge clock. 2466s Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222'. 2466s created $adff cell `$procdff$437' with negative edge clock and positive level reset. 2466s Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219'. 2466s created $dff cell `$procdff$438' with negative edge clock. 2466s Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216'. 2466s created $adff cell `$procdff$439' with negative edge clock and positive level reset. 2466s Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213'. 2466s created $dff cell `$procdff$440' with negative edge clock. 2466s Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$211'. 2466s created $dff cell `$procdff$441' with negative edge clock. 2466s Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$209'. 2466s created $dff cell `$procdff$442' with negative edge clock. 2466s Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'. 2466s created $adff cell `$procdff$443' with positive edge clock and positive level reset. 2466s Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198'. 2466s created $dff cell `$procdff$444' with positive edge clock. 2466s Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'. 2466s created $adff cell `$procdff$445' with positive edge clock and positive level reset. 2466s Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187'. 2466s created $dff cell `$procdff$446' with positive edge clock. 2466s Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184'. 2466s created $adff cell `$procdff$447' with positive edge clock and positive level reset. 2466s Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181'. 2466s created $dff cell `$procdff$448' with positive edge clock. 2466s Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178'. 2466s created $adff cell `$procdff$449' with positive edge clock and positive level reset. 2466s Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175'. 2466s created $dff cell `$procdff$450' with positive edge clock. 2466s Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$173'. 2466s created $dff cell `$procdff$451' with positive edge clock. 2466s Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$171'. 2466s created $dff cell `$procdff$452' with positive edge clock. 2466s Creating register for signal `\design_ice.\ready' using process `\design_ice.$proc$debian/tests/design_ice.v:6$1'. 2466s created $dff cell `$procdff$453' with positive edge clock. 2466s Creating register for signal `\design_ice.\value' using process `\design_ice.$proc$debian/tests/design_ice.v:6$1'. 2466s created $dff cell `$procdff$454' with positive edge clock. 2466s 2466s 2.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2466s 2466s 2.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2466s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$246'. 2466s Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'. 2466s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'. 2466s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$242'. 2466s Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236'. 2466s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236'. 2466s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$235'. 2466s Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'. 2466s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'. 2466s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$231'. 2466s Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225'. 2466s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225'. 2466s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$224'. 2466s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222'. 2466s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$221'. 2466s Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219'. 2466s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219'. 2466s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$218'. 2466s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216'. 2466s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$215'. 2466s Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213'. 2466s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213'. 2466s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$212'. 2466s Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$211'. 2466s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$211'. 2466s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 2466s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$209'. 2466s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 2466s Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'. 2466s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'. 2466s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$204'. 2466s Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198'. 2466s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198'. 2466s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$197'. 2466s Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'. 2466s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'. 2466s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$193'. 2466s Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187'. 2466s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187'. 2466s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$186'. 2466s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184'. 2466s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$183'. 2466s Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181'. 2466s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181'. 2466s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$180'. 2466s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178'. 2466s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$177'. 2466s Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175'. 2466s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175'. 2466s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$174'. 2466s Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$173'. 2466s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$173'. 2466s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 2466s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$171'. 2466s Removing empty process `design_ice.$proc$debian/tests/design_ice.v:3$2'. 2466s Found and cleaned up 1 empty switch in `\design_ice.$proc$debian/tests/design_ice.v:6$1'. 2466s Removing empty process `design_ice.$proc$debian/tests/design_ice.v:6$1'. 2466s Cleaned up 19 empty switches. 2466s 2466s 2.3.12. Executing OPT_EXPR pass (perform const folding). 2466s Optimizing module design_ice. 2466s 2466s 2.4. Executing FLATTEN pass (flatten design). 2466s 2466s 2.5. Executing TRIBUF pass. 2466s 2466s 2.6. Executing DEMINOUT pass (demote inout ports to input or output). 2466s 2466s 2.7. Executing OPT_EXPR pass (perform const folding). 2466s Optimizing module design_ice. 2466s 2466s 2.8. Executing OPT_CLEAN pass (remove unused cells and wires). 2466s Finding unused cells or wires in module \design_ice.. 2466s Removed 0 unused cells and 5 unused wires. 2466s 2466s 2466s 2.9. Executing CHECK pass (checking for obvious problems). 2466s Checking module design_ice... 2466s Found and reported 0 problems. 2466s 2466s 2.10. Executing OPT pass (performing simple optimizations). 2466s 2466s 2.10.1. Executing OPT_EXPR pass (perform const folding). 2466s Optimizing module design_ice. 2466s 2466s 2.10.2. Executing OPT_MERGE pass (detect identical cells). 2466s Finding identical cells in module `\design_ice'. 2466s Removed a total of 0 cells. 2466s 2466s 2.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 2466s Running muxtree optimizer on module \design_ice.. 2466s Creating internal representation of mux trees. 2466s Evaluating internal representation of mux trees. 2466s Replacing known input bits on port B of cell $procmux$431: \ready -> 1'1 2466s Analyzing evaluation results. 2466s Removed 0 multiplexer ports. 2466s 2466s 2466s 2.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 2466s Optimizing cells in module \design_ice. 2466s Optimizing cells in module \design_ice. 2466s Performed a total of 1 changes. 2466s 2466s 2.10.5. Executing OPT_MERGE pass (detect identical cells). 2466s Finding identical cells in module `\design_ice'. 2466s Removed a total of 0 cells. 2466s 2466s 2.10.6. Executing OPT_DFF pass (perform DFF optimizations). 2466s 2466s 2.10.7. Executing OPT_CLEAN pass (remove unused cells and wires). 2466s Finding unused cells or wires in module \design_ice.. 2466s Removed 0 unused cells and 1 unused wires. 2466s 2466s 2466s 2.10.8. Executing OPT_EXPR pass (perform const folding). 2466s Optimizing module design_ice. 2466s 2466s 2.10.9. Rerunning OPT passes. (Maybe there is more to do..) 2466s 2466s 2.10.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 2466s Running muxtree optimizer on module \design_ice.. 2466s Creating internal representation of mux trees. 2466s Evaluating internal representation of mux trees. 2466s Analyzing evaluation results. 2466s Removed 0 multiplexer ports. 2466s 2466s 2466s 2.10.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 2466s Optimizing cells in module \design_ice. 2466s Performed a total of 0 changes. 2466s 2466s 2.10.12. Executing OPT_MERGE pass (detect identical cells). 2466s Finding identical cells in module `\design_ice'. 2466s Removed a total of 0 cells. 2466s 2466s 2.10.13. Executing OPT_DFF pass (perform DFF optimizations). 2466s 2466s 2.10.14. Executing OPT_CLEAN pass (remove unused cells and wires). 2466s Finding unused cells or wires in module \design_ice.. 2466s 2466s 2.10.15. Executing OPT_EXPR pass (perform const folding). 2466s Optimizing module design_ice. 2466s 2466s 2.10.16. Finished OPT passes. (There is nothing left to do.) 2466s 2466s 2.11. Executing FSM pass (extract and optimize FSM). 2466s 2466s 2.11.1. Executing FSM_DETECT pass (finding FSMs in design). 2466s 2466s 2.11.2. Executing FSM_EXTRACT pass (extracting FSM from design). 2466s 2466s 2.11.3. Executing FSM_OPT pass (simple optimizations of FSMs). 2466s 2466s 2.11.4. Executing OPT_CLEAN pass (remove unused cells and wires). 2466s Finding unused cells or wires in module \design_ice.. 2466s 2466s 2.11.5. Executing FSM_OPT pass (simple optimizations of FSMs). 2466s 2466s 2.11.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 2466s 2466s 2.11.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 2466s 2466s 2.11.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 2466s 2466s 2.12. Executing OPT pass (performing simple optimizations). 2466s 2466s 2.12.1. Executing OPT_EXPR pass (perform const folding). 2466s Optimizing module design_ice. 2466s 2466s 2.12.2. Executing OPT_MERGE pass (detect identical cells). 2466s Finding identical cells in module `\design_ice'. 2466s Removed a total of 0 cells. 2466s 2466s 2.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 2466s Running muxtree optimizer on module \design_ice.. 2466s Creating internal representation of mux trees. 2466s Evaluating internal representation of mux trees. 2466s Analyzing evaluation results. 2466s Removed 0 multiplexer ports. 2466s 2466s 2466s 2.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 2466s Optimizing cells in module \design_ice. 2466s Performed a total of 0 changes. 2466s 2466s 2.12.5. Executing OPT_MERGE pass (detect identical cells). 2466s Finding identical cells in module `\design_ice'. 2466s Removed a total of 0 cells. 2466s 2466s 2.12.6. Executing OPT_DFF pass (perform DFF optimizations). 2466s Adding EN signal on $procdff$454 ($dff) from module design_ice (D = \I1, Q = \value). 2466s 2466s 2.12.7. Executing OPT_CLEAN pass (remove unused cells and wires). 2466s Finding unused cells or wires in module \design_ice.. 2466s Removed 1 unused cells and 1 unused wires. 2466s 2466s 2466s 2.12.8. Executing OPT_EXPR pass (perform const folding). 2466s Optimizing module design_ice. 2466s 2466s 2.12.9. Rerunning OPT passes. (Maybe there is more to do..) 2466s 2466s 2.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 2466s Running muxtree optimizer on module \design_ice.. 2466s Creating internal representation of mux trees. 2466s No muxes found in this module. 2466s Removed 0 multiplexer ports. 2466s 2466s 2.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 2466s Optimizing cells in module \design_ice. 2466s Performed a total of 0 changes. 2466s 2466s 2.12.12. Executing OPT_MERGE pass (detect identical cells). 2466s Finding identical cells in module `\design_ice'. 2466s Removed a total of 0 cells. 2466s 2466s 2.12.13. Executing OPT_DFF pass (perform DFF optimizations). 2466s 2466s 2.12.14. Executing OPT_CLEAN pass (remove unused cells and wires). 2466s Finding unused cells or wires in module \design_ice.. 2466s 2466s 2.12.15. Executing OPT_EXPR pass (perform const folding). 2466s Optimizing module design_ice. 2466s 2466s 2.12.16. Finished OPT passes. (There is nothing left to do.) 2466s 2466s 2.13. Executing WREDUCE pass (reducing word size of cells). 2466s 2466s 2.14. Executing PEEPOPT pass (run peephole optimizers). 2466s 2466s 2.15. Executing OPT_CLEAN pass (remove unused cells and wires). 2466s Finding unused cells or wires in module \design_ice.. 2466s 2466s 2.16. Executing SHARE pass (SAT-based resource sharing). 2466s 2466s 2.17. Executing TECHMAP pass (map to technology primitives). 2466s 2466s 2.17.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v 2466s Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation. 2466s Generating RTLIL representation for module `\_90_lut_cmp_'. 2466s Successfully finished Verilog frontend. 2466s 2466s 2.17.2. Continuing TECHMAP pass. 2466s No more expansions possible. 2466s 2466s 2466s 2.18. Executing OPT_EXPR pass (perform const folding). 2466s Optimizing module design_ice. 2466s 2466s 2.19. Executing OPT_CLEAN pass (remove unused cells and wires). 2466s Finding unused cells or wires in module \design_ice.. 2466s 2466s 2.20. Executing ALUMACC pass (create $alu and $macc cells). 2466s Extracting $alu and $macc cells in module design_ice: 2466s created 0 $alu and 0 $macc cells. 2466s 2466s 2.21. Executing OPT pass (performing simple optimizations). 2466s 2466s 2.21.1. Executing OPT_EXPR pass (perform const folding). 2466s Optimizing module design_ice. 2466s 2466s 2.21.2. Executing OPT_MERGE pass (detect identical cells). 2466s Finding identical cells in module `\design_ice'. 2466s Removed a total of 0 cells. 2466s 2466s 2.21.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 2466s Running muxtree optimizer on module \design_ice.. 2466s Creating internal representation of mux trees. 2466s No muxes found in this module. 2466s Removed 0 multiplexer ports. 2466s 2466s 2.21.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 2466s Optimizing cells in module \design_ice. 2466s Performed a total of 0 changes. 2466s 2466s 2.21.5. Executing OPT_MERGE pass (detect identical cells). 2466s Finding identical cells in module `\design_ice'. 2466s Removed a total of 0 cells. 2466s 2466s 2.21.6. Executing OPT_DFF pass (perform DFF optimizations). 2466s 2466s 2.21.7. Executing OPT_CLEAN pass (remove unused cells and wires). 2466s Finding unused cells or wires in module \design_ice.. 2466s 2466s 2.21.8. Executing OPT_EXPR pass (perform const folding). 2466s Optimizing module design_ice. 2466s 2466s 2.21.9. Finished OPT passes. (There is nothing left to do.) 2466s 2466s 2.22. Executing MEMORY pass. 2466s 2466s 2.22.1. Executing OPT_MEM pass (optimize memories). 2466s Performed a total of 0 transformations. 2466s 2466s 2.22.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). 2466s Performed a total of 0 transformations. 2466s 2466s 2.22.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 2466s 2466s 2.22.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 2466s 2466s 2.22.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 2466s 2466s 2.22.6. Executing OPT_CLEAN pass (remove unused cells and wires). 2466s Finding unused cells or wires in module \design_ice.. 2466s 2466s 2.22.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 2466s 2466s 2.22.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). 2466s Performed a total of 0 transformations. 2466s 2466s 2.22.9. Executing OPT_CLEAN pass (remove unused cells and wires). 2466s Finding unused cells or wires in module \design_ice.. 2466s 2466s 2.22.10. Executing MEMORY_COLLECT pass (generating $mem cells). 2466s 2466s 2.23. Executing OPT_CLEAN pass (remove unused cells and wires). 2466s Finding unused cells or wires in module \design_ice.. 2466s 2466s 2.24. Executing MEMORY_LIBMAP pass (mapping memories to cells). 2466s 2466s 2.25. Executing TECHMAP pass (map to technology primitives). 2466s 2466s 2.25.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v 2467s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation. 2467s Generating RTLIL representation for module `\$__ICE40_RAM4K_'. 2467s Successfully finished Verilog frontend. 2467s 2467s 2.25.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/spram_map.v 2467s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/spram_map.v' to AST representation. 2467s Generating RTLIL representation for module `\$__ICE40_SPRAM_'. 2467s Successfully finished Verilog frontend. 2467s 2467s 2.25.3. Continuing TECHMAP pass. 2467s No more expansions possible. 2467s 2467s 2467s 2.26. Executing ICE40_BRAMINIT pass. 2467s 2467s 2.27. Executing OPT pass (performing simple optimizations). 2467s 2467s 2.27.1. Executing OPT_EXPR pass (perform const folding). 2467s Optimizing module design_ice. 2467s 2467s 2.27.2. Executing OPT_MERGE pass (detect identical cells). 2467s Finding identical cells in module `\design_ice'. 2467s Removed a total of 0 cells. 2467s 2467s 2.27.3. Executing OPT_DFF pass (perform DFF optimizations). 2467s 2467s 2.27.4. Executing OPT_CLEAN pass (remove unused cells and wires). 2467s Finding unused cells or wires in module \design_ice.. 2467s 2467s 2.27.5. Finished fast OPT passes. 2467s 2467s 2.28. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 2467s 2467s 2.29. Executing OPT pass (performing simple optimizations). 2467s 2467s 2.29.1. Executing OPT_EXPR pass (perform const folding). 2467s Optimizing module design_ice. 2467s 2467s 2.29.2. Executing OPT_MERGE pass (detect identical cells). 2467s Finding identical cells in module `\design_ice'. 2467s Removed a total of 0 cells. 2467s 2467s 2.29.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 2467s Running muxtree optimizer on module \design_ice.. 2467s Creating internal representation of mux trees. 2467s No muxes found in this module. 2467s Removed 0 multiplexer ports. 2467s 2467s 2.29.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 2467s Optimizing cells in module \design_ice. 2467s Performed a total of 0 changes. 2467s 2467s 2.29.5. Executing OPT_MERGE pass (detect identical cells). 2467s Finding identical cells in module `\design_ice'. 2467s Removed a total of 0 cells. 2467s 2467s 2.29.6. Executing OPT_DFF pass (perform DFF optimizations). 2467s 2467s 2.29.7. Executing OPT_CLEAN pass (remove unused cells and wires). 2467s Finding unused cells or wires in module \design_ice.. 2467s 2467s 2.29.8. Executing OPT_EXPR pass (perform const folding). 2467s Optimizing module design_ice. 2467s 2467s 2.29.9. Finished OPT passes. (There is nothing left to do.) 2467s 2467s 2.30. Executing ICE40_WRAPCARRY pass (wrap carries). 2467s 2467s 2.31. Executing TECHMAP pass (map to technology primitives). 2467s 2467s 2.31.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v 2467s Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation. 2467s Generating RTLIL representation for module `\_90_simplemap_bool_ops'. 2467s Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. 2467s Generating RTLIL representation for module `\_90_simplemap_logic_ops'. 2467s Generating RTLIL representation for module `\_90_simplemap_compare_ops'. 2467s Generating RTLIL representation for module `\_90_simplemap_various'. 2467s Generating RTLIL representation for module `\_90_simplemap_registers'. 2467s Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. 2467s Generating RTLIL representation for module `\_90_shift_shiftx'. 2467s Generating RTLIL representation for module `\_90_fa'. 2467s Generating RTLIL representation for module `\_90_lcu'. 2467s Generating RTLIL representation for module `\_90_alu'. 2467s Generating RTLIL representation for module `\_90_macc'. 2467s Generating RTLIL representation for module `\_90_alumacc'. 2467s Generating RTLIL representation for module `\$__div_mod_u'. 2467s Generating RTLIL representation for module `\$__div_mod_trunc'. 2467s Generating RTLIL representation for module `\_90_div'. 2467s Generating RTLIL representation for module `\_90_mod'. 2467s Generating RTLIL representation for module `\$__div_mod_floor'. 2467s Generating RTLIL representation for module `\_90_divfloor'. 2467s Generating RTLIL representation for module `\_90_modfloor'. 2467s Generating RTLIL representation for module `\_90_pow'. 2467s Generating RTLIL representation for module `\_90_pmux'. 2467s Generating RTLIL representation for module `\_90_demux'. 2467s Generating RTLIL representation for module `\_90_lut'. 2467s Successfully finished Verilog frontend. 2467s 2467s 2.31.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v 2467s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation. 2467s Generating RTLIL representation for module `\_80_ice40_alu'. 2467s Successfully finished Verilog frontend. 2467s 2467s 2.31.3. Continuing TECHMAP pass. 2467s Using extmapper simplemap for cells of type $dffe. 2467s Using extmapper simplemap for cells of type $dff. 2467s No more expansions possible. 2467s 2467s 2467s 2.32. Executing OPT pass (performing simple optimizations). 2467s 2467s 2.32.1. Executing OPT_EXPR pass (perform const folding). 2467s Optimizing module design_ice. 2467s 2467s 2.32.2. Executing OPT_MERGE pass (detect identical cells). 2467s Finding identical cells in module `\design_ice'. 2467s Removed a total of 0 cells. 2467s 2467s 2.32.3. Executing OPT_DFF pass (perform DFF optimizations). 2467s 2467s 2.32.4. Executing OPT_CLEAN pass (remove unused cells and wires). 2467s Finding unused cells or wires in module \design_ice.. 2467s 2467s 2.32.5. Finished fast OPT passes. 2467s 2467s 2.33. Executing ICE40_OPT pass (performing simple optimizations). 2467s 2467s 2.33.1. Running ICE40 specific optimizations. 2467s 2467s 2.33.2. Executing OPT_EXPR pass (perform const folding). 2467s Optimizing module design_ice. 2467s 2467s 2.33.3. Executing OPT_MERGE pass (detect identical cells). 2467s Finding identical cells in module `\design_ice'. 2467s Removed a total of 0 cells. 2467s 2467s 2.33.4. Executing OPT_DFF pass (perform DFF optimizations). 2467s 2467s 2.33.5. Executing OPT_CLEAN pass (remove unused cells and wires). 2467s Finding unused cells or wires in module \design_ice.. 2467s 2467s 2.33.6. Finished OPT passes. (There is nothing left to do.) 2467s 2467s 2.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 2467s 2467s 2.35. Executing TECHMAP pass (map to technology primitives). 2467s 2467s 2.35.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 2467s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 2467s Generating RTLIL representation for module `\$_DFF_N_'. 2467s Generating RTLIL representation for module `\$_DFF_P_'. 2467s Generating RTLIL representation for module `\$_DFFE_NP_'. 2467s Generating RTLIL representation for module `\$_DFFE_PP_'. 2467s Generating RTLIL representation for module `\$_DFF_NP0_'. 2467s Generating RTLIL representation for module `\$_DFF_NP1_'. 2467s Generating RTLIL representation for module `\$_DFF_PP0_'. 2467s Generating RTLIL representation for module `\$_DFF_PP1_'. 2467s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 2467s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 2467s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 2467s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 2467s Generating RTLIL representation for module `\$_SDFF_NP0_'. 2467s Generating RTLIL representation for module `\$_SDFF_NP1_'. 2467s Generating RTLIL representation for module `\$_SDFF_PP0_'. 2467s Generating RTLIL representation for module `\$_SDFF_PP1_'. 2467s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 2467s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 2467s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 2467s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 2467s Successfully finished Verilog frontend. 2467s 2467s 2.35.2. Continuing TECHMAP pass. 2467s Using template \$_DFF_P_ for cells of type $_DFF_P_. 2467s Using template \$_DFFE_PP_ for cells of type $_DFFE_PP_. 2467s No more expansions possible. 2467s 2467s 2467s 2.36. Executing OPT_EXPR pass (perform const folding). 2467s Optimizing module design_ice. 2467s 2467s 2.37. Executing SIMPLEMAP pass (map simple cells to gate primitives). 2467s 2467s 2.38. Executing ICE40_OPT pass (performing simple optimizations). 2467s 2467s 2.38.1. Running ICE40 specific optimizations. 2467s 2467s 2.38.2. Executing OPT_EXPR pass (perform const folding). 2467s Optimizing module design_ice. 2467s 2467s 2.38.3. Executing OPT_MERGE pass (detect identical cells). 2467s Finding identical cells in module `\design_ice'. 2467s Removed a total of 0 cells. 2467s 2467s 2.38.4. Executing OPT_DFF pass (perform DFF optimizations). 2467s 2467s 2.38.5. Executing OPT_CLEAN pass (remove unused cells and wires). 2467s Finding unused cells or wires in module \design_ice.. 2467s Removed 0 unused cells and 9 unused wires. 2467s 2467s 2467s 2.38.6. Rerunning OPT passes. (Removed registers in this run.) 2467s 2467s 2.38.7. Running ICE40 specific optimizations. 2467s 2467s 2.38.8. Executing OPT_EXPR pass (perform const folding). 2467s Optimizing module design_ice. 2467s 2467s 2.38.9. Executing OPT_MERGE pass (detect identical cells). 2467s Finding identical cells in module `\design_ice'. 2467s Removed a total of 0 cells. 2467s 2467s 2.38.10. Executing OPT_DFF pass (perform DFF optimizations). 2467s 2467s 2.38.11. Executing OPT_CLEAN pass (remove unused cells and wires). 2467s Finding unused cells or wires in module \design_ice.. 2467s 2467s 2.38.12. Finished OPT passes. (There is nothing left to do.) 2467s 2467s 2.39. Executing TECHMAP pass (map to technology primitives). 2467s 2467s 2.39.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v 2467s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation. 2467s Generating RTLIL representation for module `\$_DLATCH_N_'. 2467s Generating RTLIL representation for module `\$_DLATCH_P_'. 2467s Successfully finished Verilog frontend. 2467s 2467s 2.39.2. Continuing TECHMAP pass. 2467s No more expansions possible. 2467s 2467s 2467s 2.40. Executing ABC pass (technology mapping using ABC). 2467s 2467s 2.40.1. Extracting gate netlist of module `\design_ice' to `/input.blif'.. 2467s Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs. 2467s Don't call ABC as there is nothing to map. 2467s Removing temp directory. 2467s 2467s 2.41. Executing ICE40_WRAPCARRY pass (wrap carries). 2467s 2467s 2.42. Executing TECHMAP pass (map to technology primitives). 2467s 2467s 2.42.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 2467s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 2467s Generating RTLIL representation for module `\$_DFF_N_'. 2467s Generating RTLIL representation for module `\$_DFF_P_'. 2467s Generating RTLIL representation for module `\$_DFFE_NP_'. 2467s Generating RTLIL representation for module `\$_DFFE_PP_'. 2467s Generating RTLIL representation for module `\$_DFF_NP0_'. 2467s Generating RTLIL representation for module `\$_DFF_NP1_'. 2467s Generating RTLIL representation for module `\$_DFF_PP0_'. 2467s Generating RTLIL representation for module `\$_DFF_PP1_'. 2467s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 2467s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 2467s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 2467s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 2467s Generating RTLIL representation for module `\$_SDFF_NP0_'. 2467s Generating RTLIL representation for module `\$_SDFF_NP1_'. 2467s Generating RTLIL representation for module `\$_SDFF_PP0_'. 2467s Generating RTLIL representation for module `\$_SDFF_PP1_'. 2467s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 2467s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 2467s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 2467s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 2467s Successfully finished Verilog frontend. 2467s 2467s 2.42.2. Continuing TECHMAP pass. 2467s No more expansions possible. 2467s 2467s 2467s 2.43. Executing OPT_LUT pass (optimize LUTs). 2467s Discovering LUTs. 2467s Number of LUTs: 0 2467s with \SB_CARRY (#0) 0 2467s with \SB_CARRY (#1) 0 2467s 2467s Eliminating LUTs. 2467s Number of LUTs: 0 2467s with \SB_CARRY (#0) 0 2467s with \SB_CARRY (#1) 0 2467s 2467s Combining LUTs. 2467s Number of LUTs: 0 2467s with \SB_CARRY (#0) 0 2467s with \SB_CARRY (#1) 0 2467s 2467s Eliminated 0 LUTs. 2467s Combined 0 LUTs. 2467s 2467s 2.44. Executing TECHMAP pass (map to technology primitives). 2467s 2467s 2.44.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v 2467s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation. 2467s Generating RTLIL representation for module `\$lut'. 2467s Successfully finished Verilog frontend. 2467s 2467s 2.44.2. Continuing TECHMAP pass. 2467s No more expansions possible. 2467s 2467s 2467s 2.45. Executing AUTONAME pass. 2467s Renamed 2 objects in module design_ice (2 iterations). 2467s 2467s 2467s 2.46. Executing HIERARCHY pass (managing design hierarchy). 2467s 2467s 2.46.1. Analyzing design hierarchy.. 2467s Top module: \design_ice 2467s 2467s 2.46.2. Analyzing design hierarchy.. 2467s Top module: \design_ice 2467s Removed 0 unused modules. 2467s 2467s 2.47. Printing statistics. 2467s 2467s === design_ice === 2467s 2467s Number of wires: 5 2467s Number of wire bits: 5 2467s Number of public wires: 5 2467s Number of public wire bits: 5 2467s Number of memories: 0 2467s Number of memory bits: 0 2467s Number of processes: 0 2467s Number of cells: 2 2467s SB_DFF 1 2467s SB_DFFE 1 2467s 2467s 2.48. Executing CHECK pass (checking for obvious problems). 2467s Checking module design_ice... 2467s Found and reported 0 problems. 2467s 2467s 2.49. Executing BLIF backend. 2467s 2467s End of script. Logfile hash: fa5339236c, CPU: user 0.89s system 0.00s, MEM: 20.00 MB peak 2467s Yosys 0.33 (git sha1 2584903a060) 2467s Time spent: 73% 13x read_verilog (0 sec), 8% 1x synth_ice40 (0 sec), ... 2467s autopkgtest [11:44:01]: test ice: -----------------------] 2468s ice PASS 2468s autopkgtest [11:44:02]: test ice: - - - - - - - - - - results - - - - - - - - - - 2468s autopkgtest [11:44:02]: test smtbc: preparing testbed 2468s Reading package lists... 2468s Building dependency tree... 2468s Reading state information... 2469s Starting pkgProblemResolver with broken count: 0 2469s Starting 2 pkgProblemResolver with broken count: 0 2469s Done 2469s 0 upgraded, 0 newly installed, 0 to remove and 0 not upgraded. 2470s autopkgtest [11:44:04]: test smtbc: [----------------------- 2472s autopkgtest [11:44:04]: test smtbc: -----------------------] 2472s smtbc PASS 2472s autopkgtest [11:44:05]: test smtbc: - - - - - - - - - - results - - - - - - - - - - 2472s autopkgtest [11:44:05]: @@@@@@@@@@@@@@@@@@@@ summary 2472s yosys-testsuite PASS 2472s ice PASS 2472s smtbc PASS 2489s nova [W] Using flock in prodstack6-ppc64el 2489s Creating nova instance adt-questing-ppc64el-yosys-20250506-074336-juju-7f2275-prod-proposed-migration-environment-20-ad3c206a-44df-4a60-ac60-fd010cacdeca from image adt/ubuntu-questing-ppc64el-server-20250505.img (UUID 5eb71ea2-eb0e-41c3-98a9-f40539045bc8)... 2489s nova [W] Timed out waiting for dcc7e6c9-cf67-4061-a7de-c5e075cda770 to get deleted. 2489s nova [W] Using flock in prodstack6-ppc64el 2489s Creating nova instance adt-questing-ppc64el-yosys-20250506-074336-juju-7f2275-prod-proposed-migration-environment-20-ad3c206a-44df-4a60-ac60-fd010cacdeca from image adt/ubuntu-questing-ppc64el-server-20250505.img (UUID 5eb71ea2-eb0e-41c3-98a9-f40539045bc8)... 2489s nova [W] Timed out waiting for c746c5ab-5d07-4dc7-8cf6-6678c9738425 to get deleted.