1s autopkgtest [22:19:06]: starting date and time: 2025-05-05 22:19:06+0000
  1s autopkgtest [22:19:06]: git checkout: 9986aa8c Merge branch 'skia/fix_network_interface' into 'ubuntu/production'
  1s autopkgtest [22:19:06]: host juju-7f2275-prod-proposed-migration-environment-9; command line: /home/ubuntu/autopkgtest/runner/autopkgtest --output-dir /tmp/autopkgtest-work.kpnq02mn/out --timeout-copy=6000 --setup-commands 'ln -s /dev/null /etc/systemd/system/bluetooth.service; printf "http_proxy=http://squid.internal:3128\nhttps_proxy=http://squid.internal:3128\nno_proxy=127.0.0.1,127.0.1.1,localhost,localdomain,internal,login.ubuntu.com,archive.ubuntu.com,ports.ubuntu.com,security.ubuntu.com,ddebs.ubuntu.com,changelogs.ubuntu.com,keyserver.ubuntu.com,launchpadlibrarian.net,launchpadcontent.net,launchpad.net,keystone.ps5.canonical.com,objectstorage.prodstack5.canonical.com,radosgw.ps5.canonical.com\n" >> /etc/environment' --apt-pocket=proposed=src:gawk --apt-upgrade yosys --timeout-short=300 --timeout-copy=20000 --timeout-build=20000 --env=ADT_TEST_TRIGGERS=gawk/1:5.3.2-1 -- lxd -r lxd-armhf-10.145.243.171 lxd-armhf-10.145.243.171:autopkgtest/ubuntu/questing/armhf
 21s autopkgtest [22:19:26]: testbed dpkg architecture: armhf
 23s autopkgtest [22:19:28]: testbed apt version: 3.0.0
 26s autopkgtest [22:19:31]: @@@@@@@@@@@@@@@@@@@@ test bed setup
 28s autopkgtest [22:19:33]: testbed release detected to be: None
 35s autopkgtest [22:19:40]: updating testbed package index (apt update)
 37s Get:1 http://ftpmaster.internal/ubuntu questing-proposed InRelease [110 kB]
 38s Get:2 http://ftpmaster.internal/ubuntu questing InRelease [110 kB]
 38s Get:3 http://ftpmaster.internal/ubuntu questing-updates InRelease [110 kB]
 38s Get:4 http://ftpmaster.internal/ubuntu questing-security InRelease [110 kB]
 38s Get:5 http://ftpmaster.internal/ubuntu questing-proposed/universe Sources [818 kB]
 38s Get:6 http://ftpmaster.internal/ubuntu questing-proposed/main Sources [86.1 kB]
 38s Get:7 http://ftpmaster.internal/ubuntu questing-proposed/multiverse Sources [30.0 kB]
 38s Get:8 http://ftpmaster.internal/ubuntu questing-proposed/main armhf Packages [115 kB]
 38s Get:9 http://ftpmaster.internal/ubuntu questing-proposed/universe armhf Packages [853 kB]
 38s Get:10 http://ftpmaster.internal/ubuntu questing-proposed/multiverse armhf Packages [16.2 kB]
 38s Get:11 http://ftpmaster.internal/ubuntu questing/main Sources [1396 kB]
 38s Get:12 http://ftpmaster.internal/ubuntu questing/multiverse Sources [307 kB]
 38s Get:13 http://ftpmaster.internal/ubuntu questing/universe Sources [21.3 MB]
 39s Get:14 http://ftpmaster.internal/ubuntu questing/main armhf Packages [1358 kB]
 39s Get:15 http://ftpmaster.internal/ubuntu questing/universe armhf Packages [15.1 MB]
 39s Get:16 http://ftpmaster.internal/ubuntu questing/multiverse armhf Packages [181 kB]
 43s Fetched 42.0 MB in 5s (8045 kB/s)
 44s Reading package lists...
 50s autopkgtest [22:19:55]: upgrading testbed (apt dist-upgrade and autopurge)
 51s Reading package lists...
 52s Building dependency tree...
 52s Reading state information...
 53s Calculating upgrade...Starting pkgProblemResolver with broken count: 0
 53s Starting 2 pkgProblemResolver with broken count: 0
 53s Done
 54s Entering ResolveByKeep
 54s 
 55s Calculating upgrade...
 55s The following package was automatically installed and is no longer required:
 55s   libsigsegv2
 55s Use 'apt autoremove' to remove it.
 55s The following packages will be upgraded:
 55s   base-files base-passwd btrfs-progs cloud-init cloud-init-base debianutils
 55s   dhcpcd-base diffutils dirmngr distro-info-data dpkg dpkg-dev ed ethtool
 55s   fwupd gawk gettext-base gir1.2-glib-2.0 gnupg gnupg-l10n gnupg-utils gpg
 55s   gpg-agent gpg-wks-client gpgconf gpgsm gpgv groff-base htop iso-codes
 55s   keyboxd less libbpf1 libdpkg-perl libevdev2 libftdi1-2 libfwupd3
 55s   libglib2.0-0t64 libglib2.0-data libgpg-error-l10n libgpg-error0 libjcat1
 55s   libmbim-glib4 libmbim-proxy libmm-glib0 libnftnl11 libnghttp2-14 libnpth0t64
 55s   libnuma1 libnvme1t64 libqmi-glib5 libqmi-proxy libselinux1 libsensors-config
 55s   libsensors5 libsepol2 libunistring5 liburcu8t64 libusb-1.0-0 libx11-6
 55s   libx11-data libxml2 man-db motd-news-config nano netbase netcat-openbsd
 55s   numactl openssh-client openssh-server openssh-sftp-server patch publicsuffix
 55s   python3-attr python3-lazr.restfulclient python3-more-itertools
 55s   python3-packaging python3-s3transfer python3-wadllib sos ubuntu-pro-client
 55s   ubuntu-pro-client-l10n usb.ids usbutils
 56s 84 upgraded, 0 newly installed, 0 to remove and 0 not upgraded.
 56s Need to get 25.2 MB of archives.
 56s After this operation, 275 kB of additional disk space will be used.
 56s Get:1 http://ftpmaster.internal/ubuntu questing/main armhf motd-news-config all 13.7ubuntu1 [5260 B]
 56s Get:2 http://ftpmaster.internal/ubuntu questing/main armhf base-files armhf 13.7ubuntu1 [75.4 kB]
 56s Get:3 http://ftpmaster.internal/ubuntu questing/main armhf debianutils armhf 5.22 [92.2 kB]
 56s Get:4 http://ftpmaster.internal/ubuntu questing/main armhf diffutils armhf 1:3.10-4 [172 kB]
 56s Get:5 http://ftpmaster.internal/ubuntu questing/main armhf dpkg armhf 1.22.18ubuntu3 [1254 kB]
 56s Get:6 http://ftpmaster.internal/ubuntu questing/main armhf libselinux1 armhf 3.8.1-1 [80.4 kB]
 56s Get:7 http://ftpmaster.internal/ubuntu questing/main armhf base-passwd armhf 3.6.7 [53.9 kB]
 56s Get:8 http://ftpmaster.internal/ubuntu questing-proposed/main armhf gawk armhf 1:5.3.2-1 [468 kB]
 56s Get:9 http://ftpmaster.internal/ubuntu questing/main armhf openssh-sftp-server armhf 1:9.9p1-3ubuntu3.1 [35.7 kB]
 56s Get:10 http://ftpmaster.internal/ubuntu questing/main armhf openssh-server armhf 1:9.9p1-3ubuntu3.1 [532 kB]
 56s Get:11 http://ftpmaster.internal/ubuntu questing/main armhf openssh-client armhf 1:9.9p1-3ubuntu3.1 [924 kB]
 56s Get:12 http://ftpmaster.internal/ubuntu questing/main armhf libsepol2 armhf 3.8.1-1 [282 kB]
 56s Get:13 http://ftpmaster.internal/ubuntu questing/main armhf libgpg-error-l10n all 1.51-4 [8880 B]
 56s Get:14 http://ftpmaster.internal/ubuntu questing/main armhf libgpg-error0 armhf 1.51-4 [64.6 kB]
 56s Get:15 http://ftpmaster.internal/ubuntu questing/main armhf libnpth0t64 armhf 1.8-3 [7716 B]
 56s Get:16 http://ftpmaster.internal/ubuntu questing/main armhf gpg-wks-client armhf 2.4.4-2ubuntu24 [87.5 kB]
 56s Get:17 http://ftpmaster.internal/ubuntu questing/main armhf dirmngr armhf 2.4.4-2ubuntu24 [348 kB]
 56s Get:18 http://ftpmaster.internal/ubuntu questing/main armhf gpgsm armhf 2.4.4-2ubuntu24 [242 kB]
 56s Get:19 http://ftpmaster.internal/ubuntu questing/main armhf gnupg-utils armhf 2.4.4-2ubuntu24 [160 kB]
 56s Get:20 http://ftpmaster.internal/ubuntu questing/main armhf gpg-agent armhf 2.4.4-2ubuntu24 [237 kB]
 56s Get:21 http://ftpmaster.internal/ubuntu questing/main armhf gpg armhf 2.4.4-2ubuntu24 [525 kB]
 56s Get:22 http://ftpmaster.internal/ubuntu questing/main armhf gpgconf armhf 2.4.4-2ubuntu24 [117 kB]
 56s Get:23 http://ftpmaster.internal/ubuntu questing/main armhf gnupg all 2.4.4-2ubuntu24 [359 kB]
 56s Get:24 http://ftpmaster.internal/ubuntu questing/main armhf keyboxd armhf 2.4.4-2ubuntu24 [112 kB]
 56s Get:25 http://ftpmaster.internal/ubuntu questing/main armhf gpgv armhf 2.4.4-2ubuntu24 [225 kB]
 56s Get:26 http://ftpmaster.internal/ubuntu questing/main armhf dhcpcd-base armhf 1:10.1.0-10 [189 kB]
 56s Get:27 http://ftpmaster.internal/ubuntu questing/main armhf distro-info-data all 0.64 [6664 B]
 56s Get:28 http://ftpmaster.internal/ubuntu questing/main armhf gir1.2-glib-2.0 armhf 2.84.1-2 [185 kB]
 56s Get:29 http://ftpmaster.internal/ubuntu questing/main armhf libglib2.0-0t64 armhf 2.84.1-2 [1455 kB]
 56s Get:30 http://ftpmaster.internal/ubuntu questing/main armhf iso-codes all 4.18.0-1 [3703 kB]
 56s Get:31 http://ftpmaster.internal/ubuntu questing/main armhf less armhf 668-1 [158 kB]
 56s Get:32 http://ftpmaster.internal/ubuntu questing/main armhf libbpf1 armhf 1:1.5.0-3 [158 kB]
 56s Get:33 http://ftpmaster.internal/ubuntu questing/main armhf libglib2.0-data all 2.84.1-2 [53.2 kB]
 56s Get:34 http://ftpmaster.internal/ubuntu questing/main armhf libunistring5 armhf 1.3-2 [583 kB]
 56s Get:35 http://ftpmaster.internal/ubuntu questing/main armhf libxml2 armhf 2.12.7+dfsg+really2.9.14-0.4ubuntu0.1 [599 kB]
 56s Get:36 http://ftpmaster.internal/ubuntu questing/main armhf netbase all 6.5 [12.9 kB]
 56s Get:37 http://ftpmaster.internal/ubuntu questing/main armhf netcat-openbsd armhf 1.229-1 [42.4 kB]
 56s Get:38 http://ftpmaster.internal/ubuntu questing/main armhf ubuntu-pro-client-l10n armhf 35.1ubuntu0 [19.7 kB]
 56s Get:39 http://ftpmaster.internal/ubuntu questing/main armhf ubuntu-pro-client armhf 35.1ubuntu0 [258 kB]
 57s Get:40 http://ftpmaster.internal/ubuntu questing/main armhf ed armhf 1.21.1-1 [53.0 kB]
 57s Get:41 http://ftpmaster.internal/ubuntu questing/main armhf ethtool armhf 1:6.14-2 [230 kB]
 57s Get:42 http://ftpmaster.internal/ubuntu questing/main armhf gettext-base armhf 0.23.1-2 [43.5 kB]
 57s Get:43 http://ftpmaster.internal/ubuntu questing/main armhf groff-base armhf 1.23.0-8 [942 kB]
 57s Get:44 http://ftpmaster.internal/ubuntu questing/main armhf libevdev2 armhf 1.13.4+dfsg-1 [29.8 kB]
 57s Get:45 http://ftpmaster.internal/ubuntu questing/main armhf libnftnl11 armhf 1.2.9-1 [53.3 kB]
 57s Get:46 http://ftpmaster.internal/ubuntu questing/main armhf libnghttp2-14 armhf 1.64.0-1.1 [68.5 kB]
 57s Get:47 http://ftpmaster.internal/ubuntu questing/main armhf libnuma1 armhf 2.0.19-1 [19.9 kB]
 57s Get:48 http://ftpmaster.internal/ubuntu questing/main armhf libsensors-config all 1:3.6.2-2 [6756 B]
 57s Get:49 http://ftpmaster.internal/ubuntu questing/main armhf libsensors5 armhf 1:3.6.2-2 [26.8 kB]
 57s Get:50 http://ftpmaster.internal/ubuntu questing/main armhf liburcu8t64 armhf 0.15.2-2 [57.3 kB]
 57s Get:51 http://ftpmaster.internal/ubuntu questing/main armhf libusb-1.0-0 armhf 2:1.0.28-1 [50.0 kB]
 57s Get:52 http://ftpmaster.internal/ubuntu questing/main armhf libx11-data all 2:1.8.12-1 [116 kB]
 57s Get:53 http://ftpmaster.internal/ubuntu questing/main armhf libx11-6 armhf 2:1.8.12-1 [586 kB]
 57s Get:54 http://ftpmaster.internal/ubuntu questing/main armhf man-db armhf 2.13.1-1 [1341 kB]
 57s Get:55 http://ftpmaster.internal/ubuntu questing/main armhf nano armhf 8.4-1 [278 kB]
 57s Get:56 http://ftpmaster.internal/ubuntu questing/main armhf numactl armhf 2.0.19-1 [38.5 kB]
 57s Get:57 http://ftpmaster.internal/ubuntu questing/main armhf publicsuffix all 20250328.1952-0.1 [135 kB]
 57s Get:58 http://ftpmaster.internal/ubuntu questing/main armhf usb.ids all 2025.04.01-1 [223 kB]
 57s Get:59 http://ftpmaster.internal/ubuntu questing/main armhf usbutils armhf 1:018-2 [77.4 kB]
 57s Get:60 http://ftpmaster.internal/ubuntu questing/main armhf btrfs-progs armhf 6.14-1 [901 kB]
 57s Get:61 http://ftpmaster.internal/ubuntu questing/main armhf cloud-init-base all 25.2~1g7a0265d3-0ubuntu1 [619 kB]
 57s Get:62 http://ftpmaster.internal/ubuntu questing/main armhf dpkg-dev all 1.22.18ubuntu3 [1089 kB]
 57s Get:63 http://ftpmaster.internal/ubuntu questing/main armhf libdpkg-perl all 1.22.18ubuntu3 [281 kB]
 57s Get:64 http://ftpmaster.internal/ubuntu questing/main armhf patch armhf 2.8-1 [94.1 kB]
 57s Get:65 http://ftpmaster.internal/ubuntu questing/main armhf libjcat1 armhf 0.2.3-1 [30.9 kB]
 57s Get:66 http://ftpmaster.internal/ubuntu questing/main armhf fwupd armhf 2.0.8-3 [1414 kB]
 57s Get:67 http://ftpmaster.internal/ubuntu questing/main armhf libfwupd3 armhf 2.0.8-3 [126 kB]
 57s Get:68 http://ftpmaster.internal/ubuntu questing/main armhf libmbim-proxy armhf 1.32.0-1 [5888 B]
 57s Get:69 http://ftpmaster.internal/ubuntu questing/main armhf libmbim-glib4 armhf 1.32.0-1 [218 kB]
 57s Get:70 http://ftpmaster.internal/ubuntu questing/main armhf libmm-glib0 armhf 1.24.0-1 [223 kB]
 57s Get:71 http://ftpmaster.internal/ubuntu questing/main armhf libqmi-proxy armhf 1.36.0-1 [5882 B]
 57s Get:72 http://ftpmaster.internal/ubuntu questing/main armhf libqmi-glib5 armhf 1.36.0-1 [936 kB]
 57s Get:73 http://ftpmaster.internal/ubuntu questing/main armhf gnupg-l10n all 2.4.4-2ubuntu24 [66.8 kB]
 57s Get:74 http://ftpmaster.internal/ubuntu questing/main armhf htop armhf 3.4.1-4 [147 kB]
 57s Get:75 http://ftpmaster.internal/ubuntu questing/main armhf libftdi1-2 armhf 1.5-10 [27.8 kB]
 57s Get:76 http://ftpmaster.internal/ubuntu questing/main armhf libnvme1t64 armhf 1.13-2 [74.3 kB]
 57s Get:77 http://ftpmaster.internal/ubuntu questing/main armhf python3-attr all 25.3.0-1 [50.9 kB]
 57s Get:78 http://ftpmaster.internal/ubuntu questing/main armhf python3-wadllib all 2.0.0-3 [36.3 kB]
 57s Get:79 http://ftpmaster.internal/ubuntu questing/main armhf python3-lazr.restfulclient all 0.14.6-3 [51.0 kB]
 57s Get:80 http://ftpmaster.internal/ubuntu questing/main armhf python3-more-itertools all 10.7.0-1 [59.6 kB]
 57s Get:81 http://ftpmaster.internal/ubuntu questing/main armhf python3-packaging all 25.0-1 [52.8 kB]
 57s Get:82 http://ftpmaster.internal/ubuntu questing/main armhf python3-s3transfer all 0.11.4-1 [55.8 kB]
 57s Get:83 http://ftpmaster.internal/ubuntu questing/main armhf sos all 4.9.1-1 [367 kB]
 57s Get:84 http://ftpmaster.internal/ubuntu questing/main armhf cloud-init all 25.2~1g7a0265d3-0ubuntu1 [2106 B]
 58s Preconfiguring packages ...
 58s Fetched 25.2 MB in 2s (14.5 MB/s)
 58s (Reading database ... 
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(Reading database ... 63953 files and directories currently installed.)
 58s Preparing to unpack .../motd-news-config_13.7ubuntu1_all.deb ...
 58s Unpacking motd-news-config (13.7ubuntu1) over (13.6ubuntu2) ...
 58s Preparing to unpack .../base-files_13.7ubuntu1_armhf.deb ...
 58s Unpacking base-files (13.7ubuntu1) over (13.6ubuntu2) ...
 58s Setting up base-files (13.7ubuntu1) ...
 58s Installing new version of config file /etc/issue ...
 58s Installing new version of config file /etc/issue.net ...
 58s Installing new version of config file /etc/lsb-release ...
 59s motd-news.service is a disabled or a static unit not running, not starting it.
 59s (Reading database ... 
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 59s Preparing to unpack .../debianutils_5.22_armhf.deb ...
 59s Unpacking debianutils (5.22) over (5.21) ...
 59s Setting up debianutils (5.22) ...
 59s (Reading database ... 
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 59s Preparing to unpack .../diffutils_1%3a3.10-4_armhf.deb ...
 59s Unpacking diffutils (1:3.10-4) over (1:3.10-3) ...
 59s Setting up diffutils (1:3.10-4) ...
 60s (Reading database ... 
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(Reading database ... 63953 files and directories currently installed.)
 60s Preparing to unpack .../dpkg_1.22.18ubuntu3_armhf.deb ...
 60s Unpacking dpkg (1.22.18ubuntu3) over (1.22.18ubuntu2) ...
 60s Setting up dpkg (1.22.18ubuntu3) ...
 60s (Reading database ... 
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(Reading database ... 63953 files and directories currently installed.)
 60s Preparing to unpack .../libselinux1_3.8.1-1_armhf.deb ...
 60s Unpacking libselinux1:armhf (3.8.1-1) over (3.7-3ubuntu3) ...
 60s Setting up libselinux1:armhf (3.8.1-1) ...
 60s (Reading database ... 
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(Reading database ... 95%
(Reading database ... 100%
(Reading database ... 63953 files and directories currently installed.)
 60s Preparing to unpack .../base-passwd_3.6.7_armhf.deb ...
 60s Unpacking base-passwd (3.6.7) over (3.6.6) ...
 60s Setting up base-passwd (3.6.7) ...
 61s (Reading database ... 
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(Reading database ... 63953 files and directories currently installed.)
 61s Preparing to unpack .../gawk_1%3a5.3.2-1_armhf.deb ...
 61s Unpacking gawk (1:5.3.2-1) over (1:5.2.1-2build3) ...
 61s Preparing to unpack .../openssh-sftp-server_1%3a9.9p1-3ubuntu3.1_armhf.deb ...
 61s Unpacking openssh-sftp-server (1:9.9p1-3ubuntu3.1) over (1:9.9p1-3ubuntu3) ...
 61s Preparing to unpack .../openssh-server_1%3a9.9p1-3ubuntu3.1_armhf.deb ...
 61s Unpacking openssh-server (1:9.9p1-3ubuntu3.1) over (1:9.9p1-3ubuntu3) ...
 61s Preparing to unpack .../openssh-client_1%3a9.9p1-3ubuntu3.1_armhf.deb ...
 61s Unpacking openssh-client (1:9.9p1-3ubuntu3.1) over (1:9.9p1-3ubuntu3) ...
 61s Preparing to unpack .../libsepol2_3.8.1-1_armhf.deb ...
 61s Unpacking libsepol2:armhf (3.8.1-1) over (3.7-1) ...
 61s Setting up libsepol2:armhf (3.8.1-1) ...
 61s (Reading database ... 
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(Reading database ... 95%
(Reading database ... 100%
(Reading database ... 63955 files and directories currently installed.)
 61s Preparing to unpack .../libgpg-error-l10n_1.51-4_all.deb ...
 61s Unpacking libgpg-error-l10n (1.51-4) over (1.51-3) ...
 61s Preparing to unpack .../libgpg-error0_1.51-4_armhf.deb ...
 61s Unpacking libgpg-error0:armhf (1.51-4) over (1.51-3) ...
 61s Setting up libgpg-error0:armhf (1.51-4) ...
 61s (Reading database ... 
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(Reading database ... 95%
(Reading database ... 100%
(Reading database ... 63955 files and directories currently installed.)
 61s Preparing to unpack .../libnpth0t64_1.8-3_armhf.deb ...
 61s Unpacking libnpth0t64:armhf (1.8-3) over (1.8-2) ...
 61s Setting up libnpth0t64:armhf (1.8-3) ...
 61s (Reading database ... 
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 67s dpkg: warning: unable to delete old directory '/etc/grub.d': Directory not empty
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 67s Unpacking gnupg-l10n (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ...
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 69s Unpacking cloud-init (25.2~1g7a0265d3-0ubuntu1) over (25.1.1-0ubuntu2) ...
 69s Setting up motd-news-config (13.7ubuntu1) ...
 69s Setting up python3-more-itertools (10.7.0-1) ...
 69s Setting up python3-attr (25.3.0-1) ...
 69s Setting up liburcu8t64:armhf (0.15.2-2) ...
 69s Setting up gawk (1:5.3.2-1) ...
 69s Setting up distro-info-data (0.64) ...
 69s Setting up htop (3.4.1-4) ...
 69s Setting up openssh-client (1:9.9p1-3ubuntu3.1) ...
 69s Setting up btrfs-progs (6.14-1) ...
 69s Setting up python3-s3transfer (0.11.4-1) ...
 69s Setting up netcat-openbsd (1.229-1) ...
 69s Setting up libsensors-config (1:3.6.2-2) ...
 69s Installing new version of config file /etc/sensors3.conf ...
 69s Setting up libnghttp2-14:armhf (1.64.0-1.1) ...
 69s Setting up less (668-1) ...
 69s Setting up gettext-base (0.23.1-2) ...
 69s Setting up libnftnl11:armhf (1.2.9-1) ...
 69s Setting up libglib2.0-0t64:armhf (2.84.1-2) ...
 69s No schema files found: doing nothing.
 69s Setting up libglib2.0-data (2.84.1-2) ...
 69s Setting up python3-packaging (25.0-1) ...
 69s Setting up libnvme1t64 (1.13-2) ...
 69s Setting up libx11-data (2:1.8.12-1) ...
 69s Setting up gnupg-l10n (2.4.4-2ubuntu24) ...
 69s Setting up ed (1.21.1-1) ...
 69s Setting up python3-wadllib (2.0.0-3) ...
 70s Setting up libunistring5:armhf (1.3-2) ...
 70s Setting up patch (2.8-1) ...
 70s Setting up usb.ids (2025.04.01-1) ...
 70s Setting up dhcpcd-base (1:10.1.0-10) ...
 70s Installing new version of config file /etc/dhcpcd.conf ...
 70s Setting up gir1.2-glib-2.0:armhf (2.84.1-2) ...
 70s Setting up libsensors5:armhf (1:3.6.2-2) ...
 70s Setting up libdpkg-perl (1.22.18ubuntu3) ...
 70s Setting up nano (8.4-1) ...
 70s Installing new version of config file /etc/nanorc ...
 70s Setting up libnuma1:armhf (2.0.19-1) ...
 70s Setting up libmm-glib0:armhf (1.24.0-1) ...
 70s Setting up groff-base (1.23.0-8) ...
 70s Setting up gpgconf (2.4.4-2ubuntu24) ...
 70s Setting up libx11-6:armhf (2:1.8.12-1) ...
 70s Setting up netbase (6.5) ...
 70s Installing new version of config file /etc/ethertypes ...
 70s Installing new version of config file /etc/services ...
 70s Setting up libusb-1.0-0:armhf (2:1.0.28-1) ...
 70s Setting up python3-lazr.restfulclient (0.14.6-3) ...
 70s Setting up libgpg-error-l10n (1.51-4) ...
 70s Setting up libevdev2:armhf (1.13.4+dfsg-1) ...
 70s Setting up publicsuffix (20250328.1952-0.1) ...
 70s Setting up libxml2:armhf (2.12.7+dfsg+really2.9.14-0.4ubuntu0.1) ...
 70s Setting up ubuntu-pro-client (35.1ubuntu0) ...
 70s apparmor_parser: Unable to replace "ubuntu_pro_apt_news".  apparmor_parser: Access denied. You need policy admin privileges to manage profiles.
 70s 
 70s apparmor_parser: Unable to replace "apt_methods".  apparmor_parser: Access denied. You need policy admin privileges to manage profiles.
 70s 
 70s apparmor_parser: Unable to replace "ubuntu_pro_esm_cache".  apparmor_parser: Access denied. You need policy admin privileges to manage profiles.
 70s 
 72s Setting up iso-codes (4.18.0-1) ...
 72s Setting up gpg (2.4.4-2ubuntu24) ...
 72s Setting up libbpf1:armhf (1:1.5.0-3) ...
 72s Setting up libmbim-glib4:armhf (1.32.0-1) ...
 72s Setting up ethtool (1:6.14-2) ...
 72s Setting up gnupg-utils (2.4.4-2ubuntu24) ...
 72s Setting up ubuntu-pro-client-l10n (35.1ubuntu0) ...
 72s Setting up sos (4.9.1-1) ...
 73s Setting up openssh-sftp-server (1:9.9p1-3ubuntu3.1) ...
 73s Setting up gpg-agent (2.4.4-2ubuntu24) ...
 73s Setting up numactl (2.0.19-1) ...
 73s Setting up openssh-server (1:9.9p1-3ubuntu3.1) ...
 74s Setting up gpgsm (2.4.4-2ubuntu24) ...
 74s Setting up libmbim-proxy (1.32.0-1) ...
 74s Setting up man-db (2.13.1-1) ...
 75s Updating database of manual pages ...
 77s apparmor_parser: Unable to replace "/usr/bin/man".  apparmor_parser: Access denied. You need policy admin privileges to manage profiles.
 77s 
 77s man-db.service is a disabled or a static unit not running, not starting it.
 77s Setting up usbutils (1:018-2) ...
 77s Setting up cloud-init-base (25.2~1g7a0265d3-0ubuntu1) ...
 79s Setting up libjcat1:armhf (0.2.3-1) ...
 79s Setting up dpkg-dev (1.22.18ubuntu3) ...
 79s Setting up dirmngr (2.4.4-2ubuntu24) ...
 79s Setting up libftdi1-2:armhf (1.5-10) ...
 79s Setting up keyboxd (2.4.4-2ubuntu24) ...
 79s Setting up gnupg (2.4.4-2ubuntu24) ...
 79s Setting up cloud-init (25.2~1g7a0265d3-0ubuntu1) ...
 79s Setting up gpg-wks-client (2.4.4-2ubuntu24) ...
 79s Setting up libqmi-glib5:armhf (1.36.0-1) ...
 79s Setting up libfwupd3:armhf (2.0.8-3) ...
 79s Setting up libqmi-proxy (1.36.0-1) ...
 79s Setting up fwupd (2.0.8-3) ...
 80s fwupd-refresh.service is a disabled or a static unit not running, not starting it.
 80s fwupd.service is a disabled or a static unit not running, not starting it.
 80s Processing triggers for libc-bin (2.41-6ubuntu1) ...
 80s Processing triggers for rsyslog (8.2412.0-2ubuntu2) ...
 81s Processing triggers for ufw (0.36.2-9) ...
 81s Processing triggers for plymouth-theme-ubuntu-text (24.004.60-2ubuntu7) ...
 81s Processing triggers for dbus (1.16.2-2ubuntu1) ...
 81s Processing triggers for install-info (7.1.1-1) ...
 81s Processing triggers for initramfs-tools (0.147ubuntu1) ...
 83s Reading package lists...
 83s Building dependency tree...
 83s Reading state information...
 84s Starting pkgProblemResolver with broken count: 0
 84s Starting 2 pkgProblemResolver with broken count: 0
 84s Done
 85s Solving dependencies...
 85s The following packages will be REMOVED:
 85s   libsigsegv2*
 86s 0 upgraded, 0 newly installed, 1 to remove and 0 not upgraded.
 86s After this operation, 38.9 kB disk space will be freed.
 86s (Reading database ... 
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(Reading database ... 63966 files and directories currently installed.)
 86s Removing libsigsegv2:armhf (2.14-1ubuntu2) ...
 86s Processing triggers for libc-bin (2.41-6ubuntu1) ...
 88s autopkgtest [22:20:33]: rebooting testbed after setup commands that affected boot
129s autopkgtest [22:21:13]: testbed running kernel: Linux 6.8.0-58-generic #60~22.04.1-Ubuntu SMP PREEMPT_DYNAMIC Fri Mar 28 14:48:37 UTC 2
153s autopkgtest [22:21:38]: @@@@@@@@@@@@@@@@@@@@ apt-source yosys
176s Get:1 http://ftpmaster.internal/ubuntu questing/universe yosys 0.33-5build2 (dsc) [3069 B]
176s Get:2 http://ftpmaster.internal/ubuntu questing/universe yosys 0.33-5build2 (tar) [6161 kB]
176s Get:3 http://ftpmaster.internal/ubuntu questing/universe yosys 0.33-5build2 (tar) [2586 kB]
176s Get:4 http://ftpmaster.internal/ubuntu questing/universe yosys 0.33-5build2 (diff) [30.3 kB]
176s gpgv: Signature made Mon Apr  1 04:53:46 2024 UTC
176s gpgv:                using RSA key A089FB36AAFBDAD5ACC1325069F790171A210984
176s gpgv: Can't check signature: No public key
176s dpkg-source: warning: cannot verify inline signature for ./yosys_0.33-5build2.dsc: no acceptable signature found
177s autopkgtest [22:22:02]: testing package yosys version 0.33-5build2
179s autopkgtest [22:22:04]: build not needed
184s autopkgtest [22:22:09]: test yosys-testsuite: preparing testbed
186s Reading package lists...
186s Building dependency tree...
186s Reading state information...
187s Starting pkgProblemResolver with broken count: 0
187s Starting 2 pkgProblemResolver with broken count: 0
187s Done
188s The following NEW packages will be installed:
188s   cpp cpp-14 cpp-14-arm-linux-gnueabihf cpp-arm-linux-gnueabihf g++ g++-14
188s   g++-14-arm-linux-gnueabihf g++-arm-linux-gnueabihf gcc gcc-14
188s   gcc-14-arm-linux-gnueabihf gcc-arm-linux-gnueabihf iverilog libasan8
188s   libc-dev-bin libc6-dev libcc1-0 libcrypt-dev libffi-dev libgcc-14-dev
188s   libgomp1 libisl23 libmpc3 libncurses-dev libpkgconf3 libreadline-dev
188s   libstdc++-14-dev libtcl8.6 libubsan1 linux-libc-dev pkg-config pkgconf
188s   pkgconf-bin python3-click rpcsvc-proto tcl tcl-dev tcl8.6 tcl8.6-dev yosys
188s   yosys-abc yosys-dev zlib1g-dev
188s 0 upgraded, 43 newly installed, 0 to remove and 0 not upgraded.
188s Need to get 64.1 MB of archives.
188s After this operation, 184 MB of additional disk space will be used.
188s Get:1 http://ftpmaster.internal/ubuntu questing/main armhf libisl23 armhf 0.27-1 [546 kB]
188s Get:2 http://ftpmaster.internal/ubuntu questing/main armhf libmpc3 armhf 1.3.1-1build2 [47.1 kB]
188s Get:3 http://ftpmaster.internal/ubuntu questing/main armhf cpp-14-arm-linux-gnueabihf armhf 14.2.0-19ubuntu2 [9221 kB]
189s Get:4 http://ftpmaster.internal/ubuntu questing/main armhf cpp-14 armhf 14.2.0-19ubuntu2 [1032 B]
189s Get:5 http://ftpmaster.internal/ubuntu questing/main armhf cpp-arm-linux-gnueabihf armhf 4:14.2.0-1ubuntu1 [5578 B]
189s Get:6 http://ftpmaster.internal/ubuntu questing/main armhf cpp armhf 4:14.2.0-1ubuntu1 [22.4 kB]
189s Get:7 http://ftpmaster.internal/ubuntu questing/main armhf libcc1-0 armhf 15-20250404-0ubuntu1 [43.3 kB]
189s Get:8 http://ftpmaster.internal/ubuntu questing/main armhf libgomp1 armhf 15-20250404-0ubuntu1 [128 kB]
189s Get:9 http://ftpmaster.internal/ubuntu questing/main armhf libasan8 armhf 15-20250404-0ubuntu1 [2951 kB]
189s Get:10 http://ftpmaster.internal/ubuntu questing/main armhf libubsan1 armhf 15-20250404-0ubuntu1 [1188 kB]
189s Get:11 http://ftpmaster.internal/ubuntu questing/main armhf libgcc-14-dev armhf 14.2.0-19ubuntu2 [897 kB]
189s Get:12 http://ftpmaster.internal/ubuntu questing/main armhf gcc-14-arm-linux-gnueabihf armhf 14.2.0-19ubuntu2 [18.0 MB]
189s Get:13 http://ftpmaster.internal/ubuntu questing/main armhf gcc-14 armhf 14.2.0-19ubuntu2 [510 kB]
189s Get:14 http://ftpmaster.internal/ubuntu questing/main armhf gcc-arm-linux-gnueabihf armhf 4:14.2.0-1ubuntu1 [1218 B]
189s Get:15 http://ftpmaster.internal/ubuntu questing/main armhf gcc armhf 4:14.2.0-1ubuntu1 [5004 B]
189s Get:16 http://ftpmaster.internal/ubuntu questing/main armhf libc-dev-bin armhf 2.41-6ubuntu1 [21.7 kB]
189s Get:17 http://ftpmaster.internal/ubuntu questing/main armhf linux-libc-dev armhf 6.14.0-15.15 [1687 kB]
189s Get:18 http://ftpmaster.internal/ubuntu questing/main armhf libcrypt-dev armhf 1:4.4.38-1 [120 kB]
189s Get:19 http://ftpmaster.internal/ubuntu questing/main armhf rpcsvc-proto armhf 1.4.2-0ubuntu7 [62.2 kB]
189s Get:20 http://ftpmaster.internal/ubuntu questing/main armhf libc6-dev armhf 2.41-6ubuntu1 [1396 kB]
189s Get:21 http://ftpmaster.internal/ubuntu questing/main armhf libstdc++-14-dev armhf 14.2.0-19ubuntu2 [2576 kB]
190s Get:22 http://ftpmaster.internal/ubuntu questing/main armhf g++-14-arm-linux-gnueabihf armhf 14.2.0-19ubuntu2 [10.5 MB]
190s Get:23 http://ftpmaster.internal/ubuntu questing/main armhf g++-14 armhf 14.2.0-19ubuntu2 [23.0 kB]
190s Get:24 http://ftpmaster.internal/ubuntu questing/main armhf g++-arm-linux-gnueabihf armhf 4:14.2.0-1ubuntu1 [966 B]
190s Get:25 http://ftpmaster.internal/ubuntu questing/main armhf g++ armhf 4:14.2.0-1ubuntu1 [1084 B]
190s Get:26 http://ftpmaster.internal/ubuntu questing/universe armhf iverilog armhf 12.0-2build2 [2047 kB]
190s Get:27 http://ftpmaster.internal/ubuntu questing/main armhf libncurses-dev armhf 6.5+20250216-2 [345 kB]
190s Get:28 http://ftpmaster.internal/ubuntu questing/main armhf libpkgconf3 armhf 1.8.1-4 [26.6 kB]
190s Get:29 http://ftpmaster.internal/ubuntu questing/main armhf libreadline-dev armhf 8.2-6 [153 kB]
190s Get:30 http://ftpmaster.internal/ubuntu questing/main armhf libtcl8.6 armhf 8.6.16+dfsg-1 [909 kB]
190s Get:31 http://ftpmaster.internal/ubuntu questing/main armhf pkgconf-bin armhf 1.8.1-4 [21.2 kB]
190s Get:32 http://ftpmaster.internal/ubuntu questing/main armhf pkgconf armhf 1.8.1-4 [16.8 kB]
190s Get:33 http://ftpmaster.internal/ubuntu questing/main armhf pkg-config armhf 1.8.1-4 [7362 B]
190s Get:34 http://ftpmaster.internal/ubuntu questing/main armhf python3-click all 8.2.0+0.really.8.1.8-1 [80.0 kB]
190s Get:35 http://ftpmaster.internal/ubuntu questing/main armhf tcl8.6 armhf 8.6.16+dfsg-1 [14.6 kB]
190s Get:36 http://ftpmaster.internal/ubuntu questing/main armhf tcl armhf 8.6.16 [4088 B]
190s Get:37 http://ftpmaster.internal/ubuntu questing/main armhf zlib1g-dev armhf 1:1.3.dfsg+really1.3.1-1ubuntu1 [880 kB]
190s Get:38 http://ftpmaster.internal/ubuntu questing/main armhf tcl8.6-dev armhf 8.6.16+dfsg-1 [933 kB]
190s Get:39 http://ftpmaster.internal/ubuntu questing/main armhf tcl-dev armhf 8.6.16 [5760 B]
190s Get:40 http://ftpmaster.internal/ubuntu questing/universe armhf yosys-abc armhf 0.33-5build2 [5336 kB]
190s Get:41 http://ftpmaster.internal/ubuntu questing/universe armhf yosys armhf 0.33-5build2 [3225 kB]
190s Get:42 http://ftpmaster.internal/ubuntu questing/main armhf libffi-dev armhf 3.4.7-1 [57.2 kB]
190s Get:43 http://ftpmaster.internal/ubuntu questing/universe armhf yosys-dev armhf 0.33-5build2 [88.4 kB]
191s Fetched 64.1 MB in 2s (27.0 MB/s)
191s Selecting previously unselected package libisl23:armhf.
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191s Preparing to unpack .../00-libisl23_0.27-1_armhf.deb ...
191s Unpacking libisl23:armhf (0.27-1) ...
191s Selecting previously unselected package libmpc3:armhf.
191s Preparing to unpack .../01-libmpc3_1.3.1-1build2_armhf.deb ...
191s Unpacking libmpc3:armhf (1.3.1-1build2) ...
191s Selecting previously unselected package cpp-14-arm-linux-gnueabihf.
191s Preparing to unpack .../02-cpp-14-arm-linux-gnueabihf_14.2.0-19ubuntu2_armhf.deb ...
191s Unpacking cpp-14-arm-linux-gnueabihf (14.2.0-19ubuntu2) ...
191s Selecting previously unselected package cpp-14.
191s Preparing to unpack .../03-cpp-14_14.2.0-19ubuntu2_armhf.deb ...
191s Unpacking cpp-14 (14.2.0-19ubuntu2) ...
191s Selecting previously unselected package cpp-arm-linux-gnueabihf.
191s Preparing to unpack .../04-cpp-arm-linux-gnueabihf_4%3a14.2.0-1ubuntu1_armhf.deb ...
191s Unpacking cpp-arm-linux-gnueabihf (4:14.2.0-1ubuntu1) ...
191s Selecting previously unselected package cpp.
191s Preparing to unpack .../05-cpp_4%3a14.2.0-1ubuntu1_armhf.deb ...
191s Unpacking cpp (4:14.2.0-1ubuntu1) ...
191s Selecting previously unselected package libcc1-0:armhf.
191s Preparing to unpack .../06-libcc1-0_15-20250404-0ubuntu1_armhf.deb ...
191s Unpacking libcc1-0:armhf (15-20250404-0ubuntu1) ...
191s Selecting previously unselected package libgomp1:armhf.
191s Preparing to unpack .../07-libgomp1_15-20250404-0ubuntu1_armhf.deb ...
191s Unpacking libgomp1:armhf (15-20250404-0ubuntu1) ...
192s Selecting previously unselected package libasan8:armhf.
192s Preparing to unpack .../08-libasan8_15-20250404-0ubuntu1_armhf.deb ...
192s Unpacking libasan8:armhf (15-20250404-0ubuntu1) ...
192s Selecting previously unselected package libubsan1:armhf.
192s Preparing to unpack .../09-libubsan1_15-20250404-0ubuntu1_armhf.deb ...
192s Unpacking libubsan1:armhf (15-20250404-0ubuntu1) ...
192s Selecting previously unselected package libgcc-14-dev:armhf.
192s Preparing to unpack .../10-libgcc-14-dev_14.2.0-19ubuntu2_armhf.deb ...
192s Unpacking libgcc-14-dev:armhf (14.2.0-19ubuntu2) ...
192s Selecting previously unselected package gcc-14-arm-linux-gnueabihf.
192s Preparing to unpack .../11-gcc-14-arm-linux-gnueabihf_14.2.0-19ubuntu2_armhf.deb ...
192s Unpacking gcc-14-arm-linux-gnueabihf (14.2.0-19ubuntu2) ...
192s Selecting previously unselected package gcc-14.
192s Preparing to unpack .../12-gcc-14_14.2.0-19ubuntu2_armhf.deb ...
192s Unpacking gcc-14 (14.2.0-19ubuntu2) ...
192s Selecting previously unselected package gcc-arm-linux-gnueabihf.
192s Preparing to unpack .../13-gcc-arm-linux-gnueabihf_4%3a14.2.0-1ubuntu1_armhf.deb ...
192s Unpacking gcc-arm-linux-gnueabihf (4:14.2.0-1ubuntu1) ...
192s Selecting previously unselected package gcc.
192s Preparing to unpack .../14-gcc_4%3a14.2.0-1ubuntu1_armhf.deb ...
192s Unpacking gcc (4:14.2.0-1ubuntu1) ...
192s Selecting previously unselected package libc-dev-bin.
192s Preparing to unpack .../15-libc-dev-bin_2.41-6ubuntu1_armhf.deb ...
192s Unpacking libc-dev-bin (2.41-6ubuntu1) ...
192s Selecting previously unselected package linux-libc-dev:armhf.
192s Preparing to unpack .../16-linux-libc-dev_6.14.0-15.15_armhf.deb ...
192s Unpacking linux-libc-dev:armhf (6.14.0-15.15) ...
193s Selecting previously unselected package libcrypt-dev:armhf.
193s Preparing to unpack .../17-libcrypt-dev_1%3a4.4.38-1_armhf.deb ...
193s Unpacking libcrypt-dev:armhf (1:4.4.38-1) ...
193s Selecting previously unselected package rpcsvc-proto.
193s Preparing to unpack .../18-rpcsvc-proto_1.4.2-0ubuntu7_armhf.deb ...
193s Unpacking rpcsvc-proto (1.4.2-0ubuntu7) ...
193s Selecting previously unselected package libc6-dev:armhf.
193s Preparing to unpack .../19-libc6-dev_2.41-6ubuntu1_armhf.deb ...
193s Unpacking libc6-dev:armhf (2.41-6ubuntu1) ...
193s Selecting previously unselected package libstdc++-14-dev:armhf.
193s Preparing to unpack .../20-libstdc++-14-dev_14.2.0-19ubuntu2_armhf.deb ...
193s Unpacking libstdc++-14-dev:armhf (14.2.0-19ubuntu2) ...
193s Selecting previously unselected package g++-14-arm-linux-gnueabihf.
193s Preparing to unpack .../21-g++-14-arm-linux-gnueabihf_14.2.0-19ubuntu2_armhf.deb ...
193s Unpacking g++-14-arm-linux-gnueabihf (14.2.0-19ubuntu2) ...
193s Selecting previously unselected package g++-14.
193s Preparing to unpack .../22-g++-14_14.2.0-19ubuntu2_armhf.deb ...
193s Unpacking g++-14 (14.2.0-19ubuntu2) ...
193s Selecting previously unselected package g++-arm-linux-gnueabihf.
194s Preparing to unpack .../23-g++-arm-linux-gnueabihf_4%3a14.2.0-1ubuntu1_armhf.deb ...
194s Unpacking g++-arm-linux-gnueabihf (4:14.2.0-1ubuntu1) ...
194s Selecting previously unselected package g++.
194s Preparing to unpack .../24-g++_4%3a14.2.0-1ubuntu1_armhf.deb ...
194s Unpacking g++ (4:14.2.0-1ubuntu1) ...
194s Selecting previously unselected package iverilog.
194s Preparing to unpack .../25-iverilog_12.0-2build2_armhf.deb ...
194s Unpacking iverilog (12.0-2build2) ...
194s Selecting previously unselected package libncurses-dev:armhf.
194s Preparing to unpack .../26-libncurses-dev_6.5+20250216-2_armhf.deb ...
194s Unpacking libncurses-dev:armhf (6.5+20250216-2) ...
194s Selecting previously unselected package libpkgconf3:armhf.
194s Preparing to unpack .../27-libpkgconf3_1.8.1-4_armhf.deb ...
194s Unpacking libpkgconf3:armhf (1.8.1-4) ...
194s Selecting previously unselected package libreadline-dev:armhf.
194s Preparing to unpack .../28-libreadline-dev_8.2-6_armhf.deb ...
194s Unpacking libreadline-dev:armhf (8.2-6) ...
194s Selecting previously unselected package libtcl8.6:armhf.
194s Preparing to unpack .../29-libtcl8.6_8.6.16+dfsg-1_armhf.deb ...
194s Unpacking libtcl8.6:armhf (8.6.16+dfsg-1) ...
194s Selecting previously unselected package pkgconf-bin.
194s Preparing to unpack .../30-pkgconf-bin_1.8.1-4_armhf.deb ...
194s Unpacking pkgconf-bin (1.8.1-4) ...
194s Selecting previously unselected package pkgconf:armhf.
194s Preparing to unpack .../31-pkgconf_1.8.1-4_armhf.deb ...
194s Unpacking pkgconf:armhf (1.8.1-4) ...
194s Selecting previously unselected package pkg-config:armhf.
194s Preparing to unpack .../32-pkg-config_1.8.1-4_armhf.deb ...
194s Unpacking pkg-config:armhf (1.8.1-4) ...
194s Selecting previously unselected package python3-click.
194s Preparing to unpack .../33-python3-click_8.2.0+0.really.8.1.8-1_all.deb ...
194s Unpacking python3-click (8.2.0+0.really.8.1.8-1) ...
194s Selecting previously unselected package tcl8.6.
194s Preparing to unpack .../34-tcl8.6_8.6.16+dfsg-1_armhf.deb ...
194s Unpacking tcl8.6 (8.6.16+dfsg-1) ...
194s Selecting previously unselected package tcl.
194s Preparing to unpack .../35-tcl_8.6.16_armhf.deb ...
194s Unpacking tcl (8.6.16) ...
194s Selecting previously unselected package zlib1g-dev:armhf.
194s Preparing to unpack .../36-zlib1g-dev_1%3a1.3.dfsg+really1.3.1-1ubuntu1_armhf.deb ...
194s Unpacking zlib1g-dev:armhf (1:1.3.dfsg+really1.3.1-1ubuntu1) ...
194s Selecting previously unselected package tcl8.6-dev:armhf.
194s Preparing to unpack .../37-tcl8.6-dev_8.6.16+dfsg-1_armhf.deb ...
194s Unpacking tcl8.6-dev:armhf (8.6.16+dfsg-1) ...
194s Selecting previously unselected package tcl-dev:armhf.
194s Preparing to unpack .../38-tcl-dev_8.6.16_armhf.deb ...
194s Unpacking tcl-dev:armhf (8.6.16) ...
194s Selecting previously unselected package yosys-abc.
194s Preparing to unpack .../39-yosys-abc_0.33-5build2_armhf.deb ...
194s Unpacking yosys-abc (0.33-5build2) ...
195s Selecting previously unselected package yosys.
195s Preparing to unpack .../40-yosys_0.33-5build2_armhf.deb ...
195s Unpacking yosys (0.33-5build2) ...
195s Selecting previously unselected package libffi-dev:armhf.
195s Preparing to unpack .../41-libffi-dev_3.4.7-1_armhf.deb ...
195s Unpacking libffi-dev:armhf (3.4.7-1) ...
195s Selecting previously unselected package yosys-dev.
195s Preparing to unpack .../42-yosys-dev_0.33-5build2_armhf.deb ...
195s Unpacking yosys-dev (0.33-5build2) ...
195s Setting up linux-libc-dev:armhf (6.14.0-15.15) ...
195s Setting up yosys-abc (0.33-5build2) ...
195s Setting up libgomp1:armhf (15-20250404-0ubuntu1) ...
195s Setting up python3-click (8.2.0+0.really.8.1.8-1) ...
195s Setting up libffi-dev:armhf (3.4.7-1) ...
195s Setting up iverilog (12.0-2build2) ...
195s Setting up libpkgconf3:armhf (1.8.1-4) ...
195s Setting up rpcsvc-proto (1.4.2-0ubuntu7) ...
195s Setting up libmpc3:armhf (1.3.1-1build2) ...
195s Setting up libtcl8.6:armhf (8.6.16+dfsg-1) ...
195s Setting up pkgconf-bin (1.8.1-4) ...
195s Setting up libubsan1:armhf (15-20250404-0ubuntu1) ...
195s Setting up libcrypt-dev:armhf (1:4.4.38-1) ...
195s Setting up libasan8:armhf (15-20250404-0ubuntu1) ...
195s Setting up libgcc-14-dev:armhf (14.2.0-19ubuntu2) ...
195s Setting up libisl23:armhf (0.27-1) ...
195s Setting up libc-dev-bin (2.41-6ubuntu1) ...
195s Setting up libcc1-0:armhf (15-20250404-0ubuntu1) ...
195s Setting up cpp-14-arm-linux-gnueabihf (14.2.0-19ubuntu2) ...
195s Setting up tcl8.6 (8.6.16+dfsg-1) ...
195s Setting up yosys (0.33-5build2) ...
195s Setting up gcc-14-arm-linux-gnueabihf (14.2.0-19ubuntu2) ...
195s Setting up pkgconf:armhf (1.8.1-4) ...
195s Setting up pkg-config:armhf (1.8.1-4) ...
195s Setting up cpp-14 (14.2.0-19ubuntu2) ...
195s Setting up tcl (8.6.16) ...
195s Setting up libc6-dev:armhf (2.41-6ubuntu1) ...
195s Setting up libstdc++-14-dev:armhf (14.2.0-19ubuntu2) ...
195s Setting up cpp-arm-linux-gnueabihf (4:14.2.0-1ubuntu1) ...
195s Setting up gcc-arm-linux-gnueabihf (4:14.2.0-1ubuntu1) ...
195s Setting up g++-14-arm-linux-gnueabihf (14.2.0-19ubuntu2) ...
195s Setting up libncurses-dev:armhf (6.5+20250216-2) ...
195s Setting up libreadline-dev:armhf (8.2-6) ...
195s Setting up gcc-14 (14.2.0-19ubuntu2) ...
195s Setting up zlib1g-dev:armhf (1:1.3.dfsg+really1.3.1-1ubuntu1) ...
195s Setting up cpp (4:14.2.0-1ubuntu1) ...
195s Setting up g++-14 (14.2.0-19ubuntu2) ...
195s Setting up g++-arm-linux-gnueabihf (4:14.2.0-1ubuntu1) ...
195s Setting up tcl8.6-dev:armhf (8.6.16+dfsg-1) ...
195s Setting up gcc (4:14.2.0-1ubuntu1) ...
195s Setting up tcl-dev:armhf (8.6.16) ...
195s Setting up g++ (4:14.2.0-1ubuntu1) ...
195s update-alternatives: using /usr/bin/g++ to provide /usr/bin/c++ (c++) in auto mode
195s Setting up yosys-dev (0.33-5build2) ...
195s Processing triggers for man-db (2.13.1-1) ...
196s Processing triggers for install-info (7.1.1-1) ...
196s Processing triggers for libc-bin (2.41-6ubuntu1) ...
207s autopkgtest [22:22:32]: test yosys-testsuite: [-----------------------
209s + [ 1 -ge 1 ]
209s + testdir=.
209s + shift
209s + mkdir -p .
209s + cd .
209s + ln -sf /usr/bin/yosys .
209s + ln -sf /usr/bin/yosys-abc .
209s + ln -sf /usr/bin/yosys-config .
209s + sed -i s/^test:.*/test: $(EXTRA_TARGETS)/ Makefile
209s + make test CONFIG=gcc ABCPULL=0
210s mkdir -p share/include/kernel/
210s cp "./"/kernel/yosys.h share/include/kernel/yosys.h
210s mkdir -p share/include/kernel/
210s cp "./"/kernel/hashlib.h share/include/kernel/hashlib.h
210s mkdir -p share/include/kernel/
210s cp "./"/kernel/log.h share/include/kernel/log.h
210s mkdir -p share/include/kernel/
210s cp "./"/kernel/rtlil.h share/include/kernel/rtlil.h
210s mkdir -p share/include/kernel/
210s cp "./"/kernel/binding.h share/include/kernel/binding.h
210s mkdir -p share/include/kernel/
210s cp "./"/kernel/register.h share/include/kernel/register.h
210s mkdir -p share/include/kernel/
210s cp "./"/kernel/cellaigs.h share/include/kernel/cellaigs.h
210s mkdir -p share/include/kernel/
210s cp "./"/kernel/celltypes.h share/include/kernel/celltypes.h
210s mkdir -p share/include/kernel/
210s cp "./"/kernel/celledges.h share/include/kernel/celledges.h
210s mkdir -p share/include/kernel/
210s cp "./"/kernel/consteval.h share/include/kernel/consteval.h
210s mkdir -p share/include/kernel/
210s cp "./"/kernel/constids.inc share/include/kernel/constids.inc
210s mkdir -p share/include/kernel/
210s cp "./"/kernel/sigtools.h share/include/kernel/sigtools.h
210s mkdir -p share/include/kernel/
210s cp "./"/kernel/modtools.h share/include/kernel/modtools.h
210s mkdir -p share/include/kernel/
210s cp "./"/kernel/macc.h share/include/kernel/macc.h
210s mkdir -p share/include/kernel/
210s cp "./"/kernel/utils.h share/include/kernel/utils.h
210s mkdir -p share/include/kernel/
210s cp "./"/kernel/satgen.h share/include/kernel/satgen.h
210s mkdir -p share/include/kernel/
210s cp "./"/kernel/qcsat.h share/include/kernel/qcsat.h
210s mkdir -p share/include/kernel/
210s cp "./"/kernel/ff.h share/include/kernel/ff.h
210s mkdir -p share/include/kernel/
210s cp "./"/kernel/ffinit.h share/include/kernel/ffinit.h
210s mkdir -p share/include/kernel/
210s cp "./"/kernel/fstdata.h share/include/kernel/fstdata.h
210s mkdir -p share/include/kernel/
210s cp "./"/kernel/mem.h share/include/kernel/mem.h
210s mkdir -p share/include/kernel/
210s cp "./"/kernel/yw.h share/include/kernel/yw.h
210s mkdir -p share/include/kernel/
210s cp "./"/kernel/json.h share/include/kernel/json.h
210s mkdir -p share/include/libs/ezsat/
210s cp "./"/libs/ezsat/ezsat.h share/include/libs/ezsat/ezsat.h
210s mkdir -p share/include/libs/ezsat/
210s cp "./"/libs/ezsat/ezminisat.h share/include/libs/ezsat/ezminisat.h
210s mkdir -p share/include/libs/fst/
210s cp "./"/libs/fst/fstapi.h share/include/libs/fst/fstapi.h
210s mkdir -p share/include/libs/sha1/
210s cp "./"/libs/sha1/sha1.h share/include/libs/sha1/sha1.h
210s mkdir -p share/include/libs/json11/
210s cp "./"/libs/json11/json11.hpp share/include/libs/json11/json11.hpp
210s mkdir -p share/include/passes/fsm/
210s cp "./"/passes/fsm/fsmdata.h share/include/passes/fsm/fsmdata.h
210s mkdir -p share/include/frontends/ast/
210s cp "./"/frontends/ast/ast.h share/include/frontends/ast/ast.h
210s mkdir -p share/include/frontends/ast/
210s cp "./"/frontends/ast/ast_binding.h share/include/frontends/ast/ast_binding.h
210s mkdir -p share/include/frontends/blif/
210s cp "./"/frontends/blif/blifparse.h share/include/frontends/blif/blifparse.h
210s mkdir -p share/include/backends/rtlil/
210s cp "./"/backends/rtlil/rtlil_backend.h share/include/backends/rtlil/rtlil_backend.h
210s mkdir -p share/include/backends/cxxrtl/
210s cp "./"/backends/cxxrtl/cxxrtl.h share/include/backends/cxxrtl/cxxrtl.h
210s mkdir -p share/include/backends/cxxrtl/
210s cp "./"/backends/cxxrtl/cxxrtl_vcd.h share/include/backends/cxxrtl/cxxrtl_vcd.h
210s mkdir -p share/include/backends/cxxrtl/
210s cp "./"/backends/cxxrtl/cxxrtl_capi.cc share/include/backends/cxxrtl/cxxrtl_capi.cc
210s mkdir -p share/include/backends/cxxrtl/
210s cp "./"/backends/cxxrtl/cxxrtl_capi.h share/include/backends/cxxrtl/cxxrtl_capi.h
210s mkdir -p share/include/backends/cxxrtl/
210s cp "./"/backends/cxxrtl/cxxrtl_vcd_capi.cc share/include/backends/cxxrtl/cxxrtl_vcd_capi.cc
210s mkdir -p share/include/backends/cxxrtl/
210s cp "./"/backends/cxxrtl/cxxrtl_vcd_capi.h share/include/backends/cxxrtl/cxxrtl_vcd_capi.h
210s mkdir -p share/python3
210s cp "./"/backends/smt2/smtio.py share/python3/smtio.py
210s mkdir -p share/python3
210s cp "./"/backends/smt2/ywio.py share/python3/ywio.py
210s mkdir -p share/achronix/speedster22i/
210s cp "./"/techlibs/achronix/speedster22i/cells_sim.v share/achronix/speedster22i/cells_sim.v
210s mkdir -p share/achronix/speedster22i/
210s cp "./"/techlibs/achronix/speedster22i/cells_map.v share/achronix/speedster22i/cells_map.v
210s mkdir -p share/anlogic
210s cp "./"/techlibs/anlogic/cells_map.v share/anlogic/cells_map.v
210s mkdir -p share/anlogic
210s cp "./"/techlibs/anlogic/arith_map.v share/anlogic/arith_map.v
210s mkdir -p share/anlogic
210s cp "./"/techlibs/anlogic/cells_sim.v share/anlogic/cells_sim.v
210s mkdir -p share/anlogic
210s cp "./"/techlibs/anlogic/eagle_bb.v share/anlogic/eagle_bb.v
210s mkdir -p share/anlogic
210s cp "./"/techlibs/anlogic/lutrams.txt share/anlogic/lutrams.txt
210s mkdir -p share/anlogic
210s cp "./"/techlibs/anlogic/lutrams_map.v share/anlogic/lutrams_map.v
210s mkdir -p share/anlogic
210s cp "./"/techlibs/anlogic/brams.txt share/anlogic/brams.txt
210s mkdir -p share/anlogic
210s cp "./"/techlibs/anlogic/brams_map.v share/anlogic/brams_map.v
210s mkdir -p share
210s cp "./"/techlibs/common/simlib.v share/simlib.v
210s mkdir -p share
210s cp "./"/techlibs/common/simcells.v share/simcells.v
210s mkdir -p share
210s cp "./"/techlibs/common/techmap.v share/techmap.v
210s mkdir -p share
210s cp "./"/techlibs/common/smtmap.v share/smtmap.v
210s mkdir -p share
210s cp "./"/techlibs/common/pmux2mux.v share/pmux2mux.v
210s mkdir -p share
210s cp "./"/techlibs/common/adff2dff.v share/adff2dff.v
210s mkdir -p share
210s cp "./"/techlibs/common/dff2ff.v share/dff2ff.v
210s mkdir -p share
210s cp "./"/techlibs/common/gate2lut.v share/gate2lut.v
210s mkdir -p share
210s cp "./"/techlibs/common/cmp2lut.v share/cmp2lut.v
210s mkdir -p share
210s cp "./"/techlibs/common/cells.lib share/cells.lib
210s mkdir -p share
210s cp "./"/techlibs/common/mul2dsp.v share/mul2dsp.v
210s mkdir -p share
210s cp "./"/techlibs/common/abc9_model.v share/abc9_model.v
210s mkdir -p share
210s cp "./"/techlibs/common/abc9_map.v share/abc9_map.v
210s mkdir -p share
210s cp "./"/techlibs/common/abc9_unmap.v share/abc9_unmap.v
210s mkdir -p share
210s cp "./"/techlibs/common/cmp2lcu.v share/cmp2lcu.v
210s mkdir -p share/coolrunner2
210s cp "./"/techlibs/coolrunner2/cells_latch.v share/coolrunner2/cells_latch.v
210s mkdir -p share/coolrunner2
210s cp "./"/techlibs/coolrunner2/cells_sim.v share/coolrunner2/cells_sim.v
210s mkdir -p share/coolrunner2
210s cp "./"/techlibs/coolrunner2/cells_counter_map.v share/coolrunner2/cells_counter_map.v
210s mkdir -p share/coolrunner2
210s cp "./"/techlibs/coolrunner2/tff_extract.v share/coolrunner2/tff_extract.v
210s mkdir -p share/coolrunner2
210s cp "./"/techlibs/coolrunner2/xc2_dff.lib share/coolrunner2/xc2_dff.lib
210s mkdir -p share/ecp5
210s cp "./"/techlibs/ecp5/cells_ff.vh share/ecp5/cells_ff.vh
210s mkdir -p share/ecp5
210s cp "./"/techlibs/ecp5/cells_io.vh share/ecp5/cells_io.vh
210s mkdir -p share/ecp5
210s cp "./"/techlibs/ecp5/cells_map.v share/ecp5/cells_map.v
210s mkdir -p share/ecp5
210s cp "./"/techlibs/ecp5/cells_sim.v share/ecp5/cells_sim.v
210s mkdir -p share/ecp5
210s cp "./"/techlibs/ecp5/cells_bb.v share/ecp5/cells_bb.v
210s mkdir -p share/ecp5
210s cp "./"/techlibs/ecp5/lutrams_map.v share/ecp5/lutrams_map.v
210s mkdir -p share/ecp5
210s cp "./"/techlibs/ecp5/lutrams.txt share/ecp5/lutrams.txt
210s mkdir -p share/ecp5
210s cp "./"/techlibs/ecp5/brams_map.v share/ecp5/brams_map.v
210s mkdir -p share/ecp5
210s cp "./"/techlibs/ecp5/brams.txt share/ecp5/brams.txt
210s mkdir -p share/ecp5
210s cp "./"/techlibs/ecp5/arith_map.v share/ecp5/arith_map.v
210s mkdir -p share/ecp5
210s cp "./"/techlibs/ecp5/latches_map.v share/ecp5/latches_map.v
210s mkdir -p share/ecp5
210s cp "./"/techlibs/ecp5/dsp_map.v share/ecp5/dsp_map.v
210s mkdir -p share/efinix
210s cp "./"/techlibs/efinix/cells_map.v share/efinix/cells_map.v
210s mkdir -p share/efinix
210s cp "./"/techlibs/efinix/arith_map.v share/efinix/arith_map.v
210s mkdir -p share/efinix
210s cp "./"/techlibs/efinix/cells_sim.v share/efinix/cells_sim.v
210s mkdir -p share/efinix
210s cp "./"/techlibs/efinix/brams_map.v share/efinix/brams_map.v
210s mkdir -p share/efinix
210s cp "./"/techlibs/efinix/gbuf_map.v share/efinix/gbuf_map.v
210s mkdir -p share/efinix
210s cp "./"/techlibs/efinix/brams.txt share/efinix/brams.txt
210s mkdir -p share/fabulous
210s cp "./"/techlibs/fabulous/cells_map.v share/fabulous/cells_map.v
210s mkdir -p share/fabulous
210s cp "./"/techlibs/fabulous/prims.v share/fabulous/prims.v
210s mkdir -p share/fabulous
210s cp "./"/techlibs/fabulous/latches_map.v share/fabulous/latches_map.v
210s mkdir -p share/fabulous
210s cp "./"/techlibs/fabulous/ff_map.v share/fabulous/ff_map.v
210s mkdir -p share/fabulous
210s cp "./"/techlibs/fabulous/ram_regfile.txt share/fabulous/ram_regfile.txt
210s mkdir -p share/fabulous
210s cp "./"/techlibs/fabulous/regfile_map.v share/fabulous/regfile_map.v
210s mkdir -p share/fabulous
210s cp "./"/techlibs/fabulous/io_map.v share/fabulous/io_map.v
210s mkdir -p share/fabulous
210s cp "./"/techlibs/fabulous/arith_map.v share/fabulous/arith_map.v
210s mkdir -p share/gatemate
210s cp "./"/techlibs/gatemate/reg_map.v share/gatemate/reg_map.v
210s mkdir -p share/gatemate
210s cp "./"/techlibs/gatemate/mux_map.v share/gatemate/mux_map.v
210s mkdir -p share/gatemate
210s cp "./"/techlibs/gatemate/lut_map.v share/gatemate/lut_map.v
210s mkdir -p share/gatemate
210s cp "./"/techlibs/gatemate/mul_map.v share/gatemate/mul_map.v
210s mkdir -p share/gatemate
210s cp "./"/techlibs/gatemate/arith_map.v share/gatemate/arith_map.v
210s mkdir -p share/gatemate
210s cp "./"/techlibs/gatemate/cells_sim.v share/gatemate/cells_sim.v
210s mkdir -p share/gatemate
210s cp "./"/techlibs/gatemate/cells_bb.v share/gatemate/cells_bb.v
210s mkdir -p share/gatemate
210s cp "./"/techlibs/gatemate/brams_map.v share/gatemate/brams_map.v
210s mkdir -p share/gatemate
210s cp "./"/techlibs/gatemate/brams.txt share/gatemate/brams.txt
210s mkdir -p share/gatemate
210s cp "./"/techlibs/gatemate/brams_init_20.vh share/gatemate/brams_init_20.vh
210s mkdir -p share/gatemate
210s cp "./"/techlibs/gatemate/brams_init_40.vh share/gatemate/brams_init_40.vh
210s mkdir -p share/gatemate
210s cp "./"/techlibs/gatemate/inv_map.v share/gatemate/inv_map.v
210s mkdir -p techlibs/gatemate
210s python3 techlibs/gatemate/make_lut_tree_lib.py
210s touch techlibs/gatemate/lut_tree_lib.mk
210s mkdir -p share/gatemate
210s cp techlibs/gatemate/lut_tree_cells.genlib share/gatemate/lut_tree_cells.genlib
210s mkdir -p share/gatemate
210s cp techlibs/gatemate/lut_tree_map.v share/gatemate/lut_tree_map.v
210s mkdir -p share/gowin
210s cp "./"/techlibs/gowin/cells_map.v share/gowin/cells_map.v
210s mkdir -p share/gowin
210s cp "./"/techlibs/gowin/cells_sim.v share/gowin/cells_sim.v
210s mkdir -p share/gowin
210s cp "./"/techlibs/gowin/cells_xtra.v share/gowin/cells_xtra.v
210s mkdir -p share/gowin
210s cp "./"/techlibs/gowin/arith_map.v share/gowin/arith_map.v
210s mkdir -p share/gowin
210s cp "./"/techlibs/gowin/brams_map.v share/gowin/brams_map.v
210s mkdir -p share/gowin
210s cp "./"/techlibs/gowin/brams.txt share/gowin/brams.txt
210s mkdir -p share/gowin
210s cp "./"/techlibs/gowin/lutrams_map.v share/gowin/lutrams_map.v
210s mkdir -p share/gowin
210s cp "./"/techlibs/gowin/lutrams.txt share/gowin/lutrams.txt
210s mkdir -p share/greenpak4
210s cp "./"/techlibs/greenpak4/cells_blackbox.v share/greenpak4/cells_blackbox.v
210s mkdir -p share/greenpak4
210s cp "./"/techlibs/greenpak4/cells_latch.v share/greenpak4/cells_latch.v
210s mkdir -p share/greenpak4
210s cp "./"/techlibs/greenpak4/cells_map.v share/greenpak4/cells_map.v
210s mkdir -p share/greenpak4
210s cp "./"/techlibs/greenpak4/cells_sim.v share/greenpak4/cells_sim.v
210s mkdir -p share/greenpak4
210s cp "./"/techlibs/greenpak4/cells_sim_ams.v share/greenpak4/cells_sim_ams.v
210s mkdir -p share/greenpak4
210s cp "./"/techlibs/greenpak4/cells_sim_digital.v share/greenpak4/cells_sim_digital.v
210s mkdir -p share/greenpak4
210s cp "./"/techlibs/greenpak4/cells_sim_wip.v share/greenpak4/cells_sim_wip.v
210s mkdir -p share/greenpak4
210s cp "./"/techlibs/greenpak4/gp_dff.lib share/greenpak4/gp_dff.lib
210s mkdir -p share/ice40
210s cp "./"/techlibs/ice40/arith_map.v share/ice40/arith_map.v
210s mkdir -p share/ice40
210s cp "./"/techlibs/ice40/cells_map.v share/ice40/cells_map.v
210s mkdir -p share/ice40
210s cp "./"/techlibs/ice40/ff_map.v share/ice40/ff_map.v
210s mkdir -p share/ice40
210s cp "./"/techlibs/ice40/cells_sim.v share/ice40/cells_sim.v
210s mkdir -p share/ice40
210s cp "./"/techlibs/ice40/latches_map.v share/ice40/latches_map.v
210s mkdir -p share/ice40
210s cp "./"/techlibs/ice40/brams.txt share/ice40/brams.txt
211s mkdir -p share/ice40
211s cp "./"/techlibs/ice40/brams_map.v share/ice40/brams_map.v
211s mkdir -p share/ice40
211s cp "./"/techlibs/ice40/spram.txt share/ice40/spram.txt
211s mkdir -p share/ice40
211s cp "./"/techlibs/ice40/spram_map.v share/ice40/spram_map.v
211s mkdir -p share/ice40
211s cp "./"/techlibs/ice40/dsp_map.v share/ice40/dsp_map.v
211s mkdir -p share/ice40
211s cp "./"/techlibs/ice40/abc9_model.v share/ice40/abc9_model.v
211s mkdir -p share/intel/common
211s cp "./"/techlibs/intel/common/m9k_bb.v share/intel/common/m9k_bb.v
211s mkdir -p share/intel/common
211s cp "./"/techlibs/intel/common/altpll_bb.v share/intel/common/altpll_bb.v
211s mkdir -p share/intel/common
211s cp "./"/techlibs/intel/common/brams_m9k.txt share/intel/common/brams_m9k.txt
211s mkdir -p share/intel/common
211s cp "./"/techlibs/intel/common/brams_map_m9k.v share/intel/common/brams_map_m9k.v
211s mkdir -p share/intel/common
211s cp "./"/techlibs/intel/common/ff_map.v share/intel/common/ff_map.v
211s mkdir -p share/intel/max10
211s cp "./"/techlibs/intel/max10/cells_sim.v share/intel/max10/cells_sim.v
211s mkdir -p share/intel/cyclone10lp
211s cp "./"/techlibs/intel/cyclone10lp/cells_sim.v share/intel/cyclone10lp/cells_sim.v
211s mkdir -p share/intel/cycloneiv
211s cp "./"/techlibs/intel/cycloneiv/cells_sim.v share/intel/cycloneiv/cells_sim.v
211s mkdir -p share/intel/cycloneive
211s cp "./"/techlibs/intel/cycloneive/cells_sim.v share/intel/cycloneive/cells_sim.v
211s mkdir -p share/intel/max10
211s cp "./"/techlibs/intel/max10/cells_map.v share/intel/max10/cells_map.v
211s mkdir -p share/intel/cyclone10lp
211s cp "./"/techlibs/intel/cyclone10lp/cells_map.v share/intel/cyclone10lp/cells_map.v
211s mkdir -p share/intel/cycloneiv
211s cp "./"/techlibs/intel/cycloneiv/cells_map.v share/intel/cycloneiv/cells_map.v
211s mkdir -p share/intel/cycloneive
211s cp "./"/techlibs/intel/cycloneive/cells_map.v share/intel/cycloneive/cells_map.v
211s mkdir -p share/intel_alm/common
211s cp "./"/techlibs/intel_alm/common/abc9_map.v share/intel_alm/common/abc9_map.v
211s mkdir -p share/intel_alm/common
211s cp "./"/techlibs/intel_alm/common/abc9_unmap.v share/intel_alm/common/abc9_unmap.v
211s mkdir -p share/intel_alm/common
211s cp "./"/techlibs/intel_alm/common/abc9_model.v share/intel_alm/common/abc9_model.v
211s mkdir -p share/intel_alm/common
211s cp "./"/techlibs/intel_alm/common/alm_map.v share/intel_alm/common/alm_map.v
211s mkdir -p share/intel_alm/common
211s cp "./"/techlibs/intel_alm/common/alm_sim.v share/intel_alm/common/alm_sim.v
211s mkdir -p share/intel_alm/common
211s cp "./"/techlibs/intel_alm/common/arith_alm_map.v share/intel_alm/common/arith_alm_map.v
211s mkdir -p share/intel_alm/common
211s cp "./"/techlibs/intel_alm/common/dff_map.v share/intel_alm/common/dff_map.v
211s mkdir -p share/intel_alm/common
211s cp "./"/techlibs/intel_alm/common/dff_sim.v share/intel_alm/common/dff_sim.v
211s mkdir -p share/intel_alm/common
211s cp "./"/techlibs/intel_alm/common/dsp_sim.v share/intel_alm/common/dsp_sim.v
211s mkdir -p share/intel_alm/common
211s cp "./"/techlibs/intel_alm/common/dsp_map.v share/intel_alm/common/dsp_map.v
211s mkdir -p share/intel_alm/common
211s cp "./"/techlibs/intel_alm/common/mem_sim.v share/intel_alm/common/mem_sim.v
211s mkdir -p share/intel_alm/common
211s cp "./"/techlibs/intel_alm/common/misc_sim.v share/intel_alm/common/misc_sim.v
211s mkdir -p share/intel_alm/cyclonev
211s cp "./"/techlibs/intel_alm/cyclonev/cells_sim.v share/intel_alm/cyclonev/cells_sim.v
211s mkdir -p share/intel_alm/common
211s cp "./"/techlibs/intel_alm/common/bram_m10k.txt share/intel_alm/common/bram_m10k.txt
211s mkdir -p share/intel_alm/common
211s cp "./"/techlibs/intel_alm/common/bram_m10k_map.v share/intel_alm/common/bram_m10k_map.v
211s mkdir -p share/intel_alm/common
211s cp "./"/techlibs/intel_alm/common/bram_m20k.txt share/intel_alm/common/bram_m20k.txt
211s mkdir -p share/intel_alm/common
211s cp "./"/techlibs/intel_alm/common/bram_m20k_map.v share/intel_alm/common/bram_m20k_map.v
211s mkdir -p share/intel_alm/common
211s cp "./"/techlibs/intel_alm/common/lutram_mlab.txt share/intel_alm/common/lutram_mlab.txt
211s mkdir -p share/intel_alm/common
211s cp "./"/techlibs/intel_alm/common/megafunction_bb.v share/intel_alm/common/megafunction_bb.v
211s mkdir -p share/intel_alm/common
211s cp "./"/techlibs/intel_alm/common/quartus_rename.v share/intel_alm/common/quartus_rename.v
211s mkdir -p share/lattice
211s cp "./"/techlibs/lattice/cells_ff.vh share/lattice/cells_ff.vh
211s mkdir -p share/lattice
211s cp "./"/techlibs/lattice/cells_io.vh share/lattice/cells_io.vh
211s mkdir -p share/lattice
211s cp "./"/techlibs/lattice/cells_map.v share/lattice/cells_map.v
211s mkdir -p share/lattice
211s cp "./"/techlibs/lattice/common_sim.vh share/lattice/common_sim.vh
211s mkdir -p share/lattice
211s cp "./"/techlibs/lattice/ccu2d_sim.vh share/lattice/ccu2d_sim.vh
211s mkdir -p share/lattice
211s cp "./"/techlibs/lattice/ccu2c_sim.vh share/lattice/ccu2c_sim.vh
211s mkdir -p share/lattice
211s cp "./"/techlibs/lattice/cells_sim_ecp5.v share/lattice/cells_sim_ecp5.v
211s mkdir -p share/lattice
211s cp "./"/techlibs/lattice/cells_sim_xo2.v share/lattice/cells_sim_xo2.v
211s mkdir -p share/lattice
211s cp "./"/techlibs/lattice/cells_sim_xo3.v share/lattice/cells_sim_xo3.v
211s mkdir -p share/lattice
211s cp "./"/techlibs/lattice/cells_sim_xo3d.v share/lattice/cells_sim_xo3d.v
211s mkdir -p share/lattice
211s cp "./"/techlibs/lattice/cells_bb_ecp5.v share/lattice/cells_bb_ecp5.v
211s mkdir -p share/lattice
211s cp "./"/techlibs/lattice/cells_bb_xo2.v share/lattice/cells_bb_xo2.v
211s mkdir -p share/lattice
211s cp "./"/techlibs/lattice/cells_bb_xo3.v share/lattice/cells_bb_xo3.v
211s mkdir -p share/lattice
211s cp "./"/techlibs/lattice/cells_bb_xo3d.v share/lattice/cells_bb_xo3d.v
211s mkdir -p share/lattice
211s cp "./"/techlibs/lattice/lutrams_map.v share/lattice/lutrams_map.v
211s mkdir -p share/lattice
211s cp "./"/techlibs/lattice/lutrams.txt share/lattice/lutrams.txt
211s mkdir -p share/lattice
211s cp "./"/techlibs/lattice/brams_map_16kd.v share/lattice/brams_map_16kd.v
211s mkdir -p share/lattice
211s cp "./"/techlibs/lattice/brams_16kd.txt share/lattice/brams_16kd.txt
211s mkdir -p share/lattice
211s cp "./"/techlibs/lattice/brams_map_8kc.v share/lattice/brams_map_8kc.v
211s mkdir -p share/lattice
211s cp "./"/techlibs/lattice/brams_8kc.txt share/lattice/brams_8kc.txt
211s mkdir -p share/lattice
211s cp "./"/techlibs/lattice/arith_map_ccu2c.v share/lattice/arith_map_ccu2c.v
211s mkdir -p share/lattice
211s cp "./"/techlibs/lattice/arith_map_ccu2d.v share/lattice/arith_map_ccu2d.v
211s mkdir -p share/lattice
211s cp "./"/techlibs/lattice/latches_map.v share/lattice/latches_map.v
211s mkdir -p share/lattice
211s cp "./"/techlibs/lattice/dsp_map_18x18.v share/lattice/dsp_map_18x18.v
211s mkdir -p share/nexus
211s cp "./"/techlibs/nexus/cells_map.v share/nexus/cells_map.v
211s mkdir -p share/nexus
211s cp "./"/techlibs/nexus/cells_sim.v share/nexus/cells_sim.v
211s mkdir -p share/nexus
211s cp "./"/techlibs/nexus/parse_init.vh share/nexus/parse_init.vh
211s mkdir -p share/nexus
211s cp "./"/techlibs/nexus/cells_xtra.v share/nexus/cells_xtra.v
211s mkdir -p share/nexus
211s cp "./"/techlibs/nexus/lutrams_map.v share/nexus/lutrams_map.v
211s mkdir -p share/nexus
211s cp "./"/techlibs/nexus/lutrams.txt share/nexus/lutrams.txt
211s mkdir -p share/nexus
211s cp "./"/techlibs/nexus/brams_map.v share/nexus/brams_map.v
211s mkdir -p share/nexus
211s cp "./"/techlibs/nexus/brams.txt share/nexus/brams.txt
211s mkdir -p share/nexus
211s cp "./"/techlibs/nexus/lrams_map.v share/nexus/lrams_map.v
211s mkdir -p share/nexus
211s cp "./"/techlibs/nexus/lrams.txt share/nexus/lrams.txt
211s mkdir -p share/nexus
211s cp "./"/techlibs/nexus/arith_map.v share/nexus/arith_map.v
211s mkdir -p share/nexus
211s cp "./"/techlibs/nexus/latches_map.v share/nexus/latches_map.v
211s mkdir -p share/nexus
211s cp "./"/techlibs/nexus/dsp_map.v share/nexus/dsp_map.v
211s mkdir -p share/quicklogic
211s cp "./"/techlibs/quicklogic/pp3_ffs_map.v share/quicklogic/pp3_ffs_map.v
211s mkdir -p share/quicklogic
211s cp "./"/techlibs/quicklogic/pp3_lut_map.v share/quicklogic/pp3_lut_map.v
211s mkdir -p share/quicklogic
211s cp "./"/techlibs/quicklogic/pp3_latches_map.v share/quicklogic/pp3_latches_map.v
211s mkdir -p share/quicklogic
211s cp "./"/techlibs/quicklogic/pp3_cells_map.v share/quicklogic/pp3_cells_map.v
211s mkdir -p share/quicklogic
211s cp "./"/techlibs/quicklogic/cells_sim.v share/quicklogic/cells_sim.v
211s mkdir -p share/quicklogic
211s cp "./"/techlibs/quicklogic/lut_sim.v share/quicklogic/lut_sim.v
211s mkdir -p share/quicklogic
211s cp "./"/techlibs/quicklogic/pp3_cells_sim.v share/quicklogic/pp3_cells_sim.v
211s mkdir -p share/quicklogic
211s cp "./"/techlibs/quicklogic/abc9_model.v share/quicklogic/abc9_model.v
211s mkdir -p share/quicklogic
211s cp "./"/techlibs/quicklogic/abc9_map.v share/quicklogic/abc9_map.v
211s mkdir -p share/quicklogic
211s cp "./"/techlibs/quicklogic/abc9_unmap.v share/quicklogic/abc9_unmap.v
211s mkdir -p share/sf2
211s cp "./"/techlibs/sf2/arith_map.v share/sf2/arith_map.v
211s mkdir -p share/sf2
211s cp "./"/techlibs/sf2/cells_map.v share/sf2/cells_map.v
211s mkdir -p share/sf2
211s cp "./"/techlibs/sf2/cells_sim.v share/sf2/cells_sim.v
211s mkdir -p share/xilinx
211s cp "./"/techlibs/xilinx/cells_map.v share/xilinx/cells_map.v
211s mkdir -p share/xilinx
211s cp "./"/techlibs/xilinx/cells_sim.v share/xilinx/cells_sim.v
211s mkdir -p share/xilinx
211s cp "./"/techlibs/xilinx/cells_xtra.v share/xilinx/cells_xtra.v
211s mkdir -p share/xilinx
211s cp "./"/techlibs/xilinx/lutrams_xcv.txt share/xilinx/lutrams_xcv.txt
211s mkdir -p share/xilinx
211s cp "./"/techlibs/xilinx/lutrams_xcv_map.v share/xilinx/lutrams_xcv_map.v
211s mkdir -p share/xilinx
211s cp "./"/techlibs/xilinx/lutrams_xc5v.txt share/xilinx/lutrams_xc5v.txt
211s mkdir -p share/xilinx
211s cp "./"/techlibs/xilinx/lutrams_xcu.txt share/xilinx/lutrams_xcu.txt
211s mkdir -p share/xilinx
211s cp "./"/techlibs/xilinx/lutrams_xc5v_map.v share/xilinx/lutrams_xc5v_map.v
211s mkdir -p share/xilinx
211s cp "./"/techlibs/xilinx/brams_xcv.txt share/xilinx/brams_xcv.txt
211s mkdir -p share/xilinx
211s cp "./"/techlibs/xilinx/brams_xcv_map.v share/xilinx/brams_xcv_map.v
211s mkdir -p share/xilinx
211s cp "./"/techlibs/xilinx/brams_defs.vh share/xilinx/brams_defs.vh
211s mkdir -p share/xilinx
211s cp "./"/techlibs/xilinx/brams_xc2v.txt share/xilinx/brams_xc2v.txt
211s mkdir -p share/xilinx
211s cp "./"/techlibs/xilinx/brams_xc2v_map.v share/xilinx/brams_xc2v_map.v
211s mkdir -p share/xilinx
211s cp "./"/techlibs/xilinx/brams_xc3sda.txt share/xilinx/brams_xc3sda.txt
211s mkdir -p share/xilinx
211s cp "./"/techlibs/xilinx/brams_xc3sda_map.v share/xilinx/brams_xc3sda_map.v
211s mkdir -p share/xilinx
211s cp "./"/techlibs/xilinx/brams_xc4v.txt share/xilinx/brams_xc4v.txt
211s mkdir -p share/xilinx
211s cp "./"/techlibs/xilinx/brams_xc4v_map.v share/xilinx/brams_xc4v_map.v
211s mkdir -p share/xilinx
211s cp "./"/techlibs/xilinx/brams_xc5v_map.v share/xilinx/brams_xc5v_map.v
211s mkdir -p share/xilinx
211s cp "./"/techlibs/xilinx/brams_xc6v_map.v share/xilinx/brams_xc6v_map.v
211s mkdir -p share/xilinx
211s cp "./"/techlibs/xilinx/brams_xcu_map.v share/xilinx/brams_xcu_map.v
211s mkdir -p share/xilinx
211s cp "./"/techlibs/xilinx/urams.txt share/xilinx/urams.txt
211s mkdir -p share/xilinx
211s cp "./"/techlibs/xilinx/urams_map.v share/xilinx/urams_map.v
211s mkdir -p share/xilinx
211s cp "./"/techlibs/xilinx/arith_map.v share/xilinx/arith_map.v
211s mkdir -p share/xilinx
211s cp "./"/techlibs/xilinx/ff_map.v share/xilinx/ff_map.v
211s mkdir -p share/xilinx
211s cp "./"/techlibs/xilinx/lut_map.v share/xilinx/lut_map.v
211s mkdir -p share/xilinx
211s cp "./"/techlibs/xilinx/mux_map.v share/xilinx/mux_map.v
211s mkdir -p share/xilinx
211s cp "./"/techlibs/xilinx/xc3s_mult_map.v share/xilinx/xc3s_mult_map.v
211s mkdir -p share/xilinx
211s cp "./"/techlibs/xilinx/xc3sda_dsp_map.v share/xilinx/xc3sda_dsp_map.v
211s mkdir -p share/xilinx
211s cp "./"/techlibs/xilinx/xc6s_dsp_map.v share/xilinx/xc6s_dsp_map.v
211s mkdir -p share/xilinx
211s cp "./"/techlibs/xilinx/xc4v_dsp_map.v share/xilinx/xc4v_dsp_map.v
211s mkdir -p share/xilinx
211s cp "./"/techlibs/xilinx/xc5v_dsp_map.v share/xilinx/xc5v_dsp_map.v
211s mkdir -p share/xilinx
211s cp "./"/techlibs/xilinx/xc7_dsp_map.v share/xilinx/xc7_dsp_map.v
211s mkdir -p share/xilinx
211s cp "./"/techlibs/xilinx/xcu_dsp_map.v share/xilinx/xcu_dsp_map.v
211s mkdir -p share/xilinx
211s cp "./"/techlibs/xilinx/abc9_model.v share/xilinx/abc9_model.v
211s cd tests/simple && bash run-test.sh ""
211s make[1]: Entering directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/simple'
211s + gcc -Wall -o /tmp/autopkgtest.iWd4A5/build.UL3/src/tests/tools/cmp_tbdata /tmp/autopkgtest.iWd4A5/build.UL3/src/tests/tools/cmp_tbdata.c
212s Test: arrays02 -> ok
215s Test: asgn_binop -> ok
215s Test: case_expr_extend -> ok
215s Test: case_expr_query -> ok
216s Test: defvalue -> ok
216s Test: implicit_ports -> ok
217s Test: lesser_size_cast -> ok
217s Test: local_loop_var -> ok
218s Test: macro_arg_spaces -> ok
218s Test: matching_end_labels -> ok
218s Test: memwr_port_connection -> ok
219s Test: unnamed_block_decl -> ok
219s Test: aes_kexp128 -> ok
220s Test: always01 -> ok
220s Test: always02 -> ok
221s Test: always03 -> ok
221s Test: arraycells -> ok
222s Test: arrays01 -> ok
222s Test: attrib01_module -> ok
222s Test: attrib02_port_decl -> ok
223s Test: attrib03_parameter -> ok
224s Test: attrib04_net_var -> ok
224s Test: attrib06_operator_suffix -> ok
225s Test: attrib08_mod_inst -> ok
225s Test: attrib09_case -> ok
226s Test: carryadd -> ok
226s Test: case_expr_const -> ok
226s Test: case_expr_non_const -> ok
237s Test: case_large -> ok
237s Test: const_branch_finish -> ok
238s Test: const_fold_func -> ok
239s Test: const_func_shadow -> ok
242s Test: constmuldivmod -> ok
242s Test: constpower -> ok
244s Test: dff_different_styles -> ok
245s Test: dff_init -> ok
247s Test: dynslice -> ok
248s Test: fiedler-cooley -> ok
249s Test: forgen01 -> ok
249s Test: forgen02 -> ok
250s Test: forloops -> ok
250s Test: fsm -> ok
251s Test: func_block -> ok
252s Test: func_recurse -> ok
252s Test: func_width_scope -> ok
253s Test: genblk_collide -> ok
253s Test: genblk_dive -> ok
253s Test: genblk_order -> ok
253s Test: genblk_port_shadow -> ok
257s Test: generate -> ok
258s Test: graphtest -> ok
258s Test: hierarchy -> ok
259s Test: hierdefparam -> ok
260s Test: i2c_master_tests -> ok
260s Test: ifdef_1 -> ok
260s Test: ifdef_2 -> ok
260s Test: localparam_attr -> ok
261s Test: loop_prefix_case -> ok
261s Test: loop_var_shadow -> ok
262s Test: loops -> ok
262s Test: macro_arg_surrounding_spaces -> ok
263s Test: macros -> ok
265s Test: mem2reg -> ok
265s Test: mem2reg_bounds_tern -> ok
267s Test: mem_arst -> ok
278s Test: memory -> ok
278s Test: module_scope -> ok
279s Test: module_scope_case -> ok
279s Test: module_scope_func -> ok
280s Test: multiplier -> ok
281s Test: muxtree -> ok
281s Test: named_genblk -> ok
282s Test: nested_genblk_resolve -> ok
282s Test: omsp_dbg_uart -> ok
290s Test: operators -> ok
291s Test: param_attr -> ok
292s Test: paramods -> ok
298s Test: partsel -> ok
299s Test: process -> ok
300s Test: realexpr -> ok
300s Test: repwhile -> ok
301s Test: retime -> ok
307s Test: rotate -> ok
308s Test: scopes -> ok
308s Test: signed_full_slice -> ok
309s Test: signedexpr -> ok
311s Test: sincos -> ok
311s Test: specify -> ok
312s Test: string_format -> ok
312s Test: subbytes -> ok
314s Test: task_func -> ok
314s Test: undef_eqx_nex -> ok
315s Test: usb_phy_tests -> ok
316s Test: values -> ok
316s Test: verilog_primitives -> ok
317s Test: vloghammer -> ok
318s Test: wandwor -> ok
320s Test: wreduce -> ok
320s make[1]: Leaving directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/simple'
320s cd tests/simple_abc9 && bash run-test.sh ""
320s ls: cannot access '*.sv': No such file or directory
320s make[1]: Entering directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/simple_abc9'
325s Test: abc9 -> ok
325s Test: aes_kexp128 -> ok
325s Test: always01 -> ok
325s Test: always02 -> ok
325s Test: always03 -> ok
325s Test: arraycells -> ok
325s Test: arrays01 -> ok
326s Test: attrib01_module -> ok
326s Test: attrib02_port_decl -> ok
327s Test: attrib03_parameter -> ok
327s Test: attrib04_net_var -> ok
327s Test: attrib06_operator_suffix -> ok
328s Test: attrib08_mod_inst -> ok
328s Test: attrib09_case -> ok
328s Test: carryadd -> ok
329s Test: case_expr_const -> ok
329s Test: case_expr_non_const -> ok
353s Test: case_large -> ok
353s Test: const_branch_finish -> ok
353s Test: const_fold_func -> ok
354s Test: const_func_shadow -> ok
358s Test: constmuldivmod -> ok
358s Test: constpower -> ok
359s Test: dff_different_styles -> ok
360s Test: dff_init -> ok
372s Test: dynslice -> ok
373s Test: fiedler-cooley -> ok
373s Test: forgen01 -> ok
373s Test: forgen02 -> ok
374s Test: forloops -> ok
374s Test: fsm -> ok
375s Test: func_block -> ok
375s Test: func_recurse -> ok
375s Test: func_width_scope -> ok
376s Test: genblk_collide -> ok
376s Test: genblk_dive -> ok
376s Test: genblk_order -> ok
376s Test: genblk_port_shadow -> ok
380s Test: generate -> ok
380s Test: graphtest -> ok
380s Test: hierarchy -> ok
381s Test: hierdefparam -> ok
381s Test: i2c_master_tests -> ok
382s Test: ifdef_1 -> ok
382s Test: ifdef_2 -> ok
382s Test: localparam_attr -> ok
382s Test: loop_prefix_case -> ok
383s Test: loop_var_shadow -> ok
383s Test: loops -> ok
383s Test: macro_arg_surrounding_spaces -> ok
384s Test: macros -> ok
385s Test: mem2reg -> ok
386s Test: mem2reg_bounds_tern -> ok
386s Test: mem_arst -> ok
392s Test: memory -> ok
392s Test: module_scope -> ok
393s Test: module_scope_case -> ok
393s Test: module_scope_func -> ok
394s Test: multiplier -> ok
395s Test: muxtree -> ok
395s Test: named_genblk -> ok
395s Test: nested_genblk_resolve -> ok
395s Test: omsp_dbg_uart -> ok
415s Test: operators -> ok
415s Test: param_attr -> ok
416s Test: paramods -> ok
425s Test: partsel -> ok
425s Test: process -> ok
426s Test: realexpr -> ok
426s Test: repwhile -> ok
427s Test: retime -> ok
429s Test: rotate -> ok
430s Test: scopes -> ok
430s Test: signed_full_slice -> ok
431s Test: signedexpr -> ok
435s Test: sincos -> ok
436s Test: string_format -> ok
436s Test: subbytes -> ok
437s Test: task_func -> ok
438s Test: undef_eqx_nex -> ok
438s Test: usb_phy_tests -> ok
439s Test: values -> ok
439s Test: verilog_primitives -> ok
440s Test: vloghammer -> ok
441s Test: wandwor -> ok
443s Test: wreduce -> ok
443s Test: arrays02 -> ok
446s Test: asgn_binop -> ok
446s Test: case_expr_extend -> ok
446s Test: case_expr_query -> ok
447s Test: defvalue -> ok
447s Test: implicit_ports -> ok
447s Test: lesser_size_cast -> ok
447s Test: local_loop_var -> ok
449s Test: macro_arg_spaces -> ok
449s Test: matching_end_labels -> ok
450s Test: memwr_port_connection -> ok
450s Test: unnamed_block_decl -> ok
450s make[1]: Leaving directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/simple_abc9'
450s cd tests/hana && bash run-test.sh ""
450s make[1]: Entering directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/hana'
455s Test: test_intermout -> ok
455s Test: test_parse2synthtrans -> ok
456s Test: test_parser -> ok
458s Test: test_simulation_always -> ok
459s Test: test_simulation_and -> ok
459s Test: test_simulation_buffer -> ok
460s Test: test_simulation_decoder -> ok
461s Test: test_simulation_inc -> ok
463s Test: test_simulation_mux -> ok
464s Test: test_simulation_nand -> ok
464s Test: test_simulation_nor -> ok
465s Test: test_simulation_or -> ok
465s Test: test_simulation_seq -> ok
469s Test: test_simulation_shifter -> ok
470s Test: test_simulation_sop -> ok
471s Test: test_simulation_techmap -> ok
475s Test: test_simulation_techmap_tech -> ok
475s Test: test_simulation_vlib -> ok
476s Test: test_simulation_xnor -> ok
476s Test: test_simulation_xor -> ok
476s make[1]: Leaving directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/hana'
476s cd tests/asicworld && bash run-test.sh ""
476s make[1]: Entering directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/asicworld'
477s Test: code_hdl_models_GrayCounter -> ok
477s Test: code_hdl_models_arbiter -> ok
489s Test: code_hdl_models_cam -> ok
489s Test: code_hdl_models_clk_div -> ok
490s Test: code_hdl_models_clk_div_45 -> ok
490s Test: code_hdl_models_d_ff_gates -> ok
490s Test: code_hdl_models_d_latch_gates -> ok
491s Test: code_hdl_models_decoder_2to4_gates -> ok
491s Test: code_hdl_models_decoder_using_assign -> ok
492s Test: code_hdl_models_decoder_using_case -> ok
492s Test: code_hdl_models_dff_async_reset -> ok
493s Test: code_hdl_models_dff_sync_reset -> ok
493s Test: code_hdl_models_encoder_4to2_gates -> ok
494s Test: code_hdl_models_encoder_using_case -> ok
494s Test: code_hdl_models_encoder_using_if -> ok
495s Test: code_hdl_models_full_adder_gates -> ok
495s Test: code_hdl_models_full_subtracter_gates -> ok
497s Test: code_hdl_models_gray_counter -> ok
497s Test: code_hdl_models_half_adder_gates -> ok
497s Test: code_hdl_models_lfsr -> ok
497s Test: code_hdl_models_lfsr_updown -> ok
497s Test: code_hdl_models_mux_2to1_gates -> ok
497s Test: code_hdl_models_mux_using_assign -> ok
498s Test: code_hdl_models_mux_using_case -> ok
498s Test: code_hdl_models_mux_using_if -> ok
499s Test: code_hdl_models_one_hot_cnt -> ok
499s Test: code_hdl_models_parallel_crc -> ok
499s Test: code_hdl_models_parity_using_assign -> ok
500s Test: code_hdl_models_parity_using_bitwise -> ok
500s Test: code_hdl_models_parity_using_function -> ok
501s Test: code_hdl_models_pri_encoder_using_assign -> ok
501s Test: code_hdl_models_rom_using_case -> ok
502s Test: code_hdl_models_serial_crc -> ok
502s Test: code_hdl_models_tff_async_reset -> ok
503s Test: code_hdl_models_tff_sync_reset -> ok
504s Test: code_hdl_models_uart -> ok
505s Test: code_hdl_models_up_counter -> ok
505s Test: code_hdl_models_up_counter_load -> ok
506s Test: code_hdl_models_up_down_counter -> ok
507s Test: code_specman_switch_fabric -> ok
507s Test: code_tidbits_asyn_reset -> ok
508s Test: code_tidbits_blocking -> ok
508s Test: code_tidbits_fsm_using_always -> ok
509s Test: code_tidbits_fsm_using_function -> ok
509s Test: code_tidbits_fsm_using_single_always -> ok
510s Test: code_tidbits_nonblocking -> ok
510s Test: code_tidbits_reg_combo_example -> ok
510s Test: code_tidbits_reg_seq_example -> ok
511s Test: code_tidbits_syn_reset -> ok
511s Test: code_tidbits_wire_example -> ok
512s Test: code_verilog_tutorial_addbit -> ok
512s Test: code_verilog_tutorial_always_example -> ok
512s Test: code_verilog_tutorial_bus_con -> ok
512s Test: code_verilog_tutorial_comment -> ok
513s Test: code_verilog_tutorial_counter -> ok
513s Test: code_verilog_tutorial_d_ff -> ok
514s Test: code_verilog_tutorial_decoder -> ok
514s Test: code_verilog_tutorial_decoder_always -> ok
514s Test: code_verilog_tutorial_escape_id -> ok
515s Test: code_verilog_tutorial_explicit -> ok
515s Test: code_verilog_tutorial_first_counter -> ok
516s Test: code_verilog_tutorial_flip_flop -> ok
516s Test: code_verilog_tutorial_fsm_full -> ok
517s Test: code_verilog_tutorial_good_code -> ok
517s Test: code_verilog_tutorial_if_else -> ok
517s Test: code_verilog_tutorial_multiply -> ok
518s Test: code_verilog_tutorial_mux_21 -> ok
518s Test: code_verilog_tutorial_n_out_primitive -> ok
518s Test: code_verilog_tutorial_parallel_if -> ok
519s Test: code_verilog_tutorial_parity -> ok
519s Test: code_verilog_tutorial_simple_function -> ok
519s Test: code_verilog_tutorial_simple_if -> ok
519s Test: code_verilog_tutorial_task_global -> ok
520s Test: code_verilog_tutorial_tri_buf -> ok
520s Test: code_verilog_tutorial_v2k_reg -> ok
521s Test: code_verilog_tutorial_which_clock -> ok
521s make[1]: Leaving directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/asicworld'
521s # +cd tests/realmath && bash run-test.sh ""
521s cd tests/share && bash run-test.sh ""
521s generating tests..
521s running tests..
525s [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41][42][43][44][45][46][47][48][49][50][51][52][53][54][55][56][57][58][59][60][61][62][63][64][65][66][67][68][69][70][71][72][73][74][75][76][77][78][79][80][81][82][83][84][85][86][87][88][89][90][91][92][93][94][95][96][97][98][99]
525s cd tests/opt_share && bash run-test.sh ""
525s generating tests..
526s running tests..
526s make[1]: Entering directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/opt_share'
666s [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41][42][43][44][45][46][47][48][49][50][51][52][53][54][55][56][57][58][59][60][61][62][63][64][65][66][67][68][69][70][71][72][73][74][75][76][77][78][79][80][81][82][83][84][85][86][87][88][89][90][91][92][93][94][95][96][97][98][99]make[1]: Leaving directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/opt_share'
666s 
666s cd tests/fsm && bash run-test.sh ""
666s generating tests..
666s PRNG seed: 1172554494
666s running tests..
666s make[1]: Entering directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/fsm'
666s [0]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
666s     Users of state reg look like FSM recoding might result in larger circuit.
666s     Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
668s K[1]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
668s     Users of state reg look like FSM recoding might result in larger circuit.
668s     Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
672s K[2]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
672s     Users of state reg look like FSM recoding might result in larger circuit.
672s     Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
676s K[3]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
676s     Users of state reg look like FSM recoding might result in larger circuit.
676s     Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
679s K[4]K[5]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
679s     Users of state reg look like FSM recoding might result in larger circuit.
679s     Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
697s K[6]K[7]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
697s     Users of state reg look like FSM recoding might result in larger circuit.
697s     Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
697s K[8]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
697s     Users of state reg look like FSM recoding might result in larger circuit.
697s     Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
703s K[9]K[10]K[11]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
703s     Users of state reg look like FSM recoding might result in larger circuit.
703s     Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
707s K[12]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
707s     Users of state reg look like FSM recoding might result in larger circuit.
707s     Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
710s K[13]K[14]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
710s     Users of state reg look like FSM recoding might result in larger circuit.
710s     Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
713s K[15]K[16]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
713s     Users of state reg look like FSM recoding might result in larger circuit.
713s     Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
714s K[17]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
714s     Users of state reg look like FSM recoding might result in larger circuit.
714s     Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
717s K[18]K[19]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
717s     Users of state reg look like FSM recoding might result in larger circuit.
717s     Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
746s T[20]K[21]K[22]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
746s     Users of state reg look like FSM recoding might result in larger circuit.
746s     Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
756s K[23]K[24]K[25]K[26]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
756s     Users of state reg look like FSM recoding might result in larger circuit.
756s     Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
778s T[27]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
778s     Users of state reg look like FSM recoding might result in larger circuit.
778s     Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
781s K[28]K[29]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
781s     Users of state reg look like FSM recoding might result in larger circuit.
781s     Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
793s K[30]K[31]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
793s     Users of state reg look like FSM recoding might result in larger circuit.
793s     Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
815s T[32]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
815s     Users of state reg look like FSM recoding might result in larger circuit.
815s     Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
817s K[33]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
817s     Users of state reg look like FSM recoding might result in larger circuit.
817s     Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
819s K[34]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
819s     Users of state reg look like FSM recoding might result in larger circuit.
819s     Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
822s K[35]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
822s     Users of state reg look like FSM recoding might result in larger circuit.
822s     Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
825s K[36]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
825s     Users of state reg look like FSM recoding might result in larger circuit.
825s     Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
834s K[37]K[38]K[39]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
834s     Users of state reg look like FSM recoding might result in larger circuit.
834s     Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
838s K[40]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
838s     Users of state reg look like FSM recoding might result in larger circuit.
838s     Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
842s K[41]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
842s     Users of state reg look like FSM recoding might result in larger circuit.
842s     Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
843s K[42]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
843s     Users of state reg look like FSM recoding might result in larger circuit.
843s     Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
848s K[43]K[44]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
848s     Users of state reg look like FSM recoding might result in larger circuit.
848s     Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
849s K[45]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
849s     Users of state reg look like FSM recoding might result in larger circuit.
849s     Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
852s K[46]K[47]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
852s     Users of state reg look like FSM recoding might result in larger circuit.
852s     Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
854s K[48]K[49]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
854s     Users of state reg look like FSM recoding might result in larger circuit.
854s     Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
860s K
860s make[1]: Leaving directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/fsm'
860s cd tests/techmap && bash run-test.sh
860s make[1]: Entering directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/techmap'
861s Passed abc9.ys
861s Warning: wire '\Q' is assigned in a block at <<EOT:9.5-9.11.
861s Warning: wire '\Q' is assigned in a block at <<EOT:11.5-11.11.
861s Passed adff2dff.ys
862s Passed aigmap.ys
862s Warning: Resizing cell port top.s0.f.j from 2 bits to 1 bits.
862s Passed autopurge.ys
862s Passed bmuxmap_pmux.ys
862s Passed bug2183.ys
862s Passed bug2321.ys
862s Passed bug2332.ys
862s Passed bug2759.ys
862s Passed bug2972.ys
862s Passed cellname.ys
862s Passed clkbufmap.ys
864s Passed cmp2lcu.ys
864s Warning: wire '\Q' is assigned in a block at <<EOT:8.3-8.9.
864s Passed dff2ff.ys
864s Passed dffinit.ys
864s Passed dfflegalize_adff.ys
864s Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe1_.ff1
864s Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe1_.ff2
864s Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe1_.ff3
864s Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adff1_.ff1
864s Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adff1_.ff2
864s Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe1_.ff0
864s Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adff1_.ff0
864s Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe0_.ff1
864s Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe0_.ff2
864s Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe0_.ff3
864s Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adff0_.ff1
864s Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adff0_.ff2
864s Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe0_.ff0
864s Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adff0_.ff0
865s Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe1.ff3
865s Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe1.ff2
865s Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe1.ff1
865s Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe1.ff0
865s Warning: Emulating mismatched async reset and init with several FFs and a mux for adff1.ff2
865s Warning: Emulating mismatched async reset and init with several FFs and a mux for adff1.ff1
865s Warning: Emulating mismatched async reset and init with several FFs and a mux for adff1.ff0
865s Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe0.ff3
865s Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe0.ff2
865s Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe0.ff1
865s Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe0.ff0
865s Warning: Emulating mismatched async reset and init with several FFs and a mux for adff0.ff2
865s Warning: Emulating mismatched async reset and init with several FFs and a mux for adff0.ff1
865s Warning: Emulating mismatched async reset and init with several FFs and a mux for adff0.ff0
865s Passed dfflegalize_adff_init.ys
865s Passed dfflegalize_adlatch.ys
865s Warning: Emulating mismatched async reset and init with several latches and a mux for top.adlatch1_.ff1
865s Warning: Emulating mismatched async reset and init with several latches and a mux for top.adlatch1_.ff2
865s Warning: Emulating mismatched async reset and init with several latches and a mux for top.adlatch1_.ff0
865s Warning: Emulating mismatched async reset and init with several latches and a mux for top.adlatch0_.ff1
865s Warning: Emulating mismatched async reset and init with several latches and a mux for top.adlatch0_.ff2
865s Warning: Emulating mismatched async reset and init with several latches and a mux for top.adlatch0_.ff0
866s Warning: Emulating mismatched async reset and init with several latches and a mux for adlatch1.ff2
866s Warning: Emulating mismatched async reset and init with several latches and a mux for adlatch1.ff1
866s Warning: Emulating mismatched async reset and init with several latches and a mux for adlatch1.ff0
866s Warning: Emulating mismatched async reset and init with several latches and a mux for adlatch0.ff2
866s Warning: Emulating mismatched async reset and init with several latches and a mux for adlatch0.ff1
866s Warning: Emulating mismatched async reset and init with several latches and a mux for adlatch0.ff0
866s Passed dfflegalize_adlatch_init.ys
866s Passed dfflegalize_aldff.ys
866s Passed dfflegalize_aldff_init.ys
867s Passed dfflegalize_dff.ys
870s Passed dfflegalize_dff_init.ys
870s Warning: Emulating async set + reset with several FFs and a mux for top.dffsre_.ff1
870s Warning: Emulating async set + reset with several FFs and a mux for top.dffsre_.ff2
870s Warning: Emulating async set + reset with several FFs and a mux for top.dffsre_.ff3
870s Warning: Emulating async set + reset with several FFs and a mux for top.dffsre_.ff4
870s Warning: Emulating async set + reset with several FFs and a mux for top.dffsr_.ff1
870s Warning: Emulating async set + reset with several FFs and a mux for top.dffsr_.ff2
870s Warning: Emulating async set + reset with several FFs and a mux for top.dffsr_.ff3
870s Warning: Emulating async set + reset with several FFs and a mux for top.dffsre_.ff0
870s Warning: Emulating async set + reset with several FFs and a mux for top.dffsr_.ff0
870s Warning: Emulating async set + reset with several FFs and a mux for dffsre.ff4
870s Warning: Emulating async set + reset with several FFs and a mux for dffsre.ff3
870s Warning: Emulating async set + reset with several FFs and a mux for dffsre.ff2
870s Warning: Emulating async set + reset with several FFs and a mux for dffsre.ff1
870s Warning: Emulating async set + reset with several FFs and a mux for dffsre.ff0
870s Warning: Emulating async set + reset with several FFs and a mux for dffsr.ff3
870s Warning: Emulating async set + reset with several FFs and a mux for dffsr.ff2
870s Warning: Emulating async set + reset with several FFs and a mux for dffsr.ff1
870s Warning: Emulating async set + reset with several FFs and a mux for dffsr.ff0
870s Passed dfflegalize_dffsr.ys
870s Warning: Emulating async set + reset with several FFs and a mux for top.dffsre1_.ff1
870s Warning: Emulating async set + reset with several FFs and a mux for top.dffsre1_.ff2
870s Warning: Emulating async set + reset with several FFs and a mux for top.dffsre1_.ff3
870s Warning: Emulating async set + reset with several FFs and a mux for top.dffsre1_.ff4
870s Warning: Emulating async set + reset with several FFs and a mux for top.dffsre0_.ff1
870s Warning: Emulating async set + reset with several FFs and a mux for top.dffsre0_.ff2
870s Warning: Emulating async set + reset with several FFs and a mux for top.dffsre0_.ff3
870s Warning: Emulating async set + reset with several FFs and a mux for top.dffsre0_.ff4
870s Warning: Emulating async set + reset with several FFs and a mux for top.dffsr1_.ff1
870s Warning: Emulating async set + reset with several FFs and a mux for top.dffsr1_.ff2
870s Warning: Emulating async set + reset with several FFs and a mux for top.dffsr1_.ff3
870s Warning: Emulating async set + reset with several FFs and a mux for top.dffsr0_.ff1
870s Warning: Emulating async set + reset with several FFs and a mux for top.dffsr0_.ff2
870s Warning: Emulating async set + reset with several FFs and a mux for top.dffsr0_.ff3
870s Warning: Emulating async set + reset with several FFs and a mux for top.dffsre1_.ff0
870s Warning: Emulating async set + reset with several FFs and a mux for top.dffsre0_.ff0
870s Warning: Emulating async set + reset with several FFs and a mux for top.dffsr1_.ff0
870s Warning: Emulating async set + reset with several FFs and a mux for top.dffsr0_.ff0
871s Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre1_.ff1 [$_DFFSRE_PPPN_].
871s Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre1_.ff2 [$_DFFSRE_PPNP_].
871s Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre1_.ff3 [$_DFFSRE_PNPP_].
871s Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre1_.ff4 [$_DFFSRE_NPPP_].
871s Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr1_.ff1 [$_DFFSR_PPN_].
871s Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr1_.ff2 [$_DFFSR_PNP_].
871s Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr1_.ff3 [$_DFFSR_NPP_].
871s Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre1_.ff0 [$_DFFSRE_PPPP_].
871s Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr1_.ff0 [$_DFFSR_PPP_].
871s Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre0_.ff1 [$_DFFSRE_PPPN_].
871s Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre0_.ff2 [$_DFFSRE_PPNP_].
871s Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre0_.ff3 [$_DFFSRE_PNPP_].
871s Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre0_.ff4 [$_DFFSRE_NPPP_].
871s Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr0_.ff1 [$_DFFSR_PPN_].
871s Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr0_.ff2 [$_DFFSR_PNP_].
871s Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr0_.ff3 [$_DFFSR_NPP_].
871s Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre0_.ff0 [$_DFFSRE_PPPP_].
871s Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr0_.ff0 [$_DFFSR_PPP_].
872s Warning: Emulating async set + reset with several FFs and a mux for dffsre1.ff4
872s Warning: Emulating async set + reset with several FFs and a mux for dffsre1.ff3
872s Warning: Emulating async set + reset with several FFs and a mux for dffsre1.ff2
872s Warning: Emulating async set + reset with several FFs and a mux for dffsre1.ff1
872s Warning: Emulating async set + reset with several FFs and a mux for dffsre1.ff0
872s Warning: Emulating async set + reset with several FFs and a mux for dffsre0.ff4
872s Warning: Emulating async set + reset with several FFs and a mux for dffsre0.ff3
872s Warning: Emulating async set + reset with several FFs and a mux for dffsre0.ff2
872s Warning: Emulating async set + reset with several FFs and a mux for dffsre0.ff1
872s Warning: Emulating async set + reset with several FFs and a mux for dffsre0.ff0
872s Warning: Emulating async set + reset with several FFs and a mux for dffsr1.ff3
872s Warning: Emulating async set + reset with several FFs and a mux for dffsr1.ff2
872s Warning: Emulating async set + reset with several FFs and a mux for dffsr1.ff1
872s Warning: Emulating async set + reset with several FFs and a mux for dffsr1.ff0
872s Warning: Emulating async set + reset with several FFs and a mux for dffsr0.ff3
872s Warning: Emulating async set + reset with several FFs and a mux for dffsr0.ff2
872s Warning: Emulating async set + reset with several FFs and a mux for dffsr0.ff1
872s Warning: Emulating async set + reset with several FFs and a mux for dffsr0.ff0
872s Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre1.ff4 [$_DFFSRE_NPPP_].
872s Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre1.ff3 [$_DFFSRE_PNPP_].
872s Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre1.ff2 [$_DFFSRE_PPNP_].
872s Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre1.ff1 [$_DFFSRE_PPPN_].
872s Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre1.ff0 [$_DFFSRE_PPPP_].
872s Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr1.ff3 [$_DFFSR_NPP_].
872s Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr1.ff2 [$_DFFSR_PNP_].
872s Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr1.ff1 [$_DFFSR_PPN_].
872s Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr1.ff0 [$_DFFSR_PPP_].
872s Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre0.ff4 [$_DFFSRE_NPPP_].
872s Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre0.ff3 [$_DFFSRE_PNPP_].
872s Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre0.ff2 [$_DFFSRE_PPNP_].
872s Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre0.ff1 [$_DFFSRE_PPPN_].
872s Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre0.ff0 [$_DFFSRE_PPPP_].
872s Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr0.ff3 [$_DFFSR_NPP_].
872s Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr0.ff2 [$_DFFSR_PNP_].
872s Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr0.ff1 [$_DFFSR_PPN_].
872s Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr0.ff0 [$_DFFSR_PPP_].
872s Passed dfflegalize_dffsr_init.ys
872s Passed dfflegalize_dlatch.ys
872s Passed dfflegalize_dlatch_const.ys
872s Passed dfflegalize_dlatch_init.ys
872s Warning: Emulating async set + reset with several FFs and a mux for dlatchsr.ff3
872s Warning: Emulating async set + reset with several FFs and a mux for dlatchsr.ff2
872s Warning: Emulating async set + reset with several FFs and a mux for dlatchsr.ff1
872s Warning: Emulating async set + reset with several FFs and a mux for dlatchsr.ff0
872s Passed dfflegalize_dlatchsr.ys
872s Warning: Emulating async set + reset with several FFs and a mux for top.dlatchsr1_.ff1
872s Warning: Emulating async set + reset with several FFs and a mux for top.dlatchsr1_.ff2
872s Warning: Emulating async set + reset with several FFs and a mux for top.dlatchsr1_.ff3
872s Warning: Emulating async set + reset with several FFs and a mux for top.dlatchsr0_.ff1
872s Warning: Emulating async set + reset with several FFs and a mux for top.dlatchsr0_.ff2
872s Warning: Emulating async set + reset with several FFs and a mux for top.dlatchsr0_.ff3
872s Warning: Emulating async set + reset with several FFs and a mux for top.dlatchsr1_.ff0
872s Warning: Emulating async set + reset with several FFs and a mux for top.dlatchsr0_.ff0
872s Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr1_.ff1 [$_DLATCHSR_PPN_].
872s Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr1_.ff2 [$_DLATCHSR_PNP_].
872s Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr1_.ff3 [$_DLATCHSR_NPP_].
872s Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr1_.ff0 [$_DLATCHSR_PPP_].
872s Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr0_.ff1 [$_DLATCHSR_PPN_].
872s Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr0_.ff2 [$_DLATCHSR_PNP_].
872s Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr0_.ff3 [$_DLATCHSR_NPP_].
872s Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr0_.ff0 [$_DLATCHSR_PPP_].
872s Warning: Emulating async set + reset with several FFs and a mux for dlatchsr1.ff3
872s Warning: Emulating async set + reset with several FFs and a mux for dlatchsr1.ff2
872s Warning: Emulating async set + reset with several FFs and a mux for dlatchsr1.ff1
872s Warning: Emulating async set + reset with several FFs and a mux for dlatchsr1.ff0
872s Warning: Emulating async set + reset with several FFs and a mux for dlatchsr0.ff3
872s Warning: Emulating async set + reset with several FFs and a mux for dlatchsr0.ff2
872s Warning: Emulating async set + reset with several FFs and a mux for dlatchsr0.ff1
872s Warning: Emulating async set + reset with several FFs and a mux for dlatchsr0.ff0
872s Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr1.ff3 [$_DLATCHSR_NPP_].
872s Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr1.ff2 [$_DLATCHSR_PNP_].
872s Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr1.ff1 [$_DLATCHSR_PPN_].
872s Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr1.ff0 [$_DLATCHSR_PPP_].
872s Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr0.ff3 [$_DLATCHSR_NPP_].
872s Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr0.ff2 [$_DLATCHSR_PNP_].
872s Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr0.ff1 [$_DLATCHSR_PPN_].
872s Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr0.ff0 [$_DLATCHSR_PPP_].
872s Passed dfflegalize_dlatchsr_init.ys
873s Passed dfflegalize_inv.ys
873s Passed dfflegalize_mince.ys
873s Passed dfflegalize_minsrst.ys
873s Passed dfflegalize_sr.ys
873s Warning: Flipping D/Q/init and inserting priority fixup to legalize top.sr1_.ff1 [$_SR_PN_].
873s Warning: Flipping D/Q/init and inserting priority fixup to legalize top.sr1_.ff2 [$_SR_NP_].
873s Warning: Flipping D/Q/init and inserting priority fixup to legalize top.sr1_.ff0 [$_SR_PP_].
873s Warning: Flipping D/Q/init and inserting priority fixup to legalize top.sr0_.ff1 [$_SR_PN_].
873s Warning: Flipping D/Q/init and inserting priority fixup to legalize top.sr0_.ff2 [$_SR_NP_].
873s Warning: Flipping D/Q/init and inserting priority fixup to legalize top.sr0_.ff0 [$_SR_PP_].
873s Warning: Flipping D/Q/init and inserting priority fixup to legalize sr1.ff2 [$_SR_NP_].
873s Warning: Flipping D/Q/init and inserting priority fixup to legalize sr1.ff1 [$_SR_PN_].
873s Warning: Flipping D/Q/init and inserting priority fixup to legalize sr1.ff0 [$_SR_PP_].
873s Warning: Flipping D/Q/init and inserting priority fixup to legalize sr0.ff2 [$_SR_NP_].
873s Warning: Flipping D/Q/init and inserting priority fixup to legalize sr0.ff1 [$_SR_PN_].
873s Warning: Flipping D/Q/init and inserting priority fixup to legalize sr0.ff0 [$_SR_PP_].
873s Passed dfflegalize_sr_init.ys
873s Warning: Complex async reset for dff `\Q'.
873s Passed dfflibmap.ys
874s Passed dffunmap.ys
874s Passed extractinv.ys
874s Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:23)
874s Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:29)
874s Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:35)
874s Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:58)
874s Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:14)
874s Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:18)
874s Passed iopadmap.ys
874s Passed pmux2mux.ys
874s Passed shiftx2mux.ys
874s Passed techmap_replace.ys
874s Passed wireinit.ys
875s Passed zinit.ys
875s Passed mem_simple_4x1_runtest.sh
875s Passed recursive_runtest.sh
875s make[1]: Leaving directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/techmap'
875s cd tests/memories && bash run-test.sh "" ""
875s make[1]: Entering directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/memories'
877s Test: amber23_sram_byte_en -> ok
877s Test: firrtl_938 -> ok
878s Test: implicit_en -> ok
881s Test: issue00335 -> ok
883s Test: issue00710 -> ok
884s Test: no_implicit_en -> ok
885s Test: read_arst -> ok
887s Test: read_two_mux -> ok
888s Test: shared_ports -> ok
889s Test: simple_sram_byte_en -> ok
890s Test: trans_addr_enable -> ok
892s Test: trans_sdp -> ok
893s Test: trans_sp -> ok
895s Test: wide_all -> ok
896s Test: wide_read_async -> ok
898s Test: wide_read_mixed -> ok
899s Test: wide_read_sync -> ok
901s Test: wide_read_trans -> ok
902s Test: wide_thru_priority -> ok
903s Test: wide_write -> ok
903s make[1]: Leaving directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/memories'
904s Testing expectations for amber23_sram_byte_en.v .. ok.
904s Testing expectations for implicit_en.v .. ok.
904s Testing expectations for issue00335.v .. ok.
904s Testing expectations for issue00710.v .. ok.
904s Testing expectations for no_implicit_en.v .. ok.
904s Testing expectations for read_arst.v .. ok.
904s Testing expectations for read_two_mux.v .. ok.
904s Testing expectations for shared_ports.v .. ok.
904s Testing expectations for simple_sram_byte_en.v .. ok.
905s Testing expectations for trans_addr_enable.v .. ok.
905s Testing expectations for trans_sdp.v .. ok.
905s Testing expectations for trans_sp.v .. ok.
905s Testing expectations for wide_all.v .. ok.
905s Testing expectations for wide_read_async.v .. ok.
905s Testing expectations for wide_read_mixed.v .. ok.
905s Testing expectations for wide_read_sync.v .. ok.
905s Testing expectations for wide_read_trans.v .. ok.
905s Testing expectations for wide_thru_priority.v .. ok.
905s Testing expectations for wide_write.v .. ok.
905s cd tests/memlib && bash run-test.sh ""
906s make[1]: Entering directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/memlib'
908s Test: t_async_big -> ok
914s Test: t_async_big_block -> ok
914s Test: t_async_small -> ok
915s Test: t_async_small_block -> ok
915s Test: t_sync_big -> ok
916s Test: t_sync_big_sdp -> ok
918s Test: t_sync_big_lut -> ok
919s Test: t_sync_small -> ok
919s Test: t_sync_small_block -> ok
919s Test: t_sync_small_block_attr -> ok
919s Test: t_init_lut_zeros_zero -> ok
920s Test: t_init_lut_zeros_any -> ok
920s Test: t_init_lut_val_zero -> ok
920s Test: t_init_lut_val_any -> ok
920s Test: t_init_lut_val_no_undef -> ok
921s Test: t_init_lut_val2_any -> ok
921s Test: t_init_lut_val2_no_undef -> ok
921s Test: t_init_lut_x_none -> ok
922s Test: t_init_lut_x_zero -> ok
922s Test: t_init_lut_x_any -> ok
922s Test: t_init_lut_x_no_undef -> ok
922s Test: t_ram_18b2B -> ok
923s Test: t_ram_9b1B -> ok
923s Test: t_ram_4b1B -> ok
923s Test: t_ram_2b1B -> ok
923s Test: t_ram_1b1B -> ok
924s Test: t_init_9b1B_zeros_zero -> ok
924s Test: t_init_9b1B_zeros_any -> ok
924s Test: t_init_9b1B_val_zero -> ok
924s Test: t_init_9b1B_val_any -> ok
925s Test: t_init_9b1B_val_no_undef -> ok
925s Test: t_init_13b2B_val_any -> ok
925s Test: t_init_18b2B_val_any -> ok
926s Test: t_init_18b2B_val_no_undef -> ok
926s Test: t_init_4b1B_x_none -> ok
926s Test: t_init_4b1B_x_zero -> ok
926s Test: t_init_4b1B_x_any -> ok
927s Test: t_init_4b1B_x_no_undef -> ok
927s Test: t_clock_a4_wANYrANYsFalse -> ok
927s Test: t_clock_a4_wANYrNEGsFalse -> ok
927s Test: t_clock_a4_wANYrPOSsFalse -> ok
928s Test: t_clock_a4_wNEGrANYsFalse -> ok
928s Test: t_clock_a4_wNEGrPOSsFalse -> ok
928s Test: t_clock_a4_wNEGrNEGsFalse -> ok
928s Test: t_clock_a4_wPOSrANYsFalse -> ok
929s Test: t_clock_a4_wPOSrNEGsFalse -> ok
929s Test: t_clock_a4_wPOSrPOSsFalse -> ok
929s Test: t_clock_a4_wANYrANYsTrue -> ok
929s Test: t_clock_a4_wNEGrPOSsTrue -> ok
930s Test: t_clock_a4_wNEGrNEGsTrue -> ok
930s Test: t_clock_a4_wPOSrNEGsTrue -> ok
930s Test: t_clock_a4_wPOSrPOSsTrue -> ok
930s Test: t_unmixed -> ok
931s Test: t_mixed_9_18 -> ok
931s Test: t_mixed_18_9 -> ok
931s Test: t_mixed_36_9 -> ok
931s Test: t_mixed_4_2 -> ok
932s Test: t_tdp -> ok
932s Test: t_sync_2clk -> ok
932s Test: t_sync_shared -> ok
933s Test: t_sync_2clk_shared -> ok
933s Test: t_sync_trans_old_old -> ok
933s Test: t_sync_trans_old_new -> ok
933s Test: t_sync_trans_old_none -> ok
934s Test: t_sync_trans_new_old -> ok
934s Test: t_sync_trans_new_new -> ok
934s Test: t_sync_trans_new_none -> ok
934s Test: t_sp_nc_none -> ok
935s Test: t_sp_new_none -> ok
935s Test: t_sp_old_none -> ok
935s Test: t_sp_nc_nc -> ok
935s Test: t_sp_new_nc -> ok
936s Test: t_sp_old_nc -> ok
936s Test: t_sp_nc_new -> ok
936s Test: t_sp_new_new -> ok
936s Test: t_sp_old_new -> ok
937s Test: t_sp_nc_old -> ok
937s Test: t_sp_new_old -> ok
937s Test: t_sp_old_old -> ok
937s Test: t_sp_nc_new_only -> ok
937s Test: t_sp_new_new_only -> ok
938s Test: t_sp_old_new_only -> ok
938s Test: t_sp_nc_new_only_be -> ok
938s Test: t_sp_new_new_only_be -> ok
938s Test: t_sp_old_new_only_be -> ok
939s Test: t_sp_nc_new_be -> ok
939s Test: t_sp_new_new_be -> ok
939s Test: t_sp_old_new_be -> ok
940s Test: t_sp_nc_old_be -> ok
940s Test: t_sp_new_old_be -> ok
940s Test: t_sp_old_old_be -> ok
940s Test: t_sp_nc_nc_be -> ok
941s Test: t_sp_new_nc_be -> ok
941s Test: t_sp_old_nc_be -> ok
941s Test: t_sp_nc_auto -> ok
941s Test: t_sp_new_auto -> ok
942s Test: t_sp_old_auto -> ok
942s Test: t_sp_nc_auto_be -> ok
942s Test: t_sp_new_auto_be -> ok
942s Test: t_sp_old_auto_be -> ok
943s Test: t_sp_init_x_x -> ok
943s Test: t_sp_init_x_x_re -> ok
943s Test: t_sp_init_x_x_ce -> ok
943s Test: t_sp_init_0_x -> ok
944s Test: t_sp_init_0_x_re -> ok
944s Test: t_sp_init_0_0 -> ok
944s Test: t_sp_init_0_0_re -> ok
944s Test: t_sp_init_0_any -> ok
944s Test: t_sp_init_0_any_re -> ok
945s Test: t_sp_init_v_x -> ok
945s Test: t_sp_init_v_x_re -> ok
945s Test: t_sp_init_v_0 -> ok
945s Test: t_sp_init_v_0_re -> ok
946s Test: t_sp_init_v_any -> ok
946s Test: t_sp_init_v_any_re -> ok
946s Test: t_sp_arst_x_x -> ok
946s Test: t_sp_arst_x_x_re -> ok
947s Test: t_sp_arst_0_x -> ok
947s Test: t_sp_arst_0_x_re -> ok
947s Test: t_sp_arst_0_0 -> ok
947s Test: t_sp_arst_0_0_re -> ok
948s Test: t_sp_arst_0_any -> ok
948s Test: t_sp_arst_0_any_re -> ok
948s Test: t_sp_arst_0_init -> ok
948s Test: t_sp_arst_0_init_re -> ok
949s Test: t_sp_arst_v_x -> ok
949s Test: t_sp_arst_v_x_re -> ok
949s Test: t_sp_arst_v_0 -> ok
949s Test: t_sp_arst_v_0_re -> ok
950s Test: t_sp_arst_v_any -> ok
950s Test: t_sp_arst_v_any_re -> ok
950s Test: t_sp_arst_v_init -> ok
950s Test: t_sp_arst_v_init_re -> ok
951s Test: t_sp_arst_e_x -> ok
951s Test: t_sp_arst_e_x_re -> ok
951s Test: t_sp_arst_e_0 -> ok
951s Test: t_sp_arst_e_0_re -> ok
952s Test: t_sp_arst_e_any -> ok
952s Test: t_sp_arst_e_any_re -> ok
952s Test: t_sp_arst_e_init -> ok
952s Test: t_sp_arst_e_init_re -> ok
953s Test: t_sp_arst_n_x -> ok
953s Test: t_sp_arst_n_x_re -> ok
953s Test: t_sp_arst_n_0 -> ok
953s Test: t_sp_arst_n_0_re -> ok
954s Test: t_sp_arst_n_any -> ok
954s Test: t_sp_arst_n_any_re -> ok
954s Test: t_sp_arst_n_init -> ok
954s Test: t_sp_arst_n_init_re -> ok
955s Test: t_sp_srst_x_x -> ok
955s Test: t_sp_srst_x_x_re -> ok
955s Test: t_sp_srst_0_x -> ok
956s Test: t_sp_srst_0_x_re -> ok
956s Test: t_sp_srst_0_0 -> ok
956s Test: t_sp_srst_0_0_re -> ok
956s Test: t_sp_srst_0_any -> ok
957s Test: t_sp_srst_0_any_re -> ok
957s Test: t_sp_srst_0_init -> ok
957s Test: t_sp_srst_0_init_re -> ok
957s Test: t_sp_srst_v_x -> ok
958s Test: t_sp_srst_v_x_re -> ok
958s Test: t_sp_srst_v_0 -> ok
958s Test: t_sp_srst_v_0_re -> ok
959s Test: t_sp_srst_v_any -> ok
959s Test: t_sp_srst_v_any_re -> ok
959s Test: t_sp_srst_v_any_re_gated -> ok
959s Test: t_sp_srst_v_any_ce -> ok
960s Test: t_sp_srst_v_any_ce_gated -> ok
960s Test: t_sp_srst_v_init -> ok
960s Test: t_sp_srst_v_init_re -> ok
960s Test: t_sp_srst_e_x -> ok
961s Test: t_sp_srst_e_x_re -> ok
961s Test: t_sp_srst_e_0 -> ok
961s Test: t_sp_srst_e_0_re -> ok
961s Test: t_sp_srst_e_any -> ok
962s Test: t_sp_srst_e_any_re -> ok
962s Test: t_sp_srst_e_init -> ok
962s Test: t_sp_srst_e_init_re -> ok
962s Test: t_sp_srst_n_x -> ok
963s Test: t_sp_srst_n_x_re -> ok
963s Test: t_sp_srst_n_0 -> ok
963s Test: t_sp_srst_n_0_re -> ok
963s Test: t_sp_srst_n_any -> ok
964s Test: t_sp_srst_n_any_re -> ok
964s Test: t_sp_srst_n_init -> ok
964s Test: t_sp_srst_n_init_re -> ok
964s Test: t_sp_srst_gv_x -> ok
965s Test: t_sp_srst_gv_x_re -> ok
965s Test: t_sp_srst_gv_0 -> ok
965s Test: t_sp_srst_gv_0_re -> ok
966s Test: t_sp_srst_gv_any -> ok
966s Test: t_sp_srst_gv_any_re -> ok
966s Test: t_sp_srst_gv_any_re_gated -> ok
966s Test: t_sp_srst_gv_any_ce -> ok
967s Test: t_sp_srst_gv_any_ce_gated -> ok
967s Test: t_sp_srst_gv_init -> ok
967s Test: t_sp_srst_gv_init_re -> ok
967s Test: t_wren_a4d4_NO_BYTE -> ok
968s Test: t_wren_a5d4_NO_BYTE -> ok
968s Test: t_wren_a6d4_NO_BYTE -> ok
968s Test: t_wren_a3d8_NO_BYTE -> ok
968s Test: t_wren_a4d8_NO_BYTE -> ok
969s Test: t_wren_a4d4_W4_B4 -> ok
969s Test: t_wren_a4d8_W4_B4_separate -> ok
969s Test: t_wren_a4d8_W8_B4 -> ok
969s Test: t_wren_a4d8_W8_B4_separate -> ok
970s Test: t_wren_a4d8_W8_B8 -> ok
970s Test: t_wren_a4d8_W8_B8_separate -> ok
970s Test: t_wren_a4d2w8_W16_B4 -> ok
970s Test: t_wren_a4d2w8_W16_B4_separate -> ok
971s Test: t_wren_a4d4w4_W16_B4 -> ok
971s Test: t_wren_a4d4w4_W16_B4_separate -> ok
971s Test: t_wren_a5d4w2_W16_B4 -> ok
971s Test: t_wren_a5d4w2_W16_B4_separate -> ok
972s Test: t_wren_a5d4w4_W16_B4 -> ok
972s Test: t_wren_a5d4w4_W16_B4_separate -> ok
972s Test: t_wren_a4d8w2_W16_B4 -> ok
973s Test: t_wren_a4d8w2_W16_B4_separate -> ok
973s Test: t_wren_a5d8w1_W16_B4 -> ok
973s Test: t_wren_a5d8w1_W16_B4_separate -> ok
973s Test: t_wren_a5d8w2_W16_B4 -> ok
974s Test: t_wren_a5d8w2_W16_B4_separate -> ok
974s Test: t_wren_a4d16w1_W16_B4 -> ok
974s Test: t_wren_a4d16w1_W16_B4_separate -> ok
975s Test: t_wren_a4d4w2_W8_B8 -> ok
975s Test: t_wren_a4d4w2_W8_B8_separate -> ok
975s Test: t_wren_a4d4w1_W8_B8 -> ok
975s Test: t_wren_a4d4w1_W8_B8_separate -> ok
976s Test: t_wren_a4d8w2_W8_B8 -> ok
976s Test: t_wren_a4d8w2_W8_B8_separate -> ok
976s Test: t_wren_a3d8w2_W8_B8 -> ok
976s Test: t_wren_a3d8w2_W8_B8_separate -> ok
977s Test: t_wren_a4d4w2_W8_B4 -> ok
977s Test: t_wren_a4d4w2_W8_B4_separate -> ok
977s Test: t_wren_a4d2w4_W8_B4 -> ok
977s Test: t_wren_a4d2w4_W8_B4_separate -> ok
978s Test: t_wren_a4d4w4_W8_B4 -> ok
978s Test: t_wren_a4d4w4_W8_B4_separate -> ok
978s Test: t_wren_a4d4w4_W4_B4 -> ok
979s Test: t_wren_a4d4w4_W4_B4_separate -> ok
979s Test: t_wren_a4d4w5_W4_B4 -> ok
979s Test: t_wren_a4d4w5_W4_B4_separate -> ok
979s Test: t_geom_a4d64_wren -> ok
980s Test: t_geom_a5d32_wren -> ok
980s Test: t_geom_a5d64_wren -> ok
980s Test: t_geom_a6d16_wren -> ok
981s Test: t_geom_a6d30_wren -> ok
981s Test: t_geom_a6d64_wren -> ok
981s Test: t_geom_a7d4_wren -> ok
981s Test: t_geom_a7d6_wren -> ok
982s Test: t_geom_a7d8_wren -> ok
982s Test: t_geom_a7d17_wren -> ok
982s Test: t_geom_a8d4_wren -> ok
983s Test: t_geom_a8d6_wren -> ok
983s Test: t_geom_a9d4_wren -> ok
984s Test: t_geom_a9d8_wren -> ok
984s Test: t_geom_a9d5_wren -> ok
984s Test: t_geom_a9d6_wren -> ok
985s Test: t_geom_a3d18_9b1B -> ok
985s Test: t_geom_a4d4_9b1B -> ok
985s Test: t_geom_a4d18_9b1B -> ok
985s Test: t_geom_a5d32_9b1B -> ok
986s Test: t_geom_a6d4_9b1B -> ok
986s Test: t_geom_a7d11_9b1B -> ok
986s Test: t_geom_a7d18_9b1B -> ok
987s Test: t_geom_a11d1_9b1B -> ok
987s Test: t_wide_sdp_a6r1w1b1x1 -> ok
987s Test: t_wide_sdp_a7r1w1b1x1 -> ok
988s Test: t_wide_sdp_a8r1w1b1x1 -> ok
988s Test: t_wide_sdp_a6r0w0b0x0 -> ok
988s Test: t_wide_sdp_a6r1w0b0x0 -> ok
989s Test: t_wide_sdp_a6r2w0b0x0 -> ok
989s Test: t_wide_sdp_a6r3w0b0x0 -> ok
989s Test: t_wide_sdp_a6r4w0b0x0 -> ok
990s Test: t_wide_sdp_a6r5w0b0x0 -> ok
990s Test: t_wide_sdp_a6r0w1b0x0 -> ok
990s Test: t_wide_sdp_a6r0w1b1x0 -> ok
991s Test: t_wide_sdp_a6r0w2b0x0 -> ok
991s Test: t_wide_sdp_a6r0w2b2x0 -> ok
991s Test: t_wide_sdp_a6r0w3b2x0 -> ok
992s Test: t_wide_sdp_a6r0w4b2x0 -> ok
992s Test: t_wide_sdp_a6r0w5b2x0 -> ok
993s Test: t_wide_sdp_a7r0w0b0x0 -> ok
993s Test: t_wide_sdp_a7r1w0b0x0 -> ok
993s Test: t_wide_sdp_a7r2w0b0x0 -> ok
994s Test: t_wide_sdp_a7r3w0b0x0 -> ok
994s Test: t_wide_sdp_a7r4w0b0x0 -> ok
994s Test: t_wide_sdp_a7r5w0b0x0 -> ok
995s Test: t_wide_sdp_a7r0w1b0x0 -> ok
995s Test: t_wide_sdp_a7r0w1b1x0 -> ok
995s Test: t_wide_sdp_a7r0w2b0x0 -> ok
996s Test: t_wide_sdp_a7r0w2b2x0 -> ok
996s Test: t_wide_sdp_a7r0w3b2x0 -> ok
996s Test: t_wide_sdp_a7r0w4b2x0 -> ok
997s Test: t_wide_sdp_a7r0w5b2x0 -> ok
997s Test: t_wide_sp_mix_a6r1w1b1 -> ok
997s Test: t_wide_sp_mix_a7r1w1b1 -> ok
998s Test: t_wide_sp_mix_a8r1w1b1 -> ok
998s Test: t_wide_sp_mix_a6r0w0b0 -> ok
998s Test: t_wide_sp_mix_a6r1w0b0 -> ok
998s Test: t_wide_sp_mix_a6r2w0b0 -> ok
999s Test: t_wide_sp_mix_a6r3w0b0 -> ok
999s Test: t_wide_sp_mix_a6r4w0b0 -> ok
999s Test: t_wide_sp_mix_a6r5w0b0 -> ok
1000s Test: t_wide_sp_mix_a6r0w1b0 -> ok
1000s Test: t_wide_sp_mix_a6r0w1b1 -> ok
1000s Test: t_wide_sp_mix_a6r0w2b0 -> ok
1000s Test: t_wide_sp_mix_a6r0w2b2 -> ok
1001s Test: t_wide_sp_mix_a6r0w3b2 -> ok
1001s Test: t_wide_sp_mix_a6r0w4b2 -> ok
1002s Test: t_wide_sp_mix_a6r0w5b2 -> ok
1002s Test: t_wide_sp_mix_a7r0w0b0 -> ok
1002s Test: t_wide_sp_mix_a7r1w0b0 -> ok
1002s Test: t_wide_sp_mix_a7r2w0b0 -> ok
1003s Test: t_wide_sp_mix_a7r3w0b0 -> ok
1003s Test: t_wide_sp_mix_a7r4w0b0 -> ok
1003s Test: t_wide_sp_mix_a7r5w0b0 -> ok
1004s Test: t_wide_sp_mix_a7r0w1b0 -> ok
1004s Test: t_wide_sp_mix_a7r0w1b1 -> ok
1004s Test: t_wide_sp_mix_a7r0w2b0 -> ok
1005s Test: t_wide_sp_mix_a7r0w2b2 -> ok
1005s Test: t_wide_sp_mix_a7r0w3b2 -> ok
1005s Test: t_wide_sp_mix_a7r0w4b2 -> ok
1006s Test: t_wide_sp_mix_a7r0w5b2 -> ok
1006s Test: t_wide_sp_tied_a6r1w1b1 -> ok
1006s Test: t_wide_sp_tied_a7r1w1b1 -> ok
1007s Test: t_wide_sp_tied_a8r1w1b1 -> ok
1007s Test: t_wide_sp_tied_a6r0w0b0 -> ok
1007s Test: t_wide_sp_tied_a6r1w0b0 -> ok
1007s Test: t_wide_sp_tied_a6r2w0b0 -> ok
1008s Test: t_wide_sp_tied_a6r3w0b0 -> ok
1008s Test: t_wide_sp_tied_a6r4w0b0 -> ok
1009s Test: t_wide_sp_tied_a6r5w0b0 -> ok
1009s Test: t_wide_sp_tied_a6r0w1b0 -> ok
1009s Test: t_wide_sp_tied_a6r0w1b1 -> ok
1009s Test: t_wide_sp_tied_a6r0w2b0 -> ok
1010s Test: t_wide_sp_tied_a6r0w2b2 -> ok
1010s Test: t_wide_sp_tied_a6r0w3b2 -> ok
1010s Test: t_wide_sp_tied_a6r0w4b2 -> ok
1011s Test: t_wide_sp_tied_a6r0w5b2 -> ok
1011s Test: t_wide_sp_tied_a7r0w0b0 -> ok
1012s Test: t_wide_sp_tied_a7r1w0b0 -> ok
1012s Test: t_wide_sp_tied_a7r2w0b0 -> ok
1012s Test: t_wide_sp_tied_a7r3w0b0 -> ok
1013s Test: t_wide_sp_tied_a7r4w0b0 -> ok
1013s Test: t_wide_sp_tied_a7r5w0b0 -> ok
1013s Test: t_wide_sp_tied_a7r0w1b0 -> ok
1014s Test: t_wide_sp_tied_a7r0w1b1 -> ok
1014s Test: t_wide_sp_tied_a7r0w2b0 -> ok
1014s Test: t_wide_sp_tied_a7r0w2b2 -> ok
1014s Test: t_wide_sp_tied_a7r0w3b2 -> ok
1015s Test: t_wide_sp_tied_a7r0w4b2 -> ok
1015s Test: t_wide_sp_tied_a7r0w5b2 -> ok
1016s Test: t_wide_read_a6r1w1b1 -> ok
1016s Test: t_wide_write_a6r1w1b1 -> ok
1017s Test: t_wide_read_a7r1w1b1 -> ok
1017s Test: t_wide_write_a7r1w1b1 -> ok
1017s Test: t_wide_read_a8r1w1b1 -> ok
1017s Test: t_wide_write_a8r1w1b1 -> ok
1017s Test: t_wide_read_a6r0w0b0 -> ok
1018s Test: t_wide_write_a6r0w0b0 -> ok
1018s Test: t_wide_read_a6r1w0b0 -> ok
1018s Test: t_wide_write_a6r1w0b0 -> ok
1018s Test: t_wide_read_a6r2w0b0 -> ok
1019s Test: t_wide_write_a6r2w0b0 -> ok
1019s Test: t_wide_read_a6r3w0b0 -> ok
1019s Test: t_wide_write_a6r3w0b0 -> ok
1020s Test: t_wide_read_a6r4w0b0 -> ok
1020s Test: t_wide_write_a6r4w0b0 -> ok
1020s Test: t_wide_read_a6r5w0b0 -> ok
1021s Test: t_wide_write_a6r5w0b0 -> ok
1021s Test: t_wide_read_a6r0w1b0 -> ok
1022s Test: t_wide_write_a6r0w1b0 -> ok
1022s Test: t_wide_read_a6r0w1b1 -> ok
1022s Test: t_wide_write_a6r0w1b1 -> ok
1023s Test: t_wide_read_a6r0w2b0 -> ok
1023s Test: t_wide_write_a6r0w2b0 -> ok
1023s Test: t_wide_read_a6r0w2b2 -> ok
1023s Test: t_wide_write_a6r0w2b2 -> ok
1024s Test: t_wide_read_a6r0w3b2 -> ok
1024s Test: t_wide_write_a6r0w3b2 -> ok
1024s Test: t_wide_read_a6r0w4b2 -> ok
1025s Test: t_wide_write_a6r0w4b2 -> ok
1025s Test: t_wide_read_a6r0w5b2 -> ok
1026s Test: t_wide_write_a6r0w5b2 -> ok
1026s Test: t_wide_read_a7r0w0b0 -> ok
1026s Test: t_wide_write_a7r0w0b0 -> ok
1027s Test: t_wide_read_a7r1w0b0 -> ok
1027s Test: t_wide_write_a7r1w0b0 -> ok
1027s Test: t_wide_read_a7r2w0b0 -> ok
1027s Test: t_wide_write_a7r2w0b0 -> ok
1028s Test: t_wide_read_a7r3w0b0 -> ok
1028s Test: t_wide_write_a7r3w0b0 -> ok
1028s Test: t_wide_read_a7r4w0b0 -> ok
1029s Test: t_wide_write_a7r4w0b0 -> ok
1029s Test: t_wide_read_a7r5w0b0 -> ok
1030s Test: t_wide_write_a7r5w0b0 -> ok
1030s Test: t_wide_read_a7r0w1b0 -> ok
1030s Test: t_wide_write_a7r0w1b0 -> ok
1031s Test: t_wide_read_a7r0w1b1 -> ok
1031s Test: t_wide_write_a7r0w1b1 -> ok
1031s Test: t_wide_read_a7r0w2b0 -> ok
1031s Test: t_wide_write_a7r0w2b0 -> ok
1032s Test: t_wide_read_a7r0w2b2 -> ok
1032s Test: t_wide_write_a7r0w2b2 -> ok
1032s Test: t_wide_read_a7r0w3b2 -> ok
1033s Test: t_wide_write_a7r0w3b2 -> ok
1033s Test: t_wide_read_a7r0w4b2 -> ok
1033s Test: t_wide_write_a7r0w4b2 -> ok
1034s Test: t_wide_read_a7r0w5b2 -> ok
1034s Test: t_wide_write_a7r0w5b2 -> ok
1035s Test: t_quad_port_a2d2 -> ok
1035s Test: t_quad_port_a4d2 -> ok
1035s Test: t_quad_port_a5d2 -> ok
1035s Test: t_quad_port_a4d4 -> ok
1036s Test: t_quad_port_a6d2 -> ok
1036s Test: t_quad_port_a4d8 -> ok
1036s Test: t_wide_quad_a4w2r1 -> ok
1036s Test: t_wide_oct_a4w2r1 -> ok
1037s Test: t_wide_quad_a4w2r2 -> ok
1037s Test: t_wide_oct_a4w2r2 -> ok
1037s Test: t_wide_quad_a4w2r3 -> ok
1037s Test: t_wide_oct_a4w2r3 -> ok
1038s Test: t_wide_quad_a4w2r4 -> ok
1038s Test: t_wide_oct_a4w2r4 -> ok
1038s Test: t_wide_quad_a4w2r5 -> ok
1038s Test: t_wide_oct_a4w2r5 -> ok
1039s Test: t_wide_quad_a4w2r6 -> ok
1039s Test: t_wide_oct_a4w2r6 -> ok
1039s Test: t_wide_quad_a4w2r7 -> ok
1039s Test: t_wide_oct_a4w2r7 -> ok
1040s Test: t_wide_quad_a4w2r8 -> ok
1040s Test: t_wide_oct_a4w2r8 -> ok
1040s Test: t_wide_quad_a4w2r9 -> ok
1041s Test: t_wide_oct_a4w2r9 -> ok
1041s Test: t_wide_quad_a4w4r1 -> ok
1041s Test: t_wide_oct_a4w4r1 -> ok
1041s Test: t_wide_quad_a4w4r4 -> ok
1042s Test: t_wide_oct_a4w4r4 -> ok
1042s Test: t_wide_quad_a4w4r6 -> ok
1042s Test: t_wide_oct_a4w4r6 -> ok
1042s Test: t_wide_quad_a4w4r9 -> ok
1043s Test: t_wide_oct_a4w4r9 -> ok
1043s Test: t_wide_quad_a5w2r1 -> ok
1043s Test: t_wide_oct_a5w2r1 -> ok
1043s Test: t_wide_quad_a5w2r4 -> ok
1044s Test: t_wide_oct_a5w2r4 -> ok
1044s Test: t_wide_quad_a5w2r9 -> ok
1044s Test: t_wide_oct_a5w2r9 -> ok
1045s Test: t_no_reset -> ok
1045s Test: t_gclken -> ok
1045s Test: t_ungated -> ok
1046s Test: t_gclken_ce -> ok
1046s Test: t_grden -> ok
1046s Test: t_grden_ce -> ok
1046s Test: t_exclwr -> ok
1047s Test: t_excl_rst -> ok
1047s Test: t_transwr -> ok
1047s Test: t_trans_rst -> ok
1048s Test: t_wr_byte -> ok
1048s Test: t_trans_byte -> ok
1048s Test: t_wr_rst_byte -> ok
1048s Test: t_rst_wr_byte -> ok
1049s Test: t_rdenrst_wr_byte -> ok
1049s make[1]: Leaving directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/memlib'
1049s cd tests/bram && bash run-test.sh ""
1049s generating tests..
1049s PRNG seed: 988586
1049s running tests..
1049s make[1]: Entering directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/bram'
1050s Passed memory_bram test 00_01.
1051s Passed memory_bram test 00_02.
1052s Passed memory_bram test 00_03.
1054s Passed memory_bram test 00_04.
1055s Passed memory_bram test 01_00.
1056s Passed memory_bram test 01_02.
1058s Passed memory_bram test 01_03.
1061s Passed memory_bram test 01_04.
1061s Passed memory_bram test 02_00.
1062s Passed memory_bram test 02_01.
1064s Passed memory_bram test 02_03.
1065s Passed memory_bram test 02_04.
1066s Passed memory_bram test 03_00.
1066s Passed memory_bram test 03_01.
1067s Passed memory_bram test 03_02.
1068s Passed memory_bram test 03_04.
1069s Passed memory_bram test 04_00.
1070s Passed memory_bram test 04_01.
1071s Passed memory_bram test 04_02.
1072s Passed memory_bram test 04_03.
1074s make[1]: Leaving directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/bram'
1074s cd tests/various && bash run-test.sh
1074s make[1]: Entering directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/various'
1074s Warning: Wire abc9_test027.$abc$91$o is used but has no driver.
1074s Passed abc9.ys
1074s Passed aiger_dff.ys
1074s Passed attrib05_port_conn.ys
1074s Passed attrib07_func_call.ys
1074s Passed autoname.ys
1074s Passed blackbox_wb.ys
1074s Passed bug1496.ys
1074s Passed bug1531.ys
1074s Passed bug1614.ys
1074s Passed bug1710.ys
1074s Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:3)
1074s <<EOT:3: ERROR: syntax error, unexpected TOK_CONSTVAL
1074s Expected error pattern 'syntax error, unexpected TOK_CONSTVAL' found !!!
1074s Passed bug1745.ys
1074s Passed bug1781.ys
1074s Passed bug1876.ys
1074s Passed bug2014.ys
1074s Passed bug3462.ys
1074s Passed cellarray_array_connections.ys
1074s Passed chformal_coverenable.ys
1074s Passed const_arg_loop.ys
1074s Passed const_func.ys
1074s Passed const_func_block_var.ys
1074s Warning: Drivers conflicting with a constant 1'1 driver:
1074s     module input A[0]
1074s Warning: Drivers conflicting with a constant 1'1 driver:
1074s     port Y[0] of cell some_buffer (buffer)
1074s Warning: reg '\Q' is assigned in a continuous assignment at <<EOT:5.9-5.14.
1074s Warning: Drivers conflicting with a constant 1'1 driver:
1074s     action \Q <= $0\Q[0:0] (sync rule) in process $proc$<<EOT:3$1
1074s Passed constant_drive_conflict.ys
1074s <<EOT:2: ERROR: syntax error, unexpected TOK_BASE
1074s Expected error pattern 'syntax error, unexpected TOK_BASE' found !!!
1074s Passed constcomment.ys
1074s Passed constmsk_test.ys
1074s Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:3)
1074s Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:4)
1074s Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:5)
1074s Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:6)
1074s Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:7)
1074s Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:8)
1074s Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:9)
1074s Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:10)
1074s Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:11)
1074s Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:12)
1074s Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:13)
1074s Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:14)
1074s Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:15)
1074s Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:52)
1074s Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:53)
1074s Passed countbits.ys
1074s Passed deminout_unused.ys
1074s Passed design.ys
1074s ERROR: No saved design 'foo' found!
1074s Expected error pattern 'No saved design 'foo' found!' found !!!
1074s Passed design1.ys
1074s ERROR: No saved design 'foo' found!
1074s Expected error pattern 'No saved design 'foo' found!' found !!!
1074s Passed design2.ys
1158s Passed dynamic_part_select.ys
1158s elab_sys_tasks.sv:8: Warning: X is 1.
1158s elab_sys_tasks.sv:22: Warning: 
1158s Warning: Yosys has only limited support for tri-state logic at the moment. (/usr/bin/../share/yosys/simcells.v:456)
1158s Passed elab_sys_tasks.ys
1158s Passed equiv_make_make_assert.ys
1158s Passed equiv_opt_multiclock.ys
1158s Passed equiv_opt_undef.ys
1158s Passed exec.ys
1158s ERROR: Command stdout did have a line matching given regex "giraffe".
1158s Expected error pattern 'stdout did have a line' found !!!
1159s Passed fib.ys
1159s Passed fib_tern.ys
1159s Passed func_port_implied_dir.ys
1159s Passed gen_if_null.ys
1159s Passed global_scope.ys
1159s Passed gzip_verilog.ys
1159s Passed help.ys
1159s Passed hierarchy_defer.ys
1159s Passed hierarchy_param.ys
1160s Passed ice40_mince_abc9.ys
1160s <<EOT:2: ERROR: syntax error, unexpected '[', expecting TOK_ID or TOK_SIGNED or TOK_UNSIGNED
1160s Expected error pattern 'syntax error, unexpected' found !!!
1160s Passed integer_range_bad_syntax.ys
1160s <<EOT:2: ERROR: syntax error, unexpected TOK_REAL, expecting TOK_ID or TOK_SIGNED or TOK_UNSIGNED
1160s Expected error pattern 'syntax error, unexpected TOK_REAL' found !!!
1160s Passed integer_real_bad_syntax.ys
1160s attribute \src "\" / \\ \010 \014 \n \015 \t \025 \033"
1160s Passed json_escape_chars.ys
1160s ERROR: Identifier `\b' is implicitly declared.
1160s Expected error pattern 'is implicitly declared.' found !!!
1160s Passed logger_error.ys
1160s Passed logger_nowarning.ys
1160s Warning: Found log message matching -W regex:
1160s Added regex 'Successfully finished Verilog frontend.' for warnings to expected warning list.
1160s <<EOF:2: Warning: Identifier `\b' is implicitly declared.
1160s <<EOF:2: Warning: Identifier `\w' is implicitly declared.
1160s Warning: Found log message matching -W regex:
1160s Successfully finished Verilog frontend.
1160s Passed logger_warn.ys
1160s Passed logger_warning.ys
1160s <<EOF:2: Warning: Identifier `\b' is implicitly declared.
1160s <<EOF:2: Warning: Identifier `\w' is implicitly declared.
1160s Passed logic_param_simple.ys
1160s Passed mem2reg.ys
1160s Passed memory_word_as_index.ys
1160s Warning: Yosys has only limited support for tri-state logic at the moment. (/usr/bin/../share/yosys/simcells.v:456)
1162s Passed muxcover.ys
1162s Passed muxpack.ys
1162s Passed param_struct.ys
1163s Passed peepopt.ys
1172s Passed pmgen_reduce.ys
1172s Passed pmux2shiftx.ys
1172s Warning: Resizing cell port act.ou2.out from 3 bits to 2 bits.
1172s Warning: Resizing cell port act.os2.out from 3 bits to 2 bits.
1172s Warning: Resizing cell port act.ou1.out from 3 bits to 1 bits.
1172s Warning: Resizing cell port act.os1.out from 3 bits to 1 bits.
1172s Warning: Resizing cell port act.pt9.a from 3 bits to 4 bits.
1172s Warning: Resizing cell port act.pt7.a from 3 bits to 4 bits.
1172s Warning: Resizing cell port act.pt6.a from 3 bits to 4 bits.
1172s Warning: Resizing cell port act.pt5.a from 2 bits to 4 bits.
1172s Warning: Resizing cell port act.pt4.a from 1 bits to 4 bits.
1172s Warning: Resizing cell port act.pt3.a from 1 bits to 4 bits.
1172s Warning: Resizing cell port act.pt2.a from 1 bits to 4 bits.
1172s Passed port_sign_extend.ys
1172s Passed primitives.ys
1172s Passed printattr.ys
1172s Passed rand_const.ys
1172s Warning: wire '\o_reg' is assigned in a block at reg_wire_error.sv:26.9-26.21.
1172s Warning: wire '\o_reg' is assigned in a block at reg_wire_error.sv:29.3-29.18.
1172s Warning: reg '\l_reg' is assigned in a continuous assignment at reg_wire_error.sv:35.8-35.22.
1172s Warning: wire '\mw2' is assigned in a block at reg_wire_error.sv:62.3-62.16.
1172s Warning: wire '\mw3' is assigned in a block at reg_wire_error.sv:69.3-69.17.
1172s Warning: Replacing memory \ml3 with list of registers. See reg_wire_error.sv:70
1172s Warning: Replacing memory \mr3 with list of registers. See reg_wire_error.sv:68
1172s Warning: Replacing memory \ml2 with list of registers. See reg_wire_error.sv:63
1172s Warning: Replacing memory \mr2 with list of registers. See reg_wire_error.sv:61
1172s Warning: Replacing memory \ml1 with list of registers. See reg_wire_error.sv:58
1172s Passed reg_wire_error.ys
1172s Passed rename_scramble_name.ys
1172s Passed rtlil_z_bits.ys
1172s Passed scratchpad.ys
1172s Passed script.ys
1172s Passed sformatf.ys
1172s Passed shregmap.ys
1172s <<EOT:2: ERROR: syntax error, unexpected TOK_INTEGER, expecting TOK_ID or '['
1172s Expected error pattern 'syntax error, unexpected TOK_INTEGER' found !!!
1172s Passed signed.ys
1172s Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:4)
1172s Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:5)
1172s Passed signext.ys
1172s Passed sim_const.ys
1172s specify.v:28: Warning: Replacing floating point parameter $specify$5.T_RISE_MIN = 1.500000 with string.
1172s specify.v:28: Warning: Replacing floating point parameter $specify$5.T_RISE_TYP = 1.500000 with string.
1172s specify.v:28: Warning: Replacing floating point parameter $specify$5.T_RISE_MAX = 1.500000 with string.
1172s specify.v:28: Warning: Replacing floating point parameter $specify$5.T_FALL_MIN = 1.500000 with string.
1172s specify.v:28: Warning: Replacing floating point parameter $specify$5.T_FALL_TYP = 1.500000 with string.
1172s specify.v:28: Warning: Replacing floating point parameter $specify$5.T_FALL_MAX = 1.500000 with string.
1172s specify.out:49: Warning: Replacing floating point parameter $specify$24.T_RISE_MIN = 1.500000 with string.
1172s specify.out:49: Warning: Replacing floating point parameter $specify$24.T_RISE_TYP = 1.500000 with string.
1172s specify.out:49: Warning: Replacing floating point parameter $specify$24.T_RISE_MAX = 1.500000 with string.
1172s specify.out:49: Warning: Replacing floating point parameter $specify$24.T_FALL_MIN = 1.500000 with string.
1172s specify.out:49: Warning: Replacing floating point parameter $specify$24.T_FALL_TYP = 1.500000 with string.
1172s specify.out:49: Warning: Replacing floating point parameter $specify$24.T_FALL_MAX = 1.500000 with string.
1173s Warning: No SAT model available for cell B_0 ($specrule).
1173s Warning: No SAT model available for cell C_0 ($specrule).
1173s Warning: No SAT model available for cell A_0 ($specify3).
1173s Warning: No SAT model available for cell A_0 ($specify2).
1173s Warning: No SAT model available for cell B_0 ($specify2).
1173s Passed specify.ys
1173s Warning: wire '\o' is assigned in a block at <<EOT:2.11-2.17.
1173s Warning: wire '\p' is assigned in a block at <<EOT:3.11-3.16.
1173s Passed src.ys
1173s Warning: Critical-path does not terminate in a recognised endpoint.
1173s Warning: Cell type 'const0' not recognised! Ignoring.
1173s Passed sta.ys
1173s Passed struct_access.ys
1173s Warning: Port directions for cell \s1 (\DFF) are unknown. Assuming inout for all ports.
1173s Warning: Port directions for cell \s2 (\DFF) are unknown. Assuming inout for all ports.
1173s Warning: Port directions for cell \s3 (\DFF) are unknown. Assuming inout for all ports.
1173s Passed submod.ys
1173s Passed submod_extract.ys
1173s Passed sv_defines.ys
1173s ERROR: Duplicate macro arguments with name `x'.
1173s Expected error pattern 'Duplicate macro arguments with name `x'' found !!!
1173s Passed sv_defines_dup.ys
1173s ERROR: Mismatched brackets in macro argument: [ and }.
1173s Expected error pattern 'Mismatched brackets in macro argument: \[ and }.' found !!!
1173s Passed sv_defines_mismatch.ys
1173s ERROR: Cannot expand macro `foo by giving only 1 argument (argument 2 has no default).
1173s Expected error pattern 'Cannot expand macro `foo by giving only 1 argument \(argument 2 has no default\).' found !!!
1173s Passed sv_defines_too_few.ys
1173s Passed wreduce.ys
1173s Passed write_gzip.ys
1173s Passed xaiger.ys
1173s Passed async.sh
1173s Passed chparam.sh
1173s Passed hierarchy.sh
1173s Passed logger_fail.sh
1176s Passed plugin.sh
1176s Passed smtlib2_module.sh
1176s Passed sv_implicit_ports.sh
1176s Passed svalways.sh
1176s make[1]: Leaving directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/various'
1176s cd tests/select && bash run-test.sh
1176s Running blackboxes.ys..
1176s Running no_warn_assert.ys..
1176s Running no_warn_prefixed_arg_memb.ys..
1176s Running no_warn_prefixed_empty_select_arg.ys..
1176s Running unset.ys..
1176s Running unset2.ys..
1176s ERROR: Selection '\foo' does not exist!
1176s Expected error pattern 'Selection '\\foo' does not exist!' found !!!
1176s Running warn_empty_select_arg.ys..
1176s ERROR: Selection @foo is not defined!
1176s Expected error pattern 'Selection @foo is not defined!' found !!!
1176s Warning: Selection "foo" did not match any module.
1176s Warning: Selection "bar" did not match any object.
1176s cd tests/sat && bash run-test.sh
1176s make[1]: Entering directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/sat'
1176s Passed asserts.ys
1176s Passed asserts_seq.ys
1176s Passed bug2595.ys
1176s Warning: Complex async reset for dff `\q [12]'.
1176s Warning: Complex async reset for dff `\q [8]'.
1191s Passed clk2fflogic.ys
1192s Passed counters-repeat.ys
1192s Passed counters.ys
1192s Passed dff.ys
1192s Passed expose_dff.ys
1193s Passed grom.ys
1193s Passed initval.ys
1196s Passed share.ys
1196s Warning: Wire top.\cnt [7] is used but has no driver.
1196s Warning: Wire top.\cnt [6] is used but has no driver.
1196s Warning: Wire top.\cnt [5] is used but has no driver.
1196s Warning: Wire top.\cnt [4] is used but has no driver.
1196s Warning: Wire top.\cnt [3] is used but has no driver.
1196s Warning: Wire top.\cnt [2] is used but has no driver.
1196s Warning: Wire top.\cnt [1] is used but has no driver.
1196s Warning: Wire top.\cnt [0] is used but has no driver.
1196s Warning: Signal 'top.cnt' in file 8'x in simulation '8'00000000'
1196s ERROR: Signal difference
1196s Expected error pattern 'Signal difference' found !!!
1196s Passed sim_counter.ys
1196s Passed sizebits.ys
1196s Passed splice.ys
1196s make[1]: Leaving directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/sat'
1196s cd tests/sim && bash run-test.sh
1196s Generate FST for sim models
1196s Test tb_adff
1196s FST info: dumpfile tb_adff.fst opened for output.
1196s tb/tb_adff.v:38: $finish called at 110 (1ns)
1196s Test tb_adffe
1196s FST info: dumpfile tb_adffe.fst opened for output.
1196s tb/tb_adffe.v:56: $finish called at 190 (1ns)
1196s Test tb_adlatch
1196s FST info: dumpfile tb_adlatch.fst opened for output.
1196s tb/tb_adlatch.v:68: $finish called at 250 (1ns)
1196s Test tb_aldff
1196s FST info: dumpfile tb_aldff.fst opened for output.
1196s tb/tb_aldff.v:71: $finish called at 270 (1ns)
1196s Test tb_aldffe
1196s FST info: dumpfile tb_aldffe.fst opened for output.
1196s tb/tb_aldffe.v:73: $finish called at 270 (1ns)
1196s Test tb_dff
1196s FST info: dumpfile tb_dff.fst opened for output.
1196s tb/tb_dff.v:45: $finish called at 150 (1ns)
1196s Test tb_dffe
1196s FST info: dumpfile tb_dffe.fst opened for output.
1196s tb/tb_dffe.v:40: $finish called at 120 (1ns)
1196s Test tb_dffsr
1196s FST info: dumpfile tb_dffsr.fst opened for output.
1196s tb/tb_dffsr.v:67: $finish called at 250 (1ns)
1196s Test tb_dlatch
1196s FST info: dumpfile tb_dlatch.fst opened for output.
1196s tb/tb_dlatch.v:48: $finish called at 160 (1ns)
1196s Test tb_dlatchsr
1196s FST info: dumpfile tb_dlatchsr.fst opened for output.
1196s tb/tb_dlatchsr.v:63: $finish called at 250 (1ns)
1196s Test tb_sdff
1196s FST info: dumpfile tb_sdff.fst opened for output.
1196s tb/tb_sdff.v:46: $finish called at 150 (1ns)
1196s Test tb_sdffce
1196s FST info: dumpfile tb_sdffce.fst opened for output.
1196s tb/tb_sdffce.v:77: $finish called at 300 (1ns)
1196s Test tb_sdffe
1196s FST info: dumpfile tb_sdffe.fst opened for output.
1196s tb/tb_sdffe.v:68: $finish called at 250 (1ns)
1196s make[1]: Entering directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/sim'
1196s Passed sim_adff.ys
1196s Passed sim_adffe.ys
1196s Passed sim_adlatch.ys
1197s Warning: Async reset value `\ad' is not constant!
1197s Passed sim_aldff.ys
1197s Warning: Async reset value `\ad' is not constant!
1197s Passed sim_aldffe.ys
1197s Passed sim_dff.ys
1197s Passed sim_dffe.ys
1197s Warning: Complex async reset for dff `\q'.
1197s Passed sim_dffsr.ys
1197s Passed sim_dlatch.ys
1197s Passed sim_dlatchsr.ys
1197s Passed sim_sdff.ys
1197s Passed sim_sdffce.ys
1197s Passed sim_sdffe.ys
1197s make[1]: Leaving directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/sim'
1197s cd tests/svinterfaces && bash run-test.sh ""
1197s Test: svinterface1 -> svinterface1_tb.v:50: $finish called at 420000 (10ps)
1197s svinterface1_tb.v:50: $finish called at 420000 (10ps)
1197s ok
1198s Test: svinterface_at_top -> svinterface_at_top_tb.v:61: $finish called at 420000 (10ps)
1198s svinterface_at_top_tb_wrapper.v:61: $finish called at 420000 (10ps)
1198s ERROR!
1198s Test: load_and_derive ->ok
1198s Test: resolve_types ->ok
1198s cd tests/svtypes && bash run-test.sh ""
1198s make[1]: Entering directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/svtypes'
1198s Passed enum_simple.ys
1198s Passed logic_rom.ys
1198s <<EOT:7: ERROR: Insufficient number of array indices for a.
1198s Expected error pattern 'Insufficient number of array indices for a.' found !!!
1198s Passed multirange_subarray_access.ys
1198s <<EOT:1: ERROR: Static cast with zero or negative size!
1198s Expected error pattern 'Static cast with zero or negative size' found !!!
1198s Passed static_cast_negative.ys
1198s Passed static_cast_nonconst.ys
1198s <<EOT:1: ERROR: Static cast with non constant expression!
1198s Expected error pattern 'Static cast with non constant expression' found !!!
1198s Passed static_cast_verilog.ys
1199s <<EOT:1: ERROR: Static cast is only supported in SystemVerilog mode.
1199s Expected error pattern 'Static cast is only supported in SystemVerilog mode' found !!!
1199s Passed static_cast_zero.ys
1199s <<EOT:1: ERROR: Static cast with zero or negative size!
1199s Expected error pattern 'Static cast with zero or negative size' found !!!
1199s Passed struct_dynamic_range.ys
1199s Warning: reg '\var_12' is assigned in a continuous assignment at typedef_initial_and_assign.sv:67.9-67.19.
1199s Warning: reg '\var_13' is assigned in a continuous assignment at typedef_initial_and_assign.sv:71.9-71.19.
1199s Warning: reg '\var_14' is assigned in a continuous assignment at typedef_initial_and_assign.sv:74.9-74.19.
1199s Warning: reg '\var_15' is assigned in a continuous assignment at typedef_initial_and_assign.sv:78.9-78.19.
1199s Warning: reg '\var_16' is assigned in a continuous assignment at typedef_initial_and_assign.sv:81.9-81.19.
1199s Warning: reg '\var_17' is assigned in a continuous assignment at typedef_initial_and_assign.sv:85.9-85.19.
1199s Warning: reg '\var_18' is assigned in a continuous assignment at typedef_initial_and_assign.sv:88.9-88.19.
1199s Warning: reg '\var_19' is assigned in a continuous assignment at typedef_initial_and_assign.sv:92.9-92.19.
1199s Passed typedef_initial_and_assign.ys
1199s Passed typedef_memory.ys
1199s Passed typedef_memory_2.ys
1199s Passed typedef_struct_port.ys
1199s Passed multirange_array.sv
1199s Passed static_cast_simple.sv
1199s struct_array.sv:22: Warning: Range [3:-4] select out of bounds on signal `\s': Setting 4 LSB bits to undef.
1199s struct_array.sv:23: Warning: Range select [23:16] out of bounds on signal `\s': Setting all 8 result bits to undef.
1199s struct_array.sv:24: Warning: Range [19:12] select out of bounds on signal `\s': Setting 4 MSB bits to undef.
1199s struct_array.sv:15: Warning: Range [-1:-8] select out of bounds on signal `\s': Setting 8 LSB bits to undef.
1199s Passed struct_array.sv
1199s Passed struct_simple.sv
1199s Passed struct_sizebits.sv
1199s Passed typedef_package.sv
1200s Passed typedef_param.sv
1200s Passed typedef_scopes.sv
1200s Passed typedef_simple.sv
1200s Passed typedef_struct.sv
1200s Passed union_simple.sv
1200s make[1]: Leaving directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/svtypes'
1200s cd tests/proc && bash run-test.sh
1200s Running bug2619.ys..
1200s Running bug2656.ys..
1200s Warning: wire '\q1' is assigned in a block at <<EOT:8.3-8.11.
1200s Warning: wire '\q2' is assigned in a block at <<EOT:12.3-12.10.
1200s Warning: wire '\q2' is assigned in a block at <<EOT:14.3-14.11.
1200s Running bug2962.ys..
1200s Running bug_1268.ys..
1200s Running clean_undef_case.ys..
1200s Running proc_rom.ys..
1200s Warning: wire '\d' is assigned in a block at <<EOT:7.10-7.20.
1200s Warning: wire '\d' is assigned in a block at <<EOT:8.10-8.20.
1200s Warning: wire '\d' is assigned in a block at <<EOT:9.10-9.20.
1200s Warning: wire '\d' is assigned in a block at <<EOT:10.10-10.20.
1200s Warning: wire '\d' is assigned in a block at <<EOT:11.10-11.20.
1200s Warning: wire '\d' is assigned in a block at <<EOT:12.10-12.20.
1200s Warning: wire '\d' is assigned in a block at <<EOT:13.10-13.20.
1200s Warning: wire '\d' is assigned in a block at <<EOT:14.10-14.20.
1200s Warning: wire '\d' is assigned in a block at <<EOT:15.10-15.20.
1200s Warning: wire '\d' is assigned in a block at <<EOT:16.10-16.20.
1200s Warning: wire '\d' is assigned in a block at <<EOT:17.10-17.20.
1200s Warning: wire '\d' is assigned in a block at <<EOT:18.10-18.20.
1200s Warning: wire '\d' is assigned in a block at <<EOT:19.10-19.20.
1200s Warning: wire '\d' is assigned in a block at <<EOT:20.10-20.20.
1200s Warning: wire '\d' is assigned in a block at <<EOT:21.10-21.20.
1200s Warning: wire '\d' is assigned in a block at <<EOT:22.10-22.20.
1200s Warning: wire '\d' is assigned in a block at <<EOT:25.3-25.9.
1200s Warning: wire '\d' is assigned in a block at <<EOT:20.13-20.23.
1200s Warning: wire '\d' is assigned in a block at <<EOT:23.3-23.9.
1200s Warning: wire '\d' is assigned in a block at <<EOT:7.7-7.17.
1200s Warning: wire '\d' is assigned in a block at <<EOT:8.7-8.17.
1200s Warning: wire '\d' is assigned in a block at <<EOT:9.7-9.17.
1200s Warning: wire '\d' is assigned in a block at <<EOT:10.7-10.17.
1200s Warning: wire '\d' is assigned in a block at <<EOT:11.7-11.17.
1200s Warning: wire '\d' is assigned in a block at <<EOT:12.7-12.17.
1200s Warning: wire '\d' is assigned in a block at <<EOT:13.7-13.17.
1200s Warning: wire '\d' is assigned in a block at <<EOT:14.7-14.17.
1200s Warning: wire '\d' is assigned in a block at <<EOT:15.7-15.17.
1200s Warning: wire '\d' is assigned in a block at <<EOT:16.7-16.17.
1200s Warning: wire '\d' is assigned in a block at <<EOT:17.8-17.18.
1200s Warning: wire '\d' is assigned in a block at <<EOT:18.8-18.18.
1200s Warning: wire '\d' is assigned in a block at <<EOT:19.8-19.18.
1200s Warning: wire '\d' is assigned in a block at <<EOT:7.9-7.19.
1200s Warning: wire '\d' is assigned in a block at <<EOT:8.9-8.19.
1200s Warning: wire '\d' is assigned in a block at <<EOT:9.9-9.19.
1200s Warning: wire '\d' is assigned in a block at <<EOT:10.9-10.19.
1200s Warning: wire '\d' is assigned in a block at <<EOT:11.9-11.19.
1200s Warning: wire '\d' is assigned in a block at <<EOT:12.9-12.19.
1200s Warning: wire '\d' is assigned in a block at <<EOT:13.9-13.19.
1200s Warning: wire '\d' is assigned in a block at <<EOT:14.9-14.19.
1200s Warning: wire '\d' is assigned in a block at <<EOT:15.9-15.19.
1200s Warning: wire '\d' is assigned in a block at <<EOT:16.9-16.19.
1200s Warning: wire '\d' is assigned in a block at <<EOT:17.9-17.19.
1200s Warning: wire '\d' is assigned in a block at <<EOT:18.9-18.19.
1200s Warning: wire '\d' is assigned in a block at <<EOT:19.9-19.19.
1200s Warning: wire '\d' is assigned in a block at <<EOT:20.9-20.19.
1200s Warning: wire '\d' is assigned in a block at <<EOT:21.9-21.19.
1200s Warning: wire '\d' is assigned in a block at <<EOT:22.9-22.19.
1200s Running rmdead.ys..
1200s cd tests/blif && bash run-test.sh
1200s Running bug2729.ys..
1200s Running bug3374.ys..
1200s ERROR: Syntax error in line 1!
1200s Expected error pattern 'Syntax error in line 1!' found !!!
1200s Running bug3385.ys..
1200s ERROR: Syntax error in line 4: names' input plane must have fewer than 13 signals.
1200s Expected error pattern 'Syntax error in line 4: names' input plane must have fewer than 13 signals.' found !!!
1200s cd tests/opt && bash run-test.sh
1200s make[1]: Entering directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/opt'
1200s Passed bug1525.ys
1200s Passed bug1758.ys
1200s Passed bug1854.ys
1201s Passed bug2010.ys
1201s Passed bug2221.ys
1201s Passed bug2311.ys
1201s Passed bug2318.ys
1201s Passed bug2623.ys
1201s Passed bug2765.ys
1201s Passed bug2766.ys
1201s Passed bug2824.ys
1201s Passed bug2920.ys
1201s Passed bug3047.ys
1201s Passed bug3117.ys
1201s Passed bug3848.ys
1201s Passed bug3867.ys
1201s Passed memory_bmux2rom.ys
1201s Passed memory_dff_trans.ys
1202s Passed memory_map_offset.ys
1202s Passed opt_clean_init.ys
1202s Passed opt_clean_mem.ys
1202s Passed opt_dff_arst.ys
1203s Passed opt_dff_clk.ys
1203s Passed opt_dff_const.ys
1203s Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:2)
1203s Passed opt_dff_dffmux.ys
1203s <<EOT:19: Warning: Range select [13:12] out of bounds on signal `\Q': Setting all 2 result bits to undef.
1203s <<EOT:20: Warning: Range select [15:14] out of bounds on signal `\Q': Setting all 2 result bits to undef.
1204s Passed opt_dff_en.ys
1205s Passed opt_dff_mux.ys
1205s <<EOT:24: Warning: Range select [21:20] out of bounds on signal `\Q': Setting all 2 result bits to undef.
1205s <<EOT:25: Warning: Range select [23:22] out of bounds on signal `\Q': Setting all 2 result bits to undef.
1205s Passed opt_dff_qd.ys
1207s Passed opt_dff_sr.ys
1207s Passed opt_dff_srst.ys
1207s Passed opt_expr.ys
1207s Passed opt_expr_alu.ys
1207s Passed opt_expr_and.ys
1207s Passed opt_expr_cmp.ys
1207s Warning: wire '\a' is assigned in a block at <<EOT:4.2-4.8.
1207s Warning: wire '\a' is assigned in a block at <<EOT:5.2-5.8.
1207s Warning: wire '\a' is assigned in a block at <<EOT:4.9-4.15.
1207s Warning: wire '\a' is assigned in a block at <<EOT:5.9-5.15.
1207s Passed opt_expr_combined_assign.ys
1207s Passed opt_expr_constconn.ys
1207s Passed opt_expr_consumex.ys
1207s Passed opt_expr_or.ys
1207s Passed opt_expr_xnor.ys
1208s Passed opt_expr_xor.ys
1209s Warning: Yosys has only limited support for tri-state logic at the moment. (/usr/bin/../share/yosys/ice40/cells_sim.v:41)
1209s Warning: Yosys has only limited support for tri-state logic at the moment. (/usr/bin/../share/yosys/ice40/cells_sim.v:86)
1209s Warning: Yosys has only limited support for tri-state logic at the moment. (/usr/bin/../share/yosys/ice40/cells_sim.v:87)
1209s Warning: Yosys has only limited support for tri-state logic at the moment. (/usr/bin/../share/yosys/ice40/cells_sim.v:2153)
1209s Warning: Yosys has only limited support for tri-state logic at the moment. (/usr/bin/../share/yosys/ice40/cells_sim.v:2154)
1209s Warning: Yosys has only limited support for tri-state logic at the moment. (/usr/bin/../share/yosys/ice40/cells_sim.v:2155)
1209s Warning: Yosys has only limited support for tri-state logic at the moment. (/usr/bin/../share/yosys/ice40/cells_sim.v:2156)
1209s Warning: Yosys has only limited support for tri-state logic at the moment. (/usr/bin/../share/yosys/ice40/cells_sim.v:2157)
1209s Warning: Yosys has only limited support for tri-state logic at the moment. (/usr/bin/../share/yosys/ice40/cells_sim.v:2158)
1209s Warning: Yosys has only limited support for tri-state logic at the moment. (/usr/bin/../share/yosys/ice40/cells_sim.v:2925)
1209s Warning: Yosys has only limited support for tri-state logic at the moment. (/usr/bin/../share/yosys/ice40/cells_sim.v:2926)
1209s Warning: Yosys has only limited support for tri-state logic at the moment. (/usr/bin/../share/yosys/ice40/cells_sim.v:2988)
1209s Warning: Yosys has only limited support for tri-state logic at the moment. (/usr/bin/../share/yosys/ice40/cells_sim.v:2989)
1209s Warning: Yosys has only limited support for tri-state logic at the moment. (/usr/bin/../share/yosys/ice40/cells_sim.v:2990)
1209s Warning: Yosys has only limited support for tri-state logic at the moment. (/usr/bin/../share/yosys/ice40/cells_sim.v:3203)
1209s Warning: Yosys has only limited support for tri-state logic at the moment. (/usr/bin/../share/yosys/ice40/cells_sim.v:3210)
1209s Passed opt_lut.ys
1209s Passed opt_lut_elim.ys
1209s Passed opt_lut_ins.ys
1209s Passed opt_lut_port.ys
1214s Passed opt_mem_feedback.ys
1215s Passed opt_mem_priority.ys
1215s Passed opt_merge_init.ys
1215s Passed opt_merge_keep.ys
1215s Passed opt_reduce_bmux.ys
1215s Passed opt_reduce_demux.ys
1215s Warning: Wire opt_rmdff_test.\Q [22] is used but has no driver.
1216s Passed opt_rmdff.ys
1216s Passed opt_rmdff_sat.ys
1216s Passed opt_share_add_sub.ys
1216s Passed opt_share_bug2334.ys
1216s Passed opt_share_bug2335.ys
1216s Passed opt_share_bug2336.ys
1216s Passed opt_share_bug2538.ys
1216s Passed opt_share_cat.ys
1216s Passed opt_share_cat_multiuser.ys
1216s Passed opt_share_diff_port_widths.ys
1217s Passed opt_share_extend.ys
1217s Passed opt_share_large_pmux_cat.ys
1217s Passed opt_share_large_pmux_cat_multipart.ys
1217s Passed opt_share_large_pmux_multipart.ys
1217s Passed opt_share_large_pmux_part.ys
1217s Passed opt_share_mux_tree.ys
1217s make[1]: Leaving directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/opt'
1217s cd tests/aiger && bash run-test.sh ""
1218s Checking and_.aag.
1218s Checking buffer.aag.
1218s Checking cnt1.aag.
1218s Warning: The new network has no primary inputs. It is recommended
1218s to add a dummy PI to make sure all commands work correctly.
1218s Checking cnt1e.aag.
1218s Checking empty.aag.
1218s Warning: The new network has no primary inputs. It is recommended
1218s to add a dummy PI to make sure all commands work correctly.
1218s Warning: The current network has no primary outputs. Some commands may not work correctly.
1218s Checking false.aag.
1218s Warning: The new network has no primary inputs. It is recommended
1218s to add a dummy PI to make sure all commands work correctly.
1218s Checking halfadder.aag.
1218s Checking inverter.aag.
1218s Checking notcnt1.aag.
1218s Warning: The new network has no primary inputs. It is recommended
1218s to add a dummy PI to make sure all commands work correctly.
1218s Checking notcnt1e.aag.
1218s Checking or_.aag.
1218s Checking symbols.aag.
1219s Checking toggle-re.aag.
1219s Checking toggle.aag.
1219s Warning: The new network has no primary inputs. It is recommended
1219s to add a dummy PI to make sure all commands work correctly.
1219s Checking true.aag.
1219s Warning: The new network has no primary inputs. It is recommended
1219s to add a dummy PI to make sure all commands work correctly.
1219s Checking and_.aig.
1219s Checking buffer.aig.
1219s Checking cnt1.aig.
1219s Warning: The new network has no primary inputs. It is recommended
1219s to add a dummy PI to make sure all commands work correctly.
1219s Checking cnt1e.aig.
1219s Checking empty.aig.
1219s Warning: The new network has no primary inputs. It is recommended
1219s to add a dummy PI to make sure all commands work correctly.
1219s Warning: The current network has no primary outputs. Some commands may not work correctly.
1219s Checking false.aig.
1219s Warning: The new network has no primary inputs. It is recommended
1219s to add a dummy PI to make sure all commands work correctly.
1219s Checking halfadder.aig.
1219s Checking inverter.aig.
1220s Checking notcnt1.aig.
1220s Warning: The new network has no primary inputs. It is recommended
1220s to add a dummy PI to make sure all commands work correctly.
1220s Checking notcnt1e.aig.
1220s Checking or_.aig.
1220s Checking symbols.aig.
1220s Checking toggle-re.aig.
1220s Checking toggle.aig.
1220s Warning: The new network has no primary inputs. It is recommended
1220s to add a dummy PI to make sure all commands work correctly.
1220s Checking true.aig.
1220s Warning: The new network has no primary inputs. It is recommended
1220s to add a dummy PI to make sure all commands work correctly.
1220s Running neg.ys.
1220s cd tests/arch && bash run-test.sh
1220s Running syntax check on arch sim models
1220s Test ../../techlibs/achronix/speedster22i/cells_sim.v -> ok
1220s Test ../../techlibs/anlogic/cells_sim.v -> ok
1220s Test ../../techlibs/coolrunner2/cells_sim.v -> ok
1220s Test ../../techlibs/ecp5/cells_sim.v -> ok
1220s Test ../../techlibs/efinix/cells_sim.v -> ok
1220s Test ../../techlibs/gatemate/cells_sim.v -> ok
1220s Test ../../techlibs/gowin/cells_sim.v -> ok
1220s Test ../../techlibs/greenpak4/cells_sim.v -> ok
1220s Test ../../techlibs/ice40/cells_sim.v -DICE40_HX ->../../techlibs/ice40/cells_sim.v:2231: warning: Choosing typ expression.
1220s ../../techlibs/ice40/cells_sim.v:2231: warning: Choosing typ expression.
1220s ../../techlibs/ice40/cells_sim.v:2233: warning: Choosing typ expression.
1220s ../../techlibs/ice40/cells_sim.v:2233: warning: Choosing typ expression.
1220s ../../techlibs/ice40/cells_sim.v:2235: warning: Choosing typ expression.
1220s ../../techlibs/ice40/cells_sim.v:2235: warning: Choosing typ expression.
1220s ../../techlibs/ice40/cells_sim.v:2237: warning: Choosing typ expression.
1220s ../../techlibs/ice40/cells_sim.v:2237: warning: Choosing typ expression.
1220s ../../techlibs/ice40/cells_sim.v:2239: warning: Choosing typ expression.
1220s ../../techlibs/ice40/cells_sim.v:2239: warning: Choosing typ expression.
1220s  ok
1220s Test ../../techlibs/ice40/cells_sim.v -DICE40_LP ->../../techlibs/ice40/cells_sim.v:2295: warning: Choosing typ expression.
1220s ../../techlibs/ice40/cells_sim.v:2295: warning: Choosing typ expression.
1220s ../../techlibs/ice40/cells_sim.v:2297: warning: Choosing typ expression.
1220s ../../techlibs/ice40/cells_sim.v:2297: warning: Choosing typ expression.
1220s ../../techlibs/ice40/cells_sim.v:2299: warning: Choosing typ expression.
1220s ../../techlibs/ice40/cells_sim.v:2299: warning: Choosing typ expression.
1220s ../../techlibs/ice40/cells_sim.v:2301: warning: Choosing typ expression.
1220s ../../techlibs/ice40/cells_sim.v:2301: warning: Choosing typ expression.
1220s ../../techlibs/ice40/cells_sim.v:2303: warning: Choosing typ expression.
1220s ../../techlibs/ice40/cells_sim.v:2303: warning: Choosing typ expression.
1220s  ok
1221s Test ../../techlibs/ice40/cells_sim.v -DICE40_U ->../../techlibs/ice40/cells_sim.v:2359: warning: Choosing typ expression.
1221s ../../techlibs/ice40/cells_sim.v:2359: warning: Choosing typ expression.
1221s ../../techlibs/ice40/cells_sim.v:2361: warning: Choosing typ expression.
1221s ../../techlibs/ice40/cells_sim.v:2361: warning: Choosing typ expression.
1221s ../../techlibs/ice40/cells_sim.v:2363: warning: Choosing typ expression.
1221s ../../techlibs/ice40/cells_sim.v:2363: warning: Choosing typ expression.
1221s ../../techlibs/ice40/cells_sim.v:2365: warning: Choosing typ expression.
1221s ../../techlibs/ice40/cells_sim.v:2365: warning: Choosing typ expression.
1221s ../../techlibs/ice40/cells_sim.v:2367: warning: Choosing typ expression.
1221s ../../techlibs/ice40/cells_sim.v:2367: warning: Choosing typ expression.
1221s  ok
1221s Test ../../techlibs/intel/cyclone10lp/cells_sim.v -> ok
1221s Test ../../techlibs/intel/cycloneiv/cells_sim.v -> ok
1221s Test ../../techlibs/intel/cycloneive/cells_sim.v -> ok
1221s Test ../../techlibs/intel/max10/cells_sim.v -> ok
1221s Test ../../techlibs/intel_alm/cyclonev/cells_sim.v -> ok
1221s Test ../../techlibs/nexus/cells_sim.v -> ok
1221s Test ../../techlibs/quicklogic/cells_sim.v -> ok
1221s Test ../../techlibs/sf2/cells_sim.v -> ok
1221s Test ../../techlibs/xilinx/cells_sim.v -> ok
1221s Test ../../techlibs/common/simcells.v -> ok
1221s Test ../../techlibs/common/simlib.v -> ok
1221s cd tests/arch/ice40 && bash run-test.sh ""
1221s make[1]: Entering directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/arch/ice40'
1222s Passed add_sub.ys
1228s Passed adffs.ys
1228s Warning: Resizing cell port SSCounter6o.l0.I3 from 32 bits to 1 bits.
1228s Warning: Resizing cell port SSCounter6o.c0.CI from 32 bits to 1 bits.
1228s Warning: Resizing cell port SSCounter6o.lien.I0 from 32 bits to 1 bits.
1228s Warning: Resizing cell port SSCounter6o.lien.I1 from 32 bits to 1 bits.
1230s Passed bug1597.ys
1231s Passed bug1598.ys
1232s Passed bug1626.ys
1258s Passed bug1644.ys
1259s Passed bug2061.ys
1260s Passed counter.ys
1263s Passed dffs.ys
1281s Passed dpram.ys
1283s Passed fsm.ys
1283s Passed ice40_dsp.ys
1284s Passed ice40_opt.ys
1284s Passed ice40_wrapcarry.ys
1288s Passed latches.ys
1290s Passed logic.ys
1300s Passed macc.ys
1379s Passed memories.ys
1380s Passed mul.ys
1387s Passed mux.ys
1387s Warning: wire '\data' is assigned in a block at rom.v:10.5-10.15.
1387s Warning: wire '\data' is assigned in a block at rom.v:11.5-11.15.
1387s Warning: wire '\data' is assigned in a block at rom.v:12.5-12.15.
1387s Warning: wire '\data' is assigned in a block at rom.v:13.6-13.16.
1387s Warning: wire '\data' is assigned in a block at rom.v:14.6-14.16.
1387s Warning: wire '\data' is assigned in a block at rom.v:15.6-15.16.
1387s Warning: wire '\data' is assigned in a block at rom.v:16.11-16.21.
1388s Passed rom.ys
1389s Passed shifter.ys
1389s Warning: wire '\read_data' is assigned in a block at spram.v:19.3-19.25.
1392s Passed spram.ys
1393s Passed tribuf.ys
1393s make[1]: Leaving directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/arch/ice40'
1393s cd tests/arch/xilinx && bash run-test.sh ""
1393s make[1]: Entering directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/arch/xilinx'
1417s Warning: Whitebox '$paramod\FDRE\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox.
1417s Warning: Whitebox 'FDSE' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox.
1418s Warning: Whitebox '$paramod\FDRE_1\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox.
1418s Warning: Whitebox '$paramod\FDSE_1\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox.
1459s Passed abc9_dff.ys
1465s Warning: Shift register inference not yet supported for family xc3s.
1471s Passed add_sub.ys
1501s Passed adffs.ys
1508s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DIADI from 64 bits to 16 bits.
1508s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOADO from 64 bits to 16 bits.
1508s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOBDO from 64 bits to 16 bits.
1508s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOPADOP from 8 bits to 2 bits.
1508s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOPBDOP from 8 bits to 2 bits.
1508s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.WEA from 4 bits to 2 bits.
1522s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.WEBWE from 1 bits to 4 bits.
1530s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DIADI from 64 bits to 16 bits.
1530s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOADO from 64 bits to 16 bits.
1530s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOBDO from 64 bits to 16 bits.
1530s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOPADOP from 8 bits to 2 bits.
1530s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOPBDOP from 8 bits to 2 bits.
1530s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.WEA from 4 bits to 2 bits.
1530s Warning: Selection "asym_ram_sdp_read_wider" did not match any module.
1551s Passed asym_ram_sdp.ys
1558s Warning: Resizing cell port block_ram.memory.0.0.DIADI from 64 bits to 16 bits.
1558s Warning: Resizing cell port block_ram.memory.0.0.DOADO from 64 bits to 16 bits.
1558s Warning: Resizing cell port block_ram.memory.0.0.DOBDO from 64 bits to 16 bits.
1558s Warning: Resizing cell port block_ram.memory.0.0.DOPADOP from 8 bits to 2 bits.
1558s Warning: Resizing cell port block_ram.memory.0.0.DOPBDOP from 8 bits to 2 bits.
1558s Warning: Resizing cell port block_ram.memory.0.0.WEA from 4 bits to 2 bits.
1595s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DIADI from 64 bits to 16 bits.
1595s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOADO from 64 bits to 16 bits.
1595s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOBDO from 64 bits to 16 bits.
1595s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOPADOP from 8 bits to 2 bits.
1595s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOPBDOP from 8 bits to 2 bits.
1595s Warning: Resizing cell port distributed_ram_manual.memory.0.0.WEA from 4 bits to 2 bits.
1595s Passed attributes_test.ys
1602s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIADI from 64 bits to 16 bits.
1602s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOADO from 64 bits to 16 bits.
1602s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOBDO from 64 bits to 16 bits.
1602s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPADOP from 8 bits to 2 bits.
1602s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPBDOP from 8 bits to 2 bits.
1602s Warning: Resizing cell port sync_ram_sdp.memory.0.0.WEA from 4 bits to 2 bits.
1608s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIPADIP from 8 bits to 2 bits.
1635s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIADI from 64 bits to 32 bits.
1635s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIPADIP from 8 bits to 4 bits.
1635s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOADO from 64 bits to 32 bits.
1635s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOBDO from 64 bits to 32 bits.
1635s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPADOP from 8 bits to 4 bits.
1635s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPBDOP from 8 bits to 4 bits.
1680s Passed blockram.ys
1686s Passed bug1460.ys
1692s Passed bug1462.ys
1698s Passed bug1480.ys
1706s Passed bug1598.ys
1707s Warning: Wire top.\t is used but has no driver.
1707s Warning: Wire top.\in is used but has no driver.
1712s Passed bug1605.ys
1712s Passed bug3670.ys
1719s Passed counter.ys
1750s Passed dffs.ys
1774s Passed dsp_abc9.ys
1792s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef.
1792s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef.
1875s Passed dsp_cascade.ys
1881s Passed dsp_fastfir.ys
1891s Passed dsp_simd.ys
1899s Warning: Shift register inference not yet supported for family xc3se.
1906s Passed fsm.ys
1927s Passed latches.ys
1934s Passed logic.ys
2006s Warning: Shift register inference not yet supported for family xc3s.
2013s Passed lutram.ys
2029s Passed macc.ys
2040s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef.
2040s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef.
2042s Passed mul.ys
2042s Warning: Replacing memory \M with list of registers. See mul_unsigned.v:25
2058s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef.
2058s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef.
2064s Passed mul_unsigned.ys
2092s Passed mux.ys
2092s Warning: Shift register inference not yet supported for family xc3se.
2112s Passed mux_lut4.ys
2125s Passed nosrl.ys
2125s Passed opt_lut_ins.ys
2143s Passed pmgen_xilinx_srl.ys
2150s Warning: Resizing cell port priority_memory.mem.0.0.ADDRARDADDR from 16 bits to 15 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.0.ADDRBWRADDR from 16 bits to 15 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.0.DINADIN from 64 bits to 32 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.0.DINBDIN from 64 bits to 32 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.0.DINPADINP from 8 bits to 4 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.0.DINPBDINP from 8 bits to 4 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.0.DOUTADOUT from 64 bits to 32 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.0.DOUTBDOUT from 64 bits to 32 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.0.DOUTPADOUTP from 8 bits to 4 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.0.DOUTPBDOUTP from 8 bits to 4 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.0.WEBWE from 4 bits to 8 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.1.ADDRARDADDR from 16 bits to 15 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.1.ADDRBWRADDR from 16 bits to 15 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.1.DINADIN from 64 bits to 32 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.1.DINBDIN from 64 bits to 32 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.1.DINPADINP from 8 bits to 4 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.1.DINPBDINP from 8 bits to 4 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.1.DOUTADOUT from 64 bits to 32 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.1.DOUTBDOUT from 64 bits to 32 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.1.DOUTPADOUTP from 8 bits to 4 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.1.DOUTPBDOUTP from 8 bits to 4 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.1.WEBWE from 4 bits to 8 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.2.ADDRARDADDR from 16 bits to 15 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.2.ADDRBWRADDR from 16 bits to 15 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.2.DINADIN from 64 bits to 32 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.2.DINBDIN from 64 bits to 32 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.2.DINPADINP from 8 bits to 4 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.2.DINPBDINP from 8 bits to 4 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.2.DOUTADOUT from 64 bits to 32 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.2.DOUTBDOUT from 64 bits to 32 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.2.DOUTPADOUTP from 8 bits to 4 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.2.DOUTPBDOUTP from 8 bits to 4 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.2.WEBWE from 4 bits to 8 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.3.ADDRARDADDR from 16 bits to 15 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.3.ADDRBWRADDR from 16 bits to 15 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.3.DINADIN from 64 bits to 32 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.3.DINBDIN from 64 bits to 32 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.3.DINPADINP from 8 bits to 4 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.3.DINPBDINP from 8 bits to 4 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.3.DOUTADOUT from 64 bits to 32 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.3.DOUTBDOUT from 64 bits to 32 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.3.DOUTPADOUTP from 8 bits to 4 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.3.DOUTPBDOUTP from 8 bits to 4 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.3.WEBWE from 4 bits to 8 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.4.ADDRARDADDR from 16 bits to 15 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.4.ADDRBWRADDR from 16 bits to 15 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.4.DINADIN from 64 bits to 32 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.4.DINBDIN from 64 bits to 32 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.4.DINPADINP from 8 bits to 4 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.4.DINPBDINP from 8 bits to 4 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.4.DOUTADOUT from 64 bits to 32 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.4.DOUTBDOUT from 64 bits to 32 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.4.DOUTPADOUTP from 8 bits to 4 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.4.DOUTPBDOUTP from 8 bits to 4 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.4.WEBWE from 4 bits to 8 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.5.ADDRARDADDR from 16 bits to 15 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.5.ADDRBWRADDR from 16 bits to 15 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.5.DINADIN from 64 bits to 32 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.5.DINBDIN from 64 bits to 32 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.5.DINPADINP from 8 bits to 4 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.5.DINPBDINP from 8 bits to 4 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.5.DOUTADOUT from 64 bits to 32 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.5.DOUTBDOUT from 64 bits to 32 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.5.DOUTPADOUTP from 8 bits to 4 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.5.DOUTPBDOUTP from 8 bits to 4 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.5.WEBWE from 4 bits to 8 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.6.ADDRARDADDR from 16 bits to 15 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.6.ADDRBWRADDR from 16 bits to 15 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.6.DINADIN from 64 bits to 32 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.6.DINBDIN from 64 bits to 32 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.6.DINPADINP from 8 bits to 4 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.6.DINPBDINP from 8 bits to 4 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.6.DOUTADOUT from 64 bits to 32 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.6.DOUTBDOUT from 64 bits to 32 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.6.DOUTPADOUTP from 8 bits to 4 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.6.DOUTPBDOUTP from 8 bits to 4 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.6.WEBWE from 4 bits to 8 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.7.ADDRARDADDR from 16 bits to 15 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.7.ADDRBWRADDR from 16 bits to 15 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.7.DINADIN from 64 bits to 32 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.7.DINBDIN from 64 bits to 32 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.7.DINPADINP from 8 bits to 4 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.7.DINPBDINP from 8 bits to 4 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.7.DOUTADOUT from 64 bits to 32 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.7.DOUTBDOUT from 64 bits to 32 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.7.DOUTPADOUTP from 8 bits to 4 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.7.DOUTPBDOUTP from 8 bits to 4 bits.
2150s Warning: Resizing cell port priority_memory.mem.0.7.WEBWE from 4 bits to 8 bits.
2156s Warning: Resizing cell port priority_memory.mem.0.0.BWE_A from 8 bits to 9 bits.
2156s Warning: Resizing cell port priority_memory.mem.0.0.BWE_B from 8 bits to 9 bits.
2174s Warning: Resizing cell port sp_write_first.mem.0.0.BWE_A from 8 bits to 9 bits.
2180s Warning: Resizing cell port sp_read_first.mem.0.0.BWE_B from 8 bits to 9 bits.
2180s Passed priority_memory.ys
2187s Passed shifter.ys
2193s Passed tribuf.ys
2198s Passed xilinx_dffopt.ys
2198s Passed xilinx_dsp.ys
2198s Passed xilinx_srl.ys
2211s Passed macc.sh
2222s Passed tribuf.sh
2222s make[1]: Leaving directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/arch/xilinx'
2222s cd tests/arch/ecp5 && bash run-test.sh ""
2222s make[1]: Entering directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/arch/ecp5'
2223s Passed add_sub.ys
2226s Passed adffs.ys
2228s Passed bug1459.ys
2229s Passed bug1598.ys
2229s Passed bug1630.ys
2229s Warning: Literal has a width of 16 bit, but value requires 184 bit. (<<EOT:1)
2229s Warning: Literal has a width of 16 bit, but value requires 183 bit. (<<EOT:1)
2229s Warning: Literal has a width of 16 bit, but value requires 182 bit. (<<EOT:1)
2229s Warning: Literal has a width of 16 bit, but value requires 165 bit. (<<EOT:1)
2229s Warning: Literal has a width of 16 bit, but value requires 152 bit. (<<EOT:1)
2229s Warning: Literal has a width of 16 bit, but value requires 126 bit. (<<EOT:1)
2229s Warning: Literal has a width of 16 bit, but value requires 108 bit. (<<EOT:1)
2229s Warning: Literal has a width of 16 bit, but value requires 150 bit. (<<EOT:1)
2229s Warning: Literal has a width of 16 bit, but value requires 164 bit. (<<EOT:1)
2229s Warning: Literal has a width of 16 bit, but value requires 181 bit. (<<EOT:1)
2230s Passed bug1836.ys
2231s Passed bug2409.ys
2232s Warning: Whitebox '$paramod\TRELLIS_FF\REGSET=t24'010100110100010101010100' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox.
2232s Passed bug2731.ys
2233s Passed counter.ys
2235s Passed dffs.ys
2237s Passed dpram.ys
2239s Passed fsm.ys
2241s Passed latches.ys
2242s Passed latches_abc9.ys
2243s Passed logic.ys
2257s Passed lutram.ys
2257s Passed macc.ys
2314s Passed memories.ys
2315s Passed mul.ys
2319s Passed mux.ys
2319s Passed opt_lut_ins.ys
2319s Warning: wire '\data' is assigned in a block at rom.v:9.5-9.15.
2319s Warning: wire '\data' is assigned in a block at rom.v:10.5-10.15.
2319s Warning: wire '\data' is assigned in a block at rom.v:11.5-11.15.
2319s Warning: wire '\data' is assigned in a block at rom.v:12.6-12.16.
2319s Warning: wire '\data' is assigned in a block at rom.v:13.6-13.16.
2319s Warning: wire '\data' is assigned in a block at rom.v:14.6-14.16.
2319s Warning: wire '\data' is assigned in a block at rom.v:15.11-15.21.
2320s Passed rom.ys
2321s Passed shifter.ys
2322s Passed tribuf.ys
2322s make[1]: Leaving directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/arch/ecp5'
2322s cd tests/arch/machxo2 && bash run-test.sh ""
2322s make[1]: Entering directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/arch/machxo2'
2323s Passed add_sub.ys
2325s Passed adffs.ys
2325s Passed counter.ys
2327s Passed dffs.ys
2328s Passed fsm.ys
2328s Passed logic.ys
2356s Passed lutram.ys
2359s Passed mux.ys
2360s Passed shifter.ys
2360s Passed tribuf.ys
2360s make[1]: Leaving directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/arch/machxo2'
2360s cd tests/arch/efinix && bash run-test.sh ""
2360s make[1]: Entering directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/arch/efinix'
2360s Passed add_sub.ys
2361s Passed adffs.ys
2361s Passed counter.ys
2361s Passed dffs.ys
2362s Passed fsm.ys
2363s Passed latches.ys
2363s Passed logic.ys
2363s Passed lutram.ys
2364s Passed mux.ys
2364s Passed shifter.ys
2364s Passed tribuf.ys
2364s make[1]: Leaving directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/arch/efinix'
2364s cd tests/arch/anlogic && bash run-test.sh ""
2364s make[1]: Entering directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/arch/anlogic'
2365s Passed add_sub.ys
2374s Passed blockram.ys
2374s Passed counter.ys
2376s Passed dffs.ys
2377s Passed fsm.ys
2380s Passed latches.ys
2380s Passed logic.ys
2381s Passed lutram.ys
2385s Passed mux.ys
2385s Passed shifter.ys
2385s Passed tribuf.ys
2385s make[1]: Leaving directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/arch/anlogic'
2385s cd tests/arch/gowin && bash run-test.sh ""
2385s make[1]: Entering directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/arch/gowin'
2386s Passed add_sub.ys
2390s Passed adffs.ys
2390s Passed compare.ys
2390s Passed counter.ys
2392s Passed dffs.ys
2393s Passed fsm.ys
2393s ERROR: FF myDFFP.$auto$ff.cc:266:slice$663 (type $_DFF_PP1_) cannot be legalized: unsupported initial value and async reset value combination
2393s Expected error pattern 'unsupported initial value and async reset value combination' found !!!
2393s Passed init-error.ys
2395s Passed init.ys
2396s Passed logic.ys
2481s Passed lutram.ys
2484s Passed mux.ys
2484s Passed shifter.ys
2485s Passed tribuf.ys
2485s make[1]: Leaving directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/arch/gowin'
2485s cd tests/arch/intel_alm && bash run-test.sh ""
2485s make[1]: Entering directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/arch/intel_alm'
2486s Passed add_sub.ys
2489s Passed adffs.ys
2489s Passed blockram.ys
2491s Passed counter.ys
2492s Passed dffs.ys
2495s Passed fsm.ys
2496s Passed logic.ys
2502s Passed lutram.ys
2505s Passed mul.ys
2508s Passed mux.ys
2508s Passed quartus_ice.ys
2509s Passed shifter.ys
2511s Passed tribuf.ys
2511s make[1]: Leaving directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/arch/intel_alm'
2511s cd tests/arch/nexus && bash run-test.sh ""
2511s make[1]: Entering directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/arch/nexus'
2523s Passed add_sub.ys
2547s Passed adffs.ys
2559s Passed blockram.ys
2565s Passed counter.ys
2578s Passed dffs.ys
2584s Passed fsm.ys
2590s Passed logic.ys
2616s Passed lutram.ys
2641s Passed mul.ys
2665s Passed mux.ys
2671s Passed shifter.ys
2677s Passed tribuf.ys
2677s make[1]: Leaving directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/arch/nexus'
2677s Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
2677s Warning: Complex async reset for dff `\Q'.
2677s cd tests/arch/quicklogic && bash run-test.sh ""
2677s make[1]: Entering directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/arch/quicklogic'
2677s Passed add_sub.ys
2677s Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
2677s Warning: Complex async reset for dff `\Q'.
2678s Passed adffs.ys
2678s Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
2678s Warning: Complex async reset for dff `\Q'.
2679s Passed counter.ys
2679s Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
2679s Warning: Complex async reset for dff `\Q'.
2679s Passed dffs.ys
2679s Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
2679s Warning: Complex async reset for dff `\Q'.
2680s Passed fsm.ys
2680s Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
2680s Warning: Complex async reset for dff `\Q'.
2681s Passed latches.ys
2681s Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
2681s Warning: Complex async reset for dff `\Q'.
2681s Passed logic.ys
2681s Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
2681s Warning: Complex async reset for dff `\Q'.
2682s Passed mux.ys
2682s Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
2682s Warning: Complex async reset for dff `\Q'.
2682s Passed tribuf.ys
2682s make[1]: Leaving directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/arch/quicklogic'
2682s cd tests/arch/gatemate && bash run-test.sh ""
2682s make[1]: Entering directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/arch/gatemate'
2684s Passed add_sub.ys
2689s Passed adffs.ys
2690s Passed counter.ys
2693s Passed dffs.ys
2695s Passed fsm.ys
2699s Passed latches.ys
2700s Passed logic.ys
2726s Passed luttrees.ys
2745s Passed memory.ys
2749s Passed mul.ys
2752s Passed mux.ys
2754s Passed shifter.ys
2755s Passed tribuf.ys
2755s make[1]: Leaving directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/arch/gatemate'
2755s cd tests/rpc && bash run-test.sh
2755s Running exec.ys..
2756s cd tests/memfile && bash run-test.sh
2756s Running from the parent directory with content1.dat
2756s Running from the parent directory with temp/content2.dat
2756s Running from the parent directory with memfile/temp/content2.dat
2756s Running from the same directory with content1.dat
2756s Running from the same directory with temp/content2.dat
2756s Running from a child directory with content1.dat
2756s Running from a child directory with temp/content2.dat
2756s Running from a child directory with content2.dat
2756s Checking a failure when zero length filename is provided
2756s memory.v:15: ERROR: Can not open file `` for \$readmemb.
2756s Execution failed, which is OK.
2756s Checking a failure when not existing filename is provided
2756s memory.v:15: ERROR: Can not open file `content3.dat` for \$readmemb.
2756s Execution failed, which is OK.
2756s cd tests/verilog && bash run-test.sh
2756s make[1]: Entering directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/verilog'
2756s <<EOF:0: ERROR: Expression width 1073741824 exceeds implementation limit of 16777216!
2756s Expected error pattern 'Expression width 1073741824 exceeds implementation limit of 16777216!' found !!!
2756s Passed absurd_width.ys
2756s <<EOF:0: ERROR: Expression width 1073741824 exceeds implementation limit of 16777216!
2756s Expected error pattern 'Expression width 1073741824 exceeds implementation limit of 16777216!' found !!!
2756s Passed absurd_width_const.ys
2756s ERROR: Latch inferred for signal `\top.$unnamed_block$1.y' from always_comb process `\top.$proc$<<EOF:0$2'.
2756s Expected error pattern '^Latch inferred for signal `\\top\.\$unnamed_block\$1\.y' from always_comb process' found !!!
2756s Passed always_comb_latch_1.ys
2756s ERROR: Latch inferred for signal `\top.$unnamed_block$1.y' from always_comb process `\top.$proc$<<EOF:0$2'.
2756s Expected error pattern '^Latch inferred for signal `\\top\.\$unnamed_block\$1\.y' from always_comb process' found !!!
2756s Passed always_comb_latch_2.ys
2756s ERROR: Latch inferred for signal `\top.$unnamed_block$1.y' from always_comb process `\top.$proc$<<EOF:0$2'.
2756s Expected error pattern '^Latch inferred for signal `\\top\.\$unnamed_block\$1\.y' from always_comb process' found !!!
2756s Passed always_comb_latch_3.ys
2756s ERROR: Latch inferred for signal `\top.$unnamed_block$3.y' from always_comb process `\top.$proc$<<EOF:0$4'.
2756s Expected error pattern '^Latch inferred for signal `\\top\.\$unnamed_block\$3\.y' from always_comb process' found !!!
2756s Passed always_comb_latch_4.ys
2756s Passed always_comb_nolatch_1.ys
2756s Passed always_comb_nolatch_2.ys
2756s Passed always_comb_nolatch_3.ys
2756s Passed always_comb_nolatch_4.ys
2756s Passed always_comb_nolatch_5.ys
2756s Passed always_comb_nolatch_6.ys
2756s Passed atom_type_signedness.ys
2756s <<EOF:5: ERROR: Begin label missing where end label (incorrect_name) was given.
2756s Expected error pattern 'Begin label missing where end label \(incorrect_name\) was given\.' found !!!
2756s Passed block_end_label_only.ys
2756s <<EOF:5: ERROR: Begin label (correct_name) and end label (incorrect_name) don't match.
2756s Expected error pattern 'Begin label \(correct_name\) and end label \(incorrect_name\) don't match\.' found !!!
2756s Passed block_end_label_wrong.ys
2756s <<EOT:5: ERROR: Begin label (a) and end label (b) don't match.
2756s Expected error pattern 'Begin label \(a\) and end label \(b\) don't match\.' found !!!
2756s Passed block_labels.ys
2756s Passed bug2037.ys
2756s <<EOT:6: ERROR: syntax error, unexpected TOK_ENDTASK, expecting ';'
2756s Expected error pattern 'syntax error, unexpected TOK_ENDTASK, expecting ';'' found !!!
2756s Passed bug2042-sv.ys
2756s Passed bug2042.ys
2756s <<EOT:5: ERROR: task/function argument direction missing
2756s Expected error pattern 'task/function argument direction missing' found !!!
2756s <<EOT:6: ERROR: Failed to detect width for identifier \genblk1.y!
2756s Expected error pattern 'Failed to detect width for identifier \\genblk1\.y!' found !!!
2756s Passed bug2493.ys
2756s Passed bug656.ys
2756s Passed conflict_assert.ys
2756s <<EOT:4: ERROR: Cannot add procedural assertion `\x' because a signal with the same name was already created at <<EOT:2.10-2.11!
2756s Expected error pattern 'Cannot add procedural assertion `\\x' because a signal with the same name was already created' found !!!
2756s <<EOT:5: ERROR: Cannot add cell `\x' because a memory with the same name was already created at <<EOT:4.15-4.16!
2756s Expected error pattern 'Cannot add cell `\\x' because a memory with the same name was already created' found !!!
2756s Passed conflict_cell_memory.ys
2756s <<EOT:0: ERROR: Cannot add interface port `\i' because a signal with the same name was already created at <<EOT:9.10-9.11!
2756s Expected error pattern 'Cannot add interface port `\\i' because a signal with the same name was already created' found !!!
2756s Passed conflict_interface_port.ys
2756s <<EOT:3: ERROR: Cannot add memory `\x' because a signal with the same name was already created at <<EOT:2.15-2.16!
2756s Expected error pattern 'Cannot add memory `\\x' because a signal with the same name was already created' found !!!
2756s Passed conflict_memory_wire.ys
2756s <<EOT:3: Warning: Ignoring assignment to constant bits:
2756s     old assignment: 2 = 1
2756s     new assignment: { } = { }.
2756s <<EOT:4: ERROR: Cannot add pwire `\x' because a signal with the same name was already created at <<EOT:2.10-2.11!
2756s Expected error pattern 'Cannot add pwire `\\x' because a signal with the same name was already created' found !!!
2756s Passed conflict_pwire.ys
2756s <<EOT:3: ERROR: Cannot add signal `\x' because a memory with the same name was already created at <<EOT:2.15-2.16!
2756s Expected error pattern 'Cannot add signal `\\x' because a memory with the same name was already created' found !!!
2756s Passed conflict_wire_memory.ys
2756s Passed const_arst.ys
2756s Warning: Complex async reset for dff `\q'.
2756s Passed const_sr.ys
2756s Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:3)
2756s Passed delay_mintypmax.ys
2756s Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:3)
2756s Passed delay_risefall.ys
2756s Passed delay_time_scale.ys
2756s Passed doubleslash.ys
2756s <<EOT:4: ERROR: For loop variable declaration is missing initialization!
2756s Expected error pattern 'For loop variable declaration is missing initialization!' found !!!
2756s Passed for_decl_no_init.ys
2756s <<EOT:4: ERROR: For loop inline variable declaration is only supported in SystemVerilog mode!
2756s Expected error pattern 'For loop inline variable declaration is only supported in SystemVerilog mode!' found !!!
2756s Passed for_decl_no_sv.ys
2756s Passed for_decl_shadow.ys
2756s <<EOT:8: ERROR: Incompatible re-declaration of wire \f$func$<<EOT:8$1.inp.
2756s Expected error pattern 'Incompatible re-declaration of wire' found !!!
2756s Passed func_arg_mismatch_1.ys
2756s <<EOT:0: ERROR: Incompatible re-declaration of constant function wire \f$func$<<EOT:8$1.inp.
2756s Expected error pattern 'Incompatible re-declaration of constant function wire' found !!!
2756s Passed func_arg_mismatch_2.ys
2756s Passed func_arg_mismatch_3.ys
2756s <<EOT:8: ERROR: Incompatible re-declaration of wire \f$func$<<EOT:8$1.inp.
2756s Expected error pattern 'Incompatible re-declaration of wire' found !!!
2756s Passed func_arg_mismatch_4.ys
2756s <<EOT:0: ERROR: Incompatible re-declaration of constant function wire \f$func$<<EOT:8$1.inp.
2756s Expected error pattern 'Incompatible re-declaration of constant function wire' found !!!
2756s Passed func_tern_hint.ys
2756s Passed func_typename_ret.ys
2776s Passed func_upto.ys
2776s <<EOF:5: ERROR: Begin label missing where end label (incorrect_name) was given.
2776s Expected error pattern 'Begin label missing where end label \(incorrect_name\) was given\.' found !!!
2776s Passed gen_block_end_label_only.ys
2776s <<EOF:5: ERROR: Begin label (correct_name) and end label (incorrect_name) don't match.
2776s Expected error pattern 'Begin label \(correct_name\) and end label \(incorrect_name\) don't match\.' found !!!
2776s Passed gen_block_end_label_wrong.ys
2776s Passed genblk_case.ys
2776s <<EOT:4: ERROR: Cannot declare module port `\x' within a generate block.
2776s Expected error pattern 'Cannot declare module port `\\x' within a generate block\.' found !!!
2776s Passed genblk_port_decl.ys
2776s <<EOT:2: ERROR: Generate for loop variable declaration is missing initialization!
2776s Expected error pattern 'Generate for loop variable declaration is missing initialization!' found !!!
2776s Passed genfor_decl_no_init.ys
2776s <<EOT:2: ERROR: Generate for loop inline variable declaration is only supported in SystemVerilog mode!
2776s Expected error pattern 'Generate for loop inline variable declaration is only supported in SystemVerilog mode!' found !!!
2776s Passed genfor_decl_no_sv.ys
2776s Passed genvar_loop_decl_1.ys
2777s Passed genvar_loop_decl_2.ys
2777s Warning: reg '\y' is assigned in a continuous assignment at genvar_loop_decl_3.sv:13.12-13.21.
2777s Warning: reg '\y' is assigned in a continuous assignment at genvar_loop_decl_3.sv:27.12-27.21.
2777s Passed genvar_loop_decl_3.ys
2777s <<EOF:0: ERROR: Can't find object for defparam `$1`!
2777s Expected error pattern 'Can't find object for defparam' found !!!
2777s Passed global_parameter.ys
2777s <<EOT:7: ERROR: Identifier `\y' is implicitly declared and `default_nettype is set to none.
2777s Expected error pattern 'Identifier `\\y' is implicitly declared and `default_nettype is set to none' found !!!
2777s Passed hidden_decl.ys
2777s Passed ifdef_nest.ys
2777s ERROR: Unterminated preprocessor conditional!
2777s Expected error pattern 'Unterminated preprocessor conditional!' found !!!
2777s Passed ifdef_unterminated.ys
2777s Passed include_self.ys
2777s Passed int_types.ys
2777s <<EOF:3: ERROR: localparam initialization is missing!
2777s Expected error pattern 'localparam initialization is missing!' found !!!
2777s Passed localparam_no_default_1.ys
2777s <<EOF:2: ERROR: localparam initialization is missing!
2777s Expected error pattern 'localparam initialization is missing!' found !!!
2777s Passed localparam_no_default_2.ys
2777s Passed macro_arg_tromp.ys
2777s ERROR: Expected to find '(' to begin macro arguments for 'MACRO', but instead found ';'
2777s Expected error pattern 'Expected to find '\(' to begin macro arguments for 'MACRO', but instead found ';'' found !!!
2777s Passed macro_unapplied.ys
2777s ERROR: Expected to find '(' to begin macro arguments for 'foo', but instead found '\x0a'
2777s Expected error pattern 'Expected to find '\(' to begin macro arguments for 'foo', but instead found '\\x0a'' found !!!
2777s Passed macro_unapplied_newline.ys
2777s Passed mem_bounds.ys
2777s <<EOF:3: ERROR: Module name (correct_name) and end label (incorrect_name) don't match.
2777s Expected error pattern 'Module name \(correct_name\) and end label \(incorrect_name\) don't match\.' found !!!
2777s Passed module_end_label.ys
2777s Passed net_types.ys
2777s <<EOF:3: ERROR: Package name (correct_name) and end label (incorrect_name) don't match.
2777s Expected error pattern 'Package name \(correct_name\) and end label \(incorrect_name\) don't match\.' found !!!
2777s Passed package_end_label.ys
2777s Passed package_task_func.ys
2777s Passed param_int_types.ys
2778s Passed param_no_default.ys
2778s <<EOF:3: ERROR: Parameter defaults can only be omitted in SystemVerilog mode!
2778s Expected error pattern 'Parameter defaults can only be omitted in SystemVerilog mode!' found !!!
2778s Passed param_no_default_not_svmode.ys
2778s <<EOF:2: ERROR: Parameter `\X' has no default value and has not been overridden!
2778s Expected error pattern 'Parameter `\\X' has no default value and has not been overridden!' found !!!
2778s Passed param_no_default_unbound_1.ys
2778s <<EOF:2: ERROR: Parameter `\X' has no default value and has not been overridden!
2778s Expected error pattern 'Parameter `\\X' has no default value and has not been overridden!' found !!!
2778s Passed param_no_default_unbound_2.ys
2778s <<EOF:2: ERROR: Parameter `\Y' has no default value and has not been overridden!
2778s Expected error pattern 'Parameter `\\Y' has no default value and has not been overridden!' found !!!
2778s Passed param_no_default_unbound_3.ys
2778s <<EOF:2: ERROR: Parameter `\X' has no default value and has not been overridden!
2778s Expected error pattern 'Parameter `\\X' has no default value and has not been overridden!' found !!!
2778s Passed param_no_default_unbound_4.ys
2778s <<EOF:2: ERROR: Parameter `\X' has no default value and has not been overridden!
2778s Expected error pattern 'Parameter `\\X' has no default value and has not been overridden!' found !!!
2778s Passed param_no_default_unbound_5.ys
2778s Passed parameters_across_files.ys
2778s Passed past_signedness.ys
2778s Passed port_int_types.ys
2778s Passed prefix.ys
2778s Passed sign_array_query.ys
2778s Passed size_cast.ys
2778s Passed struct_access.ys
2778s <<EOT:6: ERROR: syntax error, unexpected ATTR_BEGIN
2778s Expected error pattern 'syntax error, unexpected ATTR_BEGIN' found !!!
2778s Passed task_attr.ys
2778s Passed typedef_across_files.ys
2778s Passed typedef_const_shadow.ys
2778s Passed typedef_legacy_conflict.ys
2778s Warning: Yosys has only limited support for tri-state logic at the moment. (unbased_unsized.sv:17)
2778s Warning: Yosys has only limited support for tri-state logic at the moment. (unbased_unsized.sv:21)
2778s Warning: Yosys has only limited support for tri-state logic at the moment. (unbased_unsized.sv:25)
2778s Warning: Yosys has only limited support for tri-state logic at the moment. (unbased_unsized.sv:30)
2778s Warning: Yosys has only limited support for tri-state logic at the moment. (unbased_unsized.sv:34)
2778s Warning: Yosys has only limited support for tri-state logic at the moment. (unbased_unsized.sv:38)
2778s Passed unbased_unsized.ys
2778s Warning: Resizing cell port top.pt.inp from 32 bits to 64 bits.
2778s Passed unbased_unsized_shift.ys
2778s Warning: Resizing cell port gate.pt4.out from 64 bits to 40 bits.
2778s Warning: Resizing cell port gate.pt3.out from 64 bits to 40 bits.
2778s Warning: Resizing cell port gate.pt2.out from 64 bits to 40 bits.
2778s Warning: Resizing cell port gate.pt1.out from 64 bits to 40 bits.
2778s Warning: Resizing cell port gold.pt4.out from 64 bits to 40 bits.
2778s Warning: Resizing cell port gold.pt3.out from 64 bits to 40 bits.
2778s Warning: Resizing cell port gold.pt2.out from 64 bits to 40 bits.
2778s Warning: Resizing cell port gold.pt1.out from 64 bits to 40 bits.
2779s Passed unbased_unsized_tern.ys
2779s ERROR: Found `else outside of macro conditional branch!
2779s Expected error pattern 'Found `else outside of macro conditional branch!' found !!!
2779s Passed unmatched_else.ys
2779s ERROR: Found `elsif outside of macro conditional branch!
2779s Expected error pattern 'Found `elsif outside of macro conditional branch!' found !!!
2779s Passed unmatched_elsif.ys
2779s ERROR: Found `endif outside of macro conditional branch!
2779s Expected error pattern 'Found `endif outside of macro conditional branch!' found !!!
2779s Passed unmatched_endif.ys
2779s ERROR: Found `endif outside of macro conditional branch!
2779s Expected error pattern 'Found `endif outside of macro conditional branch!' found !!!
2779s Passed unmatched_endif_2.ys
2779s <<EOT:3: ERROR: Local declaration in unnamed block is only supported in SystemVerilog mode!
2779s Expected error pattern 'Local declaration in unnamed block is only supported in SystemVerilog mode!' found !!!
2779s Passed unnamed_block.ys
2779s Passed unnamed_genblk.ys
2779s Passed unreachable_case_sign.ys
2779s Passed upto.ys
2779s Warning: wire '\b' is assigned in a block at <<EOF:2.38-2.43.
2779s Warning: wire '\b' is assigned in a block at <<EOF:3.42-3.48.
2779s Warning: wire '\b' is assigned in a block at <<EOF:12.29-12.34.
2779s Warning: wire '\b' is assigned in a block at <<EOF:13.33-13.39.
2779s Warning: wire '\b' is assigned in a block at <<EOF:23.9-23.14.
2779s Warning: wire '\b' is assigned in a block at <<EOF:24.9-24.15.
2779s Warning: wire '\b' is assigned in a block at <<EOF:25.9-25.15.
2779s Passed void_func.ys
2779s Warning: wire '\wire_1' is assigned in a block at wire_and_var.sv:21.41-21.51.
2779s Warning: reg '\reg_2' is assigned in a continuous assignment at wire_and_var.sv:22.57-22.66.
2779s Warning: reg '\var_reg_2' is assigned in a continuous assignment at wire_and_var.sv:26.77-26.90.
2779s Warning: wire '\wire_logic_1' is assigned in a block at wire_and_var.sv:30.65-30.81.
2779s Warning: wire '\wire_integer_1' is assigned in a block at wire_and_var.sv:31.73-31.91.
2779s Passed wire_and_var.ys
2802s Passed dynamic_range_lhs.sh
2802s make[1]: Leaving directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/verilog'
2802s cd tests/xprop && bash run-test.sh ""
2803s xprop PRNG seed: 364630872
2803s make[1]: Entering directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/xprop'
2803s xprop_not_3s_5: ok
2803s xprop_not_3s_5: ok
2804s xprop_pos_3s_5: ok
2804s xprop_pos_3s_5: ok
2805s xprop_neg_3s_5: ok
2805s xprop_neg_3s_5: ok
2805s xprop_and_1u1_1: ok
2805s xprop_and_1u1_1: ok
2806s xprop_and_1s1_2: ok
2806s xprop_and_1s1_2: ok
2807s xprop_and_2u2_2: ok
2807s xprop_and_2u2_2: ok
2807s xprop_or_1u1_1: ok
2807s xprop_or_1u1_1: ok
2808s xprop_or_1s1_2: ok
2808s xprop_or_1s1_2: ok
2809s xprop_or_2u2_2: ok
2809s xprop_or_2u2_2: ok
2809s xprop_xor_1u1_1: ok
2809s xprop_xor_1u1_1: ok
2810s xprop_xor_1s1_2: ok
2810s xprop_xor_1s1_2: ok
2811s xprop_xor_2u2_2: ok
2811s xprop_xor_2u2_2: ok
2811s xprop_xnor_1u1_1: ok
2811s xprop_xnor_1u1_1: ok
2813s xprop_xnor_1s1_2: ok
2813s xprop_xnor_1s1_2: ok
2813s xprop_xnor_2u2_2: ok
2813s xprop_xnor_2u2_2: ok
2814s xprop_add_5u3_3: ok
2814s xprop_add_5u3_3: ok
2815s xprop_add_5s3_3: ok
2815s xprop_add_5s3_3: ok
2815s xprop_sub_5u3_3: ok
2815s xprop_sub_5u3_3: ok
2816s xprop_sub_5s3_3: ok
2816s xprop_sub_5s3_3: ok
2819s xprop_mul_5u3_3: ok
2819s xprop_mul_5u3_3: ok
2819s xprop_mul_5s3_3: ok
2819s xprop_mul_5s3_3: ok
2819s xprop_div_5u3_3: ok
2819s xprop_div_5u3_3: ok
2820s xprop_div_5s3_3: ok
2820s xprop_div_5s3_3: ok
2822s xprop_mod_5u3_3: ok
2822s xprop_mod_5u3_3: ok
2824s xprop_mod_5s3_3: ok
2824s xprop_mod_5s3_3: ok
2824s xprop_divfloor_5u3_3: ok
2824s xprop_divfloor_5u3_3: ok
2825s xprop_divfloor_5s3_3: ok
2825s xprop_divfloor_5s3_3: ok
2826s xprop_modfloor_5u3_3: ok
2826s xprop_modfloor_5u3_3: ok
2827s xprop_modfloor_5s3_3: ok
2827s xprop_modfloor_5s3_3: ok
2828s xprop_lt_5u3_2: ok
2828s xprop_lt_5u3_2: ok
2829s xprop_lt_5s3_2: ok
2829s xprop_lt_5s3_2: ok
2830s xprop_le_5u3_2: ok
2830s xprop_le_5u3_2: ok
2831s xprop_le_5s3_2: ok
2831s xprop_le_5s3_2: ok
2832s xprop_eq_5u3_2: ok
2832s xprop_eq_5u3_2: ok
2832s xprop_eq_5s3_2: ok
2832s xprop_eq_5s3_2: ok
2833s xprop_ne_5u3_2: ok
2833s xprop_ne_5u3_2: ok
2834s xprop_ne_5s3_2: ok
2834s xprop_ne_5s3_2: ok
2835s xprop_eqx_5u3_2: ok
2835s xprop_eqx_5u3_2: ok
2836s xprop_eqx_5s3_2: ok
2836s xprop_eqx_5s3_2: ok
2837s xprop_nex_5u3_2: ok
2837s xprop_nex_5u3_2: ok
2837s xprop_nex_5s3_2: ok
2837s xprop_nex_5s3_2: ok
2838s xprop_ge_5u3_2: ok
2838s xprop_ge_5u3_2: ok
2839s xprop_ge_5s3_2: ok
2839s xprop_ge_5s3_2: ok
2840s xprop_gt_5u3_2: ok
2840s xprop_gt_5u3_2: ok
2841s xprop_gt_5s3_2: ok
2841s xprop_gt_5s3_2: ok
2841s xprop_reduce_and_3u_3: ok
2841s xprop_reduce_and_3u_3: ok
2842s xprop_reduce_and_3s_3: ok
2842s xprop_reduce_and_3s_3: ok
2843s xprop_reduce_or_3u_3: ok
2843s xprop_reduce_or_3u_3: ok
2843s xprop_reduce_or_3s_3: ok
2843s xprop_reduce_or_3s_3: ok
2844s xprop_reduce_xor_3u_3: ok
2844s xprop_reduce_xor_3u_3: ok
2845s xprop_reduce_xor_3s_3: ok
2845s xprop_reduce_xor_3s_3: ok
2846s xprop_reduce_xnor_3u_3: ok
2846s xprop_reduce_xnor_3u_3: ok
2846s xprop_reduce_xnor_3s_3: ok
2846s xprop_reduce_xnor_3s_3: ok
2847s xprop_reduce_bool_1u_1: ok
2847s xprop_reduce_bool_1u_1: ok
2848s xprop_reduce_bool_3u_3: ok
2848s xprop_reduce_bool_3u_3: ok
2848s xprop_reduce_bool_3s_3: ok
2848s xprop_reduce_bool_3s_3: ok
2849s xprop_reduce_bool_3s_1: ok
2849s xprop_reduce_bool_3s_1: ok
2850s xprop_logic_not_1u_1: ok
2850s xprop_logic_not_1u_1: ok
2850s xprop_logic_not_3u_3: ok
2850s xprop_logic_not_3u_3: ok
2851s xprop_logic_not_3s_3: ok
2851s xprop_logic_not_3s_3: ok
2852s xprop_logic_not_3s_1: ok
2852s xprop_logic_not_3s_1: ok
2852s xprop_logic_and_1u1_1: ok
2852s xprop_logic_and_1u1_1: ok
2853s xprop_logic_and_3u3_3: ok
2853s xprop_logic_and_3u3_3: ok
2854s xprop_logic_and_3s3_3: ok
2854s xprop_logic_and_3s3_3: ok
2855s xprop_logic_and_3s3_1: ok
2855s xprop_logic_and_3s3_1: ok
2855s xprop_logic_or_1u1_1: ok
2855s xprop_logic_or_1u1_1: ok
2856s xprop_logic_or_3u3_3: ok
2856s xprop_logic_or_3u3_3: ok
2857s xprop_logic_or_3s3_3: ok
2857s xprop_logic_or_3s3_3: ok
2858s xprop_logic_or_3s3_1: ok
2858s xprop_logic_or_3s3_1: ok
2858s xprop_shl_4u3u_3: ok
2858s xprop_shl_4u3u_3: ok
2859s xprop_shl_4s3u_3: ok
2859s xprop_shl_4s3u_3: ok
2860s xprop_shr_4u3u_3: ok
2860s xprop_shr_4u3u_3: ok
2861s xprop_shr_4s3u_3: ok
2861s xprop_shr_4s3u_3: ok
2862s xprop_sshl_4u3u_3: ok
2862s xprop_sshl_4u3u_3: ok
2863s xprop_sshl_4s3u_3: ok
2863s xprop_sshl_4s3u_3: ok
2864s xprop_sshr_4u3u_3: ok
2864s xprop_sshr_4u3u_3: ok
2865s xprop_sshr_4s3u_3: ok
2865s xprop_sshr_4s3u_3: ok
2866s xprop_shift_4u3u_3: ok
2866s xprop_shift_4u3u_3: ok
2867s xprop_shift_4s3u_3: ok
2867s xprop_shift_4s3u_3: ok
2868s xprop_shift_4u2s_8: ok
2868s xprop_shift_4u2s_8: ok
2870s xprop_shift_4s2s_8: ok
2870s xprop_shift_4s2s_8: ok
2871s xprop_shift_4u3s_3: ok
2871s xprop_shift_4u3s_3: ok
2872s xprop_shift_4s3s_3: ok
2872s xprop_shift_4s3s_3: ok
2873s xprop_shiftx_4u2s_8: ok
2873s xprop_shiftx_4u2s_8: ok
2874s xprop_shiftx_4u3s_3: ok
2874s xprop_shiftx_4u3s_3: ok
2875s xprop_mux_1: ok
2875s xprop_mux_1: ok
2876s xprop_mux_3: ok
2876s xprop_mux_3: ok
2876s xprop_bmux_1_2: ok
2876s xprop_bmux_1_2: ok
2878s xprop_bmux_2_2: ok
2878s xprop_bmux_2_2: ok
2879s xprop_bmux_3_1: ok
2879s xprop_bmux_3_1: ok
2880s xprop_demux_1_2: ok
2880s xprop_demux_1_2: ok
2882s xprop_demux_2_2: ok
2882s xprop_demux_2_2: ok
2883s xprop_demux_3_1: ok
2883s xprop_demux_3_1: ok
2884s xprop_pmux_1_4: ok
2884s xprop_pmux_1_4: ok
2885s xprop_pmux_2_2: ok
2885s xprop_pmux_2_2: ok
2885s xprop_pmux_3_1: ok
2885s xprop_pmux_3_1: ok
2887s xprop_pmux_4_4: ok
2887s xprop_pmux_4_4: ok
2888s xprop_bwmux_1: ok
2888s xprop_bwmux_1: ok
2889s xprop_bwmux_3: ok
2889s xprop_bwmux_3: ok
2889s xprop_bweqx_1: ok
2889s xprop_bweqx_1: ok
2890s xprop_bweqx_3: ok
2890s xprop_bweqx_3: ok
2891s xprop_ff_1: ok
2891s xprop_ff_1: ok
2892s xprop_ff_3: ok
2892s xprop_ff_3: ok
2893s xprop_dff_1pd: ok
2893s xprop_dff_1pd: ok
2894s xprop_dff_1nd: ok
2894s xprop_dff_1nd: ok
2895s xprop_dff_3pd: ok
2895s xprop_dff_3pd: ok
2896s xprop_dff_3nd: ok
2896s xprop_dff_3nd: ok
2897s xprop_dffe_1pnd: ok
2897s xprop_dffe_1pnd: ok
2898s xprop_dffe_1nnd: ok
2898s xprop_dffe_1nnd: ok
2899s xprop_dffe_3pnd: ok
2899s xprop_dffe_3pnd: ok
2901s xprop_dffe_3nnd: ok
2901s xprop_dffe_3nnd: ok
2902s xprop_dffe_1ppd: ok
2902s xprop_dffe_1ppd: ok
2903s xprop_dffe_1npd: ok
2903s xprop_dffe_1npd: ok
2904s xprop_dffe_3ppd: ok
2904s xprop_dffe_3ppd: ok
2906s xprop_dffe_3npd: ok
2906s xprop_dffe_3npd: ok
2906s done
2906s make[1]: Leaving directory '/tmp/autopkgtest.iWd4A5/build.UL3/src/tests/xprop'
2906s cd tests/fmt && bash run-test.sh
2906s + awk '/<<<BEGIN>>>/,/<<<END>>>/ {print $0}'
2906s + ../../yosys -p 'read_verilog initial_display.v'
2906s + iverilog -o iverilog-initial_display initial_display.v
2906s + ./iverilog-initial_display
2906s + diff yosys-initial_display.log iverilog-initial_display.log
2906s + test_always_display clk -DEVENT_CLK
2906s + local subtest=clk
2906s + shift
2906s + ../../yosys -p 'read_verilog -DEVENT_CLK always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk-1.v
2906s 
2906s  /----------------------------------------------------------------------------\
2906s  |                                                                            |
2906s  |  yosys -- Yosys Open SYnthesis Suite                                       |
2906s  |                                                                            |
2906s  |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
2906s  |                                                                            |
2906s  |  Permission to use, copy, modify, and/or distribute this software for any  |
2906s  |  purpose with or without fee is hereby granted, provided that the above    |
2906s  |  copyright notice and this permission notice appear in all copies.         |
2906s  |                                                                            |
2906s  |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
2906s  |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
2906s  |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
2906s  |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
2906s  |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
2906s  |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
2906s  |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
2906s  |                                                                            |
2906s  \----------------------------------------------------------------------------/
2906s 
2906s  Yosys 0.33 (git sha1 2584903a060)
2906s 
2906s 
2906s -- Running command `read_verilog -DEVENT_CLK always_display.v; proc; opt_expr -mux_bool; clean' --
2906s 
2906s 1. Executing Verilog-2005 frontend: always_display.v
2906s Parsing Verilog input from `always_display.v' to AST representation.
2906s Generating RTLIL representation for module `\m'.
2906s Successfully finished Verilog frontend.
2906s 
2906s 2. Executing PROC pass (convert processes to netlists).
2906s 
2906s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2906s Cleaned up 0 empty switches.
2906s 
2906s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
2906s Removed a total of 0 dead cases.
2906s 
2906s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
2906s Removed 1 redundant assignment.
2906s Promoted 1 assignment to connection.
2906s 
2906s 2.4. Executing PROC_INIT pass (extract init attributes).
2906s 
2906s 2.5. Executing PROC_ARST pass (detect async resets in processes).
2906s 
2906s 2.6. Executing PROC_ROM pass (convert switches to ROMs).
2906s Converted 0 switches.
2906s 
2906s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
2906s Creating decoders for process `\m.$proc$always_display.v:4$1'.
2906s 
2906s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2906s + ../../yosys -p 'read_verilog yosys-always_display-clk-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk-2.v
2906s 
2906s 2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2906s 
2906s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2906s 
2906s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2906s Removing empty process `m.$proc$always_display.v:4$1'.
2906s Cleaned up 0 empty switches.
2906s 
2906s 2.12. Executing OPT_EXPR pass (perform const folding).
2906s Optimizing module m.
2906s 
2906s 3. Executing OPT_EXPR pass (perform const folding).
2906s Optimizing module m.
2906s Removed 0 unused cells and 1 unused wires.
2906s 
2906s -- Writing to `yosys-always_display-clk-1.v' using backend `verilog' --
2906s 
2906s 4. Executing Verilog backend.
2906s 
2906s 4.1. Executing BMUXMAP pass.
2906s 
2906s 4.2. Executing DEMUXMAP pass.
2906s Dumping module `\m'.
2906s 
2906s End of script. Logfile hash: 0de35d2746, CPU: user 0.01s system 0.00s, MEM: 7.25 MB peak
2906s Yosys 0.33 (git sha1 2584903a060)
2906s Time spent: 31% 2x opt_expr (0 sec), 20% 1x clean (0 sec), ...
2906s 
2906s  /----------------------------------------------------------------------------\
2906s  |                                                                            |
2906s  |  yosys -- Yosys Open SYnthesis Suite                                       |
2906s  |                                                                            |
2906s  |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
2906s  |                                                                            |
2906s  |  Permission to use, copy, modify, and/or distribute this software for any  |
2906s  |  purpose with or without fee is hereby granted, provided that the above    |
2906s  |  copyright notice and this permission notice appear in all copies.         |
2906s  |                                                                            |
2906s  |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
2906s  |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
2906s  |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
2906s  |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
2906s  |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
2906s  |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
2906s  |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
2906s  |                                                                            |
2906s  \----------------------------------------------------------------------------/
2906s 
2906s  Yosys 0.33 (git sha1 2584903a060)
2906s 
2906s 
2906s -- Running command `read_verilog yosys-always_display-clk-1.v; proc; opt_expr -mux_bool; clean' --
2906s 
2906s 1. Executing Verilog-2005 frontend: yosys-always_display-clk-1.v
2906s Parsing Verilog input from `yosys-always_display-clk-1.v' to AST representation.
2906s Generating RTLIL representation for module `\m'.
2906s Successfully finished Verilog frontend.
2906s 
2906s 2. Executing PROC pass (convert processes to netlists).
2906s 
2906s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2906s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk-1.v:18$1'.
2906s Cleaned up 1 empty switch.
2906s 
2906s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
2906s Removed a total of 0 dead cases.
2906s 
2906s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
2906s Removed 1 redundant assignment.
2906s Promoted 1 assignment to connection.
2906s 
2906s 2.4. Executing PROC_INIT pass (extract init attributes).
2906s 
2906s 2.5. Executing PROC_ARST pass (detect async resets in processes).
2906s 
2906s 2.6. Executing PROC_ROM pass (convert switches to ROMs).
2906s Converted 0 switches.
2906s 
2906s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
2906s Creating decoders for process `\m.$proc$yosys-always_display-clk-1.v:18$1'.
2906s 
2906s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2906s 
2906s 2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2906s 
2906s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2906s 
2906s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2906s Removing empty process `m.$proc$yosys-always_display-clk-1.v:18$1'.
2906s Cleaned up 0 empty switches.
2906s 
2906s 2.12. Executing OPT_EXPR pass (perform const folding).
2906s + diff yosys-always_display-clk-1.v yosys-always_display-clk-2.v
2906s + test_always_display clk_rst -DEVENT_CLK_RST
2906s + local subtest=clk_rst
2906s + shift
2906s + ../../yosys -p 'read_verilog -DEVENT_CLK_RST always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst-1.v
2906s + ../../yosys -p 'read_verilog yosys-always_display-clk_rst-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst-2.v
2906s Optimizing module m.
2906s 
2906s 3. Executing OPT_EXPR pass (perform const folding).
2906s Optimizing module m.
2906s Removed 0 unused cells and 1 unused wires.
2906s 
2906s -- Writing to `yosys-always_display-clk-2.v' using backend `verilog' --
2906s 
2906s 4. Executing Verilog backend.
2906s 
2906s 4.1. Executing BMUXMAP pass.
2906s 
2906s 4.2. Executing DEMUXMAP pass.
2906s Dumping module `\m'.
2906s 
2906s End of script. Logfile hash: e35e8bb689, CPU: user 0.01s system 0.00s, MEM: 7.25 MB peak
2906s Yosys 0.33 (git sha1 2584903a060)
2906s Time spent: 33% 2x opt_expr (0 sec), 21% 1x clean (0 sec), ...
2906s 
2906s  /----------------------------------------------------------------------------\
2906s  |                                                                            |
2906s  |  yosys -- Yosys Open SYnthesis Suite                                       |
2906s  |                                                                            |
2906s  |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
2906s  |                                                                            |
2906s  |  Permission to use, copy, modify, and/or distribute this software for any  |
2906s  |  purpose with or without fee is hereby granted, provided that the above    |
2906s  |  copyright notice and this permission notice appear in all copies.         |
2906s  |                                                                            |
2906s  |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
2906s  |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
2906s  |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
2906s  |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
2906s  |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
2906s  |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
2906s  |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
2906s  |                                                                            |
2906s  \----------------------------------------------------------------------------/
2906s 
2906s  Yosys 0.33 (git sha1 2584903a060)
2906s 
2906s 
2906s -- Running command `read_verilog -DEVENT_CLK_RST always_display.v; proc; opt_expr -mux_bool; clean' --
2906s 
2906s 1. Executing Verilog-2005 frontend: always_display.v
2906s + diff yosys-always_display-clk_rst-1.v yosys-always_display-clk_rst-2.v
2906s + test_always_display star -DEVENT_STAR
2906s + local subtest=star
2906s + shift
2906s + ../../yosys -p 'read_verilog -DEVENT_STAR always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star-1.v
2906s Parsing Verilog input from `always_display.v' to AST representation.
2906s Generating RTLIL representation for module `\m'.
2906s Successfully finished Verilog frontend.
2906s 
2906s 2. Executing PROC pass (convert processes to netlists).
2906s 
2906s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2906s Cleaned up 0 empty switches.
2906s 
2906s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
2906s Removed a total of 0 dead cases.
2906s 
2906s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
2906s Removed 1 redundant assignment.
2906s Promoted 1 assignment to connection.
2906s 
2906s 2.4. Executing PROC_INIT pass (extract init attributes).
2906s 
2906s 2.5. Executing PROC_ARST pass (detect async resets in processes).
2906s 
2906s 2.6. Executing PROC_ROM pass (convert switches to ROMs).
2906s Converted 0 switches.
2906s 
2906s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
2906s Creating decoders for process `\m.$proc$always_display.v:7$1'.
2906s 
2906s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2906s 
2906s 2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2906s 
2906s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2906s 
2906s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2906s Removing empty process `m.$proc$always_display.v:7$1'.
2906s Cleaned up 0 empty switches.
2906s 
2906s 2.12. Executing OPT_EXPR pass (perform const folding).
2906s Optimizing module m.
2906s 
2906s 3. Executing OPT_EXPR pass (perform const folding).
2906s Optimizing module m.
2906s Removed 0 unused cells and 1 unused wires.
2906s 
2906s -- Writing to `yosys-always_display-clk_rst-1.v' using backend `verilog' --
2906s 
2906s 4. Executing Verilog backend.
2906s 
2906s 4.1. Executing BMUXMAP pass.
2906s 
2906s 4.2. Executing DEMUXMAP pass.
2906s Dumping module `\m'.
2906s 
2906s End of script. Logfile hash: c95608ddf0, CPU: user 0.01s system 0.00s, MEM: 7.25 MB peak
2906s Yosys 0.33 (git sha1 2584903a060)
2906s Time spent: 32% 2x opt_expr (0 sec), 26% 1x clean (0 sec), ...
2906s 
2906s  /----------------------------------------------------------------------------\
2906s  |                                                                            |
2906s  |  yosys -- Yosys Open SYnthesis Suite                                       |
2906s  |                                                                            |
2906s  |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
2906s  |                                                                            |
2906s  |  Permission to use, copy, modify, and/or distribute this software for any  |
2906s  |  purpose with or without fee is hereby granted, provided that the above    |
2906s  |  copyright notice and this permission notice appear in all copies.         |
2906s  |                                                                            |
2906s  |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
2906s  |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
2906s  |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
2906s  |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
2906s  |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
2906s  |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
2906s  |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
2906s  |                                                                            |
2906s  \----------------------------------------------------------------------------/
2906s 
2906s  Yosys 0.33 (git sha1 2584903a060)
2906s 
2906s 
2906s -- Running command `read_verilog yosys-always_display-clk_rst-1.v; proc; opt_expr -mux_bool; clean' --
2906s 
2906s 1. Executing Verilog-2005 frontend: yosys-always_display-clk_rst-1.v
2906s Parsing Verilog input from `yosys-always_display-clk_rst-1.v' to AST representation.
2906s Generating RTLIL representation for module `\m'.
2906s Successfully finished Verilog frontend.
2906s 
2906s 2. Executing PROC pass (convert processes to netlists).
2906s 
2906s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2906s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_rst-1.v:18$1'.
2906s Cleaned up 1 empty switch.
2906s 
2906s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
2906s Removed a total of 0 dead cases.
2906s 
2906s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
2906s Removed 1 redundant assignment.
2906s Promoted 1 assignment to connection.
2906s 
2906s 2.4. Executing PROC_INIT pass (extract init attributes).
2906s 
2906s 2.5. Executing PROC_ARST pass (detect async resets in processes).
2906s 
2906s 2.6. Executing PROC_ROM pass (convert switches to ROMs).
2906s Converted 0 switches.
2906s 
2906s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
2906s Creating decoders for process `\m.$proc$yosys-always_display-clk_rst-1.v:18$1'.
2906s 
2906s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2906s 
2906s 2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2906s 
2906s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2906s 
2906s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2906s Removing empty process `m.$proc$yosys-always_display-clk_rst-1.v:18$1'.
2906s Cleaned up 0 empty switches.
2906s 
2906s 2.12. Executing OPT_EXPR pass (perform const folding).
2906s Optimizing module m.
2906s 
2906s 3. Executing OPT_EXPR pass (perform const folding).
2906s Optimizing module m.
2906s Removed 0 unused cells and 1 unused wires.
2906s 
2906s -- Writing to `yosys-always_display-clk_rst-2.v' using backend `verilog' --
2906s 
2906s 4. Executing Verilog backend.
2906s 
2906s 4.1. Executing BMUXMAP pass.
2906s 
2906s 4.2. Executing DEMUXMAP pass.
2906s Dumping module `\m'.
2906s 
2906s End of script. Logfile hash: faf50513c3, CPU: user 0.01s system 0.00s, MEM: 7.25 MB peak
2906s Yosys 0.33 (git sha1 2584903a060)
2906s Time spent: 34% 2x opt_expr (0 sec), 21% 1x clean (0 sec), ...
2906s 
2906s  /----------------------------------------------------------------------------\
2906s  |                                                                            |
2906s  |  yosys -- Yosys Open SYnthesis Suite                                       |
2906s  |                                                                            |
2906s  |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
2906s  |                                                                            |
2906s  |  Permission to use, copy, modify, and/or distribute this software for any  |
2906s  |  purpose with or without fee is hereby granted, provided that the above    |
2906s  |  copyright notice and this permission notice appear in all copies.         |
2906s  |                                                                            |
2906s  |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
2906s  |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
2906s  |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
2906s  |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
2906s  |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
2906s  |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
2906s  |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
2906s  |                                                                            |
2906s  \----------------------------------------------------------------------------/
2906s 
2906s  Yosys 0.33 (git sha1 2584903a060)
2906s 
2906s 
2906s -- Running command `read_verilog -DEVENT_STAR always_display.v; proc; opt_expr -mux_bool; clean' --
2906s 
2906s 1. Executing Verilog-2005 frontend: always_display.v
2906s Parsing Verilog input from `always_display.v' to AST representation.
2906s Generating RTLIL representation for module `\m'.
2906s Successfully finished Verilog frontend.
2906s 
2906s 2. Executing PROC pass (convert processes to netlists).
2906s 
2906s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2906s Cleaned up 0 empty switches.
2906s 
2906s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
2906s Removed a total of 0 dead cases.
2906s 
2906s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
2906s Removed 1 redundant assignment.
2906s Promoted 1 assignment to connection.
2906s 
2906s 2.4. Executing PROC_INIT pass (extract init attributes).
2906s 
2906s 2.5. Executing PROC_ARST pass (detect async resets in processes).
2906s 
2906s 2.6. Executing PROC_ROM pass (convert switches to ROMs).
2906s Converted 0 switches.
2906s 
2906s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
2906s Creating decoders for process `\m.$proc$always_display.v:10$1'.
2906s 
2906s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2906s + ../../yosys -p 'read_verilog yosys-always_display-star-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star-2.v
2906s 
2906s 2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2906s 
2906s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2906s 
2906s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2906s Removing empty process `m.$proc$always_display.v:10$1'.
2906s Cleaned up 0 empty switches.
2906s 
2906s 2.12. Executing OPT_EXPR pass (perform const folding).
2906s Optimizing module m.
2906s 
2906s 3. Executing OPT_EXPR pass (perform const folding).
2906s Optimizing module m.
2906s Removed 0 unused cells and 1 unused wires.
2906s 
2906s -- Writing to `yosys-always_display-star-1.v' using backend `verilog' --
2906s 
2906s 4. Executing Verilog backend.
2906s 
2906s 4.1. Executing BMUXMAP pass.
2906s 
2906s 4.2. Executing DEMUXMAP pass.
2906s Dumping module `\m'.
2906s 
2906s End of script. Logfile hash: 7b2c5274a5, CPU: user 0.01s system 0.00s, MEM: 7.25 MB peak
2906s Yosys 0.33 (git sha1 2584903a060)
2906s Time spent: 35% 2x opt_expr (0 sec), 21% 1x clean (0 sec), ...
2906s 
2906s  /----------------------------------------------------------------------------\
2906s  |                                                                            |
2906s  |  yosys -- Yosys Open SYnthesis Suite                                       |
2906s  |                                                                            |
2906s  |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
2906s  |                                                                            |
2906s  |  Permission to use, copy, modify, and/or distribute this software for any  |
2906s  |  purpose with or without fee is hereby granted, provided that the above    |
2906s  |  copyright notice and this permission notice appear in all copies.         |
2906s  |                                                                            |
2906s  |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
2906s  |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
2906s  |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
2906s  |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
2906s  |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
2906s  |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
2906s  |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
2906s  |                                                                            |
2906s  \----------------------------------------------------------------------------/
2906s 
2906s  Yosys 0.33 (git sha1 2584903a060)
2906s 
2906s 
2906s -- Running command `read_verilog yosys-always_display-star-1.v; proc; opt_expr -mux_bool; clean' --
2906s 
2906s 1. Executing Verilog-2005 frontend: yosys-always_display-star-1.v
2906s Parsing Verilog input from `yosys-always_display-star-1.v' to AST representation.
2906s Generating RTLIL representation for module `\m'.
2906s Successfully finished Verilog frontend.
2906s 
2906s 2. Executing PROC pass (convert processes to netlists).
2906s 
2906s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2906s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-star-1.v:18$1'.
2906s Cleaned up 1 empty switch.
2906s 
2906s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
2906s Removed a total of 0 dead cases.
2906s 
2906s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
2906s Removed 1 redundant assignment.
2906s Promoted 1 assignment to connection.
2906s 
2906s 2.4. Executing PROC_INIT pass (extract init attributes).
2906s 
2906s 2.5. Executing PROC_ARST pass (detect async resets in processes).
2906s 
2906s 2.6. Executing PROC_ROM pass (convert switches to ROMs).
2906s Converted 0 switches.
2906s 
2906s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
2906s Creating decoders for process `\m.$proc$yosys-always_display-star-1.v:18$1'.
2906s 
2906s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2906s 
2906s 2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2906s 
2906s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2906s 
2906s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2906s Removing empty process `m.$proc$yosys-always_display-star-1.v:18$1'.
2906s Cleaned up 0 empty switches.
2906s 
2906s 2.12. Executing OPT_EXPR pass (perform const folding).
2906s Optimizing module m.
2906s 
2906s 3. Executing OPT_EXPR pass (perform const folding).
2906s Optimizing module m.
2906s Removed 0 unused cells and 1 unused wires.
2906s 
2906s -- Writing to `yosys-always_display-star-2.v' using backend `verilog' --
2906s 
2906s 4. Executing Verilog backend.
2906s 
2906s 4.1. Executing BMUXMAP pass.
2906s 
2906s 4.2. Executing DEMUXMAP pass.
2906s Dumping module `\m'.
2906s 
2906s End of script. Logfile hash: 8979c5de0b, CPU: user 0.01s system 0.00s, MEM: 7.25 MB peak
2906s Yosys 0.33 (git sha1 2584903a060)
2906s Time spent: 32% 2x opt_expr (0 sec), 21% 1x clean (0 sec), ...
2906s + diff yosys-always_display-star-1.v yosys-always_display-star-2.v
2906s + test_always_display clk_en -DEVENT_CLK -DCOND_EN
2906s + local subtest=clk_en
2906s + shift
2906s + ../../yosys -p 'read_verilog -DEVENT_CLK -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_en-1.v
2906s + ../../yosys -p 'read_verilog yosys-always_display-clk_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_en-2.v
2906s 
2906s  /----------------------------------------------------------------------------\
2906s  |                                                                            |
2906s  |  yosys -- Yosys Open SYnthesis Suite                                       |
2906s  |                                                                            |
2906s  |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
2906s  |                                                                            |
2906s  |  Permission to use, copy, modify, and/or distribute this software for any  |
2906s  |  purpose with or without fee is hereby granted, provided that the above    |
2906s  |  copyright notice and this permission notice appear in all copies.         |
2906s  |                                                                            |
2906s  |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
2906s  |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
2906s  |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
2906s  |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
2906s  |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
2906s  |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
2906s  |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
2906s  |                                                                            |
2906s  \----------------------------------------------------------------------------/
2906s 
2906s  Yosys 0.33 (git sha1 2584903a060)
2906s 
2906s 
2906s -- Running command `read_verilog -DEVENT_CLK -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' --
2906s 
2906s 1. Executing Verilog-2005 frontend: always_display.v
2906s Parsing Verilog input from `always_display.v' to AST representation.
2906s Generating RTLIL representation for module `\m'.
2906s Successfully finished Verilog frontend.
2906s 
2906s 2. Executing PROC pass (convert processes to netlists).
2906s 
2906s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2906s Cleaned up 0 empty switches.
2906s 
2906s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
2906s Removed a total of 0 dead cases.
2906s 
2906s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
2906s Removed 0 redundant assignments.
2906s Promoted 0 assignments to connections.
2906s 
2906s 2.4. Executing PROC_INIT pass (extract init attributes).
2906s 
2906s 2.5. Executing PROC_ARST pass (detect async resets in processes).
2906s 
2906s 2.6. Executing PROC_ROM pass (convert switches to ROMs).
2906s Converted 0 switches.
2906s <suppressed ~1 debug messages>
2906s 
2906s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
2906s Creating decoders for process `\m.$proc$always_display.v:4$1'.
2906s      1/1: $display$always_display.v:15$2_EN
2906s 
2906s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2906s 
2906s 2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2906s 
2906s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2906s 
2906s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2906s Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:4$1'.
2906s Removing empty process `m.$proc$always_display.v:4$1'.
2906s Cleaned up 1 empty switch.
2906s 
2906s 2.12. Executing OPT_EXPR pass (perform const folding).
2906s Optimizing module m.
2906s 
2906s 3. Executing OPT_EXPR pass (perform const folding).
2906s Optimizing module m.
2906s <suppressed ~1 debug messages>
2906s Removed 0 unused cells and 3 unused wires.
2906s 
2906s -- Writing to `yosys-always_display-clk_en-1.v' using backend `verilog' --
2906s 
2906s 4. Executing Verilog backend.
2906s 
2906s 4.1. Executing BMUXMAP pass.
2906s 
2906s 4.2. Executing DEMUXMAP pass.
2906s Dumping module `\m'.
2906s 
2906s End of script. Logfile hash: 4f8a3b339c, CPU: user 0.01s system 0.00s, MEM: 7.25 MB peak
2906s Yosys 0.33 (git sha1 2584903a060)
2906s Time spent: 36% 2x opt_expr (0 sec), 21% 1x clean (0 sec), ...
2906s + diff yosys-always_display-clk_en-1.v yosys-always_display-clk_en-2.v
2906s + test_always_display clk_rst_en -DEVENT_CLK_RST -DCOND_EN
2906s + local subtest=clk_rst_en
2906s + shift
2906s + ../../yosys -p 'read_verilog -DEVENT_CLK_RST -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst_en-1.v
2906s 
2906s  /----------------------------------------------------------------------------\
2906s  |                                                                            |
2906s  |  yosys -- Yosys Open SYnthesis Suite                                       |
2906s  |                                                                            |
2906s  |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
2906s  |                                                                            |
2906s  |  Permission to use, copy, modify, and/or distribute this software for any  |
2906s  |  purpose with or without fee is hereby granted, provided that the above    |
2906s  |  copyright notice and this permission notice appear in all copies.         |
2906s  |                                                                            |
2906s  |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
2906s  |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
2906s  |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
2906s  |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
2906s  |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
2906s  |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
2906s  |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
2906s  |                                                                            |
2906s  \----------------------------------------------------------------------------/
2906s 
2906s  Yosys 0.33 (git sha1 2584903a060)
2906s 
2906s 
2906s -- Running command `read_verilog yosys-always_display-clk_en-1.v; proc; opt_expr -mux_bool; clean' --
2906s 
2906s 1. Executing Verilog-2005 frontend: yosys-always_display-clk_en-1.v
2906s Parsing Verilog input from `yosys-always_display-clk_en-1.v' to AST representation.
2906s Generating RTLIL representation for module `\m'.
2906s Successfully finished Verilog frontend.
2906s 
2906s 2. Executing PROC pass (convert processes to netlists).
2906s 
2906s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2906s Cleaned up 0 empty switches.
2906s 
2906s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
2906s Removed a total of 0 dead cases.
2906s 
2906s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
2906s Removed 0 redundant assignments.
2906s Promoted 0 assignments to connections.
2906s 
2906s 2.4. Executing PROC_INIT pass (extract init attributes).
2906s 
2906s 2.5. Executing PROC_ARST pass (detect async resets in processes).
2906s 
2906s 2.6. Executing PROC_ROM pass (convert switches to ROMs).
2906s Converted 0 switches.
2906s <suppressed ~1 debug messages>
2906s 
2906s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
2906s Creating decoders for process `\m.$proc$yosys-always_display-clk_en-1.v:18$1'.
2906s      1/1: $write$yosys-always_display-clk_en-1.v:20$2_EN
2906s 
2906s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2906s 
2906s 2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2906s 
2906s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2906s 
2906s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2906s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_en-1.v:18$1'.
2906s Removing empty process `m.$proc$yosys-always_display-clk_en-1.v:18$1'.
2906s Cleaned up 1 empty switch.
2906s 
2906s 2.12. Executing OPT_EXPR pass (perform const folding).
2906s Optimizing module m.
2906s 
2906s 3. Executing OPT_EXPR pass (perform const folding).
2906s Optimizing module m.
2906s <suppressed ~1 debug messages>
2906s Removed 0 unused cells and 3 unused wires.
2906s 
2906s -- Writing to `yosys-always_display-clk_en-2.v' using backend `verilog' --
2906s 
2906s 4. Executing Verilog backend.
2906s 
2906s 4.1. Executing BMUXMAP pass.
2906s 
2906s 4.2. Executing DEMUXMAP pass.
2906s Dumping module `\m'.
2906s 
2906s End of script. Logfile hash: 51e7fa3902, CPU: user 0.01s system 0.00s, MEM: 7.38 MB peak
2906s Yosys 0.33 (git sha1 2584903a060)
2906s Time spent: 33% 2x opt_expr (0 sec), 19% 1x clean (0 sec), ...
2906s 
2906s  /----------------------------------------------------------------------------\
2906s  |                                                                            |
2906s  |  yosys -- Yosys Open SYnthesis Suite                                       |
2906s  |                                                                            |
2906s  |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
2906s  |                                                                            |
2906s  |  Permission to use, copy, modify, and/or distribute this software for any  |
2906s  |  purpose with or without fee is hereby granted, provided that the above    |
2906s  |  copyright notice and this permission notice appear in all copies.         |
2906s  |                                                                            |
2906s  |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
2906s  |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
2906s  |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
2906s  |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
2906s  |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
2906s  |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
2906s  |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
2906s  |                                                                            |
2906s  \----------------------------------------------------------------------------/
2906s 
2906s  Yosys 0.33 (git sha1 2584903a060)
2906s 
2906s 
2906s -- Running command `read_verilog -DEVENT_CLK_RST -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' --
2906s 
2906s 1. Executing Verilog-2005 frontend: always_display.v
2906s Parsing Verilog input from `always_display.v' to AST representation.
2906s Generating RTLIL representation for module `\m'.
2906s Successfully finished Verilog frontend.
2906s 
2906s 2. Executing PROC pass (convert processes to netlists).
2906s 
2906s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2906s Cleaned up 0 empty switches.
2906s 
2906s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
2906s Removed a total of 0 dead cases.
2906s 
2906s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
2906s Removed 0 redundant assignments.
2906s Promoted 0 assignments to connections.
2906s 
2906s 2.4. Executing PROC_INIT pass (extract init attributes).
2906s 
2906s 2.5. Executing PROC_ARST pass (detect async resets in processes).
2906s 
2906s 2.6. Executing PROC_ROM pass (convert switches to ROMs).
2906s Converted 0 switches.
2906s <suppressed ~1 debug messages>
2906s 
2906s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
2906s Creating decoders for process `\m.$proc$always_display.v:7$1'.
2906s      1/1: $display$always_display.v:15$2_EN
2906s 
2906s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2906s 
2906s 2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2906s 
2906s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2906s 
2906s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2906s Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:7$1'.
2906s Removing empty process `m.$proc$always_display.v:7$1'.
2906s Cleaned up 1 empty switch.
2906s 
2906s 2.12. Executing OPT_EXPR pass (perform const folding).
2906s Optimizing module m.
2906s 
2906s 3. Executing OPT_EXPR pass (perform const folding).
2906s Optimizing module m.
2906s <suppressed ~1 debug messages>
2906s Removed 0 unused cells and 3 unused wires.
2906s 
2906s -- Writing to `yosys-always_display-clk_rst_en-1.v' using backend `verilog' --
2906s 
2906s 4. Executing Verilog backend.
2906s 
2906s 4.1. Executing BMUXMAP pass.
2906s 
2906s 4.2. Executing DEMUXMAP pass.
2906s Dumping module `\m'.
2906s 
2906s End of script. Logfile hash: f9b4876f33, CPU: user 0.01s system 0.00s, MEM: 7.38 MB peak
2906s Yosys 0.33 (git sha1 2584903a060)
2906s Time spent: 36% 2x opt_expr (0 sec), 20% 1x clean (0 sec), ...
2906s + ../../yosys -p 'read_verilog yosys-always_display-clk_rst_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst_en-2.v
2906s 
2906s  /----------------------------------------------------------------------------\
2906s  |                                                                            |
2906s  |  yosys -- Yosys Open SYnthesis Suite                                       |
2906s  |                                                                            |
2906s  |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
2906s  |                                                                            |
2906s  |  Permission to use, copy, modify, and/or distribute this software for any  |
2906s  |  purpose with or without fee is hereby granted, provided that the above    |
2906s  |  copyright notice and this permission notice appear in all copies.         |
2906s  |                                                                            |
2906s  |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
2906s  |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
2906s  |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
2906s  |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
2906s  |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
2906s  |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
2906s  |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
2906s  |                                                                            |
2906s  \----------------------------------------------------------------------------/
2906s 
2906s  Yosys 0.33 (git sha1 2584903a060)
2906s 
2906s 
2906s -- Running command `read_verilog yosys-always_display-clk_rst_en-1.v; proc; opt_expr -mux_bool; clean' --
2906s 
2906s 1. Executing Verilog-2005 frontend: yosys-always_display-clk_rst_en-1.v
2906s Parsing Verilog input from `yosys-always_display-clk_rst_en-1.v' to AST representation.
2906s Generating RTLIL representation for module `\m'.
2906s Successfully finished Verilog frontend.
2906s 
2906s 2. Executing PROC pass (convert processes to netlists).
2906s 
2906s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2906s Cleaned up 0 empty switches.
2906s 
2906s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
2906s Removed a total of 0 dead cases.
2906s 
2906s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
2906s Removed 0 redundant assignments.
2906s Promoted 0 assignments to connections.
2906s 
2906s 2.4. Executing PROC_INIT pass (extract init attributes).
2906s 
2906s 2.5. Executing PROC_ARST pass (detect async resets in processes).
2906s 
2906s 2.6. Executing PROC_ROM pass (convert switches to ROMs).
2906s Converted 0 switches.
2906s <suppressed ~1 debug messages>
2906s 
2906s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
2906s Creating decoders for process `\m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'.
2906s      1/1: $write$yosys-always_display-clk_rst_en-1.v:20$2_EN
2906s 
2906s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2906s 
2906s 2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2906s 
2906s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2906s 
2906s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2906s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'.
2906s Removing empty process `m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'.
2906s Cleaned up 1 empty switch.
2906s 
2906s 2.12. Executing OPT_EXPR pass (perform const folding).
2906s Optimizing module m.
2906s 
2906s 3. Executing OPT_EXPR pass (perform const folding).
2906s Optimizing module m.
2906s <suppressed ~1 debug messages>
2906s Removed 0 unused cells and 3 unused wires.
2906s 
2906s -- Writing to `yosys-always_display-clk_rst_en-2.v' using backend `verilog' --
2906s 
2906s 4. Executing Verilog backend.
2906s 
2906s 4.1. Executing BMUXMAP pass.
2906s 
2906s 4.2. Executing DEMUXMAP pass.
2906s Dumping module `\m'.
2906s 
2906s End of script. Logfile hash: 0c4b4eaa9c, CPU: user 0.01s system 0.00s, MEM: 7.38 MB peak
2906s Yosys 0.33 (git sha1 2584903a060)
2906s Time spent: 34% 2x opt_expr (0 sec), 20% 1x clean (0 sec), ...
2906s + diff yosys-always_display-clk_rst_en-1.v yosys-always_display-clk_rst_en-2.v
2906s + test_always_display star_en -DEVENT_STAR -DCOND_EN
2906s + local subtest=star_en
2906s + shift
2906s + ../../yosys -p 'read_verilog -DEVENT_STAR -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star_en-1.v
2906s 
2906s  /----------------------------------------------------------------------------\
2906s  |                                                                            |
2906s  |  yosys -- Yosys Open SYnthesis Suite                                       |
2906s  |                                                                            |
2906s  |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
2906s  |                                                                            |
2906s  |  Permission to use, copy, modify, and/or distribute this software for any  |
2906s  |  purpose with or without fee is hereby granted, provided that the above    |
2906s  |  copyright notice and this permission notice appear in all copies.         |
2906s  |                                                                            |
2906s  |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
2906s  |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
2906s  |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
2906s  |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
2906s  |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
2906s  |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
2906s  |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
2906s  |                                                                            |
2906s  \----------------------------------------------------------------------------/
2906s 
2906s  Yosys 0.33 (git sha1 2584903a060)
2906s 
2906s 
2906s -- Running command `read_verilog -DEVENT_STAR -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' --
2906s 
2906s 1. Executing Verilog-2005 frontend: always_display.v
2906s Parsing Verilog input from `always_display.v' to AST representation.
2906s Generating RTLIL representation for module `\m'.
2906s Successfully finished Verilog frontend.
2906s 
2906s 2. Executing PROC pass (convert processes to netlists).
2906s 
2906s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2906s Cleaned up 0 empty switches.
2906s 
2906s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
2906s + ../../yosys -p 'read_verilog yosys-always_display-star_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star_en-2.v
2906s Removed a total of 0 dead cases.
2906s 
2906s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
2906s Removed 0 redundant assignments.
2906s Promoted 0 assignments to connections.
2906s 
2906s 2.4. Executing PROC_INIT pass (extract init attributes).
2906s 
2906s 2.5. Executing PROC_ARST pass (detect async resets in processes).
2906s 
2906s 2.6. Executing PROC_ROM pass (convert switches to ROMs).
2906s Converted 0 switches.
2906s <suppressed ~1 debug messages>
2906s 
2906s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
2906s Creating decoders for process `\m.$proc$always_display.v:10$1'.
2906s      1/1: $display$always_display.v:15$2_EN
2906s 
2906s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2906s 
2906s 2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2906s 
2906s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2906s 
2906s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2906s Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:10$1'.
2906s Removing empty process `m.$proc$always_display.v:10$1'.
2906s Cleaned up 1 empty switch.
2906s 
2906s 2.12. Executing OPT_EXPR pass (perform const folding).
2906s Optimizing module m.
2906s 
2906s 3. Executing OPT_EXPR pass (perform const folding).
2906s Optimizing module m.
2906s <suppressed ~1 debug messages>
2906s Removed 0 unused cells and 3 unused wires.
2906s 
2906s -- Writing to `yosys-always_display-star_en-1.v' using backend `verilog' --
2906s 
2906s 4. Executing Verilog backend.
2906s 
2906s 4.1. Executing BMUXMAP pass.
2906s 
2906s 4.2. Executing DEMUXMAP pass.
2906s Dumping module `\m'.
2906s 
2906s End of script. Logfile hash: d6a7335726, CPU: user 0.01s system 0.00s, MEM: 7.38 MB peak
2906s Yosys 0.33 (git sha1 2584903a060)
2906s Time spent: 34% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ...
2906s 
2906s  /----------------------------------------------------------------------------\
2906s  |                                                                            |
2906s  |  yosys -- Yosys Open SYnthesis Suite                                       |
2906s  |                                                                            |
2906s  |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
2906s  |                                                                            |
2906s  |  Permission to use, copy, modify, and/or distribute this software for any  |
2906s  |  purpose with or without fee is hereby granted, provided that the above    |
2906s  |  copyright notice and this permission notice appear in all copies.         |
2906s  |                                                                            |
2906s  |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
2906s  |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
2906s  |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
2906s  |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
2906s  |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
2906s  |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
2906s  |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
2906s  |                                                                            |
2906s  \----------------------------------------------------------------------------/
2906s 
2906s  Yosys 0.33 (git sha1 2584903a060)
2906s 
2906s 
2906s -- Running command `read_verilog yosys-always_display-star_en-1.v; proc; opt_expr -mux_bool; clean' --
2906s 
2906s 1. Executing Verilog-2005 frontend: yosys-always_display-star_en-1.v
2906s Parsing Verilog input from `yosys-always_display-star_en-1.v' to AST representation.
2906s Generating RTLIL representation for module `\m'.
2906s Successfully finished Verilog frontend.
2906s 
2906s 2. Executing PROC pass (convert processes to netlists).
2906s 
2906s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2906s Cleaned up 0 empty switches.
2906s 
2906s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
2906s Removed a total of 0 dead cases.
2906s 
2906s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
2906s Removed 0 redundant assignments.
2906s Promoted 0 assignments to connections.
2906s 
2906s 2.4. Executing PROC_INIT pass (extract init attributes).
2906s 
2906s 2.5. Executing PROC_ARST pass (detect async resets in processes).
2906s 
2906s 2.6. Executing PROC_ROM pass (convert switches to ROMs).
2906s Converted 0 switches.
2906s <suppressed ~1 debug messages>
2906s 
2906s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
2906s Creating decoders for process `\m.$proc$yosys-always_display-star_en-1.v:18$1'.
2906s      1/1: $write$yosys-always_display-star_en-1.v:20$2_EN
2906s 
2906s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2906s 
2906s 2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2906s 
2906s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2906s 
2906s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2906s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-star_en-1.v:18$1'.
2906s Removing empty process `m.$proc$yosys-always_display-star_en-1.v:18$1'.
2906s Cleaned up 1 empty switch.
2906s 
2906s 2.12. Executing OPT_EXPR pass (perform const folding).
2906s Optimizing module m.
2906s 
2906s 3. Executing OPT_EXPR pass (perform const folding).
2906s Optimizing module m.
2906s <suppressed ~1 debug messages>
2906s Removed 0 unused cells and 3 unused wires.
2906s 
2906s -- Writing to `yosys-always_display-star_en-2.v' using backend `verilog' --
2906s 
2906s 4. Executing Verilog backend.
2906s 
2906s 4.1. Executing BMUXMAP pass.
2906s 
2906s 4.2. Executing DEMUXMAP pass.
2906s Dumping module `\m'.
2906s 
2906s End of script. Logfile hash: 18895a2046, CPU: user 0.01s system 0.00s, MEM: 7.25 MB peak
2906s Yosys 0.33 (git sha1 2584903a060)
2906s Time spent: 33% 2x opt_expr (0 sec), 21% 1x clean (0 sec), ...
2906s + diff yosys-always_display-star_en-1.v yosys-always_display-star_en-2.v
2906s + test_roundtrip dec_unsigned -DBASE_DEC -DSIGN=
2906s + local subtest=dec_unsigned
2906s + shift
2906s + ../../yosys -p 'read_verilog -DBASE_DEC -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-dec_unsigned-1.v
2906s 
2906s  /----------------------------------------------------------------------------\
2906s  |                                                                            |
2906s  |  yosys -- Yosys Open SYnthesis Suite                                       |
2906s  |                                                                            |
2906s  |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
2906s  |                                                                            |
2906s  |  Permission to use, copy, modify, and/or distribute this software for any  |
2906s  |  purpose with or without fee is hereby granted, provided that the above    |
2906s  |  copyright notice and this permission notice appear in all copies.         |
2906s  |                                                                            |
2906s  |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
2906s  |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
2906s  |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
2906s  |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
2906s  |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
2906s  |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
2906s  |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
2906s  |                                                                            |
2906s  \----------------------------------------------------------------------------/
2906s 
2906s  Yosys 0.33 (git sha1 2584903a060)
2906s 
2906s 
2906s -- Running command `read_verilog -DBASE_DEC -DSIGN= roundtrip.v; proc; clean' --
2906s 
2906s 1. Executing Verilog-2005 frontend: roundtrip.v
2906s Parsing Verilog input from `roundtrip.v' to AST representation.
2906s Generating RTLIL representation for module `\m'.
2906s Successfully finished Verilog frontend.
2906s 
2906s 2. Executing PROC pass (convert processes to netlists).
2906s 
2906s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2906s Cleaned up 0 empty switches.
2906s 
2906s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
2906s Removed a total of 0 dead cases.
2906s 
2906s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
2906s Removed 1 redundant assignment.
2906s Promoted 1 assignment to connection.
2906s 
2906s 2.4. Executing PROC_INIT pass (extract init attributes).
2906s 
2906s 2.5. Executing PROC_ARST pass (detect async resets in processes).
2906s 
2906s 2.6. Executing PROC_ROM pass (convert switches to ROMs).
2906s Converted 0 switches.
2906s 
2906s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
2906s Creating decoders for process `\m.$proc$roundtrip.v:3$1'.
2906s 
2906s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2906s 
2906s 2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2906s 
2906s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2906s 
2906s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2906s Removing empty process `m.$proc$roundtrip.v:3$1'.
2906s Cleaned up 0 empty switches.
2906s 
2906s 2.12. Executing OPT_EXPR pass (perform const folding).
2906s Optimizing module m.
2906s Removed 0 unused cells and 1 unused wires.
2906s 
2906s -- Writing to `yosys-roundtrip-dec_unsigned-1.v' using backend `verilog' --
2906s 
2906s 3. Executing Verilog backend.
2906s 
2906s 3.1. Executing BMUXMAP pass.
2906s 
2906s 3.2. Executing DEMUXMAP pass.
2906s Dumping module `\m'.
2906s 
2906s End of script. Logfile hash: bfb187b86d, CPU: user 0.01s system 0.00s, MEM: 7.25 MB peak
2906s Yosys 0.33 (git sha1 2584903a060)
2906s Time spent: 26% 1x clean (0 sec), 18% 1x opt_expr (0 sec), ...
2906s + ../../yosys -p 'read_verilog yosys-roundtrip-dec_unsigned-1.v; proc; clean' -o yosys-roundtrip-dec_unsigned-2.v
2906s 
2906s  /----------------------------------------------------------------------------\
2906s  |                                                                            |
2906s  |  yosys -- Yosys Open SYnthesis Suite                                       |
2906s  |                                                                            |
2906s  |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
2906s  |                                                                            |
2906s  |  Permission to use, copy, modify, and/or distribute this software for any  |
2906s  |  purpose with or without fee is hereby granted, provided that the above    |
2906s  |  copyright notice and this permission notice appear in all copies.         |
2906s  |                                                                            |
2906s  |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
2906s  |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
2906s  |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
2906s  |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
2906s  |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
2906s  |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
2906s  |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
2906s  |                                                                            |
2906s  \----------------------------------------------------------------------------/
2906s 
2906s  Yosys 0.33 (git sha1 2584903a060)
2906s 
2906s 
2906s -- Running command `read_verilog yosys-roundtrip-dec_unsigned-1.v; proc; clean' --
2906s 
2906s 1. Executing Verilog-2005 frontend: yosys-roundtrip-dec_unsigned-1.v
2906s Parsing Verilog input from `yosys-roundtrip-dec_unsigned-1.v' to AST representation.
2906s Generating RTLIL representation for module `\m'.
2906s Successfully finished Verilog frontend.
2906s 
2906s 2. Executing PROC pass (convert processes to netlists).
2906s 
2906s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2906s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'.
2906s Cleaned up 1 empty switch.
2906s 
2906s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
2906s Removed a total of 0 dead cases.
2906s 
2906s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
2906s Removed 1 redundant assignment.
2906s Promoted 1 assignment to connection.
2906s 
2906s 2.4. Executing PROC_INIT pass (extract init attributes).
2906s 
2906s 2.5. Executing PROC_ARST pass (detect async resets in processes).
2906s 
2906s 2.6. Executing PROC_ROM pass (convert switches to ROMs).
2906s Converted 0 switches.
2906s 
2906s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
2906s Creating decoders for process `\m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'.
2906s 
2906s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2906s 
2906s 2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2906s 
2906s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2906s 
2906s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2906s Removing empty process `m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'.
2906s Cleaned up 0 empty switches.
2906s 
2906s 2.12. Executing OPT_EXPR pass (perform const folding).
2906s Optimizing module m.
2906s Removed 0 unused cells and 1 unused wires.
2906s 
2906s -- Writing to `yosys-roundtrip-dec_unsigned-2.v' using backend `verilog' --
2906s 
2906s 3. Executing Verilog backend.
2906s 
2906s 3.1. Executing BMUXMAP pass.
2906s 
2906s 3.2. Executing DEMUXMAP pass.
2906s Dumping module `\m'.
2906s 
2906s End of script. Logfile hash: 4be9539e85, CPU: user 0.01s system 0.01s, MEM: 7.25 MB peak
2906s Yosys 0.33 (git sha1 2584903a060)
2906s Time spent: 27% 1x clean (0 sec), 18% 2x read_verilog (0 sec), ...
2906s + diff yosys-roundtrip-dec_unsigned-1.v yosys-roundtrip-dec_unsigned-2.v
2906s + iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned roundtrip.v roundtrip_tb.v
2906s + ./iverilog-roundtrip-dec_unsigned
2906s + iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned-1 yosys-roundtrip-dec_unsigned-1.v roundtrip_tb.v
2906s + ./iverilog-roundtrip-dec_unsigned-1
2906s + iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned-2 yosys-roundtrip-dec_unsigned-2.v roundtrip_tb.v
2906s + ./iverilog-roundtrip-dec_unsigned-1
2906s + diff iverilog-roundtrip-dec_unsigned.log iverilog-roundtrip-dec_unsigned-1.log
2906s + diff iverilog-roundtrip-dec_unsigned-1.log iverilog-roundtrip-dec_unsigned-2.log
2906s + test_roundtrip dec_signed -DBASE_DEC -DSIGN=signed
2906s + local subtest=dec_signed
2906s + shift
2906s + ../../yosys -p 'read_verilog -DBASE_DEC -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-dec_signed-1.v
2906s 
2906s  /----------------------------------------------------------------------------\
2906s  |                                                                            |
2906s  |  yosys -- Yosys Open SYnthesis Suite                                       |
2906s  |                                                                            |
2906s  |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
2906s  |                                                                            |
2906s  |  Permission to use, copy, modify, and/or distribute this software for any  |
2906s  |  purpose with or without fee is hereby granted, provided that the above    |
2906s  |  copyright notice and this permission notice appear in all copies.         |
2906s  |                                                                            |
2906s  |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
2906s  |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
2906s  |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
2906s  |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
2906s  |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
2906s  |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
2906s  |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
2906s  |                                                                            |
2906s  \----------------------------------------------------------------------------/
2906s 
2906s  Yosys 0.33 (git sha1 2584903a060)
2906s 
2906s 
2906s -- Running command `read_verilog -DBASE_DEC -DSIGN=signed roundtrip.v; proc; clean' --
2906s 
2906s 1. Executing Verilog-2005 frontend: roundtrip.v
2906s Parsing Verilog input from `roundtrip.v' to AST representation.
2906s Generating RTLIL representation for module `\m'.
2906s Successfully finished Verilog frontend.
2906s 
2906s 2. Executing PROC pass (convert processes to netlists).
2906s 
2906s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2906s Cleaned up 0 empty switches.
2906s 
2906s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
2906s Removed a total of 0 dead cases.
2906s 
2906s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
2906s Removed 1 redundant assignment.
2906s Promoted 1 assignment to connection.
2906s 
2906s 2.4. Executing PROC_INIT pass (extract init attributes).
2906s 
2906s 2.5. Executing PROC_ARST pass (detect async resets in processes).
2906s 
2906s 2.6. Executing PROC_ROM pass (convert switches to ROMs).
2906s Converted 0 switches.
2906s 
2906s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
2906s Creating decoders for process `\m.$proc$roundtrip.v:3$1'.
2906s 
2906s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2906s 
2906s 2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2906s 
2906s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2906s 
2906s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2906s Removing empty process `m.$proc$roundtrip.v:3$1'.
2906s Cleaned up 0 empty switches.
2906s 
2906s 2.12. Executing OPT_EXPR pass (perform const folding).
2906s Optimizing module m.
2906s Removed 0 unused cells and 1 unused wires.
2906s 
2906s -- Writing to `yosys-roundtrip-dec_signed-1.v' using backend `verilog' --
2906s 
2906s 3. Executing Verilog backend.
2906s 
2906s 3.1. Executing BMUXMAP pass.
2906s 
2906s 3.2. Executing DEMUXMAP pass.
2906s Dumping module `\m'.
2906s 
2906s End of script. Logfile hash: bbdfa5ca92, CPU: user 0.00s system 0.01s, MEM: 7.25 MB peak
2906s Yosys 0.33 (git sha1 2584903a060)
2906s Time spent: 26% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ...
2906s + ../../yosys -p 'read_verilog yosys-roundtrip-dec_signed-1.v; proc; clean' -o yosys-roundtrip-dec_signed-2.v
2906s 
2906s  /----------------------------------------------------------------------------\
2906s  |                                                                            |
2906s  |  yosys -- Yosys Open SYnthesis Suite                                       |
2906s  |                                                                            |
2906s  |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
2906s  |                                                                            |
2906s  |  Permission to use, copy, modify, and/or distribute this software for any  |
2906s  |  purpose with or without fee is hereby granted, provided that the above    |
2906s  |  copyright notice and this permission notice appear in all copies.         |
2906s  |                                                                            |
2906s  |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
2906s  |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
2906s  |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
2906s  |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
2906s  |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
2906s  |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
2906s  |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
2906s  |                                                                            |
2906s  \----------------------------------------------------------------------------/
2906s 
2906s  Yosys 0.33 (git sha1 2584903a060)
2906s 
2906s 
2906s -- Running command `read_verilog yosys-roundtrip-dec_signed-1.v; proc; clean' --
2906s 
2906s 1. Executing Verilog-2005 frontend: yosys-roundtrip-dec_signed-1.v
2906s Parsing Verilog input from `yosys-roundtrip-dec_signed-1.v' to AST representation.
2906s Generating RTLIL representation for module `\m'.
2906s Successfully finished Verilog frontend.
2906s 
2906s 2. Executing PROC pass (convert processes to netlists).
2906s 
2906s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2906s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'.
2906s Cleaned up 1 empty switch.
2906s 
2906s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
2906s Removed a total of 0 dead cases.
2906s 
2906s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
2906s Removed 1 redundant assignment.
2906s Promoted 1 assignment to connection.
2906s 
2906s 2.4. Executing PROC_INIT pass (extract init attributes).
2906s 
2906s 2.5. Executing PROC_ARST pass (detect async resets in processes).
2906s 
2906s 2.6. Executing PROC_ROM pass (convert switches to ROMs).
2906s Converted 0 switches.
2906s 
2906s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
2906s Creating decoders for process `\m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'.
2906s 
2906s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2906s 
2906s 2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2906s 
2906s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2906s 
2906s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2906s Removing empty process `m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'.
2906s Cleaned up 0 empty switches.
2906s 
2906s 2.12. Executing OPT_EXPR pass (perform const folding).
2906s Optimizing module m.
2906s Removed 0 unused cells and 1 unused wires.
2906s 
2906s -- Writing to `yosys-roundtrip-dec_signed-2.v' using backend `verilog' --
2906s 
2906s 3. Executing Verilog backend.
2906s 
2906s 3.1. Executing BMUXMAP pass.
2906s 
2906s 3.2. Executing DEMUXMAP pass.
2906s Dumping module `\m'.
2906s 
2906s End of script. Logfile hash: b233de92a6, CPU: user 0.01s system 0.00s, MEM: 7.25 MB peak
2906s Yosys 0.33 (git sha1 2584903a060)
2906s Time spent: 22% 1x clean (0 sec), 20% 2x read_verilog (0 sec), ...
2906s + diff yosys-roundtrip-dec_signed-1.v yosys-roundtrip-dec_signed-2.v
2906s + iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed roundtrip.v roundtrip_tb.v
2906s + ./iverilog-roundtrip-dec_signed
2906s + iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed-1 yosys-roundtrip-dec_signed-1.v roundtrip_tb.v
2906s + ./iverilog-roundtrip-dec_signed-1
2906s + iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed-2 yosys-roundtrip-dec_signed-2.v roundtrip_tb.v
2906s + ./iverilog-roundtrip-dec_signed-1
2906s + diff iverilog-roundtrip-dec_signed.log iverilog-roundtrip-dec_signed-1.log
2906s + diff iverilog-roundtrip-dec_signed-1.log iverilog-roundtrip-dec_signed-2.log
2906s + test_roundtrip hex_unsigned -DBASE_HEX -DSIGN=
2906s + local subtest=hex_unsigned
2906s + shift
2906s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-hex_unsigned-1.v
2906s 
2906s  /----------------------------------------------------------------------------\
2906s  |                                                                            |
2906s  |  yosys -- Yosys Open SYnthesis Suite                                       |
2906s  |                                                                            |
2906s  |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
2906s  |                                                                            |
2906s  |  Permission to use, copy, modify, and/or distribute this software for any  |
2906s  |  purpose with or without fee is hereby granted, provided that the above    |
2906s  |  copyright notice and this permission notice appear in all copies.         |
2906s  |                                                                            |
2906s  |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
2906s  |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
2906s  |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
2906s  |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
2906s  |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
2906s  |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
2906s  |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
2906s  |                                                                            |
2906s  \----------------------------------------------------------------------------/
2906s 
2906s  Yosys 0.33 (git sha1 2584903a060)
2906s 
2906s 
2906s -- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' --
2906s 
2906s 1. Executing Verilog-2005 frontend: roundtrip.v
2906s Parsing Verilog input from `roundtrip.v' to AST representation.
2906s Generating RTLIL representation for module `\m'.
2906s Successfully finished Verilog frontend.
2906s 
2906s 2. Executing PROC pass (convert processes to netlists).
2906s 
2906s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2906s Cleaned up 0 empty switches.
2906s 
2906s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
2906s Removed a total of 0 dead cases.
2906s 
2906s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
2906s Removed 1 redundant assignment.
2906s Promoted 1 assignment to connection.
2906s 
2906s 2.4. Executing PROC_INIT pass (extract init attributes).
2906s 
2906s 2.5. Executing PROC_ARST pass (detect async resets in processes).
2906s 
2906s 2.6. Executing PROC_ROM pass (convert switches to ROMs).
2906s Converted 0 switches.
2906s 
2906s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
2906s Creating decoders for process `\m.$proc$roundtrip.v:3$1'.
2906s 
2906s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2906s 
2906s 2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2906s 
2906s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2906s 
2906s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2906s Removing empty process `m.$proc$roundtrip.v:3$1'.
2906s Cleaned up 0 empty switches.
2906s 
2906s 2.12. Executing OPT_EXPR pass (perform const folding).
2906s Optimizing module m.
2906s Removed 0 unused cells and 1 unused wires.
2906s 
2906s -- Writing to `yosys-roundtrip-hex_unsigned-1.v' using backend `verilog' --
2906s 
2906s 3. Executing Verilog backend.
2906s 
2906s 3.1. Executing BMUXMAP pass.
2906s 
2906s 3.2. Executing DEMUXMAP pass.
2906s Dumping module `\m'.
2906s 
2906s End of script. Logfile hash: 2377f2e106, CPU: user 0.01s system 0.00s, MEM: 7.25 MB peak
2906s Yosys 0.33 (git sha1 2584903a060)
2906s Time spent: 26% 1x clean (0 sec), 19% 1x opt_expr (0 sec), ...
2906s + ../../yosys -p 'read_verilog yosys-roundtrip-hex_unsigned-1.v; proc; clean' -o yosys-roundtrip-hex_unsigned-2.v
2906s 
2906s  /----------------------------------------------------------------------------\
2906s  |                                                                            |
2906s  |  yosys -- Yosys Open SYnthesis Suite                                       |
2906s  |                                                                            |
2906s  |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
2906s  |                                                                            |
2906s  |  Permission to use, copy, modify, and/or distribute this software for any  |
2906s  |  purpose with or without fee is hereby granted, provided that the above    |
2906s  |  copyright notice and this permission notice appear in all copies.         |
2906s  |                                                                            |
2906s  |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
2906s  |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
2906s  |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
2906s  |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
2906s  |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
2906s  |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
2906s  |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
2906s  |                                                                            |
2906s  \----------------------------------------------------------------------------/
2906s 
2906s  Yosys 0.33 (git sha1 2584903a060)
2906s 
2906s 
2906s -- Running command `read_verilog yosys-roundtrip-hex_unsigned-1.v; proc; clean' --
2906s 
2906s 1. Executing Verilog-2005 frontend: yosys-roundtrip-hex_unsigned-1.v
2906s Parsing Verilog input from `yosys-roundtrip-hex_unsigned-1.v' to AST representation.
2906s Generating RTLIL representation for module `\m'.
2906s Successfully finished Verilog frontend.
2906s 
2906s 2. Executing PROC pass (convert processes to netlists).
2906s 
2906s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2906s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'.
2906s Cleaned up 1 empty switch.
2906s 
2906s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
2906s Removed a total of 0 dead cases.
2906s 
2906s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
2906s Removed 1 redundant assignment.
2906s Promoted 1 assignment to connection.
2906s 
2906s 2.4. Executing PROC_INIT pass (extract init attributes).
2906s 
2906s 2.5. Executing PROC_ARST pass (detect async resets in processes).
2906s 
2906s 2.6. Executing PROC_ROM pass (convert switches to ROMs).
2906s Converted 0 switches.
2906s 
2906s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
2906s Creating decoders for process `\m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'.
2906s 
2906s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2906s 
2906s 2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2906s 
2906s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2906s 
2906s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2906s Removing empty process `m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'.
2906s Cleaned up 0 empty switches.
2906s 
2906s 2.12. Executing OPT_EXPR pass (perform const folding).
2906s Optimizing module m.
2906s Removed 0 unused cells and 1 unused wires.
2906s 
2906s -- Writing to `yosys-roundtrip-hex_unsigned-2.v' using backend `verilog' --
2906s 
2906s 3. Executing Verilog backend.
2906s 
2906s 3.1. Executing BMUXMAP pass.
2906s 
2906s 3.2. Executing DEMUXMAP pass.
2906s Dumping module `\m'.
2906s 
2906s End of script. Logfile hash: 06bfea69c8, CPU: user 0.01s system 0.00s, MEM: 7.25 MB peak
2906s Yosys 0.33 (git sha1 2584903a060)
2906s Time spent: 24% 1x clean (0 sec), 19% 1x opt_expr (0 sec), ...
2906s + diff yosys-roundtrip-hex_unsigned-1.v yosys-roundtrip-hex_unsigned-2.v
2906s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned roundtrip.v roundtrip_tb.v
2906s + ./iverilog-roundtrip-hex_unsigned
2906s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned-1 yosys-roundtrip-hex_unsigned-1.v roundtrip_tb.v
2906s + ./iverilog-roundtrip-hex_unsigned-1
2906s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned-2 yosys-roundtrip-hex_unsigned-2.v roundtrip_tb.v
2906s + ./iverilog-roundtrip-hex_unsigned-1
2906s + diff iverilog-roundtrip-hex_unsigned.log iverilog-roundtrip-hex_unsigned-1.log
2906s + diff iverilog-roundtrip-hex_unsigned-1.log iverilog-roundtrip-hex_unsigned-2.log
2906s + test_roundtrip hex_signed -DBASE_HEX -DSIGN=signed
2906s + local subtest=hex_signed
2906s + shift
2906s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-hex_signed-1.v
2906s 
2906s  /----------------------------------------------------------------------------\
2906s  |                                                                            |
2906s  |  yosys -- Yosys Open SYnthesis Suite                                       |
2906s  |                                                                            |
2906s  |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
2906s  |                                                                            |
2906s  |  Permission to use, copy, modify, and/or distribute this software for any  |
2906s  |  purpose with or without fee is hereby granted, provided that the above    |
2906s  |  copyright notice and this permission notice appear in all copies.         |
2906s  |                                                                            |
2906s  |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
2906s  |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
2906s  |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
2906s  |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
2906s  |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
2906s  |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
2906s  |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
2906s  |                                                                            |
2906s  \----------------------------------------------------------------------------/
2906s 
2906s  Yosys 0.33 (git sha1 2584903a060)
2906s 
2906s 
2906s -- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' --
2906s 
2906s 1. Executing Verilog-2005 frontend: roundtrip.v
2906s Parsing Verilog input from `roundtrip.v' to AST representation.
2906s Generating RTLIL representation for module `\m'.
2906s Successfully finished Verilog frontend.
2906s 
2906s 2. Executing PROC pass (convert processes to netlists).
2906s 
2906s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2906s Cleaned up 0 empty switches.
2906s 
2906s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
2906s Removed a total of 0 dead cases.
2906s 
2906s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
2906s Removed 1 redundant assignment.
2906s Promoted 1 assignment to connection.
2906s 
2906s 2.4. Executing PROC_INIT pass (extract init attributes).
2906s 
2906s 2.5. Executing PROC_ARST pass (detect async resets in processes).
2906s 
2906s 2.6. Executing PROC_ROM pass (convert switches to ROMs).
2906s Converted 0 switches.
2906s 
2906s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
2906s Creating decoders for process `\m.$proc$roundtrip.v:3$1'.
2906s 
2906s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2906s 
2906s 2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2906s 
2906s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2906s 
2906s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2906s Removing empty process `m.$proc$roundtrip.v:3$1'.
2906s Cleaned up 0 empty switches.
2906s 
2906s 2.12. Executing OPT_EXPR pass (perform const folding).
2906s Optimizing module m.
2906s Removed 0 unused cells and 1 unused wires.
2906s 
2906s -- Writing to `yosys-roundtrip-hex_signed-1.v' using backend `verilog' --
2906s 
2906s 3. Executing Verilog backend.
2906s 
2906s 3.1. Executing BMUXMAP pass.
2906s 
2906s 3.2. Executing DEMUXMAP pass.
2906s Dumping module `\m'.
2906s 
2906s End of script. Logfile hash: 824c3b1e65, CPU: user 0.01s system 0.00s, MEM: 7.25 MB peak
2906s Yosys 0.33 (git sha1 2584903a060)
2906s Time spent: 27% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ...
2906s + ../../yosys -p 'read_verilog yosys-roundtrip-hex_signed-1.v; proc; clean' -o yosys-roundtrip-hex_signed-2.v
2906s 
2906s  /----------------------------------------------------------------------------\
2906s  |                                                                            |
2906s  |  yosys -- Yosys Open SYnthesis Suite                                       |
2906s  |                                                                            |
2906s  |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
2906s  |                                                                            |
2906s  |  Permission to use, copy, modify, and/or distribute this software for any  |
2906s  |  purpose with or without fee is hereby granted, provided that the above    |
2906s  |  copyright notice and this permission notice appear in all copies.         |
2906s  |                                                                            |
2906s  |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
2906s  |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
2906s  |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
2906s  |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
2906s  |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
2906s  |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
2906s  |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
2906s  |                                                                            |
2906s  \----------------------------------------------------------------------------/
2906s 
2906s  Yosys 0.33 (git sha1 2584903a060)
2906s 
2906s 
2906s -- Running command `read_verilog yosys-roundtrip-hex_signed-1.v; proc; clean' --
2906s 
2906s 1. Executing Verilog-2005 frontend: yosys-roundtrip-hex_signed-1.v
2906s Parsing Verilog input from `yosys-roundtrip-hex_signed-1.v' to AST representation.
2906s Generating RTLIL representation for module `\m'.
2906s Successfully finished Verilog frontend.
2906s 
2906s 2. Executing PROC pass (convert processes to netlists).
2906s 
2906s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2906s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'.
2906s Cleaned up 1 empty switch.
2906s 
2906s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
2906s Removed a total of 0 dead cases.
2906s 
2906s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
2906s Removed 1 redundant assignment.
2906s Promoted 1 assignment to connection.
2906s 
2906s 2.4. Executing PROC_INIT pass (extract init attributes).
2906s 
2906s 2.5. Executing PROC_ARST pass (detect async resets in processes).
2906s 
2906s 2.6. Executing PROC_ROM pass (convert switches to ROMs).
2906s Converted 0 switches.
2906s 
2906s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
2906s Creating decoders for process `\m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'.
2906s 
2906s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2906s 
2906s 2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2906s 
2906s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2906s 
2906s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2906s Removing empty process `m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'.
2906s Cleaned up 0 empty switches.
2906s 
2906s 2.12. Executing OPT_EXPR pass (perform const folding).
2906s Optimizing module m.
2906s Removed 0 unused cells and 1 unused wires.
2906s 
2906s -- Writing to `yosys-roundtrip-hex_signed-2.v' using backend `verilog' --
2906s 
2906s 3. Executing Verilog backend.
2906s 
2906s 3.1. Executing BMUXMAP pass.
2906s 
2906s 3.2. Executing DEMUXMAP pass.
2906s Dumping module `\m'.
2906s 
2906s End of script. Logfile hash: f18b3fa15b, CPU: user 0.01s system 0.00s, MEM: 7.25 MB peak
2906s Yosys 0.33 (git sha1 2584903a060)
2906s Time spent: 26% 1x clean (0 sec), 19% 1x opt_expr (0 sec), ...
2906s + diff yosys-roundtrip-hex_signed-1.v yosys-roundtrip-hex_signed-2.v
2906s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed roundtrip.v roundtrip_tb.v
2906s + ./iverilog-roundtrip-hex_signed
2906s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed-1 yosys-roundtrip-hex_signed-1.v roundtrip_tb.v
2906s + ./iverilog-roundtrip-hex_signed-1
2906s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed-2 yosys-roundtrip-hex_signed-2.v roundtrip_tb.v
2906s + ./iverilog-roundtrip-hex_signed-1
2906s + diff iverilog-roundtrip-hex_signed.log iverilog-roundtrip-hex_signed-1.log
2906s + diff iverilog-roundtrip-hex_signed-1.log iverilog-roundtrip-hex_signed-2.log
2906s + test_roundtrip oct_unsigned -DBASE_HEX -DSIGN=
2906s + local subtest=oct_unsigned
2906s + shift
2906s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-oct_unsigned-1.v
2906s 
2906s  /----------------------------------------------------------------------------\
2906s  |                                                                            |
2906s  |  yosys -- Yosys Open SYnthesis Suite                                       |
2906s  |                                                                            |
2906s  |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
2906s  |                                                                            |
2906s  |  Permission to use, copy, modify, and/or distribute this software for any  |
2906s  |  purpose with or without fee is hereby granted, provided that the above    |
2906s  |  copyright notice and this permission notice appear in all copies.         |
2906s  |                                                                            |
2906s  |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
2906s  |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
2906s  |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
2906s  |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
2906s  |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
2906s  |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
2906s  |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
2906s  |                                                                            |
2906s  \----------------------------------------------------------------------------/
2906s 
2906s  Yosys 0.33 (git sha1 2584903a060)
2906s 
2906s 
2906s -- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' --
2906s 
2906s 1. Executing Verilog-2005 frontend: roundtrip.v
2906s Parsing Verilog input from `roundtrip.v' to AST representation.
2906s Generating RTLIL representation for module `\m'.
2906s Successfully finished Verilog frontend.
2906s 
2906s 2. Executing PROC pass (convert processes to netlists).
2906s 
2906s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2906s Cleaned up 0 empty switches.
2906s 
2906s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
2906s Removed a total of 0 dead cases.
2906s 
2906s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
2906s Removed 1 redundant assignment.
2906s Promoted 1 assignment to connection.
2906s 
2906s 2.4. Executing PROC_INIT pass (extract init attributes).
2906s 
2906s 2.5. Executing PROC_ARST pass (detect async resets in processes).
2906s 
2906s 2.6. Executing PROC_ROM pass (convert switches to ROMs).
2906s Converted 0 switches.
2906s 
2906s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
2906s Creating decoders for process `\m.$proc$roundtrip.v:3$1'.
2906s 
2906s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2906s 
2906s 2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2906s 
2906s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2906s 
2906s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2906s Removing empty process `m.$proc$roundtrip.v:3$1'.
2906s Cleaned up 0 empty switches.
2906s 
2906s 2.12. Executing OPT_EXPR pass (perform const folding).
2906s Optimizing module m.
2906s Removed 0 unused cells and 1 unused wires.
2906s 
2906s -- Writing to `yosys-roundtrip-oct_unsigned-1.v' using backend `verilog' --
2906s 
2906s 3. Executing Verilog backend.
2906s 
2906s 3.1. Executing BMUXMAP pass.
2906s 
2906s 3.2. Executing DEMUXMAP pass.
2906s Dumping module `\m'.
2906s 
2906s End of script. Logfile hash: b768358a65, CPU: user 0.01s system 0.00s, MEM: 7.25 MB peak
2906s Yosys 0.33 (git sha1 2584903a060)
2906s Time spent: 26% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ...
2906s + ../../yosys -p 'read_verilog yosys-roundtrip-oct_unsigned-1.v; proc; clean' -o yosys-roundtrip-oct_unsigned-2.v
2906s 
2906s  /----------------------------------------------------------------------------\
2906s  |                                                                            |
2906s  |  yosys -- Yosys Open SYnthesis Suite                                       |
2906s  |                                                                            |
2906s  |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
2906s  |                                                                            |
2906s  |  Permission to use, copy, modify, and/or distribute this software for any  |
2906s  |  purpose with or without fee is hereby granted, provided that the above    |
2906s  |  copyright notice and this permission notice appear in all copies.         |
2906s  |                                                                            |
2906s  |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
2906s  |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
2906s  |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
2906s  |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
2906s  |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
2906s  |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
2906s  |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
2906s  |                                                                            |
2906s  \----------------------------------------------------------------------------/
2906s 
2906s  Yosys 0.33 (git sha1 2584903a060)
2906s 
2906s 
2906s -- Running command `read_verilog yosys-roundtrip-oct_unsigned-1.v; proc; clean' --
2906s 
2906s 1. Executing Verilog-2005 frontend: yosys-roundtrip-oct_unsigned-1.v
2906s Parsing Verilog input from `yosys-roundtrip-oct_unsigned-1.v' to AST representation.
2906s Generating RTLIL representation for module `\m'.
2906s Successfully finished Verilog frontend.
2906s 
2906s 2. Executing PROC pass (convert processes to netlists).
2906s 
2906s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2906s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'.
2906s Cleaned up 1 empty switch.
2906s 
2906s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
2906s Removed a total of 0 dead cases.
2906s 
2906s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
2906s Removed 1 redundant assignment.
2906s Promoted 1 assignment to connection.
2906s 
2906s 2.4. Executing PROC_INIT pass (extract init attributes).
2906s 
2906s 2.5. Executing PROC_ARST pass (detect async resets in processes).
2906s 
2906s 2.6. Executing PROC_ROM pass (convert switches to ROMs).
2906s Converted 0 switches.
2906s 
2906s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
2906s Creating decoders for process `\m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'.
2906s 
2906s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2906s 
2906s 2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2906s 
2906s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2906s 
2906s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2906s Removing empty process `m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'.
2906s Cleaned up 0 empty switches.
2906s 
2906s 2.12. Executing OPT_EXPR pass (perform const folding).
2906s Optimizing module m.
2906s Removed 0 unused cells and 1 unused wires.
2906s 
2906s -- Writing to `yosys-roundtrip-oct_unsigned-2.v' using backend `verilog' --
2906s 
2906s 3. Executing Verilog backend.
2906s 
2906s 3.1. Executing BMUXMAP pass.
2906s 
2906s 3.2. Executing DEMUXMAP pass.
2906s Dumping module `\m'.
2906s 
2906s End of script. Logfile hash: 762621cd95, CPU: user 0.01s system 0.00s, MEM: 7.38 MB peak
2906s Yosys 0.33 (git sha1 2584903a060)
2906s Time spent: 26% 1x clean (0 sec), 19% 1x opt_expr (0 sec), ...
2906s + diff yosys-roundtrip-oct_unsigned-1.v yosys-roundtrip-oct_unsigned-2.v
2906s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned roundtrip.v roundtrip_tb.v
2906s + ./iverilog-roundtrip-oct_unsigned
2907s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned-1 yosys-roundtrip-oct_unsigned-1.v roundtrip_tb.v
2907s + ./iverilog-roundtrip-oct_unsigned-1
2907s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned-2 yosys-roundtrip-oct_unsigned-2.v roundtrip_tb.v
2907s + ./iverilog-roundtrip-oct_unsigned-1
2907s + diff iverilog-roundtrip-oct_unsigned.log iverilog-roundtrip-oct_unsigned-1.log
2907s + diff iverilog-roundtrip-oct_unsigned-1.log iverilog-roundtrip-oct_unsigned-2.log
2907s + test_roundtrip oct_signed -DBASE_HEX -DSIGN=signed
2907s + local subtest=oct_signed
2907s + shift
2907s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-oct_signed-1.v
2907s 
2907s  /----------------------------------------------------------------------------\
2907s  |                                                                            |
2907s  |  yosys -- Yosys Open SYnthesis Suite                                       |
2907s  |                                                                            |
2907s  |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
2907s  |                                                                            |
2907s  |  Permission to use, copy, modify, and/or distribute this software for any  |
2907s  |  purpose with or without fee is hereby granted, provided that the above    |
2907s  |  copyright notice and this permission notice appear in all copies.         |
2907s  |                                                                            |
2907s  |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
2907s  |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
2907s  |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
2907s  |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
2907s  |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
2907s  |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
2907s  |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
2907s  |                                                                            |
2907s  \----------------------------------------------------------------------------/
2907s 
2907s  Yosys 0.33 (git sha1 2584903a060)
2907s 
2907s 
2907s -- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' --
2907s 
2907s 1. Executing Verilog-2005 frontend: roundtrip.v
2907s Parsing Verilog input from `roundtrip.v' to AST representation.
2907s Generating RTLIL representation for module `\m'.
2907s Successfully finished Verilog frontend.
2907s 
2907s 2. Executing PROC pass (convert processes to netlists).
2907s 
2907s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2907s Cleaned up 0 empty switches.
2907s 
2907s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
2907s Removed a total of 0 dead cases.
2907s 
2907s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
2907s Removed 1 redundant assignment.
2907s Promoted 1 assignment to connection.
2907s 
2907s 2.4. Executing PROC_INIT pass (extract init attributes).
2907s 
2907s 2.5. Executing PROC_ARST pass (detect async resets in processes).
2907s 
2907s 2.6. Executing PROC_ROM pass (convert switches to ROMs).
2907s Converted 0 switches.
2907s 
2907s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
2907s Creating decoders for process `\m.$proc$roundtrip.v:3$1'.
2907s 
2907s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2907s 
2907s 2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2907s 
2907s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2907s 
2907s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2907s Removing empty process `m.$proc$roundtrip.v:3$1'.
2907s Cleaned up 0 empty switches.
2907s 
2907s 2.12. Executing OPT_EXPR pass (perform const folding).
2907s Optimizing module m.
2907s Removed 0 unused cells and 1 unused wires.
2907s 
2907s -- Writing to `yosys-roundtrip-oct_signed-1.v' using backend `verilog' --
2907s 
2907s 3. Executing Verilog backend.
2907s 
2907s 3.1. Executing BMUXMAP pass.
2907s 
2907s 3.2. Executing DEMUXMAP pass.
2907s Dumping module `\m'.
2907s 
2907s End of script. Logfile hash: 7ec82b15e3, CPU: user 0.01s system 0.00s, MEM: 7.25 MB peak
2907s Yosys 0.33 (git sha1 2584903a060)
2907s Time spent: 26% 1x clean (0 sec), 19% 1x opt_expr (0 sec), ...
2907s + ../../yosys -p 'read_verilog yosys-roundtrip-oct_signed-1.v; proc; clean' -o yosys-roundtrip-oct_signed-2.v
2907s 
2907s  /----------------------------------------------------------------------------\
2907s  |                                                                            |
2907s  |  yosys -- Yosys Open SYnthesis Suite                                       |
2907s  |                                                                            |
2907s  |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
2907s  |                                                                            |
2907s  |  Permission to use, copy, modify, and/or distribute this software for any  |
2907s  |  purpose with or without fee is hereby granted, provided that the above    |
2907s  |  copyright notice and this permission notice appear in all copies.         |
2907s  |                                                                            |
2907s  |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
2907s  |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
2907s  |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
2907s  |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
2907s  |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
2907s  |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
2907s  |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
2907s  |                                                                            |
2907s  \----------------------------------------------------------------------------/
2907s 
2907s  Yosys 0.33 (git sha1 2584903a060)
2907s 
2907s 
2907s -- Running command `read_verilog yosys-roundtrip-oct_signed-1.v; proc; clean' --
2907s 
2907s 1. Executing Verilog-2005 frontend: yosys-roundtrip-oct_signed-1.v
2907s Parsing Verilog input from `yosys-roundtrip-oct_signed-1.v' to AST representation.
2907s Generating RTLIL representation for module `\m'.
2907s Successfully finished Verilog frontend.
2907s 
2907s 2. Executing PROC pass (convert processes to netlists).
2907s 
2907s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2907s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'.
2907s Cleaned up 1 empty switch.
2907s 
2907s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
2907s Removed a total of 0 dead cases.
2907s 
2907s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
2907s Removed 1 redundant assignment.
2907s Promoted 1 assignment to connection.
2907s 
2907s 2.4. Executing PROC_INIT pass (extract init attributes).
2907s 
2907s 2.5. Executing PROC_ARST pass (detect async resets in processes).
2907s 
2907s 2.6. Executing PROC_ROM pass (convert switches to ROMs).
2907s Converted 0 switches.
2907s 
2907s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
2907s Creating decoders for process `\m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'.
2907s 
2907s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2907s 
2907s 2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2907s 
2907s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2907s 
2907s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2907s Removing empty process `m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'.
2907s Cleaned up 0 empty switches.
2907s 
2907s 2.12. Executing OPT_EXPR pass (perform const folding).
2907s Optimizing module m.
2907s Removed 0 unused cells and 1 unused wires.
2907s 
2907s -- Writing to `yosys-roundtrip-oct_signed-2.v' using backend `verilog' --
2907s 
2907s 3. Executing Verilog backend.
2907s 
2907s 3.1. Executing BMUXMAP pass.
2907s 
2907s 3.2. Executing DEMUXMAP pass.
2907s Dumping module `\m'.
2907s 
2907s End of script. Logfile hash: a747b9bd4f, CPU: user 0.01s system 0.01s, MEM: 7.25 MB peak
2907s Yosys 0.33 (git sha1 2584903a060)
2907s Time spent: 26% 1x clean (0 sec), 18% 1x opt_expr (0 sec), ...
2907s + diff yosys-roundtrip-oct_signed-1.v yosys-roundtrip-oct_signed-2.v
2907s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed roundtrip.v roundtrip_tb.v
2907s + ./iverilog-roundtrip-oct_signed
2907s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed-1 yosys-roundtrip-oct_signed-1.v roundtrip_tb.v
2907s + ./iverilog-roundtrip-oct_signed-1
2907s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed-2 yosys-roundtrip-oct_signed-2.v roundtrip_tb.v
2907s + ./iverilog-roundtrip-oct_signed-1
2907s + diff iverilog-roundtrip-oct_signed.log iverilog-roundtrip-oct_signed-1.log
2907s + diff iverilog-roundtrip-oct_signed-1.log iverilog-roundtrip-oct_signed-2.log
2907s + test_roundtrip bin_unsigned -DBASE_HEX -DSIGN=
2907s + local subtest=bin_unsigned
2907s + shift
2907s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-bin_unsigned-1.v
2907s 
2907s  /----------------------------------------------------------------------------\
2907s  |                                                                            |
2907s  |  yosys -- Yosys Open SYnthesis Suite                                       |
2907s  |                                                                            |
2907s  |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
2907s  |                                                                            |
2907s  |  Permission to use, copy, modify, and/or distribute this software for any  |
2907s  |  purpose with or without fee is hereby granted, provided that the above    |
2907s  |  copyright notice and this permission notice appear in all copies.         |
2907s  |                                                                            |
2907s  |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
2907s  |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
2907s  |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
2907s  |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
2907s  |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
2907s  |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
2907s  |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
2907s  |                                                                            |
2907s  \----------------------------------------------------------------------------/
2907s 
2907s  Yosys 0.33 (git sha1 2584903a060)
2907s 
2907s 
2907s -- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' --
2907s 
2907s 1. Executing Verilog-2005 frontend: roundtrip.v
2907s Parsing Verilog input from `roundtrip.v' to AST representation.
2907s Generating RTLIL representation for module `\m'.
2907s Successfully finished Verilog frontend.
2907s 
2907s 2. Executing PROC pass (convert processes to netlists).
2907s 
2907s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2907s Cleaned up 0 empty switches.
2907s 
2907s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
2907s Removed a total of 0 dead cases.
2907s 
2907s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
2907s Removed 1 redundant assignment.
2907s Promoted 1 assignment to connection.
2907s 
2907s 2.4. Executing PROC_INIT pass (extract init attributes).
2907s 
2907s 2.5. Executing PROC_ARST pass (detect async resets in processes).
2907s 
2907s 2.6. Executing PROC_ROM pass (convert switches to ROMs).
2907s Converted 0 switches.
2907s 
2907s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
2907s Creating decoders for process `\m.$proc$roundtrip.v:3$1'.
2907s 
2907s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2907s 
2907s 2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2907s 
2907s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2907s 
2907s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2907s Removing empty process `m.$proc$roundtrip.v:3$1'.
2907s Cleaned up 0 empty switches.
2907s 
2907s 2.12. Executing OPT_EXPR pass (perform const folding).
2907s Optimizing module m.
2907s Removed 0 unused cells and 1 unused wires.
2907s 
2907s -- Writing to `yosys-roundtrip-bin_unsigned-1.v' using backend `verilog' --
2907s 
2907s 3. Executing Verilog backend.
2907s 
2907s 3.1. Executing BMUXMAP pass.
2907s 
2907s 3.2. Executing DEMUXMAP pass.
2907s Dumping module `\m'.
2907s 
2907s End of script. Logfile hash: 270b564880, CPU: user 0.01s system 0.00s, MEM: 7.25 MB peak
2907s Yosys 0.33 (git sha1 2584903a060)
2907s Time spent: 26% 1x clean (0 sec), 19% 1x opt_expr (0 sec), ...
2907s + ../../yosys -p 'read_verilog yosys-roundtrip-bin_unsigned-1.v; proc; clean' -o yosys-roundtrip-bin_unsigned-2.v
2907s 
2907s  /----------------------------------------------------------------------------\
2907s  |                                                                            |
2907s  |  yosys -- Yosys Open SYnthesis Suite                                       |
2907s  |                                                                            |
2907s  |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
2907s  |                                                                            |
2907s  |  Permission to use, copy, modify, and/or distribute this software for any  |
2907s  |  purpose with or without fee is hereby granted, provided that the above    |
2907s  |  copyright notice and this permission notice appear in all copies.         |
2907s  |                                                                            |
2907s  |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
2907s  |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
2907s  |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
2907s  |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
2907s  |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
2907s  |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
2907s  |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
2907s  |                                                                            |
2907s  \----------------------------------------------------------------------------/
2907s 
2907s  Yosys 0.33 (git sha1 2584903a060)
2907s 
2907s 
2907s -- Running command `read_verilog yosys-roundtrip-bin_unsigned-1.v; proc; clean' --
2907s 
2907s 1. Executing Verilog-2005 frontend: yosys-roundtrip-bin_unsigned-1.v
2907s Parsing Verilog input from `yosys-roundtrip-bin_unsigned-1.v' to AST representation.
2907s Generating RTLIL representation for module `\m'.
2907s Successfully finished Verilog frontend.
2907s 
2907s 2. Executing PROC pass (convert processes to netlists).
2907s 
2907s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2907s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'.
2907s Cleaned up 1 empty switch.
2907s 
2907s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
2907s Removed a total of 0 dead cases.
2907s 
2907s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
2907s Removed 1 redundant assignment.
2907s Promoted 1 assignment to connection.
2907s 
2907s 2.4. Executing PROC_INIT pass (extract init attributes).
2907s 
2907s 2.5. Executing PROC_ARST pass (detect async resets in processes).
2907s 
2907s 2.6. Executing PROC_ROM pass (convert switches to ROMs).
2907s Converted 0 switches.
2907s 
2907s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
2907s Creating decoders for process `\m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'.
2907s 
2907s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2907s 
2907s 2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2907s 
2907s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2907s 
2907s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2907s Removing empty process `m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'.
2907s Cleaned up 0 empty switches.
2907s 
2907s 2.12. Executing OPT_EXPR pass (perform const folding).
2907s Optimizing module m.
2907s Removed 0 unused cells and 1 unused wires.
2907s 
2907s -- Writing to `yosys-roundtrip-bin_unsigned-2.v' using backend `verilog' --
2907s 
2907s 3. Executing Verilog backend.
2907s 
2907s 3.1. Executing BMUXMAP pass.
2907s 
2907s 3.2. Executing DEMUXMAP pass.
2907s Dumping module `\m'.
2907s 
2907s End of script. Logfile hash: dc9f56cb10, CPU: user 0.01s system 0.00s, MEM: 7.25 MB peak
2907s Yosys 0.33 (git sha1 2584903a060)
2907s Time spent: 27% 1x clean (0 sec), 18% 1x opt_expr (0 sec), ...
2907s + diff yosys-roundtrip-bin_unsigned-1.v yosys-roundtrip-bin_unsigned-2.v
2907s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned roundtrip.v roundtrip_tb.v
2907s + ./iverilog-roundtrip-bin_unsigned
2907s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned-1 yosys-roundtrip-bin_unsigned-1.v roundtrip_tb.v
2907s + ./iverilog-roundtrip-bin_unsigned-1
2907s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned-2 yosys-roundtrip-bin_unsigned-2.v roundtrip_tb.v
2907s + ./iverilog-roundtrip-bin_unsigned-1
2907s + diff iverilog-roundtrip-bin_unsigned.log iverilog-roundtrip-bin_unsigned-1.log
2907s + diff iverilog-roundtrip-bin_unsigned-1.log iverilog-roundtrip-bin_unsigned-2.log
2907s + test_roundtrip bin_signed -DBASE_HEX -DSIGN=signed
2907s + local subtest=bin_signed
2907s + shift
2907s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-bin_signed-1.v
2907s 
2907s  /----------------------------------------------------------------------------\
2907s  |                                                                            |
2907s  |  yosys -- Yosys Open SYnthesis Suite                                       |
2907s  |                                                                            |
2907s  |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
2907s  |                                                                            |
2907s  |  Permission to use, copy, modify, and/or distribute this software for any  |
2907s  |  purpose with or without fee is hereby granted, provided that the above    |
2907s  |  copyright notice and this permission notice appear in all copies.         |
2907s  |                                                                            |
2907s  |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
2907s  |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
2907s  |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
2907s  |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
2907s  |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
2907s  |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
2907s  |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
2907s  |                                                                            |
2907s  \----------------------------------------------------------------------------/
2907s 
2907s  Yosys 0.33 (git sha1 2584903a060)
2907s 
2907s 
2907s -- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' --
2907s 
2907s 1. Executing Verilog-2005 frontend: roundtrip.v
2907s Parsing Verilog input from `roundtrip.v' to AST representation.
2907s Generating RTLIL representation for module `\m'.
2907s Successfully finished Verilog frontend.
2907s 
2907s 2. Executing PROC pass (convert processes to netlists).
2907s 
2907s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2907s Cleaned up 0 empty switches.
2907s 
2907s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
2907s Removed a total of 0 dead cases.
2907s 
2907s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
2907s Removed 1 redundant assignment.
2907s Promoted 1 assignment to connection.
2907s 
2907s 2.4. Executing PROC_INIT pass (extract init attributes).
2907s 
2907s 2.5. Executing PROC_ARST pass (detect async resets in processes).
2907s 
2907s 2.6. Executing PROC_ROM pass (convert switches to ROMs).
2907s Converted 0 switches.
2907s 
2907s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
2907s Creating decoders for process `\m.$proc$roundtrip.v:3$1'.
2907s 
2907s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2907s 
2907s 2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2907s 
2907s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2907s 
2907s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2907s Removing empty process `m.$proc$roundtrip.v:3$1'.
2907s Cleaned up 0 empty switches.
2907s 
2907s 2.12. Executing OPT_EXPR pass (perform const folding).
2907s Optimizing module m.
2907s Removed 0 unused cells and 1 unused wires.
2907s 
2907s -- Writing to `yosys-roundtrip-bin_signed-1.v' using backend `verilog' --
2907s 
2907s 3. Executing Verilog backend.
2907s 
2907s 3.1. Executing BMUXMAP pass.
2907s 
2907s 3.2. Executing DEMUXMAP pass.
2907s Dumping module `\m'.
2907s 
2907s End of script. Logfile hash: 7709253822, CPU: user 0.01s system 0.00s, MEM: 7.25 MB peak
2907s Yosys 0.33 (git sha1 2584903a060)
2907s Time spent: 26% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ...
2907s + ../../yosys -p 'read_verilog yosys-roundtrip-bin_signed-1.v; proc; clean' -o yosys-roundtrip-bin_signed-2.v
2907s 
2907s  /----------------------------------------------------------------------------\
2907s  |                                                                            |
2907s  |  yosys -- Yosys Open SYnthesis Suite                                       |
2907s  |                                                                            |
2907s  |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
2907s  |                                                                            |
2907s  |  Permission to use, copy, modify, and/or distribute this software for any  |
2907s  |  purpose with or without fee is hereby granted, provided that the above    |
2907s  |  copyright notice and this permission notice appear in all copies.         |
2907s  |                                                                            |
2907s  |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
2907s  |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
2907s  |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
2907s  |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
2907s  |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
2907s  |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
2907s  |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
2907s  |                                                                            |
2907s  \----------------------------------------------------------------------------/
2907s 
2907s  Yosys 0.33 (git sha1 2584903a060)
2907s 
2907s 
2907s -- Running command `read_verilog yosys-roundtrip-bin_signed-1.v; proc; clean' --
2907s 
2907s 1. Executing Verilog-2005 frontend: yosys-roundtrip-bin_signed-1.v
2907s Parsing Verilog input from `yosys-roundtrip-bin_signed-1.v' to AST representation.
2907s Generating RTLIL representation for module `\m'.
2907s Successfully finished Verilog frontend.
2907s 
2907s 2. Executing PROC pass (convert processes to netlists).
2907s 
2907s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2907s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'.
2907s Cleaned up 1 empty switch.
2907s 
2907s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
2907s Removed a total of 0 dead cases.
2907s 
2907s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
2907s Removed 1 redundant assignment.
2907s Promoted 1 assignment to connection.
2907s 
2907s 2.4. Executing PROC_INIT pass (extract init attributes).
2907s 
2907s 2.5. Executing PROC_ARST pass (detect async resets in processes).
2907s 
2907s 2.6. Executing PROC_ROM pass (convert switches to ROMs).
2907s Converted 0 switches.
2907s 
2907s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
2907s Creating decoders for process `\m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'.
2907s 
2907s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2907s 
2907s 2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2907s 
2907s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2907s 
2907s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2907s Removing empty process `m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'.
2907s Cleaned up 0 empty switches.
2907s 
2907s 2.12. Executing OPT_EXPR pass (perform const folding).
2907s Optimizing module m.
2907s Removed 0 unused cells and 1 unused wires.
2907s 
2907s -- Writing to `yosys-roundtrip-bin_signed-2.v' using backend `verilog' --
2907s 
2907s 3. Executing Verilog backend.
2907s 
2907s 3.1. Executing BMUXMAP pass.
2907s 
2907s 3.2. Executing DEMUXMAP pass.
2907s Dumping module `\m'.
2907s 
2907s End of script. Logfile hash: 7e2d8271c4, CPU: user 0.01s system 0.01s, MEM: 7.25 MB peak
2907s Yosys 0.33 (git sha1 2584903a060)
2907s Time spent: 26% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ...
2907s + diff yosys-roundtrip-bin_signed-1.v yosys-roundtrip-bin_signed-2.v
2907s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed roundtrip.v roundtrip_tb.v
2907s + ./iverilog-roundtrip-bin_signed
2907s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed-1 yosys-roundtrip-bin_signed-1.v roundtrip_tb.v
2907s + ./iverilog-roundtrip-bin_signed-1
2907s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed-2 yosys-roundtrip-bin_signed-2.v roundtrip_tb.v
2907s + ./iverilog-roundtrip-bin_signed-1
2907s + diff iverilog-roundtrip-bin_signed.log iverilog-roundtrip-bin_signed-1.log
2907s + diff iverilog-roundtrip-bin_signed-1.log iverilog-roundtrip-bin_signed-2.log
2907s + test_cxxrtl always_full
2907s + local subtest=always_full
2907s + shift
2907s + ../../yosys -p 'read_verilog always_full.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_full.cc'
2907s 
2907s  /----------------------------------------------------------------------------\
2907s  |                                                                            |
2907s  |  yosys -- Yosys Open SYnthesis Suite                                       |
2907s  |                                                                            |
2907s  |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
2907s  |                                                                            |
2907s  |  Permission to use, copy, modify, and/or distribute this software for any  |
2907s  |  purpose with or without fee is hereby granted, provided that the above    |
2907s  |  copyright notice and this permission notice appear in all copies.         |
2907s  |                                                                            |
2907s  |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
2907s  |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
2907s  |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
2907s  |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
2907s  |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
2907s  |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
2907s  |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
2907s  |                                                                            |
2907s  \----------------------------------------------------------------------------/
2907s 
2907s  Yosys 0.33 (git sha1 2584903a060)
2907s 
2907s 
2907s -- Running command `read_verilog always_full.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_full.cc' --
2907s 
2907s 1. Executing Verilog-2005 frontend: always_full.v
2907s Parsing Verilog input from `always_full.v' to AST representation.
2907s Generating RTLIL representation for module `\always_full'.
2907s Successfully finished Verilog frontend.
2907s 
2907s 2. Executing PROC pass (convert processes to netlists).
2907s 
2907s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2907s Cleaned up 0 empty switches.
2907s 
2907s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
2907s Removed a total of 0 dead cases.
2907s 
2907s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
2907s Removed 207 redundant assignments.
2907s Promoted 207 assignments to connections.
2907s 
2907s 2.4. Executing PROC_INIT pass (extract init attributes).
2907s 
2907s 2.5. Executing PROC_ARST pass (detect async resets in processes).
2907s 
2907s 2.6. Executing PROC_ROM pass (convert switches to ROMs).
2907s Converted 0 switches.
2907s 
2907s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
2907s Creating decoders for process `\always_full.$proc$always_full.v:3$1'.
2907s 
2907s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2907s 
2907s 2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2907s 
2907s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2907s 
2907s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2907s Removing empty process `always_full.$proc$always_full.v:3$1'.
2907s Cleaned up 0 empty switches.
2907s 
2907s 2.12. Executing OPT_EXPR pass (perform const folding).
2907s Optimizing module always_full.
2907s Removed 0 unused cells and 207 unused wires.
2907s 
2907s 3. Executing CXXRTL backend.
2907s 
2907s 3.1. Executing HIERARCHY pass (managing design hierarchy).
2907s 
2907s 3.1.1. Finding top of design hierarchy..
2907s root of   0 design levels: always_full         
2907s Automatically selected always_full as design top module.
2907s 
2907s 3.1.2. Analyzing design hierarchy..
2907s Top module:  \always_full
2907s 
2907s 3.1.3. Analyzing design hierarchy..
2907s Top module:  \always_full
2907s Removed 0 unused modules.
2907s 
2907s 3.2. Executing FLATTEN pass (flatten design).
2907s 
2907s 3.3. Executing PROC pass (convert processes to netlists).
2907s 
2907s 3.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2907s Cleaned up 0 empty switches.
2907s 
2907s 3.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
2907s Removed a total of 0 dead cases.
2907s 
2907s 3.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
2907s Removed 0 redundant assignments.
2907s Promoted 0 assignments to connections.
2907s 
2907s 3.3.4. Executing PROC_INIT pass (extract init attributes).
2907s 
2907s 3.3.5. Executing PROC_ARST pass (detect async resets in processes).
2907s 
2907s 3.3.6. Executing PROC_ROM pass (convert switches to ROMs).
2907s Converted 0 switches.
2907s 
2907s 3.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
2907s 
2907s 3.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2907s 
2907s 3.3.9. Executing PROC_DFF pass (convert process syncs to FFs).
2907s 
2907s 3.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2907s 
2907s 3.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2907s Cleaned up 0 empty switches.
2907s 
2907s 3.3.12. Executing OPT_EXPR pass (perform const folding).
2907s Optimizing module always_full.
2907s 
2907s <suppressed ~11 debug messages>
2907s 
2907s End of script. Logfile hash: 6abd135c0a, CPU: user 0.03s system 0.00s, MEM: 8.38 MB peak
2907s Yosys 0.33 (git sha1 2584903a060)
2907s Time spent: 24% 2x read_verilog (0 sec), 21% 2x opt_expr (0 sec), ...
2907s + gcc -std=c++11 -o yosys-always_full -I../.. always_full_tb.cc -lstdc++
2908s + ./yosys-always_full
2909s + iverilog -o iverilog-always_full always_full.v always_full_tb.v
2909s + ./iverilog-always_full
2909s + grep -v '\$finish called'
2909s + diff iverilog-always_full.log yosys-always_full.log
2909s + test_cxxrtl always_comb
2909s + local subtest=always_comb
2909s + shift
2909s + ../../yosys -p 'read_verilog always_comb.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_comb.cc'
2909s 
2909s  /----------------------------------------------------------------------------\
2909s  |                                                                            |
2909s  |  yosys -- Yosys Open SYnthesis Suite                                       |
2909s  |                                                                            |
2909s  |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
2909s  |                                                                            |
2909s  |  Permission to use, copy, modify, and/or distribute this software for any  |
2909s  |  purpose with or without fee is hereby granted, provided that the above    |
2909s  |  copyright notice and this permission notice appear in all copies.         |
2909s  |                                                                            |
2909s  |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
2909s  |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
2909s  |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
2909s  |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
2909s  |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
2909s  |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
2909s  |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
2909s  |                                                                            |
2909s  \----------------------------------------------------------------------------/
2909s 
2909s  Yosys 0.33 (git sha1 2584903a060)
2909s 
2909s 
2909s -- Running command `read_verilog always_comb.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_comb.cc' --
2909s 
2909s 1. Executing Verilog-2005 frontend: always_comb.v
2909s Parsing Verilog input from `always_comb.v' to AST representation.
2909s Generating RTLIL representation for module `\top'.
2909s Generating RTLIL representation for module `\sub'.
2909s Successfully finished Verilog frontend.
2909s 
2909s 2. Executing PROC pass (convert processes to netlists).
2909s 
2909s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2909s Cleaned up 0 empty switches.
2909s 
2909s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
2909s Removed a total of 0 dead cases.
2909s 
2909s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
2909s Removed 0 redundant assignments.
2909s Promoted 4 assignments to connections.
2909s 
2909s 2.4. Executing PROC_INIT pass (extract init attributes).
2909s Found init rule in `\top.$proc$always_comb.v:3$13'.
2909s   Set init value: \b = 1'0
2909s Found init rule in `\top.$proc$always_comb.v:2$12'.
2909s   Set init value: \a = 1'0
2909s 
2909s 2.5. Executing PROC_ARST pass (detect async resets in processes).
2909s 
2909s 2.6. Executing PROC_ROM pass (convert switches to ROMs).
2909s Converted 0 switches.
2909s <suppressed ~1 debug messages>
2909s 
2909s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
2909s Creating decoders for process `\sub.$proc$always_comb.v:23$15'.
2909s      1/1: $display$always_comb.v:23$19_EN
2909s Creating decoders for process `\top.$proc$always_comb.v:3$13'.
2909s Creating decoders for process `\top.$proc$always_comb.v:2$12'.
2909s Creating decoders for process `\top.$proc$always_comb.v:8$1'.
2909s 
2909s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2909s 
2909s 2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2909s Creating register for signal `\top.\a' using process `\top.$proc$always_comb.v:8$1'.
2909s   created $dff cell `$procdff$22' with positive edge clock.
2909s Creating register for signal `\top.\b' using process `\top.$proc$always_comb.v:8$1'.
2909s   created $dff cell `$procdff$23' with positive edge clock.
2909s 
2909s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2909s 
2909s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2909s Found and cleaned up 1 empty switch in `\sub.$proc$always_comb.v:23$15'.
2909s Removing empty process `sub.$proc$always_comb.v:23$15'.
2909s Removing empty process `top.$proc$always_comb.v:3$13'.
2909s Removing empty process `top.$proc$always_comb.v:2$12'.
2909s Removing empty process `top.$proc$always_comb.v:8$1'.
2909s Cleaned up 1 empty switch.
2909s 
2909s 2.12. Executing OPT_EXPR pass (perform const folding).
2909s Optimizing module sub.
2909s Optimizing module top.
2909s Removed 0 unused cells and 7 unused wires.
2909s 
2909s 3. Executing CXXRTL backend.
2909s 
2909s 3.1. Executing HIERARCHY pass (managing design hierarchy).
2909s 
2909s 3.1.1. Finding top of design hierarchy..
2909s root of   0 design levels: sub                 
2909s root of   1 design levels: top                 
2909s Automatically selected top as design top module.
2909s 
2909s 3.1.2. Analyzing design hierarchy..
2909s Top module:  \top
2909s Used module:     \sub
2909s 
2909s 3.1.3. Analyzing design hierarchy..
2909s + gcc -std=c++11 -o yosys-always_comb -I../.. always_comb_tb.cc -lstdc++
2909s Top module:  \top
2909s Used module:     \sub
2909s Removed 0 unused modules.
2909s 
2909s 3.2. Executing FLATTEN pass (flatten design).
2909s Deleting now unused module sub.
2909s <suppressed ~1 debug messages>
2909s 
2909s 3.3. Executing PROC pass (convert processes to netlists).
2909s 
2909s 3.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2909s Cleaned up 0 empty switches.
2909s 
2909s 3.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
2909s Removed a total of 0 dead cases.
2909s 
2909s 3.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
2909s Removed 0 redundant assignments.
2909s Promoted 0 assignments to connections.
2909s 
2909s 3.3.4. Executing PROC_INIT pass (extract init attributes).
2909s 
2909s 3.3.5. Executing PROC_ARST pass (detect async resets in processes).
2909s 
2909s 3.3.6. Executing PROC_ROM pass (convert switches to ROMs).
2909s Converted 0 switches.
2909s 
2909s 3.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
2909s 
2909s 3.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2909s 
2909s 3.3.9. Executing PROC_DFF pass (convert process syncs to FFs).
2909s 
2909s 3.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2909s 
2909s 3.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2909s Cleaned up 0 empty switches.
2909s 
2909s 3.3.12. Executing OPT_EXPR pass (perform const folding).
2909s Optimizing module top.
2909s 
2909s <suppressed ~11 debug messages>
2909s 
2909s End of script. Logfile hash: 03fe26efda, CPU: user 0.01s system 0.01s, MEM: 7.62 MB peak
2909s Yosys 0.33 (git sha1 2584903a060)
2909s Time spent: 28% 2x opt_expr (0 sec), 19% 1x clean (0 sec), ...
2910s + ./yosys-always_comb
2910s + iverilog -o iverilog-always_comb always_comb.v always_comb_tb.v
2910s + ./iverilog-always_comb
2910s + grep -v '\$finish called'
2910s + diff iverilog-always_comb.log yosys-always_comb.log
2910s + ../../yosys -p 'read_verilog always_full.v; prep; clean' -o yosys-always_full-1.v
2910s 
2910s  /----------------------------------------------------------------------------\
2910s  |                                                                            |
2910s  |  yosys -- Yosys Open SYnthesis Suite                                       |
2910s  |                                                                            |
2910s  |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
2910s  |                                                                            |
2910s  |  Permission to use, copy, modify, and/or distribute this software for any  |
2910s  |  purpose with or without fee is hereby granted, provided that the above    |
2910s  |  copyright notice and this permission notice appear in all copies.         |
2910s  |                                                                            |
2910s  |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
2910s  |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
2910s  |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
2910s  |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
2910s  |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
2910s  |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
2910s  |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
2910s  |                                                                            |
2910s  \----------------------------------------------------------------------------/
2910s 
2910s  Yosys 0.33 (git sha1 2584903a060)
2910s 
2910s 
2910s -- Running command `read_verilog always_full.v; prep; clean' --
2910s 
2910s 1. Executing Verilog-2005 frontend: always_full.v
2910s Parsing Verilog input from `always_full.v' to AST representation.
2910s Generating RTLIL representation for module `\always_full'.
2910s Successfully finished Verilog frontend.
2910s 
2910s 2. Executing PREP pass.
2910s 
2910s 2.1. Executing HIERARCHY pass (managing design hierarchy).
2910s 
2910s 2.2. Executing PROC pass (convert processes to netlists).
2910s 
2910s 2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2910s Cleaned up 0 empty switches.
2910s 
2910s 2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
2910s Removed a total of 0 dead cases.
2910s 
2910s 2.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
2910s Removed 207 redundant assignments.
2910s Promoted 207 assignments to connections.
2910s 
2910s 2.2.4. Executing PROC_INIT pass (extract init attributes).
2910s 
2910s 2.2.5. Executing PROC_ARST pass (detect async resets in processes).
2910s 
2910s 2.2.6. Executing PROC_ROM pass (convert switches to ROMs).
2910s Converted 0 switches.
2910s 
2910s 2.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
2910s Creating decoders for process `\always_full.$proc$always_full.v:3$1'.
2910s 
2910s 2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2910s 
2910s 2.2.9. Executing PROC_DFF pass (convert process syncs to FFs).
2910s 
2910s 2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2910s 
2910s 2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2910s Removing empty process `always_full.$proc$always_full.v:3$1'.
2910s Cleaned up 0 empty switches.
2910s 
2910s 2.2.12. Executing OPT_EXPR pass (perform const folding).
2910s Optimizing module always_full.
2910s 
2910s 2.3. Executing OPT_EXPR pass (perform const folding).
2910s Optimizing module always_full.
2910s 
2910s 2.4. Executing OPT_CLEAN pass (remove unused cells and wires).
2910s Finding unused cells or wires in module \always_full..
2910s Removed 0 unused cells and 207 unused wires.
2910s <suppressed ~1 debug messages>
2910s 
2910s 2.5. Executing CHECK pass (checking for obvious problems).
2910s Checking module always_full...
2910s Found and reported 0 problems.
2910s 
2910s 2.6. Executing OPT pass (performing simple optimizations).
2910s 
2910s 2.6.1. Executing OPT_EXPR pass (perform const folding).
2910s Optimizing module always_full.
2910s 
2910s 2.6.2. Executing OPT_MERGE pass (detect identical cells).
2910s Finding identical cells in module `\always_full'.
2910s Removed a total of 0 cells.
2910s 
2910s 2.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
2910s Running muxtree optimizer on module \always_full..
2910s   Creating internal representation of mux trees.
2910s   No muxes found in this module.
2910s Removed 0 multiplexer ports.
2910s 
2910s 2.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
2910s   Optimizing cells in module \always_full.
2910s Performed a total of 0 changes.
2910s 
2910s 2.6.5. Executing OPT_MERGE pass (detect identical cells).
2910s Finding identical cells in module `\always_full'.
2910s Removed a total of 0 cells.
2910s 
2910s 2.6.6. Executing OPT_CLEAN pass (remove unused cells and wires).
2910s Finding unused cells or wires in module \always_full..
2910s 
2910s 2.6.7. Executing OPT_EXPR pass (perform const folding).
2910s Optimizing module always_full.
2910s 
2910s 2.6.8. Finished OPT passes. (There is nothing left to do.)
2910s 
2910s 2.7. Executing WREDUCE pass (reducing word size of cells).
2910s 
2910s 2.8. Executing OPT_CLEAN pass (remove unused cells and wires).
2910s Finding unused cells or wires in module \always_full..
2910s 
2910s 2.9. Executing MEMORY_COLLECT pass (generating $mem cells).
2910s 
2910s 2.10. Executing OPT pass (performing simple optimizations).
2910s 
2910s 2.10.1. Executing OPT_EXPR pass (perform const folding).
2910s Optimizing module always_full.
2910s 
2910s 2.10.2. Executing OPT_MERGE pass (detect identical cells).
2910s Finding identical cells in module `\always_full'.
2910s Removed a total of 0 cells.
2910s 
2910s 2.10.3. Executing OPT_CLEAN pass (remove unused cells and wires).
2910s Finding unused cells or wires in module \always_full..
2910s 
2910s 2.10.4. Finished fast OPT passes.
2910s 
2910s 2.11. Printing statistics.
2910s 
2910s === always_full ===
2910s 
2910s    Number of wires:                  1
2910s    Number of wire bits:              1
2910s    Number of public wires:           1
2910s    Number of public wire bits:       1
2910s    Number of memories:               0
2910s    Number of memory bits:            0
2910s    Number of processes:              0
2910s    Number of cells:                207
2910s      $print                        207
2910s 
2910s 2.12. Executing CHECK pass (checking for obvious problems).
2910s Checking module always_full...
2910s Found and reported 0 problems.
2910s 
2910s -- Writing to `yosys-always_full-1.v' using backend `verilog' --
2910s 
2910s 3. Executing Verilog backend.
2910s 
2910s 3.1. Executing BMUXMAP pass.
2910s 
2910s 3.2. Executing DEMUXMAP pass.
2910s Dumping module `\always_full'.
2910s 
2910s End of script. Logfile hash: cfd5b76053, CPU: user 0.08s system 0.01s, MEM: 8.25 MB peak
2910s Yosys 0.33 (git sha1 2584903a060)
2910s Time spent: 20% 5x opt_expr (0 sec), 20% 4x opt_clean (0 sec), ...
2910s + iverilog -o iverilog-always_full-1 yosys-always_full-1.v always_full_tb.v
2910s + ./iverilog-always_full-1
2910s + grep -v '\$finish called'
2910s + diff iverilog-always_full.log iverilog-always_full-1.log
2910s + ../../yosys -p 'read_verilog display_lm.v'
2910s + ../../yosys -p 'read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc'
2910s 
2910s  /----------------------------------------------------------------------------\
2910s  |                                                                            |
2910s  |  yosys -- Yosys Open SYnthesis Suite                                       |
2910s  |                                                                            |
2910s  |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
2910s  |                                                                            |
2910s  |  Permission to use, copy, modify, and/or distribute this software for any  |
2910s  |  purpose with or without fee is hereby granted, provided that the above    |
2910s  |  copyright notice and this permission notice appear in all copies.         |
2910s  |                                                                            |
2910s  |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
2910s  |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
2910s  |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
2910s  |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
2910s  |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
2910s  |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
2910s  |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
2910s  |                                                                            |
2910s  \----------------------------------------------------------------------------/
2910s 
2910s  Yosys 0.33 (git sha1 2584903a060)
2910s 
2910s 
2910s -- Running command `read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc' --
2910s 
2910s 1. Executing Verilog-2005 frontend: display_lm.v
2910s Parsing Verilog input from `display_lm.v' to AST representation.
2910s Generating RTLIL representation for module `\top'.
2910s Generating RTLIL representation for module `\mid'.
2910s Generating RTLIL representation for module `\bot'.
2910s %l: \bot
2910s %m: \bot
2910s Successfully finished Verilog frontend.
2910s 
2910s 2. Executing CXXRTL backend.
2910s 
2910s 2.1. Executing HIERARCHY pass (managing design hierarchy).
2910s 
2910s 2.1.1. Finding top of design hierarchy..
2910s root of   0 design levels: bot                 
2910s root of   1 design levels: mid                 
2910s root of   2 design levels: top                 
2910s Automatically selected top as design top module.
2910s 
2910s 2.1.2. Analyzing design hierarchy..
2910s Top module:  \top
2910s Used module:     \mid
2910s Used module:         \bot
2910s 
2910s 2.1.3. Analyzing design hierarchy..
2910s Top module:  \top
2910s Used module:     \mid
2910s Used module:         \bot
2910s Removed 0 unused modules.
2910s 
2910s 2.2. Executing FLATTEN pass (flatten design).
2910s Deleting now unused module bot.
2910s Deleting now unused module mid.
2910s <suppressed ~2 debug messages>
2910s 
2910s 2.3. Executing PROC pass (convert processes to netlists).
2910s 
2910s 2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2910s Removing empty process `top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:0$3'.
2910s Cleaned up 0 empty switches.
2910s 
2910s 2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
2910s Removed a total of 0 dead cases.
2910s 
2910s 2.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
2910s Removed 1 redundant assignment.
2910s Promoted 1 assignment to connection.
2910s 
2910s 2.3.4. Executing PROC_INIT pass (extract init attributes).
2910s 
2910s 2.3.5. Executing PROC_ARST pass (detect async resets in processes).
2910s 
2910s 2.3.6. Executing PROC_ROM pass (convert switches to ROMs).
2910s Converted 0 switches.
2910s 
2910s 2.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
2910s Creating decoders for process `\top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:11$1'.
2910s 
2910s 2.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).
2910s 
2910s 2.3.9. Executing PROC_DFF pass (convert process syncs to FFs).
2910s 
2910s 2.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
2910s 
2910s 2.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
2910s Removing empty process `top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:11$1'.
2910s Cleaned up 0 empty switches.
2910s 
2910s 2.3.12. Executing OPT_EXPR pass (perform const folding).
2910s Optimizing module top.
2910s 
2910s <suppressed ~11 debug messages>
2910s 
2910s End of script. Logfile hash: 1b689717a7, CPU: user 0.01s system 0.00s, MEM: 7.38 MB peak
2910s Yosys 0.33 (git sha1 2584903a060)
2910s Time spent: 31% 1x opt_expr (0 sec), 24% 2x read_verilog (0 sec), ...
2910s + gcc -std=c++11 -o yosys-display_lm_cc -I../.. display_lm_tb.cc -lstdc++
2911s + ./yosys-display_lm_cc
2911s + for log in yosys-display_lm.log yosys-display_lm_cc.log
2911s + grep '^%l: \\bot$' yosys-display_lm.log
2911s %l: \bot
2911s + grep '^%m: \\bot$' yosys-display_lm.log
2911s %m: \bot
2911s + for log in yosys-display_lm.log yosys-display_lm_cc.log
2911s + grep '^%l: \\bot$' yosys-display_lm_cc.log
2911s %l: \bot
2911s + grep '^%m: \\bot$' yosys-display_lm_cc.log
2911s %m: \bot
2911s 
2911s   Passed "make test".
2911s 
2911s autopkgtest [23:07:36]: test yosys-testsuite: -----------------------]
2915s autopkgtest [23:07:40]: test yosys-testsuite:  - - - - - - - - - - results - - - - - - - - - -
2915s yosys-testsuite      PASS
2919s autopkgtest [23:07:44]: test ice: preparing testbed
2941s autopkgtest [23:08:06]: testbed dpkg architecture: armhf
2943s autopkgtest [23:08:08]: testbed apt version: 3.0.0
2947s autopkgtest [23:08:12]: @@@@@@@@@@@@@@@@@@@@ test bed setup
2949s autopkgtest [23:08:14]: testbed release detected to be: questing
2956s autopkgtest [23:08:21]: updating testbed package index (apt update)
2957s Get:1 http://ftpmaster.internal/ubuntu questing-proposed InRelease [110 kB]
2958s Get:2 http://ftpmaster.internal/ubuntu questing InRelease [110 kB]
2958s Get:3 http://ftpmaster.internal/ubuntu questing-updates InRelease [110 kB]
2958s Get:4 http://ftpmaster.internal/ubuntu questing-security InRelease [110 kB]
2958s Get:5 http://ftpmaster.internal/ubuntu questing-proposed/universe Sources [818 kB]
2958s Get:6 http://ftpmaster.internal/ubuntu questing-proposed/main Sources [86.1 kB]
2958s Get:7 http://ftpmaster.internal/ubuntu questing-proposed/multiverse Sources [30.0 kB]
2958s Get:8 http://ftpmaster.internal/ubuntu questing-proposed/main armhf Packages [115 kB]
2958s Get:9 http://ftpmaster.internal/ubuntu questing-proposed/universe armhf Packages [853 kB]
2958s Get:10 http://ftpmaster.internal/ubuntu questing-proposed/multiverse armhf Packages [16.2 kB]
2958s Get:11 http://ftpmaster.internal/ubuntu questing/multiverse Sources [307 kB]
2958s Get:12 http://ftpmaster.internal/ubuntu questing/universe Sources [21.3 MB]
2959s Get:13 http://ftpmaster.internal/ubuntu questing/main Sources [1396 kB]
2959s Get:14 http://ftpmaster.internal/ubuntu questing/main armhf Packages [1358 kB]
2959s Get:15 http://ftpmaster.internal/ubuntu questing/universe armhf Packages [15.1 MB]
2960s Get:16 http://ftpmaster.internal/ubuntu questing/multiverse armhf Packages [181 kB]
2964s Fetched 42.0 MB in 6s (6821 kB/s)
2965s Reading package lists...
2970s autopkgtest [23:08:35]: upgrading testbed (apt dist-upgrade and autopurge)
2972s Reading package lists...
2973s Building dependency tree...
2973s Reading state information...
2974s Calculating upgrade...Starting pkgProblemResolver with broken count: 0
2974s Starting 2 pkgProblemResolver with broken count: 0
2974s Done
2975s Entering ResolveByKeep
2976s 
2976s Calculating upgrade...
2977s The following package was automatically installed and is no longer required:
2977s   libsigsegv2
2977s Use 'apt autoremove' to remove it.
2977s The following packages will be upgraded:
2977s   base-files base-passwd btrfs-progs cloud-init cloud-init-base debianutils
2977s   dhcpcd-base diffutils dirmngr distro-info-data dpkg dpkg-dev ed ethtool
2977s   fwupd gawk gettext-base gir1.2-glib-2.0 gnupg gnupg-l10n gnupg-utils gpg
2977s   gpg-agent gpg-wks-client gpgconf gpgsm gpgv groff-base htop iso-codes
2977s   keyboxd less libbpf1 libdpkg-perl libevdev2 libftdi1-2 libfwupd3
2977s   libglib2.0-0t64 libglib2.0-data libgpg-error-l10n libgpg-error0 libjcat1
2977s   libmbim-glib4 libmbim-proxy libmm-glib0 libnftnl11 libnghttp2-14 libnpth0t64
2977s   libnuma1 libnvme1t64 libqmi-glib5 libqmi-proxy libselinux1 libsensors-config
2977s   libsensors5 libsepol2 libunistring5 liburcu8t64 libusb-1.0-0 libx11-6
2977s   libx11-data libxml2 man-db motd-news-config nano netbase netcat-openbsd
2977s   numactl openssh-client openssh-server openssh-sftp-server patch publicsuffix
2977s   python3-attr python3-lazr.restfulclient python3-more-itertools
2977s   python3-packaging python3-s3transfer python3-wadllib sos ubuntu-pro-client
2977s   ubuntu-pro-client-l10n usb.ids usbutils
2978s 84 upgraded, 0 newly installed, 0 to remove and 0 not upgraded.
2978s Need to get 25.2 MB of archives.
2978s After this operation, 275 kB of additional disk space will be used.
2978s Get:1 http://ftpmaster.internal/ubuntu questing/main armhf motd-news-config all 13.7ubuntu1 [5260 B]
2978s Get:2 http://ftpmaster.internal/ubuntu questing/main armhf base-files armhf 13.7ubuntu1 [75.4 kB]
2978s Get:3 http://ftpmaster.internal/ubuntu questing/main armhf debianutils armhf 5.22 [92.2 kB]
2978s Get:4 http://ftpmaster.internal/ubuntu questing/main armhf diffutils armhf 1:3.10-4 [172 kB]
2978s Get:5 http://ftpmaster.internal/ubuntu questing/main armhf dpkg armhf 1.22.18ubuntu3 [1254 kB]
2978s Get:6 http://ftpmaster.internal/ubuntu questing/main armhf libselinux1 armhf 3.8.1-1 [80.4 kB]
2978s Get:7 http://ftpmaster.internal/ubuntu questing/main armhf base-passwd armhf 3.6.7 [53.9 kB]
2978s Get:8 http://ftpmaster.internal/ubuntu questing-proposed/main armhf gawk armhf 1:5.3.2-1 [468 kB]
2978s Get:9 http://ftpmaster.internal/ubuntu questing/main armhf openssh-sftp-server armhf 1:9.9p1-3ubuntu3.1 [35.7 kB]
2978s Get:10 http://ftpmaster.internal/ubuntu questing/main armhf openssh-server armhf 1:9.9p1-3ubuntu3.1 [532 kB]
2978s Get:11 http://ftpmaster.internal/ubuntu questing/main armhf openssh-client armhf 1:9.9p1-3ubuntu3.1 [924 kB]
2978s Get:12 http://ftpmaster.internal/ubuntu questing/main armhf libsepol2 armhf 3.8.1-1 [282 kB]
2978s Get:13 http://ftpmaster.internal/ubuntu questing/main armhf libgpg-error-l10n all 1.51-4 [8880 B]
2978s Get:14 http://ftpmaster.internal/ubuntu questing/main armhf libgpg-error0 armhf 1.51-4 [64.6 kB]
2978s Get:15 http://ftpmaster.internal/ubuntu questing/main armhf libnpth0t64 armhf 1.8-3 [7716 B]
2978s Get:16 http://ftpmaster.internal/ubuntu questing/main armhf gpg-wks-client armhf 2.4.4-2ubuntu24 [87.5 kB]
2978s Get:17 http://ftpmaster.internal/ubuntu questing/main armhf dirmngr armhf 2.4.4-2ubuntu24 [348 kB]
2978s Get:18 http://ftpmaster.internal/ubuntu questing/main armhf gpgsm armhf 2.4.4-2ubuntu24 [242 kB]
2978s Get:19 http://ftpmaster.internal/ubuntu questing/main armhf gnupg-utils armhf 2.4.4-2ubuntu24 [160 kB]
2978s Get:20 http://ftpmaster.internal/ubuntu questing/main armhf gpg-agent armhf 2.4.4-2ubuntu24 [237 kB]
2978s Get:21 http://ftpmaster.internal/ubuntu questing/main armhf gpg armhf 2.4.4-2ubuntu24 [525 kB]
2978s Get:22 http://ftpmaster.internal/ubuntu questing/main armhf gpgconf armhf 2.4.4-2ubuntu24 [117 kB]
2978s Get:23 http://ftpmaster.internal/ubuntu questing/main armhf gnupg all 2.4.4-2ubuntu24 [359 kB]
2978s Get:24 http://ftpmaster.internal/ubuntu questing/main armhf keyboxd armhf 2.4.4-2ubuntu24 [112 kB]
2978s Get:25 http://ftpmaster.internal/ubuntu questing/main armhf gpgv armhf 2.4.4-2ubuntu24 [225 kB]
2978s Get:26 http://ftpmaster.internal/ubuntu questing/main armhf dhcpcd-base armhf 1:10.1.0-10 [189 kB]
2978s Get:27 http://ftpmaster.internal/ubuntu questing/main armhf distro-info-data all 0.64 [6664 B]
2978s Get:28 http://ftpmaster.internal/ubuntu questing/main armhf gir1.2-glib-2.0 armhf 2.84.1-2 [185 kB]
2978s Get:29 http://ftpmaster.internal/ubuntu questing/main armhf libglib2.0-0t64 armhf 2.84.1-2 [1455 kB]
2978s Get:30 http://ftpmaster.internal/ubuntu questing/main armhf iso-codes all 4.18.0-1 [3703 kB]
2978s Get:31 http://ftpmaster.internal/ubuntu questing/main armhf less armhf 668-1 [158 kB]
2978s Get:32 http://ftpmaster.internal/ubuntu questing/main armhf libbpf1 armhf 1:1.5.0-3 [158 kB]
2978s Get:33 http://ftpmaster.internal/ubuntu questing/main armhf libglib2.0-data all 2.84.1-2 [53.2 kB]
2978s Get:34 http://ftpmaster.internal/ubuntu questing/main armhf libunistring5 armhf 1.3-2 [583 kB]
2978s Get:35 http://ftpmaster.internal/ubuntu questing/main armhf libxml2 armhf 2.12.7+dfsg+really2.9.14-0.4ubuntu0.1 [599 kB]
2978s Get:36 http://ftpmaster.internal/ubuntu questing/main armhf netbase all 6.5 [12.9 kB]
2978s Get:37 http://ftpmaster.internal/ubuntu questing/main armhf netcat-openbsd armhf 1.229-1 [42.4 kB]
2978s Get:38 http://ftpmaster.internal/ubuntu questing/main armhf ubuntu-pro-client-l10n armhf 35.1ubuntu0 [19.7 kB]
2978s Get:39 http://ftpmaster.internal/ubuntu questing/main armhf ubuntu-pro-client armhf 35.1ubuntu0 [258 kB]
2979s Get:40 http://ftpmaster.internal/ubuntu questing/main armhf ed armhf 1.21.1-1 [53.0 kB]
2979s Get:41 http://ftpmaster.internal/ubuntu questing/main armhf ethtool armhf 1:6.14-2 [230 kB]
2979s Get:42 http://ftpmaster.internal/ubuntu questing/main armhf gettext-base armhf 0.23.1-2 [43.5 kB]
2979s Get:43 http://ftpmaster.internal/ubuntu questing/main armhf groff-base armhf 1.23.0-8 [942 kB]
2979s Get:44 http://ftpmaster.internal/ubuntu questing/main armhf libevdev2 armhf 1.13.4+dfsg-1 [29.8 kB]
2979s Get:45 http://ftpmaster.internal/ubuntu questing/main armhf libnftnl11 armhf 1.2.9-1 [53.3 kB]
2979s Get:46 http://ftpmaster.internal/ubuntu questing/main armhf libnghttp2-14 armhf 1.64.0-1.1 [68.5 kB]
2979s Get:47 http://ftpmaster.internal/ubuntu questing/main armhf libnuma1 armhf 2.0.19-1 [19.9 kB]
2979s Get:48 http://ftpmaster.internal/ubuntu questing/main armhf libsensors-config all 1:3.6.2-2 [6756 B]
2979s Get:49 http://ftpmaster.internal/ubuntu questing/main armhf libsensors5 armhf 1:3.6.2-2 [26.8 kB]
2979s Get:50 http://ftpmaster.internal/ubuntu questing/main armhf liburcu8t64 armhf 0.15.2-2 [57.3 kB]
2979s Get:51 http://ftpmaster.internal/ubuntu questing/main armhf libusb-1.0-0 armhf 2:1.0.28-1 [50.0 kB]
2979s Get:52 http://ftpmaster.internal/ubuntu questing/main armhf libx11-data all 2:1.8.12-1 [116 kB]
2979s Get:53 http://ftpmaster.internal/ubuntu questing/main armhf libx11-6 armhf 2:1.8.12-1 [586 kB]
2979s Get:54 http://ftpmaster.internal/ubuntu questing/main armhf man-db armhf 2.13.1-1 [1341 kB]
2979s Get:55 http://ftpmaster.internal/ubuntu questing/main armhf nano armhf 8.4-1 [278 kB]
2979s Get:56 http://ftpmaster.internal/ubuntu questing/main armhf numactl armhf 2.0.19-1 [38.5 kB]
2979s Get:57 http://ftpmaster.internal/ubuntu questing/main armhf publicsuffix all 20250328.1952-0.1 [135 kB]
2979s Get:58 http://ftpmaster.internal/ubuntu questing/main armhf usb.ids all 2025.04.01-1 [223 kB]
2979s Get:59 http://ftpmaster.internal/ubuntu questing/main armhf usbutils armhf 1:018-2 [77.4 kB]
2979s Get:60 http://ftpmaster.internal/ubuntu questing/main armhf btrfs-progs armhf 6.14-1 [901 kB]
2979s Get:61 http://ftpmaster.internal/ubuntu questing/main armhf cloud-init-base all 25.2~1g7a0265d3-0ubuntu1 [619 kB]
2979s Get:62 http://ftpmaster.internal/ubuntu questing/main armhf dpkg-dev all 1.22.18ubuntu3 [1089 kB]
2979s Get:63 http://ftpmaster.internal/ubuntu questing/main armhf libdpkg-perl all 1.22.18ubuntu3 [281 kB]
2979s Get:64 http://ftpmaster.internal/ubuntu questing/main armhf patch armhf 2.8-1 [94.1 kB]
2979s Get:65 http://ftpmaster.internal/ubuntu questing/main armhf libjcat1 armhf 0.2.3-1 [30.9 kB]
2979s Get:66 http://ftpmaster.internal/ubuntu questing/main armhf fwupd armhf 2.0.8-3 [1414 kB]
2979s Get:67 http://ftpmaster.internal/ubuntu questing/main armhf libfwupd3 armhf 2.0.8-3 [126 kB]
2979s Get:68 http://ftpmaster.internal/ubuntu questing/main armhf libmbim-proxy armhf 1.32.0-1 [5888 B]
2979s Get:69 http://ftpmaster.internal/ubuntu questing/main armhf libmbim-glib4 armhf 1.32.0-1 [218 kB]
2979s Get:70 http://ftpmaster.internal/ubuntu questing/main armhf libmm-glib0 armhf 1.24.0-1 [223 kB]
2979s Get:71 http://ftpmaster.internal/ubuntu questing/main armhf libqmi-proxy armhf 1.36.0-1 [5882 B]
2979s Get:72 http://ftpmaster.internal/ubuntu questing/main armhf libqmi-glib5 armhf 1.36.0-1 [936 kB]
2979s Get:73 http://ftpmaster.internal/ubuntu questing/main armhf gnupg-l10n all 2.4.4-2ubuntu24 [66.8 kB]
2979s Get:74 http://ftpmaster.internal/ubuntu questing/main armhf htop armhf 3.4.1-4 [147 kB]
2979s Get:75 http://ftpmaster.internal/ubuntu questing/main armhf libftdi1-2 armhf 1.5-10 [27.8 kB]
2979s Get:76 http://ftpmaster.internal/ubuntu questing/main armhf libnvme1t64 armhf 1.13-2 [74.3 kB]
2979s Get:77 http://ftpmaster.internal/ubuntu questing/main armhf python3-attr all 25.3.0-1 [50.9 kB]
2979s Get:78 http://ftpmaster.internal/ubuntu questing/main armhf python3-wadllib all 2.0.0-3 [36.3 kB]
2979s Get:79 http://ftpmaster.internal/ubuntu questing/main armhf python3-lazr.restfulclient all 0.14.6-3 [51.0 kB]
2979s Get:80 http://ftpmaster.internal/ubuntu questing/main armhf python3-more-itertools all 10.7.0-1 [59.6 kB]
2979s Get:81 http://ftpmaster.internal/ubuntu questing/main armhf python3-packaging all 25.0-1 [52.8 kB]
2979s Get:82 http://ftpmaster.internal/ubuntu questing/main armhf python3-s3transfer all 0.11.4-1 [55.8 kB]
2979s Get:83 http://ftpmaster.internal/ubuntu questing/main armhf sos all 4.9.1-1 [367 kB]
2979s Get:84 http://ftpmaster.internal/ubuntu questing/main armhf cloud-init all 25.2~1g7a0265d3-0ubuntu1 [2106 B]
2980s Preconfiguring packages ...
2980s Fetched 25.2 MB in 2s (14.2 MB/s)
2980s (Reading database ... 
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(Reading database ... 63953 files and directories currently installed.)
2980s Preparing to unpack .../motd-news-config_13.7ubuntu1_all.deb ...
2980s Unpacking motd-news-config (13.7ubuntu1) over (13.6ubuntu2) ...
2980s Preparing to unpack .../base-files_13.7ubuntu1_armhf.deb ...
2980s Unpacking base-files (13.7ubuntu1) over (13.6ubuntu2) ...
2981s Setting up base-files (13.7ubuntu1) ...
2981s Installing new version of config file /etc/issue ...
2981s Installing new version of config file /etc/issue.net ...
2981s Installing new version of config file /etc/lsb-release ...
2981s motd-news.service is a disabled or a static unit not running, not starting it.
2981s (Reading database ... 
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(Reading database ... 63953 files and directories currently installed.)
2981s Preparing to unpack .../debianutils_5.22_armhf.deb ...
2981s Unpacking debianutils (5.22) over (5.21) ...
2981s Setting up debianutils (5.22) ...
2982s (Reading database ... 
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(Reading database ... 90%
(Reading database ... 95%
(Reading database ... 100%
(Reading database ... 63953 files and directories currently installed.)
2982s Preparing to unpack .../diffutils_1%3a3.10-4_armhf.deb ...
2982s Unpacking diffutils (1:3.10-4) over (1:3.10-3) ...
2982s Setting up diffutils (1:3.10-4) ...
2982s (Reading database ... 
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(Reading database ... 70%
(Reading database ... 75%
(Reading database ... 80%
(Reading database ... 85%
(Reading database ... 90%
(Reading database ... 95%
(Reading database ... 100%
(Reading database ... 63953 files and directories currently installed.)
2982s Preparing to unpack .../dpkg_1.22.18ubuntu3_armhf.deb ...
2982s Unpacking dpkg (1.22.18ubuntu3) over (1.22.18ubuntu2) ...
2982s Setting up dpkg (1.22.18ubuntu3) ...
2982s (Reading database ... 
(Reading database ... 5%
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(Reading database ... 55%
(Reading database ... 60%
(Reading database ... 65%
(Reading database ... 70%
(Reading database ... 75%
(Reading database ... 80%
(Reading database ... 85%
(Reading database ... 90%
(Reading database ... 95%
(Reading database ... 100%
(Reading database ... 63953 files and directories currently installed.)
2982s Preparing to unpack .../libselinux1_3.8.1-1_armhf.deb ...
2982s Unpacking libselinux1:armhf (3.8.1-1) over (3.7-3ubuntu3) ...
2983s Setting up libselinux1:armhf (3.8.1-1) ...
2983s (Reading database ... 
(Reading database ... 5%
(Reading database ... 10%
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(Reading database ... 25%
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(Reading database ... 35%
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(Reading database ... 45%
(Reading database ... 50%
(Reading database ... 55%
(Reading database ... 60%
(Reading database ... 65%
(Reading database ... 70%
(Reading database ... 75%
(Reading database ... 80%
(Reading database ... 85%
(Reading database ... 90%
(Reading database ... 95%
(Reading database ... 100%
(Reading database ... 63953 files and directories currently installed.)
2983s Preparing to unpack .../base-passwd_3.6.7_armhf.deb ...
2983s Unpacking base-passwd (3.6.7) over (3.6.6) ...
2983s Setting up base-passwd (3.6.7) ...
2983s (Reading database ... 
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(Reading database ... 25%
(Reading database ... 30%
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(Reading database ... 45%
(Reading database ... 50%
(Reading database ... 55%
(Reading database ... 60%
(Reading database ... 65%
(Reading database ... 70%
(Reading database ... 75%
(Reading database ... 80%
(Reading database ... 85%
(Reading database ... 90%
(Reading database ... 95%
(Reading database ... 100%
(Reading database ... 63953 files and directories currently installed.)
2983s Preparing to unpack .../gawk_1%3a5.3.2-1_armhf.deb ...
2983s Unpacking gawk (1:5.3.2-1) over (1:5.2.1-2build3) ...
2983s Preparing to unpack .../openssh-sftp-server_1%3a9.9p1-3ubuntu3.1_armhf.deb ...
2983s Unpacking openssh-sftp-server (1:9.9p1-3ubuntu3.1) over (1:9.9p1-3ubuntu3) ...
2983s Preparing to unpack .../openssh-server_1%3a9.9p1-3ubuntu3.1_armhf.deb ...
2983s Unpacking openssh-server (1:9.9p1-3ubuntu3.1) over (1:9.9p1-3ubuntu3) ...
2983s Preparing to unpack .../openssh-client_1%3a9.9p1-3ubuntu3.1_armhf.deb ...
2983s Unpacking openssh-client (1:9.9p1-3ubuntu3.1) over (1:9.9p1-3ubuntu3) ...
2983s Preparing to unpack .../libsepol2_3.8.1-1_armhf.deb ...
2983s Unpacking libsepol2:armhf (3.8.1-1) over (3.7-1) ...
2984s Setting up libsepol2:armhf (3.8.1-1) ...
2984s (Reading database ... 
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(Reading database ... 25%
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(Reading database ... 40%
(Reading database ... 45%
(Reading database ... 50%
(Reading database ... 55%
(Reading database ... 60%
(Reading database ... 65%
(Reading database ... 70%
(Reading database ... 75%
(Reading database ... 80%
(Reading database ... 85%
(Reading database ... 90%
(Reading database ... 95%
(Reading database ... 100%
(Reading database ... 63955 files and directories currently installed.)
2984s Preparing to unpack .../libgpg-error-l10n_1.51-4_all.deb ...
2984s Unpacking libgpg-error-l10n (1.51-4) over (1.51-3) ...
2984s Preparing to unpack .../libgpg-error0_1.51-4_armhf.deb ...
2984s Unpacking libgpg-error0:armhf (1.51-4) over (1.51-3) ...
2984s Setting up libgpg-error0:armhf (1.51-4) ...
2984s (Reading database ... 
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(Reading database ... 45%
(Reading database ... 50%
(Reading database ... 55%
(Reading database ... 60%
(Reading database ... 65%
(Reading database ... 70%
(Reading database ... 75%
(Reading database ... 80%
(Reading database ... 85%
(Reading database ... 90%
(Reading database ... 95%
(Reading database ... 100%
(Reading database ... 63955 files and directories currently installed.)
2984s Preparing to unpack .../libnpth0t64_1.8-3_armhf.deb ...
2984s Unpacking libnpth0t64:armhf (1.8-3) over (1.8-2) ...
2984s Setting up libnpth0t64:armhf (1.8-3) ...
2984s (Reading database ... 
(Reading database ... 5%
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(Reading database ... 25%
(Reading database ... 30%
(Reading database ... 35%
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(Reading database ... 45%
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(Reading database ... 55%
(Reading database ... 60%
(Reading database ... 65%
(Reading database ... 70%
(Reading database ... 75%
(Reading database ... 80%
(Reading database ... 85%
(Reading database ... 90%
(Reading database ... 95%
(Reading database ... 100%
(Reading database ... 63955 files and directories currently installed.)
2984s Preparing to unpack .../0-gpg-wks-client_2.4.4-2ubuntu24_armhf.deb ...
2984s Unpacking gpg-wks-client (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ...
2984s Preparing to unpack .../1-dirmngr_2.4.4-2ubuntu24_armhf.deb ...
2984s Unpacking dirmngr (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ...
2984s Preparing to unpack .../2-gpgsm_2.4.4-2ubuntu24_armhf.deb ...
2984s Unpacking gpgsm (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ...
2984s Preparing to unpack .../3-gnupg-utils_2.4.4-2ubuntu24_armhf.deb ...
2984s Unpacking gnupg-utils (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ...
2984s Preparing to unpack .../4-gpg-agent_2.4.4-2ubuntu24_armhf.deb ...
2984s Unpacking gpg-agent (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ...
2984s Preparing to unpack .../5-gpg_2.4.4-2ubuntu24_armhf.deb ...
2984s Unpacking gpg (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ...
2984s Preparing to unpack .../6-gpgconf_2.4.4-2ubuntu24_armhf.deb ...
2984s Unpacking gpgconf (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ...
2984s Preparing to unpack .../7-gnupg_2.4.4-2ubuntu24_all.deb ...
2984s Unpacking gnupg (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ...
2985s Preparing to unpack .../8-keyboxd_2.4.4-2ubuntu24_armhf.deb ...
2985s Unpacking keyboxd (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ...
2985s Preparing to unpack .../9-gpgv_2.4.4-2ubuntu24_armhf.deb ...
2985s Unpacking gpgv (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ...
2985s Setting up gpgv (2.4.4-2ubuntu24) ...
2985s (Reading database ... 
(Reading database ... 5%
(Reading database ... 10%
(Reading database ... 15%
(Reading database ... 20%
(Reading database ... 25%
(Reading database ... 30%
(Reading database ... 35%
(Reading database ... 40%
(Reading database ... 45%
(Reading database ... 50%
(Reading database ... 55%
(Reading database ... 60%
(Reading database ... 65%
(Reading database ... 70%
(Reading database ... 75%
(Reading database ... 80%
(Reading database ... 85%
(Reading database ... 90%
(Reading database ... 95%
(Reading database ... 100%
(Reading database ... 63955 files and directories currently installed.)
2985s Preparing to unpack .../00-dhcpcd-base_1%3a10.1.0-10_armhf.deb ...
2985s Unpacking dhcpcd-base (1:10.1.0-10) over (1:10.1.0-8) ...
2985s Preparing to unpack .../01-distro-info-data_0.64_all.deb ...
2985s Unpacking distro-info-data (0.64) over (0.63) ...
2985s Preparing to unpack .../02-gir1.2-glib-2.0_2.84.1-2_armhf.deb ...
2985s Unpacking gir1.2-glib-2.0:armhf (2.84.1-2) over (2.84.1-1) ...
2985s Preparing to unpack .../03-libglib2.0-0t64_2.84.1-2_armhf.deb ...
2985s Unpacking libglib2.0-0t64:armhf (2.84.1-2) over (2.84.1-1) ...
2985s Preparing to unpack .../04-iso-codes_4.18.0-1_all.deb ...
2985s Unpacking iso-codes (4.18.0-1) over (4.17.0-1) ...
2985s Preparing to unpack .../05-less_668-1_armhf.deb ...
2985s Unpacking less (668-1) over (643-1) ...
2986s Preparing to unpack .../06-libbpf1_1%3a1.5.0-3_armhf.deb ...
2986s Unpacking libbpf1:armhf (1:1.5.0-3) over (1:1.5.0-2) ...
2986s Preparing to unpack .../07-libglib2.0-data_2.84.1-2_all.deb ...
2986s Unpacking libglib2.0-data (2.84.1-2) over (2.84.1-1) ...
2986s Preparing to unpack .../08-libunistring5_1.3-2_armhf.deb ...
2986s Unpacking libunistring5:armhf (1.3-2) over (1.3-1) ...
2986s Preparing to unpack .../09-libxml2_2.12.7+dfsg+really2.9.14-0.4ubuntu0.1_armhf.deb ...
2986s Unpacking libxml2:armhf (2.12.7+dfsg+really2.9.14-0.4ubuntu0.1) over (2.12.7+dfsg+really2.9.14-0.4) ...
2986s Preparing to unpack .../10-netbase_6.5_all.deb ...
2986s Unpacking netbase (6.5) over (6.4) ...
2986s Preparing to unpack .../11-netcat-openbsd_1.229-1_armhf.deb ...
2986s Unpacking netcat-openbsd (1.229-1) over (1.228-1) ...
2986s Preparing to unpack .../12-ubuntu-pro-client-l10n_35.1ubuntu0_armhf.deb ...
2986s Unpacking ubuntu-pro-client-l10n (35.1ubuntu0) over (35) ...
2986s Preparing to unpack .../13-ubuntu-pro-client_35.1ubuntu0_armhf.deb ...
2986s Unpacking ubuntu-pro-client (35.1ubuntu0) over (35) ...
2986s Preparing to unpack .../14-ed_1.21.1-1_armhf.deb ...
2986s Unpacking ed (1.21.1-1) over (1.21-1) ...
2986s Preparing to unpack .../15-ethtool_1%3a6.14-2_armhf.deb ...
2986s Unpacking ethtool (1:6.14-2) over (1:6.11-1) ...
2986s Preparing to unpack .../16-gettext-base_0.23.1-2_armhf.deb ...
2986s Unpacking gettext-base (0.23.1-2) over (0.23.1-1) ...
2986s Preparing to unpack .../17-groff-base_1.23.0-8_armhf.deb ...
2986s Unpacking groff-base (1.23.0-8) over (1.23.0-7) ...
2987s Preparing to unpack .../18-libevdev2_1.13.4+dfsg-1_armhf.deb ...
2987s Unpacking libevdev2:armhf (1.13.4+dfsg-1) over (1.13.3+dfsg-1) ...
2987s Preparing to unpack .../19-libnftnl11_1.2.9-1_armhf.deb ...
2987s Unpacking libnftnl11:armhf (1.2.9-1) over (1.2.8-1) ...
2987s Preparing to unpack .../20-libnghttp2-14_1.64.0-1.1_armhf.deb ...
2987s Unpacking libnghttp2-14:armhf (1.64.0-1.1) over (1.64.0-1ubuntu1) ...
2987s Preparing to unpack .../21-libnuma1_2.0.19-1_armhf.deb ...
2987s Unpacking libnuma1:armhf (2.0.19-1) over (2.0.18-1build1) ...
2987s Preparing to unpack .../22-libsensors-config_1%3a3.6.2-2_all.deb ...
2987s Unpacking libsensors-config (1:3.6.2-2) over (1:3.6.0-10) ...
2987s Preparing to unpack .../23-libsensors5_1%3a3.6.2-2_armhf.deb ...
2987s Unpacking libsensors5:armhf (1:3.6.2-2) over (1:3.6.0-10) ...
2987s Preparing to unpack .../24-liburcu8t64_0.15.2-2_armhf.deb ...
2987s Unpacking liburcu8t64:armhf (0.15.2-2) over (0.15.1-1) ...
2987s Preparing to unpack .../25-libusb-1.0-0_2%3a1.0.28-1_armhf.deb ...
2987s Unpacking libusb-1.0-0:armhf (2:1.0.28-1) over (2:1.0.27-2) ...
2987s Preparing to unpack .../26-libx11-data_2%3a1.8.12-1_all.deb ...
2987s Unpacking libx11-data (2:1.8.12-1) over (2:1.8.10-2) ...
2987s Preparing to unpack .../27-libx11-6_2%3a1.8.12-1_armhf.deb ...
2987s Unpacking libx11-6:armhf (2:1.8.12-1) over (2:1.8.10-2) ...
2987s Preparing to unpack .../28-man-db_2.13.1-1_armhf.deb ...
2987s Unpacking man-db (2.13.1-1) over (2.13.0-1) ...
2987s Preparing to unpack .../29-nano_8.4-1_armhf.deb ...
2987s Unpacking nano (8.4-1) over (8.3-1) ...
2987s Preparing to unpack .../30-numactl_2.0.19-1_armhf.deb ...
2987s Unpacking numactl (2.0.19-1) over (2.0.18-1build1) ...
2988s Preparing to unpack .../31-publicsuffix_20250328.1952-0.1_all.deb ...
2988s Unpacking publicsuffix (20250328.1952-0.1) over (20250108.1153-0.1) ...
2988s Preparing to unpack .../32-usb.ids_2025.04.01-1_all.deb ...
2988s Unpacking usb.ids (2025.04.01-1) over (2025.01.14-1) ...
2988s Preparing to unpack .../33-usbutils_1%3a018-2_armhf.deb ...
2988s Unpacking usbutils (1:018-2) over (1:018-1) ...
2988s Preparing to unpack .../34-btrfs-progs_6.14-1_armhf.deb ...
2988s Unpacking btrfs-progs (6.14-1) over (6.12-1build1) ...
2988s Preparing to unpack .../35-cloud-init-base_25.2~1g7a0265d3-0ubuntu1_all.deb ...
2988s Unpacking cloud-init-base (25.2~1g7a0265d3-0ubuntu1) over (25.1.1-0ubuntu2) ...
2989s Preparing to unpack .../36-dpkg-dev_1.22.18ubuntu3_all.deb ...
2989s Unpacking dpkg-dev (1.22.18ubuntu3) over (1.22.18ubuntu2) ...
2989s Preparing to unpack .../37-libdpkg-perl_1.22.18ubuntu3_all.deb ...
2989s Unpacking libdpkg-perl (1.22.18ubuntu3) over (1.22.18ubuntu2) ...
2989s Preparing to unpack .../38-patch_2.8-1_armhf.deb ...
2989s Unpacking patch (2.8-1) over (2.7.6-7build3) ...
2989s Preparing to unpack .../39-libjcat1_0.2.3-1_armhf.deb ...
2989s Unpacking libjcat1:armhf (0.2.3-1) over (0.2.0-2build3) ...
2989s Preparing to unpack .../40-fwupd_2.0.8-3_armhf.deb ...
2989s Unpacking fwupd (2.0.8-3) over (2.0.7-1) ...
2990s dpkg: warning: unable to delete old directory '/etc/grub.d': Directory not empty
2990s Preparing to unpack .../41-libfwupd3_2.0.8-3_armhf.deb ...
2990s Unpacking libfwupd3:armhf (2.0.8-3) over (2.0.7-1) ...
2990s Preparing to unpack .../42-libmbim-proxy_1.32.0-1_armhf.deb ...
2990s Unpacking libmbim-proxy (1.32.0-1) over (1.31.2-0ubuntu4) ...
2990s Preparing to unpack .../43-libmbim-glib4_1.32.0-1_armhf.deb ...
2990s Unpacking libmbim-glib4:armhf (1.32.0-1) over (1.31.2-0ubuntu4) ...
2990s Preparing to unpack .../44-libmm-glib0_1.24.0-1_armhf.deb ...
2990s Unpacking libmm-glib0:armhf (1.24.0-1) over (1.23.4-0ubuntu3) ...
2990s Preparing to unpack .../45-libqmi-proxy_1.36.0-1_armhf.deb ...
2990s Unpacking libqmi-proxy (1.36.0-1) over (1.35.6-1) ...
2990s Preparing to unpack .../46-libqmi-glib5_1.36.0-1_armhf.deb ...
2990s Unpacking libqmi-glib5:armhf (1.36.0-1) over (1.35.6-1) ...
2990s Preparing to unpack .../47-gnupg-l10n_2.4.4-2ubuntu24_all.deb ...
2990s Unpacking gnupg-l10n (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ...
2990s Preparing to unpack .../48-htop_3.4.1-4_armhf.deb ...
2990s Unpacking htop (3.4.1-4) over (3.4.0-2) ...
2990s Preparing to unpack .../49-libftdi1-2_1.5-10_armhf.deb ...
2990s Unpacking libftdi1-2:armhf (1.5-10) over (1.5-8build1) ...
2990s Preparing to unpack .../50-libnvme1t64_1.13-2_armhf.deb ...
2990s Unpacking libnvme1t64 (1.13-2) over (1.11.1-2) ...
2990s Preparing to unpack .../51-python3-attr_25.3.0-1_all.deb ...
2990s Unpacking python3-attr (25.3.0-1) over (25.1.0-1) ...
2990s Preparing to unpack .../52-python3-wadllib_2.0.0-3_all.deb ...
2991s Unpacking python3-wadllib (2.0.0-3) over (2.0.0-2) ...
2991s Preparing to unpack .../53-python3-lazr.restfulclient_0.14.6-3_all.deb ...
2991s Unpacking python3-lazr.restfulclient (0.14.6-3) over (0.14.6-2) ...
2991s Preparing to unpack .../54-python3-more-itertools_10.7.0-1_all.deb ...
2991s Unpacking python3-more-itertools (10.7.0-1) over (10.6.0-1) ...
2991s Preparing to unpack .../55-python3-packaging_25.0-1_all.deb ...
2991s Unpacking python3-packaging (25.0-1) over (24.2-1) ...
2991s Preparing to unpack .../56-python3-s3transfer_0.11.4-1_all.deb ...
2991s Unpacking python3-s3transfer (0.11.4-1) over (0.11.2-2) ...
2991s Preparing to unpack .../57-sos_4.9.1-1_all.deb ...
2992s Unpacking sos (4.9.1-1) over (4.9.0-6) ...
2992s Preparing to unpack .../58-cloud-init_25.2~1g7a0265d3-0ubuntu1_all.deb ...
2992s Unpacking cloud-init (25.2~1g7a0265d3-0ubuntu1) over (25.1.1-0ubuntu2) ...
2992s Setting up motd-news-config (13.7ubuntu1) ...
2992s Setting up python3-more-itertools (10.7.0-1) ...
2992s Setting up python3-attr (25.3.0-1) ...
2992s Setting up liburcu8t64:armhf (0.15.2-2) ...
2992s Setting up gawk (1:5.3.2-1) ...
2992s Setting up distro-info-data (0.64) ...
2992s Setting up htop (3.4.1-4) ...
2992s Setting up openssh-client (1:9.9p1-3ubuntu3.1) ...
2992s Setting up btrfs-progs (6.14-1) ...
2992s Setting up python3-s3transfer (0.11.4-1) ...
2993s Setting up netcat-openbsd (1.229-1) ...
2993s Setting up libsensors-config (1:3.6.2-2) ...
2993s Installing new version of config file /etc/sensors3.conf ...
2993s Setting up libnghttp2-14:armhf (1.64.0-1.1) ...
2993s Setting up less (668-1) ...
2993s Setting up gettext-base (0.23.1-2) ...
2993s Setting up libnftnl11:armhf (1.2.9-1) ...
2993s Setting up libglib2.0-0t64:armhf (2.84.1-2) ...
2993s No schema files found: doing nothing.
2993s Setting up libglib2.0-data (2.84.1-2) ...
2993s Setting up python3-packaging (25.0-1) ...
2993s Setting up libnvme1t64 (1.13-2) ...
2993s Setting up libx11-data (2:1.8.12-1) ...
2993s Setting up gnupg-l10n (2.4.4-2ubuntu24) ...
2993s Setting up ed (1.21.1-1) ...
2993s Setting up python3-wadllib (2.0.0-3) ...
2993s Setting up libunistring5:armhf (1.3-2) ...
2993s Setting up patch (2.8-1) ...
2993s Setting up usb.ids (2025.04.01-1) ...
2993s Setting up dhcpcd-base (1:10.1.0-10) ...
2993s Installing new version of config file /etc/dhcpcd.conf ...
2993s Setting up gir1.2-glib-2.0:armhf (2.84.1-2) ...
2993s Setting up libsensors5:armhf (1:3.6.2-2) ...
2993s Setting up libdpkg-perl (1.22.18ubuntu3) ...
2993s Setting up nano (8.4-1) ...
2993s Installing new version of config file /etc/nanorc ...
2993s Setting up libnuma1:armhf (2.0.19-1) ...
2993s Setting up libmm-glib0:armhf (1.24.0-1) ...
2993s Setting up groff-base (1.23.0-8) ...
2993s Setting up gpgconf (2.4.4-2ubuntu24) ...
2993s Setting up libx11-6:armhf (2:1.8.12-1) ...
2993s Setting up netbase (6.5) ...
2993s Installing new version of config file /etc/ethertypes ...
2993s Installing new version of config file /etc/services ...
2993s Setting up libusb-1.0-0:armhf (2:1.0.28-1) ...
2993s Setting up python3-lazr.restfulclient (0.14.6-3) ...
2993s Setting up libgpg-error-l10n (1.51-4) ...
2993s Setting up libevdev2:armhf (1.13.4+dfsg-1) ...
2993s Setting up publicsuffix (20250328.1952-0.1) ...
2993s Setting up libxml2:armhf (2.12.7+dfsg+really2.9.14-0.4ubuntu0.1) ...
2993s Setting up ubuntu-pro-client (35.1ubuntu0) ...
2994s apparmor_parser: Unable to replace "ubuntu_pro_apt_news".  apparmor_parser: Access denied. You need policy admin privileges to manage profiles.
2994s 
2994s apparmor_parser: Unable to replace "apt_methods".  apparmor_parser: Access denied. You need policy admin privileges to manage profiles.
2994s 
2994s apparmor_parser: Unable to replace "ubuntu_pro_esm_cache".  apparmor_parser: Access denied. You need policy admin privileges to manage profiles.
2994s 
2996s Setting up iso-codes (4.18.0-1) ...
2996s Setting up gpg (2.4.4-2ubuntu24) ...
2996s Setting up libbpf1:armhf (1:1.5.0-3) ...
2996s Setting up libmbim-glib4:armhf (1.32.0-1) ...
2996s Setting up ethtool (1:6.14-2) ...
2996s Setting up gnupg-utils (2.4.4-2ubuntu24) ...
2996s Setting up ubuntu-pro-client-l10n (35.1ubuntu0) ...
2996s Setting up sos (4.9.1-1) ...
2996s Setting up openssh-sftp-server (1:9.9p1-3ubuntu3.1) ...
2996s Setting up gpg-agent (2.4.4-2ubuntu24) ...
2997s Setting up numactl (2.0.19-1) ...
2997s Setting up openssh-server (1:9.9p1-3ubuntu3.1) ...
2998s Setting up gpgsm (2.4.4-2ubuntu24) ...
2998s Setting up libmbim-proxy (1.32.0-1) ...
2998s Setting up man-db (2.13.1-1) ...
2999s Updating database of manual pages ...
3001s apparmor_parser: Unable to replace "/usr/bin/man".  apparmor_parser: Access denied. You need policy admin privileges to manage profiles.
3001s 
3001s man-db.service is a disabled or a static unit not running, not starting it.
3001s Setting up usbutils (1:018-2) ...
3001s Setting up cloud-init-base (25.2~1g7a0265d3-0ubuntu1) ...
3003s Setting up libjcat1:armhf (0.2.3-1) ...
3003s Setting up dpkg-dev (1.22.18ubuntu3) ...
3003s Setting up dirmngr (2.4.4-2ubuntu24) ...
3004s Setting up libftdi1-2:armhf (1.5-10) ...
3004s Setting up keyboxd (2.4.4-2ubuntu24) ...
3004s Setting up gnupg (2.4.4-2ubuntu24) ...
3004s Setting up cloud-init (25.2~1g7a0265d3-0ubuntu1) ...
3004s Setting up gpg-wks-client (2.4.4-2ubuntu24) ...
3004s Setting up libqmi-glib5:armhf (1.36.0-1) ...
3004s Setting up libfwupd3:armhf (2.0.8-3) ...
3004s Setting up libqmi-proxy (1.36.0-1) ...
3004s Setting up fwupd (2.0.8-3) ...
3004s fwupd-refresh.service is a disabled or a static unit not running, not starting it.
3004s fwupd.service is a disabled or a static unit not running, not starting it.
3004s Processing triggers for libc-bin (2.41-6ubuntu1) ...
3005s Processing triggers for rsyslog (8.2412.0-2ubuntu2) ...
3005s Processing triggers for ufw (0.36.2-9) ...
3005s Processing triggers for plymouth-theme-ubuntu-text (24.004.60-2ubuntu7) ...
3005s Processing triggers for dbus (1.16.2-2ubuntu1) ...
3005s Processing triggers for install-info (7.1.1-1) ...
3005s Processing triggers for initramfs-tools (0.147ubuntu1) ...
3007s Reading package lists...
3008s Building dependency tree...
3008s Reading state information...
3009s Starting pkgProblemResolver with broken count: 0
3009s Starting 2 pkgProblemResolver with broken count: 0
3009s Done
3010s Solving dependencies...
3011s The following packages will be REMOVED:
3011s   libsigsegv2*
3011s 0 upgraded, 0 newly installed, 1 to remove and 0 not upgraded.
3011s After this operation, 38.9 kB disk space will be freed.
3011s (Reading database ... 
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(Reading database ... 63966 files and directories currently installed.)
3011s Removing libsigsegv2:armhf (2.14-1ubuntu2) ...
3011s Processing triggers for libc-bin (2.41-6ubuntu1) ...
3013s autopkgtest [23:09:18]: rebooting testbed after setup commands that affected boot
3074s Reading package lists...
3075s Building dependency tree...
3075s Reading state information...
3075s Starting pkgProblemResolver with broken count: 0
3075s Starting 2 pkgProblemResolver with broken count: 0
3075s Done
3077s The following NEW packages will be installed:
3077s   libtcl8.6 python3-click yosys yosys-abc
3077s 0 upgraded, 4 newly installed, 0 to remove and 0 not upgraded.
3077s Need to get 9551 kB of archives.
3077s After this operation, 24.9 MB of additional disk space will be used.
3077s Get:1 http://ftpmaster.internal/ubuntu questing/main armhf libtcl8.6 armhf 8.6.16+dfsg-1 [909 kB]
3078s Get:2 http://ftpmaster.internal/ubuntu questing/main armhf python3-click all 8.2.0+0.really.8.1.8-1 [80.0 kB]
3078s Get:3 http://ftpmaster.internal/ubuntu questing/universe armhf yosys-abc armhf 0.33-5build2 [5336 kB]
3078s Get:4 http://ftpmaster.internal/ubuntu questing/universe armhf yosys armhf 0.33-5build2 [3225 kB]
3079s Fetched 9551 kB in 1s (9479 kB/s)
3079s Selecting previously unselected package libtcl8.6:armhf.
3079s (Reading database ... 
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(Reading database ... 63959 files and directories currently installed.)
3079s Preparing to unpack .../libtcl8.6_8.6.16+dfsg-1_armhf.deb ...
3079s Unpacking libtcl8.6:armhf (8.6.16+dfsg-1) ...
3079s Selecting previously unselected package python3-click.
3079s Preparing to unpack .../python3-click_8.2.0+0.really.8.1.8-1_all.deb ...
3079s Unpacking python3-click (8.2.0+0.really.8.1.8-1) ...
3079s Selecting previously unselected package yosys-abc.
3079s Preparing to unpack .../yosys-abc_0.33-5build2_armhf.deb ...
3079s Unpacking yosys-abc (0.33-5build2) ...
3079s Selecting previously unselected package yosys.
3079s Preparing to unpack .../yosys_0.33-5build2_armhf.deb ...
3079s Unpacking yosys (0.33-5build2) ...
3079s Setting up yosys-abc (0.33-5build2) ...
3079s Setting up python3-click (8.2.0+0.really.8.1.8-1) ...
3079s Setting up libtcl8.6:armhf (8.6.16+dfsg-1) ...
3079s Setting up yosys (0.33-5build2) ...
3080s Processing triggers for libc-bin (2.41-6ubuntu1) ...
3080s Processing triggers for man-db (2.13.1-1) ...
3100s autopkgtest [23:10:45]: test ice: [-----------------------
3102s 
3102s  /----------------------------------------------------------------------------\
3102s  |                                                                            |
3102s  |  yosys -- Yosys Open SYnthesis Suite                                       |
3102s  |                                                                            |
3102s  |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
3102s  |                                                                            |
3102s  |  Permission to use, copy, modify, and/or distribute this software for any  |
3102s  |  purpose with or without fee is hereby granted, provided that the above    |
3102s  |  copyright notice and this permission notice appear in all copies.         |
3102s  |                                                                            |
3102s  |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
3102s  |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
3102s  |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
3102s  |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
3102s  |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
3102s  |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
3102s  |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
3102s  |                                                                            |
3102s  \----------------------------------------------------------------------------/
3102s 
3102s  Yosys 0.33 (git sha1 2584903a060)
3102s 
3102s 
3102s -- Running command `read_verilog debian/tests/design_ice.v; synth_ice40 -blif /tmp/autopkgtest.iWd4A5/autopkgtest_tmp/design_ice.blif' --
3102s 
3102s 1. Executing Verilog-2005 frontend: debian/tests/design_ice.v
3102s Parsing Verilog input from `debian/tests/design_ice.v' to AST representation.
3102s Generating RTLIL representation for module `\design_ice'.
3102s Successfully finished Verilog frontend.
3102s 
3102s 2. Executing SYNTH_ICE40 pass.
3102s 
3102s 2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v
3102s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation.
3102s Generating RTLIL representation for module `\SB_IO'.
3102s Generating RTLIL representation for module `\SB_GB_IO'.
3102s Generating RTLIL representation for module `\SB_GB'.
3102s Generating RTLIL representation for module `\SB_LUT4'.
3102s Generating RTLIL representation for module `\SB_CARRY'.
3102s Generating RTLIL representation for module `\SB_DFF'.
3102s Generating RTLIL representation for module `\SB_DFFE'.
3102s Generating RTLIL representation for module `\SB_DFFSR'.
3102s Generating RTLIL representation for module `\SB_DFFR'.
3102s Generating RTLIL representation for module `\SB_DFFSS'.
3102s Generating RTLIL representation for module `\SB_DFFS'.
3102s Generating RTLIL representation for module `\SB_DFFESR'.
3102s Generating RTLIL representation for module `\SB_DFFER'.
3102s Generating RTLIL representation for module `\SB_DFFESS'.
3102s Generating RTLIL representation for module `\SB_DFFES'.
3102s Generating RTLIL representation for module `\SB_DFFN'.
3102s Generating RTLIL representation for module `\SB_DFFNE'.
3102s Generating RTLIL representation for module `\SB_DFFNSR'.
3102s Generating RTLIL representation for module `\SB_DFFNR'.
3102s Generating RTLIL representation for module `\SB_DFFNSS'.
3102s Generating RTLIL representation for module `\SB_DFFNS'.
3102s Generating RTLIL representation for module `\SB_DFFNESR'.
3102s Generating RTLIL representation for module `\SB_DFFNER'.
3102s Generating RTLIL representation for module `\SB_DFFNESS'.
3102s Generating RTLIL representation for module `\SB_DFFNES'.
3102s Generating RTLIL representation for module `\SB_RAM40_4K'.
3102s Generating RTLIL representation for module `\SB_RAM40_4KNR'.
3102s Generating RTLIL representation for module `\SB_RAM40_4KNW'.
3102s Generating RTLIL representation for module `\SB_RAM40_4KNRNW'.
3102s Generating RTLIL representation for module `\ICESTORM_LC'.
3102s Generating RTLIL representation for module `\SB_PLL40_CORE'.
3102s Generating RTLIL representation for module `\SB_PLL40_PAD'.
3102s Generating RTLIL representation for module `\SB_PLL40_2_PAD'.
3102s Generating RTLIL representation for module `\SB_PLL40_2F_CORE'.
3102s Generating RTLIL representation for module `\SB_PLL40_2F_PAD'.
3102s Generating RTLIL representation for module `\SB_WARMBOOT'.
3102s Generating RTLIL representation for module `\SB_SPRAM256KA'.
3102s Generating RTLIL representation for module `\SB_HFOSC'.
3102s Generating RTLIL representation for module `\SB_LFOSC'.
3102s Generating RTLIL representation for module `\SB_RGBA_DRV'.
3102s Generating RTLIL representation for module `\SB_LED_DRV_CUR'.
3102s Generating RTLIL representation for module `\SB_RGB_DRV'.
3102s Generating RTLIL representation for module `\SB_I2C'.
3102s Generating RTLIL representation for module `\SB_SPI'.
3102s Generating RTLIL representation for module `\SB_LEDDA_IP'.
3102s Generating RTLIL representation for module `\SB_FILTER_50NS'.
3102s Generating RTLIL representation for module `\SB_IO_I3C'.
3102s Generating RTLIL representation for module `\SB_IO_OD'.
3102s Generating RTLIL representation for module `\SB_MAC16'.
3102s Generating RTLIL representation for module `\ICESTORM_RAM'.
3102s Successfully finished Verilog frontend.
3102s 
3102s 2.2. Executing HIERARCHY pass (managing design hierarchy).
3102s 
3102s 2.2.1. Finding top of design hierarchy..
3102s root of   0 design levels: design_ice          
3102s Automatically selected design_ice as design top module.
3102s 
3102s 2.2.2. Analyzing design hierarchy..
3102s Top module:  \design_ice
3102s 
3102s 2.2.3. Analyzing design hierarchy..
3102s Top module:  \design_ice
3102s Removed 0 unused modules.
3102s 
3102s 2.3. Executing PROC pass (convert processes to netlists).
3102s 
3102s 2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
3102s Cleaned up 0 empty switches.
3102s 
3102s 2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
3102s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243 in module SB_DFFNES.
3102s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236 in module SB_DFFNESS.
3102s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232 in module SB_DFFNER.
3102s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225 in module SB_DFFNESR.
3102s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222 in module SB_DFFNS.
3102s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219 in module SB_DFFNSS.
3102s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216 in module SB_DFFNR.
3102s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213 in module SB_DFFNSR.
3102s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205 in module SB_DFFES.
3102s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198 in module SB_DFFESS.
3102s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194 in module SB_DFFER.
3102s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187 in module SB_DFFESR.
3102s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184 in module SB_DFFS.
3102s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181 in module SB_DFFSS.
3102s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178 in module SB_DFFR.
3102s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175 in module SB_DFFSR.
3102s Marked 1 switch rules as full_case in process $proc$debian/tests/design_ice.v:6$1 in module design_ice.
3102s Removed a total of 0 dead cases.
3102s 
3102s 2.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
3102s Removed 8 redundant assignments.
3102s Promoted 23 assignments to connections.
3102s 
3102s 2.3.4. Executing PROC_INIT pass (extract init attributes).
3102s Found init rule in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$246'.
3102s   Set init value: \Q = 1'0
3102s Found init rule in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$242'.
3102s   Set init value: \Q = 1'0
3102s Found init rule in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$235'.
3102s   Set init value: \Q = 1'0
3102s Found init rule in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$231'.
3102s   Set init value: \Q = 1'0
3102s Found init rule in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$224'.
3102s   Set init value: \Q = 1'0
3102s Found init rule in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$221'.
3102s   Set init value: \Q = 1'0
3102s Found init rule in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$218'.
3102s   Set init value: \Q = 1'0
3102s Found init rule in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$215'.
3102s   Set init value: \Q = 1'0
3102s Found init rule in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$212'.
3102s   Set init value: \Q = 1'0
3102s Found init rule in `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'.
3102s   Set init value: \Q = 1'0
3102s Found init rule in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'.
3102s   Set init value: \Q = 1'0
3102s Found init rule in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$204'.
3102s   Set init value: \Q = 1'0
3102s Found init rule in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$197'.
3102s   Set init value: \Q = 1'0
3102s Found init rule in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$193'.
3102s   Set init value: \Q = 1'0
3102s Found init rule in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$186'.
3102s   Set init value: \Q = 1'0
3102s Found init rule in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$183'.
3102s   Set init value: \Q = 1'0
3102s Found init rule in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$180'.
3102s   Set init value: \Q = 1'0
3102s Found init rule in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$177'.
3102s   Set init value: \Q = 1'0
3102s Found init rule in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$174'.
3102s   Set init value: \Q = 1'0
3102s Found init rule in `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'.
3102s   Set init value: \Q = 1'0
3102s Found init rule in `\design_ice.$proc$debian/tests/design_ice.v:3$2'.
3102s   Set init value: \ready = 1'0
3102s 
3102s 2.3.5. Executing PROC_ARST pass (detect async resets in processes).
3102s Found async reset \S in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'.
3102s Found async reset \R in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'.
3102s Found async reset \S in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222'.
3102s Found async reset \R in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216'.
3102s Found async reset \S in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'.
3102s Found async reset \R in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'.
3102s Found async reset \S in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184'.
3102s Found async reset \R in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178'.
3102s 
3102s 2.3.6. Executing PROC_ROM pass (convert switches to ROMs).
3102s Converted 0 switches.
3102s <suppressed ~19 debug messages>
3102s 
3102s 2.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
3102s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$246'.
3102s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'.
3102s      1/1: $0\Q[0:0]
3102s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$242'.
3102s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236'.
3102s      1/1: $0\Q[0:0]
3102s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$235'.
3102s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'.
3102s      1/1: $0\Q[0:0]
3102s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$231'.
3102s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225'.
3102s      1/1: $0\Q[0:0]
3102s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$224'.
3102s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222'.
3102s      1/1: $0\Q[0:0]
3102s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$221'.
3102s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219'.
3102s      1/1: $0\Q[0:0]
3102s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$218'.
3102s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216'.
3102s      1/1: $0\Q[0:0]
3102s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$215'.
3102s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213'.
3102s      1/1: $0\Q[0:0]
3102s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$212'.
3102s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$211'.
3102s      1/1: $0\Q[0:0]
3102s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'.
3102s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$209'.
3102s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'.
3102s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'.
3102s      1/1: $0\Q[0:0]
3102s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$204'.
3102s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198'.
3102s      1/1: $0\Q[0:0]
3102s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$197'.
3102s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'.
3102s      1/1: $0\Q[0:0]
3102s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$193'.
3102s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187'.
3102s      1/1: $0\Q[0:0]
3102s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$186'.
3102s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184'.
3102s      1/1: $0\Q[0:0]
3102s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$183'.
3102s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181'.
3102s      1/1: $0\Q[0:0]
3102s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$180'.
3102s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178'.
3102s      1/1: $0\Q[0:0]
3102s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$177'.
3102s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175'.
3102s      1/1: $0\Q[0:0]
3102s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$174'.
3102s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$173'.
3102s      1/1: $0\Q[0:0]
3102s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'.
3102s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$171'.
3102s Creating decoders for process `\design_ice.$proc$debian/tests/design_ice.v:3$2'.
3102s Creating decoders for process `\design_ice.$proc$debian/tests/design_ice.v:6$1'.
3102s      1/2: $0\value[0:0]
3102s      2/2: $0\ready[0:0]
3102s 
3102s 2.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).
3102s 
3102s 2.3.9. Executing PROC_DFF pass (convert process syncs to FFs).
3102s Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'.
3102s   created $adff cell `$procdff$433' with negative edge clock and positive level reset.
3102s Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236'.
3102s   created $dff cell `$procdff$434' with negative edge clock.
3102s Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'.
3102s   created $adff cell `$procdff$435' with negative edge clock and positive level reset.
3102s Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225'.
3102s   created $dff cell `$procdff$436' with negative edge clock.
3102s Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222'.
3102s   created $adff cell `$procdff$437' with negative edge clock and positive level reset.
3102s Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219'.
3102s   created $dff cell `$procdff$438' with negative edge clock.
3102s Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216'.
3102s   created $adff cell `$procdff$439' with negative edge clock and positive level reset.
3102s Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213'.
3102s   created $dff cell `$procdff$440' with negative edge clock.
3102s Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$211'.
3102s   created $dff cell `$procdff$441' with negative edge clock.
3102s Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$209'.
3102s   created $dff cell `$procdff$442' with negative edge clock.
3102s Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'.
3102s   created $adff cell `$procdff$443' with positive edge clock and positive level reset.
3102s Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198'.
3102s   created $dff cell `$procdff$444' with positive edge clock.
3102s Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'.
3102s   created $adff cell `$procdff$445' with positive edge clock and positive level reset.
3102s Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187'.
3102s   created $dff cell `$procdff$446' with positive edge clock.
3102s Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184'.
3102s   created $adff cell `$procdff$447' with positive edge clock and positive level reset.
3102s Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181'.
3102s   created $dff cell `$procdff$448' with positive edge clock.
3102s Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178'.
3102s   created $adff cell `$procdff$449' with positive edge clock and positive level reset.
3102s Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175'.
3102s   created $dff cell `$procdff$450' with positive edge clock.
3102s Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$173'.
3102s   created $dff cell `$procdff$451' with positive edge clock.
3102s Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$171'.
3102s   created $dff cell `$procdff$452' with positive edge clock.
3102s Creating register for signal `\design_ice.\ready' using process `\design_ice.$proc$debian/tests/design_ice.v:6$1'.
3102s   created $dff cell `$procdff$453' with positive edge clock.
3102s Creating register for signal `\design_ice.\value' using process `\design_ice.$proc$debian/tests/design_ice.v:6$1'.
3102s   created $dff cell `$procdff$454' with positive edge clock.
3102s 
3102s 2.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
3102s 
3102s 2.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
3102s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$246'.
3102s Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'.
3102s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'.
3102s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$242'.
3102s Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236'.
3102s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236'.
3102s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$235'.
3102s Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'.
3102s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'.
3102s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$231'.
3102s Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225'.
3102s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225'.
3102s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$224'.
3102s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222'.
3102s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$221'.
3102s Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219'.
3102s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219'.
3102s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$218'.
3102s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216'.
3102s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$215'.
3102s Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213'.
3102s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213'.
3102s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$212'.
3102s Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$211'.
3102s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$211'.
3102s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'.
3102s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$209'.
3102s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'.
3102s Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'.
3102s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'.
3102s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$204'.
3102s Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198'.
3102s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198'.
3102s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$197'.
3102s Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'.
3102s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'.
3102s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$193'.
3102s Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187'.
3102s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187'.
3102s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$186'.
3102s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184'.
3102s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$183'.
3102s Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181'.
3102s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181'.
3102s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$180'.
3102s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178'.
3102s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$177'.
3102s Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175'.
3102s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175'.
3102s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$174'.
3102s Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$173'.
3102s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$173'.
3102s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'.
3102s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$171'.
3102s Removing empty process `design_ice.$proc$debian/tests/design_ice.v:3$2'.
3102s Found and cleaned up 1 empty switch in `\design_ice.$proc$debian/tests/design_ice.v:6$1'.
3102s Removing empty process `design_ice.$proc$debian/tests/design_ice.v:6$1'.
3102s Cleaned up 19 empty switches.
3102s 
3102s 2.3.12. Executing OPT_EXPR pass (perform const folding).
3102s Optimizing module design_ice.
3102s 
3102s 2.4. Executing FLATTEN pass (flatten design).
3102s 
3102s 2.5. Executing TRIBUF pass.
3102s 
3102s 2.6. Executing DEMINOUT pass (demote inout ports to input or output).
3102s 
3102s 2.7. Executing OPT_EXPR pass (perform const folding).
3102s Optimizing module design_ice.
3102s 
3102s 2.8. Executing OPT_CLEAN pass (remove unused cells and wires).
3102s Finding unused cells or wires in module \design_ice..
3102s Removed 0 unused cells and 5 unused wires.
3102s <suppressed ~1 debug messages>
3102s 
3102s 2.9. Executing CHECK pass (checking for obvious problems).
3102s Checking module design_ice...
3102s Found and reported 0 problems.
3102s 
3102s 2.10. Executing OPT pass (performing simple optimizations).
3102s 
3102s 2.10.1. Executing OPT_EXPR pass (perform const folding).
3102s Optimizing module design_ice.
3102s 
3102s 2.10.2. Executing OPT_MERGE pass (detect identical cells).
3102s Finding identical cells in module `\design_ice'.
3102s Removed a total of 0 cells.
3102s 
3102s 2.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
3102s Running muxtree optimizer on module \design_ice..
3102s   Creating internal representation of mux trees.
3102s   Evaluating internal representation of mux trees.
3102s       Replacing known input bits on port B of cell $procmux$431: \ready -> 1'1
3102s   Analyzing evaluation results.
3102s Removed 0 multiplexer ports.
3102s <suppressed ~2 debug messages>
3102s 
3102s 2.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
3102s   Optimizing cells in module \design_ice.
3102s   Optimizing cells in module \design_ice.
3102s Performed a total of 1 changes.
3102s 
3102s 2.10.5. Executing OPT_MERGE pass (detect identical cells).
3102s Finding identical cells in module `\design_ice'.
3102s Removed a total of 0 cells.
3102s 
3102s 2.10.6. Executing OPT_DFF pass (perform DFF optimizations).
3102s 
3102s 2.10.7. Executing OPT_CLEAN pass (remove unused cells and wires).
3102s Finding unused cells or wires in module \design_ice..
3102s Removed 0 unused cells and 1 unused wires.
3102s <suppressed ~1 debug messages>
3102s 
3102s 2.10.8. Executing OPT_EXPR pass (perform const folding).
3102s Optimizing module design_ice.
3102s 
3102s 2.10.9. Rerunning OPT passes. (Maybe there is more to do..)
3102s 
3102s 2.10.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
3102s Running muxtree optimizer on module \design_ice..
3102s   Creating internal representation of mux trees.
3102s   Evaluating internal representation of mux trees.
3102s   Analyzing evaluation results.
3102s Removed 0 multiplexer ports.
3102s <suppressed ~1 debug messages>
3102s 
3102s 2.10.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
3102s   Optimizing cells in module \design_ice.
3102s Performed a total of 0 changes.
3102s 
3102s 2.10.12. Executing OPT_MERGE pass (detect identical cells).
3102s Finding identical cells in module `\design_ice'.
3102s Removed a total of 0 cells.
3102s 
3102s 2.10.13. Executing OPT_DFF pass (perform DFF optimizations).
3102s 
3102s 2.10.14. Executing OPT_CLEAN pass (remove unused cells and wires).
3102s Finding unused cells or wires in module \design_ice..
3102s 
3102s 2.10.15. Executing OPT_EXPR pass (perform const folding).
3102s Optimizing module design_ice.
3102s 
3102s 2.10.16. Finished OPT passes. (There is nothing left to do.)
3102s 
3102s 2.11. Executing FSM pass (extract and optimize FSM).
3102s 
3102s 2.11.1. Executing FSM_DETECT pass (finding FSMs in design).
3102s 
3102s 2.11.2. Executing FSM_EXTRACT pass (extracting FSM from design).
3102s 
3102s 2.11.3. Executing FSM_OPT pass (simple optimizations of FSMs).
3102s 
3102s 2.11.4. Executing OPT_CLEAN pass (remove unused cells and wires).
3102s Finding unused cells or wires in module \design_ice..
3102s 
3102s 2.11.5. Executing FSM_OPT pass (simple optimizations of FSMs).
3102s 
3102s 2.11.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
3102s 
3102s 2.11.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
3102s 
3102s 2.11.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
3102s 
3102s 2.12. Executing OPT pass (performing simple optimizations).
3102s 
3102s 2.12.1. Executing OPT_EXPR pass (perform const folding).
3102s Optimizing module design_ice.
3102s 
3102s 2.12.2. Executing OPT_MERGE pass (detect identical cells).
3102s Finding identical cells in module `\design_ice'.
3102s Removed a total of 0 cells.
3102s 
3102s 2.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
3102s Running muxtree optimizer on module \design_ice..
3102s   Creating internal representation of mux trees.
3102s   Evaluating internal representation of mux trees.
3102s   Analyzing evaluation results.
3102s Removed 0 multiplexer ports.
3102s <suppressed ~1 debug messages>
3102s 
3102s 2.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
3102s   Optimizing cells in module \design_ice.
3102s Performed a total of 0 changes.
3102s 
3102s 2.12.5. Executing OPT_MERGE pass (detect identical cells).
3102s Finding identical cells in module `\design_ice'.
3102s Removed a total of 0 cells.
3102s 
3102s 2.12.6. Executing OPT_DFF pass (perform DFF optimizations).
3102s Adding EN signal on $procdff$454 ($dff) from module design_ice (D = \I1, Q = \value).
3102s 
3102s 2.12.7. Executing OPT_CLEAN pass (remove unused cells and wires).
3102s Finding unused cells or wires in module \design_ice..
3102s Removed 1 unused cells and 1 unused wires.
3102s <suppressed ~2 debug messages>
3102s 
3102s 2.12.8. Executing OPT_EXPR pass (perform const folding).
3102s Optimizing module design_ice.
3102s 
3102s 2.12.9. Rerunning OPT passes. (Maybe there is more to do..)
3102s 
3102s 2.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
3102s Running muxtree optimizer on module \design_ice..
3102s   Creating internal representation of mux trees.
3102s   No muxes found in this module.
3102s Removed 0 multiplexer ports.
3102s 
3102s 2.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
3102s   Optimizing cells in module \design_ice.
3102s Performed a total of 0 changes.
3102s 
3102s 2.12.12. Executing OPT_MERGE pass (detect identical cells).
3102s Finding identical cells in module `\design_ice'.
3102s Removed a total of 0 cells.
3102s 
3102s 2.12.13. Executing OPT_DFF pass (perform DFF optimizations).
3102s 
3102s 2.12.14. Executing OPT_CLEAN pass (remove unused cells and wires).
3102s Finding unused cells or wires in module \design_ice..
3102s 
3102s 2.12.15. Executing OPT_EXPR pass (perform const folding).
3102s Optimizing module design_ice.
3102s 
3102s 2.12.16. Finished OPT passes. (There is nothing left to do.)
3102s 
3102s 2.13. Executing WREDUCE pass (reducing word size of cells).
3102s 
3102s 2.14. Executing PEEPOPT pass (run peephole optimizers).
3102s 
3102s 2.15. Executing OPT_CLEAN pass (remove unused cells and wires).
3102s Finding unused cells or wires in module \design_ice..
3102s 
3102s 2.16. Executing SHARE pass (SAT-based resource sharing).
3102s 
3102s 2.17. Executing TECHMAP pass (map to technology primitives).
3102s 
3102s 2.17.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v
3102s Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation.
3102s Generating RTLIL representation for module `\_90_lut_cmp_'.
3102s Successfully finished Verilog frontend.
3102s 
3102s 2.17.2. Continuing TECHMAP pass.
3102s No more expansions possible.
3102s <suppressed ~6 debug messages>
3102s 
3102s 2.18. Executing OPT_EXPR pass (perform const folding).
3102s Optimizing module design_ice.
3102s 
3102s 2.19. Executing OPT_CLEAN pass (remove unused cells and wires).
3102s Finding unused cells or wires in module \design_ice..
3102s 
3102s 2.20. Executing ALUMACC pass (create $alu and $macc cells).
3102s Extracting $alu and $macc cells in module design_ice:
3102s   created 0 $alu and 0 $macc cells.
3102s 
3102s 2.21. Executing OPT pass (performing simple optimizations).
3102s 
3102s 2.21.1. Executing OPT_EXPR pass (perform const folding).
3102s Optimizing module design_ice.
3102s 
3102s 2.21.2. Executing OPT_MERGE pass (detect identical cells).
3102s Finding identical cells in module `\design_ice'.
3102s Removed a total of 0 cells.
3102s 
3102s 2.21.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
3102s Running muxtree optimizer on module \design_ice..
3102s   Creating internal representation of mux trees.
3102s   No muxes found in this module.
3102s Removed 0 multiplexer ports.
3102s 
3102s 2.21.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
3102s   Optimizing cells in module \design_ice.
3102s Performed a total of 0 changes.
3102s 
3102s 2.21.5. Executing OPT_MERGE pass (detect identical cells).
3102s Finding identical cells in module `\design_ice'.
3102s Removed a total of 0 cells.
3102s 
3102s 2.21.6. Executing OPT_DFF pass (perform DFF optimizations).
3102s 
3102s 2.21.7. Executing OPT_CLEAN pass (remove unused cells and wires).
3102s Finding unused cells or wires in module \design_ice..
3102s 
3102s 2.21.8. Executing OPT_EXPR pass (perform const folding).
3102s Optimizing module design_ice.
3102s 
3102s 2.21.9. Finished OPT passes. (There is nothing left to do.)
3102s 
3102s 2.22. Executing MEMORY pass.
3102s 
3102s 2.22.1. Executing OPT_MEM pass (optimize memories).
3102s Performed a total of 0 transformations.
3102s 
3102s 2.22.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
3102s Performed a total of 0 transformations.
3102s 
3102s 2.22.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
3102s 
3102s 2.22.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
3102s 
3102s 2.22.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
3102s 
3102s 2.22.6. Executing OPT_CLEAN pass (remove unused cells and wires).
3102s Finding unused cells or wires in module \design_ice..
3102s 
3102s 2.22.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
3102s 
3102s 2.22.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
3102s Performed a total of 0 transformations.
3102s 
3102s 2.22.9. Executing OPT_CLEAN pass (remove unused cells and wires).
3102s Finding unused cells or wires in module \design_ice..
3102s 
3102s 2.22.10. Executing MEMORY_COLLECT pass (generating $mem cells).
3102s 
3102s 2.23. Executing OPT_CLEAN pass (remove unused cells and wires).
3102s Finding unused cells or wires in module \design_ice..
3102s 
3102s 2.24. Executing MEMORY_LIBMAP pass (mapping memories to cells).
3102s 
3102s 2.25. Executing TECHMAP pass (map to technology primitives).
3102s 
3102s 2.25.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v
3103s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation.
3103s Generating RTLIL representation for module `\$__ICE40_RAM4K_'.
3103s Successfully finished Verilog frontend.
3103s 
3103s 2.25.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/spram_map.v
3103s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/spram_map.v' to AST representation.
3103s Generating RTLIL representation for module `\$__ICE40_SPRAM_'.
3103s Successfully finished Verilog frontend.
3103s 
3103s 2.25.3. Continuing TECHMAP pass.
3103s No more expansions possible.
3103s <suppressed ~4 debug messages>
3103s 
3103s 2.26. Executing ICE40_BRAMINIT pass.
3103s 
3103s 2.27. Executing OPT pass (performing simple optimizations).
3103s 
3103s 2.27.1. Executing OPT_EXPR pass (perform const folding).
3103s Optimizing module design_ice.
3103s 
3103s 2.27.2. Executing OPT_MERGE pass (detect identical cells).
3103s Finding identical cells in module `\design_ice'.
3103s Removed a total of 0 cells.
3103s 
3103s 2.27.3. Executing OPT_DFF pass (perform DFF optimizations).
3103s 
3103s 2.27.4. Executing OPT_CLEAN pass (remove unused cells and wires).
3103s Finding unused cells or wires in module \design_ice..
3103s 
3103s 2.27.5. Finished fast OPT passes.
3103s 
3103s 2.28. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
3103s 
3103s 2.29. Executing OPT pass (performing simple optimizations).
3103s 
3103s 2.29.1. Executing OPT_EXPR pass (perform const folding).
3103s Optimizing module design_ice.
3103s 
3103s 2.29.2. Executing OPT_MERGE pass (detect identical cells).
3103s Finding identical cells in module `\design_ice'.
3103s Removed a total of 0 cells.
3103s 
3103s 2.29.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
3103s Running muxtree optimizer on module \design_ice..
3103s   Creating internal representation of mux trees.
3103s   No muxes found in this module.
3103s Removed 0 multiplexer ports.
3103s 
3103s 2.29.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
3103s   Optimizing cells in module \design_ice.
3103s Performed a total of 0 changes.
3103s 
3103s 2.29.5. Executing OPT_MERGE pass (detect identical cells).
3103s Finding identical cells in module `\design_ice'.
3103s Removed a total of 0 cells.
3103s 
3103s 2.29.6. Executing OPT_DFF pass (perform DFF optimizations).
3103s 
3103s 2.29.7. Executing OPT_CLEAN pass (remove unused cells and wires).
3103s Finding unused cells or wires in module \design_ice..
3103s 
3103s 2.29.8. Executing OPT_EXPR pass (perform const folding).
3103s Optimizing module design_ice.
3103s 
3103s 2.29.9. Finished OPT passes. (There is nothing left to do.)
3103s 
3103s 2.30. Executing ICE40_WRAPCARRY pass (wrap carries).
3103s 
3103s 2.31. Executing TECHMAP pass (map to technology primitives).
3103s 
3103s 2.31.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v
3103s Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation.
3103s Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
3103s Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
3103s Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
3103s Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
3103s Generating RTLIL representation for module `\_90_simplemap_various'.
3103s Generating RTLIL representation for module `\_90_simplemap_registers'.
3103s Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
3103s Generating RTLIL representation for module `\_90_shift_shiftx'.
3103s Generating RTLIL representation for module `\_90_fa'.
3103s Generating RTLIL representation for module `\_90_lcu'.
3103s Generating RTLIL representation for module `\_90_alu'.
3103s Generating RTLIL representation for module `\_90_macc'.
3103s Generating RTLIL representation for module `\_90_alumacc'.
3103s Generating RTLIL representation for module `\$__div_mod_u'.
3103s Generating RTLIL representation for module `\$__div_mod_trunc'.
3103s Generating RTLIL representation for module `\_90_div'.
3103s Generating RTLIL representation for module `\_90_mod'.
3103s Generating RTLIL representation for module `\$__div_mod_floor'.
3103s Generating RTLIL representation for module `\_90_divfloor'.
3103s Generating RTLIL representation for module `\_90_modfloor'.
3103s Generating RTLIL representation for module `\_90_pow'.
3103s Generating RTLIL representation for module `\_90_pmux'.
3103s Generating RTLIL representation for module `\_90_demux'.
3103s Generating RTLIL representation for module `\_90_lut'.
3103s Successfully finished Verilog frontend.
3103s 
3103s 2.31.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v
3103s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation.
3103s Generating RTLIL representation for module `\_80_ice40_alu'.
3103s Successfully finished Verilog frontend.
3103s 
3103s 2.31.3. Continuing TECHMAP pass.
3103s Using extmapper simplemap for cells of type $dffe.
3103s Using extmapper simplemap for cells of type $dff.
3103s No more expansions possible.
3103s <suppressed ~75 debug messages>
3103s 
3103s 2.32. Executing OPT pass (performing simple optimizations).
3103s 
3103s 2.32.1. Executing OPT_EXPR pass (perform const folding).
3103s Optimizing module design_ice.
3103s 
3103s 2.32.2. Executing OPT_MERGE pass (detect identical cells).
3103s Finding identical cells in module `\design_ice'.
3103s Removed a total of 0 cells.
3103s 
3103s 2.32.3. Executing OPT_DFF pass (perform DFF optimizations).
3103s 
3103s 2.32.4. Executing OPT_CLEAN pass (remove unused cells and wires).
3103s Finding unused cells or wires in module \design_ice..
3103s 
3103s 2.32.5. Finished fast OPT passes.
3103s 
3103s 2.33. Executing ICE40_OPT pass (performing simple optimizations).
3103s 
3103s 2.33.1. Running ICE40 specific optimizations.
3103s 
3103s 2.33.2. Executing OPT_EXPR pass (perform const folding).
3103s Optimizing module design_ice.
3103s 
3103s 2.33.3. Executing OPT_MERGE pass (detect identical cells).
3103s Finding identical cells in module `\design_ice'.
3103s Removed a total of 0 cells.
3103s 
3103s 2.33.4. Executing OPT_DFF pass (perform DFF optimizations).
3103s 
3103s 2.33.5. Executing OPT_CLEAN pass (remove unused cells and wires).
3103s Finding unused cells or wires in module \design_ice..
3103s 
3103s 2.33.6. Finished OPT passes. (There is nothing left to do.)
3103s 
3103s 2.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
3103s 
3103s 2.35. Executing TECHMAP pass (map to technology primitives).
3103s 
3103s 2.35.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v
3103s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation.
3103s Generating RTLIL representation for module `\$_DFF_N_'.
3103s Generating RTLIL representation for module `\$_DFF_P_'.
3103s Generating RTLIL representation for module `\$_DFFE_NP_'.
3103s Generating RTLIL representation for module `\$_DFFE_PP_'.
3103s Generating RTLIL representation for module `\$_DFF_NP0_'.
3103s Generating RTLIL representation for module `\$_DFF_NP1_'.
3103s Generating RTLIL representation for module `\$_DFF_PP0_'.
3103s Generating RTLIL representation for module `\$_DFF_PP1_'.
3103s Generating RTLIL representation for module `\$_DFFE_NP0P_'.
3103s Generating RTLIL representation for module `\$_DFFE_NP1P_'.
3103s Generating RTLIL representation for module `\$_DFFE_PP0P_'.
3103s Generating RTLIL representation for module `\$_DFFE_PP1P_'.
3103s Generating RTLIL representation for module `\$_SDFF_NP0_'.
3103s Generating RTLIL representation for module `\$_SDFF_NP1_'.
3103s Generating RTLIL representation for module `\$_SDFF_PP0_'.
3103s Generating RTLIL representation for module `\$_SDFF_PP1_'.
3103s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
3103s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
3103s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
3103s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
3103s Successfully finished Verilog frontend.
3103s 
3103s 2.35.2. Continuing TECHMAP pass.
3103s Using template \$_DFF_P_ for cells of type $_DFF_P_.
3103s Using template \$_DFFE_PP_ for cells of type $_DFFE_PP_.
3103s No more expansions possible.
3103s <suppressed ~24 debug messages>
3103s 
3103s 2.36. Executing OPT_EXPR pass (perform const folding).
3103s Optimizing module design_ice.
3103s 
3103s 2.37. Executing SIMPLEMAP pass (map simple cells to gate primitives).
3103s 
3103s 2.38. Executing ICE40_OPT pass (performing simple optimizations).
3103s 
3103s 2.38.1. Running ICE40 specific optimizations.
3103s 
3103s 2.38.2. Executing OPT_EXPR pass (perform const folding).
3103s Optimizing module design_ice.
3103s 
3103s 2.38.3. Executing OPT_MERGE pass (detect identical cells).
3103s Finding identical cells in module `\design_ice'.
3103s Removed a total of 0 cells.
3103s 
3103s 2.38.4. Executing OPT_DFF pass (perform DFF optimizations).
3103s 
3103s 2.38.5. Executing OPT_CLEAN pass (remove unused cells and wires).
3103s Finding unused cells or wires in module \design_ice..
3103s Removed 0 unused cells and 9 unused wires.
3103s <suppressed ~1 debug messages>
3103s 
3103s 2.38.6. Rerunning OPT passes. (Removed registers in this run.)
3103s 
3103s 2.38.7. Running ICE40 specific optimizations.
3103s 
3103s 2.38.8. Executing OPT_EXPR pass (perform const folding).
3103s Optimizing module design_ice.
3103s 
3103s 2.38.9. Executing OPT_MERGE pass (detect identical cells).
3103s Finding identical cells in module `\design_ice'.
3103s Removed a total of 0 cells.
3103s 
3103s 2.38.10. Executing OPT_DFF pass (perform DFF optimizations).
3103s 
3103s 2.38.11. Executing OPT_CLEAN pass (remove unused cells and wires).
3103s Finding unused cells or wires in module \design_ice..
3103s 
3103s 2.38.12. Finished OPT passes. (There is nothing left to do.)
3103s 
3103s 2.39. Executing TECHMAP pass (map to technology primitives).
3103s 
3103s 2.39.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v
3103s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation.
3103s Generating RTLIL representation for module `\$_DLATCH_N_'.
3103s Generating RTLIL representation for module `\$_DLATCH_P_'.
3103s Successfully finished Verilog frontend.
3103s 
3103s 2.39.2. Continuing TECHMAP pass.
3103s No more expansions possible.
3103s <suppressed ~4 debug messages>
3103s 
3103s 2.40. Executing ABC pass (technology mapping using ABC).
3103s 
3103s 2.40.1. Extracting gate netlist of module `\design_ice' to `<abc-temp-dir>/input.blif'..
3103s Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
3103s Don't call ABC as there is nothing to map.
3103s Removing temp directory.
3103s 
3103s 2.41. Executing ICE40_WRAPCARRY pass (wrap carries).
3103s 
3103s 2.42. Executing TECHMAP pass (map to technology primitives).
3103s 
3103s 2.42.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v
3103s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation.
3103s Generating RTLIL representation for module `\$_DFF_N_'.
3103s Generating RTLIL representation for module `\$_DFF_P_'.
3103s Generating RTLIL representation for module `\$_DFFE_NP_'.
3103s Generating RTLIL representation for module `\$_DFFE_PP_'.
3103s Generating RTLIL representation for module `\$_DFF_NP0_'.
3103s Generating RTLIL representation for module `\$_DFF_NP1_'.
3103s Generating RTLIL representation for module `\$_DFF_PP0_'.
3103s Generating RTLIL representation for module `\$_DFF_PP1_'.
3103s Generating RTLIL representation for module `\$_DFFE_NP0P_'.
3103s Generating RTLIL representation for module `\$_DFFE_NP1P_'.
3103s Generating RTLIL representation for module `\$_DFFE_PP0P_'.
3103s Generating RTLIL representation for module `\$_DFFE_PP1P_'.
3103s Generating RTLIL representation for module `\$_SDFF_NP0_'.
3103s Generating RTLIL representation for module `\$_SDFF_NP1_'.
3103s Generating RTLIL representation for module `\$_SDFF_PP0_'.
3103s Generating RTLIL representation for module `\$_SDFF_PP1_'.
3103s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
3103s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
3103s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
3103s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
3103s Successfully finished Verilog frontend.
3103s 
3103s 2.42.2. Continuing TECHMAP pass.
3103s No more expansions possible.
3103s <suppressed ~22 debug messages>
3103s 
3103s 2.43. Executing OPT_LUT pass (optimize LUTs).
3103s Discovering LUTs.
3103s Number of LUTs:        0
3103s   with \SB_CARRY    (#0)    0
3103s   with \SB_CARRY    (#1)    0
3103s 
3103s Eliminating LUTs.
3103s Number of LUTs:        0
3103s   with \SB_CARRY    (#0)    0
3103s   with \SB_CARRY    (#1)    0
3103s 
3103s Combining LUTs.
3103s Number of LUTs:        0
3103s   with \SB_CARRY    (#0)    0
3103s   with \SB_CARRY    (#1)    0
3103s 
3103s Eliminated 0 LUTs.
3103s Combined 0 LUTs.
3103s 
3103s 2.44. Executing TECHMAP pass (map to technology primitives).
3103s 
3103s 2.44.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v
3103s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation.
3103s Generating RTLIL representation for module `\$lut'.
3103s Successfully finished Verilog frontend.
3103s 
3103s 2.44.2. Continuing TECHMAP pass.
3103s No more expansions possible.
3103s <suppressed ~3 debug messages>
3103s 
3103s 2.45. Executing AUTONAME pass.
3103s Renamed 2 objects in module design_ice (2 iterations).
3103s <suppressed ~2 debug messages>
3103s 
3103s 2.46. Executing HIERARCHY pass (managing design hierarchy).
3103s 
3103s 2.46.1. Analyzing design hierarchy..
3103s Top module:  \design_ice
3103s 
3103s 2.46.2. Analyzing design hierarchy..
3103s Top module:  \design_ice
3103s Removed 0 unused modules.
3103s 
3103s 2.47. Printing statistics.
3103s 
3103s === design_ice ===
3103s 
3103s    Number of wires:                  5
3103s    Number of wire bits:              5
3103s    Number of public wires:           5
3103s    Number of public wire bits:       5
3103s    Number of memories:               0
3103s    Number of memory bits:            0
3103s    Number of processes:              0
3103s    Number of cells:                  2
3103s      SB_DFF                          1
3103s      SB_DFFE                         1
3103s 
3103s 2.48. Executing CHECK pass (checking for obvious problems).
3103s Checking module design_ice...
3103s Found and reported 0 problems.
3103s 
3103s 2.49. Executing BLIF backend.
3103s 
3103s End of script. Logfile hash: 6865b0492f, CPU: user 1.01s system 0.02s, MEM: 13.88 MB peak
3103s Yosys 0.33 (git sha1 2584903a060)
3103s Time spent: 69% 13x read_verilog (0 sec), 8% 1x synth_ice40 (0 sec), ...
3104s autopkgtest [23:10:49]: test ice: -----------------------]
3107s autopkgtest [23:10:52]: test ice:  - - - - - - - - - - results - - - - - - - - - -
3107s ice                  PASS
3111s autopkgtest [23:10:56]: test smtbc: preparing testbed
3112s Reading package lists...
3113s Building dependency tree...
3113s Reading state information...
3113s Starting pkgProblemResolver with broken count: 0
3114s Starting 2 pkgProblemResolver with broken count: 0
3114s Done
3115s 0 upgraded, 0 newly installed, 0 to remove and 0 not upgraded.
3122s autopkgtest [23:11:07]: test smtbc: [-----------------------
3125s autopkgtest [23:11:10]: test smtbc: -----------------------]
3129s smtbc                PASS
3129s autopkgtest [23:11:14]: test smtbc:  - - - - - - - - - - results - - - - - - - - - -
3132s autopkgtest [23:11:17]: @@@@@@@@@@@@@@@@@@@@ summary
3132s yosys-testsuite      PASS
3132s ice                  PASS
3132s smtbc                PASS