0s autopkgtest [22:18:31]: starting date and time: 2025-05-05 22:18:31+0000 0s autopkgtest [22:18:31]: git checkout: 9986aa8c Merge branch 'skia/fix_network_interface' into 'ubuntu/production' 0s autopkgtest [22:18:31]: host juju-7f2275-prod-proposed-migration-environment-15; command line: /home/ubuntu/autopkgtest/runner/autopkgtest --output-dir /tmp/autopkgtest-work.hdoja7pz/out --timeout-copy=6000 --setup-commands /home/ubuntu/autopkgtest-cloud/worker-config-production/setup-canonical.sh --apt-pocket=proposed=src:gawk --apt-upgrade yosys --timeout-short=300 --timeout-copy=20000 --timeout-build=20000 --env=ADT_TEST_TRIGGERS=gawk/1:5.3.2-1 -- ssh -s /home/ubuntu/autopkgtest/ssh-setup/nova -- --flavor autopkgtest --security-groups autopkgtest-juju-7f2275-prod-proposed-migration-environment-15@bos03-arm64-13.secgroup --name adt-questing-arm64-yosys-20250505-221831-juju-7f2275-prod-proposed-migration-environment-15-aea8ce69-126c-4081-b944-b7ebfd847f66 --image adt/ubuntu-questing-arm64-server --keyname testbed-juju-7f2275-prod-proposed-migration-environment-15 --net-id=net_prod-proposed-migration -e TERM=linux --mirror=http://ftpmaster.internal/ubuntu/ 123s autopkgtest [22:20:34]: testbed dpkg architecture: arm64 123s autopkgtest [22:20:34]: testbed apt version: 3.0.0 124s autopkgtest [22:20:35]: @@@@@@@@@@@@@@@@@@@@ test bed setup 124s autopkgtest [22:20:35]: testbed release detected to be: None 125s autopkgtest [22:20:36]: updating testbed package index (apt update) 125s Get:1 http://ftpmaster.internal/ubuntu questing-proposed InRelease [110 kB] 125s Hit:2 http://ftpmaster.internal/ubuntu questing InRelease 125s Hit:3 http://ftpmaster.internal/ubuntu questing-updates InRelease 125s Hit:4 http://ftpmaster.internal/ubuntu questing-security InRelease 126s Get:5 http://ftpmaster.internal/ubuntu questing-proposed/multiverse Sources [30.0 kB] 126s Get:6 http://ftpmaster.internal/ubuntu questing-proposed/main Sources [86.1 kB] 126s Get:7 http://ftpmaster.internal/ubuntu questing-proposed/universe Sources [818 kB] 126s Get:8 http://ftpmaster.internal/ubuntu questing-proposed/main arm64 Packages [116 kB] 126s Get:9 http://ftpmaster.internal/ubuntu questing-proposed/universe arm64 Packages [892 kB] 126s Get:10 http://ftpmaster.internal/ubuntu questing-proposed/multiverse arm64 Packages [18.0 kB] 126s Fetched 2070 kB in 1s (2116 kB/s) 128s Reading package lists... 128s autopkgtest [22:20:39]: upgrading testbed (apt dist-upgrade and autopurge) 128s Reading package lists... 129s Building dependency tree... 129s Reading state information... 129s Calculating upgrade...Starting pkgProblemResolver with broken count: 0 129s Starting 2 pkgProblemResolver with broken count: 0 129s Done 130s Entering ResolveByKeep 130s 131s Calculating upgrade... 131s The following package was automatically installed and is no longer required: 131s libsigsegv2 131s Use 'sudo apt autoremove' to remove it. 131s The following packages will be upgraded: 131s dhcpcd-base dirmngr gawk gir1.2-glib-2.0 gnupg gnupg-l10n gnupg-utils gpg 131s gpg-agent gpg-wks-client gpgconf gpgsm gpgv keyboxd libglib2.0-0t64 131s libglib2.0-data libnuma1 libpython3.12-minimal libpython3.12-stdlib 131s libpython3.12t64 libx11-6 libx11-data libxml2 numactl openssh-client 131s openssh-server openssh-sftp-server python3-wadllib 131s 28 upgraded, 0 newly installed, 0 to remove and 0 not upgraded. 131s Need to get 13.1 MB of archives. 131s After this operation, 81.9 kB disk space will be freed. 131s Get:1 http://ftpmaster.internal/ubuntu questing-proposed/main arm64 gawk arm64 1:5.3.2-1 [504 kB] 132s Get:2 http://ftpmaster.internal/ubuntu questing/main arm64 openssh-sftp-server arm64 1:9.9p1-3ubuntu3.1 [36.9 kB] 132s Get:3 http://ftpmaster.internal/ubuntu questing/main arm64 openssh-server arm64 1:9.9p1-3ubuntu3.1 [524 kB] 132s Get:4 http://ftpmaster.internal/ubuntu questing/main arm64 openssh-client arm64 1:9.9p1-3ubuntu3.1 [922 kB] 132s Get:5 http://ftpmaster.internal/ubuntu questing/main arm64 gpg-wks-client arm64 2.4.4-2ubuntu24 [70.3 kB] 132s Get:6 http://ftpmaster.internal/ubuntu questing/main arm64 dirmngr arm64 2.4.4-2ubuntu24 [321 kB] 132s Get:7 http://ftpmaster.internal/ubuntu questing/main arm64 gpgsm arm64 2.4.4-2ubuntu24 [228 kB] 132s Get:8 http://ftpmaster.internal/ubuntu questing/main arm64 gnupg-utils arm64 2.4.4-2ubuntu24 [107 kB] 132s Get:9 http://ftpmaster.internal/ubuntu questing/main arm64 gpg-agent arm64 2.4.4-2ubuntu24 [224 kB] 132s Get:10 http://ftpmaster.internal/ubuntu questing/main arm64 gpg arm64 2.4.4-2ubuntu24 [555 kB] 132s Get:11 http://ftpmaster.internal/ubuntu questing/main arm64 gpgconf arm64 2.4.4-2ubuntu24 [104 kB] 132s Get:12 http://ftpmaster.internal/ubuntu questing/main arm64 gnupg all 2.4.4-2ubuntu24 [359 kB] 132s Get:13 http://ftpmaster.internal/ubuntu questing/main arm64 keyboxd arm64 2.4.4-2ubuntu24 [76.1 kB] 132s Get:14 http://ftpmaster.internal/ubuntu questing/main arm64 gpgv arm64 2.4.4-2ubuntu24 [154 kB] 132s Get:15 http://ftpmaster.internal/ubuntu questing/main arm64 dhcpcd-base arm64 1:10.1.0-10 [216 kB] 132s Get:16 http://ftpmaster.internal/ubuntu questing/main arm64 gir1.2-glib-2.0 arm64 2.84.1-2 [185 kB] 132s Get:17 http://ftpmaster.internal/ubuntu questing/main arm64 libglib2.0-0t64 arm64 2.84.1-2 [1572 kB] 132s Get:18 http://ftpmaster.internal/ubuntu questing/main arm64 libglib2.0-data all 2.84.1-2 [53.2 kB] 132s Get:19 http://ftpmaster.internal/ubuntu questing/main arm64 libxml2 arm64 2.12.7+dfsg+really2.9.14-0.4ubuntu0.1 [736 kB] 132s Get:20 http://ftpmaster.internal/ubuntu questing/main arm64 libnuma1 arm64 2.0.19-1 [23.9 kB] 132s Get:21 http://ftpmaster.internal/ubuntu questing/main arm64 libx11-data all 2:1.8.12-1 [116 kB] 132s Get:22 http://ftpmaster.internal/ubuntu questing/main arm64 libx11-6 arm64 2:1.8.12-1 [651 kB] 132s Get:23 http://ftpmaster.internal/ubuntu questing/main arm64 numactl arm64 2.0.19-1 [39.2 kB] 132s Get:24 http://ftpmaster.internal/ubuntu questing/main arm64 gnupg-l10n all 2.4.4-2ubuntu24 [66.8 kB] 132s Get:25 http://ftpmaster.internal/ubuntu questing-proposed/universe arm64 libpython3.12t64 arm64 3.12.10-1 [2314 kB] 132s Get:26 http://ftpmaster.internal/ubuntu questing-proposed/universe arm64 libpython3.12-stdlib arm64 3.12.10-1 [2029 kB] 132s Get:27 http://ftpmaster.internal/ubuntu questing-proposed/universe arm64 libpython3.12-minimal arm64 3.12.10-1 [836 kB] 132s Get:28 http://ftpmaster.internal/ubuntu questing/main arm64 python3-wadllib all 2.0.0-3 [36.3 kB] 133s Preconfiguring packages ... 133s Fetched 13.1 MB in 1s (10.6 MB/s) 133s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 117830 files and directories currently installed.) 133s Preparing to unpack .../00-gawk_1%3a5.3.2-1_arm64.deb ... 133s Unpacking gawk (1:5.3.2-1) over (1:5.2.1-2build3) ... 133s Preparing to unpack .../01-openssh-sftp-server_1%3a9.9p1-3ubuntu3.1_arm64.deb ... 133s Unpacking openssh-sftp-server (1:9.9p1-3ubuntu3.1) over (1:9.9p1-3ubuntu3) ... 133s Preparing to unpack .../02-openssh-server_1%3a9.9p1-3ubuntu3.1_arm64.deb ... 134s Unpacking openssh-server (1:9.9p1-3ubuntu3.1) over (1:9.9p1-3ubuntu3) ... 134s Preparing to unpack .../03-openssh-client_1%3a9.9p1-3ubuntu3.1_arm64.deb ... 134s Unpacking openssh-client (1:9.9p1-3ubuntu3.1) over (1:9.9p1-3ubuntu3) ... 134s Preparing to unpack .../04-gpg-wks-client_2.4.4-2ubuntu24_arm64.deb ... 134s Unpacking gpg-wks-client (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 134s Preparing to unpack .../05-dirmngr_2.4.4-2ubuntu24_arm64.deb ... 134s Unpacking dirmngr (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 134s Preparing to unpack .../06-gpgsm_2.4.4-2ubuntu24_arm64.deb ... 134s Unpacking gpgsm (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 134s Preparing to unpack .../07-gnupg-utils_2.4.4-2ubuntu24_arm64.deb ... 134s Unpacking gnupg-utils (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 134s Preparing to unpack .../08-gpg-agent_2.4.4-2ubuntu24_arm64.deb ... 134s Unpacking gpg-agent (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 134s Preparing to unpack .../09-gpg_2.4.4-2ubuntu24_arm64.deb ... 134s Unpacking gpg (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 134s Preparing to unpack .../10-gpgconf_2.4.4-2ubuntu24_arm64.deb ... 134s Unpacking gpgconf (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 134s Preparing to unpack .../11-gnupg_2.4.4-2ubuntu24_all.deb ... 134s Unpacking gnupg (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 134s Preparing to unpack .../12-keyboxd_2.4.4-2ubuntu24_arm64.deb ... 134s Unpacking keyboxd (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 134s Preparing to unpack .../13-gpgv_2.4.4-2ubuntu24_arm64.deb ... 134s Unpacking gpgv (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 134s Setting up gpgv (2.4.4-2ubuntu24) ... 134s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 117832 files and directories currently installed.) 134s Preparing to unpack .../00-dhcpcd-base_1%3a10.1.0-10_arm64.deb ... 134s Unpacking dhcpcd-base (1:10.1.0-10) over (1:10.1.0-8) ... 134s Preparing to unpack .../01-gir1.2-glib-2.0_2.84.1-2_arm64.deb ... 134s Unpacking gir1.2-glib-2.0:arm64 (2.84.1-2) over (2.84.1-1) ... 134s Preparing to unpack .../02-libglib2.0-0t64_2.84.1-2_arm64.deb ... 134s Unpacking libglib2.0-0t64:arm64 (2.84.1-2) over (2.84.1-1) ... 135s Preparing to unpack .../03-libglib2.0-data_2.84.1-2_all.deb ... 135s Unpacking libglib2.0-data (2.84.1-2) over (2.84.1-1) ... 135s Preparing to unpack .../04-libxml2_2.12.7+dfsg+really2.9.14-0.4ubuntu0.1_arm64.deb ... 135s Unpacking libxml2:arm64 (2.12.7+dfsg+really2.9.14-0.4ubuntu0.1) over (2.12.7+dfsg+really2.9.14-0.4) ... 135s Preparing to unpack .../05-libnuma1_2.0.19-1_arm64.deb ... 135s Unpacking libnuma1:arm64 (2.0.19-1) over (2.0.18-1build1) ... 135s Preparing to unpack .../06-libx11-data_2%3a1.8.12-1_all.deb ... 135s Unpacking libx11-data (2:1.8.12-1) over (2:1.8.10-2) ... 135s Preparing to unpack .../07-libx11-6_2%3a1.8.12-1_arm64.deb ... 135s Unpacking libx11-6:arm64 (2:1.8.12-1) over (2:1.8.10-2) ... 135s Preparing to unpack .../08-numactl_2.0.19-1_arm64.deb ... 135s Unpacking numactl (2.0.19-1) over (2.0.18-1build1) ... 135s Preparing to unpack .../09-gnupg-l10n_2.4.4-2ubuntu24_all.deb ... 135s Unpacking gnupg-l10n (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 135s Preparing to unpack .../10-libpython3.12t64_3.12.10-1_arm64.deb ... 135s Unpacking libpython3.12t64:arm64 (3.12.10-1) over (3.12.8-3) ... 135s Preparing to unpack .../11-libpython3.12-stdlib_3.12.10-1_arm64.deb ... 135s Unpacking libpython3.12-stdlib:arm64 (3.12.10-1) over (3.12.8-3) ... 135s Preparing to unpack .../12-libpython3.12-minimal_3.12.10-1_arm64.deb ... 135s Unpacking libpython3.12-minimal:arm64 (3.12.10-1) over (3.12.8-3) ... 135s Preparing to unpack .../13-python3-wadllib_2.0.0-3_all.deb ... 135s Unpacking python3-wadllib (2.0.0-3) over (2.0.0-2) ... 135s Setting up gawk (1:5.3.2-1) ... 136s Setting up openssh-client (1:9.9p1-3ubuntu3.1) ... 136s Setting up libpython3.12-minimal:arm64 (3.12.10-1) ... 136s Setting up libglib2.0-0t64:arm64 (2.84.1-2) ... 136s No schema files found: doing nothing. 136s Setting up libglib2.0-data (2.84.1-2) ... 136s Setting up libx11-data (2:1.8.12-1) ... 136s Setting up gnupg-l10n (2.4.4-2ubuntu24) ... 136s Setting up python3-wadllib (2.0.0-3) ... 136s Setting up dhcpcd-base (1:10.1.0-10) ... 136s Installing new version of config file /etc/dhcpcd.conf ... 136s Setting up gir1.2-glib-2.0:arm64 (2.84.1-2) ... 136s Setting up libnuma1:arm64 (2.0.19-1) ... 136s Setting up gpgconf (2.4.4-2ubuntu24) ... 136s Setting up libx11-6:arm64 (2:1.8.12-1) ... 136s Setting up libxml2:arm64 (2.12.7+dfsg+really2.9.14-0.4ubuntu0.1) ... 136s Setting up gpg (2.4.4-2ubuntu24) ... 136s Setting up gnupg-utils (2.4.4-2ubuntu24) ... 136s Setting up openssh-sftp-server (1:9.9p1-3ubuntu3.1) ... 136s Setting up gpg-agent (2.4.4-2ubuntu24) ... 136s Setting up libpython3.12-stdlib:arm64 (3.12.10-1) ... 136s Setting up numactl (2.0.19-1) ... 136s Setting up openssh-server (1:9.9p1-3ubuntu3.1) ... 138s Setting up gpgsm (2.4.4-2ubuntu24) ... 138s Setting up libpython3.12t64:arm64 (3.12.10-1) ... 138s Setting up dirmngr (2.4.4-2ubuntu24) ... 138s Setting up keyboxd (2.4.4-2ubuntu24) ... 138s Setting up gnupg (2.4.4-2ubuntu24) ... 138s Setting up gpg-wks-client (2.4.4-2ubuntu24) ... 138s Processing triggers for ufw (0.36.2-9) ... 138s Processing triggers for man-db (2.13.1-1) ... 139s Processing triggers for install-info (7.1.1-1) ... 139s Processing triggers for libc-bin (2.41-6ubuntu1) ... 140s Reading package lists... 140s Building dependency tree... 140s Reading state information... 140s Starting pkgProblemResolver with broken count: 0 140s Starting 2 pkgProblemResolver with broken count: 0 140s Done 141s Solving dependencies... 141s The following packages will be REMOVED: 141s libsigsegv2* 142s 0 upgraded, 0 newly installed, 1 to remove and 0 not upgraded. 142s After this operation, 97.3 kB disk space will be freed. 142s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 117832 files and directories currently installed.) 142s Removing libsigsegv2:arm64 (2.14-1ubuntu2) ... 142s Processing triggers for libc-bin (2.41-6ubuntu1) ... 142s autopkgtest [22:20:53]: rebooting testbed after setup commands that affected boot 165s autopkgtest [22:21:16]: testbed running kernel: Linux 6.14.0-15-generic #15-Ubuntu SMP PREEMPT_DYNAMIC Sun Apr 6 14:37:51 UTC 2025 168s autopkgtest [22:21:19]: @@@@@@@@@@@@@@@@@@@@ apt-source yosys 172s Get:1 http://ftpmaster.internal/ubuntu questing/universe yosys 0.33-5build2 (dsc) [3069 B] 172s Get:2 http://ftpmaster.internal/ubuntu questing/universe yosys 0.33-5build2 (tar) [6161 kB] 172s Get:3 http://ftpmaster.internal/ubuntu questing/universe yosys 0.33-5build2 (tar) [2586 kB] 172s Get:4 http://ftpmaster.internal/ubuntu questing/universe yosys 0.33-5build2 (diff) [30.3 kB] 173s gpgv: Signature made Mon Apr 1 04:53:46 2024 UTC 173s gpgv: using RSA key A089FB36AAFBDAD5ACC1325069F790171A210984 173s gpgv: Can't check signature: No public key 173s dpkg-source: warning: cannot verify inline signature for ./yosys_0.33-5build2.dsc: no acceptable signature found 173s autopkgtest [22:21:24]: testing package yosys version 0.33-5build2 174s autopkgtest [22:21:25]: build not needed 177s autopkgtest [22:21:28]: test yosys-testsuite: preparing testbed 177s Reading package lists... 177s Building dependency tree... 177s Reading state information... 177s Starting pkgProblemResolver with broken count: 0 178s Starting 2 pkgProblemResolver with broken count: 0 178s Done 178s The following NEW packages will be installed: 178s cpp cpp-14 cpp-14-aarch64-linux-gnu cpp-aarch64-linux-gnu g++ g++-14 178s g++-14-aarch64-linux-gnu g++-aarch64-linux-gnu gcc gcc-14 178s gcc-14-aarch64-linux-gnu gcc-aarch64-linux-gnu iverilog libasan8 libcc1-0 178s libffi-dev libgcc-14-dev libgomp1 libhwasan0 libisl23 libitm1 liblsan0 178s libmpc3 libncurses-dev libpkgconf3 libreadline-dev libstdc++-14-dev 178s libtcl8.6 libtsan2 libubsan1 pkg-config pkgconf pkgconf-bin python3-click 178s tcl tcl-dev tcl8.6 tcl8.6-dev yosys yosys-abc yosys-dev zlib1g-dev 178s 0 upgraded, 42 newly installed, 0 to remove and 0 not upgraded. 178s Need to get 74.6 MB of archives. 178s After this operation, 258 MB of additional disk space will be used. 178s Get:1 http://ftpmaster.internal/ubuntu questing/main arm64 libisl23 arm64 0.27-1 [676 kB] 179s Get:2 http://ftpmaster.internal/ubuntu questing/main arm64 libmpc3 arm64 1.3.1-1build2 [56.8 kB] 179s Get:3 http://ftpmaster.internal/ubuntu questing/main arm64 cpp-14-aarch64-linux-gnu arm64 14.2.0-19ubuntu2 [10.6 MB] 184s Get:4 http://ftpmaster.internal/ubuntu questing/main arm64 cpp-14 arm64 14.2.0-19ubuntu2 [1026 B] 184s Get:5 http://ftpmaster.internal/ubuntu questing/main arm64 cpp-aarch64-linux-gnu arm64 4:14.2.0-1ubuntu1 [5558 B] 184s Get:6 http://ftpmaster.internal/ubuntu questing/main arm64 cpp arm64 4:14.2.0-1ubuntu1 [22.4 kB] 184s Get:7 http://ftpmaster.internal/ubuntu questing/main arm64 libcc1-0 arm64 15-20250404-0ubuntu1 [49.1 kB] 184s Get:8 http://ftpmaster.internal/ubuntu questing/main arm64 libgomp1 arm64 15-20250404-0ubuntu1 [147 kB] 184s Get:9 http://ftpmaster.internal/ubuntu questing/main arm64 libitm1 arm64 15-20250404-0ubuntu1 [27.8 kB] 184s Get:10 http://ftpmaster.internal/ubuntu questing/main arm64 libasan8 arm64 15-20250404-0ubuntu1 [2922 kB] 185s Get:11 http://ftpmaster.internal/ubuntu questing/main arm64 liblsan0 arm64 15-20250404-0ubuntu1 [1318 kB] 185s Get:12 http://ftpmaster.internal/ubuntu questing/main arm64 libtsan2 arm64 15-20250404-0ubuntu1 [2692 kB] 186s Get:13 http://ftpmaster.internal/ubuntu questing/main arm64 libubsan1 arm64 15-20250404-0ubuntu1 [1177 kB] 187s Get:14 http://ftpmaster.internal/ubuntu questing/main arm64 libhwasan0 arm64 15-20250404-0ubuntu1 [1640 kB] 187s Get:15 http://ftpmaster.internal/ubuntu questing/main arm64 libgcc-14-dev arm64 14.2.0-19ubuntu2 [2593 kB] 188s Get:16 http://ftpmaster.internal/ubuntu questing/main arm64 gcc-14-aarch64-linux-gnu arm64 14.2.0-19ubuntu2 [20.9 MB] 192s Get:17 http://ftpmaster.internal/ubuntu questing/main arm64 gcc-14 arm64 14.2.0-19ubuntu2 [529 kB] 192s Get:18 http://ftpmaster.internal/ubuntu questing/main arm64 gcc-aarch64-linux-gnu arm64 4:14.2.0-1ubuntu1 [1200 B] 192s Get:19 http://ftpmaster.internal/ubuntu questing/main arm64 gcc arm64 4:14.2.0-1ubuntu1 [4998 B] 192s Get:20 http://ftpmaster.internal/ubuntu questing/main arm64 libstdc++-14-dev arm64 14.2.0-19ubuntu2 [2501 kB] 193s Get:21 http://ftpmaster.internal/ubuntu questing/main arm64 g++-14-aarch64-linux-gnu arm64 14.2.0-19ubuntu2 [12.1 MB] 194s Get:22 http://ftpmaster.internal/ubuntu questing/main arm64 g++-14 arm64 14.2.0-19ubuntu2 [23.0 kB] 194s Get:23 http://ftpmaster.internal/ubuntu questing/main arm64 g++-aarch64-linux-gnu arm64 4:14.2.0-1ubuntu1 [956 B] 194s Get:24 http://ftpmaster.internal/ubuntu questing/main arm64 g++ arm64 4:14.2.0-1ubuntu1 [1080 B] 194s Get:25 http://ftpmaster.internal/ubuntu questing/universe arm64 iverilog arm64 12.0-2build2 [2065 kB] 194s Get:26 http://ftpmaster.internal/ubuntu questing/main arm64 libncurses-dev arm64 6.5+20250216-2 [389 kB] 194s Get:27 http://ftpmaster.internal/ubuntu questing/main arm64 libpkgconf3 arm64 1.8.1-4 [31.4 kB] 194s Get:28 http://ftpmaster.internal/ubuntu questing/main arm64 libreadline-dev arm64 8.2-6 [179 kB] 194s Get:29 http://ftpmaster.internal/ubuntu questing/main arm64 libtcl8.6 arm64 8.6.16+dfsg-1 [987 kB] 194s Get:30 http://ftpmaster.internal/ubuntu questing/main arm64 pkgconf-bin arm64 1.8.1-4 [20.9 kB] 194s Get:31 http://ftpmaster.internal/ubuntu questing/main arm64 pkgconf arm64 1.8.1-4 [16.7 kB] 194s Get:32 http://ftpmaster.internal/ubuntu questing/main arm64 pkg-config arm64 1.8.1-4 [7362 B] 194s Get:33 http://ftpmaster.internal/ubuntu questing/main arm64 python3-click all 8.2.0+0.really.8.1.8-1 [80.0 kB] 194s Get:34 http://ftpmaster.internal/ubuntu questing/main arm64 tcl8.6 arm64 8.6.16+dfsg-1 [14.8 kB] 194s Get:35 http://ftpmaster.internal/ubuntu questing/main arm64 tcl arm64 8.6.16 [4084 B] 194s Get:36 http://ftpmaster.internal/ubuntu questing/main arm64 zlib1g-dev arm64 1:1.3.dfsg+really1.3.1-1ubuntu1 [894 kB] 194s Get:37 http://ftpmaster.internal/ubuntu questing/main arm64 tcl8.6-dev arm64 8.6.16+dfsg-1 [1036 kB] 194s Get:38 http://ftpmaster.internal/ubuntu questing/main arm64 tcl-dev arm64 8.6.16 [5750 B] 194s Get:39 http://ftpmaster.internal/ubuntu questing/universe arm64 yosys-abc arm64 0.33-5build2 [5605 kB] 195s Get:40 http://ftpmaster.internal/ubuntu questing/universe arm64 yosys arm64 0.33-5build2 [3098 kB] 195s Get:41 http://ftpmaster.internal/ubuntu questing/main arm64 libffi-dev arm64 3.4.7-1 [59.5 kB] 195s Get:42 http://ftpmaster.internal/ubuntu questing/universe arm64 yosys-dev arm64 0.33-5build2 [88.4 kB] 196s Fetched 74.6 MB in 17s (4426 kB/s) 196s Selecting previously unselected package libisl23:arm64. 196s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 117825 files and directories currently installed.) 196s Preparing to unpack .../00-libisl23_0.27-1_arm64.deb ... 196s Unpacking libisl23:arm64 (0.27-1) ... 196s Selecting previously unselected package libmpc3:arm64. 196s Preparing to unpack .../01-libmpc3_1.3.1-1build2_arm64.deb ... 196s Unpacking libmpc3:arm64 (1.3.1-1build2) ... 196s Selecting previously unselected package cpp-14-aarch64-linux-gnu. 196s Preparing to unpack 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libubsan1:arm64 (15-20250404-0ubuntu1) ... 197s Selecting previously unselected package libhwasan0:arm64. 197s Preparing to unpack .../13-libhwasan0_15-20250404-0ubuntu1_arm64.deb ... 197s Unpacking libhwasan0:arm64 (15-20250404-0ubuntu1) ... 197s Selecting previously unselected package libgcc-14-dev:arm64. 197s Preparing to unpack .../14-libgcc-14-dev_14.2.0-19ubuntu2_arm64.deb ... 197s Unpacking libgcc-14-dev:arm64 (14.2.0-19ubuntu2) ... 197s Selecting previously unselected package gcc-14-aarch64-linux-gnu. 197s Preparing to unpack .../15-gcc-14-aarch64-linux-gnu_14.2.0-19ubuntu2_arm64.deb ... 197s Unpacking gcc-14-aarch64-linux-gnu (14.2.0-19ubuntu2) ... 197s Selecting previously unselected package gcc-14. 197s Preparing to unpack .../16-gcc-14_14.2.0-19ubuntu2_arm64.deb ... 197s Unpacking gcc-14 (14.2.0-19ubuntu2) ... 197s Selecting previously unselected package gcc-aarch64-linux-gnu. 197s Preparing to unpack .../17-gcc-aarch64-linux-gnu_4%3a14.2.0-1ubuntu1_arm64.deb ... 197s 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g++-aarch64-linux-gnu (4:14.2.0-1ubuntu1) ... 198s Selecting previously unselected package g++. 198s Preparing to unpack .../23-g++_4%3a14.2.0-1ubuntu1_arm64.deb ... 198s Unpacking g++ (4:14.2.0-1ubuntu1) ... 198s Selecting previously unselected package iverilog. 198s Preparing to unpack .../24-iverilog_12.0-2build2_arm64.deb ... 198s Unpacking iverilog (12.0-2build2) ... 198s Selecting previously unselected package libncurses-dev:arm64. 198s Preparing to unpack .../25-libncurses-dev_6.5+20250216-2_arm64.deb ... 198s Unpacking libncurses-dev:arm64 (6.5+20250216-2) ... 198s Selecting previously unselected package libpkgconf3:arm64. 198s Preparing to unpack .../26-libpkgconf3_1.8.1-4_arm64.deb ... 198s Unpacking libpkgconf3:arm64 (1.8.1-4) ... 199s Selecting previously unselected package libreadline-dev:arm64. 199s Preparing to unpack .../27-libreadline-dev_8.2-6_arm64.deb ... 199s Unpacking libreadline-dev:arm64 (8.2-6) ... 199s Selecting previously unselected package libtcl8.6:arm64. 199s Preparing to unpack .../28-libtcl8.6_8.6.16+dfsg-1_arm64.deb ... 199s Unpacking libtcl8.6:arm64 (8.6.16+dfsg-1) ... 199s Selecting previously unselected package pkgconf-bin. 199s Preparing to unpack .../29-pkgconf-bin_1.8.1-4_arm64.deb ... 199s Unpacking pkgconf-bin (1.8.1-4) ... 199s Selecting previously unselected package pkgconf:arm64. 199s Preparing to unpack .../30-pkgconf_1.8.1-4_arm64.deb ... 199s Unpacking pkgconf:arm64 (1.8.1-4) ... 199s Selecting previously unselected package pkg-config:arm64. 199s Preparing to unpack .../31-pkg-config_1.8.1-4_arm64.deb ... 199s Unpacking pkg-config:arm64 (1.8.1-4) ... 199s Selecting previously unselected package python3-click. 199s Preparing to unpack .../32-python3-click_8.2.0+0.really.8.1.8-1_all.deb ... 199s Unpacking python3-click (8.2.0+0.really.8.1.8-1) ... 199s Selecting previously unselected package tcl8.6. 199s Preparing to unpack .../33-tcl8.6_8.6.16+dfsg-1_arm64.deb ... 199s Unpacking tcl8.6 (8.6.16+dfsg-1) ... 199s Selecting previously unselected package tcl. 199s Preparing to unpack .../34-tcl_8.6.16_arm64.deb ... 199s Unpacking tcl (8.6.16) ... 199s Selecting previously unselected package zlib1g-dev:arm64. 199s Preparing to unpack .../35-zlib1g-dev_1%3a1.3.dfsg+really1.3.1-1ubuntu1_arm64.deb ... 199s Unpacking zlib1g-dev:arm64 (1:1.3.dfsg+really1.3.1-1ubuntu1) ... 199s Selecting previously unselected package tcl8.6-dev:arm64. 199s Preparing to unpack .../36-tcl8.6-dev_8.6.16+dfsg-1_arm64.deb ... 199s Unpacking tcl8.6-dev:arm64 (8.6.16+dfsg-1) ... 199s Selecting previously unselected package tcl-dev:arm64. 199s Preparing to unpack .../37-tcl-dev_8.6.16_arm64.deb ... 199s Unpacking tcl-dev:arm64 (8.6.16) ... 199s Selecting previously unselected package yosys-abc. 199s Preparing to unpack .../38-yosys-abc_0.33-5build2_arm64.deb ... 199s Unpacking yosys-abc (0.33-5build2) ... 200s Selecting previously unselected package yosys. 200s Preparing to unpack .../39-yosys_0.33-5build2_arm64.deb ... 200s Unpacking yosys (0.33-5build2) ... 200s Selecting previously unselected package libffi-dev:arm64. 200s Preparing to unpack .../40-libffi-dev_3.4.7-1_arm64.deb ... 200s Unpacking libffi-dev:arm64 (3.4.7-1) ... 200s Selecting previously unselected package yosys-dev. 200s Preparing to unpack .../41-yosys-dev_0.33-5build2_arm64.deb ... 200s Unpacking yosys-dev (0.33-5build2) ... 200s Setting up libncurses-dev:arm64 (6.5+20250216-2) ... 200s Setting up yosys-abc (0.33-5build2) ... 200s Setting up libreadline-dev:arm64 (8.2-6) ... 200s Setting up libgomp1:arm64 (15-20250404-0ubuntu1) ... 200s Setting up python3-click (8.2.0+0.really.8.1.8-1) ... 200s Setting up libffi-dev:arm64 (3.4.7-1) ... 200s Setting up iverilog (12.0-2build2) ... 200s Setting up libpkgconf3:arm64 (1.8.1-4) ... 200s Setting up libmpc3:arm64 (1.3.1-1build2) ... 200s Setting up libtcl8.6:arm64 (8.6.16+dfsg-1) ... 200s Setting up pkgconf-bin (1.8.1-4) ... 200s Setting up libubsan1:arm64 (15-20250404-0ubuntu1) ... 200s Setting up zlib1g-dev:arm64 (1:1.3.dfsg+really1.3.1-1ubuntu1) ... 200s Setting up libhwasan0:arm64 (15-20250404-0ubuntu1) ... 200s Setting up libasan8:arm64 (15-20250404-0ubuntu1) ... 200s Setting up libtsan2:arm64 (15-20250404-0ubuntu1) ... 200s Setting up libisl23:arm64 (0.27-1) ... 200s Setting up libcc1-0:arm64 (15-20250404-0ubuntu1) ... 200s Setting up liblsan0:arm64 (15-20250404-0ubuntu1) ... 200s Setting up libitm1:arm64 (15-20250404-0ubuntu1) ... 200s Setting up tcl8.6 (8.6.16+dfsg-1) ... 200s Setting up tcl8.6-dev:arm64 (8.6.16+dfsg-1) ... 200s Setting up yosys (0.33-5build2) ... 201s Setting up pkgconf:arm64 (1.8.1-4) ... 201s Setting up pkg-config:arm64 (1.8.1-4) ... 201s Setting up cpp-14-aarch64-linux-gnu (14.2.0-19ubuntu2) ... 201s Setting up tcl (8.6.16) ... 201s Setting up libgcc-14-dev:arm64 (14.2.0-19ubuntu2) ... 201s Setting up libstdc++-14-dev:arm64 (14.2.0-19ubuntu2) ... 201s Setting up cpp-aarch64-linux-gnu (4:14.2.0-1ubuntu1) ... 201s Setting up cpp-14 (14.2.0-19ubuntu2) ... 201s Setting up tcl-dev:arm64 (8.6.16) ... 201s Setting up cpp (4:14.2.0-1ubuntu1) ... 201s Setting up gcc-14-aarch64-linux-gnu (14.2.0-19ubuntu2) ... 201s Setting up yosys-dev (0.33-5build2) ... 201s Setting up gcc-aarch64-linux-gnu (4:14.2.0-1ubuntu1) ... 201s Setting up g++-14-aarch64-linux-gnu (14.2.0-19ubuntu2) ... 201s Setting up gcc-14 (14.2.0-19ubuntu2) ... 201s Setting up g++-aarch64-linux-gnu (4:14.2.0-1ubuntu1) ... 201s Setting up g++-14 (14.2.0-19ubuntu2) ... 201s Setting up gcc (4:14.2.0-1ubuntu1) ... 201s Setting up g++ (4:14.2.0-1ubuntu1) ... 201s update-alternatives: using /usr/bin/g++ to provide /usr/bin/c++ (c++) in auto mode 201s Processing triggers for libc-bin (2.41-6ubuntu1) ... 201s Processing triggers for man-db (2.13.1-1) ... 202s Processing triggers for install-info (7.1.1-1) ... 204s autopkgtest [22:21:55]: test yosys-testsuite: [----------------------- 204s + [ 1 -ge 1 ] 204s + testdir=. 204s + shift 204s + mkdir -p . 204s + cd . 204s + ln -sf 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"./"/backends/cxxrtl/cxxrtl_capi.h share/include/backends/cxxrtl/cxxrtl_capi.h 204s mkdir -p share/include/backends/cxxrtl/ 204s cp "./"/backends/cxxrtl/cxxrtl_vcd_capi.cc share/include/backends/cxxrtl/cxxrtl_vcd_capi.cc 204s mkdir -p share/include/backends/cxxrtl/ 204s cp "./"/backends/cxxrtl/cxxrtl_vcd_capi.h share/include/backends/cxxrtl/cxxrtl_vcd_capi.h 204s mkdir -p share/python3 204s cp "./"/backends/smt2/smtio.py share/python3/smtio.py 204s mkdir -p share/python3 204s cp "./"/backends/smt2/ywio.py share/python3/ywio.py 204s mkdir -p share/achronix/speedster22i/ 204s cp "./"/techlibs/achronix/speedster22i/cells_sim.v share/achronix/speedster22i/cells_sim.v 204s mkdir -p share/achronix/speedster22i/ 204s cp "./"/techlibs/achronix/speedster22i/cells_map.v share/achronix/speedster22i/cells_map.v 204s mkdir -p share/anlogic 204s cp "./"/techlibs/anlogic/cells_map.v share/anlogic/cells_map.v 204s mkdir -p share/anlogic 204s cp "./"/techlibs/anlogic/arith_map.v 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cp "./"/techlibs/common/adff2dff.v share/adff2dff.v 204s mkdir -p share 204s cp "./"/techlibs/common/dff2ff.v share/dff2ff.v 204s mkdir -p share 204s cp "./"/techlibs/common/gate2lut.v share/gate2lut.v 204s mkdir -p share 204s cp "./"/techlibs/common/cmp2lut.v share/cmp2lut.v 204s mkdir -p share 204s cp "./"/techlibs/common/cells.lib share/cells.lib 204s mkdir -p share 204s cp "./"/techlibs/common/mul2dsp.v share/mul2dsp.v 204s mkdir -p share 204s cp "./"/techlibs/common/abc9_model.v share/abc9_model.v 204s mkdir -p share 204s cp "./"/techlibs/common/abc9_map.v share/abc9_map.v 204s mkdir -p share 204s cp "./"/techlibs/common/abc9_unmap.v share/abc9_unmap.v 204s mkdir -p share 204s cp "./"/techlibs/common/cmp2lcu.v share/cmp2lcu.v 204s mkdir -p share/coolrunner2 204s cp "./"/techlibs/coolrunner2/cells_latch.v share/coolrunner2/cells_latch.v 204s mkdir -p share/coolrunner2 204s cp "./"/techlibs/coolrunner2/cells_sim.v share/coolrunner2/cells_sim.v 204s mkdir -p share/coolrunner2 204s cp "./"/techlibs/coolrunner2/cells_counter_map.v share/coolrunner2/cells_counter_map.v 204s mkdir -p share/coolrunner2 204s cp "./"/techlibs/coolrunner2/tff_extract.v share/coolrunner2/tff_extract.v 204s mkdir -p share/coolrunner2 204s cp "./"/techlibs/coolrunner2/xc2_dff.lib share/coolrunner2/xc2_dff.lib 204s mkdir -p share/ecp5 204s cp "./"/techlibs/ecp5/cells_ff.vh share/ecp5/cells_ff.vh 204s mkdir -p share/ecp5 204s cp "./"/techlibs/ecp5/cells_io.vh share/ecp5/cells_io.vh 204s mkdir -p share/ecp5 204s cp "./"/techlibs/ecp5/cells_map.v share/ecp5/cells_map.v 204s mkdir -p share/ecp5 204s cp "./"/techlibs/ecp5/cells_sim.v share/ecp5/cells_sim.v 204s mkdir -p share/ecp5 204s cp "./"/techlibs/ecp5/cells_bb.v share/ecp5/cells_bb.v 204s mkdir -p share/ecp5 204s cp "./"/techlibs/ecp5/lutrams_map.v share/ecp5/lutrams_map.v 204s mkdir -p share/ecp5 204s cp "./"/techlibs/ecp5/lutrams.txt share/ecp5/lutrams.txt 204s mkdir -p share/ecp5 204s cp "./"/techlibs/ecp5/brams_map.v share/ecp5/brams_map.v 204s mkdir -p share/ecp5 204s cp "./"/techlibs/ecp5/brams.txt share/ecp5/brams.txt 204s mkdir -p share/ecp5 204s cp "./"/techlibs/ecp5/arith_map.v share/ecp5/arith_map.v 204s mkdir -p share/ecp5 204s cp "./"/techlibs/ecp5/latches_map.v share/ecp5/latches_map.v 204s mkdir -p share/ecp5 204s cp "./"/techlibs/ecp5/dsp_map.v share/ecp5/dsp_map.v 204s mkdir -p share/efinix 204s cp "./"/techlibs/efinix/cells_map.v share/efinix/cells_map.v 204s mkdir -p share/efinix 204s cp "./"/techlibs/efinix/arith_map.v share/efinix/arith_map.v 204s mkdir -p share/efinix 204s cp "./"/techlibs/efinix/cells_sim.v share/efinix/cells_sim.v 204s mkdir -p share/efinix 204s cp "./"/techlibs/efinix/brams_map.v share/efinix/brams_map.v 205s mkdir -p share/efinix 205s cp "./"/techlibs/efinix/gbuf_map.v share/efinix/gbuf_map.v 205s mkdir -p share/efinix 205s cp "./"/techlibs/efinix/brams.txt share/efinix/brams.txt 205s mkdir -p share/fabulous 205s cp "./"/techlibs/fabulous/cells_map.v share/fabulous/cells_map.v 205s mkdir -p share/fabulous 205s cp "./"/techlibs/fabulous/prims.v share/fabulous/prims.v 205s mkdir -p share/fabulous 205s cp "./"/techlibs/fabulous/latches_map.v share/fabulous/latches_map.v 205s mkdir -p share/fabulous 205s cp "./"/techlibs/fabulous/ff_map.v share/fabulous/ff_map.v 205s mkdir -p share/fabulous 205s cp "./"/techlibs/fabulous/ram_regfile.txt share/fabulous/ram_regfile.txt 205s mkdir -p share/fabulous 205s cp "./"/techlibs/fabulous/regfile_map.v share/fabulous/regfile_map.v 205s mkdir -p share/fabulous 205s cp "./"/techlibs/fabulous/io_map.v share/fabulous/io_map.v 205s mkdir -p share/fabulous 205s cp "./"/techlibs/fabulous/arith_map.v share/fabulous/arith_map.v 205s mkdir -p share/gatemate 205s cp "./"/techlibs/gatemate/reg_map.v share/gatemate/reg_map.v 205s mkdir -p share/gatemate 205s cp "./"/techlibs/gatemate/mux_map.v share/gatemate/mux_map.v 205s mkdir -p share/gatemate 205s cp "./"/techlibs/gatemate/lut_map.v share/gatemate/lut_map.v 205s mkdir -p share/gatemate 205s cp "./"/techlibs/gatemate/mul_map.v share/gatemate/mul_map.v 205s mkdir -p share/gatemate 205s cp "./"/techlibs/gatemate/arith_map.v share/gatemate/arith_map.v 205s mkdir -p share/gatemate 205s cp "./"/techlibs/gatemate/cells_sim.v share/gatemate/cells_sim.v 205s mkdir -p share/gatemate 205s cp "./"/techlibs/gatemate/cells_bb.v share/gatemate/cells_bb.v 205s mkdir -p share/gatemate 205s cp "./"/techlibs/gatemate/brams_map.v share/gatemate/brams_map.v 205s mkdir -p share/gatemate 205s cp "./"/techlibs/gatemate/brams.txt share/gatemate/brams.txt 205s mkdir -p share/gatemate 205s cp "./"/techlibs/gatemate/brams_init_20.vh share/gatemate/brams_init_20.vh 205s mkdir -p share/gatemate 205s cp "./"/techlibs/gatemate/brams_init_40.vh share/gatemate/brams_init_40.vh 205s mkdir -p share/gatemate 205s cp "./"/techlibs/gatemate/inv_map.v share/gatemate/inv_map.v 205s mkdir -p techlibs/gatemate 205s python3 techlibs/gatemate/make_lut_tree_lib.py 205s touch techlibs/gatemate/lut_tree_lib.mk 205s mkdir -p share/gatemate 205s cp techlibs/gatemate/lut_tree_cells.genlib share/gatemate/lut_tree_cells.genlib 205s mkdir -p share/gatemate 205s cp techlibs/gatemate/lut_tree_map.v share/gatemate/lut_tree_map.v 205s mkdir -p share/gowin 205s cp "./"/techlibs/gowin/cells_map.v share/gowin/cells_map.v 205s mkdir -p share/gowin 205s cp "./"/techlibs/gowin/cells_sim.v share/gowin/cells_sim.v 205s mkdir -p share/gowin 205s cp "./"/techlibs/gowin/cells_xtra.v share/gowin/cells_xtra.v 205s mkdir -p share/gowin 205s cp "./"/techlibs/gowin/arith_map.v share/gowin/arith_map.v 205s mkdir -p share/gowin 205s cp "./"/techlibs/gowin/brams_map.v share/gowin/brams_map.v 205s mkdir -p share/gowin 205s cp "./"/techlibs/gowin/brams.txt share/gowin/brams.txt 205s mkdir -p share/gowin 205s cp "./"/techlibs/gowin/lutrams_map.v share/gowin/lutrams_map.v 205s mkdir -p share/gowin 205s cp "./"/techlibs/gowin/lutrams.txt share/gowin/lutrams.txt 205s mkdir -p share/greenpak4 205s cp "./"/techlibs/greenpak4/cells_blackbox.v share/greenpak4/cells_blackbox.v 205s mkdir -p share/greenpak4 205s cp "./"/techlibs/greenpak4/cells_latch.v share/greenpak4/cells_latch.v 205s mkdir -p share/greenpak4 205s cp "./"/techlibs/greenpak4/cells_map.v share/greenpak4/cells_map.v 205s mkdir -p share/greenpak4 205s cp "./"/techlibs/greenpak4/cells_sim.v share/greenpak4/cells_sim.v 205s mkdir -p share/greenpak4 205s cp "./"/techlibs/greenpak4/cells_sim_ams.v share/greenpak4/cells_sim_ams.v 205s mkdir -p share/greenpak4 205s cp "./"/techlibs/greenpak4/cells_sim_digital.v share/greenpak4/cells_sim_digital.v 205s mkdir -p share/greenpak4 205s cp "./"/techlibs/greenpak4/cells_sim_wip.v share/greenpak4/cells_sim_wip.v 205s mkdir -p share/greenpak4 205s cp "./"/techlibs/greenpak4/gp_dff.lib share/greenpak4/gp_dff.lib 205s mkdir -p share/ice40 205s cp "./"/techlibs/ice40/arith_map.v share/ice40/arith_map.v 205s mkdir -p share/ice40 205s cp "./"/techlibs/ice40/cells_map.v share/ice40/cells_map.v 205s mkdir -p share/ice40 205s cp "./"/techlibs/ice40/ff_map.v share/ice40/ff_map.v 205s mkdir -p share/ice40 205s cp "./"/techlibs/ice40/cells_sim.v share/ice40/cells_sim.v 205s mkdir -p share/ice40 205s cp "./"/techlibs/ice40/latches_map.v share/ice40/latches_map.v 205s mkdir -p share/ice40 205s cp "./"/techlibs/ice40/brams.txt share/ice40/brams.txt 205s mkdir -p share/ice40 205s cp "./"/techlibs/ice40/brams_map.v share/ice40/brams_map.v 205s mkdir -p share/ice40 205s cp "./"/techlibs/ice40/spram.txt share/ice40/spram.txt 205s mkdir -p share/ice40 205s cp "./"/techlibs/ice40/spram_map.v share/ice40/spram_map.v 205s mkdir -p share/ice40 205s cp "./"/techlibs/ice40/dsp_map.v share/ice40/dsp_map.v 205s mkdir -p share/ice40 205s cp "./"/techlibs/ice40/abc9_model.v share/ice40/abc9_model.v 205s mkdir -p share/intel/common 205s cp "./"/techlibs/intel/common/m9k_bb.v share/intel/common/m9k_bb.v 205s mkdir -p share/intel/common 205s cp "./"/techlibs/intel/common/altpll_bb.v share/intel/common/altpll_bb.v 205s mkdir -p share/intel/common 205s cp "./"/techlibs/intel/common/brams_m9k.txt share/intel/common/brams_m9k.txt 205s mkdir -p share/intel/common 205s cp "./"/techlibs/intel/common/brams_map_m9k.v share/intel/common/brams_map_m9k.v 205s mkdir -p share/intel/common 205s cp "./"/techlibs/intel/common/ff_map.v share/intel/common/ff_map.v 205s mkdir -p share/intel/max10 205s cp "./"/techlibs/intel/max10/cells_sim.v share/intel/max10/cells_sim.v 205s mkdir -p share/intel/cyclone10lp 205s cp "./"/techlibs/intel/cyclone10lp/cells_sim.v share/intel/cyclone10lp/cells_sim.v 205s mkdir -p share/intel/cycloneiv 205s cp "./"/techlibs/intel/cycloneiv/cells_sim.v share/intel/cycloneiv/cells_sim.v 205s mkdir -p share/intel/cycloneive 205s cp "./"/techlibs/intel/cycloneive/cells_sim.v share/intel/cycloneive/cells_sim.v 205s mkdir -p share/intel/max10 205s cp "./"/techlibs/intel/max10/cells_map.v share/intel/max10/cells_map.v 205s mkdir -p share/intel/cyclone10lp 205s cp "./"/techlibs/intel/cyclone10lp/cells_map.v share/intel/cyclone10lp/cells_map.v 205s mkdir -p share/intel/cycloneiv 205s cp "./"/techlibs/intel/cycloneiv/cells_map.v share/intel/cycloneiv/cells_map.v 205s mkdir -p share/intel/cycloneive 205s cp "./"/techlibs/intel/cycloneive/cells_map.v share/intel/cycloneive/cells_map.v 205s mkdir -p share/intel_alm/common 205s cp "./"/techlibs/intel_alm/common/abc9_map.v share/intel_alm/common/abc9_map.v 205s mkdir -p share/intel_alm/common 205s cp "./"/techlibs/intel_alm/common/abc9_unmap.v share/intel_alm/common/abc9_unmap.v 205s mkdir -p share/intel_alm/common 205s cp "./"/techlibs/intel_alm/common/abc9_model.v share/intel_alm/common/abc9_model.v 205s mkdir -p share/intel_alm/common 205s cp "./"/techlibs/intel_alm/common/alm_map.v share/intel_alm/common/alm_map.v 205s mkdir -p share/intel_alm/common 205s cp "./"/techlibs/intel_alm/common/alm_sim.v share/intel_alm/common/alm_sim.v 205s mkdir -p share/intel_alm/common 205s cp "./"/techlibs/intel_alm/common/arith_alm_map.v share/intel_alm/common/arith_alm_map.v 205s mkdir -p share/intel_alm/common 205s cp "./"/techlibs/intel_alm/common/dff_map.v share/intel_alm/common/dff_map.v 205s mkdir -p share/intel_alm/common 205s cp "./"/techlibs/intel_alm/common/dff_sim.v share/intel_alm/common/dff_sim.v 205s mkdir -p share/intel_alm/common 205s cp "./"/techlibs/intel_alm/common/dsp_sim.v share/intel_alm/common/dsp_sim.v 205s mkdir -p share/intel_alm/common 205s cp "./"/techlibs/intel_alm/common/dsp_map.v share/intel_alm/common/dsp_map.v 205s mkdir -p share/intel_alm/common 205s cp "./"/techlibs/intel_alm/common/mem_sim.v share/intel_alm/common/mem_sim.v 205s mkdir -p share/intel_alm/common 205s cp "./"/techlibs/intel_alm/common/misc_sim.v share/intel_alm/common/misc_sim.v 205s mkdir -p share/intel_alm/cyclonev 205s cp "./"/techlibs/intel_alm/cyclonev/cells_sim.v share/intel_alm/cyclonev/cells_sim.v 205s mkdir -p share/intel_alm/common 205s cp "./"/techlibs/intel_alm/common/bram_m10k.txt share/intel_alm/common/bram_m10k.txt 205s mkdir -p share/intel_alm/common 205s cp "./"/techlibs/intel_alm/common/bram_m10k_map.v share/intel_alm/common/bram_m10k_map.v 205s mkdir -p share/intel_alm/common 205s cp "./"/techlibs/intel_alm/common/bram_m20k.txt share/intel_alm/common/bram_m20k.txt 205s mkdir -p share/intel_alm/common 205s cp "./"/techlibs/intel_alm/common/bram_m20k_map.v share/intel_alm/common/bram_m20k_map.v 205s mkdir -p share/intel_alm/common 205s cp "./"/techlibs/intel_alm/common/lutram_mlab.txt share/intel_alm/common/lutram_mlab.txt 205s mkdir -p share/intel_alm/common 205s cp "./"/techlibs/intel_alm/common/megafunction_bb.v share/intel_alm/common/megafunction_bb.v 205s mkdir -p share/intel_alm/common 205s cp "./"/techlibs/intel_alm/common/quartus_rename.v share/intel_alm/common/quartus_rename.v 205s mkdir -p share/lattice 205s cp "./"/techlibs/lattice/cells_ff.vh share/lattice/cells_ff.vh 205s mkdir -p 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205s mkdir -p share/lattice 205s cp "./"/techlibs/lattice/cells_bb_xo2.v share/lattice/cells_bb_xo2.v 205s mkdir -p share/lattice 205s cp "./"/techlibs/lattice/cells_bb_xo3.v share/lattice/cells_bb_xo3.v 205s mkdir -p share/lattice 205s cp "./"/techlibs/lattice/cells_bb_xo3d.v share/lattice/cells_bb_xo3d.v 205s mkdir -p share/lattice 205s cp "./"/techlibs/lattice/lutrams_map.v share/lattice/lutrams_map.v 205s mkdir -p share/lattice 205s cp "./"/techlibs/lattice/lutrams.txt share/lattice/lutrams.txt 205s mkdir -p share/lattice 205s cp "./"/techlibs/lattice/brams_map_16kd.v share/lattice/brams_map_16kd.v 205s mkdir -p share/lattice 205s cp "./"/techlibs/lattice/brams_16kd.txt share/lattice/brams_16kd.txt 205s mkdir -p share/lattice 205s cp "./"/techlibs/lattice/brams_map_8kc.v share/lattice/brams_map_8kc.v 205s mkdir -p share/lattice 205s cp "./"/techlibs/lattice/brams_8kc.txt share/lattice/brams_8kc.txt 205s mkdir -p share/lattice 205s cp "./"/techlibs/lattice/arith_map_ccu2c.v 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"./"/techlibs/xilinx/brams_xc2v.txt share/xilinx/brams_xc2v.txt 205s mkdir -p share/xilinx 205s cp "./"/techlibs/xilinx/brams_xc2v_map.v share/xilinx/brams_xc2v_map.v 205s mkdir -p share/xilinx 205s cp "./"/techlibs/xilinx/brams_xc3sda.txt share/xilinx/brams_xc3sda.txt 205s mkdir -p share/xilinx 205s cp "./"/techlibs/xilinx/brams_xc3sda_map.v share/xilinx/brams_xc3sda_map.v 205s mkdir -p share/xilinx 205s cp "./"/techlibs/xilinx/brams_xc4v.txt share/xilinx/brams_xc4v.txt 205s mkdir -p share/xilinx 205s cp "./"/techlibs/xilinx/brams_xc4v_map.v share/xilinx/brams_xc4v_map.v 205s mkdir -p share/xilinx 205s cp "./"/techlibs/xilinx/brams_xc5v_map.v share/xilinx/brams_xc5v_map.v 205s mkdir -p share/xilinx 205s cp "./"/techlibs/xilinx/brams_xc6v_map.v share/xilinx/brams_xc6v_map.v 205s mkdir -p share/xilinx 205s cp "./"/techlibs/xilinx/brams_xcu_map.v share/xilinx/brams_xcu_map.v 205s mkdir -p share/xilinx 205s cp "./"/techlibs/xilinx/urams.txt share/xilinx/urams.txt 205s mkdir -p share/xilinx 205s cp "./"/techlibs/xilinx/urams_map.v share/xilinx/urams_map.v 205s mkdir -p share/xilinx 205s cp "./"/techlibs/xilinx/arith_map.v share/xilinx/arith_map.v 205s mkdir -p share/xilinx 205s cp "./"/techlibs/xilinx/ff_map.v share/xilinx/ff_map.v 205s mkdir -p share/xilinx 205s cp "./"/techlibs/xilinx/lut_map.v share/xilinx/lut_map.v 205s mkdir -p share/xilinx 205s cp "./"/techlibs/xilinx/mux_map.v share/xilinx/mux_map.v 205s mkdir -p share/xilinx 205s cp "./"/techlibs/xilinx/xc3s_mult_map.v share/xilinx/xc3s_mult_map.v 205s mkdir -p share/xilinx 205s cp "./"/techlibs/xilinx/xc3sda_dsp_map.v share/xilinx/xc3sda_dsp_map.v 205s mkdir -p share/xilinx 205s cp "./"/techlibs/xilinx/xc6s_dsp_map.v share/xilinx/xc6s_dsp_map.v 205s mkdir -p share/xilinx 205s cp "./"/techlibs/xilinx/xc4v_dsp_map.v share/xilinx/xc4v_dsp_map.v 205s mkdir -p share/xilinx 205s cp "./"/techlibs/xilinx/xc5v_dsp_map.v share/xilinx/xc5v_dsp_map.v 205s mkdir -p share/xilinx 205s cp "./"/techlibs/xilinx/xc7_dsp_map.v share/xilinx/xc7_dsp_map.v 205s mkdir -p share/xilinx 205s cp "./"/techlibs/xilinx/xcu_dsp_map.v share/xilinx/xcu_dsp_map.v 205s mkdir -p share/xilinx 205s cp "./"/techlibs/xilinx/abc9_model.v share/xilinx/abc9_model.v 205s cd tests/simple && bash run-test.sh "" 205s make[1]: Entering directory '/tmp/autopkgtest.ldz5d8/build.yUl/src/tests/simple' 205s + gcc -Wall -o /tmp/autopkgtest.ldz5d8/build.yUl/src/tests/tools/cmp_tbdata /tmp/autopkgtest.ldz5d8/build.yUl/src/tests/tools/cmp_tbdata.c 206s Test: arrays02 -> ok 209s Test: asgn_binop -> ok 209s Test: case_expr_extend -> ok 209s Test: case_expr_query -> ok 209s Test: defvalue -> ok 210s Test: implicit_ports -> ok 210s Test: lesser_size_cast -> ok 210s Test: local_loop_var -> ok 211s Test: macro_arg_spaces -> ok 211s Test: matching_end_labels -> ok 211s Test: memwr_port_connection -> ok 211s Test: unnamed_block_decl -> ok 212s Test: aes_kexp128 -> ok 212s Test: always01 -> ok 212s Test: always02 -> ok 213s Test: always03 -> ok 213s Test: arraycells -> ok 214s Test: arrays01 -> ok 214s Test: attrib01_module -> ok 215s Test: attrib02_port_decl -> ok 215s Test: attrib03_parameter -> ok 216s Test: attrib04_net_var -> ok 216s Test: attrib06_operator_suffix -> ok 216s Test: attrib08_mod_inst -> ok 217s Test: attrib09_case -> ok 217s Test: carryadd -> ok 217s Test: case_expr_const -> ok 218s Test: case_expr_non_const -> ok 226s Test: case_large -> ok 227s Test: const_branch_finish -> ok 227s Test: const_fold_func -> ok 228s Test: const_func_shadow -> ok 230s Test: constmuldivmod -> ok 231s Test: constpower -> ok 232s Test: dff_different_styles -> ok 233s Test: dff_init -> ok 235s Test: dynslice -> ok 235s Test: fiedler-cooley -> ok 236s Test: forgen01 -> ok 236s Test: forgen02 -> ok 237s Test: forloops -> ok 237s Test: fsm -> ok 238s Test: func_block -> ok 238s Test: func_recurse -> ok 239s Test: func_width_scope -> ok 239s Test: genblk_collide -> ok 239s Test: genblk_dive -> ok 240s Test: genblk_order -> ok 240s Test: genblk_port_shadow -> ok 243s Test: generate -> ok 243s Test: graphtest -> ok 243s Test: hierarchy -> ok 244s Test: hierdefparam -> ok 245s Test: i2c_master_tests -> ok 245s Test: ifdef_1 -> ok 245s Test: ifdef_2 -> ok 245s Test: localparam_attr -> ok 246s Test: loop_prefix_case -> ok 246s Test: loop_var_shadow -> ok 246s Test: loops -> ok 247s Test: macro_arg_surrounding_spaces -> ok 247s Test: macros -> ok 249s Test: mem2reg -> ok 249s Test: mem2reg_bounds_tern -> ok 250s Test: mem_arst -> ok 258s Test: memory -> ok 259s Test: module_scope -> ok 259s Test: module_scope_case -> ok 259s Test: module_scope_func -> ok 260s Test: multiplier -> ok 261s Test: muxtree -> ok 261s Test: named_genblk -> ok 262s Test: nested_genblk_resolve -> ok 262s Test: omsp_dbg_uart -> ok 267s Test: operators -> ok 267s Test: param_attr -> ok 268s Test: paramods -> ok 273s Test: partsel -> ok 274s Test: process -> ok 275s Test: realexpr -> ok 275s Test: repwhile -> ok 276s Test: retime -> ok 281s Test: rotate -> ok 281s Test: scopes -> ok 282s Test: signed_full_slice -> ok 282s Test: signedexpr -> ok 284s Test: sincos -> ok 284s Test: specify -> ok 284s Test: string_format -> ok 285s Test: subbytes -> ok 286s Test: task_func -> ok 287s Test: undef_eqx_nex -> ok 287s Test: usb_phy_tests -> ok 288s Test: values -> ok 288s Test: verilog_primitives -> ok 289s Test: vloghammer -> ok 290s Test: wandwor -> ok 291s Test: wreduce -> ok 291s make[1]: Leaving directory '/tmp/autopkgtest.ldz5d8/build.yUl/src/tests/simple' 291s cd tests/simple_abc9 && bash run-test.sh "" 291s ls: cannot access '*.sv': No such file or directory 291s make[1]: Entering directory '/tmp/autopkgtest.ldz5d8/build.yUl/src/tests/simple_abc9' 294s Test: abc9 -> ok 294s Test: aes_kexp128 -> ok 294s Test: always01 -> ok 295s Test: always02 -> ok 295s Test: always03 -> ok 295s Test: arraycells -> ok 295s Test: arrays01 -> ok 296s Test: attrib01_module -> ok 296s Test: attrib02_port_decl -> ok 296s Test: attrib03_parameter -> ok 297s Test: attrib04_net_var -> ok 297s Test: attrib06_operator_suffix -> ok 297s Test: attrib08_mod_inst -> ok 298s Test: attrib09_case -> ok 298s Test: carryadd -> ok 298s Test: case_expr_const -> ok 298s Test: case_expr_non_const -> ok 314s Test: case_large -> ok 315s Test: const_branch_finish -> ok 315s Test: const_fold_func -> ok 316s Test: const_func_shadow -> ok 318s Test: constmuldivmod -> ok 319s Test: constpower -> ok 319s Test: dff_different_styles -> ok 320s Test: dff_init -> ok 329s Test: dynslice -> ok 330s Test: fiedler-cooley -> ok 330s Test: forgen01 -> ok 330s Test: forgen02 -> ok 331s Test: forloops -> ok 331s Test: fsm -> ok 331s Test: func_block -> ok 331s Test: func_recurse -> ok 332s Test: func_width_scope -> ok 332s Test: genblk_collide -> ok 332s Test: genblk_dive -> ok 332s Test: genblk_order -> ok 333s Test: genblk_port_shadow -> ok 335s Test: generate -> ok 335s Test: graphtest -> ok 335s Test: hierarchy -> ok 336s Test: hierdefparam -> ok 337s Test: i2c_master_tests -> ok 337s Test: ifdef_1 -> ok 337s Test: ifdef_2 -> ok 337s Test: localparam_attr -> ok 337s Test: loop_prefix_case -> ok 337s Test: loop_var_shadow -> ok 338s Test: loops -> ok 338s Test: macro_arg_surrounding_spaces -> ok 339s Test: macros -> ok 340s Test: mem2reg -> ok 340s Test: mem2reg_bounds_tern -> ok 341s Test: mem_arst -> ok 345s Test: memory -> ok 345s Test: module_scope -> ok 345s Test: module_scope_case -> ok 346s Test: module_scope_func -> ok 346s Test: multiplier -> ok 347s Test: muxtree -> ok 347s Test: named_genblk -> ok 347s Test: nested_genblk_resolve -> ok 347s Test: omsp_dbg_uart -> ok 355s Test: operators -> ok 355s Test: param_attr -> ok 356s Test: paramods -> ok 362s Test: partsel -> ok 363s Test: process -> ok 363s Test: realexpr -> ok 364s Test: repwhile -> ok 364s Test: retime -> ok 366s Test: rotate -> ok 366s Test: scopes -> ok 367s Test: signed_full_slice -> ok 367s Test: signedexpr -> ok 370s Test: sincos -> ok 370s Test: string_format -> ok 370s Test: subbytes -> ok 371s Test: task_func -> ok 371s Test: undef_eqx_nex -> ok 372s Test: usb_phy_tests -> ok 372s Test: values -> ok 372s Test: verilog_primitives -> ok 373s Test: vloghammer -> ok 374s Test: wandwor -> ok 375s Test: wreduce -> ok 376s Test: arrays02 -> ok 377s Test: asgn_binop -> ok 377s Test: case_expr_extend -> ok 378s Test: case_expr_query -> ok 378s Test: defvalue -> ok 378s Test: implicit_ports -> ok 379s Test: lesser_size_cast -> ok 379s Test: local_loop_var -> ok 380s Test: macro_arg_spaces -> ok 380s Test: matching_end_labels -> ok 381s Test: memwr_port_connection -> ok 381s Test: unnamed_block_decl -> ok 381s make[1]: Leaving directory '/tmp/autopkgtest.ldz5d8/build.yUl/src/tests/simple_abc9' 381s cd tests/hana && bash run-test.sh "" 381s make[1]: Entering directory '/tmp/autopkgtest.ldz5d8/build.yUl/src/tests/hana' 385s Test: test_intermout -> ok 385s Test: test_parse2synthtrans -> ok 386s Test: test_parser -> ok 387s Test: test_simulation_always -> ok 388s Test: test_simulation_and -> ok 388s Test: test_simulation_buffer -> ok 389s Test: test_simulation_decoder -> ok 390s Test: test_simulation_inc -> ok 392s Test: test_simulation_mux -> ok 392s Test: test_simulation_nand -> ok 393s Test: test_simulation_nor -> ok 393s Test: test_simulation_or -> ok 394s Test: test_simulation_seq -> ok 396s Test: test_simulation_shifter -> ok 397s Test: test_simulation_sop -> ok 399s Test: test_simulation_techmap -> ok 401s Test: test_simulation_techmap_tech -> ok 402s Test: test_simulation_vlib -> ok 402s Test: test_simulation_xnor -> ok 403s Test: test_simulation_xor -> ok 403s make[1]: Leaving directory '/tmp/autopkgtest.ldz5d8/build.yUl/src/tests/hana' 403s cd tests/asicworld && bash run-test.sh "" 403s make[1]: Entering directory '/tmp/autopkgtest.ldz5d8/build.yUl/src/tests/asicworld' 403s Test: code_hdl_models_GrayCounter -> ok 403s Test: code_hdl_models_arbiter -> ok 413s Test: code_hdl_models_cam -> ok 413s Test: code_hdl_models_clk_div -> ok 413s Test: code_hdl_models_clk_div_45 -> ok 414s Test: code_hdl_models_d_ff_gates -> ok 414s Test: code_hdl_models_d_latch_gates -> ok 414s Test: code_hdl_models_decoder_2to4_gates -> ok 414s Test: code_hdl_models_decoder_using_assign -> ok 415s Test: code_hdl_models_decoder_using_case -> ok 415s Test: code_hdl_models_dff_async_reset -> ok 415s Test: code_hdl_models_dff_sync_reset -> ok 416s Test: code_hdl_models_encoder_4to2_gates -> ok 416s Test: code_hdl_models_encoder_using_case -> ok 416s Test: code_hdl_models_encoder_using_if -> ok 417s Test: code_hdl_models_full_adder_gates -> ok 417s Test: code_hdl_models_full_subtracter_gates -> ok 417s Test: code_hdl_models_gray_counter -> ok 418s Test: code_hdl_models_half_adder_gates -> ok 418s Test: code_hdl_models_lfsr -> ok 419s Test: code_hdl_models_lfsr_updown -> ok 419s Test: code_hdl_models_mux_2to1_gates -> ok 419s Test: code_hdl_models_mux_using_assign -> ok 419s Test: code_hdl_models_mux_using_case -> ok 419s Test: code_hdl_models_mux_using_if -> ok 420s Test: code_hdl_models_one_hot_cnt -> ok 420s Test: code_hdl_models_parallel_crc -> ok 420s Test: code_hdl_models_parity_using_assign -> ok 421s Test: code_hdl_models_parity_using_bitwise -> ok 421s Test: code_hdl_models_parity_using_function -> ok 421s Test: code_hdl_models_pri_encoder_using_assign -> ok 422s Test: code_hdl_models_rom_using_case -> ok 422s Test: code_hdl_models_serial_crc -> ok 422s Test: code_hdl_models_tff_async_reset -> ok 423s Test: code_hdl_models_tff_sync_reset -> ok 425s Test: code_hdl_models_uart -> ok 425s Test: code_hdl_models_up_counter -> ok 425s Test: code_hdl_models_up_counter_load -> ok 426s Test: code_hdl_models_up_down_counter -> ok 426s Test: code_specman_switch_fabric -> ok 426s Test: code_tidbits_asyn_reset -> ok 427s Test: code_tidbits_blocking -> ok 427s Test: code_tidbits_fsm_using_always -> ok 427s Test: code_tidbits_fsm_using_function -> ok 428s Test: code_tidbits_fsm_using_single_always -> ok 428s Test: code_tidbits_nonblocking -> ok 429s Test: code_tidbits_reg_combo_example -> ok 429s Test: code_tidbits_reg_seq_example -> ok 429s Test: code_tidbits_syn_reset -> ok 429s Test: code_tidbits_wire_example -> ok 430s Test: code_verilog_tutorial_addbit -> ok 430s Test: code_verilog_tutorial_always_example -> ok 430s Test: code_verilog_tutorial_bus_con -> ok 430s Test: code_verilog_tutorial_comment -> ok 430s Test: code_verilog_tutorial_counter -> ok 431s Test: code_verilog_tutorial_d_ff -> ok 431s Test: code_verilog_tutorial_decoder -> ok 431s Test: code_verilog_tutorial_decoder_always -> ok 432s Test: code_verilog_tutorial_escape_id -> ok 432s Test: code_verilog_tutorial_explicit -> ok 432s Test: code_verilog_tutorial_first_counter -> ok 433s Test: code_verilog_tutorial_flip_flop -> ok 433s Test: code_verilog_tutorial_fsm_full -> ok 433s Test: code_verilog_tutorial_good_code -> ok 434s Test: code_verilog_tutorial_if_else -> ok 434s Test: code_verilog_tutorial_multiply -> ok 434s Test: code_verilog_tutorial_mux_21 -> ok 434s Test: code_verilog_tutorial_n_out_primitive -> ok 435s Test: code_verilog_tutorial_parallel_if -> ok 435s Test: code_verilog_tutorial_parity -> ok 435s Test: code_verilog_tutorial_simple_function -> ok 435s Test: code_verilog_tutorial_simple_if -> ok 435s Test: code_verilog_tutorial_task_global -> ok 436s Test: code_verilog_tutorial_tri_buf -> ok 436s Test: code_verilog_tutorial_v2k_reg -> ok 436s Test: code_verilog_tutorial_which_clock -> ok 436s make[1]: Leaving directory '/tmp/autopkgtest.ldz5d8/build.yUl/src/tests/asicworld' 436s # +cd tests/realmath && bash run-test.sh "" 436s cd tests/share && bash run-test.sh "" 436s generating tests.. 436s running tests.. 439s [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41][42][43][44][45][46][47][48][49][50][51][52][53][54][55][56][57][58][59][60][61][62][63][64][65][66][67][68][69][70][71][72][73][74][75][76][77][78][79][80][81][82][83][84][85][86][87][88][89][90][91][92][93][94][95][96][97][98][99] 439s cd tests/opt_share && bash run-test.sh "" 439s generating tests.. 439s running tests.. 439s make[1]: Entering directory '/tmp/autopkgtest.ldz5d8/build.yUl/src/tests/opt_share' 480s [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41][42][43][44][45][46][47][48][49][50][51][52][53][54][55][56][57][58][59][60][61][62][63][64][65][66][67][68][69][70][71][72][73][74][75][76][77][78][79][80][81][82][83][84][85][86][87][88][89][90][91][92][93][94][95][96][97][98][99]make[1]: Leaving directory '/tmp/autopkgtest.ldz5d8/build.yUl/src/tests/opt_share' 480s 480s cd tests/fsm && bash run-test.sh "" 480s generating tests.. 480s PRNG seed: 4157291289506992235 480s running tests.. 480s make[1]: Entering directory '/tmp/autopkgtest.ldz5d8/build.yUl/src/tests/fsm' 482s [0]K[1]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 482s Users of state reg look like FSM recoding might result in larger circuit. 482s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 484s K[2]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 484s Users of state reg look like FSM recoding might result in larger circuit. 484s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 489s K[3]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 489s Users of state reg look like FSM recoding might result in larger circuit. 489s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 490s K[4]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 490s Users of state reg look like FSM recoding might result in larger circuit. 490s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 493s K[5]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 493s Users of state reg look like FSM recoding might result in larger circuit. 493s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 494s K[6]K[7]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 494s Users of state reg look like FSM recoding might result in larger circuit. 494s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 497s K[8]K[9]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 497s Users of state reg look like FSM recoding might result in larger circuit. 497s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 500s K[10]K[11]K[12]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 500s Users of state reg look like FSM recoding might result in larger circuit. 500s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 502s K[13]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 502s Users of state reg look like FSM recoding might result in larger circuit. 502s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 528s T[14]K[15]K[16]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 528s Users of state reg look like FSM recoding might result in larger circuit. 528s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 529s K[17]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 529s Users of state reg look like FSM recoding might result in larger circuit. 529s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 531s K[18]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 531s Users of state reg look like FSM recoding might result in larger circuit. 531s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 532s K[19]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 532s Users of state reg look like FSM recoding might result in larger circuit. 532s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 533s K[20]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 533s Users of state reg look like FSM recoding might result in larger circuit. 533s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 533s K[21]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 533s Users of state reg look like FSM recoding might result in larger circuit. 533s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 537s K[22]K[23]K[24]K[25]K[26]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 537s Users of state reg look like FSM recoding might result in larger circuit. 537s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 538s K[27]K[28]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 538s Users of state reg look like FSM recoding might result in larger circuit. 538s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 539s K[29]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 539s Users of state reg look like FSM recoding might result in larger circuit. 539s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 541s K[30]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 541s Users of state reg look like FSM recoding might result in larger circuit. 541s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 543s K[31]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 543s Users of state reg look like FSM recoding might result in larger circuit. 543s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 547s K[32]K[33]K[34]K[35]K[36]K[37]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 547s Users of state reg look like FSM recoding might result in larger circuit. 547s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 547s K[38]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 547s Users of state reg look like FSM recoding might result in larger circuit. 547s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 549s K[39]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 549s Users of state reg look like FSM recoding might result in larger circuit. 549s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 552s K[40]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 552s Users of state reg look like FSM recoding might result in larger circuit. 552s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 557s K[41]K[42]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 557s Users of state reg look like FSM recoding might result in larger circuit. 557s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 557s KWarning: Regarding the user-specified fsm_encoding attribute on gate.state: 557s Users of state reg look like FSM recoding might result in larger circuit. 557s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 557s Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 557s Users of state reg look like FSM recoding might result in larger circuit. 557s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 559s [43]K[44]K[45]K[46]K[47]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 559s Users of state reg look like FSM recoding might result in larger circuit. 559s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 562s K[48]K[49]K 562s make[1]: Leaving directory '/tmp/autopkgtest.ldz5d8/build.yUl/src/tests/fsm' 562s cd tests/techmap && bash run-test.sh 562s make[1]: Entering directory '/tmp/autopkgtest.ldz5d8/build.yUl/src/tests/techmap' 563s Passed abc9.ys 563s Warning: wire '\Q' is assigned in a block at < ok 576s Test: firrtl_938 -> ok 577s Test: implicit_en -> ok 579s Test: issue00335 -> ok 581s Test: issue00710 -> ok 581s Test: no_implicit_en -> ok 582s Test: read_arst -> ok 584s Test: read_two_mux -> ok 584s Test: shared_ports -> ok 585s Test: simple_sram_byte_en -> ok 586s Test: trans_addr_enable -> ok 587s Test: trans_sdp -> ok 589s Test: trans_sp -> ok 590s Test: wide_all -> ok 591s Test: wide_read_async -> ok 592s Test: wide_read_mixed -> ok 593s Test: wide_read_sync -> ok 594s Test: wide_read_trans -> ok 595s Test: wide_thru_priority -> ok 596s Test: wide_write -> ok 596s make[1]: Leaving directory '/tmp/autopkgtest.ldz5d8/build.yUl/src/tests/memories' 596s Testing expectations for amber23_sram_byte_en.v .. ok. 596s Testing expectations for implicit_en.v .. ok. 597s Testing expectations for issue00335.v .. ok. 597s Testing expectations for issue00710.v .. ok. 597s Testing expectations for no_implicit_en.v .. ok. 597s Testing expectations for read_arst.v .. ok. 597s Testing expectations for read_two_mux.v .. ok. 597s Testing expectations for shared_ports.v .. ok. 597s Testing expectations for simple_sram_byte_en.v .. ok. 597s Testing expectations for trans_addr_enable.v .. ok. 597s Testing expectations for trans_sdp.v .. ok. 597s Testing expectations for trans_sp.v .. ok. 597s Testing expectations for wide_all.v .. ok. 597s Testing expectations for wide_read_async.v .. ok. 597s Testing expectations for wide_read_mixed.v .. ok. 597s Testing expectations for wide_read_sync.v .. ok. 597s Testing expectations for wide_read_trans.v .. ok. 598s Testing expectations for wide_thru_priority.v .. ok. 598s Testing expectations for wide_write.v .. ok. 598s cd tests/memlib && bash run-test.sh "" 598s make[1]: Entering directory '/tmp/autopkgtest.ldz5d8/build.yUl/src/tests/memlib' 599s Test: t_async_big -> ok 603s Test: t_async_big_block -> ok 603s Test: t_async_small -> ok 603s Test: t_async_small_block -> ok 603s Test: t_sync_big -> ok 603s Test: t_sync_big_sdp -> ok 605s Test: t_sync_big_lut -> ok 605s Test: t_sync_small -> ok 605s Test: t_sync_small_block -> ok 606s Test: t_sync_small_block_attr -> ok 606s Test: t_init_lut_zeros_zero -> ok 606s Test: t_init_lut_zeros_any -> ok 606s Test: t_init_lut_val_zero -> ok 606s Test: t_init_lut_val_any -> ok 606s Test: t_init_lut_val_no_undef -> ok 607s Test: t_init_lut_val2_any -> ok 607s Test: t_init_lut_val2_no_undef -> ok 607s Test: t_init_lut_x_none -> ok 607s Test: t_init_lut_x_zero -> ok 607s Test: t_init_lut_x_any -> ok 608s Test: t_init_lut_x_no_undef -> ok 608s Test: t_ram_18b2B -> ok 608s Test: t_ram_9b1B -> ok 608s Test: t_ram_4b1B -> ok 608s Test: t_ram_2b1B -> ok 608s Test: t_ram_1b1B -> ok 609s Test: t_init_9b1B_zeros_zero -> ok 609s Test: t_init_9b1B_zeros_any -> ok 609s Test: t_init_9b1B_val_zero -> ok 609s Test: t_init_9b1B_val_any -> ok 609s Test: t_init_9b1B_val_no_undef -> ok 609s Test: t_init_13b2B_val_any -> ok 610s Test: t_init_18b2B_val_any -> ok 610s Test: t_init_18b2B_val_no_undef -> ok 610s Test: t_init_4b1B_x_none -> ok 610s Test: t_init_4b1B_x_zero -> ok 610s Test: t_init_4b1B_x_any -> ok 611s Test: t_init_4b1B_x_no_undef -> ok 611s Test: t_clock_a4_wANYrANYsFalse -> ok 611s Test: t_clock_a4_wANYrNEGsFalse -> ok 611s Test: t_clock_a4_wANYrPOSsFalse -> ok 611s Test: t_clock_a4_wNEGrANYsFalse -> ok 611s Test: t_clock_a4_wNEGrPOSsFalse -> ok 612s Test: t_clock_a4_wNEGrNEGsFalse -> ok 612s Test: t_clock_a4_wPOSrANYsFalse -> ok 612s Test: t_clock_a4_wPOSrNEGsFalse -> ok 612s Test: t_clock_a4_wPOSrPOSsFalse -> ok 612s Test: t_clock_a4_wANYrANYsTrue -> ok 612s Test: t_clock_a4_wNEGrPOSsTrue -> ok 613s Test: t_clock_a4_wNEGrNEGsTrue -> ok 613s Test: t_clock_a4_wPOSrNEGsTrue -> ok 613s Test: t_clock_a4_wPOSrPOSsTrue -> ok 613s Test: t_unmixed -> ok 613s Test: t_mixed_9_18 -> ok 613s Test: t_mixed_18_9 -> ok 614s Test: t_mixed_36_9 -> ok 614s Test: t_mixed_4_2 -> ok 614s Test: t_tdp -> ok 614s Test: t_sync_2clk -> ok 614s Test: t_sync_shared -> ok 615s Test: t_sync_2clk_shared -> ok 615s Test: t_sync_trans_old_old -> ok 615s Test: t_sync_trans_old_new -> ok 615s Test: t_sync_trans_old_none -> ok 615s Test: t_sync_trans_new_old -> ok 615s Test: t_sync_trans_new_new -> ok 616s Test: t_sync_trans_new_none -> ok 616s Test: t_sp_nc_none -> ok 616s Test: t_sp_new_none -> ok 616s Test: t_sp_old_none -> ok 616s Test: t_sp_nc_nc -> ok 616s Test: t_sp_new_nc -> ok 617s Test: t_sp_old_nc -> ok 617s Test: t_sp_nc_new -> ok 617s Test: t_sp_new_new -> ok 617s Test: t_sp_old_new -> ok 617s Test: t_sp_nc_old -> ok 617s Test: t_sp_new_old -> ok 618s Test: t_sp_old_old -> ok 618s Test: t_sp_nc_new_only -> ok 618s Test: t_sp_new_new_only -> ok 618s Test: t_sp_old_new_only -> ok 618s Test: t_sp_nc_new_only_be -> ok 618s Test: t_sp_new_new_only_be -> ok 619s Test: t_sp_old_new_only_be -> ok 619s Test: t_sp_nc_new_be -> ok 619s Test: t_sp_new_new_be -> ok 619s Test: t_sp_old_new_be -> ok 619s Test: t_sp_nc_old_be -> ok 619s Test: t_sp_new_old_be -> ok 620s Test: t_sp_old_old_be -> ok 620s Test: t_sp_nc_nc_be -> ok 620s Test: t_sp_new_nc_be -> ok 620s Test: t_sp_old_nc_be -> ok 620s Test: t_sp_nc_auto -> ok 621s Test: t_sp_new_auto -> ok 621s Test: t_sp_old_auto -> ok 621s Test: t_sp_nc_auto_be -> ok 621s Test: t_sp_new_auto_be -> ok 621s Test: t_sp_old_auto_be -> ok 621s Test: t_sp_init_x_x -> ok 621s Test: t_sp_init_x_x_re -> ok 622s Test: t_sp_init_x_x_ce -> ok 622s Test: t_sp_init_0_x -> ok 622s Test: t_sp_init_0_x_re -> ok 622s Test: t_sp_init_0_0 -> ok 622s Test: t_sp_init_0_0_re -> ok 622s Test: t_sp_init_0_any -> ok 623s Test: t_sp_init_0_any_re -> ok 623s Test: t_sp_init_v_x -> ok 623s Test: t_sp_init_v_x_re -> ok 624s Test: t_sp_init_v_0 -> ok 624s Test: t_sp_init_v_0_re -> ok 624s Test: t_sp_init_v_any -> ok 624s Test: t_sp_init_v_any_re -> ok 624s Test: t_sp_arst_x_x -> ok 624s Test: t_sp_arst_x_x_re -> ok 624s Test: t_sp_arst_0_x -> ok 624s Test: t_sp_arst_0_x_re -> ok 624s Test: t_sp_arst_0_0 -> ok 625s Test: t_sp_arst_0_0_re -> ok 625s Test: t_sp_arst_0_any -> ok 625s Test: t_sp_arst_0_any_re -> ok 625s Test: t_sp_arst_0_init -> ok 625s Test: t_sp_arst_0_init_re -> ok 625s Test: t_sp_arst_v_x -> ok 626s Test: t_sp_arst_v_x_re -> ok 626s Test: t_sp_arst_v_0 -> ok 626s Test: t_sp_arst_v_0_re -> ok 626s Test: t_sp_arst_v_any -> ok 626s Test: t_sp_arst_v_any_re -> ok 626s Test: t_sp_arst_v_init -> ok 627s Test: t_sp_arst_v_init_re -> ok 627s Test: t_sp_arst_e_x -> ok 627s Test: t_sp_arst_e_x_re -> ok 627s Test: t_sp_arst_e_0 -> ok 627s Test: t_sp_arst_e_0_re -> ok 627s Test: t_sp_arst_e_any -> ok 628s Test: t_sp_arst_e_any_re -> ok 628s Test: t_sp_arst_e_init -> ok 628s Test: t_sp_arst_e_init_re -> ok 628s Test: t_sp_arst_n_x -> ok 628s Test: t_sp_arst_n_x_re -> ok 628s Test: t_sp_arst_n_0 -> ok 629s Test: t_sp_arst_n_0_re -> ok 629s Test: t_sp_arst_n_any -> ok 630s Test: t_sp_arst_n_any_re -> ok 630s Test: t_sp_arst_n_init -> ok 630s Test: t_sp_arst_n_init_re -> ok 630s Test: t_sp_srst_x_x -> ok 630s Test: t_sp_srst_x_x_re -> ok 630s Test: t_sp_srst_0_x -> ok 630s Test: t_sp_srst_0_x_re -> ok 630s Test: t_sp_srst_0_0 -> ok 630s Test: t_sp_srst_0_0_re -> ok 630s Test: t_sp_srst_0_any -> ok 631s Test: t_sp_srst_0_any_re -> ok 631s Test: t_sp_srst_0_init -> ok 631s Test: t_sp_srst_0_init_re -> ok 631s Test: t_sp_srst_v_x -> ok 631s Test: t_sp_srst_v_x_re -> ok 632s Test: t_sp_srst_v_0 -> ok 632s Test: t_sp_srst_v_0_re -> ok 632s Test: t_sp_srst_v_any -> ok 632s Test: t_sp_srst_v_any_re -> ok 632s Test: t_sp_srst_v_any_re_gated -> ok 632s Test: t_sp_srst_v_any_ce -> ok 633s Test: t_sp_srst_v_any_ce_gated -> ok 633s Test: t_sp_srst_v_init -> ok 633s Test: t_sp_srst_v_init_re -> ok 633s Test: t_sp_srst_e_x -> ok 633s Test: t_sp_srst_e_x_re -> ok 633s Test: t_sp_srst_e_0 -> ok 634s Test: t_sp_srst_e_0_re -> ok 634s Test: t_sp_srst_e_any -> ok 634s Test: t_sp_srst_e_any_re -> ok 634s Test: t_sp_srst_e_init -> ok 634s Test: t_sp_srst_e_init_re -> ok 635s Test: t_sp_srst_n_x -> ok 635s Test: t_sp_srst_n_x_re -> ok 635s Test: t_sp_srst_n_0 -> ok 635s Test: t_sp_srst_n_0_re -> ok 635s Test: t_sp_srst_n_any -> ok 635s Test: t_sp_srst_n_any_re -> ok 636s Test: t_sp_srst_n_init -> ok 636s Test: t_sp_srst_n_init_re -> ok 636s Test: t_sp_srst_gv_x -> ok 636s Test: t_sp_srst_gv_x_re -> ok 636s Test: t_sp_srst_gv_0 -> ok 636s Test: t_sp_srst_gv_0_re -> ok 637s Test: t_sp_srst_gv_any -> ok 637s Test: t_sp_srst_gv_any_re -> ok 637s Test: t_sp_srst_gv_any_re_gated -> ok 637s Test: t_sp_srst_gv_any_ce -> ok 638s Test: t_sp_srst_gv_any_ce_gated -> ok 638s Test: t_sp_srst_gv_init -> ok 638s Test: t_sp_srst_gv_init_re -> ok 638s Test: t_wren_a4d4_NO_BYTE -> ok 638s Test: t_wren_a5d4_NO_BYTE -> ok 639s Test: t_wren_a6d4_NO_BYTE -> ok 639s Test: t_wren_a3d8_NO_BYTE -> ok 639s Test: t_wren_a4d8_NO_BYTE -> ok 639s Test: t_wren_a4d4_W4_B4 -> ok 640s Test: t_wren_a4d8_W4_B4_separate -> ok 640s Test: t_wren_a4d8_W8_B4 -> ok 640s Test: t_wren_a4d8_W8_B4_separate -> ok 640s Test: t_wren_a4d8_W8_B8 -> ok 641s Test: t_wren_a4d8_W8_B8_separate -> ok 641s Test: t_wren_a4d2w8_W16_B4 -> ok 641s Test: t_wren_a4d2w8_W16_B4_separate -> ok 641s Test: t_wren_a4d4w4_W16_B4 -> ok 642s Test: t_wren_a4d4w4_W16_B4_separate -> ok 642s Test: t_wren_a5d4w2_W16_B4 -> ok 642s Test: t_wren_a5d4w2_W16_B4_separate -> ok 642s Test: t_wren_a5d4w4_W16_B4 -> ok 643s Test: t_wren_a5d4w4_W16_B4_separate -> ok 643s Test: t_wren_a4d8w2_W16_B4 -> ok 643s Test: t_wren_a4d8w2_W16_B4_separate -> ok 644s Test: t_wren_a5d8w1_W16_B4 -> ok 644s Test: t_wren_a5d8w1_W16_B4_separate -> ok 644s Test: t_wren_a5d8w2_W16_B4 -> ok 644s Test: t_wren_a5d8w2_W16_B4_separate -> ok 645s Test: t_wren_a4d16w1_W16_B4 -> ok 645s Test: t_wren_a4d16w1_W16_B4_separate -> ok 645s Test: t_wren_a4d4w2_W8_B8 -> ok 645s Test: t_wren_a4d4w2_W8_B8_separate -> ok 646s Test: t_wren_a4d4w1_W8_B8 -> ok 646s Test: t_wren_a4d4w1_W8_B8_separate -> ok 646s Test: t_wren_a4d8w2_W8_B8 -> ok 646s Test: t_wren_a4d8w2_W8_B8_separate -> ok 646s Test: t_wren_a3d8w2_W8_B8 -> ok 646s Test: t_wren_a3d8w2_W8_B8_separate -> ok 647s Test: t_wren_a4d4w2_W8_B4 -> ok 647s Test: t_wren_a4d4w2_W8_B4_separate -> ok 647s Test: t_wren_a4d2w4_W8_B4 -> ok 647s Test: t_wren_a4d2w4_W8_B4_separate -> ok 647s Test: t_wren_a4d4w4_W8_B4 -> ok 648s Test: t_wren_a4d4w4_W8_B4_separate -> ok 648s Test: t_wren_a4d4w4_W4_B4 -> ok 648s Test: t_wren_a4d4w4_W4_B4_separate -> ok 648s Test: t_wren_a4d4w5_W4_B4 -> ok 648s Test: t_wren_a4d4w5_W4_B4_separate -> ok 648s Test: t_geom_a4d64_wren -> ok 649s Test: t_geom_a5d32_wren -> ok 649s Test: t_geom_a5d64_wren -> ok 649s Test: t_geom_a6d16_wren -> ok 649s Test: t_geom_a6d30_wren -> ok 649s Test: t_geom_a6d64_wren -> ok 649s Test: t_geom_a7d4_wren -> ok 650s Test: t_geom_a7d6_wren -> ok 650s Test: t_geom_a7d8_wren -> ok 650s Test: t_geom_a7d17_wren -> ok 650s Test: t_geom_a8d4_wren -> ok 650s Test: t_geom_a8d6_wren -> ok 651s Test: t_geom_a9d4_wren -> ok 651s Test: t_geom_a9d8_wren -> ok 651s Test: t_geom_a9d5_wren -> ok 651s Test: t_geom_a9d6_wren -> ok 651s Test: t_geom_a3d18_9b1B -> ok 652s Test: t_geom_a4d4_9b1B -> ok 652s Test: t_geom_a4d18_9b1B -> ok 652s Test: t_geom_a5d32_9b1B -> ok 652s Test: t_geom_a6d4_9b1B -> ok 652s Test: t_geom_a7d11_9b1B -> ok 652s Test: t_geom_a7d18_9b1B -> ok 653s Test: t_geom_a11d1_9b1B -> ok 653s Test: t_wide_sdp_a6r1w1b1x1 -> ok 653s Test: t_wide_sdp_a7r1w1b1x1 -> ok 653s Test: t_wide_sdp_a8r1w1b1x1 -> ok 653s Test: t_wide_sdp_a6r0w0b0x0 -> ok 653s Test: t_wide_sdp_a6r1w0b0x0 -> ok 654s Test: t_wide_sdp_a6r2w0b0x0 -> ok 654s Test: t_wide_sdp_a6r3w0b0x0 -> ok 654s Test: t_wide_sdp_a6r4w0b0x0 -> ok 654s Test: t_wide_sdp_a6r5w0b0x0 -> ok 655s Test: t_wide_sdp_a6r0w1b0x0 -> ok 655s Test: t_wide_sdp_a6r0w1b1x0 -> ok 655s Test: t_wide_sdp_a6r0w2b0x0 -> ok 655s Test: t_wide_sdp_a6r0w2b2x0 -> ok 655s Test: t_wide_sdp_a6r0w3b2x0 -> ok 656s Test: t_wide_sdp_a6r0w4b2x0 -> ok 656s Test: t_wide_sdp_a6r0w5b2x0 -> ok 656s Test: t_wide_sdp_a7r0w0b0x0 -> ok 656s Test: t_wide_sdp_a7r1w0b0x0 -> ok 657s Test: t_wide_sdp_a7r2w0b0x0 -> ok 657s Test: t_wide_sdp_a7r3w0b0x0 -> ok 657s Test: t_wide_sdp_a7r4w0b0x0 -> ok 657s Test: t_wide_sdp_a7r5w0b0x0 -> ok 657s Test: t_wide_sdp_a7r0w1b0x0 -> ok 658s Test: t_wide_sdp_a7r0w1b1x0 -> ok 658s Test: t_wide_sdp_a7r0w2b0x0 -> ok 658s Test: t_wide_sdp_a7r0w2b2x0 -> ok 658s Test: t_wide_sdp_a7r0w3b2x0 -> ok 658s Test: t_wide_sdp_a7r0w4b2x0 -> ok 659s Test: t_wide_sdp_a7r0w5b2x0 -> ok 659s Test: t_wide_sp_mix_a6r1w1b1 -> ok 659s Test: t_wide_sp_mix_a7r1w1b1 -> ok 659s Test: t_wide_sp_mix_a8r1w1b1 -> ok 659s Test: t_wide_sp_mix_a6r0w0b0 -> ok 660s Test: t_wide_sp_mix_a6r1w0b0 -> ok 660s Test: t_wide_sp_mix_a6r2w0b0 -> ok 660s Test: t_wide_sp_mix_a6r3w0b0 -> ok 660s Test: t_wide_sp_mix_a6r4w0b0 -> ok 661s Test: t_wide_sp_mix_a6r5w0b0 -> ok 661s Test: t_wide_sp_mix_a6r0w1b0 -> ok 661s Test: t_wide_sp_mix_a6r0w1b1 -> ok 661s Test: t_wide_sp_mix_a6r0w2b0 -> ok 661s Test: t_wide_sp_mix_a6r0w2b2 -> ok 661s Test: t_wide_sp_mix_a6r0w3b2 -> ok 662s Test: t_wide_sp_mix_a6r0w4b2 -> ok 662s Test: t_wide_sp_mix_a6r0w5b2 -> ok 662s Test: t_wide_sp_mix_a7r0w0b0 -> ok 662s Test: t_wide_sp_mix_a7r1w0b0 -> ok 663s Test: t_wide_sp_mix_a7r2w0b0 -> ok 663s Test: t_wide_sp_mix_a7r3w0b0 -> ok 663s Test: t_wide_sp_mix_a7r4w0b0 -> ok 663s Test: t_wide_sp_mix_a7r5w0b0 -> ok 663s Test: t_wide_sp_mix_a7r0w1b0 -> ok 664s Test: t_wide_sp_mix_a7r0w1b1 -> ok 664s Test: t_wide_sp_mix_a7r0w2b0 -> ok 664s Test: t_wide_sp_mix_a7r0w2b2 -> ok 664s Test: t_wide_sp_mix_a7r0w3b2 -> ok 665s Test: t_wide_sp_mix_a7r0w4b2 -> ok 665s Test: t_wide_sp_mix_a7r0w5b2 -> ok 665s Test: t_wide_sp_tied_a6r1w1b1 -> ok 665s Test: t_wide_sp_tied_a7r1w1b1 -> ok 665s Test: t_wide_sp_tied_a8r1w1b1 -> ok 666s Test: t_wide_sp_tied_a6r0w0b0 -> ok 666s Test: t_wide_sp_tied_a6r1w0b0 -> ok 666s Test: t_wide_sp_tied_a6r2w0b0 -> ok 666s Test: t_wide_sp_tied_a6r3w0b0 -> ok 666s Test: t_wide_sp_tied_a6r4w0b0 -> ok 667s Test: t_wide_sp_tied_a6r5w0b0 -> ok 667s Test: t_wide_sp_tied_a6r0w1b0 -> ok 667s Test: t_wide_sp_tied_a6r0w1b1 -> ok 667s Test: t_wide_sp_tied_a6r0w2b0 -> ok 667s Test: t_wide_sp_tied_a6r0w2b2 -> ok 668s Test: t_wide_sp_tied_a6r0w3b2 -> ok 668s Test: t_wide_sp_tied_a6r0w4b2 -> ok 668s Test: t_wide_sp_tied_a6r0w5b2 -> ok 668s Test: t_wide_sp_tied_a7r0w0b0 -> ok 669s Test: t_wide_sp_tied_a7r1w0b0 -> ok 669s Test: t_wide_sp_tied_a7r2w0b0 -> ok 669s Test: t_wide_sp_tied_a7r3w0b0 -> ok 669s Test: t_wide_sp_tied_a7r4w0b0 -> ok 670s Test: t_wide_sp_tied_a7r5w0b0 -> ok 670s Test: t_wide_sp_tied_a7r0w1b0 -> ok 670s Test: t_wide_sp_tied_a7r0w1b1 -> ok 670s Test: t_wide_sp_tied_a7r0w2b0 -> ok 670s Test: t_wide_sp_tied_a7r0w2b2 -> ok 671s Test: t_wide_sp_tied_a7r0w3b2 -> ok 671s Test: t_wide_sp_tied_a7r0w4b2 -> ok 671s Test: t_wide_sp_tied_a7r0w5b2 -> ok 671s Test: t_wide_read_a6r1w1b1 -> ok 671s Test: t_wide_write_a6r1w1b1 -> ok 672s Test: t_wide_read_a7r1w1b1 -> ok 672s Test: t_wide_write_a7r1w1b1 -> ok 672s Test: t_wide_read_a8r1w1b1 -> ok 672s Test: t_wide_write_a8r1w1b1 -> ok 672s Test: t_wide_read_a6r0w0b0 -> ok 673s Test: t_wide_write_a6r0w0b0 -> ok 673s Test: t_wide_read_a6r1w0b0 -> ok 673s Test: t_wide_write_a6r1w0b0 -> ok 673s Test: t_wide_read_a6r2w0b0 -> ok 673s Test: t_wide_write_a6r2w0b0 -> ok 673s Test: t_wide_read_a6r3w0b0 -> ok 674s Test: t_wide_write_a6r3w0b0 -> ok 674s Test: t_wide_read_a6r4w0b0 -> ok 674s Test: t_wide_write_a6r4w0b0 -> ok 674s Test: t_wide_read_a6r5w0b0 -> ok 675s Test: t_wide_write_a6r5w0b0 -> ok 675s Test: t_wide_read_a6r0w1b0 -> ok 675s Test: t_wide_write_a6r0w1b0 -> ok 675s Test: t_wide_read_a6r0w1b1 -> ok 675s Test: t_wide_write_a6r0w1b1 -> ok 675s Test: t_wide_read_a6r0w2b0 -> ok 676s Test: t_wide_write_a6r0w2b0 -> ok 676s Test: t_wide_read_a6r0w2b2 -> ok 676s Test: t_wide_write_a6r0w2b2 -> ok 676s Test: t_wide_read_a6r0w3b2 -> ok 676s Test: t_wide_write_a6r0w3b2 -> ok 677s Test: t_wide_read_a6r0w4b2 -> ok 677s Test: t_wide_write_a6r0w4b2 -> ok 677s Test: t_wide_read_a6r0w5b2 -> ok 678s Test: t_wide_write_a6r0w5b2 -> ok 678s Test: t_wide_read_a7r0w0b0 -> ok 678s Test: t_wide_write_a7r0w0b0 -> ok 678s Test: t_wide_read_a7r1w0b0 -> ok 678s Test: t_wide_write_a7r1w0b0 -> ok 678s Test: t_wide_read_a7r2w0b0 -> ok 679s Test: t_wide_write_a7r2w0b0 -> ok 679s Test: t_wide_read_a7r3w0b0 -> ok 679s Test: t_wide_write_a7r3w0b0 -> ok 679s Test: t_wide_read_a7r4w0b0 -> ok 679s Test: t_wide_write_a7r4w0b0 -> ok 680s Test: t_wide_read_a7r5w0b0 -> ok 680s Test: t_wide_write_a7r5w0b0 -> ok 680s Test: t_wide_read_a7r0w1b0 -> ok 680s Test: t_wide_write_a7r0w1b0 -> ok 681s Test: t_wide_read_a7r0w1b1 -> ok 681s Test: t_wide_write_a7r0w1b1 -> ok 681s Test: t_wide_read_a7r0w2b0 -> ok 681s Test: t_wide_write_a7r0w2b0 -> ok 681s Test: t_wide_read_a7r0w2b2 -> ok 682s Test: t_wide_write_a7r0w2b2 -> ok 682s Test: t_wide_read_a7r0w3b2 -> ok 682s Test: t_wide_write_a7r0w3b2 -> ok 682s Test: t_wide_read_a7r0w4b2 -> ok 682s Test: t_wide_write_a7r0w4b2 -> ok 683s Test: t_wide_read_a7r0w5b2 -> ok 683s Test: t_wide_write_a7r0w5b2 -> ok 683s Test: t_quad_port_a2d2 -> ok 683s Test: t_quad_port_a4d2 -> ok 684s Test: t_quad_port_a5d2 -> ok 684s Test: t_quad_port_a4d4 -> ok 684s Test: t_quad_port_a6d2 -> ok 684s Test: t_quad_port_a4d8 -> ok 684s Test: t_wide_quad_a4w2r1 -> ok 685s Test: t_wide_oct_a4w2r1 -> ok 685s Test: t_wide_quad_a4w2r2 -> ok 685s Test: t_wide_oct_a4w2r2 -> ok 685s Test: t_wide_quad_a4w2r3 -> ok 685s Test: t_wide_oct_a4w2r3 -> ok 685s Test: t_wide_quad_a4w2r4 -> ok 685s Test: t_wide_oct_a4w2r4 -> ok 686s Test: t_wide_quad_a4w2r5 -> ok 686s Test: t_wide_oct_a4w2r5 -> ok 686s Test: t_wide_quad_a4w2r6 -> ok 686s Test: t_wide_oct_a4w2r6 -> ok 686s Test: t_wide_quad_a4w2r7 -> ok 687s Test: t_wide_oct_a4w2r7 -> ok 687s Test: t_wide_quad_a4w2r8 -> ok 687s Test: t_wide_oct_a4w2r8 -> ok 687s Test: t_wide_quad_a4w2r9 -> ok 687s Test: t_wide_oct_a4w2r9 -> ok 687s Test: t_wide_quad_a4w4r1 -> ok 688s Test: t_wide_oct_a4w4r1 -> ok 688s Test: t_wide_quad_a4w4r4 -> ok 688s Test: t_wide_oct_a4w4r4 -> ok 688s Test: t_wide_quad_a4w4r6 -> ok 688s Test: t_wide_oct_a4w4r6 -> ok 689s Test: t_wide_quad_a4w4r9 -> ok 689s Test: t_wide_oct_a4w4r9 -> ok 689s Test: t_wide_quad_a5w2r1 -> ok 689s Test: t_wide_oct_a5w2r1 -> ok 689s Test: t_wide_quad_a5w2r4 -> ok 689s Test: t_wide_oct_a5w2r4 -> ok 690s Test: t_wide_quad_a5w2r9 -> ok 690s Test: t_wide_oct_a5w2r9 -> ok 690s Test: t_no_reset -> ok 690s Test: t_gclken -> ok 690s Test: t_ungated -> ok 691s Test: t_gclken_ce -> ok 691s Test: t_grden -> ok 691s Test: t_grden_ce -> ok 691s Test: t_exclwr -> ok 691s Test: t_excl_rst -> ok 692s Test: t_transwr -> ok 692s Test: t_trans_rst -> ok 692s Test: t_wr_byte -> ok 692s Test: t_trans_byte -> ok 692s Test: t_wr_rst_byte -> ok 693s Test: t_rst_wr_byte -> ok 693s Test: t_rdenrst_wr_byte -> ok 693s make[1]: Leaving directory '/tmp/autopkgtest.ldz5d8/build.yUl/src/tests/memlib' 693s cd tests/bram && bash run-test.sh "" 693s generating tests.. 693s PRNG seed: 351620 693s running tests.. 693s make[1]: Entering directory '/tmp/autopkgtest.ldz5d8/build.yUl/src/tests/bram' 695s Passed memory_bram test 00_01. 696s Passed memory_bram test 00_02. 696s Passed memory_bram test 00_03. 697s Passed memory_bram test 00_04. 698s Passed memory_bram test 01_00. 698s Passed memory_bram test 01_02. 699s Passed memory_bram test 01_03. 700s Passed memory_bram test 01_04. 701s Passed memory_bram test 02_00. 703s Passed memory_bram test 02_01. 704s Passed memory_bram test 02_03. 706s Passed memory_bram test 02_04. 706s Passed memory_bram test 03_00. 707s Passed memory_bram test 03_01. 708s Passed memory_bram test 03_02. 708s Passed memory_bram test 03_04. 709s Passed memory_bram test 04_00. 710s Passed memory_bram test 04_01. 710s Passed memory_bram test 04_02. 711s Passed memory_bram test 04_03. 711s make[1]: Leaving directory '/tmp/autopkgtest.ldz5d8/build.yUl/src/tests/bram' 711s cd tests/various && bash run-test.sh 711s make[1]: Entering directory '/tmp/autopkgtest.ldz5d8/build.yUl/src/tests/various' 711s Warning: Wire abc9_test027.$abc$91$o is used but has no driver. 712s Passed abc9.ys 712s Passed aiger_dff.ys 712s Passed attrib05_port_conn.ys 712s Passed attrib07_func_call.ys 712s Passed autoname.ys 712s Passed blackbox_wb.ys 712s Passed bug1496.ys 712s Passed bug1531.ys 712s Passed bug1614.ys 712s Passed bug1710.ys 712s Warning: Yosys has only limited support for tri-state logic at the moment. (< svinterface1_tb.v:50: $finish called at 420000 (10ps) 783s svinterface1_tb.v:50: $finish called at 420000 (10ps) 783s ok 784s Test: svinterface_at_top -> svinterface_at_top_tb.v:61: $finish called at 420000 (10ps) 784s svinterface_at_top_tb_wrapper.v:61: $finish called at 420000 (10ps) 784s ERROR! 784s Test: load_and_derive ->ok 784s Test: resolve_types ->ok 784s cd tests/svtypes && bash run-test.sh "" 784s make[1]: Entering directory '/tmp/autopkgtest.ldz5d8/build.yUl/src/tests/svtypes' 784s Passed enum_simple.ys 784s Passed logic_rom.ys 784s < ok 799s Test ../../techlibs/anlogic/cells_sim.v -> ok 799s Test ../../techlibs/coolrunner2/cells_sim.v -> ok 799s Test ../../techlibs/ecp5/cells_sim.v -> ok 799s Test ../../techlibs/efinix/cells_sim.v -> ok 799s Test ../../techlibs/gatemate/cells_sim.v -> ok 799s Test ../../techlibs/gowin/cells_sim.v -> ok 799s Test ../../techlibs/greenpak4/cells_sim.v -> ok 799s Test ../../techlibs/ice40/cells_sim.v -DICE40_HX ->../../techlibs/ice40/cells_sim.v:2231: warning: Choosing typ expression. 799s ../../techlibs/ice40/cells_sim.v:2231: warning: Choosing typ expression. 799s ../../techlibs/ice40/cells_sim.v:2233: warning: Choosing typ expression. 799s ../../techlibs/ice40/cells_sim.v:2233: warning: Choosing typ expression. 799s ../../techlibs/ice40/cells_sim.v:2235: warning: Choosing typ expression. 799s ../../techlibs/ice40/cells_sim.v:2235: warning: Choosing typ expression. 799s ../../techlibs/ice40/cells_sim.v:2237: warning: Choosing typ expression. 799s ../../techlibs/ice40/cells_sim.v:2237: warning: Choosing typ expression. 799s ../../techlibs/ice40/cells_sim.v:2239: warning: Choosing typ expression. 799s ../../techlibs/ice40/cells_sim.v:2239: warning: Choosing typ expression. 799s ok 799s Test ../../techlibs/ice40/cells_sim.v -DICE40_LP ->../../techlibs/ice40/cells_sim.v:2295: warning: Choosing typ expression. 799s ../../techlibs/ice40/cells_sim.v:2295: warning: Choosing typ expression. 799s ../../techlibs/ice40/cells_sim.v:2297: warning: Choosing typ expression. 799s ../../techlibs/ice40/cells_sim.v:2297: warning: Choosing typ expression. 799s ../../techlibs/ice40/cells_sim.v:2299: warning: Choosing typ expression. 799s ../../techlibs/ice40/cells_sim.v:2299: warning: Choosing typ expression. 799s ../../techlibs/ice40/cells_sim.v:2301: warning: Choosing typ expression. 799s ../../techlibs/ice40/cells_sim.v:2301: warning: Choosing typ expression. 799s ../../techlibs/ice40/cells_sim.v:2303: warning: Choosing typ expression. 799s ../../techlibs/ice40/cells_sim.v:2303: warning: Choosing typ expression. 799s ok 799s Test ../../techlibs/ice40/cells_sim.v -DICE40_U ->../../techlibs/ice40/cells_sim.v:2359: warning: Choosing typ expression. 799s ../../techlibs/ice40/cells_sim.v:2359: warning: Choosing typ expression. 799s ../../techlibs/ice40/cells_sim.v:2361: warning: Choosing typ expression. 799s ../../techlibs/ice40/cells_sim.v:2361: warning: Choosing typ expression. 799s ../../techlibs/ice40/cells_sim.v:2363: warning: Choosing typ expression. 799s ../../techlibs/ice40/cells_sim.v:2363: warning: Choosing typ expression. 799s ../../techlibs/ice40/cells_sim.v:2365: warning: Choosing typ expression. 799s ../../techlibs/ice40/cells_sim.v:2365: warning: Choosing typ expression. 799s ../../techlibs/ice40/cells_sim.v:2367: warning: Choosing typ expression. 799s ../../techlibs/ice40/cells_sim.v:2367: warning: Choosing typ expression. 799s ok 799s Test ../../techlibs/intel/cyclone10lp/cells_sim.v -> ok 799s Test ../../techlibs/intel/max10/cells_sim.v -> ok 799s Test ../../techlibs/intel/cycloneive/cells_sim.v -> ok 799s Test ../../techlibs/intel/cycloneiv/cells_sim.v -> ok 799s Test ../../techlibs/intel_alm/cyclonev/cells_sim.v -> ok 799s Test ../../techlibs/nexus/cells_sim.v -> ok 799s Test ../../techlibs/quicklogic/cells_sim.v -> ok 799s Test ../../techlibs/sf2/cells_sim.v -> ok 799s Test ../../techlibs/xilinx/cells_sim.v -> ok 799s Test ../../techlibs/common/simcells.v -> ok 799s Test ../../techlibs/common/simlib.v -> ok 799s cd tests/arch/ice40 && bash run-test.sh "" 799s make[1]: Entering directory '/tmp/autopkgtest.ldz5d8/build.yUl/src/tests/arch/ice40' 800s Passed add_sub.ys 803s Passed adffs.ys 804s Warning: Resizing cell port SSCounter6o.l0.I3 from 32 bits to 1 bits. 804s Warning: Resizing cell port SSCounter6o.c0.CI from 32 bits to 1 bits. 804s Warning: Resizing cell port SSCounter6o.lien.I0 from 32 bits to 1 bits. 804s Warning: Resizing cell port SSCounter6o.lien.I1 from 32 bits to 1 bits. 804s Passed bug1597.ys 805s Passed bug1598.ys 806s Passed bug1626.ys 822s Passed bug1644.ys 823s Passed bug2061.ys 824s Passed counter.ys 826s Passed dffs.ys 835s Passed dpram.ys 836s Passed fsm.ys 836s Passed ice40_dsp.ys 837s Passed ice40_opt.ys 837s Passed ice40_wrapcarry.ys 839s Passed latches.ys 840s Passed logic.ys 846s Passed macc.ys 900s Passed memories.ys 901s Passed mul.ys 905s Passed mux.ys 905s Warning: wire '\data' is assigned in a block at rom.v:10.5-10.15. 905s Warning: wire '\data' is assigned in a block at rom.v:11.5-11.15. 905s Warning: wire '\data' is assigned in a block at rom.v:12.5-12.15. 905s Warning: wire '\data' is assigned in a block at rom.v:13.6-13.16. 905s Warning: wire '\data' is assigned in a block at rom.v:14.6-14.16. 905s Warning: wire '\data' is assigned in a block at rom.v:15.6-15.16. 905s Warning: wire '\data' is assigned in a block at rom.v:16.11-16.21. 906s Passed rom.ys 907s Passed shifter.ys 907s Warning: wire '\read_data' is assigned in a block at spram.v:19.3-19.25. 909s Passed spram.ys 910s Passed tribuf.ys 910s make[1]: Leaving directory '/tmp/autopkgtest.ldz5d8/build.yUl/src/tests/arch/ice40' 910s cd tests/arch/xilinx && bash run-test.sh "" 910s make[1]: Entering directory '/tmp/autopkgtest.ldz5d8/build.yUl/src/tests/arch/xilinx' 925s Warning: Whitebox '$paramod\FDRE\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. 925s Warning: Whitebox 'FDSE' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. 925s Warning: Whitebox '$paramod\FDRE_1\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. 925s Warning: Whitebox '$paramod\FDSE_1\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. 951s Passed abc9_dff.ys 955s Warning: Shift register inference not yet supported for family xc3s. 958s Passed add_sub.ys 976s Passed adffs.ys 981s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DIADI from 64 bits to 16 bits. 981s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOADO from 64 bits to 16 bits. 981s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOBDO from 64 bits to 16 bits. 981s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOPADOP from 8 bits to 2 bits. 981s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOPBDOP from 8 bits to 2 bits. 981s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.WEA from 4 bits to 2 bits. 990s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.WEBWE from 1 bits to 4 bits. 994s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DIADI from 64 bits to 16 bits. 994s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOADO from 64 bits to 16 bits. 994s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOBDO from 64 bits to 16 bits. 994s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOPADOP from 8 bits to 2 bits. 994s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOPBDOP from 8 bits to 2 bits. 994s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.WEA from 4 bits to 2 bits. 994s Warning: Selection "asym_ram_sdp_read_wider" did not match any module. 1008s Passed asym_ram_sdp.ys 1012s Warning: Resizing cell port block_ram.memory.0.0.DIADI from 64 bits to 16 bits. 1012s Warning: Resizing cell port block_ram.memory.0.0.DOADO from 64 bits to 16 bits. 1012s Warning: Resizing cell port block_ram.memory.0.0.DOBDO from 64 bits to 16 bits. 1012s Warning: Resizing cell port block_ram.memory.0.0.DOPADOP from 8 bits to 2 bits. 1012s Warning: Resizing cell port block_ram.memory.0.0.DOPBDOP from 8 bits to 2 bits. 1012s Warning: Resizing cell port block_ram.memory.0.0.WEA from 4 bits to 2 bits. 1036s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DIADI from 64 bits to 16 bits. 1036s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOADO from 64 bits to 16 bits. 1036s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOBDO from 64 bits to 16 bits. 1036s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOPADOP from 8 bits to 2 bits. 1036s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOPBDOP from 8 bits to 2 bits. 1036s Warning: Resizing cell port distributed_ram_manual.memory.0.0.WEA from 4 bits to 2 bits. 1036s Passed attributes_test.ys 1041s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIADI from 64 bits to 16 bits. 1041s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOADO from 64 bits to 16 bits. 1041s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOBDO from 64 bits to 16 bits. 1041s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPADOP from 8 bits to 2 bits. 1041s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPBDOP from 8 bits to 2 bits. 1041s Warning: Resizing cell port sync_ram_sdp.memory.0.0.WEA from 4 bits to 2 bits. 1045s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIPADIP from 8 bits to 2 bits. 1063s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIADI from 64 bits to 32 bits. 1063s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIPADIP from 8 bits to 4 bits. 1063s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOADO from 64 bits to 32 bits. 1063s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOBDO from 64 bits to 32 bits. 1063s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPADOP from 8 bits to 4 bits. 1063s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPBDOP from 8 bits to 4 bits. 1092s Passed blockram.ys 1097s Passed bug1460.ys 1101s Passed bug1462.ys 1105s Passed bug1480.ys 1110s Passed bug1598.ys 1111s Warning: Wire top.\t is used but has no driver. 1111s Warning: Wire top.\in is used but has no driver. 1114s Passed bug1605.ys 1115s Passed bug3670.ys 1120s Passed counter.ys 1141s Passed dffs.ys 1157s Passed dsp_abc9.ys 1169s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef. 1169s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef. 1222s Passed dsp_cascade.ys 1227s Passed dsp_fastfir.ys 1234s Passed dsp_simd.ys 1239s Warning: Shift register inference not yet supported for family xc3se. 1243s Passed fsm.ys 1257s Passed latches.ys 1261s Passed logic.ys 1306s Warning: Shift register inference not yet supported for family xc3s. 1310s Passed lutram.ys 1322s Passed macc.ys 1329s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef. 1329s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef. 1331s Passed mul.ys 1331s Warning: Replacing memory \M with list of registers. See mul_unsigned.v:25 1342s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef. 1342s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef. 1346s Passed mul_unsigned.ys 1365s Passed mux.ys 1365s Warning: Shift register inference not yet supported for family xc3se. 1378s Passed mux_lut4.ys 1387s Passed nosrl.ys 1388s Passed opt_lut_ins.ys 1400s Passed pmgen_xilinx_srl.ys 1405s Warning: Resizing cell port priority_memory.mem.0.0.ADDRARDADDR from 16 bits to 15 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.0.ADDRBWRADDR from 16 bits to 15 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.0.DINADIN from 64 bits to 32 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.0.DINBDIN from 64 bits to 32 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.0.DINPADINP from 8 bits to 4 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.0.DINPBDINP from 8 bits to 4 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.0.DOUTADOUT from 64 bits to 32 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.0.DOUTBDOUT from 64 bits to 32 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.0.DOUTPADOUTP from 8 bits to 4 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.0.DOUTPBDOUTP from 8 bits to 4 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.0.WEBWE from 4 bits to 8 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.1.ADDRARDADDR from 16 bits to 15 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.1.ADDRBWRADDR from 16 bits to 15 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.1.DINADIN from 64 bits to 32 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.1.DINBDIN from 64 bits to 32 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.1.DINPADINP from 8 bits to 4 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.1.DINPBDINP from 8 bits to 4 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.1.DOUTADOUT from 64 bits to 32 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.1.DOUTBDOUT from 64 bits to 32 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.1.DOUTPADOUTP from 8 bits to 4 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.1.DOUTPBDOUTP from 8 bits to 4 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.1.WEBWE from 4 bits to 8 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.2.ADDRARDADDR from 16 bits to 15 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.2.ADDRBWRADDR from 16 bits to 15 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.2.DINADIN from 64 bits to 32 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.2.DINBDIN from 64 bits to 32 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.2.DINPADINP from 8 bits to 4 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.2.DINPBDINP from 8 bits to 4 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.2.DOUTADOUT from 64 bits to 32 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.2.DOUTBDOUT from 64 bits to 32 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.2.DOUTPADOUTP from 8 bits to 4 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.2.DOUTPBDOUTP from 8 bits to 4 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.2.WEBWE from 4 bits to 8 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.3.ADDRARDADDR from 16 bits to 15 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.3.ADDRBWRADDR from 16 bits to 15 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.3.DINADIN from 64 bits to 32 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.3.DINBDIN from 64 bits to 32 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.3.DINPADINP from 8 bits to 4 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.3.DINPBDINP from 8 bits to 4 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.3.DOUTADOUT from 64 bits to 32 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.3.DOUTBDOUT from 64 bits to 32 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.3.DOUTPADOUTP from 8 bits to 4 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.3.DOUTPBDOUTP from 8 bits to 4 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.3.WEBWE from 4 bits to 8 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.4.ADDRARDADDR from 16 bits to 15 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.4.ADDRBWRADDR from 16 bits to 15 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.4.DINADIN from 64 bits to 32 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.4.DINBDIN from 64 bits to 32 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.4.DINPADINP from 8 bits to 4 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.4.DINPBDINP from 8 bits to 4 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.4.DOUTADOUT from 64 bits to 32 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.4.DOUTBDOUT from 64 bits to 32 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.4.DOUTPADOUTP from 8 bits to 4 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.4.DOUTPBDOUTP from 8 bits to 4 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.4.WEBWE from 4 bits to 8 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.5.ADDRARDADDR from 16 bits to 15 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.5.ADDRBWRADDR from 16 bits to 15 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.5.DINADIN from 64 bits to 32 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.5.DINBDIN from 64 bits to 32 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.5.DINPADINP from 8 bits to 4 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.5.DINPBDINP from 8 bits to 4 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.5.DOUTADOUT from 64 bits to 32 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.5.DOUTBDOUT from 64 bits to 32 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.5.DOUTPADOUTP from 8 bits to 4 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.5.DOUTPBDOUTP from 8 bits to 4 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.5.WEBWE from 4 bits to 8 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.6.ADDRARDADDR from 16 bits to 15 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.6.ADDRBWRADDR from 16 bits to 15 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.6.DINADIN from 64 bits to 32 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.6.DINBDIN from 64 bits to 32 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.6.DINPADINP from 8 bits to 4 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.6.DINPBDINP from 8 bits to 4 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.6.DOUTADOUT from 64 bits to 32 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.6.DOUTBDOUT from 64 bits to 32 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.6.DOUTPADOUTP from 8 bits to 4 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.6.DOUTPBDOUTP from 8 bits to 4 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.6.WEBWE from 4 bits to 8 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.7.ADDRARDADDR from 16 bits to 15 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.7.ADDRBWRADDR from 16 bits to 15 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.7.DINADIN from 64 bits to 32 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.7.DINBDIN from 64 bits to 32 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.7.DINPADINP from 8 bits to 4 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.7.DINPBDINP from 8 bits to 4 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.7.DOUTADOUT from 64 bits to 32 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.7.DOUTBDOUT from 64 bits to 32 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.7.DOUTPADOUTP from 8 bits to 4 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.7.DOUTPBDOUTP from 8 bits to 4 bits. 1405s Warning: Resizing cell port priority_memory.mem.0.7.WEBWE from 4 bits to 8 bits. 1410s Warning: Resizing cell port priority_memory.mem.0.0.BWE_A from 8 bits to 9 bits. 1410s Warning: Resizing cell port priority_memory.mem.0.0.BWE_B from 8 bits to 9 bits. 1423s Warning: Resizing cell port sp_write_first.mem.0.0.BWE_A from 8 bits to 9 bits. 1427s Warning: Resizing cell port sp_read_first.mem.0.0.BWE_B from 8 bits to 9 bits. 1427s Passed priority_memory.ys 1432s Passed shifter.ys 1436s Passed tribuf.ys 1440s Passed xilinx_dffopt.ys 1440s Passed xilinx_dsp.ys 1441s Passed xilinx_srl.ys 1449s Passed macc.sh 1457s Passed tribuf.sh 1457s make[1]: Leaving directory '/tmp/autopkgtest.ldz5d8/build.yUl/src/tests/arch/xilinx' 1457s cd tests/arch/ecp5 && bash run-test.sh "" 1457s make[1]: Entering directory '/tmp/autopkgtest.ldz5d8/build.yUl/src/tests/arch/ecp5' 1458s Passed add_sub.ys 1461s Passed adffs.ys 1462s Passed bug1459.ys 1462s Passed bug1598.ys 1463s Passed bug1630.ys 1463s Warning: Literal has a width of 16 bit, but value requires 184 bit. (<>>/,/<<>>/ {print $0}' 1951s + iverilog -o iverilog-initial_display initial_display.v 1951s + ./iverilog-initial_display 1951s + diff yosys-initial_display.log iverilog-initial_display.log 1951s + test_always_display clk -DEVENT_CLK 1951s + local subtest=clk 1951s + shift 1951s + ../../yosys -p 'read_verilog -DEVENT_CLK always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk-1.v 1951s 1951s /----------------------------------------------------------------------------\ 1951s | | 1951s | yosys -- Yosys Open SYnthesis Suite | 1951s | | 1951s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1951s | | 1951s | Permission to use, copy, modify, and/or distribute this software for any | 1951s | purpose with or without fee is hereby granted, provided that the above | 1951s | copyright notice and this permission notice appear in all copies. | 1951s | | 1951s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1951s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1951s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1951s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1951s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1951s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1951s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1951s | | 1951s \----------------------------------------------------------------------------/ 1951s 1951s Yosys 0.33 (git sha1 2584903a060) 1951s 1951s 1951s -- Running command `read_verilog -DEVENT_CLK always_display.v; proc; opt_expr -mux_bool; clean' -- 1951s 1951s 1. Executing Verilog-2005 frontend: always_display.v 1951s Parsing Verilog input from `always_display.v' to AST representation. 1951s Generating RTLIL representation for module `\m'. 1951s Successfully finished Verilog frontend. 1951s 1951s 2. Executing PROC pass (convert processes to netlists). 1951s 1951s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Cleaned up 0 empty switches. 1951s 1951s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1951s Removed a total of 0 dead cases. 1951s 1951s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1951s Removed 1 redundant assignment. 1951s Promoted 1 assignment to connection. 1951s 1951s 2.4. Executing PROC_INIT pass (extract init attributes). 1951s 1951s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1951s 1951s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1951s Converted 0 switches. 1951s 1951s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1951s Creating decoders for process `\m.$proc$always_display.v:4$1'. 1951s 1951s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1951s 1951s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1951s 1951s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1951s 1951s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Removing empty process `m.$proc$always_display.v:4$1'. 1951s Cleaned up 0 empty switches. 1951s 1951s 2.12. Executing OPT_EXPR pass (perform const folding). 1951s Optimizing module m. 1951s 1951s 3. Executing OPT_EXPR pass (perform const folding). 1951s Optimizing module m. 1951s Removed 0 unused cells and 1 unused wires. 1951s 1951s -- Writing to `yosys-always_display-clk-1.v' using backend `verilog' -- 1951s 1951s 4. Executing Verilog backend. 1951s 1951s 4.1. Executing BMUXMAP pass. 1951s 1951s 4.2. Executing DEMUXMAP pass. 1951s Dumping module `\m'. 1951s 1951s End of script. Logfile hash: 0de35d2746, CPU: user 0.00s system 0.00s, MEM: 9.66 MB peak 1951s Yosys 0.33 (git sha1 2584903a060) 1951s Time spent: 37% 2x opt_expr (0 sec), 24% 1x clean (0 sec), ... 1951s + ../../yosys -p 'read_verilog yosys-always_display-clk-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk-2.v 1951s 1951s /----------------------------------------------------------------------------\ 1951s | | 1951s | yosys -- Yosys Open SYnthesis Suite | 1951s | | 1951s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1951s | | 1951s | Permission to use, copy, modify, and/or distribute this software for any | 1951s | purpose with or without fee is hereby granted, provided that the above | 1951s | copyright notice and this permission notice appear in all copies. | 1951s | | 1951s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1951s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1951s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1951s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1951s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1951s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1951s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1951s | | 1951s \----------------------------------------------------------------------------/ 1951s 1951s Yosys 0.33 (git sha1 2584903a060) 1951s 1951s 1951s -- Running command `read_verilog yosys-always_display-clk-1.v; proc; opt_expr -mux_bool; clean' -- 1951s 1951s 1. Executing Verilog-2005 frontend: yosys-always_display-clk-1.v 1951s Parsing Verilog input from `yosys-always_display-clk-1.v' to AST representation. 1951s Generating RTLIL representation for module `\m'. 1951s Successfully finished Verilog frontend. 1951s 1951s 2. Executing PROC pass (convert processes to netlists). 1951s 1951s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk-1.v:18$1'. 1951s Cleaned up 1 empty switch. 1951s 1951s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1951s Removed a total of 0 dead cases. 1951s 1951s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1951s Removed 1 redundant assignment. 1951s Promoted 1 assignment to connection. 1951s 1951s 2.4. Executing PROC_INIT pass (extract init attributes). 1951s 1951s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1951s 1951s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1951s Converted 0 switches. 1951s 1951s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1951s Creating decoders for process `\m.$proc$yosys-always_display-clk-1.v:18$1'. 1951s 1951s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1951s 1951s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1951s 1951s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1951s 1951s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s + diff yosys-always_display-clk-1.v yosys-always_display-clk-2.v 1951s + test_always_display clk_rst -DEVENT_CLK_RST 1951s + local subtest=clk_rst 1951s + shift 1951s + ../../yosys -p 'read_verilog -DEVENT_CLK_RST always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst-1.v 1951s Removing empty process `m.$proc$yosys-always_display-clk-1.v:18$1'. 1951s Cleaned up 0 empty switches. 1951s 1951s 2.12. Executing OPT_EXPR pass (perform const folding). 1951s Optimizing module m. 1951s 1951s 3. Executing OPT_EXPR pass (perform const folding). 1951s Optimizing module m. 1951s Removed 0 unused cells and 1 unused wires. 1951s 1951s -- Writing to `yosys-always_display-clk-2.v' using backend `verilog' -- 1951s 1951s 4. Executing Verilog backend. 1951s 1951s 4.1. Executing BMUXMAP pass. 1951s 1951s 4.2. Executing DEMUXMAP pass. 1951s Dumping module `\m'. 1951s 1951s End of script. Logfile hash: e35e8bb689, CPU: user 0.01s system 0.00s, MEM: 9.66 MB peak 1951s Yosys 0.33 (git sha1 2584903a060) 1951s Time spent: 36% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ... 1951s 1951s /----------------------------------------------------------------------------\ 1951s | | 1951s | yosys -- Yosys Open SYnthesis Suite | 1951s | | 1951s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1951s | | 1951s | Permission to use, copy, modify, and/or distribute this software for any | 1951s | purpose with or without fee is hereby granted, provided that the above | 1951s | copyright notice and this permission notice appear in all copies. | 1951s | | 1951s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1951s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1951s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1951s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1951s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1951s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1951s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1951s | | 1951s \----------------------------------------------------------------------------/ 1951s 1951s Yosys 0.33 (git sha1 2584903a060) 1951s 1951s 1951s -- Running command `read_verilog -DEVENT_CLK_RST always_display.v; proc; opt_expr -mux_bool; clean' -- 1951s 1951s 1. Executing Verilog-2005 frontend: always_display.v 1951s Parsing Verilog input from `always_display.v' to AST representation. 1951s Generating RTLIL representation for module `\m'. 1951s Successfully finished Verilog frontend. 1951s 1951s 2. Executing PROC pass (convert processes to netlists). 1951s 1951s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Cleaned up 0 empty switches. 1951s 1951s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1951s Removed a total of 0 dead cases. 1951s 1951s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1951s Removed 1 redundant assignment. 1951s Promoted 1 assignment to connection. 1951s 1951s 2.4. Executing PROC_INIT pass (extract init attributes). 1951s 1951s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1951s 1951s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1951s Converted 0 switches. 1951s 1951s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1951s Creating decoders for process `\m.$proc$always_display.v:7$1'. 1951s 1951s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1951s 1951s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1951s 1951s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1951s 1951s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Removing empty process `m.$proc$always_display.v:7$1'. 1951s Cleaned up 0 empty switches. 1951s 1951s 2.12. Executing OPT_EXPR pass (perform const folding). 1951s Optimizing module m. 1951s 1951s 3. Executing OPT_EXPR pass (perform const folding). 1951s Optimizing module m. 1951s Removed 0 unused cells and 1 unused wires. 1951s 1951s -- Writing to `yosys-always_display-clk_rst-1.v' using backend `verilog' -- 1951s 1951s 4. Executing Verilog backend. 1951s 1951s 4.1. Executing BMUXMAP pass. 1951s 1951s 4.2. Executing DEMUXMAP pass. 1951s Dumping module `\m'. 1951s 1951s End of script. Logfile hash: c95608ddf0, CPU: user 0.01s system 0.00s, MEM: 9.66 MB peak 1951s Yosys 0.33 (git sha1 2584903a060) 1951s Time spent: 37% 2x opt_expr (0 sec), 24% 1x clean (0 sec), ... 1951s + ../../yosys -p 'read_verilog yosys-always_display-clk_rst-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst-2.v 1951s 1951s /----------------------------------------------------------------------------\ 1951s | | 1951s | yosys -- Yosys Open SYnthesis Suite | 1951s | | 1951s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1951s | | 1951s | Permission to use, copy, modify, and/or distribute this software for any | 1951s | purpose with or without fee is hereby granted, provided that the above | 1951s | copyright notice and this permission notice appear in all copies. | 1951s | | 1951s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1951s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1951s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1951s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1951s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1951s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1951s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1951s | | 1951s \----------------------------------------------------------------------------/ 1951s 1951s Yosys 0.33 (git sha1 2584903a060) 1951s 1951s 1951s -- Running command `read_verilog yosys-always_display-clk_rst-1.v; proc; opt_expr -mux_bool; clean' -- 1951s 1951s 1. Executing Verilog-2005 frontend: yosys-always_display-clk_rst-1.v 1951s Parsing Verilog input from `yosys-always_display-clk_rst-1.v' to AST representation. 1951s Generating RTLIL representation for module `\m'. 1951s Successfully finished Verilog frontend. 1951s 1951s 2. Executing PROC pass (convert processes to netlists). 1951s 1951s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_rst-1.v:18$1'. 1951s Cleaned up 1 empty switch. 1951s 1951s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1951s Removed a total of 0 dead cases. 1951s 1951s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1951s Removed 1 redundant assignment. 1951s Promoted 1 assignment to connection. 1951s 1951s 2.4. Executing PROC_INIT pass (extract init attributes). 1951s 1951s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1951s 1951s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1951s Converted 0 switches. 1951s 1951s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1951s Creating decoders for process `\m.$proc$yosys-always_display-clk_rst-1.v:18$1'. 1951s 1951s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1951s 1951s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1951s 1951s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1951s 1951s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Removing empty process `m.$proc$yosys-always_display-clk_rst-1.v:18$1'. 1951s Cleaned up 0 empty switches. 1951s 1951s 2.12. Executing OPT_EXPR pass (perform const folding). 1951s Optimizing module m. 1951s 1951s 3. Executing OPT_EXPR pass (perform const folding). 1951s Optimizing module m. 1951s + diff yosys-always_display-clk_rst-1.v yosys-always_display-clk_rst-2.v 1951s + test_always_display star -DEVENT_STAR 1951s + local subtest=star 1951s + shift 1951s + ../../yosys -p 'read_verilog -DEVENT_STAR always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star-1.v 1951s Removed 0 unused cells and 1 unused wires. 1951s 1951s -- Writing to `yosys-always_display-clk_rst-2.v' using backend `verilog' -- 1951s 1951s 4. Executing Verilog backend. 1951s 1951s 4.1. Executing BMUXMAP pass. 1951s 1951s 4.2. Executing DEMUXMAP pass. 1951s Dumping module `\m'. 1951s 1951s End of script. Logfile hash: faf50513c3, CPU: user 0.00s system 0.01s, MEM: 9.66 MB peak 1951s Yosys 0.33 (git sha1 2584903a060) 1951s Time spent: 35% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ... 1951s 1951s /----------------------------------------------------------------------------\ 1951s | | 1951s | yosys -- Yosys Open SYnthesis Suite | 1951s | | 1951s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1951s | | 1951s | Permission to use, copy, modify, and/or distribute this software for any | 1951s | purpose with or without fee is hereby granted, provided that the above | 1951s | copyright notice and this permission notice appear in all copies. | 1951s | | 1951s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1951s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1951s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1951s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1951s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1951s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1951s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1951s | | 1951s \----------------------------------------------------------------------------/ 1951s 1951s Yosys 0.33 (git sha1 2584903a060) 1951s 1951s 1951s -- Running command `read_verilog -DEVENT_STAR always_display.v; proc; opt_expr -mux_bool; clean' -- 1951s 1951s 1. Executing Verilog-2005 frontend: always_display.v 1951s + ../../yosys -p 'read_verilog yosys-always_display-star-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star-2.v 1951s Parsing Verilog input from `always_display.v' to AST representation. 1951s Generating RTLIL representation for module `\m'. 1951s Successfully finished Verilog frontend. 1951s 1951s 2. Executing PROC pass (convert processes to netlists). 1951s 1951s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Cleaned up 0 empty switches. 1951s 1951s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1951s Removed a total of 0 dead cases. 1951s 1951s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1951s Removed 1 redundant assignment. 1951s Promoted 1 assignment to connection. 1951s 1951s 2.4. Executing PROC_INIT pass (extract init attributes). 1951s 1951s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1951s 1951s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1951s Converted 0 switches. 1951s 1951s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1951s Creating decoders for process `\m.$proc$always_display.v:10$1'. 1951s 1951s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1951s 1951s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1951s 1951s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1951s 1951s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Removing empty process `m.$proc$always_display.v:10$1'. 1951s Cleaned up 0 empty switches. 1951s 1951s 2.12. Executing OPT_EXPR pass (perform const folding). 1951s Optimizing module m. 1951s 1951s 3. Executing OPT_EXPR pass (perform const folding). 1951s Optimizing module m. 1951s Removed 0 unused cells and 1 unused wires. 1951s 1951s -- Writing to `yosys-always_display-star-1.v' using backend `verilog' -- 1951s 1951s 4. Executing Verilog backend. 1951s 1951s 4.1. Executing BMUXMAP pass. 1951s 1951s 4.2. Executing DEMUXMAP pass. 1951s Dumping module `\m'. 1951s 1951s End of script. Logfile hash: 7b2c5274a5, CPU: user 0.01s system 0.00s, MEM: 9.54 MB peak 1951s Yosys 0.33 (git sha1 2584903a060) 1951s Time spent: 37% 2x opt_expr (0 sec), 23% 1x clean (0 sec), ... 1951s 1951s /----------------------------------------------------------------------------\ 1951s | | 1951s | yosys -- Yosys Open SYnthesis Suite | 1951s | | 1951s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1951s | | 1951s | Permission to use, copy, modify, and/or distribute this software for any | 1951s | purpose with or without fee is hereby granted, provided that the above | 1951s | copyright notice and this permission notice appear in all copies. | 1951s | | 1951s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1951s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1951s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1951s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1951s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1951s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1951s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1951s | | 1951s \----------------------------------------------------------------------------/ 1951s 1951s Yosys 0.33 (git sha1 2584903a060) 1951s 1951s 1951s -- Running command `read_verilog yosys-always_display-star-1.v; proc; opt_expr -mux_bool; clean' -- 1951s 1951s 1. Executing Verilog-2005 frontend: yosys-always_display-star-1.v 1951s Parsing Verilog input from `yosys-always_display-star-1.v' to AST representation. 1951s Generating RTLIL representation for module `\m'. 1951s Successfully finished Verilog frontend. 1951s 1951s 2. Executing PROC pass (convert processes to netlists). 1951s 1951s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-star-1.v:18$1'. 1951s Cleaned up 1 empty switch. 1951s 1951s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1951s Removed a total of 0 dead cases. 1951s 1951s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1951s Removed 1 redundant assignment. 1951s Promoted 1 assignment to connection. 1951s 1951s 2.4. Executing PROC_INIT pass (extract init attributes). 1951s 1951s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1951s 1951s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1951s + diff yosys-always_display-star-1.v yosys-always_display-star-2.v 1951s + test_always_display clk_en -DEVENT_CLK -DCOND_EN 1951s + local subtest=clk_en 1951s + shift 1951s + ../../yosys -p 'read_verilog -DEVENT_CLK -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_en-1.v 1951s + ../../yosys -p 'read_verilog yosys-always_display-clk_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_en-2.v 1951s Converted 0 switches. 1951s 1951s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1951s Creating decoders for process `\m.$proc$yosys-always_display-star-1.v:18$1'. 1951s 1951s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1951s 1951s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1951s 1951s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1951s 1951s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Removing empty process `m.$proc$yosys-always_display-star-1.v:18$1'. 1951s Cleaned up 0 empty switches. 1951s 1951s 2.12. Executing OPT_EXPR pass (perform const folding). 1951s Optimizing module m. 1951s 1951s 3. Executing OPT_EXPR pass (perform const folding). 1951s Optimizing module m. 1951s Removed 0 unused cells and 1 unused wires. 1951s 1951s -- Writing to `yosys-always_display-star-2.v' using backend `verilog' -- 1951s 1951s 4. Executing Verilog backend. 1951s 1951s 4.1. Executing BMUXMAP pass. 1951s 1951s 4.2. Executing DEMUXMAP pass. 1951s Dumping module `\m'. 1951s 1951s End of script. Logfile hash: 8979c5de0b, CPU: user 0.01s system 0.00s, MEM: 9.54 MB peak 1951s Yosys 0.33 (git sha1 2584903a060) 1951s Time spent: 35% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ... 1951s 1951s /----------------------------------------------------------------------------\ 1951s | | 1951s | yosys -- Yosys Open SYnthesis Suite | 1951s | | 1951s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1951s | | 1951s | Permission to use, copy, modify, and/or distribute this software for any | 1951s | purpose with or without fee is hereby granted, provided that the above | 1951s | copyright notice and this permission notice appear in all copies. | 1951s | | 1951s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1951s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1951s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1951s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1951s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1951s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1951s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1951s | | 1951s \----------------------------------------------------------------------------/ 1951s 1951s Yosys 0.33 (git sha1 2584903a060) 1951s 1951s 1951s -- Running command `read_verilog -DEVENT_CLK -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -- 1951s 1951s 1. Executing Verilog-2005 frontend: always_display.v 1951s Parsing Verilog input from `always_display.v' to AST representation. 1951s Generating RTLIL representation for module `\m'. 1951s Successfully finished Verilog frontend. 1951s 1951s 2. Executing PROC pass (convert processes to netlists). 1951s 1951s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Cleaned up 0 empty switches. 1951s 1951s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1951s Removed a total of 0 dead cases. 1951s 1951s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1951s Removed 0 redundant assignments. 1951s Promoted 0 assignments to connections. 1951s 1951s 2.4. Executing PROC_INIT pass (extract init attributes). 1951s 1951s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1951s 1951s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1951s Converted 0 switches. 1951s 1951s 1951s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1951s Creating decoders for process `\m.$proc$always_display.v:4$1'. 1951s 1/1: $display$always_display.v:15$2_EN 1951s 1951s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1951s 1951s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1951s 1951s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1951s 1951s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:4$1'. 1951s Removing empty process `m.$proc$always_display.v:4$1'. 1951s Cleaned up 1 empty switch. 1951s 1951s 2.12. Executing OPT_EXPR pass (perform const folding). 1951s Optimizing module m. 1951s 1951s 3. Executing OPT_EXPR pass (perform const folding). 1951s Optimizing module m. 1951s 1951s Removed 0 unused cells and 3 unused wires. 1951s 1951s -- Writing to `yosys-always_display-clk_en-1.v' using backend `verilog' -- 1951s 1951s 4. Executing Verilog backend. 1951s 1951s 4.1. Executing BMUXMAP pass. 1951s 1951s 4.2. Executing DEMUXMAP pass. 1951s Dumping module `\m'. 1951s 1951s End of script. Logfile hash: 4f8a3b339c, CPU: user 0.01s system 0.00s, MEM: 9.66 MB peak 1951s Yosys 0.33 (git sha1 2584903a060) 1951s Time spent: 38% 2x opt_expr (0 sec), 21% 1x clean (0 sec), ... 1951s 1951s /----------------------------------------------------------------------------\ 1951s | | 1951s | yosys -- Yosys Open SYnthesis Suite | 1951s | | 1951s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1951s | | 1951s | Permission to use, copy, modify, and/or distribute this software for any | 1951s | purpose with or without fee is hereby granted, provided that the above | 1951s | copyright notice and this permission notice appear in all copies. | 1951s | | 1951s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1951s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1951s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1951s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1951s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1951s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1951s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1951s | | 1951s \----------------------------------------------------------------------------/ 1951s 1951s Yosys 0.33 (git sha1 2584903a060) 1951s 1951s 1951s -- Running command `read_verilog yosys-always_display-clk_en-1.v; proc; opt_expr -mux_bool; clean' -- 1951s 1951s 1. Executing Verilog-2005 frontend: yosys-always_display-clk_en-1.v 1951s Parsing Verilog input from `yosys-always_display-clk_en-1.v' to AST representation. 1951s Generating RTLIL representation for module `\m'. 1951s Successfully finished Verilog frontend. 1951s 1951s 2. Executing PROC pass (convert processes to netlists). 1951s 1951s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Cleaned up 0 empty switches. 1951s 1951s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1951s Removed a total of 0 dead cases. 1951s 1951s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1951s Removed 0 redundant assignments. 1951s Promoted 0 assignments to connections. 1951s 1951s 2.4. Executing PROC_INIT pass (extract init attributes). 1951s 1951s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1951s 1951s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1951s + diff yosys-always_display-clk_en-1.v yosys-always_display-clk_en-2.v 1951s + test_always_display clk_rst_en -DEVENT_CLK_RST -DCOND_EN 1951s + local subtest=clk_rst_en 1951s + shift 1951s + ../../yosys -p 'read_verilog -DEVENT_CLK_RST -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst_en-1.v 1951s Converted 0 switches. 1951s 1951s 1951s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1951s Creating decoders for process `\m.$proc$yosys-always_display-clk_en-1.v:18$1'. 1951s 1/1: $write$yosys-always_display-clk_en-1.v:20$2_EN 1951s 1951s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1951s 1951s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1951s 1951s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1951s 1951s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_en-1.v:18$1'. 1951s Removing empty process `m.$proc$yosys-always_display-clk_en-1.v:18$1'. 1951s Cleaned up 1 empty switch. 1951s 1951s 2.12. Executing OPT_EXPR pass (perform const folding). 1951s Optimizing module m. 1951s 1951s 3. Executing OPT_EXPR pass (perform const folding). 1951s Optimizing module m. 1951s 1951s Removed 0 unused cells and 3 unused wires. 1951s 1951s -- Writing to `yosys-always_display-clk_en-2.v' using backend `verilog' -- 1951s 1951s 4. Executing Verilog backend. 1951s 1951s 4.1. Executing BMUXMAP pass. 1951s 1951s 4.2. Executing DEMUXMAP pass. 1951s Dumping module `\m'. 1951s 1951s End of script. Logfile hash: 51e7fa3902, CPU: user 0.01s system 0.00s, MEM: 9.65 MB peak 1951s Yosys 0.33 (git sha1 2584903a060) 1951s Time spent: 37% 2x opt_expr (0 sec), 21% 1x clean (0 sec), ... 1951s 1951s /----------------------------------------------------------------------------\ 1951s | | 1951s | yosys -- Yosys Open SYnthesis Suite | 1951s | | 1951s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1951s | | 1951s | Permission to use, copy, modify, and/or distribute this software for any | 1951s | purpose with or without fee is hereby granted, provided that the above | 1951s | copyright notice and this permission notice appear in all copies. | 1951s | | 1951s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1951s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1951s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1951s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1951s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1951s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1951s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1951s | | 1951s \----------------------------------------------------------------------------/ 1951s 1951s Yosys 0.33 (git sha1 2584903a060) 1951s 1951s 1951s -- Running command `read_verilog -DEVENT_CLK_RST -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -- 1951s 1951s 1. Executing Verilog-2005 frontend: always_display.v 1951s Parsing Verilog input from `always_display.v' to AST representation. 1951s Generating RTLIL representation for module `\m'. 1951s Successfully finished Verilog frontend. 1951s 1951s 2. Executing PROC pass (convert processes to netlists). 1951s 1951s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Cleaned up 0 empty switches. 1951s 1951s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1951s Removed a total of 0 dead cases. 1951s 1951s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1951s Removed 0 redundant assignments. 1951s Promoted 0 assignments to connections. 1951s 1951s 2.4. Executing PROC_INIT pass (extract init attributes). 1951s 1951s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1951s 1951s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1951s Converted 0 switches. 1951s 1951s 1951s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1951s Creating decoders for process `\m.$proc$always_display.v:7$1'. 1951s 1/1: $display$always_display.v:15$2_EN 1951s 1951s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1951s 1951s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1951s 1951s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1951s 1951s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:7$1'. 1951s Removing empty process `m.$proc$always_display.v:7$1'. 1951s Cleaned up 1 empty switch. 1951s 1951s 2.12. Executing OPT_EXPR pass (perform const folding). 1951s Optimizing module m. 1951s 1951s 3. Executing OPT_EXPR pass (perform const folding). 1951s Optimizing module m. 1951s 1951s Removed 0 unused cells and 3 unused wires. 1951s 1951s -- Writing to `yosys-always_display-clk_rst_en-1.v' using backend `verilog' -- 1951s 1951s 4. Executing Verilog backend. 1951s 1951s 4.1. Executing BMUXMAP pass. 1951s 1951s 4.2. Executing DEMUXMAP pass. 1951s + ../../yosys -p 'read_verilog yosys-always_display-clk_rst_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst_en-2.v 1951s Dumping module `\m'. 1951s 1951s End of script. Logfile hash: f9b4876f33, CPU: user 0.01s system 0.00s, MEM: 9.66 MB peak 1951s Yosys 0.33 (git sha1 2584903a060) 1951s Time spent: 38% 2x opt_expr (0 sec), 21% 1x clean (0 sec), ... 1951s + diff yosys-always_display-clk_rst_en-1.v yosys-always_display-clk_rst_en-2.v 1951s 1951s /----------------------------------------------------------------------------\ 1951s | | 1951s | yosys -- Yosys Open SYnthesis Suite | 1951s | | 1951s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1951s | | 1951s | Permission to use, copy, modify, and/or distribute this software for any | 1951s | purpose with or without fee is hereby granted, provided that the above | 1951s | copyright notice and this permission notice appear in all copies. | 1951s | | 1951s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1951s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1951s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1951s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1951s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1951s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1951s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1951s | | 1951s \----------------------------------------------------------------------------/ 1951s 1951s Yosys 0.33 (git sha1 2584903a060) 1951s 1951s 1951s -- Running command `read_verilog yosys-always_display-clk_rst_en-1.v; proc; opt_expr -mux_bool; clean' -- 1951s 1951s 1. Executing Verilog-2005 frontend: yosys-always_display-clk_rst_en-1.v 1951s Parsing Verilog input from `yosys-always_display-clk_rst_en-1.v' to AST representation. 1951s Generating RTLIL representation for module `\m'. 1951s Successfully finished Verilog frontend. 1951s 1951s 2. Executing PROC pass (convert processes to netlists). 1951s 1951s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Cleaned up 0 empty switches. 1951s 1951s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1951s Removed a total of 0 dead cases. 1951s 1951s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1951s Removed 0 redundant assignments. 1951s Promoted 0 assignments to connections. 1951s 1951s 2.4. Executing PROC_INIT pass (extract init attributes). 1951s 1951s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1951s 1951s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1951s Converted 0 switches. 1951s 1951s 1951s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1951s Creating decoders for process `\m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'. 1951s 1/1: $write$yosys-always_display-clk_rst_en-1.v:20$2_EN 1951s 1951s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1951s 1951s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1951s 1951s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1951s 1951s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'. 1951s Removing empty process `m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'. 1951s Cleaned up 1 empty switch. 1951s 1951s 2.12. Executing OPT_EXPR pass (perform const folding). 1951s Optimizing module m. 1951s 1951s 3. Executing OPT_EXPR pass (perform const folding). 1951s Optimizing module m. 1951s 1951s Removed 0 unused cells and 3 unused wires. 1951s 1951s -- Writing to `yosys-always_display-clk_rst_en-2.v' using backend `verilog' -- 1951s 1951s 4. Executing Verilog backend. 1951s 1951s 4.1. Executing BMUXMAP pass. 1951s 1951s 4.2. Executing DEMUXMAP pass. 1951s Dumping module `\m'. 1951s 1951s End of script. Logfile hash: 0c4b4eaa9c, CPU: user 0.01s system 0.00s, MEM: 9.66 MB peak 1951s Yosys 0.33 (git sha1 2584903a060) 1951s Time spent: 37% 2x opt_expr (0 sec), 20% 1x clean (0 sec), ... 1951s + test_always_display star_en -DEVENT_STAR -DCOND_EN 1951s + local subtest=star_en 1951s + shift 1951s + ../../yosys -p 'read_verilog -DEVENT_STAR -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star_en-1.v 1951s 1951s /----------------------------------------------------------------------------\ 1951s | | 1951s | yosys -- Yosys Open SYnthesis Suite | 1951s | | 1951s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1951s | | 1951s | Permission to use, copy, modify, and/or distribute this software for any | 1951s | purpose with or without fee is hereby granted, provided that the above | 1951s | copyright notice and this permission notice appear in all copies. | 1951s | | 1951s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1951s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1951s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1951s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1951s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1951s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1951s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1951s | | 1951s \----------------------------------------------------------------------------/ 1951s 1951s Yosys 0.33 (git sha1 2584903a060) 1951s 1951s 1951s -- Running command `read_verilog -DEVENT_STAR -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -- 1951s 1951s 1. Executing Verilog-2005 frontend: always_display.v 1951s Parsing Verilog input from `always_display.v' to AST representation. 1951s Generating RTLIL representation for module `\m'. 1951s Successfully finished Verilog frontend. 1951s 1951s 2. Executing PROC pass (convert processes to netlists). 1951s 1951s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Cleaned up 0 empty switches. 1951s 1951s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1951s Removed a total of 0 dead cases. 1951s 1951s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1951s Removed 0 redundant assignments. 1951s Promoted 0 assignments to connections. 1951s 1951s 2.4. Executing PROC_INIT pass (extract init attributes). 1951s 1951s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1951s 1951s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1951s Converted 0 switches. 1951s 1951s 1951s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1951s Creating decoders for process `\m.$proc$always_display.v:10$1'. 1951s 1/1: $display$always_display.v:15$2_EN 1951s 1951s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1951s 1951s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1951s 1951s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1951s 1951s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:10$1'. 1951s Removing empty process `m.$proc$always_display.v:10$1'. 1951s Cleaned up 1 empty switch. 1951s 1951s 2.12. Executing OPT_EXPR pass (perform const folding). 1951s Optimizing module m. 1951s 1951s 3. Executing OPT_EXPR pass (perform const folding). 1951s Optimizing module m. 1951s 1951s Removed 0 unused cells and 3 unused wires. 1951s 1951s -- Writing to `yosys-always_display-star_en-1.v' using backend `verilog' -- 1951s 1951s 4. Executing Verilog backend. 1951s 1951s 4.1. Executing BMUXMAP pass. 1951s 1951s 4.2. Executing DEMUXMAP pass. 1951s Dumping module `\m'. 1951s 1951s End of script. Logfile hash: d6a7335726, CPU: user 0.01s system 0.00s, MEM: 9.66 MB peak 1951s Yosys 0.33 (git sha1 2584903a060) 1951s Time spent: 39% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ... 1951s 1951s /----------------------------------------------------------------------------\ 1951s | | 1951s | yosys -- Yosys Open SYnthesis Suite | 1951s | | 1951s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1951s | | 1951s | Permission to use, copy, modify, and/or distribute this software for any | 1951s | purpose with or without fee is hereby granted, provided that the above | 1951s | copyright notice and this permission notice appear in all copies. | 1951s | | 1951s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1951s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1951s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1951s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1951s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1951s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1951s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1951s | | 1951s \----------------------------------------------------------------------------/ 1951s 1951s Yosys 0.33 (git sha1 2584903a060) 1951s 1951s 1951s -- Running command `read_verilog yosys-always_display-star_en-1.v; proc; opt_expr -mux_bool; clean' -- 1951s 1951s 1. Executing Verilog-2005 frontend: yosys-always_display-star_en-1.v 1951s Parsing Verilog input from `yosys-always_display-star_en-1.v' to AST representation. 1951s Generating RTLIL representation for module `\m'. 1951s Successfully finished Verilog frontend. 1951s 1951s 2. Executing PROC pass (convert processes to netlists). 1951s 1951s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Cleaned up 0 empty switches. 1951s 1951s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1951s Removed a total of 0 dead cases. 1951s 1951s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1951s Removed 0 redundant assignments. 1951s Promoted 0 assignments to connections. 1951s 1951s 2.4. Executing PROC_INIT pass (extract init attributes). 1951s 1951s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1951s 1951s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1951s Converted 0 switches. 1951s 1951s 1951s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1951s Creating decoders for process `\m.$proc$yosys-always_display-star_en-1.v:18$1'. 1951s 1/1: $write$yosys-always_display-star_en-1.v:20$2_EN 1951s 1951s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1951s 1951s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1951s 1951s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1951s 1951s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-star_en-1.v:18$1'. 1951s Removing empty process `m.$proc$yosys-always_display-star_en-1.v:18$1'. 1951s Cleaned up 1 empty switch. 1951s 1951s 2.12. Executing OPT_EXPR pass (perform const folding). 1951s Optimizing module m. 1951s + ../../yosys -p 'read_verilog yosys-always_display-star_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star_en-2.v 1951s 1951s 3. Executing OPT_EXPR pass (perform const folding). 1951s Optimizing module m. 1951s 1951s Removed 0 unused cells and 3 unused wires. 1951s 1951s -- Writing to `yosys-always_display-star_en-2.v' using backend `verilog' -- 1951s 1951s 4. Executing Verilog backend. 1951s 1951s 4.1. Executing BMUXMAP pass. 1951s 1951s 4.2. Executing DEMUXMAP pass. 1951s Dumping module `\m'. 1951s 1951s End of script. Logfile hash: 18895a2046, CPU: user 0.01s system 0.00s, MEM: 9.66 MB peak 1951s Yosys 0.33 (git sha1 2584903a060) 1951s Time spent: 37% 2x opt_expr (0 sec), 21% 1x clean (0 sec), ... 1951s + diff yosys-always_display-star_en-1.v yosys-always_display-star_en-2.v 1951s + test_roundtrip dec_unsigned -DBASE_DEC -DSIGN= 1951s + local subtest=dec_unsigned 1951s + shift 1951s + ../../yosys -p 'read_verilog -DBASE_DEC -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-dec_unsigned-1.v 1951s 1951s /----------------------------------------------------------------------------\ 1951s | | 1951s | yosys -- Yosys Open SYnthesis Suite | 1951s | | 1951s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1951s | | 1951s | Permission to use, copy, modify, and/or distribute this software for any | 1951s | purpose with or without fee is hereby granted, provided that the above | 1951s | copyright notice and this permission notice appear in all copies. | 1951s | | 1951s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1951s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1951s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1951s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1951s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1951s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1951s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1951s | | 1951s \----------------------------------------------------------------------------/ 1951s 1951s Yosys 0.33 (git sha1 2584903a060) 1951s 1951s 1951s -- Running command `read_verilog -DBASE_DEC -DSIGN= roundtrip.v; proc; clean' -- 1951s 1951s 1. Executing Verilog-2005 frontend: roundtrip.v 1951s Parsing Verilog input from `roundtrip.v' to AST representation. 1951s Generating RTLIL representation for module `\m'. 1951s Successfully finished Verilog frontend. 1951s 1951s 2. Executing PROC pass (convert processes to netlists). 1951s 1951s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Cleaned up 0 empty switches. 1951s 1951s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1951s Removed a total of 0 dead cases. 1951s 1951s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1951s Removed 1 redundant assignment. 1951s Promoted 1 assignment to connection. 1951s 1951s 2.4. Executing PROC_INIT pass (extract init attributes). 1951s 1951s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1951s 1951s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1951s Converted 0 switches. 1951s 1951s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1951s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 1951s 1951s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1951s 1951s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1951s 1951s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1951s 1951s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Removing empty process `m.$proc$roundtrip.v:3$1'. 1951s Cleaned up 0 empty switches. 1951s 1951s 2.12. Executing OPT_EXPR pass (perform const folding). 1951s Optimizing module m. 1951s Removed 0 unused cells and 1 unused wires. 1951s 1951s -- Writing to `yosys-roundtrip-dec_unsigned-1.v' using backend `verilog' -- 1951s 1951s 3. Executing Verilog backend. 1951s 1951s 3.1. Executing BMUXMAP pass. 1951s 1951s 3.2. Executing DEMUXMAP pass. 1951s Dumping module `\m'. 1951s 1951s End of script. Logfile hash: bfb187b86d, CPU: user 0.00s system 0.00s, MEM: 9.66 MB peak 1951s Yosys 0.33 (git sha1 2584903a060) 1951s Time spent: 28% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ... 1951s 1951s /----------------------------------------------------------------------------\ 1951s | | 1951s | yosys -- Yosys Open SYnthesis Suite | 1951s | | 1951s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1951s | | 1951s | Permission to use, copy, modify, and/or distribute this software for any | 1951s | purpose with or without fee is hereby granted, provided that the above | 1951s | copyright notice and this permission notice appear in all copies. | 1951s | | 1951s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1951s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1951s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1951s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1951s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1951s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1951s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1951s | | 1951s \----------------------------------------------------------------------------/ 1951s 1951s Yosys 0.33 (git sha1 2584903a060) 1951s 1951s 1951s -- Running command `read_verilog yosys-roundtrip-dec_unsigned-1.v; proc; clean' -- 1951s 1951s 1. Executing Verilog-2005 frontend: yosys-roundtrip-dec_unsigned-1.v 1951s Parsing Verilog input from `yosys-roundtrip-dec_unsigned-1.v' to AST representation. 1951s Generating RTLIL representation for module `\m'. 1951s Successfully finished Verilog frontend. 1951s 1951s 2. Executing PROC pass (convert processes to netlists). 1951s 1951s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'. 1951s Cleaned up 1 empty switch. 1951s 1951s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1951s Removed a total of 0 dead cases. 1951s 1951s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1951s Removed 1 redundant assignment. 1951s Promoted 1 assignment to connection. 1951s 1951s 2.4. Executing PROC_INIT pass (extract init attributes). 1951s 1951s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1951s 1951s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1951s Converted 0 switches. 1951s 1951s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1951s Creating decoders for process `\m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'. 1951s 1951s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1951s 1951s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1951s 1951s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1951s 1951s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Removing empty process `m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'. 1951s Cleaned up 0 empty switches. 1951s 1951s 2.12. Executing OPT_EXPR pass (perform const folding). 1951s Optimizing module m. 1951s Removed 0 unused cells and 1 unused wires. 1951s 1951s -- Writing to `yosys-roundtrip-dec_unsigned-2.v' using backend `verilog' -- 1951s 1951s 3. Executing Verilog backend. 1951s 1951s 3.1. Executing BMUXMAP pass. 1951s 1951s 3.2. Executing DEMUXMAP pass. 1951s Dumping module `\m'. 1951s 1951s End of script. Logfile hash: 4be9539e85, CPU: user 0.00s system 0.00s, MEM: 9.66 MB peak 1951s Yosys 0.33 (git sha1 2584903a060) 1951s Time spent: 28% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 1951s + ../../yosys -p 'read_verilog yosys-roundtrip-dec_unsigned-1.v; proc; clean' -o yosys-roundtrip-dec_unsigned-2.v 1951s + diff yosys-roundtrip-dec_unsigned-1.v yosys-roundtrip-dec_unsigned-2.v 1951s + iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned roundtrip.v roundtrip_tb.v 1951s + ./iverilog-roundtrip-dec_unsigned 1951s + iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned-1 yosys-roundtrip-dec_unsigned-1.v roundtrip_tb.v 1951s + ./iverilog-roundtrip-dec_unsigned-1 1951s + iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned-2 yosys-roundtrip-dec_unsigned-2.v roundtrip_tb.v 1951s + ./iverilog-roundtrip-dec_unsigned-1 1951s + diff iverilog-roundtrip-dec_unsigned.log iverilog-roundtrip-dec_unsigned-1.log 1951s + diff iverilog-roundtrip-dec_unsigned-1.log iverilog-roundtrip-dec_unsigned-2.log 1951s 1951s /----------------------------------------------------------------------------\ 1951s | | 1951s | yosys -- Yosys Open SYnthesis Suite | 1951s | | 1951s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1951s | | 1951s | Permission to use, copy, modify, and/or distribute this software for any | 1951s | purpose with or without fee is hereby granted, provided that the above | 1951s | copyright notice and this permission notice appear in all copies. | 1951s | | 1951s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1951s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1951s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1951s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1951s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1951s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1951s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1951s | | 1951s \----------------------------------------------------------------------------/ 1951s 1951s Yosys 0.33 (git sha1 2584903a060) 1951s 1951s 1951s -- Running command `read_verilog -DBASE_DEC -DSIGN=signed roundtrip.v; proc; clean' -- 1951s 1951s 1. Executing Verilog-2005 frontend: roundtrip.v 1951s + test_roundtrip dec_signed -DBASE_DEC -DSIGN=signed 1951s + local subtest=dec_signed 1951s + shift 1951s + ../../yosys -p 'read_verilog -DBASE_DEC -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-dec_signed-1.v 1951s Parsing Verilog input from `roundtrip.v' to AST representation. 1951s Generating RTLIL representation for module `\m'. 1951s Successfully finished Verilog frontend. 1951s 1951s 2. Executing PROC pass (convert processes to netlists). 1951s 1951s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Cleaned up 0 empty switches. 1951s 1951s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1951s Removed a total of 0 dead cases. 1951s 1951s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1951s Removed 1 redundant assignment. 1951s Promoted 1 assignment to connection. 1951s 1951s 2.4. Executing PROC_INIT pass (extract init attributes). 1951s 1951s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1951s 1951s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1951s Converted 0 switches. 1951s 1951s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1951s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 1951s 1951s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1951s 1951s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1951s 1951s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1951s 1951s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Removing empty process `m.$proc$roundtrip.v:3$1'. 1951s Cleaned up 0 empty switches. 1951s 1951s 2.12. Executing OPT_EXPR pass (perform const folding). 1951s Optimizing module m. 1951s Removed 0 unused cells and 1 unused wires. 1951s 1951s -- Writing to `yosys-roundtrip-dec_signed-1.v' using backend `verilog' -- 1951s 1951s 3. Executing Verilog backend. 1951s 1951s 3.1. Executing BMUXMAP pass. 1951s 1951s 3.2. Executing DEMUXMAP pass. 1951s Dumping module `\m'. 1951s 1951s End of script. Logfile hash: bbdfa5ca92, CPU: user 0.01s system 0.00s, MEM: 9.66 MB peak 1951s Yosys 0.33 (git sha1 2584903a060) 1951s Time spent: 27% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 1951s + ../../yosys -p 'read_verilog yosys-roundtrip-dec_signed-1.v; proc; clean' -o yosys-roundtrip-dec_signed-2.v 1951s 1951s /----------------------------------------------------------------------------\ 1951s | | 1951s | yosys -- Yosys Open SYnthesis Suite | 1951s | | 1951s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1951s | | 1951s | Permission to use, copy, modify, and/or distribute this software for any | 1951s | purpose with or without fee is hereby granted, provided that the above | 1951s | copyright notice and this permission notice appear in all copies. | 1951s | | 1951s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1951s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1951s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1951s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1951s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1951s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1951s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1951s | | 1951s \----------------------------------------------------------------------------/ 1951s 1951s Yosys 0.33 (git sha1 2584903a060) 1951s 1951s 1951s -- Running command `read_verilog yosys-roundtrip-dec_signed-1.v; proc; clean' -- 1951s 1951s 1. Executing Verilog-2005 frontend: yosys-roundtrip-dec_signed-1.v 1951s Parsing Verilog input from `yosys-roundtrip-dec_signed-1.v' to AST representation. 1951s Generating RTLIL representation for module `\m'. 1951s Successfully finished Verilog frontend. 1951s 1951s 2. Executing PROC pass (convert processes to netlists). 1951s 1951s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'. 1951s Cleaned up 1 empty switch. 1951s 1951s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1951s Removed a total of 0 dead cases. 1951s 1951s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1951s Removed 1 redundant assignment. 1951s Promoted 1 assignment to connection. 1951s 1951s 2.4. Executing PROC_INIT pass (extract init attributes). 1951s 1951s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1951s 1951s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1951s Converted 0 switches. 1951s 1951s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1951s Creating decoders for process `\m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'. 1951s 1951s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1951s 1951s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1951s 1951s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1951s 1951s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Removing empty process `m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'. 1951s Cleaned up 0 empty switches. 1951s 1951s 2.12. Executing OPT_EXPR pass (perform const folding). 1951s Optimizing module m. 1951s + diff yosys-roundtrip-dec_signed-1.v yosys-roundtrip-dec_signed-2.v 1951s + iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed roundtrip.v roundtrip_tb.v 1951s Removed 0 unused cells and 1 unused wires. 1951s 1951s -- Writing to `yosys-roundtrip-dec_signed-2.v' using backend `verilog' -- 1951s 1951s 3. Executing Verilog backend. 1951s 1951s 3.1. Executing BMUXMAP pass. 1951s 1951s 3.2. Executing DEMUXMAP pass. 1951s Dumping module `\m'. 1951s 1951s End of script. Logfile hash: b233de92a6, CPU: user 0.01s system 0.00s, MEM: 9.66 MB peak 1951s Yosys 0.33 (git sha1 2584903a060) 1951s Time spent: 26% 1x clean (0 sec), 19% 1x opt_expr (0 sec), ... 1951s + ./iverilog-roundtrip-dec_signed 1951s + iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed-1 yosys-roundtrip-dec_signed-1.v roundtrip_tb.v 1951s + ./iverilog-roundtrip-dec_signed-1 1951s + iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed-2 yosys-roundtrip-dec_signed-2.v roundtrip_tb.v 1951s + ./iverilog-roundtrip-dec_signed-1 1951s + diff iverilog-roundtrip-dec_signed.log iverilog-roundtrip-dec_signed-1.log 1951s + diff iverilog-roundtrip-dec_signed-1.log iverilog-roundtrip-dec_signed-2.log 1951s + test_roundtrip hex_unsigned -DBASE_HEX -DSIGN= 1951s + local subtest=hex_unsigned 1951s + shift 1951s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-hex_unsigned-1.v 1951s 1951s /----------------------------------------------------------------------------\ 1951s | | 1951s | yosys -- Yosys Open SYnthesis Suite | 1951s | | 1951s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1951s | | 1951s | Permission to use, copy, modify, and/or distribute this software for any | 1951s | purpose with or without fee is hereby granted, provided that the above | 1951s | copyright notice and this permission notice appear in all copies. | 1951s | | 1951s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1951s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1951s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1951s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1951s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1951s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1951s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1951s | | 1951s \----------------------------------------------------------------------------/ 1951s 1951s Yosys 0.33 (git sha1 2584903a060) 1951s 1951s 1951s -- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -- 1951s 1951s 1. Executing Verilog-2005 frontend: roundtrip.v 1951s Parsing Verilog input from `roundtrip.v' to AST representation. 1951s Generating RTLIL representation for module `\m'. 1951s Successfully finished Verilog frontend. 1951s 1951s 2. Executing PROC pass (convert processes to netlists). 1951s 1951s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Cleaned up 0 empty switches. 1951s 1951s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1951s Removed a total of 0 dead cases. 1951s 1951s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1951s Removed 1 redundant assignment. 1951s Promoted 1 assignment to connection. 1951s 1951s 2.4. Executing PROC_INIT pass (extract init attributes). 1951s 1951s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1951s 1951s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1951s Converted 0 switches. 1951s 1951s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1951s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 1951s 1951s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1951s 1951s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1951s 1951s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1951s 1951s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Removing empty process `m.$proc$roundtrip.v:3$1'. 1951s Cleaned up 0 empty switches. 1951s 1951s 2.12. Executing OPT_EXPR pass (perform const folding). 1951s Optimizing module m. 1951s Removed 0 unused cells and 1 unused wires. 1951s 1951s -- Writing to `yosys-roundtrip-hex_unsigned-1.v' using backend `verilog' -- 1951s 1951s 3. Executing Verilog backend. 1951s 1951s 3.1. Executing BMUXMAP pass. 1951s 1951s 3.2. Executing DEMUXMAP pass. 1951s Dumping module `\m'. 1951s 1951s End of script. Logfile hash: 2377f2e106, CPU: user 0.00s system 0.00s, MEM: 9.66 MB peak 1951s Yosys 0.33 (git sha1 2584903a060) 1951s Time spent: 28% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... 1951s + ../../yosys -p 'read_verilog yosys-roundtrip-hex_unsigned-1.v; proc; clean' -o yosys-roundtrip-hex_unsigned-2.v 1951s 1951s /----------------------------------------------------------------------------\ 1951s | | 1951s | yosys -- Yosys Open SYnthesis Suite | 1951s | | 1951s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1951s | | 1951s | Permission to use, copy, modify, and/or distribute this software for any | 1951s | purpose with or without fee is hereby granted, provided that the above | 1951s | copyright notice and this permission notice appear in all copies. | 1951s | | 1951s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1951s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1951s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1951s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1951s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1951s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1951s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1951s | | 1951s \----------------------------------------------------------------------------/ 1951s 1951s Yosys 0.33 (git sha1 2584903a060) 1951s 1951s 1951s -- Running command `read_verilog yosys-roundtrip-hex_unsigned-1.v; proc; clean' -- 1951s 1951s 1. Executing Verilog-2005 frontend: yosys-roundtrip-hex_unsigned-1.v 1951s Parsing Verilog input from `yosys-roundtrip-hex_unsigned-1.v' to AST representation. 1951s Generating RTLIL representation for module `\m'. 1951s Successfully finished Verilog frontend. 1951s 1951s 2. Executing PROC pass (convert processes to netlists). 1951s 1951s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'. 1951s Cleaned up 1 empty switch. 1951s 1951s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1951s Removed a total of 0 dead cases. 1951s 1951s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1951s Removed 1 redundant assignment. 1951s Promoted 1 assignment to connection. 1951s 1951s 2.4. Executing PROC_INIT pass (extract init attributes). 1951s 1951s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1951s 1951s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1951s Converted 0 switches. 1951s 1951s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1951s Creating decoders for process `\m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'. 1951s 1951s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1951s 1951s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1951s 1951s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1951s 1951s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Removing empty process `m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'. 1951s Cleaned up 0 empty switches. 1951s 1951s 2.12. Executing OPT_EXPR pass (perform const folding). 1951s Optimizing module m. 1951s Removed 0 unused cells and 1 unused wires. 1951s 1951s -- Writing to `yosys-roundtrip-hex_unsigned-2.v' using backend `verilog' -- 1951s 1951s 3. Executing Verilog backend. 1951s 1951s 3.1. Executing BMUXMAP pass. 1951s 1951s 3.2. Executing DEMUXMAP pass. 1951s Dumping module `\m'. 1951s 1951s End of script. Logfile hash: 06bfea69c8, CPU: user 0.00s system 0.00s, MEM: 9.66 MB peak 1951s Yosys 0.33 (git sha1 2584903a060) 1951s Time spent: 26% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 1951s + diff yosys-roundtrip-hex_unsigned-1.v yosys-roundtrip-hex_unsigned-2.v 1951s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned roundtrip.v roundtrip_tb.v 1951s + ./iverilog-roundtrip-hex_unsigned 1951s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned-1 yosys-roundtrip-hex_unsigned-1.v roundtrip_tb.v 1951s + ./iverilog-roundtrip-hex_unsigned-1 1951s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned-2 yosys-roundtrip-hex_unsigned-2.v roundtrip_tb.v 1951s + ./iverilog-roundtrip-hex_unsigned-1 1951s + diff iverilog-roundtrip-hex_unsigned.log iverilog-roundtrip-hex_unsigned-1.log 1951s + diff iverilog-roundtrip-hex_unsigned-1.log iverilog-roundtrip-hex_unsigned-2.log 1951s + test_roundtrip hex_signed -DBASE_HEX -DSIGN=signed 1951s + local subtest=hex_signed 1951s + shift 1951s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-hex_signed-1.v 1951s 1951s /----------------------------------------------------------------------------\ 1951s | | 1951s | yosys -- Yosys Open SYnthesis Suite | 1951s | | 1951s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1951s | | 1951s | Permission to use, copy, modify, and/or distribute this software for any | 1951s | purpose with or without fee is hereby granted, provided that the above | 1951s | copyright notice and this permission notice appear in all copies. | 1951s | | 1951s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1951s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1951s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1951s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1951s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1951s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1951s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1951s | | 1951s \----------------------------------------------------------------------------/ 1951s 1951s Yosys 0.33 (git sha1 2584903a060) 1951s 1951s 1951s -- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -- 1951s 1951s 1. Executing Verilog-2005 frontend: roundtrip.v 1951s Parsing Verilog input from `roundtrip.v' to AST representation. 1951s Generating RTLIL representation for module `\m'. 1951s Successfully finished Verilog frontend. 1951s 1951s 2. Executing PROC pass (convert processes to netlists). 1951s 1951s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Cleaned up 0 empty switches. 1951s 1951s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1951s Removed a total of 0 dead cases. 1951s 1951s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1951s Removed 1 redundant assignment. 1951s Promoted 1 assignment to connection. 1951s 1951s 2.4. Executing PROC_INIT pass (extract init attributes). 1951s 1951s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1951s 1951s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1951s Converted 0 switches. 1951s 1951s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1951s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 1951s 1951s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1951s 1951s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1951s 1951s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1951s 1951s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Removing empty process `m.$proc$roundtrip.v:3$1'. 1951s Cleaned up 0 empty switches. 1951s 1951s 2.12. Executing OPT_EXPR pass (perform const folding). 1951s Optimizing module m. 1951s Removed 0 unused cells and 1 unused wires. 1951s 1951s -- Writing to `yosys-roundtrip-hex_signed-1.v' using backend `verilog' -- 1951s 1951s 3. Executing Verilog backend. 1951s 1951s 3.1. Executing BMUXMAP pass. 1951s 1951s 3.2. Executing DEMUXMAP pass. 1951s + ../../yosys -p 'read_verilog yosys-roundtrip-hex_signed-1.v; proc; clean' -o yosys-roundtrip-hex_signed-2.v 1951s Dumping module `\m'. 1951s 1951s End of script. Logfile hash: 824c3b1e65, CPU: user 0.00s system 0.00s, MEM: 9.66 MB peak 1951s Yosys 0.33 (git sha1 2584903a060) 1951s Time spent: 28% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... 1951s 1951s /----------------------------------------------------------------------------\ 1951s | | 1951s | yosys -- Yosys Open SYnthesis Suite | 1951s | | 1951s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1951s | | 1951s | Permission to use, copy, modify, and/or distribute this software for any | 1951s | purpose with or without fee is hereby granted, provided that the above | 1951s | copyright notice and this permission notice appear in all copies. | 1951s | | 1951s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1951s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1951s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1951s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1951s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1951s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1951s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1951s | | 1951s \----------------------------------------------------------------------------/ 1951s 1951s Yosys 0.33 (git sha1 2584903a060) 1951s 1951s 1951s -- Running command `read_verilog yosys-roundtrip-hex_signed-1.v; proc; clean' -- 1951s 1951s 1. Executing Verilog-2005 frontend: yosys-roundtrip-hex_signed-1.v 1951s Parsing Verilog input from `yosys-roundtrip-hex_signed-1.v' to AST representation. 1951s Generating RTLIL representation for module `\m'. 1951s Successfully finished Verilog frontend. 1951s 1951s 2. Executing PROC pass (convert processes to netlists). 1951s 1951s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'. 1951s Cleaned up 1 empty switch. 1951s 1951s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1951s Removed a total of 0 dead cases. 1951s 1951s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1951s Removed 1 redundant assignment. 1951s Promoted 1 assignment to connection. 1951s 1951s 2.4. Executing PROC_INIT pass (extract init attributes). 1951s 1951s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1951s 1951s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1951s Converted 0 switches. 1951s 1951s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1951s Creating decoders for process `\m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'. 1951s 1951s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1951s 1951s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1951s 1951s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1951s 1951s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Removing empty process `m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'. 1951s Cleaned up 0 empty switches. 1951s 1951s 2.12. Executing OPT_EXPR pass (perform const folding). 1951s + diff yosys-roundtrip-hex_signed-1.v yosys-roundtrip-hex_signed-2.v 1951s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed roundtrip.v roundtrip_tb.v 1951s Optimizing module m. 1951s Removed 0 unused cells and 1 unused wires. 1951s 1951s -- Writing to `yosys-roundtrip-hex_signed-2.v' using backend `verilog' -- 1951s 1951s 3. Executing Verilog backend. 1951s 1951s 3.1. Executing BMUXMAP pass. 1951s 1951s 3.2. Executing DEMUXMAP pass. 1951s Dumping module `\m'. 1951s 1951s End of script. Logfile hash: f18b3fa15b, CPU: user 0.01s system 0.00s, MEM: 9.64 MB peak 1951s Yosys 0.33 (git sha1 2584903a060) 1951s Time spent: 27% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 1951s + ./iverilog-roundtrip-hex_signed 1951s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed-1 yosys-roundtrip-hex_signed-1.v roundtrip_tb.v 1951s + ./iverilog-roundtrip-hex_signed-1 1951s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed-2 yosys-roundtrip-hex_signed-2.v roundtrip_tb.v 1951s + ./iverilog-roundtrip-hex_signed-1 1951s + diff iverilog-roundtrip-hex_signed.log iverilog-roundtrip-hex_signed-1.log 1951s + diff iverilog-roundtrip-hex_signed-1.log iverilog-roundtrip-hex_signed-2.log 1951s + test_roundtrip oct_unsigned -DBASE_HEX -DSIGN= 1951s + local subtest=oct_unsigned 1951s + shift 1951s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-oct_unsigned-1.v 1951s 1951s /----------------------------------------------------------------------------\ 1951s | | 1951s | yosys -- Yosys Open SYnthesis Suite | 1951s | | 1951s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1951s | | 1951s | Permission to use, copy, modify, and/or distribute this software for any | 1951s | purpose with or without fee is hereby granted, provided that the above | 1951s | copyright notice and this permission notice appear in all copies. | 1951s | | 1951s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1951s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1951s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1951s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1951s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1951s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1951s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1951s | | 1951s \----------------------------------------------------------------------------/ 1951s 1951s Yosys 0.33 (git sha1 2584903a060) 1951s 1951s 1951s -- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -- 1951s 1951s 1. Executing Verilog-2005 frontend: roundtrip.v 1951s Parsing Verilog input from `roundtrip.v' to AST representation. 1951s Generating RTLIL representation for module `\m'. 1951s Successfully finished Verilog frontend. 1951s 1951s 2. Executing PROC pass (convert processes to netlists). 1951s 1951s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Cleaned up 0 empty switches. 1951s 1951s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1951s Removed a total of 0 dead cases. 1951s 1951s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1951s Removed 1 redundant assignment. 1951s Promoted 1 assignment to connection. 1951s 1951s 2.4. Executing PROC_INIT pass (extract init attributes). 1951s 1951s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1951s 1951s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1951s Converted 0 switches. 1951s 1951s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1951s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 1951s 1951s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1951s 1951s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1951s 1951s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1951s 1951s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Removing empty process `m.$proc$roundtrip.v:3$1'. 1951s Cleaned up 0 empty switches. 1951s 1951s 2.12. Executing OPT_EXPR pass (perform const folding). 1951s Optimizing module m. 1951s Removed 0 unused cells and 1 unused wires. 1951s 1951s -- Writing to `yosys-roundtrip-oct_unsigned-1.v' using backend `verilog' -- 1951s 1951s 3. Executing Verilog backend. 1951s 1951s 3.1. Executing BMUXMAP pass. 1951s 1951s 3.2. Executing DEMUXMAP pass. 1951s Dumping module `\m'. 1951s 1951s End of script. Logfile hash: b768358a65, CPU: user 0.01s system 0.00s, MEM: 9.65 MB peak 1951s Yosys 0.33 (git sha1 2584903a060) 1951s Time spent: 28% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 1951s + ../../yosys -p 'read_verilog yosys-roundtrip-oct_unsigned-1.v; proc; clean' -o yosys-roundtrip-oct_unsigned-2.v 1951s 1951s /----------------------------------------------------------------------------\ 1951s | | 1951s | yosys -- Yosys Open SYnthesis Suite | 1951s | | 1951s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1951s | | 1951s | Permission to use, copy, modify, and/or distribute this software for any | 1951s | purpose with or without fee is hereby granted, provided that the above | 1951s | copyright notice and this permission notice appear in all copies. | 1951s | | 1951s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1951s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1951s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1951s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1951s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1951s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1951s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1951s | | 1951s \----------------------------------------------------------------------------/ 1951s 1951s Yosys 0.33 (git sha1 2584903a060) 1951s 1951s 1951s -- Running command `read_verilog yosys-roundtrip-oct_unsigned-1.v; proc; clean' -- 1951s 1951s 1. Executing Verilog-2005 frontend: yosys-roundtrip-oct_unsigned-1.v 1951s Parsing Verilog input from `yosys-roundtrip-oct_unsigned-1.v' to AST representation. 1951s Generating RTLIL representation for module `\m'. 1951s Successfully finished Verilog frontend. 1951s 1951s 2. Executing PROC pass (convert processes to netlists). 1951s 1951s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'. 1951s Cleaned up 1 empty switch. 1951s 1951s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1951s Removed a total of 0 dead cases. 1951s 1951s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1951s Removed 1 redundant assignment. 1951s Promoted 1 assignment to connection. 1951s 1951s 2.4. Executing PROC_INIT pass (extract init attributes). 1951s 1951s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1951s 1951s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1951s Converted 0 switches. 1951s 1951s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1951s Creating decoders for process `\m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'. 1951s 1951s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1951s 1951s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1951s 1951s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1951s 1951s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Removing empty process `m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'. 1951s Cleaned up 0 empty switches. 1951s 1951s 2.12. Executing OPT_EXPR pass (perform const folding). 1951s Optimizing module m. 1951s Removed 0 unused cells and 1 unused wires. 1951s 1951s -- Writing to `yosys-roundtrip-oct_unsigned-2.v' using backend `verilog' -- 1951s 1951s 3. Executing Verilog backend. 1951s + diff yosys-roundtrip-oct_unsigned-1.v yosys-roundtrip-oct_unsigned-2.v 1951s 1951s 3.1. Executing BMUXMAP pass. 1951s 1951s 3.2. Executing DEMUXMAP pass. 1951s Dumping module `\m'. 1951s 1951s End of script. Logfile hash: 762621cd95, CPU: user 0.01s system 0.00s, MEM: 9.66 MB peak 1951s Yosys 0.33 (git sha1 2584903a060) 1951s Time spent: 26% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... 1951s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned roundtrip.v roundtrip_tb.v 1951s + ./iverilog-roundtrip-oct_unsigned 1951s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned-1 yosys-roundtrip-oct_unsigned-1.v roundtrip_tb.v 1951s + ./iverilog-roundtrip-oct_unsigned-1 1951s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned-2 yosys-roundtrip-oct_unsigned-2.v roundtrip_tb.v 1951s + ./iverilog-roundtrip-oct_unsigned-1 1951s + diff iverilog-roundtrip-oct_unsigned.log iverilog-roundtrip-oct_unsigned-1.log 1951s + diff iverilog-roundtrip-oct_unsigned-1.log iverilog-roundtrip-oct_unsigned-2.log 1951s + test_roundtrip oct_signed -DBASE_HEX -DSIGN=signed 1951s + local subtest=oct_signed 1951s + shift 1951s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-oct_signed-1.v 1951s 1951s /----------------------------------------------------------------------------\ 1951s | | 1951s | yosys -- Yosys Open SYnthesis Suite | 1951s | | 1951s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1951s | | 1951s | Permission to use, copy, modify, and/or distribute this software for any | 1951s | purpose with or without fee is hereby granted, provided that the above | 1951s | copyright notice and this permission notice appear in all copies. | 1951s | | 1951s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1951s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1951s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1951s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1951s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1951s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1951s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1951s | | 1951s \----------------------------------------------------------------------------/ 1951s 1951s Yosys 0.33 (git sha1 2584903a060) 1951s 1951s 1951s -- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -- 1951s 1951s 1. Executing Verilog-2005 frontend: roundtrip.v 1951s Parsing Verilog input from `roundtrip.v' to AST representation. 1951s Generating RTLIL representation for module `\m'. 1951s Successfully finished Verilog frontend. 1951s 1951s 2. Executing PROC pass (convert processes to netlists). 1951s 1951s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Cleaned up 0 empty switches. 1951s 1951s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1951s Removed a total of 0 dead cases. 1951s 1951s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1951s Removed 1 redundant assignment. 1951s Promoted 1 assignment to connection. 1951s 1951s 2.4. Executing PROC_INIT pass (extract init attributes). 1951s 1951s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1951s 1951s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1951s Converted 0 switches. 1951s 1951s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1951s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 1951s 1951s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1951s 1951s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1951s 1951s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1951s 1951s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Removing empty process `m.$proc$roundtrip.v:3$1'. 1951s Cleaned up 0 empty switches. 1951s 1951s 2.12. Executing OPT_EXPR pass (perform const folding). 1951s Optimizing module m. 1951s Removed 0 unused cells and 1 unused wires. 1951s 1951s -- Writing to `yosys-roundtrip-oct_signed-1.v' using backend `verilog' -- 1951s 1951s 3. Executing Verilog backend. 1951s 1951s 3.1. Executing BMUXMAP pass. 1951s 1951s 3.2. Executing DEMUXMAP pass. 1951s + ../../yosys -p 'read_verilog yosys-roundtrip-oct_signed-1.v; proc; clean' -o yosys-roundtrip-oct_signed-2.v 1951s Dumping module `\m'. 1951s 1951s End of script. Logfile hash: 7ec82b15e3, CPU: user 0.00s system 0.00s, MEM: 9.66 MB peak 1951s Yosys 0.33 (git sha1 2584903a060) 1951s Time spent: 28% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 1951s 1951s /----------------------------------------------------------------------------\ 1951s | | 1951s | yosys -- Yosys Open SYnthesis Suite | 1951s | | 1951s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1951s | | 1951s | Permission to use, copy, modify, and/or distribute this software for any | 1951s | purpose with or without fee is hereby granted, provided that the above | 1951s | copyright notice and this permission notice appear in all copies. | 1951s | | 1951s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1951s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1951s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1951s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1951s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1951s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1951s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1951s | | 1951s \----------------------------------------------------------------------------/ 1951s 1951s Yosys 0.33 (git sha1 2584903a060) 1951s 1951s 1951s -- Running command `read_verilog yosys-roundtrip-oct_signed-1.v; proc; clean' -- 1951s 1951s 1. Executing Verilog-2005 frontend: yosys-roundtrip-oct_signed-1.v 1951s Parsing Verilog input from `yosys-roundtrip-oct_signed-1.v' to AST representation. 1951s Generating RTLIL representation for module `\m'. 1951s Successfully finished Verilog frontend. 1951s 1951s 2. Executing PROC pass (convert processes to netlists). 1951s 1951s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'. 1951s Cleaned up 1 empty switch. 1951s 1951s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1951s Removed a total of 0 dead cases. 1951s 1951s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1951s Removed 1 redundant assignment. 1951s Promoted 1 assignment to connection. 1951s 1951s 2.4. Executing PROC_INIT pass (extract init attributes). 1951s 1951s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1951s 1951s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1951s Converted 0 switches. 1951s 1951s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1951s Creating decoders for process `\m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'. 1951s 1951s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1951s 1951s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1951s 1951s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1951s 1951s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Removing empty process `m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'. 1951s Cleaned up 0 empty switches. 1951s 1951s 2.12. Executing OPT_EXPR pass (perform const folding). 1951s Optimizing module m. 1951s Removed 0 unused cells and 1 unused wires. 1951s 1951s -- Writing to `yosys-roundtrip-oct_signed-2.v' using backend `verilog' -- 1951s 1951s 3. Executing Verilog backend. 1951s 1951s 3.1. Executing BMUXMAP pass. 1951s 1951s 3.2. Executing DEMUXMAP pass. 1951s + diff yosys-roundtrip-oct_signed-1.v yosys-roundtrip-oct_signed-2.v 1951s Dumping module `\m'. 1951s 1951s End of script. Logfile hash: a747b9bd4f, CPU: user 0.01s system 0.00s, MEM: 9.66 MB peak 1951s Yosys 0.33 (git sha1 2584903a060) 1951s Time spent: 29% 1x clean (0 sec), 19% 1x opt_expr (0 sec), ... 1951s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed roundtrip.v roundtrip_tb.v 1951s + ./iverilog-roundtrip-oct_signed 1951s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed-1 yosys-roundtrip-oct_signed-1.v roundtrip_tb.v 1951s + ./iverilog-roundtrip-oct_signed-1 1951s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed-2 yosys-roundtrip-oct_signed-2.v roundtrip_tb.v 1951s + ./iverilog-roundtrip-oct_signed-1 1951s + diff iverilog-roundtrip-oct_signed.log iverilog-roundtrip-oct_signed-1.log 1951s + diff iverilog-roundtrip-oct_signed-1.log iverilog-roundtrip-oct_signed-2.log 1951s + test_roundtrip bin_unsigned -DBASE_HEX -DSIGN= 1951s + local subtest=bin_unsigned 1951s + shift 1951s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-bin_unsigned-1.v 1951s 1951s /----------------------------------------------------------------------------\ 1951s | | 1951s | yosys -- Yosys Open SYnthesis Suite | 1951s | | 1951s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1951s | | 1951s | Permission to use, copy, modify, and/or distribute this software for any | 1951s | purpose with or without fee is hereby granted, provided that the above | 1951s | copyright notice and this permission notice appear in all copies. | 1951s | | 1951s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1951s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1951s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1951s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1951s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1951s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1951s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1951s | | 1951s \----------------------------------------------------------------------------/ 1951s 1951s Yosys 0.33 (git sha1 2584903a060) 1951s 1951s 1951s -- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -- 1951s 1951s 1. Executing Verilog-2005 frontend: roundtrip.v 1951s Parsing Verilog input from `roundtrip.v' to AST representation. 1951s Generating RTLIL representation for module `\m'. 1951s Successfully finished Verilog frontend. 1951s 1951s 2. Executing PROC pass (convert processes to netlists). 1951s 1951s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Cleaned up 0 empty switches. 1951s 1951s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1951s Removed a total of 0 dead cases. 1951s 1951s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1951s Removed 1 redundant assignment. 1951s Promoted 1 assignment to connection. 1951s 1951s 2.4. Executing PROC_INIT pass (extract init attributes). 1951s 1951s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1951s 1951s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1951s Converted 0 switches. 1951s 1951s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1951s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 1951s 1951s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1951s 1951s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1951s 1951s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1951s 1951s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Removing empty process `m.$proc$roundtrip.v:3$1'. 1951s Cleaned up 0 empty switches. 1951s 1951s 2.12. Executing OPT_EXPR pass (perform const folding). 1951s Optimizing module m. 1951s Removed 0 unused cells and 1 unused wires. 1951s 1951s -- Writing to `yosys-roundtrip-bin_unsigned-1.v' using backend `verilog' -- 1951s 1951s 3. Executing Verilog backend. 1951s 1951s 3.1. Executing BMUXMAP pass. 1951s 1951s 3.2. Executing DEMUXMAP pass. 1951s Dumping module `\m'. 1951s 1951s End of script. Logfile hash: 270b564880, CPU: user 0.01s system 0.00s, MEM: 9.66 MB peak 1951s Yosys 0.33 (git sha1 2584903a060) 1951s Time spent: 28% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... 1951s + ../../yosys -p 'read_verilog yosys-roundtrip-bin_unsigned-1.v; proc; clean' -o yosys-roundtrip-bin_unsigned-2.v 1951s + diff yosys-roundtrip-bin_unsigned-1.v yosys-roundtrip-bin_unsigned-2.v 1951s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned roundtrip.v roundtrip_tb.v 1951s + ./iverilog-roundtrip-bin_unsigned 1951s 1951s /----------------------------------------------------------------------------\ 1951s | | 1951s | yosys -- Yosys Open SYnthesis Suite | 1951s | | 1951s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1951s | | 1951s | Permission to use, copy, modify, and/or distribute this software for any | 1951s | purpose with or without fee is hereby granted, provided that the above | 1951s | copyright notice and this permission notice appear in all copies. | 1951s | | 1951s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1951s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1951s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1951s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1951s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1951s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1951s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1951s | | 1951s \----------------------------------------------------------------------------/ 1951s 1951s Yosys 0.33 (git sha1 2584903a060) 1951s 1951s 1951s -- Running command `read_verilog yosys-roundtrip-bin_unsigned-1.v; proc; clean' -- 1951s 1951s 1. Executing Verilog-2005 frontend: yosys-roundtrip-bin_unsigned-1.v 1951s Parsing Verilog input from `yosys-roundtrip-bin_unsigned-1.v' to AST representation. 1951s Generating RTLIL representation for module `\m'. 1951s Successfully finished Verilog frontend. 1951s 1951s 2. Executing PROC pass (convert processes to netlists). 1951s 1951s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'. 1951s Cleaned up 1 empty switch. 1951s 1951s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1951s Removed a total of 0 dead cases. 1951s 1951s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1951s Removed 1 redundant assignment. 1951s Promoted 1 assignment to connection. 1951s 1951s 2.4. Executing PROC_INIT pass (extract init attributes). 1951s 1951s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1951s 1951s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1951s Converted 0 switches. 1951s 1951s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1951s Creating decoders for process `\m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'. 1951s 1951s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1951s 1951s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1951s 1951s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1951s 1951s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Removing empty process `m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'. 1951s Cleaned up 0 empty switches. 1951s 1951s 2.12. Executing OPT_EXPR pass (perform const folding). 1951s Optimizing module m. 1951s Removed 0 unused cells and 1 unused wires. 1951s 1951s -- Writing to `yosys-roundtrip-bin_unsigned-2.v' using backend `verilog' -- 1951s 1951s 3. Executing Verilog backend. 1951s 1951s 3.1. Executing BMUXMAP pass. 1951s 1951s 3.2. Executing DEMUXMAP pass. 1951s Dumping module `\m'. 1951s 1951s End of script. Logfile hash: dc9f56cb10, CPU: user 0.01s system 0.00s, MEM: 9.66 MB peak 1951s Yosys 0.33 (git sha1 2584903a060) 1951s Time spent: 27% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 1951s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned-1 yosys-roundtrip-bin_unsigned-1.v roundtrip_tb.v 1951s + ./iverilog-roundtrip-bin_unsigned-1 1951s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned-2 yosys-roundtrip-bin_unsigned-2.v roundtrip_tb.v 1951s + ./iverilog-roundtrip-bin_unsigned-1 1951s + diff iverilog-roundtrip-bin_unsigned.log iverilog-roundtrip-bin_unsigned-1.log 1951s + diff iverilog-roundtrip-bin_unsigned-1.log iverilog-roundtrip-bin_unsigned-2.log 1951s + test_roundtrip bin_signed -DBASE_HEX -DSIGN=signed 1951s + local subtest=bin_signed 1951s + shift 1951s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-bin_signed-1.v 1951s 1951s /----------------------------------------------------------------------------\ 1951s | | 1951s | yosys -- Yosys Open SYnthesis Suite | 1951s | | 1951s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1951s | | 1951s | Permission to use, copy, modify, and/or distribute this software for any | 1951s | purpose with or without fee is hereby granted, provided that the above | 1951s | copyright notice and this permission notice appear in all copies. | 1951s | | 1951s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1951s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1951s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1951s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1951s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1951s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1951s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1951s | | 1951s \----------------------------------------------------------------------------/ 1951s 1951s Yosys 0.33 (git sha1 2584903a060) 1951s 1951s 1951s -- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -- 1951s 1951s 1. Executing Verilog-2005 frontend: roundtrip.v 1951s Parsing Verilog input from `roundtrip.v' to AST representation. 1951s Generating RTLIL representation for module `\m'. 1951s Successfully finished Verilog frontend. 1951s 1951s 2. Executing PROC pass (convert processes to netlists). 1951s 1951s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Cleaned up 0 empty switches. 1951s 1951s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1951s Removed a total of 0 dead cases. 1951s 1951s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1951s Removed 1 redundant assignment. 1951s Promoted 1 assignment to connection. 1951s 1951s 2.4. Executing PROC_INIT pass (extract init attributes). 1951s 1951s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1951s 1951s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1951s Converted 0 switches. 1951s 1951s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1951s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 1951s 1951s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1951s 1951s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1951s 1951s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1951s 1951s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Removing empty process `m.$proc$roundtrip.v:3$1'. 1951s Cleaned up 0 empty switches. 1951s 1951s 2.12. Executing OPT_EXPR pass (perform const folding). 1951s Optimizing module m. 1951s Removed 0 unused cells and 1 unused wires. 1951s 1951s -- Writing to `yosys-roundtrip-bin_signed-1.v' using backend `verilog' -- 1951s 1951s 3. Executing Verilog backend. 1951s 1951s 3.1. Executing BMUXMAP pass. 1951s 1951s 3.2. Executing DEMUXMAP pass. 1951s Dumping module `\m'. 1951s 1951s End of script. Logfile hash: 7709253822, CPU: user 0.01s system 0.00s, MEM: 9.66 MB peak 1951s Yosys 0.33 (git sha1 2584903a060) 1951s Time spent: 29% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 1951s 1951s /----------------------------------------------------------------------------\ 1951s | | 1951s | yosys -- Yosys Open SYnthesis Suite | 1951s | | 1951s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1951s | | 1951s | Permission to use, copy, modify, and/or distribute this software for any | 1951s | purpose with or without fee is hereby granted, provided that the above | 1951s | copyright notice and this permission notice appear in all copies. | 1951s | | 1951s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1951s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1951s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1951s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1951s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1951s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1951s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1951s | | 1951s \----------------------------------------------------------------------------/ 1951s 1951s Yosys 0.33 (git sha1 2584903a060) 1951s 1951s 1951s -- Running command `read_verilog yosys-roundtrip-bin_signed-1.v; proc; clean' -- 1951s 1951s 1. Executing Verilog-2005 frontend: yosys-roundtrip-bin_signed-1.v 1951s Parsing Verilog input from `yosys-roundtrip-bin_signed-1.v' to AST representation. 1951s Generating RTLIL representation for module `\m'. 1951s Successfully finished Verilog frontend. 1951s 1951s 2. Executing PROC pass (convert processes to netlists). 1951s 1951s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'. 1951s Cleaned up 1 empty switch. 1951s 1951s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1951s Removed a total of 0 dead cases. 1951s 1951s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1951s Removed 1 redundant assignment. 1951s Promoted 1 assignment to connection. 1951s 1951s 2.4. Executing PROC_INIT pass (extract init attributes). 1951s 1951s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1951s 1951s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1951s Converted 0 switches. 1951s 1951s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1951s Creating decoders for process `\m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'. 1951s 1951s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1951s 1951s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1951s + ../../yosys -p 'read_verilog yosys-roundtrip-bin_signed-1.v; proc; clean' -o yosys-roundtrip-bin_signed-2.v 1951s 1951s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1951s 1951s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Removing empty process `m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'. 1951s Cleaned up 0 empty switches. 1951s 1951s 2.12. Executing OPT_EXPR pass (perform const folding). 1951s Optimizing module m. 1951s Removed 0 unused cells and 1 unused wires. 1951s 1951s -- Writing to `yosys-roundtrip-bin_signed-2.v' using backend `verilog' -- 1951s 1951s 3. Executing Verilog backend. 1951s 1951s 3.1. Executing BMUXMAP pass. 1951s 1951s 3.2. Executing DEMUXMAP pass. 1951s Dumping module `\m'. 1951s 1951s End of script. Logfile hash: 7e2d8271c4, CPU: user 0.01s system 0.00s, MEM: 9.66 MB peak 1951s Yosys 0.33 (git sha1 2584903a060) 1951s Time spent: 26% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... 1951s + diff yosys-roundtrip-bin_signed-1.v yosys-roundtrip-bin_signed-2.v 1951s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed roundtrip.v roundtrip_tb.v 1951s + ./iverilog-roundtrip-bin_signed 1951s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed-1 yosys-roundtrip-bin_signed-1.v roundtrip_tb.v 1951s + ./iverilog-roundtrip-bin_signed-1 1951s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed-2 yosys-roundtrip-bin_signed-2.v roundtrip_tb.v 1951s + ./iverilog-roundtrip-bin_signed-1 1951s + diff iverilog-roundtrip-bin_signed.log iverilog-roundtrip-bin_signed-1.log 1951s + diff iverilog-roundtrip-bin_signed-1.log iverilog-roundtrip-bin_signed-2.log 1951s + test_cxxrtl always_full 1951s + local subtest=always_full 1951s + shift 1951s + ../../yosys -p 'read_verilog always_full.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_full.cc' 1951s 1951s /----------------------------------------------------------------------------\ 1951s | | 1951s | yosys -- Yosys Open SYnthesis Suite | 1951s | | 1951s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1951s | | 1951s | Permission to use, copy, modify, and/or distribute this software for any | 1951s | purpose with or without fee is hereby granted, provided that the above | 1951s | copyright notice and this permission notice appear in all copies. | 1951s | | 1951s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1951s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1951s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1951s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1951s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1951s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1951s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1951s | | 1951s \----------------------------------------------------------------------------/ 1951s 1951s Yosys 0.33 (git sha1 2584903a060) 1951s 1951s 1951s -- Running command `read_verilog always_full.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_full.cc' -- 1951s 1951s 1. Executing Verilog-2005 frontend: always_full.v 1951s Parsing Verilog input from `always_full.v' to AST representation. 1951s Generating RTLIL representation for module `\always_full'. 1951s Successfully finished Verilog frontend. 1951s 1951s 2. Executing PROC pass (convert processes to netlists). 1951s 1951s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Cleaned up 0 empty switches. 1951s 1951s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1951s Removed a total of 0 dead cases. 1951s 1951s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1951s Removed 207 redundant assignments. 1951s Promoted 207 assignments to connections. 1951s 1951s 2.4. Executing PROC_INIT pass (extract init attributes). 1951s 1951s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1951s 1951s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1951s Converted 0 switches. 1951s 1951s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1951s Creating decoders for process `\always_full.$proc$always_full.v:3$1'. 1951s 1951s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1951s 1951s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1951s 1951s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1951s 1951s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Removing empty process `always_full.$proc$always_full.v:3$1'. 1951s Cleaned up 0 empty switches. 1951s 1951s 2.12. Executing OPT_EXPR pass (perform const folding). 1951s Optimizing module always_full. 1951s Removed 0 unused cells and 207 unused wires. 1951s 1951s 3. Executing CXXRTL backend. 1951s 1951s 3.1. Executing HIERARCHY pass (managing design hierarchy). 1951s 1951s 3.1.1. Finding top of design hierarchy.. 1951s root of 0 design levels: always_full 1951s Automatically selected always_full as design top module. 1951s 1951s 3.1.2. Analyzing design hierarchy.. 1951s Top module: \always_full 1951s 1951s 3.1.3. Analyzing design hierarchy.. 1951s Top module: \always_full 1951s Removed 0 unused modules. 1951s 1951s 3.2. Executing FLATTEN pass (flatten design). 1951s 1951s 3.3. Executing PROC pass (convert processes to netlists). 1951s 1951s 3.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Cleaned up 0 empty switches. 1951s 1951s 3.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1951s Removed a total of 0 dead cases. 1951s 1951s 3.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1951s Removed 0 redundant assignments. 1951s Promoted 0 assignments to connections. 1951s 1951s 3.3.4. Executing PROC_INIT pass (extract init attributes). 1951s 1951s 3.3.5. Executing PROC_ARST pass (detect async resets in processes). 1951s 1951s 3.3.6. Executing PROC_ROM pass (convert switches to ROMs). 1951s Converted 0 switches. 1951s 1951s 3.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1951s 1951s 3.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1951s 1951s 3.3.9. Executing PROC_DFF pass (convert process syncs to FFs). 1951s 1951s 3.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1951s 1951s 3.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1951s Cleaned up 0 empty switches. 1951s 1951s 3.3.12. Executing OPT_EXPR pass (perform const folding). 1951s Optimizing module always_full. 1951s 1951s 1951s 1951s End of script. Logfile hash: 6abd135c0a, CPU: user 0.02s system 0.00s, MEM: 10.79 MB peak 1951s Yosys 0.33 (git sha1 2584903a060) 1951s Time spent: 26% 2x read_verilog (0 sec), 21% 2x opt_expr (0 sec), ... 1951s + gcc -std=c++11 -o yosys-always_full -I../.. always_full_tb.cc -lstdc++ 1953s + ./yosys-always_full 1953s + iverilog -o iverilog-always_full always_full.v always_full_tb.v 1953s + ./iverilog-always_full 1953s + grep -v '\$finish called' 1953s + diff iverilog-always_full.log yosys-always_full.log 1953s + test_cxxrtl always_comb 1953s + local subtest=always_comb 1953s + shift 1953s + ../../yosys -p 'read_verilog always_comb.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_comb.cc' 1953s 1953s /----------------------------------------------------------------------------\ 1953s | | 1953s | yosys -- Yosys Open SYnthesis Suite | 1953s | | 1953s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1953s | | 1953s | Permission to use, copy, modify, and/or distribute this software for any | 1953s | purpose with or without fee is hereby granted, provided that the above | 1953s | copyright notice and this permission notice appear in all copies. | 1953s | | 1953s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1953s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1953s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1953s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1953s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1953s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1953s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1953s | | 1953s \----------------------------------------------------------------------------/ 1953s 1953s Yosys 0.33 (git sha1 2584903a060) 1953s 1953s 1953s -- Running command `read_verilog always_comb.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_comb.cc' -- 1953s 1953s 1. Executing Verilog-2005 frontend: always_comb.v 1953s Parsing Verilog input from `always_comb.v' to AST representation. 1953s Generating RTLIL representation for module `\top'. 1953s Generating RTLIL representation for module `\sub'. 1953s Successfully finished Verilog frontend. 1953s 1953s 2. Executing PROC pass (convert processes to netlists). 1953s 1953s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1953s Cleaned up 0 empty switches. 1953s 1953s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1953s Removed a total of 0 dead cases. 1953s 1953s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1953s Removed 0 redundant assignments. 1953s Promoted 4 assignments to connections. 1953s 1953s 2.4. Executing PROC_INIT pass (extract init attributes). 1953s Found init rule in `\top.$proc$always_comb.v:3$13'. 1953s Set init value: \b = 1'0 1953s Found init rule in `\top.$proc$always_comb.v:2$12'. 1953s Set init value: \a = 1'0 1953s 1953s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1953s 1953s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1953s Converted 0 switches. 1953s 1953s 1953s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1953s Creating decoders for process `\sub.$proc$always_comb.v:23$15'. 1953s 1/1: $display$always_comb.v:23$19_EN 1953s Creating decoders for process `\top.$proc$always_comb.v:3$13'. 1953s Creating decoders for process `\top.$proc$always_comb.v:2$12'. 1953s Creating decoders for process `\top.$proc$always_comb.v:8$1'. 1953s 1953s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1953s 1953s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1953s Creating register for signal `\top.\a' using process `\top.$proc$always_comb.v:8$1'. 1953s created $dff cell `$procdff$22' with positive edge clock. 1953s Creating register for signal `\top.\b' using process `\top.$proc$always_comb.v:8$1'. 1953s created $dff cell `$procdff$23' with positive edge clock. 1953s 1953s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1953s 1953s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1953s + gcc -std=c++11 -o yosys-always_comb -I../.. always_comb_tb.cc -lstdc++ 1953s Found and cleaned up 1 empty switch in `\sub.$proc$always_comb.v:23$15'. 1953s Removing empty process `sub.$proc$always_comb.v:23$15'. 1953s Removing empty process `top.$proc$always_comb.v:3$13'. 1953s Removing empty process `top.$proc$always_comb.v:2$12'. 1953s Removing empty process `top.$proc$always_comb.v:8$1'. 1953s Cleaned up 1 empty switch. 1953s 1953s 2.12. Executing OPT_EXPR pass (perform const folding). 1953s Optimizing module sub. 1953s Optimizing module top. 1953s Removed 0 unused cells and 7 unused wires. 1953s 1953s 3. Executing CXXRTL backend. 1953s 1953s 3.1. Executing HIERARCHY pass (managing design hierarchy). 1953s 1953s 3.1.1. Finding top of design hierarchy.. 1953s root of 0 design levels: sub 1953s root of 1 design levels: top 1953s Automatically selected top as design top module. 1953s 1953s 3.1.2. Analyzing design hierarchy.. 1953s Top module: \top 1953s Used module: \sub 1953s 1953s 3.1.3. Analyzing design hierarchy.. 1953s Top module: \top 1953s Used module: \sub 1953s Removed 0 unused modules. 1953s 1953s 3.2. Executing FLATTEN pass (flatten design). 1953s Deleting now unused module sub. 1953s 1953s 1953s 3.3. Executing PROC pass (convert processes to netlists). 1953s 1953s 3.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1953s Cleaned up 0 empty switches. 1953s 1953s 3.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1953s Removed a total of 0 dead cases. 1953s 1953s 3.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1953s Removed 0 redundant assignments. 1953s Promoted 0 assignments to connections. 1953s 1953s 3.3.4. Executing PROC_INIT pass (extract init attributes). 1953s 1953s 3.3.5. Executing PROC_ARST pass (detect async resets in processes). 1953s 1953s 3.3.6. Executing PROC_ROM pass (convert switches to ROMs). 1953s Converted 0 switches. 1953s 1953s 3.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1953s 1953s 3.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1953s 1953s 3.3.9. Executing PROC_DFF pass (convert process syncs to FFs). 1953s 1953s 3.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1953s 1953s 3.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1953s Cleaned up 0 empty switches. 1953s 1953s 3.3.12. Executing OPT_EXPR pass (perform const folding). 1953s Optimizing module top. 1953s 1953s 1953s 1953s End of script. Logfile hash: 03fe26efda, CPU: user 0.01s system 0.00s, MEM: 10.16 MB peak 1953s Yosys 0.33 (git sha1 2584903a060) 1953s Time spent: 29% 2x opt_expr (0 sec), 19% 1x clean (0 sec), ... 1954s + ./yosys-always_comb 1954s + iverilog -o iverilog-always_comb always_comb.v always_comb_tb.v 1954s + ./iverilog-always_comb 1954s + grep -v '\$finish called' 1954s + diff iverilog-always_comb.log yosys-always_comb.log 1954s + ../../yosys -p 'read_verilog always_full.v; prep; clean' -o yosys-always_full-1.v 1954s 1954s /----------------------------------------------------------------------------\ 1954s | | 1954s | yosys -- Yosys Open SYnthesis Suite | 1954s | | 1954s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1954s | | 1954s | Permission to use, copy, modify, and/or distribute this software for any | 1954s | purpose with or without fee is hereby granted, provided that the above | 1954s | copyright notice and this permission notice appear in all copies. | 1954s | | 1954s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1954s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1954s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1954s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1954s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1954s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1954s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1954s | | 1954s \----------------------------------------------------------------------------/ 1954s 1954s Yosys 0.33 (git sha1 2584903a060) 1954s 1954s 1954s -- Running command `read_verilog always_full.v; prep; clean' -- 1954s 1954s 1. Executing Verilog-2005 frontend: always_full.v 1954s Parsing Verilog input from `always_full.v' to AST representation. 1954s Generating RTLIL representation for module `\always_full'. 1954s Successfully finished Verilog frontend. 1954s 1954s 2. Executing PREP pass. 1954s 1954s 2.1. Executing HIERARCHY pass (managing design hierarchy). 1954s 1954s 2.2. Executing PROC pass (convert processes to netlists). 1954s 1954s 2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1954s Cleaned up 0 empty switches. 1954s 1954s 2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1954s Removed a total of 0 dead cases. 1954s 1954s 2.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1954s Removed 207 redundant assignments. 1954s Promoted 207 assignments to connections. 1954s 1954s 2.2.4. Executing PROC_INIT pass (extract init attributes). 1954s 1954s 2.2.5. Executing PROC_ARST pass (detect async resets in processes). 1954s 1954s 2.2.6. Executing PROC_ROM pass (convert switches to ROMs). 1954s Converted 0 switches. 1954s 1954s 2.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1954s Creating decoders for process `\always_full.$proc$always_full.v:3$1'. 1954s 1954s 2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1954s 1954s 2.2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1954s 1954s 2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1954s 1954s 2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1954s Removing empty process `always_full.$proc$always_full.v:3$1'. 1954s Cleaned up 0 empty switches. 1954s 1954s 2.2.12. Executing OPT_EXPR pass (perform const folding). 1954s Optimizing module always_full. 1954s 1954s 2.3. Executing OPT_EXPR pass (perform const folding). 1954s Optimizing module always_full. 1954s 1954s 2.4. Executing OPT_CLEAN pass (remove unused cells and wires). 1954s Finding unused cells or wires in module \always_full.. 1954s Removed 0 unused cells and 207 unused wires. 1954s 1954s 1954s 2.5. Executing CHECK pass (checking for obvious problems). 1954s Checking module always_full... 1954s Found and reported 0 problems. 1954s 1954s 2.6. Executing OPT pass (performing simple optimizations). 1954s 1954s 2.6.1. Executing OPT_EXPR pass (perform const folding). 1954s Optimizing module always_full. 1954s 1954s 2.6.2. Executing OPT_MERGE pass (detect identical cells). 1954s Finding identical cells in module `\always_full'. 1954s Removed a total of 0 cells. 1954s 1954s 2.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 1954s Running muxtree optimizer on module \always_full.. 1954s Creating internal representation of mux trees. 1954s No muxes found in this module. 1954s Removed 0 multiplexer ports. 1954s 1954s 2.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 1954s Optimizing cells in module \always_full. 1954s Performed a total of 0 changes. 1954s 1954s 2.6.5. Executing OPT_MERGE pass (detect identical cells). 1954s Finding identical cells in module `\always_full'. 1954s Removed a total of 0 cells. 1954s 1954s 2.6.6. Executing OPT_CLEAN pass (remove unused cells and wires). 1954s Finding unused cells or wires in module \always_full.. 1954s 1954s 2.6.7. Executing OPT_EXPR pass (perform const folding). 1954s Optimizing module always_full. 1954s 1954s 2.6.8. Finished OPT passes. (There is nothing left to do.) 1954s 1954s 2.7. Executing WREDUCE pass (reducing word size of cells). 1954s 1954s 2.8. Executing OPT_CLEAN pass (remove unused cells and wires). 1954s Finding unused cells or wires in module \always_full.. 1954s 1954s 2.9. Executing MEMORY_COLLECT pass (generating $mem cells). 1954s 1954s 2.10. Executing OPT pass (performing simple optimizations). 1954s 1954s 2.10.1. Executing OPT_EXPR pass (perform const folding). 1954s Optimizing module always_full. 1954s 1954s 2.10.2. Executing OPT_MERGE pass (detect identical cells). 1954s Finding identical cells in module `\always_full'. 1954s Removed a total of 0 cells. 1954s 1954s 2.10.3. Executing OPT_CLEAN pass (remove unused cells and wires). 1954s Finding unused cells or wires in module \always_full.. 1954s 1954s 2.10.4. Finished fast OPT passes. 1954s 1954s 2.11. Printing statistics. 1954s 1954s === always_full === 1954s 1954s Number of wires: 1 1954s Number of wire bits: 1 1954s Number of public wires: 1 1954s Number of public wire bits: 1 1954s Number of memories: 0 1954s Number of memory bits: 0 1954s Number of processes: 0 1954s Number of cells: 207 1954s $print 207 1954s 1954s 2.12. Executing CHECK pass (checking for obvious problems). 1954s Checking module always_full... 1954s Found and reported 0 problems. 1954s 1954s -- Writing to `yosys-always_full-1.v' using backend `verilog' -- 1954s 1954s 3. Executing Verilog backend. 1954s 1954s 3.1. Executing BMUXMAP pass. 1954s 1954s 3.2. Executing DEMUXMAP pass. 1954s Dumping module `\always_full'. 1954s 1954s End of script. Logfile hash: cfd5b76053, CPU: user 0.06s system 0.00s, MEM: 10.91 MB peak 1954s Yosys 0.33 (git sha1 2584903a060) 1954s Time spent: 20% 4x opt_clean (0 sec), 20% 5x opt_expr (0 sec), ... 1954s + iverilog -o iverilog-always_full-1 yosys-always_full-1.v always_full_tb.v 1954s + ./iverilog-always_full-1 1954s + grep -v '\$finish called' 1954s + diff iverilog-always_full.log iverilog-always_full-1.log 1954s + ../../yosys -p 'read_verilog display_lm.v' 1954s + ../../yosys -p 'read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc' 1954s 1954s /----------------------------------------------------------------------------\ 1954s | | 1954s | yosys -- Yosys Open SYnthesis Suite | 1954s | | 1954s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1954s | | 1954s | Permission to use, copy, modify, and/or distribute this software for any | 1954s | purpose with or without fee is hereby granted, provided that the above | 1954s | copyright notice and this permission notice appear in all copies. | 1954s | | 1954s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1954s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1954s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1954s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1954s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1954s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1954s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1954s | | 1954s \----------------------------------------------------------------------------/ 1954s 1954s Yosys 0.33 (git sha1 2584903a060) 1954s 1954s 1954s -- Running command `read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc' -- 1954s 1954s 1. Executing Verilog-2005 frontend: display_lm.v 1954s Parsing Verilog input from `display_lm.v' to AST representation. 1954s Generating RTLIL representation for module `\top'. 1954s Generating RTLIL representation for module `\mid'. 1954s Generating RTLIL representation for module `\bot'. 1954s %l: \bot 1954s %m: \bot 1954s Successfully finished Verilog frontend. 1954s 1954s 2. Executing CXXRTL backend. 1954s 1954s 2.1. Executing HIERARCHY pass (managing design hierarchy). 1954s 1954s 2.1.1. Finding top of design hierarchy.. 1954s root of 0 design levels: bot 1954s root of 1 design levels: mid 1954s root of 2 design levels: top 1954s Automatically selected top as design top module. 1954s 1954s 2.1.2. Analyzing design hierarchy.. 1954s Top module: \top 1954s Used module: \mid 1954s Used module: \bot 1954s 1954s 2.1.3. Analyzing design hierarchy.. 1954s Top module: \top 1954s Used module: \mid 1954s Used module: \bot 1954s Removed 0 unused modules. 1954s 1954s 2.2. Executing FLATTEN pass (flatten design). 1954s Deleting now unused module bot. 1954s Deleting now unused module mid. 1954s 1954s 1954s 2.3. Executing PROC pass (convert processes to netlists). 1954s + gcc -std=c++11 -o yosys-display_lm_cc -I../.. display_lm_tb.cc -lstdc++ 1954s 1954s 2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1954s Removing empty process `top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:0$3'. 1954s Cleaned up 0 empty switches. 1954s 1954s 2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1954s Removed a total of 0 dead cases. 1954s 1954s 2.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1954s Removed 1 redundant assignment. 1954s Promoted 1 assignment to connection. 1954s 1954s 2.3.4. Executing PROC_INIT pass (extract init attributes). 1954s 1954s 2.3.5. Executing PROC_ARST pass (detect async resets in processes). 1954s 1954s 2.3.6. Executing PROC_ROM pass (convert switches to ROMs). 1954s Converted 0 switches. 1954s 1954s 2.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1954s Creating decoders for process `\top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:11$1'. 1954s 1954s 2.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1954s 1954s 2.3.9. Executing PROC_DFF pass (convert process syncs to FFs). 1954s 1954s 2.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1954s 1954s 2.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1954s Removing empty process `top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:11$1'. 1954s Cleaned up 0 empty switches. 1954s 1954s 2.3.12. Executing OPT_EXPR pass (perform const folding). 1954s Optimizing module top. 1954s 1954s 1954s 1954s End of script. Logfile hash: 1b689717a7, CPU: user 0.01s system 0.00s, MEM: 9.78 MB peak 1954s Yosys 0.33 (git sha1 2584903a060) 1954s Time spent: 36% 1x opt_expr (0 sec), 16% 2x read_verilog (0 sec), ... 1954s + ./yosys-display_lm_cc 1954s + for log in yosys-display_lm.log yosys-display_lm_cc.log 1954s + grep '^%l: \\bot$' yosys-display_lm.log 1954s + grep '^%m: \\bot$' yosys-display_lm.log 1954s + for log in yosys-display_lm.log yosys-display_lm_cc.log 1954s + grep '^%l: \\bot$' yosys-display_lm_cc.log 1954s %l: \bot 1954s %m: \bot 1954s + grep '^%m: \\bot$' yosys-display_lm_cc.log 1954s %l: \bot 1954s %m: \bot 1954s 1954s Passed "make test". 1954s 1955s autopkgtest [22:51:06]: test yosys-testsuite: -----------------------] 1955s yosys-testsuite PASS 1955s autopkgtest [22:51:06]: test yosys-testsuite: - - - - - - - - - - results - - - - - - - - - - 1956s autopkgtest [22:51:07]: test ice: preparing testbed 2083s autopkgtest [22:53:14]: testbed dpkg architecture: arm64 2083s autopkgtest [22:53:14]: testbed apt version: 3.0.0 2084s autopkgtest [22:53:15]: @@@@@@@@@@@@@@@@@@@@ test bed setup 2084s autopkgtest [22:53:15]: testbed release detected to be: questing 2085s autopkgtest [22:53:16]: updating testbed package index (apt update) 2085s Get:1 http://ftpmaster.internal/ubuntu questing-proposed InRelease [110 kB] 2085s Hit:2 http://ftpmaster.internal/ubuntu questing InRelease 2085s Hit:3 http://ftpmaster.internal/ubuntu questing-updates InRelease 2085s Hit:4 http://ftpmaster.internal/ubuntu questing-security InRelease 2085s Get:5 http://ftpmaster.internal/ubuntu questing-proposed/universe Sources [818 kB] 2086s Get:6 http://ftpmaster.internal/ubuntu questing-proposed/main Sources [86.1 kB] 2086s Get:7 http://ftpmaster.internal/ubuntu questing-proposed/multiverse Sources [30.0 kB] 2086s Get:8 http://ftpmaster.internal/ubuntu questing-proposed/main arm64 Packages [116 kB] 2086s Get:9 http://ftpmaster.internal/ubuntu questing-proposed/universe arm64 Packages [892 kB] 2086s Get:10 http://ftpmaster.internal/ubuntu questing-proposed/multiverse arm64 Packages [18.0 kB] 2086s Fetched 2070 kB in 1s (2083 kB/s) 2087s Reading package lists... 2087s autopkgtest [22:53:18]: upgrading testbed (apt dist-upgrade and autopurge) 2088s Reading package lists... 2088s Building dependency tree... 2088s Reading state information... 2088s Calculating upgrade...Starting pkgProblemResolver with broken count: 0 2089s Starting 2 pkgProblemResolver with broken count: 0 2089s Done 2089s Entering ResolveByKeep 2090s 2090s Calculating upgrade... 2090s The following package was automatically installed and is no longer required: 2090s libsigsegv2 2090s Use 'sudo apt autoremove' to remove it. 2090s The following packages will be upgraded: 2090s dhcpcd-base dirmngr gawk gir1.2-glib-2.0 gnupg gnupg-l10n gnupg-utils gpg 2090s gpg-agent gpg-wks-client gpgconf gpgsm gpgv keyboxd libglib2.0-0t64 2090s libglib2.0-data libnuma1 libpython3.12-minimal libpython3.12-stdlib 2090s libpython3.12t64 libx11-6 libx11-data libxml2 numactl openssh-client 2090s openssh-server openssh-sftp-server python3-wadllib 2090s 28 upgraded, 0 newly installed, 0 to remove and 0 not upgraded. 2090s Need to get 13.1 MB of archives. 2090s After this operation, 81.9 kB disk space will be freed. 2090s Get:1 http://ftpmaster.internal/ubuntu questing-proposed/main arm64 gawk arm64 1:5.3.2-1 [504 kB] 2091s Get:2 http://ftpmaster.internal/ubuntu questing/main arm64 openssh-sftp-server arm64 1:9.9p1-3ubuntu3.1 [36.9 kB] 2091s Get:3 http://ftpmaster.internal/ubuntu questing/main arm64 openssh-server arm64 1:9.9p1-3ubuntu3.1 [524 kB] 2091s Get:4 http://ftpmaster.internal/ubuntu questing/main arm64 openssh-client arm64 1:9.9p1-3ubuntu3.1 [922 kB] 2091s Get:5 http://ftpmaster.internal/ubuntu questing/main arm64 gpg-wks-client arm64 2.4.4-2ubuntu24 [70.3 kB] 2091s Get:6 http://ftpmaster.internal/ubuntu questing/main arm64 dirmngr arm64 2.4.4-2ubuntu24 [321 kB] 2091s Get:7 http://ftpmaster.internal/ubuntu questing/main arm64 gpgsm arm64 2.4.4-2ubuntu24 [228 kB] 2091s Get:8 http://ftpmaster.internal/ubuntu questing/main arm64 gnupg-utils arm64 2.4.4-2ubuntu24 [107 kB] 2091s Get:9 http://ftpmaster.internal/ubuntu questing/main arm64 gpg-agent arm64 2.4.4-2ubuntu24 [224 kB] 2091s Get:10 http://ftpmaster.internal/ubuntu questing/main arm64 gpg arm64 2.4.4-2ubuntu24 [555 kB] 2091s Get:11 http://ftpmaster.internal/ubuntu questing/main arm64 gpgconf arm64 2.4.4-2ubuntu24 [104 kB] 2091s Get:12 http://ftpmaster.internal/ubuntu questing/main arm64 gnupg all 2.4.4-2ubuntu24 [359 kB] 2091s Get:13 http://ftpmaster.internal/ubuntu questing/main arm64 keyboxd arm64 2.4.4-2ubuntu24 [76.1 kB] 2091s Get:14 http://ftpmaster.internal/ubuntu questing/main arm64 gpgv arm64 2.4.4-2ubuntu24 [154 kB] 2091s Get:15 http://ftpmaster.internal/ubuntu questing/main arm64 dhcpcd-base arm64 1:10.1.0-10 [216 kB] 2091s Get:16 http://ftpmaster.internal/ubuntu questing/main arm64 gir1.2-glib-2.0 arm64 2.84.1-2 [185 kB] 2091s Get:17 http://ftpmaster.internal/ubuntu questing/main arm64 libglib2.0-0t64 arm64 2.84.1-2 [1572 kB] 2091s Get:18 http://ftpmaster.internal/ubuntu questing/main arm64 libglib2.0-data all 2.84.1-2 [53.2 kB] 2091s Get:19 http://ftpmaster.internal/ubuntu questing/main arm64 libxml2 arm64 2.12.7+dfsg+really2.9.14-0.4ubuntu0.1 [736 kB] 2091s Get:20 http://ftpmaster.internal/ubuntu questing/main arm64 libnuma1 arm64 2.0.19-1 [23.9 kB] 2091s Get:21 http://ftpmaster.internal/ubuntu questing/main arm64 libx11-data all 2:1.8.12-1 [116 kB] 2091s Get:22 http://ftpmaster.internal/ubuntu questing/main arm64 libx11-6 arm64 2:1.8.12-1 [651 kB] 2091s Get:23 http://ftpmaster.internal/ubuntu questing/main arm64 numactl arm64 2.0.19-1 [39.2 kB] 2091s Get:24 http://ftpmaster.internal/ubuntu questing/main arm64 gnupg-l10n all 2.4.4-2ubuntu24 [66.8 kB] 2091s Get:25 http://ftpmaster.internal/ubuntu questing-proposed/universe arm64 libpython3.12t64 arm64 3.12.10-1 [2314 kB] 2091s Get:26 http://ftpmaster.internal/ubuntu questing-proposed/universe arm64 libpython3.12-stdlib arm64 3.12.10-1 [2029 kB] 2091s Get:27 http://ftpmaster.internal/ubuntu questing-proposed/universe arm64 libpython3.12-minimal arm64 3.12.10-1 [836 kB] 2092s Get:28 http://ftpmaster.internal/ubuntu questing/main arm64 python3-wadllib all 2.0.0-3 [36.3 kB] 2092s Preconfiguring packages ... 2092s Fetched 13.1 MB in 1s (11.0 MB/s) 2092s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 117830 files and directories currently installed.) 2092s Preparing to unpack .../00-gawk_1%3a5.3.2-1_arm64.deb ... 2092s Unpacking gawk (1:5.3.2-1) over (1:5.2.1-2build3) ... 2093s Preparing to unpack .../01-openssh-sftp-server_1%3a9.9p1-3ubuntu3.1_arm64.deb ... 2093s Unpacking openssh-sftp-server (1:9.9p1-3ubuntu3.1) over (1:9.9p1-3ubuntu3) ... 2093s Preparing to unpack .../02-openssh-server_1%3a9.9p1-3ubuntu3.1_arm64.deb ... 2093s Unpacking openssh-server (1:9.9p1-3ubuntu3.1) over (1:9.9p1-3ubuntu3) ... 2093s Preparing to unpack .../03-openssh-client_1%3a9.9p1-3ubuntu3.1_arm64.deb ... 2093s Unpacking openssh-client (1:9.9p1-3ubuntu3.1) over (1:9.9p1-3ubuntu3) ... 2093s Preparing to unpack .../04-gpg-wks-client_2.4.4-2ubuntu24_arm64.deb ... 2093s Unpacking gpg-wks-client (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 2093s Preparing to unpack .../05-dirmngr_2.4.4-2ubuntu24_arm64.deb ... 2093s Unpacking dirmngr (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 2093s Preparing to unpack .../06-gpgsm_2.4.4-2ubuntu24_arm64.deb ... 2093s Unpacking gpgsm (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 2093s Preparing to unpack .../07-gnupg-utils_2.4.4-2ubuntu24_arm64.deb ... 2093s Unpacking gnupg-utils (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 2093s Preparing to unpack .../08-gpg-agent_2.4.4-2ubuntu24_arm64.deb ... 2093s Unpacking gpg-agent (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 2093s Preparing to unpack .../09-gpg_2.4.4-2ubuntu24_arm64.deb ... 2093s Unpacking gpg (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 2093s Preparing to unpack .../10-gpgconf_2.4.4-2ubuntu24_arm64.deb ... 2093s Unpacking gpgconf (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 2093s Preparing to unpack .../11-gnupg_2.4.4-2ubuntu24_all.deb ... 2093s Unpacking gnupg (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 2094s Preparing to unpack .../12-keyboxd_2.4.4-2ubuntu24_arm64.deb ... 2094s Unpacking keyboxd (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 2094s Preparing to unpack .../13-gpgv_2.4.4-2ubuntu24_arm64.deb ... 2094s Unpacking gpgv (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 2094s Setting up gpgv (2.4.4-2ubuntu24) ... 2094s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 117832 files and directories currently installed.) 2094s Preparing to unpack .../00-dhcpcd-base_1%3a10.1.0-10_arm64.deb ... 2094s Unpacking dhcpcd-base (1:10.1.0-10) over (1:10.1.0-8) ... 2094s Preparing to unpack .../01-gir1.2-glib-2.0_2.84.1-2_arm64.deb ... 2094s Unpacking gir1.2-glib-2.0:arm64 (2.84.1-2) over (2.84.1-1) ... 2094s Preparing to unpack .../02-libglib2.0-0t64_2.84.1-2_arm64.deb ... 2094s Unpacking libglib2.0-0t64:arm64 (2.84.1-2) over (2.84.1-1) ... 2094s Preparing to unpack .../03-libglib2.0-data_2.84.1-2_all.deb ... 2094s Unpacking libglib2.0-data (2.84.1-2) over (2.84.1-1) ... 2094s Preparing to unpack .../04-libxml2_2.12.7+dfsg+really2.9.14-0.4ubuntu0.1_arm64.deb ... 2094s Unpacking libxml2:arm64 (2.12.7+dfsg+really2.9.14-0.4ubuntu0.1) over (2.12.7+dfsg+really2.9.14-0.4) ... 2094s Preparing to unpack .../05-libnuma1_2.0.19-1_arm64.deb ... 2094s Unpacking libnuma1:arm64 (2.0.19-1) over (2.0.18-1build1) ... 2094s Preparing to unpack .../06-libx11-data_2%3a1.8.12-1_all.deb ... 2094s Unpacking libx11-data (2:1.8.12-1) over (2:1.8.10-2) ... 2094s Preparing to unpack .../07-libx11-6_2%3a1.8.12-1_arm64.deb ... 2094s Unpacking libx11-6:arm64 (2:1.8.12-1) over (2:1.8.10-2) ... 2094s Preparing to unpack .../08-numactl_2.0.19-1_arm64.deb ... 2094s Unpacking numactl (2.0.19-1) over (2.0.18-1build1) ... 2094s Preparing to unpack .../09-gnupg-l10n_2.4.4-2ubuntu24_all.deb ... 2094s Unpacking gnupg-l10n (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 2094s Preparing to unpack .../10-libpython3.12t64_3.12.10-1_arm64.deb ... 2094s Unpacking libpython3.12t64:arm64 (3.12.10-1) over (3.12.8-3) ... 2095s Preparing to unpack .../11-libpython3.12-stdlib_3.12.10-1_arm64.deb ... 2095s Unpacking libpython3.12-stdlib:arm64 (3.12.10-1) over (3.12.8-3) ... 2095s Preparing to unpack .../12-libpython3.12-minimal_3.12.10-1_arm64.deb ... 2095s Unpacking libpython3.12-minimal:arm64 (3.12.10-1) over (3.12.8-3) ... 2095s Preparing to unpack .../13-python3-wadllib_2.0.0-3_all.deb ... 2095s Unpacking python3-wadllib (2.0.0-3) over (2.0.0-2) ... 2095s Setting up gawk (1:5.3.2-1) ... 2095s Setting up openssh-client (1:9.9p1-3ubuntu3.1) ... 2095s Setting up libpython3.12-minimal:arm64 (3.12.10-1) ... 2095s Setting up libglib2.0-0t64:arm64 (2.84.1-2) ... 2095s No schema files found: doing nothing. 2095s Setting up libglib2.0-data (2.84.1-2) ... 2095s Setting up libx11-data (2:1.8.12-1) ... 2095s Setting up gnupg-l10n (2.4.4-2ubuntu24) ... 2095s Setting up python3-wadllib (2.0.0-3) ... 2095s Setting up dhcpcd-base (1:10.1.0-10) ... 2095s Installing new version of config file /etc/dhcpcd.conf ... 2095s Setting up gir1.2-glib-2.0:arm64 (2.84.1-2) ... 2095s Setting up libnuma1:arm64 (2.0.19-1) ... 2095s Setting up gpgconf (2.4.4-2ubuntu24) ... 2095s Setting up libx11-6:arm64 (2:1.8.12-1) ... 2095s Setting up libxml2:arm64 (2.12.7+dfsg+really2.9.14-0.4ubuntu0.1) ... 2095s Setting up gpg (2.4.4-2ubuntu24) ... 2095s Setting up gnupg-utils (2.4.4-2ubuntu24) ... 2095s Setting up openssh-sftp-server (1:9.9p1-3ubuntu3.1) ... 2095s Setting up gpg-agent (2.4.4-2ubuntu24) ... 2096s Setting up libpython3.12-stdlib:arm64 (3.12.10-1) ... 2096s Setting up numactl (2.0.19-1) ... 2096s Setting up openssh-server (1:9.9p1-3ubuntu3.1) ... 2097s Setting up gpgsm (2.4.4-2ubuntu24) ... 2097s Setting up libpython3.12t64:arm64 (3.12.10-1) ... 2097s Setting up dirmngr (2.4.4-2ubuntu24) ... 2097s Setting up keyboxd (2.4.4-2ubuntu24) ... 2098s Setting up gnupg (2.4.4-2ubuntu24) ... 2098s Setting up gpg-wks-client (2.4.4-2ubuntu24) ... 2098s Processing triggers for ufw (0.36.2-9) ... 2098s Processing triggers for man-db (2.13.1-1) ... 2099s Processing triggers for install-info (7.1.1-1) ... 2099s Processing triggers for libc-bin (2.41-6ubuntu1) ... 2100s Reading package lists... 2100s Building dependency tree... 2100s Reading state information... 2100s Starting pkgProblemResolver with broken count: 0 2100s Starting 2 pkgProblemResolver with broken count: 0 2100s Done 2101s Solving dependencies... 2101s The following packages will be REMOVED: 2101s libsigsegv2* 2102s 0 upgraded, 0 newly installed, 1 to remove and 0 not upgraded. 2102s After this operation, 97.3 kB disk space will be freed. 2102s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 117832 files and directories currently installed.) 2102s Removing libsigsegv2:arm64 (2.14-1ubuntu2) ... 2102s Processing triggers for libc-bin (2.41-6ubuntu1) ... 2102s autopkgtest [22:53:33]: rebooting testbed after setup commands that affected boot 2133s Reading package lists... 2133s Building dependency tree... 2133s Reading state information... 2133s Starting pkgProblemResolver with broken count: 0 2133s Starting 2 pkgProblemResolver with broken count: 0 2133s Done 2134s The following NEW packages will be installed: 2134s libtcl8.6 python3-click yosys yosys-abc 2134s 0 upgraded, 4 newly installed, 0 to remove and 0 not upgraded. 2134s Need to get 9770 kB of archives. 2134s After this operation, 32.3 MB of additional disk space will be used. 2134s Get:1 http://ftpmaster.internal/ubuntu questing/main arm64 libtcl8.6 arm64 8.6.16+dfsg-1 [987 kB] 2135s Get:2 http://ftpmaster.internal/ubuntu questing/main arm64 python3-click all 8.2.0+0.really.8.1.8-1 [80.0 kB] 2135s Get:3 http://ftpmaster.internal/ubuntu questing/universe arm64 yosys-abc arm64 0.33-5build2 [5605 kB] 2135s Get:4 http://ftpmaster.internal/ubuntu questing/universe arm64 yosys arm64 0.33-5build2 [3098 kB] 2135s Fetched 9770 kB in 1s (10.9 MB/s) 2135s Selecting previously unselected package libtcl8.6:arm64. 2136s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 117825 files and directories currently installed.) 2136s Preparing to unpack .../libtcl8.6_8.6.16+dfsg-1_arm64.deb ... 2136s Unpacking libtcl8.6:arm64 (8.6.16+dfsg-1) ... 2136s Selecting previously unselected package python3-click. 2136s Preparing to unpack .../python3-click_8.2.0+0.really.8.1.8-1_all.deb ... 2136s Unpacking python3-click (8.2.0+0.really.8.1.8-1) ... 2136s Selecting previously unselected package yosys-abc. 2136s Preparing to unpack .../yosys-abc_0.33-5build2_arm64.deb ... 2136s Unpacking yosys-abc (0.33-5build2) ... 2136s Selecting previously unselected package yosys. 2136s Preparing to unpack .../yosys_0.33-5build2_arm64.deb ... 2136s Unpacking yosys (0.33-5build2) ... 2136s Setting up yosys-abc (0.33-5build2) ... 2136s Setting up python3-click (8.2.0+0.really.8.1.8-1) ... 2136s Setting up libtcl8.6:arm64 (8.6.16+dfsg-1) ... 2136s Setting up yosys (0.33-5build2) ... 2136s Processing triggers for libc-bin (2.41-6ubuntu1) ... 2136s Processing triggers for man-db (2.13.1-1) ... 2148s autopkgtest [22:54:19]: test ice: [----------------------- 2148s 2148s /----------------------------------------------------------------------------\ 2148s | | 2148s | yosys -- Yosys Open SYnthesis Suite | 2148s | | 2148s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2148s | | 2148s | Permission to use, copy, modify, and/or distribute this software for any | 2148s | purpose with or without fee is hereby granted, provided that the above | 2148s | copyright notice and this permission notice appear in all copies. | 2148s | | 2148s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2148s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2148s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2148s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2148s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2148s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2148s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2148s | | 2148s \----------------------------------------------------------------------------/ 2148s 2148s Yosys 0.33 (git sha1 2584903a060) 2148s 2148s 2148s -- Running command `read_verilog debian/tests/design_ice.v; synth_ice40 -blif /tmp/autopkgtest.ldz5d8/autopkgtest_tmp/design_ice.blif' -- 2148s 2148s 1. Executing Verilog-2005 frontend: debian/tests/design_ice.v 2148s Parsing Verilog input from `debian/tests/design_ice.v' to AST representation. 2148s Generating RTLIL representation for module `\design_ice'. 2148s Successfully finished Verilog frontend. 2148s 2148s 2. Executing SYNTH_ICE40 pass. 2148s 2148s 2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v 2148s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation. 2148s Generating RTLIL representation for module `\SB_IO'. 2148s Generating RTLIL representation for module `\SB_GB_IO'. 2148s Generating RTLIL representation for module `\SB_GB'. 2148s Generating RTLIL representation for module `\SB_LUT4'. 2148s Generating RTLIL representation for module `\SB_CARRY'. 2148s Generating RTLIL representation for module `\SB_DFF'. 2148s Generating RTLIL representation for module `\SB_DFFE'. 2148s Generating RTLIL representation for module `\SB_DFFSR'. 2148s Generating RTLIL representation for module `\SB_DFFR'. 2148s Generating RTLIL representation for module `\SB_DFFSS'. 2148s Generating RTLIL representation for module `\SB_DFFS'. 2148s Generating RTLIL representation for module `\SB_DFFESR'. 2148s Generating RTLIL representation for module `\SB_DFFER'. 2148s Generating RTLIL representation for module `\SB_DFFESS'. 2148s Generating RTLIL representation for module `\SB_DFFES'. 2148s Generating RTLIL representation for module `\SB_DFFN'. 2148s Generating RTLIL representation for module `\SB_DFFNE'. 2148s Generating RTLIL representation for module `\SB_DFFNSR'. 2148s Generating RTLIL representation for module `\SB_DFFNR'. 2148s Generating RTLIL representation for module `\SB_DFFNSS'. 2148s Generating RTLIL representation for module `\SB_DFFNS'. 2148s Generating RTLIL representation for module `\SB_DFFNESR'. 2148s Generating RTLIL representation for module `\SB_DFFNER'. 2148s Generating RTLIL representation for module `\SB_DFFNESS'. 2148s Generating RTLIL representation for module `\SB_DFFNES'. 2148s Generating RTLIL representation for module `\SB_RAM40_4K'. 2148s Generating RTLIL representation for module `\SB_RAM40_4KNR'. 2148s Generating RTLIL representation for module `\SB_RAM40_4KNW'. 2148s Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. 2148s Generating RTLIL representation for module `\ICESTORM_LC'. 2148s Generating RTLIL representation for module `\SB_PLL40_CORE'. 2148s Generating RTLIL representation for module `\SB_PLL40_PAD'. 2148s Generating RTLIL representation for module `\SB_PLL40_2_PAD'. 2148s Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. 2148s Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. 2148s Generating RTLIL representation for module `\SB_WARMBOOT'. 2148s Generating RTLIL representation for module `\SB_SPRAM256KA'. 2148s Generating RTLIL representation for module `\SB_HFOSC'. 2148s Generating RTLIL representation for module `\SB_LFOSC'. 2148s Generating RTLIL representation for module `\SB_RGBA_DRV'. 2148s Generating RTLIL representation for module `\SB_LED_DRV_CUR'. 2148s Generating RTLIL representation for module `\SB_RGB_DRV'. 2148s Generating RTLIL representation for module `\SB_I2C'. 2148s Generating RTLIL representation for module `\SB_SPI'. 2148s Generating RTLIL representation for module `\SB_LEDDA_IP'. 2148s Generating RTLIL representation for module `\SB_FILTER_50NS'. 2148s Generating RTLIL representation for module `\SB_IO_I3C'. 2148s Generating RTLIL representation for module `\SB_IO_OD'. 2148s Generating RTLIL representation for module `\SB_MAC16'. 2148s Generating RTLIL representation for module `\ICESTORM_RAM'. 2148s Successfully finished Verilog frontend. 2148s 2148s 2.2. Executing HIERARCHY pass (managing design hierarchy). 2148s 2148s 2.2.1. Finding top of design hierarchy.. 2148s root of 0 design levels: design_ice 2148s Automatically selected design_ice as design top module. 2148s 2148s 2.2.2. Analyzing design hierarchy.. 2148s Top module: \design_ice 2148s 2148s 2.2.3. Analyzing design hierarchy.. 2148s Top module: \design_ice 2148s Removed 0 unused modules. 2148s 2148s 2.3. Executing PROC pass (convert processes to netlists). 2148s 2148s 2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2148s Cleaned up 0 empty switches. 2148s 2148s 2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2148s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243 in module SB_DFFNES. 2148s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236 in module SB_DFFNESS. 2148s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232 in module SB_DFFNER. 2148s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225 in module SB_DFFNESR. 2148s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222 in module SB_DFFNS. 2148s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219 in module SB_DFFNSS. 2148s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216 in module SB_DFFNR. 2148s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213 in module SB_DFFNSR. 2148s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205 in module SB_DFFES. 2148s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198 in module SB_DFFESS. 2148s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194 in module SB_DFFER. 2148s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187 in module SB_DFFESR. 2148s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184 in module SB_DFFS. 2148s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181 in module SB_DFFSS. 2148s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178 in module SB_DFFR. 2148s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175 in module SB_DFFSR. 2148s Marked 1 switch rules as full_case in process $proc$debian/tests/design_ice.v:6$1 in module design_ice. 2148s Removed a total of 0 dead cases. 2148s 2148s 2.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2148s Removed 8 redundant assignments. 2148s Promoted 23 assignments to connections. 2148s 2148s 2.3.4. Executing PROC_INIT pass (extract init attributes). 2148s Found init rule in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$246'. 2148s Set init value: \Q = 1'0 2148s Found init rule in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$242'. 2148s Set init value: \Q = 1'0 2148s Found init rule in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$235'. 2148s Set init value: \Q = 1'0 2148s Found init rule in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$231'. 2148s Set init value: \Q = 1'0 2148s Found init rule in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$224'. 2148s Set init value: \Q = 1'0 2148s Found init rule in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$221'. 2148s Set init value: \Q = 1'0 2148s Found init rule in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$218'. 2148s Set init value: \Q = 1'0 2148s Found init rule in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$215'. 2148s Set init value: \Q = 1'0 2148s Found init rule in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$212'. 2148s Set init value: \Q = 1'0 2148s Found init rule in `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 2148s Set init value: \Q = 1'0 2148s Found init rule in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 2148s Set init value: \Q = 1'0 2148s Found init rule in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$204'. 2148s Set init value: \Q = 1'0 2148s Found init rule in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$197'. 2148s Set init value: \Q = 1'0 2148s Found init rule in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$193'. 2148s Set init value: \Q = 1'0 2148s Found init rule in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$186'. 2148s Set init value: \Q = 1'0 2148s Found init rule in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$183'. 2148s Set init value: \Q = 1'0 2148s Found init rule in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$180'. 2148s Set init value: \Q = 1'0 2148s Found init rule in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$177'. 2148s Set init value: \Q = 1'0 2148s Found init rule in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$174'. 2148s Set init value: \Q = 1'0 2148s Found init rule in `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 2148s Set init value: \Q = 1'0 2148s Found init rule in `\design_ice.$proc$debian/tests/design_ice.v:3$2'. 2148s Set init value: \ready = 1'0 2148s 2148s 2.3.5. Executing PROC_ARST pass (detect async resets in processes). 2148s Found async reset \S in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'. 2148s Found async reset \R in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'. 2148s Found async reset \S in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222'. 2148s Found async reset \R in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216'. 2148s Found async reset \S in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'. 2148s Found async reset \R in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'. 2148s Found async reset \S in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184'. 2148s Found async reset \R in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178'. 2148s 2148s 2.3.6. Executing PROC_ROM pass (convert switches to ROMs). 2148s Converted 0 switches. 2148s 2148s 2148s 2.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2148s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$246'. 2148s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'. 2148s 1/1: $0\Q[0:0] 2148s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$242'. 2148s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236'. 2148s 1/1: $0\Q[0:0] 2148s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$235'. 2148s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'. 2148s 1/1: $0\Q[0:0] 2148s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$231'. 2148s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225'. 2148s 1/1: $0\Q[0:0] 2148s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$224'. 2148s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222'. 2148s 1/1: $0\Q[0:0] 2148s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$221'. 2148s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219'. 2148s 1/1: $0\Q[0:0] 2148s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$218'. 2148s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216'. 2148s 1/1: $0\Q[0:0] 2148s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$215'. 2148s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213'. 2148s 1/1: $0\Q[0:0] 2148s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$212'. 2148s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$211'. 2148s 1/1: $0\Q[0:0] 2148s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 2148s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$209'. 2148s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 2148s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'. 2148s 1/1: $0\Q[0:0] 2148s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$204'. 2148s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198'. 2148s 1/1: $0\Q[0:0] 2148s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$197'. 2148s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'. 2148s 1/1: $0\Q[0:0] 2148s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$193'. 2148s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187'. 2148s 1/1: $0\Q[0:0] 2148s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$186'. 2148s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184'. 2148s 1/1: $0\Q[0:0] 2148s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$183'. 2148s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181'. 2148s 1/1: $0\Q[0:0] 2148s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$180'. 2148s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178'. 2148s 1/1: $0\Q[0:0] 2148s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$177'. 2148s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175'. 2148s 1/1: $0\Q[0:0] 2148s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$174'. 2148s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$173'. 2148s 1/1: $0\Q[0:0] 2148s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 2148s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$171'. 2148s Creating decoders for process `\design_ice.$proc$debian/tests/design_ice.v:3$2'. 2148s Creating decoders for process `\design_ice.$proc$debian/tests/design_ice.v:6$1'. 2148s 1/2: $0\value[0:0] 2148s 2/2: $0\ready[0:0] 2148s 2148s 2.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2148s 2148s 2.3.9. Executing PROC_DFF pass (convert process syncs to FFs). 2148s Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'. 2148s created $adff cell `$procdff$433' with negative edge clock and positive level reset. 2148s Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236'. 2148s created $dff cell `$procdff$434' with negative edge clock. 2148s Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'. 2148s created $adff cell `$procdff$435' with negative edge clock and positive level reset. 2148s Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225'. 2148s created $dff cell `$procdff$436' with negative edge clock. 2148s Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222'. 2148s created $adff cell `$procdff$437' with negative edge clock and positive level reset. 2148s Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219'. 2148s created $dff cell `$procdff$438' with negative edge clock. 2148s Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216'. 2148s created $adff cell `$procdff$439' with negative edge clock and positive level reset. 2148s Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213'. 2148s created $dff cell `$procdff$440' with negative edge clock. 2148s Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$211'. 2148s created $dff cell `$procdff$441' with negative edge clock. 2148s Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$209'. 2148s created $dff cell `$procdff$442' with negative edge clock. 2148s Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'. 2148s created $adff cell `$procdff$443' with positive edge clock and positive level reset. 2148s Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198'. 2148s created $dff cell `$procdff$444' with positive edge clock. 2148s Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'. 2148s created $adff cell `$procdff$445' with positive edge clock and positive level reset. 2148s Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187'. 2148s created $dff cell `$procdff$446' with positive edge clock. 2148s Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184'. 2148s created $adff cell `$procdff$447' with positive edge clock and positive level reset. 2148s Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181'. 2148s created $dff cell `$procdff$448' with positive edge clock. 2148s Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178'. 2148s created $adff cell `$procdff$449' with positive edge clock and positive level reset. 2148s Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175'. 2148s created $dff cell `$procdff$450' with positive edge clock. 2148s Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$173'. 2148s created $dff cell `$procdff$451' with positive edge clock. 2148s Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$171'. 2148s created $dff cell `$procdff$452' with positive edge clock. 2148s Creating register for signal `\design_ice.\ready' using process `\design_ice.$proc$debian/tests/design_ice.v:6$1'. 2148s created $dff cell `$procdff$453' with positive edge clock. 2148s Creating register for signal `\design_ice.\value' using process `\design_ice.$proc$debian/tests/design_ice.v:6$1'. 2148s created $dff cell `$procdff$454' with positive edge clock. 2148s 2148s 2.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2148s 2148s 2.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2148s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$246'. 2148s Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'. 2148s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'. 2148s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$242'. 2148s Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236'. 2148s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236'. 2148s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$235'. 2148s Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'. 2148s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'. 2148s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$231'. 2148s Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225'. 2148s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225'. 2148s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$224'. 2148s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222'. 2148s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$221'. 2148s Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219'. 2148s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219'. 2148s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$218'. 2148s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216'. 2148s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$215'. 2148s Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213'. 2148s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213'. 2148s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$212'. 2148s Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$211'. 2148s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$211'. 2148s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 2148s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$209'. 2148s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 2148s Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'. 2148s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'. 2148s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$204'. 2148s Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198'. 2148s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198'. 2148s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$197'. 2148s Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'. 2148s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'. 2148s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$193'. 2148s Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187'. 2148s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187'. 2148s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$186'. 2148s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184'. 2148s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$183'. 2148s Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181'. 2148s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181'. 2148s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$180'. 2148s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178'. 2148s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$177'. 2148s Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175'. 2148s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175'. 2148s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$174'. 2148s Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$173'. 2148s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$173'. 2148s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 2148s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$171'. 2148s Removing empty process `design_ice.$proc$debian/tests/design_ice.v:3$2'. 2148s Found and cleaned up 1 empty switch in `\design_ice.$proc$debian/tests/design_ice.v:6$1'. 2148s Removing empty process `design_ice.$proc$debian/tests/design_ice.v:6$1'. 2148s Cleaned up 19 empty switches. 2148s 2148s 2.3.12. Executing OPT_EXPR pass (perform const folding). 2148s Optimizing module design_ice. 2148s 2148s 2.4. Executing FLATTEN pass (flatten design). 2148s 2148s 2.5. Executing TRIBUF pass. 2148s 2148s 2.6. Executing DEMINOUT pass (demote inout ports to input or output). 2148s 2148s 2.7. Executing OPT_EXPR pass (perform const folding). 2148s Optimizing module design_ice. 2148s 2148s 2.8. Executing OPT_CLEAN pass (remove unused cells and wires). 2148s Finding unused cells or wires in module \design_ice.. 2148s Removed 0 unused cells and 5 unused wires. 2148s 2148s 2148s 2.9. Executing CHECK pass (checking for obvious problems). 2148s Checking module design_ice... 2148s Found and reported 0 problems. 2148s 2148s 2.10. Executing OPT pass (performing simple optimizations). 2148s 2148s 2.10.1. Executing OPT_EXPR pass (perform const folding). 2148s Optimizing module design_ice. 2148s 2148s 2.10.2. Executing OPT_MERGE pass (detect identical cells). 2148s Finding identical cells in module `\design_ice'. 2148s Removed a total of 0 cells. 2148s 2148s 2.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 2148s Running muxtree optimizer on module \design_ice.. 2148s Creating internal representation of mux trees. 2148s Evaluating internal representation of mux trees. 2148s Replacing known input bits on port B of cell $procmux$431: \ready -> 1'1 2148s Analyzing evaluation results. 2148s Removed 0 multiplexer ports. 2148s 2148s 2148s 2.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 2148s Optimizing cells in module \design_ice. 2148s Optimizing cells in module \design_ice. 2148s Performed a total of 1 changes. 2148s 2148s 2.10.5. Executing OPT_MERGE pass (detect identical cells). 2148s Finding identical cells in module `\design_ice'. 2148s Removed a total of 0 cells. 2148s 2148s 2.10.6. Executing OPT_DFF pass (perform DFF optimizations). 2148s 2148s 2.10.7. Executing OPT_CLEAN pass (remove unused cells and wires). 2148s Finding unused cells or wires in module \design_ice.. 2148s Removed 0 unused cells and 1 unused wires. 2148s 2148s 2148s 2.10.8. Executing OPT_EXPR pass (perform const folding). 2148s Optimizing module design_ice. 2148s 2148s 2.10.9. Rerunning OPT passes. (Maybe there is more to do..) 2148s 2148s 2.10.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 2148s Running muxtree optimizer on module \design_ice.. 2148s Creating internal representation of mux trees. 2148s Evaluating internal representation of mux trees. 2148s Analyzing evaluation results. 2148s Removed 0 multiplexer ports. 2148s 2148s 2148s 2.10.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 2148s Optimizing cells in module \design_ice. 2148s Performed a total of 0 changes. 2148s 2148s 2.10.12. Executing OPT_MERGE pass (detect identical cells). 2148s Finding identical cells in module `\design_ice'. 2148s Removed a total of 0 cells. 2148s 2148s 2.10.13. Executing OPT_DFF pass (perform DFF optimizations). 2148s 2148s 2.10.14. Executing OPT_CLEAN pass (remove unused cells and wires). 2148s Finding unused cells or wires in module \design_ice.. 2148s 2148s 2.10.15. Executing OPT_EXPR pass (perform const folding). 2148s Optimizing module design_ice. 2148s 2148s 2.10.16. Finished OPT passes. (There is nothing left to do.) 2148s 2148s 2.11. Executing FSM pass (extract and optimize FSM). 2148s 2148s 2.11.1. Executing FSM_DETECT pass (finding FSMs in design). 2148s 2148s 2.11.2. Executing FSM_EXTRACT pass (extracting FSM from design). 2148s 2148s 2.11.3. Executing FSM_OPT pass (simple optimizations of FSMs). 2148s 2148s 2.11.4. Executing OPT_CLEAN pass (remove unused cells and wires). 2148s Finding unused cells or wires in module \design_ice.. 2148s 2148s 2.11.5. Executing FSM_OPT pass (simple optimizations of FSMs). 2148s 2148s 2.11.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 2148s 2148s 2.11.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 2148s 2148s 2.11.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 2148s 2148s 2.12. Executing OPT pass (performing simple optimizations). 2148s 2148s 2.12.1. Executing OPT_EXPR pass (perform const folding). 2148s Optimizing module design_ice. 2148s 2148s 2.12.2. Executing OPT_MERGE pass (detect identical cells). 2148s Finding identical cells in module `\design_ice'. 2148s Removed a total of 0 cells. 2148s 2148s 2.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 2148s Running muxtree optimizer on module \design_ice.. 2148s Creating internal representation of mux trees. 2148s Evaluating internal representation of mux trees. 2148s Analyzing evaluation results. 2148s Removed 0 multiplexer ports. 2148s 2148s 2148s 2.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 2148s Optimizing cells in module \design_ice. 2148s Performed a total of 0 changes. 2148s 2148s 2.12.5. Executing OPT_MERGE pass (detect identical cells). 2148s Finding identical cells in module `\design_ice'. 2148s Removed a total of 0 cells. 2148s 2148s 2.12.6. Executing OPT_DFF pass (perform DFF optimizations). 2148s Adding EN signal on $procdff$454 ($dff) from module design_ice (D = \I1, Q = \value). 2148s 2148s 2.12.7. Executing OPT_CLEAN pass (remove unused cells and wires). 2148s Finding unused cells or wires in module \design_ice.. 2148s Removed 1 unused cells and 1 unused wires. 2148s 2148s 2148s 2.12.8. Executing OPT_EXPR pass (perform const folding). 2148s Optimizing module design_ice. 2148s 2148s 2.12.9. Rerunning OPT passes. (Maybe there is more to do..) 2148s 2148s 2.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 2148s Running muxtree optimizer on module \design_ice.. 2148s Creating internal representation of mux trees. 2148s No muxes found in this module. 2148s Removed 0 multiplexer ports. 2148s 2148s 2.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 2148s Optimizing cells in module \design_ice. 2148s Performed a total of 0 changes. 2148s 2148s 2.12.12. Executing OPT_MERGE pass (detect identical cells). 2148s Finding identical cells in module `\design_ice'. 2148s Removed a total of 0 cells. 2148s 2148s 2.12.13. Executing OPT_DFF pass (perform DFF optimizations). 2148s 2148s 2.12.14. Executing OPT_CLEAN pass (remove unused cells and wires). 2148s Finding unused cells or wires in module \design_ice.. 2148s 2148s 2.12.15. Executing OPT_EXPR pass (perform const folding). 2148s Optimizing module design_ice. 2148s 2148s 2.12.16. Finished OPT passes. (There is nothing left to do.) 2148s 2148s 2.13. Executing WREDUCE pass (reducing word size of cells). 2148s 2148s 2.14. Executing PEEPOPT pass (run peephole optimizers). 2148s 2148s 2.15. Executing OPT_CLEAN pass (remove unused cells and wires). 2148s Finding unused cells or wires in module \design_ice.. 2148s 2148s 2.16. Executing SHARE pass (SAT-based resource sharing). 2148s 2148s 2.17. Executing TECHMAP pass (map to technology primitives). 2148s 2148s 2.17.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v 2148s Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation. 2148s Generating RTLIL representation for module `\_90_lut_cmp_'. 2148s Successfully finished Verilog frontend. 2148s 2148s 2.17.2. Continuing TECHMAP pass. 2148s No more expansions possible. 2148s 2148s 2148s 2.18. Executing OPT_EXPR pass (perform const folding). 2148s Optimizing module design_ice. 2148s 2148s 2.19. Executing OPT_CLEAN pass (remove unused cells and wires). 2148s Finding unused cells or wires in module \design_ice.. 2148s 2148s 2.20. Executing ALUMACC pass (create $alu and $macc cells). 2148s Extracting $alu and $macc cells in module design_ice: 2148s created 0 $alu and 0 $macc cells. 2148s 2148s 2.21. Executing OPT pass (performing simple optimizations). 2148s 2148s 2.21.1. Executing OPT_EXPR pass (perform const folding). 2148s Optimizing module design_ice. 2148s 2148s 2.21.2. Executing OPT_MERGE pass (detect identical cells). 2148s Finding identical cells in module `\design_ice'. 2148s Removed a total of 0 cells. 2148s 2148s 2.21.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 2148s Running muxtree optimizer on module \design_ice.. 2148s Creating internal representation of mux trees. 2148s No muxes found in this module. 2148s Removed 0 multiplexer ports. 2148s 2148s 2.21.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 2148s Optimizing cells in module \design_ice. 2148s Performed a total of 0 changes. 2148s 2148s 2.21.5. Executing OPT_MERGE pass (detect identical cells). 2148s Finding identical cells in module `\design_ice'. 2148s Removed a total of 0 cells. 2148s 2148s 2.21.6. Executing OPT_DFF pass (perform DFF optimizations). 2148s 2148s 2.21.7. Executing OPT_CLEAN pass (remove unused cells and wires). 2148s Finding unused cells or wires in module \design_ice.. 2148s 2148s 2.21.8. Executing OPT_EXPR pass (perform const folding). 2148s Optimizing module design_ice. 2148s 2148s 2.21.9. Finished OPT passes. (There is nothing left to do.) 2148s 2148s 2.22. Executing MEMORY pass. 2148s 2148s 2.22.1. Executing OPT_MEM pass (optimize memories). 2148s Performed a total of 0 transformations. 2148s 2148s 2.22.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). 2148s Performed a total of 0 transformations. 2148s 2148s 2.22.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 2148s 2148s 2.22.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 2148s 2148s 2.22.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 2148s 2148s 2.22.6. Executing OPT_CLEAN pass (remove unused cells and wires). 2148s Finding unused cells or wires in module \design_ice.. 2148s 2148s 2.22.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 2148s 2148s 2.22.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). 2148s Performed a total of 0 transformations. 2148s 2148s 2.22.9. Executing OPT_CLEAN pass (remove unused cells and wires). 2148s Finding unused cells or wires in module \design_ice.. 2148s 2148s 2.22.10. Executing MEMORY_COLLECT pass (generating $mem cells). 2148s 2148s 2.23. Executing OPT_CLEAN pass (remove unused cells and wires). 2148s Finding unused cells or wires in module \design_ice.. 2148s 2148s 2.24. Executing MEMORY_LIBMAP pass (mapping memories to cells). 2148s 2148s 2.25. Executing TECHMAP pass (map to technology primitives). 2148s 2148s 2.25.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v 2148s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation. 2148s Generating RTLIL representation for module `\$__ICE40_RAM4K_'. 2148s Successfully finished Verilog frontend. 2148s 2148s 2.25.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/spram_map.v 2148s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/spram_map.v' to AST representation. 2148s Generating RTLIL representation for module `\$__ICE40_SPRAM_'. 2148s Successfully finished Verilog frontend. 2148s 2148s 2.25.3. Continuing TECHMAP pass. 2148s No more expansions possible. 2148s 2148s 2148s 2.26. Executing ICE40_BRAMINIT pass. 2148s 2148s 2.27. Executing OPT pass (performing simple optimizations). 2148s 2148s 2.27.1. Executing OPT_EXPR pass (perform const folding). 2148s Optimizing module design_ice. 2148s 2148s 2.27.2. Executing OPT_MERGE pass (detect identical cells). 2148s Finding identical cells in module `\design_ice'. 2148s Removed a total of 0 cells. 2148s 2148s 2.27.3. Executing OPT_DFF pass (perform DFF optimizations). 2148s 2148s 2.27.4. Executing OPT_CLEAN pass (remove unused cells and wires). 2148s Finding unused cells or wires in module \design_ice.. 2148s 2148s 2.27.5. Finished fast OPT passes. 2148s 2148s 2.28. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 2148s 2148s 2.29. Executing OPT pass (performing simple optimizations). 2148s 2148s 2.29.1. Executing OPT_EXPR pass (perform const folding). 2148s Optimizing module design_ice. 2148s 2148s 2.29.2. Executing OPT_MERGE pass (detect identical cells). 2148s Finding identical cells in module `\design_ice'. 2148s Removed a total of 0 cells. 2148s 2148s 2.29.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 2148s Running muxtree optimizer on module \design_ice.. 2148s Creating internal representation of mux trees. 2148s No muxes found in this module. 2148s Removed 0 multiplexer ports. 2148s 2148s 2.29.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 2148s Optimizing cells in module \design_ice. 2148s Performed a total of 0 changes. 2148s 2148s 2.29.5. Executing OPT_MERGE pass (detect identical cells). 2148s Finding identical cells in module `\design_ice'. 2148s Removed a total of 0 cells. 2148s 2148s 2.29.6. Executing OPT_DFF pass (perform DFF optimizations). 2148s 2148s 2.29.7. Executing OPT_CLEAN pass (remove unused cells and wires). 2148s Finding unused cells or wires in module \design_ice.. 2148s 2148s 2.29.8. Executing OPT_EXPR pass (perform const folding). 2148s Optimizing module design_ice. 2148s 2148s 2.29.9. Finished OPT passes. (There is nothing left to do.) 2148s 2148s 2.30. Executing ICE40_WRAPCARRY pass (wrap carries). 2148s 2148s 2.31. Executing TECHMAP pass (map to technology primitives). 2148s 2148s 2.31.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v 2148s Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation. 2148s Generating RTLIL representation for module `\_90_simplemap_bool_ops'. 2148s Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. 2148s Generating RTLIL representation for module `\_90_simplemap_logic_ops'. 2148s Generating RTLIL representation for module `\_90_simplemap_compare_ops'. 2148s Generating RTLIL representation for module `\_90_simplemap_various'. 2148s Generating RTLIL representation for module `\_90_simplemap_registers'. 2148s Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. 2148s Generating RTLIL representation for module `\_90_shift_shiftx'. 2148s Generating RTLIL representation for module `\_90_fa'. 2148s Generating RTLIL representation for module `\_90_lcu'. 2148s Generating RTLIL representation for module `\_90_alu'. 2148s Generating RTLIL representation for module `\_90_macc'. 2148s Generating RTLIL representation for module `\_90_alumacc'. 2148s Generating RTLIL representation for module `\$__div_mod_u'. 2148s Generating RTLIL representation for module `\$__div_mod_trunc'. 2148s Generating RTLIL representation for module `\_90_div'. 2148s Generating RTLIL representation for module `\_90_mod'. 2148s Generating RTLIL representation for module `\$__div_mod_floor'. 2148s Generating RTLIL representation for module `\_90_divfloor'. 2148s Generating RTLIL representation for module `\_90_modfloor'. 2148s Generating RTLIL representation for module `\_90_pow'. 2148s Generating RTLIL representation for module `\_90_pmux'. 2148s Generating RTLIL representation for module `\_90_demux'. 2148s Generating RTLIL representation for module `\_90_lut'. 2148s Successfully finished Verilog frontend. 2148s 2148s 2.31.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v 2148s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation. 2148s Generating RTLIL representation for module `\_80_ice40_alu'. 2148s Successfully finished Verilog frontend. 2148s 2148s 2.31.3. Continuing TECHMAP pass. 2148s Using extmapper simplemap for cells of type $dffe. 2148s Using extmapper simplemap for cells of type $dff. 2148s No more expansions possible. 2148s 2148s 2148s 2.32. Executing OPT pass (performing simple optimizations). 2148s 2148s 2.32.1. Executing OPT_EXPR pass (perform const folding). 2148s Optimizing module design_ice. 2148s 2148s 2.32.2. Executing OPT_MERGE pass (detect identical cells). 2148s Finding identical cells in module `\design_ice'. 2148s Removed a total of 0 cells. 2148s 2148s 2.32.3. Executing OPT_DFF pass (perform DFF optimizations). 2148s 2148s 2.32.4. Executing OPT_CLEAN pass (remove unused cells and wires). 2148s Finding unused cells or wires in module \design_ice.. 2148s 2148s 2.32.5. Finished fast OPT passes. 2148s 2148s 2.33. Executing ICE40_OPT pass (performing simple optimizations). 2148s 2148s 2.33.1. Running ICE40 specific optimizations. 2148s 2148s 2.33.2. Executing OPT_EXPR pass (perform const folding). 2148s Optimizing module design_ice. 2148s 2148s 2.33.3. Executing OPT_MERGE pass (detect identical cells). 2148s Finding identical cells in module `\design_ice'. 2148s Removed a total of 0 cells. 2148s 2148s 2.33.4. Executing OPT_DFF pass (perform DFF optimizations). 2148s 2148s 2.33.5. Executing OPT_CLEAN pass (remove unused cells and wires). 2148s Finding unused cells or wires in module \design_ice.. 2148s 2148s 2.33.6. Finished OPT passes. (There is nothing left to do.) 2148s 2148s 2.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 2148s 2148s 2.35. Executing TECHMAP pass (map to technology primitives). 2148s 2148s 2.35.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 2148s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 2148s Generating RTLIL representation for module `\$_DFF_N_'. 2148s Generating RTLIL representation for module `\$_DFF_P_'. 2148s Generating RTLIL representation for module `\$_DFFE_NP_'. 2148s Generating RTLIL representation for module `\$_DFFE_PP_'. 2148s Generating RTLIL representation for module `\$_DFF_NP0_'. 2148s Generating RTLIL representation for module `\$_DFF_NP1_'. 2148s Generating RTLIL representation for module `\$_DFF_PP0_'. 2148s Generating RTLIL representation for module `\$_DFF_PP1_'. 2148s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 2148s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 2148s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 2148s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 2148s Generating RTLIL representation for module `\$_SDFF_NP0_'. 2148s Generating RTLIL representation for module `\$_SDFF_NP1_'. 2148s Generating RTLIL representation for module `\$_SDFF_PP0_'. 2148s Generating RTLIL representation for module `\$_SDFF_PP1_'. 2148s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 2148s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 2148s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 2148s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 2148s Successfully finished Verilog frontend. 2148s 2148s 2.35.2. Continuing TECHMAP pass. 2148s Using template \$_DFF_P_ for cells of type $_DFF_P_. 2148s Using template \$_DFFE_PP_ for cells of type $_DFFE_PP_. 2148s No more expansions possible. 2148s 2148s 2148s 2.36. Executing OPT_EXPR pass (perform const folding). 2148s Optimizing module design_ice. 2148s 2148s 2.37. Executing SIMPLEMAP pass (map simple cells to gate primitives). 2148s 2148s 2.38. Executing ICE40_OPT pass (performing simple optimizations). 2148s 2148s 2.38.1. Running ICE40 specific optimizations. 2148s 2148s 2.38.2. Executing OPT_EXPR pass (perform const folding). 2148s Optimizing module design_ice. 2148s 2148s 2.38.3. Executing OPT_MERGE pass (detect identical cells). 2148s Finding identical cells in module `\design_ice'. 2148s Removed a total of 0 cells. 2148s 2148s 2.38.4. Executing OPT_DFF pass (perform DFF optimizations). 2149s 2149s 2.38.5. Executing OPT_CLEAN pass (remove unused cells and wires). 2149s Finding unused cells or wires in module \design_ice.. 2149s Removed 0 unused cells and 9 unused wires. 2149s 2149s 2149s 2.38.6. Rerunning OPT passes. (Removed registers in this run.) 2149s 2149s 2.38.7. Running ICE40 specific optimizations. 2149s 2149s 2.38.8. Executing OPT_EXPR pass (perform const folding). 2149s Optimizing module design_ice. 2149s 2149s 2.38.9. Executing OPT_MERGE pass (detect identical cells). 2149s Finding identical cells in module `\design_ice'. 2149s Removed a total of 0 cells. 2149s 2149s 2.38.10. Executing OPT_DFF pass (perform DFF optimizations). 2149s 2149s 2.38.11. Executing OPT_CLEAN pass (remove unused cells and wires). 2149s Finding unused cells or wires in module \design_ice.. 2149s 2149s 2.38.12. Finished OPT passes. (There is nothing left to do.) 2149s 2149s 2.39. Executing TECHMAP pass (map to technology primitives). 2149s 2149s 2.39.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v 2149s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation. 2149s Generating RTLIL representation for module `\$_DLATCH_N_'. 2149s Generating RTLIL representation for module `\$_DLATCH_P_'. 2149s Successfully finished Verilog frontend. 2149s 2149s 2.39.2. Continuing TECHMAP pass. 2149s No more expansions possible. 2149s 2149s 2149s 2.40. Executing ABC pass (technology mapping using ABC). 2149s 2149s 2.40.1. Extracting gate netlist of module `\design_ice' to `/input.blif'.. 2149s Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs. 2149s Don't call ABC as there is nothing to map. 2149s Removing temp directory. 2149s 2149s 2.41. Executing ICE40_WRAPCARRY pass (wrap carries). 2149s 2149s 2.42. Executing TECHMAP pass (map to technology primitives). 2149s 2149s 2.42.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 2149s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 2149s Generating RTLIL representation for module `\$_DFF_N_'. 2149s Generating RTLIL representation for module `\$_DFF_P_'. 2149s Generating RTLIL representation for module `\$_DFFE_NP_'. 2149s Generating RTLIL representation for module `\$_DFFE_PP_'. 2149s Generating RTLIL representation for module `\$_DFF_NP0_'. 2149s Generating RTLIL representation for module `\$_DFF_NP1_'. 2149s Generating RTLIL representation for module `\$_DFF_PP0_'. 2149s Generating RTLIL representation for module `\$_DFF_PP1_'. 2149s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 2149s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 2149s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 2149s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 2149s Generating RTLIL representation for module `\$_SDFF_NP0_'. 2149s Generating RTLIL representation for module `\$_SDFF_NP1_'. 2149s Generating RTLIL representation for module `\$_SDFF_PP0_'. 2149s Generating RTLIL representation for module `\$_SDFF_PP1_'. 2149s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 2149s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 2149s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 2149s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 2149s Successfully finished Verilog frontend. 2149s 2149s 2.42.2. Continuing TECHMAP pass. 2149s No more expansions possible. 2149s 2149s 2149s 2.43. Executing OPT_LUT pass (optimize LUTs). 2149s Discovering LUTs. 2149s Number of LUTs: 0 2149s with \SB_CARRY (#0) 0 2149s with \SB_CARRY (#1) 0 2149s 2149s Eliminating LUTs. 2149s Number of LUTs: 0 2149s with \SB_CARRY (#0) 0 2149s with \SB_CARRY (#1) 0 2149s 2149s Combining LUTs. 2149s Number of LUTs: 0 2149s with \SB_CARRY (#0) 0 2149s with \SB_CARRY (#1) 0 2149s 2149s Eliminated 0 LUTs. 2149s Combined 0 LUTs. 2149s 2149s 2.44. Executing TECHMAP pass (map to technology primitives). 2149s 2149s 2.44.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v 2149s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation. 2149s Generating RTLIL representation for module `\$lut'. 2149s Successfully finished Verilog frontend. 2149s 2149s 2.44.2. Continuing TECHMAP pass. 2149s No more expansions possible. 2149s 2149s 2149s 2.45. Executing AUTONAME pass. 2149s Renamed 2 objects in module design_ice (2 iterations). 2149s 2149s 2149s 2.46. Executing HIERARCHY pass (managing design hierarchy). 2149s 2149s 2.46.1. Analyzing design hierarchy.. 2149s Top module: \design_ice 2149s 2149s 2.46.2. Analyzing design hierarchy.. 2149s Top module: \design_ice 2149s Removed 0 unused modules. 2149s 2149s 2.47. Printing statistics. 2149s 2149s === design_ice === 2149s 2149s Number of wires: 5 2149s Number of wire bits: 5 2149s Number of public wires: 5 2149s Number of public wire bits: 5 2149s Number of memories: 0 2149s Number of memory bits: 0 2149s Number of processes: 0 2149s Number of cells: 2 2149s SB_DFF 1 2149s SB_DFFE 1 2149s 2149s 2.48. Executing CHECK pass (checking for obvious problems). 2149s Checking module design_ice... 2149s Found and reported 0 problems. 2149s 2149s 2.49. Executing BLIF backend. 2149s 2149s End of script. Logfile hash: 38f2f133b9, CPU: user 0.67s system 0.03s, MEM: 19.16 MB peak 2149s Yosys 0.33 (git sha1 2584903a060) 2149s Time spent: 67% 13x read_verilog (0 sec), 8% 1x synth_ice40 (0 sec), ... 2149s autopkgtest [22:54:20]: test ice: -----------------------] 2149s ice PASS 2149s autopkgtest [22:54:20]: test ice: - - - - - - - - - - results - - - - - - - - - - 2150s autopkgtest [22:54:21]: test smtbc: preparing testbed 2150s Reading package lists... 2150s Building dependency tree... 2150s Reading state information... 2151s Starting pkgProblemResolver with broken count: 0 2151s Starting 2 pkgProblemResolver with broken count: 0 2151s Done 2151s 0 upgraded, 0 newly installed, 0 to remove and 0 not upgraded. 2152s autopkgtest [22:54:23]: test smtbc: [----------------------- 2153s autopkgtest [22:54:24]: test smtbc: -----------------------] 2153s autopkgtest [22:54:24]: test smtbc: - - - - - - - - - - results - - - - - - - - - - 2153s smtbc PASS 2154s autopkgtest [22:54:25]: @@@@@@@@@@@@@@@@@@@@ summary 2154s yosys-testsuite PASS 2154s ice PASS 2154s smtbc PASS 2171s nova [W] Using flock in prodstack6-arm64 2171s Creating nova instance adt-questing-arm64-yosys-20250505-221831-juju-7f2275-prod-proposed-migration-environment-15-aea8ce69-126c-4081-b944-b7ebfd847f66 from image adt/ubuntu-questing-arm64-server-20250505.img (UUID df0e3f26-2615-49ec-84ba-7cef705cfad7)... 2171s nova [W] Timed out waiting for b5365ecd-aeb8-4e9a-b5e0-dbb979707ad6 to get deleted. 2171s nova [W] Using flock in prodstack6-arm64 2171s Creating nova instance adt-questing-arm64-yosys-20250505-221831-juju-7f2275-prod-proposed-migration-environment-15-aea8ce69-126c-4081-b944-b7ebfd847f66 from image adt/ubuntu-questing-arm64-server-20250505.img (UUID df0e3f26-2615-49ec-84ba-7cef705cfad7)... 2171s nova [W] Timed out waiting for 0ca73921-6a31-46ab-a6b2-4bd29fe2a398 to get deleted.