0s autopkgtest [22:18:06]: starting date and time: 2025-05-05 22:18:06+0000 0s autopkgtest [22:18:06]: git checkout: 9986aa8c Merge branch 'skia/fix_network_interface' into 'ubuntu/production' 0s autopkgtest [22:18:06]: host juju-7f2275-prod-proposed-migration-environment-2; command line: /home/ubuntu/autopkgtest/runner/autopkgtest --output-dir /tmp/autopkgtest-work.7i4chb7q/out --timeout-copy=6000 --setup-commands /home/ubuntu/autopkgtest-cloud/worker-config-production/setup-canonical.sh --apt-pocket=proposed=src:gawk --apt-upgrade yosys --timeout-short=300 --timeout-copy=20000 --timeout-build=20000 --env=ADT_TEST_TRIGGERS=gawk/1:5.3.2-1 -- ssh -s /home/ubuntu/autopkgtest/ssh-setup/nova -- --flavor builder-cpu2-ram4-disk20 --security-groups autopkgtest-juju-7f2275-prod-proposed-migration-environment-2@bos03-19.secgroup --name adt-questing-amd64-yosys-20250505-221806-juju-7f2275-prod-proposed-migration-environment-2-7789d234-fb3b-438f-a626-4da25cd68b69 --image adt/ubuntu-questing-amd64-server --keyname testbed-juju-7f2275-prod-proposed-migration-environment-2 --net-id=net_prod-proposed-migration-amd64 -e TERM=linux --mirror=http://ftpmaster.internal/ubuntu/ 52s autopkgtest [22:18:58]: testbed dpkg architecture: amd64 52s autopkgtest [22:18:58]: testbed apt version: 3.0.0 52s autopkgtest [22:18:58]: @@@@@@@@@@@@@@@@@@@@ test bed setup 52s autopkgtest [22:18:58]: testbed release detected to be: None 53s autopkgtest [22:18:59]: updating testbed package index (apt update) 53s Get:1 http://ftpmaster.internal/ubuntu questing-proposed InRelease [110 kB] 54s Hit:2 http://ftpmaster.internal/ubuntu questing InRelease 54s Hit:3 http://ftpmaster.internal/ubuntu questing-updates InRelease 54s Hit:4 http://ftpmaster.internal/ubuntu questing-security InRelease 54s Get:5 http://ftpmaster.internal/ubuntu questing-proposed/main Sources [86.1 kB] 54s Get:6 http://ftpmaster.internal/ubuntu questing-proposed/universe Sources [818 kB] 54s Get:7 http://ftpmaster.internal/ubuntu questing-proposed/multiverse Sources [30.0 kB] 54s Get:8 http://ftpmaster.internal/ubuntu questing-proposed/main amd64 Packages [126 kB] 54s Get:9 http://ftpmaster.internal/ubuntu questing-proposed/main i386 Packages [86.1 kB] 54s Get:10 http://ftpmaster.internal/ubuntu questing-proposed/universe i386 Packages [333 kB] 54s Get:11 http://ftpmaster.internal/ubuntu questing-proposed/universe amd64 Packages [908 kB] 54s Get:12 http://ftpmaster.internal/ubuntu questing-proposed/multiverse i386 Packages [11.3 kB] 54s Get:13 http://ftpmaster.internal/ubuntu questing-proposed/multiverse amd64 Packages [20.3 kB] 54s Fetched 2529 kB in 1s (2635 kB/s) 55s Reading package lists... 56s autopkgtest [22:19:02]: upgrading testbed (apt dist-upgrade and autopurge) 56s Reading package lists... 56s Building dependency tree... 56s Reading state information... 57s Calculating upgrade...Starting pkgProblemResolver with broken count: 0 57s Starting 2 pkgProblemResolver with broken count: 0 57s Done 57s Entering ResolveByKeep 57s 57s Calculating upgrade... 58s The following package was automatically installed and is no longer required: 58s libsigsegv2 58s Use 'sudo apt autoremove' to remove it. 58s The following packages will be upgraded: 58s dhcpcd-base dirmngr gawk gir1.2-glib-2.0 gnupg gnupg-l10n gnupg-utils gpg 58s gpg-agent gpg-wks-client gpgconf gpgsm gpgv groff-base keyboxd 58s libglib2.0-0t64 libglib2.0-data libgpg-error-l10n libgpg-error0 libnuma1 58s libselinux1 libx11-6 libx11-data libxml2 netbase numactl openssh-client 58s openssh-server openssh-sftp-server python3-packaging python3-wadllib 58s 31 upgraded, 0 newly installed, 0 to remove and 0 not upgraded. 58s Need to get 9531 kB of archives. 58s After this operation, 880 kB disk space will be freed. 58s Get:1 http://ftpmaster.internal/ubuntu questing-proposed/main amd64 gawk amd64 1:5.3.2-1 [522 kB] 58s Get:2 http://ftpmaster.internal/ubuntu questing/main amd64 libselinux1 amd64 3.8.1-1 [89.8 kB] 58s Get:3 http://ftpmaster.internal/ubuntu questing/main amd64 openssh-sftp-server amd64 1:9.9p1-3ubuntu3.1 [41.2 kB] 58s Get:4 http://ftpmaster.internal/ubuntu questing/main amd64 openssh-server amd64 1:9.9p1-3ubuntu3.1 [625 kB] 58s Get:5 http://ftpmaster.internal/ubuntu questing/main amd64 openssh-client amd64 1:9.9p1-3ubuntu3.1 [1080 kB] 58s Get:6 http://ftpmaster.internal/ubuntu questing/main amd64 libgpg-error-l10n all 1.51-4 [8880 B] 58s Get:7 http://ftpmaster.internal/ubuntu questing/main amd64 libgpg-error0 amd64 1.51-4 [76.9 kB] 58s Get:8 http://ftpmaster.internal/ubuntu questing/main amd64 gpg-wks-client amd64 2.4.4-2ubuntu24 [71.6 kB] 58s Get:9 http://ftpmaster.internal/ubuntu questing/main amd64 dirmngr amd64 2.4.4-2ubuntu24 [327 kB] 58s Get:10 http://ftpmaster.internal/ubuntu questing/main amd64 gpgsm amd64 2.4.4-2ubuntu24 [236 kB] 58s Get:11 http://ftpmaster.internal/ubuntu questing/main amd64 gnupg-utils amd64 2.4.4-2ubuntu24 [110 kB] 58s Get:12 http://ftpmaster.internal/ubuntu questing/main amd64 gpg-agent amd64 2.4.4-2ubuntu24 [231 kB] 58s Get:13 http://ftpmaster.internal/ubuntu questing/main amd64 gpg amd64 2.4.4-2ubuntu24 [572 kB] 58s Get:14 http://ftpmaster.internal/ubuntu questing/main amd64 gpgconf amd64 2.4.4-2ubuntu24 [104 kB] 58s Get:15 http://ftpmaster.internal/ubuntu questing/main amd64 gnupg all 2.4.4-2ubuntu24 [359 kB] 58s Get:16 http://ftpmaster.internal/ubuntu questing/main amd64 keyboxd amd64 2.4.4-2ubuntu24 [78.4 kB] 58s Get:17 http://ftpmaster.internal/ubuntu questing/main amd64 gpgv amd64 2.4.4-2ubuntu24 [160 kB] 58s Get:18 http://ftpmaster.internal/ubuntu questing/main amd64 dhcpcd-base amd64 1:10.1.0-10 [219 kB] 58s Get:19 http://ftpmaster.internal/ubuntu questing/main amd64 gir1.2-glib-2.0 amd64 2.84.1-2 [184 kB] 58s Get:20 http://ftpmaster.internal/ubuntu questing/main amd64 libglib2.0-0t64 amd64 2.84.1-2 [1584 kB] 58s Get:21 http://ftpmaster.internal/ubuntu questing/main amd64 libglib2.0-data all 2.84.1-2 [53.2 kB] 58s Get:22 http://ftpmaster.internal/ubuntu questing/main amd64 libxml2 amd64 2.12.7+dfsg+really2.9.14-0.4ubuntu0.1 [772 kB] 58s Get:23 http://ftpmaster.internal/ubuntu questing/main amd64 netbase all 6.5 [12.9 kB] 59s Get:24 http://ftpmaster.internal/ubuntu questing/main amd64 groff-base amd64 1.23.0-8 [1023 kB] 59s Get:25 http://ftpmaster.internal/ubuntu questing/main amd64 libnuma1 amd64 2.0.19-1 [23.5 kB] 59s Get:26 http://ftpmaster.internal/ubuntu questing/main amd64 libx11-data all 2:1.8.12-1 [116 kB] 59s Get:27 http://ftpmaster.internal/ubuntu questing/main amd64 libx11-6 amd64 2:1.8.12-1 [656 kB] 59s Get:28 http://ftpmaster.internal/ubuntu questing/main amd64 numactl amd64 2.0.19-1 [38.8 kB] 59s Get:29 http://ftpmaster.internal/ubuntu questing/main amd64 gnupg-l10n all 2.4.4-2ubuntu24 [66.8 kB] 59s Get:30 http://ftpmaster.internal/ubuntu questing/main amd64 python3-packaging all 25.0-1 [52.8 kB] 59s Get:31 http://ftpmaster.internal/ubuntu questing/main amd64 python3-wadllib all 2.0.0-3 [36.3 kB] 59s Preconfiguring packages ... 59s Fetched 9531 kB in 1s (9642 kB/s) 59s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 80527 files and directories currently installed.) 59s Preparing to unpack .../gawk_1%3a5.3.2-1_amd64.deb ... 59s Unpacking gawk (1:5.3.2-1) over (1:5.2.1-2build3) ... 59s Preparing to unpack .../libselinux1_3.8.1-1_amd64.deb ... 59s Unpacking libselinux1:amd64 (3.8.1-1) over (3.7-3ubuntu3) ... 59s Setting up libselinux1:amd64 (3.8.1-1) ... 59s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 80529 files and directories currently installed.) 59s Preparing to unpack .../openssh-sftp-server_1%3a9.9p1-3ubuntu3.1_amd64.deb ... 59s Unpacking openssh-sftp-server (1:9.9p1-3ubuntu3.1) over (1:9.9p1-3ubuntu3) ... 59s Preparing to unpack .../openssh-server_1%3a9.9p1-3ubuntu3.1_amd64.deb ... 59s Unpacking openssh-server (1:9.9p1-3ubuntu3.1) over (1:9.9p1-3ubuntu3) ... 59s Preparing to unpack .../openssh-client_1%3a9.9p1-3ubuntu3.1_amd64.deb ... 59s Unpacking openssh-client (1:9.9p1-3ubuntu3.1) over (1:9.9p1-3ubuntu3) ... 60s Preparing to unpack .../libgpg-error-l10n_1.51-4_all.deb ... 60s Unpacking libgpg-error-l10n (1.51-4) over (1.51-3) ... 60s Preparing to unpack .../libgpg-error0_1.51-4_amd64.deb ... 60s Unpacking libgpg-error0:amd64 (1.51-4) over (1.51-3) ... 60s Setting up libgpg-error0:amd64 (1.51-4) ... 60s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 80529 files and directories currently installed.) 60s Preparing to unpack .../0-gpg-wks-client_2.4.4-2ubuntu24_amd64.deb ... 60s Unpacking gpg-wks-client (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 60s Preparing to unpack .../1-dirmngr_2.4.4-2ubuntu24_amd64.deb ... 60s Unpacking dirmngr (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 60s Preparing to unpack .../2-gpgsm_2.4.4-2ubuntu24_amd64.deb ... 60s Unpacking gpgsm (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 60s Preparing to unpack .../3-gnupg-utils_2.4.4-2ubuntu24_amd64.deb ... 60s Unpacking gnupg-utils (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 60s Preparing to unpack .../4-gpg-agent_2.4.4-2ubuntu24_amd64.deb ... 60s Unpacking gpg-agent (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 60s Preparing to unpack .../5-gpg_2.4.4-2ubuntu24_amd64.deb ... 60s Unpacking gpg (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 60s Preparing to unpack .../6-gpgconf_2.4.4-2ubuntu24_amd64.deb ... 60s Unpacking gpgconf (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 60s Preparing to unpack .../7-gnupg_2.4.4-2ubuntu24_all.deb ... 60s Unpacking gnupg (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 60s Preparing to unpack .../8-keyboxd_2.4.4-2ubuntu24_amd64.deb ... 60s Unpacking keyboxd (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 60s Preparing to unpack .../9-gpgv_2.4.4-2ubuntu24_amd64.deb ... 60s Unpacking gpgv (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 60s Setting up gpgv (2.4.4-2ubuntu24) ... 60s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 80529 files and directories currently installed.) 60s Preparing to unpack .../00-dhcpcd-base_1%3a10.1.0-10_amd64.deb ... 60s Unpacking dhcpcd-base (1:10.1.0-10) over (1:10.1.0-8) ... 60s Preparing to unpack .../01-gir1.2-glib-2.0_2.84.1-2_amd64.deb ... 60s Unpacking gir1.2-glib-2.0:amd64 (2.84.1-2) over (2.84.1-1) ... 60s Preparing to unpack .../02-libglib2.0-0t64_2.84.1-2_amd64.deb ... 60s Unpacking libglib2.0-0t64:amd64 (2.84.1-2) over (2.84.1-1) ... 60s Preparing to unpack .../03-libglib2.0-data_2.84.1-2_all.deb ... 60s Unpacking libglib2.0-data (2.84.1-2) over (2.84.1-1) ... 60s Preparing to unpack .../04-libxml2_2.12.7+dfsg+really2.9.14-0.4ubuntu0.1_amd64.deb ... 60s Unpacking libxml2:amd64 (2.12.7+dfsg+really2.9.14-0.4ubuntu0.1) over (2.12.7+dfsg+really2.9.14-0.4) ... 60s Preparing to unpack .../05-netbase_6.5_all.deb ... 60s Unpacking netbase (6.5) over (6.4) ... 60s Preparing to unpack .../06-groff-base_1.23.0-8_amd64.deb ... 60s Unpacking groff-base (1.23.0-8) over (1.23.0-7) ... 60s Preparing to unpack .../07-libnuma1_2.0.19-1_amd64.deb ... 60s Unpacking libnuma1:amd64 (2.0.19-1) over (2.0.18-1build1) ... 60s Preparing to unpack .../08-libx11-data_2%3a1.8.12-1_all.deb ... 60s Unpacking libx11-data (2:1.8.12-1) over (2:1.8.10-2) ... 61s Preparing to unpack .../09-libx11-6_2%3a1.8.12-1_amd64.deb ... 61s Unpacking libx11-6:amd64 (2:1.8.12-1) over (2:1.8.10-2) ... 61s Preparing to unpack .../10-numactl_2.0.19-1_amd64.deb ... 61s Unpacking numactl (2.0.19-1) over (2.0.18-1build1) ... 61s Preparing to unpack .../11-gnupg-l10n_2.4.4-2ubuntu24_all.deb ... 61s Unpacking gnupg-l10n (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 61s Preparing to unpack .../12-python3-packaging_25.0-1_all.deb ... 61s Unpacking python3-packaging (25.0-1) over (24.2-1) ... 61s Preparing to unpack .../13-python3-wadllib_2.0.0-3_all.deb ... 61s Unpacking python3-wadllib (2.0.0-3) over (2.0.0-2) ... 61s Setting up gawk (1:5.3.2-1) ... 61s Setting up openssh-client (1:9.9p1-3ubuntu3.1) ... 61s Setting up libglib2.0-0t64:amd64 (2.84.1-2) ... 61s No schema files found: doing nothing. 61s Setting up libglib2.0-data (2.84.1-2) ... 61s Setting up python3-packaging (25.0-1) ... 61s Setting up libx11-data (2:1.8.12-1) ... 61s Setting up gnupg-l10n (2.4.4-2ubuntu24) ... 61s Setting up python3-wadllib (2.0.0-3) ... 61s Setting up dhcpcd-base (1:10.1.0-10) ... 61s Installing new version of config file /etc/dhcpcd.conf ... 61s Setting up gir1.2-glib-2.0:amd64 (2.84.1-2) ... 61s Setting up libnuma1:amd64 (2.0.19-1) ... 61s Setting up groff-base (1.23.0-8) ... 61s Setting up gpgconf (2.4.4-2ubuntu24) ... 61s Setting up libx11-6:amd64 (2:1.8.12-1) ... 61s Setting up netbase (6.5) ... 61s Installing new version of config file /etc/ethertypes ... 61s Installing new version of config file /etc/services ... 61s Setting up libgpg-error-l10n (1.51-4) ... 61s Setting up libxml2:amd64 (2.12.7+dfsg+really2.9.14-0.4ubuntu0.1) ... 61s Setting up gpg (2.4.4-2ubuntu24) ... 61s Setting up gnupg-utils (2.4.4-2ubuntu24) ... 61s Setting up openssh-sftp-server (1:9.9p1-3ubuntu3.1) ... 61s Setting up gpg-agent (2.4.4-2ubuntu24) ... 62s Setting up numactl (2.0.19-1) ... 62s Setting up openssh-server (1:9.9p1-3ubuntu3.1) ... 63s Setting up gpgsm (2.4.4-2ubuntu24) ... 63s Setting up dirmngr (2.4.4-2ubuntu24) ... 63s Setting up keyboxd (2.4.4-2ubuntu24) ... 63s Setting up gnupg (2.4.4-2ubuntu24) ... 63s Setting up gpg-wks-client (2.4.4-2ubuntu24) ... 63s Processing triggers for ufw (0.36.2-9) ... 63s Processing triggers for man-db (2.13.1-1) ... 64s Processing triggers for install-info (7.1.1-1) ... 64s Processing triggers for libc-bin (2.41-6ubuntu1) ... 65s Reading package lists... 65s Building dependency tree... 65s Reading state information... 65s Starting pkgProblemResolver with broken count: 0 65s Starting 2 pkgProblemResolver with broken count: 0 65s Done 66s Solving dependencies... 66s The following packages will be REMOVED: 66s libsigsegv2* 66s 0 upgraded, 0 newly installed, 1 to remove and 0 not upgraded. 66s After this operation, 48.1 kB disk space will be freed. 66s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 80529 files and directories currently installed.) 66s Removing libsigsegv2:amd64 (2.14-1ubuntu2) ... 66s Processing triggers for libc-bin (2.41-6ubuntu1) ... 67s autopkgtest [22:19:13]: rebooting testbed after setup commands that affected boot 90s autopkgtest [22:19:36]: testbed running kernel: Linux 6.14.0-15-generic #15-Ubuntu SMP PREEMPT_DYNAMIC Sun Apr 6 15:05:05 UTC 2025 92s autopkgtest [22:19:38]: @@@@@@@@@@@@@@@@@@@@ apt-source yosys 96s Get:1 http://ftpmaster.internal/ubuntu questing/universe yosys 0.33-5build2 (dsc) [3069 B] 96s Get:2 http://ftpmaster.internal/ubuntu questing/universe yosys 0.33-5build2 (tar) [6161 kB] 96s Get:3 http://ftpmaster.internal/ubuntu questing/universe yosys 0.33-5build2 (tar) [2586 kB] 96s Get:4 http://ftpmaster.internal/ubuntu questing/universe yosys 0.33-5build2 (diff) [30.3 kB] 96s gpgv: Signature made Mon Apr 1 04:53:46 2024 UTC 96s gpgv: using RSA key A089FB36AAFBDAD5ACC1325069F790171A210984 96s gpgv: Can't check signature: No public key 96s dpkg-source: warning: cannot verify inline signature for ./yosys_0.33-5build2.dsc: no acceptable signature found 97s autopkgtest [22:19:43]: testing package yosys version 0.33-5build2 98s autopkgtest [22:19:44]: build not needed 101s autopkgtest [22:19:47]: test yosys-testsuite: preparing testbed 101s Reading package lists... 101s Building dependency tree... 101s Reading state information... 102s Starting pkgProblemResolver with broken count: 0 102s Starting 2 pkgProblemResolver with broken count: 0 102s Done 102s The following NEW packages will be installed: 102s cpp cpp-14 cpp-14-x86-64-linux-gnu cpp-x86-64-linux-gnu g++ g++-14 102s g++-14-x86-64-linux-gnu g++-x86-64-linux-gnu gcc gcc-14 102s gcc-14-x86-64-linux-gnu gcc-x86-64-linux-gnu iverilog libasan8 libcc1-0 102s libffi-dev libgcc-14-dev libgomp1 libhwasan0 libisl23 libitm1 liblsan0 102s libmpc3 libncurses-dev libpkgconf3 libquadmath0 libreadline-dev 102s libstdc++-14-dev libtcl8.6 libtsan2 libubsan1 pkg-config pkgconf pkgconf-bin 102s python3-click tcl tcl-dev tcl8.6 tcl8.6-dev yosys yosys-abc yosys-dev 102s zlib1g-dev 102s 0 upgraded, 43 newly installed, 0 to remove and 0 not upgraded. 102s Need to get 80.9 MB of archives. 102s After this operation, 274 MB of additional disk space will be used. 102s Get:1 http://ftpmaster.internal/ubuntu questing/main amd64 libisl23 amd64 0.27-1 [685 kB] 102s Get:2 http://ftpmaster.internal/ubuntu questing/main amd64 libmpc3 amd64 1.3.1-1build2 [55.3 kB] 102s Get:3 http://ftpmaster.internal/ubuntu questing/main amd64 cpp-14-x86-64-linux-gnu amd64 14.2.0-19ubuntu2 [11.9 MB] 103s Get:4 http://ftpmaster.internal/ubuntu questing/main amd64 cpp-14 amd64 14.2.0-19ubuntu2 [1030 B] 103s Get:5 http://ftpmaster.internal/ubuntu questing/main amd64 cpp-x86-64-linux-gnu amd64 4:14.2.0-1ubuntu1 [5586 B] 103s Get:6 http://ftpmaster.internal/ubuntu questing/main amd64 cpp amd64 4:14.2.0-1ubuntu1 [22.4 kB] 103s Get:7 http://ftpmaster.internal/ubuntu questing/main amd64 libcc1-0 amd64 15-20250404-0ubuntu1 [47.1 kB] 103s Get:8 http://ftpmaster.internal/ubuntu questing/main amd64 libgomp1 amd64 15-20250404-0ubuntu1 [151 kB] 103s Get:9 http://ftpmaster.internal/ubuntu questing/main amd64 libitm1 amd64 15-20250404-0ubuntu1 [29.5 kB] 103s Get:10 http://ftpmaster.internal/ubuntu questing/main amd64 libasan8 amd64 15-20250404-0ubuntu1 [3076 kB] 103s Get:11 http://ftpmaster.internal/ubuntu questing/main amd64 liblsan0 amd64 15-20250404-0ubuntu1 [1362 kB] 103s Get:12 http://ftpmaster.internal/ubuntu questing/main amd64 libtsan2 amd64 15-20250404-0ubuntu1 [2760 kB] 103s Get:13 http://ftpmaster.internal/ubuntu questing/main amd64 libubsan1 amd64 15-20250404-0ubuntu1 [1211 kB] 103s Get:14 http://ftpmaster.internal/ubuntu questing/main amd64 libhwasan0 amd64 15-20250404-0ubuntu1 [1687 kB] 103s Get:15 http://ftpmaster.internal/ubuntu questing/main amd64 libquadmath0 amd64 15-20250404-0ubuntu1 [153 kB] 103s Get:16 http://ftpmaster.internal/ubuntu questing/main amd64 libgcc-14-dev amd64 14.2.0-19ubuntu2 [2815 kB] 103s Get:17 http://ftpmaster.internal/ubuntu questing/main amd64 gcc-14-x86-64-linux-gnu amd64 14.2.0-19ubuntu2 [23.3 MB] 104s Get:18 http://ftpmaster.internal/ubuntu questing/main amd64 gcc-14 amd64 14.2.0-19ubuntu2 [540 kB] 104s Get:19 http://ftpmaster.internal/ubuntu questing/main amd64 gcc-x86-64-linux-gnu amd64 4:14.2.0-1ubuntu1 [1208 B] 104s Get:20 http://ftpmaster.internal/ubuntu questing/main amd64 gcc amd64 4:14.2.0-1ubuntu1 [5004 B] 104s Get:21 http://ftpmaster.internal/ubuntu questing/main amd64 libstdc++-14-dev amd64 14.2.0-19ubuntu2 [2510 kB] 104s Get:22 http://ftpmaster.internal/ubuntu questing/main amd64 g++-14-x86-64-linux-gnu amd64 14.2.0-19ubuntu2 [13.4 MB] 104s Get:23 http://ftpmaster.internal/ubuntu questing/main amd64 g++-14 amd64 14.2.0-19ubuntu2 [23.0 kB] 104s Get:24 http://ftpmaster.internal/ubuntu questing/main amd64 g++-x86-64-linux-gnu amd64 4:14.2.0-1ubuntu1 [968 B] 104s Get:25 http://ftpmaster.internal/ubuntu questing/main amd64 g++ amd64 4:14.2.0-1ubuntu1 [1100 B] 104s Get:26 http://ftpmaster.internal/ubuntu questing/universe amd64 iverilog amd64 12.0-2build2 [2126 kB] 104s Get:27 http://ftpmaster.internal/ubuntu questing/main amd64 libncurses-dev amd64 6.5+20250216-2 [424 kB] 104s Get:28 http://ftpmaster.internal/ubuntu questing/main amd64 libpkgconf3 amd64 1.8.1-4 [32.3 kB] 104s Get:29 http://ftpmaster.internal/ubuntu questing/main amd64 libreadline-dev amd64 8.2-6 [184 kB] 104s Get:30 http://ftpmaster.internal/ubuntu questing/main amd64 libtcl8.6 amd64 8.6.16+dfsg-1 [1086 kB] 104s Get:31 http://ftpmaster.internal/ubuntu questing/main amd64 pkgconf-bin amd64 1.8.1-4 [21.6 kB] 104s Get:32 http://ftpmaster.internal/ubuntu questing/main amd64 pkgconf amd64 1.8.1-4 [16.8 kB] 104s Get:33 http://ftpmaster.internal/ubuntu questing/main amd64 pkg-config amd64 1.8.1-4 [7362 B] 104s Get:34 http://ftpmaster.internal/ubuntu questing/main amd64 python3-click all 8.2.0+0.really.8.1.8-1 [80.0 kB] 104s Get:35 http://ftpmaster.internal/ubuntu questing/main amd64 tcl8.6 amd64 8.6.16+dfsg-1 [14.9 kB] 104s Get:36 http://ftpmaster.internal/ubuntu questing/main amd64 tcl amd64 8.6.16 [4086 B] 104s Get:37 http://ftpmaster.internal/ubuntu questing/main amd64 zlib1g-dev amd64 1:1.3.dfsg+really1.3.1-1ubuntu1 [895 kB] 104s Get:38 http://ftpmaster.internal/ubuntu questing/main amd64 tcl8.6-dev amd64 8.6.16+dfsg-1 [1081 kB] 104s Get:39 http://ftpmaster.internal/ubuntu questing/main amd64 tcl-dev amd64 8.6.16 [5768 B] 104s Get:40 http://ftpmaster.internal/ubuntu questing/universe amd64 yosys-abc amd64 0.33-5build2 [5829 kB] 104s Get:41 http://ftpmaster.internal/ubuntu questing/universe amd64 yosys amd64 0.33-5build2 [3222 kB] 105s Get:42 http://ftpmaster.internal/ubuntu questing/main amd64 libffi-dev amd64 3.4.7-1 [65.5 kB] 105s Get:43 http://ftpmaster.internal/ubuntu questing/universe amd64 yosys-dev amd64 0.33-5build2 [88.4 kB] 105s Fetched 80.9 MB in 3s (30.7 MB/s) 105s Selecting previously unselected package libisl23:amd64. 105s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 80522 files and directories currently installed.) 105s Preparing to unpack .../00-libisl23_0.27-1_amd64.deb ... 105s Unpacking libisl23:amd64 (0.27-1) ... 105s Selecting previously unselected package libmpc3:amd64. 105s Preparing to unpack .../01-libmpc3_1.3.1-1build2_amd64.deb ... 105s Unpacking libmpc3:amd64 (1.3.1-1build2) ... 105s Selecting previously unselected package cpp-14-x86-64-linux-gnu. 105s Preparing to unpack .../02-cpp-14-x86-64-linux-gnu_14.2.0-19ubuntu2_amd64.deb ... 105s Unpacking cpp-14-x86-64-linux-gnu (14.2.0-19ubuntu2) ... 106s Selecting previously unselected package cpp-14. 106s Preparing to unpack .../03-cpp-14_14.2.0-19ubuntu2_amd64.deb ... 106s Unpacking cpp-14 (14.2.0-19ubuntu2) ... 106s Selecting previously unselected package cpp-x86-64-linux-gnu. 106s Preparing to unpack .../04-cpp-x86-64-linux-gnu_4%3a14.2.0-1ubuntu1_amd64.deb ... 106s Unpacking cpp-x86-64-linux-gnu (4:14.2.0-1ubuntu1) ... 106s Selecting previously unselected package cpp. 106s Preparing to unpack .../05-cpp_4%3a14.2.0-1ubuntu1_amd64.deb ... 106s Unpacking cpp (4:14.2.0-1ubuntu1) ... 106s Selecting previously unselected package libcc1-0:amd64. 106s Preparing to unpack .../06-libcc1-0_15-20250404-0ubuntu1_amd64.deb ... 106s Unpacking libcc1-0:amd64 (15-20250404-0ubuntu1) ... 106s Selecting previously unselected package libgomp1:amd64. 106s Preparing to unpack .../07-libgomp1_15-20250404-0ubuntu1_amd64.deb ... 106s Unpacking libgomp1:amd64 (15-20250404-0ubuntu1) ... 106s Selecting previously unselected package libitm1:amd64. 106s Preparing to unpack .../08-libitm1_15-20250404-0ubuntu1_amd64.deb ... 106s Unpacking libitm1:amd64 (15-20250404-0ubuntu1) ... 106s Selecting previously unselected package libasan8:amd64. 106s Preparing to unpack .../09-libasan8_15-20250404-0ubuntu1_amd64.deb ... 106s Unpacking libasan8:amd64 (15-20250404-0ubuntu1) ... 106s Selecting previously unselected package liblsan0:amd64. 106s Preparing to unpack .../10-liblsan0_15-20250404-0ubuntu1_amd64.deb ... 106s Unpacking liblsan0:amd64 (15-20250404-0ubuntu1) ... 106s Selecting previously unselected package libtsan2:amd64. 106s Preparing to unpack .../11-libtsan2_15-20250404-0ubuntu1_amd64.deb ... 106s Unpacking libtsan2:amd64 (15-20250404-0ubuntu1) ... 106s Selecting previously unselected package libubsan1:amd64. 106s Preparing to unpack .../12-libubsan1_15-20250404-0ubuntu1_amd64.deb ... 106s Unpacking libubsan1:amd64 (15-20250404-0ubuntu1) ... 106s Selecting previously unselected package libhwasan0:amd64. 106s Preparing to unpack .../13-libhwasan0_15-20250404-0ubuntu1_amd64.deb ... 106s Unpacking libhwasan0:amd64 (15-20250404-0ubuntu1) ... 106s Selecting previously unselected package libquadmath0:amd64. 106s Preparing to unpack .../14-libquadmath0_15-20250404-0ubuntu1_amd64.deb ... 106s Unpacking libquadmath0:amd64 (15-20250404-0ubuntu1) ... 106s Selecting previously unselected package libgcc-14-dev:amd64. 106s Preparing to unpack .../15-libgcc-14-dev_14.2.0-19ubuntu2_amd64.deb ... 106s Unpacking libgcc-14-dev:amd64 (14.2.0-19ubuntu2) ... 106s Selecting previously unselected package gcc-14-x86-64-linux-gnu. 106s Preparing to unpack .../16-gcc-14-x86-64-linux-gnu_14.2.0-19ubuntu2_amd64.deb ... 106s Unpacking gcc-14-x86-64-linux-gnu (14.2.0-19ubuntu2) ... 106s Selecting previously unselected package gcc-14. 106s Preparing to unpack .../17-gcc-14_14.2.0-19ubuntu2_amd64.deb ... 106s Unpacking gcc-14 (14.2.0-19ubuntu2) ... 106s Selecting previously unselected package gcc-x86-64-linux-gnu. 107s Preparing to unpack .../18-gcc-x86-64-linux-gnu_4%3a14.2.0-1ubuntu1_amd64.deb ... 107s Unpacking gcc-x86-64-linux-gnu (4:14.2.0-1ubuntu1) ... 107s Selecting previously unselected package gcc. 107s Preparing to unpack .../19-gcc_4%3a14.2.0-1ubuntu1_amd64.deb ... 107s Unpacking gcc (4:14.2.0-1ubuntu1) ... 107s Selecting previously unselected package libstdc++-14-dev:amd64. 107s Preparing to unpack .../20-libstdc++-14-dev_14.2.0-19ubuntu2_amd64.deb ... 107s Unpacking libstdc++-14-dev:amd64 (14.2.0-19ubuntu2) ... 107s Selecting previously unselected package g++-14-x86-64-linux-gnu. 107s Preparing to unpack .../21-g++-14-x86-64-linux-gnu_14.2.0-19ubuntu2_amd64.deb ... 107s Unpacking g++-14-x86-64-linux-gnu (14.2.0-19ubuntu2) ... 107s Selecting previously unselected package g++-14. 107s Preparing to unpack .../22-g++-14_14.2.0-19ubuntu2_amd64.deb ... 107s Unpacking g++-14 (14.2.0-19ubuntu2) ... 107s Selecting previously unselected package g++-x86-64-linux-gnu. 107s Preparing to unpack .../23-g++-x86-64-linux-gnu_4%3a14.2.0-1ubuntu1_amd64.deb ... 107s Unpacking g++-x86-64-linux-gnu (4:14.2.0-1ubuntu1) ... 107s Selecting previously unselected package g++. 107s Preparing to unpack .../24-g++_4%3a14.2.0-1ubuntu1_amd64.deb ... 107s Unpacking g++ (4:14.2.0-1ubuntu1) ... 107s Selecting previously unselected package iverilog. 107s Preparing to unpack .../25-iverilog_12.0-2build2_amd64.deb ... 107s Unpacking iverilog (12.0-2build2) ... 107s Selecting previously unselected package libncurses-dev:amd64. 107s Preparing to unpack .../26-libncurses-dev_6.5+20250216-2_amd64.deb ... 107s Unpacking libncurses-dev:amd64 (6.5+20250216-2) ... 107s Selecting previously unselected package libpkgconf3:amd64. 107s Preparing to unpack .../27-libpkgconf3_1.8.1-4_amd64.deb ... 107s Unpacking libpkgconf3:amd64 (1.8.1-4) ... 107s Selecting previously unselected package libreadline-dev:amd64. 107s Preparing to unpack .../28-libreadline-dev_8.2-6_amd64.deb ... 107s Unpacking libreadline-dev:amd64 (8.2-6) ... 107s Selecting previously unselected package libtcl8.6:amd64. 107s Preparing to unpack .../29-libtcl8.6_8.6.16+dfsg-1_amd64.deb ... 107s Unpacking libtcl8.6:amd64 (8.6.16+dfsg-1) ... 107s Selecting previously unselected package pkgconf-bin. 107s Preparing to unpack .../30-pkgconf-bin_1.8.1-4_amd64.deb ... 107s Unpacking pkgconf-bin (1.8.1-4) ... 107s Selecting previously unselected package pkgconf:amd64. 107s Preparing to unpack .../31-pkgconf_1.8.1-4_amd64.deb ... 107s Unpacking pkgconf:amd64 (1.8.1-4) ... 107s Selecting previously unselected package pkg-config:amd64. 107s Preparing to unpack .../32-pkg-config_1.8.1-4_amd64.deb ... 107s Unpacking pkg-config:amd64 (1.8.1-4) ... 107s Selecting previously unselected package python3-click. 107s Preparing to unpack .../33-python3-click_8.2.0+0.really.8.1.8-1_all.deb ... 107s Unpacking python3-click (8.2.0+0.really.8.1.8-1) ... 107s Selecting previously unselected package tcl8.6. 107s Preparing to unpack .../34-tcl8.6_8.6.16+dfsg-1_amd64.deb ... 107s Unpacking tcl8.6 (8.6.16+dfsg-1) ... 107s Selecting previously unselected package tcl. 107s Preparing to unpack .../35-tcl_8.6.16_amd64.deb ... 107s Unpacking tcl (8.6.16) ... 107s Selecting previously unselected package zlib1g-dev:amd64. 107s Preparing to unpack .../36-zlib1g-dev_1%3a1.3.dfsg+really1.3.1-1ubuntu1_amd64.deb ... 107s Unpacking zlib1g-dev:amd64 (1:1.3.dfsg+really1.3.1-1ubuntu1) ... 107s Selecting previously unselected package tcl8.6-dev:amd64. 107s Preparing to unpack .../37-tcl8.6-dev_8.6.16+dfsg-1_amd64.deb ... 107s Unpacking tcl8.6-dev:amd64 (8.6.16+dfsg-1) ... 107s Selecting previously unselected package tcl-dev:amd64. 107s Preparing to unpack .../38-tcl-dev_8.6.16_amd64.deb ... 107s Unpacking tcl-dev:amd64 (8.6.16) ... 107s Selecting previously unselected package yosys-abc. 108s Preparing to unpack .../39-yosys-abc_0.33-5build2_amd64.deb ... 108s Unpacking yosys-abc (0.33-5build2) ... 108s Selecting previously unselected package yosys. 108s Preparing to unpack .../40-yosys_0.33-5build2_amd64.deb ... 108s Unpacking yosys (0.33-5build2) ... 108s Selecting previously unselected package libffi-dev:amd64. 108s Preparing to unpack .../41-libffi-dev_3.4.7-1_amd64.deb ... 108s Unpacking libffi-dev:amd64 (3.4.7-1) ... 108s Selecting previously unselected package yosys-dev. 108s Preparing to unpack .../42-yosys-dev_0.33-5build2_amd64.deb ... 108s Unpacking yosys-dev (0.33-5build2) ... 108s Setting up libncurses-dev:amd64 (6.5+20250216-2) ... 108s Setting up yosys-abc (0.33-5build2) ... 108s Setting up libreadline-dev:amd64 (8.2-6) ... 108s Setting up libgomp1:amd64 (15-20250404-0ubuntu1) ... 108s Setting up python3-click (8.2.0+0.really.8.1.8-1) ... 108s Setting up libffi-dev:amd64 (3.4.7-1) ... 108s Setting up iverilog (12.0-2build2) ... 108s Setting up libpkgconf3:amd64 (1.8.1-4) ... 108s Setting up libquadmath0:amd64 (15-20250404-0ubuntu1) ... 108s Setting up libmpc3:amd64 (1.3.1-1build2) ... 108s Setting up libtcl8.6:amd64 (8.6.16+dfsg-1) ... 108s Setting up pkgconf-bin (1.8.1-4) ... 108s Setting up libubsan1:amd64 (15-20250404-0ubuntu1) ... 108s Setting up zlib1g-dev:amd64 (1:1.3.dfsg+really1.3.1-1ubuntu1) ... 108s Setting up libhwasan0:amd64 (15-20250404-0ubuntu1) ... 108s Setting up libasan8:amd64 (15-20250404-0ubuntu1) ... 108s Setting up libtsan2:amd64 (15-20250404-0ubuntu1) ... 108s Setting up libisl23:amd64 (0.27-1) ... 108s Setting up libcc1-0:amd64 (15-20250404-0ubuntu1) ... 108s Setting up liblsan0:amd64 (15-20250404-0ubuntu1) ... 108s Setting up libitm1:amd64 (15-20250404-0ubuntu1) ... 108s Setting up tcl8.6 (8.6.16+dfsg-1) ... 108s Setting up tcl8.6-dev:amd64 (8.6.16+dfsg-1) ... 108s Setting up yosys (0.33-5build2) ... 108s Setting up pkgconf:amd64 (1.8.1-4) ... 108s Setting up pkg-config:amd64 (1.8.1-4) ... 108s Setting up cpp-14-x86-64-linux-gnu (14.2.0-19ubuntu2) ... 108s Setting up cpp-14 (14.2.0-19ubuntu2) ... 108s Setting up tcl (8.6.16) ... 108s Setting up libgcc-14-dev:amd64 (14.2.0-19ubuntu2) ... 108s Setting up libstdc++-14-dev:amd64 (14.2.0-19ubuntu2) ... 108s Setting up cpp-x86-64-linux-gnu (4:14.2.0-1ubuntu1) ... 108s Setting up tcl-dev:amd64 (8.6.16) ... 108s Setting up cpp (4:14.2.0-1ubuntu1) ... 108s Setting up gcc-14-x86-64-linux-gnu (14.2.0-19ubuntu2) ... 108s Setting up yosys-dev (0.33-5build2) ... 108s Setting up gcc-x86-64-linux-gnu (4:14.2.0-1ubuntu1) ... 108s Setting up gcc-14 (14.2.0-19ubuntu2) ... 108s Setting up g++-14-x86-64-linux-gnu (14.2.0-19ubuntu2) ... 108s Setting up g++-x86-64-linux-gnu (4:14.2.0-1ubuntu1) ... 108s Setting up g++-14 (14.2.0-19ubuntu2) ... 108s Setting up gcc (4:14.2.0-1ubuntu1) ... 108s Setting up g++ (4:14.2.0-1ubuntu1) ... 108s update-alternatives: using /usr/bin/g++ to provide /usr/bin/c++ (c++) in auto mode 108s Processing triggers for libc-bin (2.41-6ubuntu1) ... 108s Processing triggers for man-db (2.13.1-1) ... 109s Processing triggers for install-info (7.1.1-1) ... 111s autopkgtest [22:19:57]: test yosys-testsuite: [----------------------- 111s + [ 1 -ge 1 ] 111s + testdir=. 111s + shift 111s + mkdir -p . 111s + cd . 111s + ln -sf /usr/bin/yosys . 111s + ln -sf /usr/bin/yosys-abc . 111s + ln -sf /usr/bin/yosys-config . 111s + sed -i s/^test:.*/test: $(EXTRA_TARGETS)/ Makefile 111s + make test CONFIG=gcc ABCPULL=0 111s mkdir -p share/include/kernel/ 111s cp "./"/kernel/yosys.h share/include/kernel/yosys.h 111s mkdir -p share/include/kernel/ 111s cp "./"/kernel/hashlib.h share/include/kernel/hashlib.h 111s mkdir -p share/include/kernel/ 111s cp "./"/kernel/log.h share/include/kernel/log.h 111s mkdir -p share/include/kernel/ 111s cp "./"/kernel/rtlil.h share/include/kernel/rtlil.h 111s mkdir -p share/include/kernel/ 111s cp "./"/kernel/binding.h share/include/kernel/binding.h 111s mkdir -p share/include/kernel/ 111s cp "./"/kernel/register.h share/include/kernel/register.h 111s mkdir -p share/include/kernel/ 111s cp "./"/kernel/cellaigs.h share/include/kernel/cellaigs.h 111s mkdir -p share/include/kernel/ 111s cp "./"/kernel/celltypes.h share/include/kernel/celltypes.h 111s mkdir -p share/include/kernel/ 111s cp "./"/kernel/celledges.h share/include/kernel/celledges.h 111s mkdir -p share/include/kernel/ 111s cp "./"/kernel/consteval.h share/include/kernel/consteval.h 111s mkdir -p share/include/kernel/ 111s cp "./"/kernel/constids.inc share/include/kernel/constids.inc 111s mkdir -p share/include/kernel/ 111s cp "./"/kernel/sigtools.h share/include/kernel/sigtools.h 111s mkdir -p share/include/kernel/ 111s cp "./"/kernel/modtools.h share/include/kernel/modtools.h 111s mkdir -p share/include/kernel/ 111s cp "./"/kernel/macc.h share/include/kernel/macc.h 111s mkdir -p share/include/kernel/ 111s cp "./"/kernel/utils.h share/include/kernel/utils.h 111s mkdir -p share/include/kernel/ 111s cp "./"/kernel/satgen.h share/include/kernel/satgen.h 111s mkdir -p share/include/kernel/ 111s cp "./"/kernel/qcsat.h share/include/kernel/qcsat.h 111s mkdir -p share/include/kernel/ 111s cp "./"/kernel/ff.h share/include/kernel/ff.h 111s mkdir -p share/include/kernel/ 111s cp "./"/kernel/ffinit.h share/include/kernel/ffinit.h 111s mkdir -p share/include/kernel/ 111s cp "./"/kernel/fstdata.h share/include/kernel/fstdata.h 111s mkdir -p share/include/kernel/ 111s cp "./"/kernel/mem.h share/include/kernel/mem.h 111s mkdir -p share/include/kernel/ 111s cp "./"/kernel/yw.h share/include/kernel/yw.h 111s mkdir -p share/include/kernel/ 111s cp "./"/kernel/json.h share/include/kernel/json.h 111s mkdir -p share/include/libs/ezsat/ 111s cp "./"/libs/ezsat/ezsat.h share/include/libs/ezsat/ezsat.h 111s mkdir -p share/include/libs/ezsat/ 111s cp "./"/libs/ezsat/ezminisat.h share/include/libs/ezsat/ezminisat.h 111s mkdir -p share/include/libs/fst/ 111s cp "./"/libs/fst/fstapi.h share/include/libs/fst/fstapi.h 111s mkdir -p share/include/libs/sha1/ 111s cp "./"/libs/sha1/sha1.h share/include/libs/sha1/sha1.h 111s mkdir -p share/include/libs/json11/ 111s cp "./"/libs/json11/json11.hpp share/include/libs/json11/json11.hpp 111s mkdir -p share/include/passes/fsm/ 111s cp "./"/passes/fsm/fsmdata.h share/include/passes/fsm/fsmdata.h 111s mkdir -p share/include/frontends/ast/ 111s cp "./"/frontends/ast/ast.h share/include/frontends/ast/ast.h 111s mkdir -p share/include/frontends/ast/ 111s cp "./"/frontends/ast/ast_binding.h share/include/frontends/ast/ast_binding.h 111s mkdir -p share/include/frontends/blif/ 111s cp "./"/frontends/blif/blifparse.h share/include/frontends/blif/blifparse.h 111s mkdir -p share/include/backends/rtlil/ 111s cp "./"/backends/rtlil/rtlil_backend.h share/include/backends/rtlil/rtlil_backend.h 111s mkdir -p share/include/backends/cxxrtl/ 111s cp "./"/backends/cxxrtl/cxxrtl.h share/include/backends/cxxrtl/cxxrtl.h 111s mkdir -p share/include/backends/cxxrtl/ 111s cp "./"/backends/cxxrtl/cxxrtl_vcd.h share/include/backends/cxxrtl/cxxrtl_vcd.h 111s mkdir -p share/include/backends/cxxrtl/ 111s cp "./"/backends/cxxrtl/cxxrtl_capi.cc share/include/backends/cxxrtl/cxxrtl_capi.cc 111s mkdir -p share/include/backends/cxxrtl/ 111s cp "./"/backends/cxxrtl/cxxrtl_capi.h share/include/backends/cxxrtl/cxxrtl_capi.h 111s mkdir -p share/include/backends/cxxrtl/ 111s cp "./"/backends/cxxrtl/cxxrtl_vcd_capi.cc share/include/backends/cxxrtl/cxxrtl_vcd_capi.cc 111s mkdir -p share/include/backends/cxxrtl/ 111s cp "./"/backends/cxxrtl/cxxrtl_vcd_capi.h share/include/backends/cxxrtl/cxxrtl_vcd_capi.h 111s mkdir -p share/python3 111s cp "./"/backends/smt2/smtio.py share/python3/smtio.py 111s mkdir -p share/python3 111s cp "./"/backends/smt2/ywio.py share/python3/ywio.py 111s mkdir -p share/achronix/speedster22i/ 111s cp "./"/techlibs/achronix/speedster22i/cells_sim.v share/achronix/speedster22i/cells_sim.v 111s mkdir -p share/achronix/speedster22i/ 111s cp "./"/techlibs/achronix/speedster22i/cells_map.v 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cp "./"/techlibs/coolrunner2/cells_latch.v share/coolrunner2/cells_latch.v 111s mkdir -p share/coolrunner2 111s cp "./"/techlibs/coolrunner2/cells_sim.v share/coolrunner2/cells_sim.v 111s mkdir -p share/coolrunner2 111s cp "./"/techlibs/coolrunner2/cells_counter_map.v share/coolrunner2/cells_counter_map.v 111s mkdir -p share/coolrunner2 111s cp "./"/techlibs/coolrunner2/tff_extract.v share/coolrunner2/tff_extract.v 111s mkdir -p share/coolrunner2 111s cp "./"/techlibs/coolrunner2/xc2_dff.lib share/coolrunner2/xc2_dff.lib 111s mkdir -p share/ecp5 111s cp "./"/techlibs/ecp5/cells_ff.vh share/ecp5/cells_ff.vh 111s mkdir -p share/ecp5 111s cp "./"/techlibs/ecp5/cells_io.vh share/ecp5/cells_io.vh 111s mkdir -p share/ecp5 111s cp "./"/techlibs/ecp5/cells_map.v share/ecp5/cells_map.v 111s mkdir -p share/ecp5 111s cp "./"/techlibs/ecp5/cells_sim.v share/ecp5/cells_sim.v 111s mkdir -p share/ecp5 111s cp "./"/techlibs/ecp5/cells_bb.v share/ecp5/cells_bb.v 111s mkdir -p share/ecp5 111s cp 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"./"/techlibs/efinix/gbuf_map.v share/efinix/gbuf_map.v 111s mkdir -p share/efinix 111s cp "./"/techlibs/efinix/brams.txt share/efinix/brams.txt 111s mkdir -p share/fabulous 111s cp "./"/techlibs/fabulous/cells_map.v share/fabulous/cells_map.v 111s mkdir -p share/fabulous 111s cp "./"/techlibs/fabulous/prims.v share/fabulous/prims.v 111s mkdir -p share/fabulous 111s cp "./"/techlibs/fabulous/latches_map.v share/fabulous/latches_map.v 111s mkdir -p share/fabulous 111s cp "./"/techlibs/fabulous/ff_map.v share/fabulous/ff_map.v 111s mkdir -p share/fabulous 111s cp "./"/techlibs/fabulous/ram_regfile.txt share/fabulous/ram_regfile.txt 111s mkdir -p share/fabulous 111s cp "./"/techlibs/fabulous/regfile_map.v share/fabulous/regfile_map.v 111s mkdir -p share/fabulous 111s cp "./"/techlibs/fabulous/io_map.v share/fabulous/io_map.v 111s mkdir -p share/fabulous 111s cp "./"/techlibs/fabulous/arith_map.v share/fabulous/arith_map.v 111s mkdir -p share/gatemate 111s cp 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"./"/techlibs/gatemate/brams_init_40.vh share/gatemate/brams_init_40.vh 111s mkdir -p share/gatemate 111s cp "./"/techlibs/gatemate/inv_map.v share/gatemate/inv_map.v 111s mkdir -p techlibs/gatemate 111s python3 techlibs/gatemate/make_lut_tree_lib.py 111s touch techlibs/gatemate/lut_tree_lib.mk 111s mkdir -p share/gatemate 111s cp techlibs/gatemate/lut_tree_cells.genlib share/gatemate/lut_tree_cells.genlib 111s mkdir -p share/gatemate 111s cp techlibs/gatemate/lut_tree_map.v share/gatemate/lut_tree_map.v 111s mkdir -p share/gowin 111s cp "./"/techlibs/gowin/cells_map.v share/gowin/cells_map.v 111s mkdir -p share/gowin 111s cp "./"/techlibs/gowin/cells_sim.v share/gowin/cells_sim.v 111s mkdir -p share/gowin 111s cp "./"/techlibs/gowin/cells_xtra.v share/gowin/cells_xtra.v 111s mkdir -p share/gowin 111s cp "./"/techlibs/gowin/arith_map.v share/gowin/arith_map.v 111s mkdir -p share/gowin 111s cp "./"/techlibs/gowin/brams_map.v share/gowin/brams_map.v 111s mkdir -p share/gowin 111s cp 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cp "./"/techlibs/intel_alm/common/alm_map.v share/intel_alm/common/alm_map.v 112s mkdir -p share/intel_alm/common 112s cp "./"/techlibs/intel_alm/common/alm_sim.v share/intel_alm/common/alm_sim.v 112s mkdir -p share/intel_alm/common 112s cp "./"/techlibs/intel_alm/common/arith_alm_map.v share/intel_alm/common/arith_alm_map.v 112s mkdir -p share/intel_alm/common 112s cp "./"/techlibs/intel_alm/common/dff_map.v share/intel_alm/common/dff_map.v 112s mkdir -p share/intel_alm/common 112s cp "./"/techlibs/intel_alm/common/dff_sim.v share/intel_alm/common/dff_sim.v 112s mkdir -p share/intel_alm/common 112s cp "./"/techlibs/intel_alm/common/dsp_sim.v share/intel_alm/common/dsp_sim.v 112s mkdir -p share/intel_alm/common 112s cp "./"/techlibs/intel_alm/common/dsp_map.v share/intel_alm/common/dsp_map.v 112s mkdir -p share/intel_alm/common 112s cp "./"/techlibs/intel_alm/common/mem_sim.v share/intel_alm/common/mem_sim.v 112s mkdir -p share/intel_alm/common 112s cp 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share/intel_alm/common 112s cp "./"/techlibs/intel_alm/common/quartus_rename.v share/intel_alm/common/quartus_rename.v 112s mkdir -p share/lattice 112s cp "./"/techlibs/lattice/cells_ff.vh share/lattice/cells_ff.vh 112s mkdir -p share/lattice 112s cp "./"/techlibs/lattice/cells_io.vh share/lattice/cells_io.vh 112s mkdir -p share/lattice 112s cp "./"/techlibs/lattice/cells_map.v share/lattice/cells_map.v 112s mkdir -p share/lattice 112s cp "./"/techlibs/lattice/common_sim.vh share/lattice/common_sim.vh 112s mkdir -p share/lattice 112s cp "./"/techlibs/lattice/ccu2d_sim.vh share/lattice/ccu2d_sim.vh 112s mkdir -p share/lattice 112s cp "./"/techlibs/lattice/ccu2c_sim.vh share/lattice/ccu2c_sim.vh 112s mkdir -p share/lattice 112s cp "./"/techlibs/lattice/cells_sim_ecp5.v share/lattice/cells_sim_ecp5.v 112s mkdir -p share/lattice 112s cp "./"/techlibs/lattice/cells_sim_xo2.v share/lattice/cells_sim_xo2.v 112s mkdir -p share/lattice 112s cp "./"/techlibs/lattice/cells_sim_xo3.v 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"./"/techlibs/nexus/lutrams_map.v share/nexus/lutrams_map.v 112s mkdir -p share/nexus 112s cp "./"/techlibs/nexus/lutrams.txt share/nexus/lutrams.txt 112s mkdir -p share/nexus 112s cp "./"/techlibs/nexus/brams_map.v share/nexus/brams_map.v 112s mkdir -p share/nexus 112s cp "./"/techlibs/nexus/brams.txt share/nexus/brams.txt 112s mkdir -p share/nexus 112s cp "./"/techlibs/nexus/lrams_map.v share/nexus/lrams_map.v 112s mkdir -p share/nexus 112s cp "./"/techlibs/nexus/lrams.txt share/nexus/lrams.txt 112s mkdir -p share/nexus 112s cp "./"/techlibs/nexus/arith_map.v share/nexus/arith_map.v 112s mkdir -p share/nexus 112s cp "./"/techlibs/nexus/latches_map.v share/nexus/latches_map.v 112s mkdir -p share/nexus 112s cp "./"/techlibs/nexus/dsp_map.v share/nexus/dsp_map.v 112s mkdir -p share/quicklogic 112s cp "./"/techlibs/quicklogic/pp3_ffs_map.v share/quicklogic/pp3_ffs_map.v 112s mkdir -p share/quicklogic 112s cp "./"/techlibs/quicklogic/pp3_lut_map.v share/quicklogic/pp3_lut_map.v 112s mkdir -p share/quicklogic 112s cp "./"/techlibs/quicklogic/pp3_latches_map.v share/quicklogic/pp3_latches_map.v 112s mkdir -p share/quicklogic 112s cp "./"/techlibs/quicklogic/pp3_cells_map.v share/quicklogic/pp3_cells_map.v 112s mkdir -p share/quicklogic 112s cp "./"/techlibs/quicklogic/cells_sim.v share/quicklogic/cells_sim.v 112s mkdir -p share/quicklogic 112s cp "./"/techlibs/quicklogic/lut_sim.v share/quicklogic/lut_sim.v 112s mkdir -p share/quicklogic 112s cp "./"/techlibs/quicklogic/pp3_cells_sim.v share/quicklogic/pp3_cells_sim.v 112s mkdir -p share/quicklogic 112s cp "./"/techlibs/quicklogic/abc9_model.v share/quicklogic/abc9_model.v 112s mkdir -p share/quicklogic 112s cp "./"/techlibs/quicklogic/abc9_map.v share/quicklogic/abc9_map.v 112s mkdir -p share/quicklogic 112s cp "./"/techlibs/quicklogic/abc9_unmap.v share/quicklogic/abc9_unmap.v 112s mkdir -p share/sf2 112s cp "./"/techlibs/sf2/arith_map.v share/sf2/arith_map.v 112s mkdir -p share/sf2 112s cp "./"/techlibs/sf2/cells_map.v share/sf2/cells_map.v 112s mkdir -p share/sf2 112s cp "./"/techlibs/sf2/cells_sim.v share/sf2/cells_sim.v 112s mkdir -p share/xilinx 112s cp "./"/techlibs/xilinx/cells_map.v share/xilinx/cells_map.v 112s mkdir -p share/xilinx 112s cp "./"/techlibs/xilinx/cells_sim.v share/xilinx/cells_sim.v 112s mkdir -p share/xilinx 112s cp "./"/techlibs/xilinx/cells_xtra.v share/xilinx/cells_xtra.v 112s mkdir -p share/xilinx 112s cp "./"/techlibs/xilinx/lutrams_xcv.txt share/xilinx/lutrams_xcv.txt 112s mkdir -p share/xilinx 112s cp "./"/techlibs/xilinx/lutrams_xcv_map.v share/xilinx/lutrams_xcv_map.v 112s mkdir -p share/xilinx 112s cp "./"/techlibs/xilinx/lutrams_xc5v.txt share/xilinx/lutrams_xc5v.txt 112s mkdir -p share/xilinx 112s cp "./"/techlibs/xilinx/lutrams_xcu.txt share/xilinx/lutrams_xcu.txt 112s mkdir -p share/xilinx 112s cp "./"/techlibs/xilinx/lutrams_xc5v_map.v share/xilinx/lutrams_xc5v_map.v 112s mkdir -p share/xilinx 112s cp "./"/techlibs/xilinx/brams_xcv.txt share/xilinx/brams_xcv.txt 112s mkdir -p share/xilinx 112s cp "./"/techlibs/xilinx/brams_xcv_map.v share/xilinx/brams_xcv_map.v 112s mkdir -p share/xilinx 112s cp "./"/techlibs/xilinx/brams_defs.vh share/xilinx/brams_defs.vh 112s mkdir -p share/xilinx 112s cp "./"/techlibs/xilinx/brams_xc2v.txt share/xilinx/brams_xc2v.txt 112s mkdir -p share/xilinx 112s cp "./"/techlibs/xilinx/brams_xc2v_map.v share/xilinx/brams_xc2v_map.v 112s mkdir -p share/xilinx 112s cp "./"/techlibs/xilinx/brams_xc3sda.txt share/xilinx/brams_xc3sda.txt 112s mkdir -p share/xilinx 112s cp "./"/techlibs/xilinx/brams_xc3sda_map.v share/xilinx/brams_xc3sda_map.v 112s mkdir -p share/xilinx 112s cp "./"/techlibs/xilinx/brams_xc4v.txt share/xilinx/brams_xc4v.txt 112s mkdir -p share/xilinx 112s cp "./"/techlibs/xilinx/brams_xc4v_map.v share/xilinx/brams_xc4v_map.v 112s mkdir -p share/xilinx 112s cp "./"/techlibs/xilinx/brams_xc5v_map.v share/xilinx/brams_xc5v_map.v 112s mkdir -p share/xilinx 112s cp "./"/techlibs/xilinx/brams_xc6v_map.v share/xilinx/brams_xc6v_map.v 112s mkdir -p share/xilinx 112s cp "./"/techlibs/xilinx/brams_xcu_map.v share/xilinx/brams_xcu_map.v 112s mkdir -p share/xilinx 112s cp "./"/techlibs/xilinx/urams.txt share/xilinx/urams.txt 112s mkdir -p share/xilinx 112s cp "./"/techlibs/xilinx/urams_map.v share/xilinx/urams_map.v 112s mkdir -p share/xilinx 112s cp "./"/techlibs/xilinx/arith_map.v share/xilinx/arith_map.v 112s mkdir -p share/xilinx 112s cp "./"/techlibs/xilinx/ff_map.v share/xilinx/ff_map.v 112s mkdir -p share/xilinx 112s cp "./"/techlibs/xilinx/lut_map.v share/xilinx/lut_map.v 112s mkdir -p share/xilinx 112s cp "./"/techlibs/xilinx/mux_map.v share/xilinx/mux_map.v 112s mkdir -p share/xilinx 112s cp "./"/techlibs/xilinx/xc3s_mult_map.v share/xilinx/xc3s_mult_map.v 112s mkdir -p share/xilinx 112s cp "./"/techlibs/xilinx/xc3sda_dsp_map.v share/xilinx/xc3sda_dsp_map.v 112s mkdir -p share/xilinx 112s cp "./"/techlibs/xilinx/xc6s_dsp_map.v share/xilinx/xc6s_dsp_map.v 112s mkdir -p share/xilinx 112s cp "./"/techlibs/xilinx/xc4v_dsp_map.v share/xilinx/xc4v_dsp_map.v 112s mkdir -p share/xilinx 112s cp "./"/techlibs/xilinx/xc5v_dsp_map.v share/xilinx/xc5v_dsp_map.v 112s mkdir -p share/xilinx 112s cp "./"/techlibs/xilinx/xc7_dsp_map.v share/xilinx/xc7_dsp_map.v 112s mkdir -p share/xilinx 112s cp "./"/techlibs/xilinx/xcu_dsp_map.v share/xilinx/xcu_dsp_map.v 112s mkdir -p share/xilinx 112s cp "./"/techlibs/xilinx/abc9_model.v share/xilinx/abc9_model.v 112s cd tests/simple && bash run-test.sh "" 112s make[1]: Entering directory '/tmp/autopkgtest.JGlVyS/build.mfJ/src/tests/simple' 112s + gcc -Wall -o /tmp/autopkgtest.JGlVyS/build.mfJ/src/tests/tools/cmp_tbdata /tmp/autopkgtest.JGlVyS/build.mfJ/src/tests/tools/cmp_tbdata.c 112s Test: arrays02 -> ok 114s Test: asgn_binop -> ok 114s Test: case_expr_extend -> ok 115s Test: case_expr_query -> ok 115s Test: defvalue -> ok 115s Test: implicit_ports -> ok 116s Test: lesser_size_cast -> ok 116s Test: local_loop_var -> ok 116s Test: macro_arg_spaces -> ok 116s Test: matching_end_labels -> ok 117s Test: memwr_port_connection -> ok 117s Test: unnamed_block_decl -> ok 117s Test: aes_kexp128 -> ok 117s Test: always01 -> ok 118s Test: always02 -> ok 118s Test: always03 -> ok 119s Test: arraycells -> ok 119s Test: arrays01 -> ok 119s Test: attrib01_module -> ok 120s Test: attrib02_port_decl -> ok 120s Test: attrib03_parameter -> ok 120s Test: attrib04_net_var -> ok 121s Test: attrib06_operator_suffix -> ok 121s Test: attrib08_mod_inst -> ok 121s Test: attrib09_case -> ok 122s Test: carryadd -> ok 122s Test: case_expr_const -> ok 122s Test: case_expr_non_const -> ok 129s Test: case_large -> ok 129s Test: const_branch_finish -> ok 130s Test: const_fold_func -> ok 130s Test: const_func_shadow -> ok 132s Test: constmuldivmod -> ok 132s Test: constpower -> ok 133s Test: dff_different_styles -> ok 134s Test: dff_init -> ok 136s Test: dynslice -> ok 136s Test: fiedler-cooley -> ok 137s Test: forgen01 -> ok 137s Test: forgen02 -> ok 137s Test: forloops -> ok 138s Test: fsm -> ok 138s Test: func_block -> ok 139s Test: func_recurse -> ok 139s Test: func_width_scope -> ok 139s Test: genblk_collide -> ok 140s Test: genblk_dive -> ok 140s Test: genblk_order -> ok 140s Test: genblk_port_shadow -> ok 142s Test: generate -> ok 143s Test: graphtest -> ok 143s Test: hierarchy -> ok 143s Test: hierdefparam -> ok 144s Test: i2c_master_tests -> ok 144s Test: ifdef_1 -> ok 144s Test: ifdef_2 -> ok 144s Test: localparam_attr -> ok 145s Test: loop_prefix_case -> ok 145s Test: loop_var_shadow -> ok 145s Test: loops -> ok 145s Test: macro_arg_surrounding_spaces -> ok 146s Test: macros -> ok 147s Test: mem2reg -> ok 148s Test: mem2reg_bounds_tern -> ok 149s Test: mem_arst -> ok 155s Test: memory -> ok 155s Test: module_scope -> ok 155s Test: module_scope_case -> ok 155s Test: module_scope_func -> ok 156s Test: multiplier -> ok 157s Test: muxtree -> ok 157s Test: named_genblk -> ok 157s Test: nested_genblk_resolve -> ok 157s Test: omsp_dbg_uart -> ok 161s Test: operators -> ok 161s Test: param_attr -> ok 162s Test: paramods -> ok 166s Test: partsel -> ok 167s Test: process -> ok 167s Test: realexpr -> ok 168s Test: repwhile -> ok 168s Test: retime -> ok 172s Test: rotate -> ok 172s Test: scopes -> ok 173s Test: signed_full_slice -> ok 173s Test: signedexpr -> ok 175s Test: sincos -> ok 175s Test: specify -> ok 175s Test: string_format -> ok 176s Test: subbytes -> ok 177s Test: task_func -> ok 177s Test: undef_eqx_nex -> ok 177s Test: usb_phy_tests -> ok 178s Test: values -> ok 178s Test: verilog_primitives -> ok 179s Test: vloghammer -> ok 179s Test: wandwor -> ok 180s Test: wreduce -> ok 180s make[1]: Leaving directory '/tmp/autopkgtest.JGlVyS/build.mfJ/src/tests/simple' 180s cd tests/simple_abc9 && bash run-test.sh "" 180s ls: cannot access '*.sv': No such file or directory 180s make[1]: Entering directory '/tmp/autopkgtest.JGlVyS/build.mfJ/src/tests/simple_abc9' 182s Test: abc9 -> ok 183s Test: aes_kexp128 -> ok 183s Test: always01 -> ok 183s Test: always02 -> ok 183s Test: always03 -> ok 183s Test: arraycells -> ok 184s Test: arrays01 -> ok 184s Test: attrib01_module -> ok 184s Test: attrib02_port_decl -> ok 184s Test: attrib03_parameter -> ok 185s Test: attrib04_net_var -> ok 185s Test: attrib06_operator_suffix -> ok 185s Test: attrib08_mod_inst -> ok 186s Test: attrib09_case -> ok 186s Test: carryadd -> ok 186s Test: case_expr_const -> ok 186s Test: case_expr_non_const -> ok 200s Test: case_large -> ok 200s Test: const_branch_finish -> ok 200s Test: const_fold_func -> ok 200s Test: const_func_shadow -> ok 203s Test: constmuldivmod -> ok 203s Test: constpower -> ok 203s Test: dff_different_styles -> ok 204s Test: dff_init -> ok 211s Test: dynslice -> ok 211s Test: fiedler-cooley -> ok 211s Test: forgen01 -> ok 212s Test: forgen02 -> ok 212s Test: forloops -> ok 212s Test: fsm -> ok 213s Test: func_block -> ok 213s Test: func_recurse -> ok 213s Test: func_width_scope -> ok 213s Test: genblk_collide -> ok 213s Test: genblk_dive -> ok 214s Test: genblk_order -> ok 214s Test: genblk_port_shadow -> ok 215s Test: generate -> ok 216s Test: graphtest -> ok 216s Test: hierarchy -> ok 216s Test: hierdefparam -> ok 217s Test: i2c_master_tests -> ok 217s Test: ifdef_1 -> ok 217s Test: ifdef_2 -> ok 217s Test: localparam_attr -> ok 217s Test: loop_prefix_case -> ok 218s Test: loop_var_shadow -> ok 218s Test: loops -> ok 218s Test: macro_arg_surrounding_spaces -> ok 219s Test: macros -> ok 219s Test: mem2reg -> ok 220s Test: mem2reg_bounds_tern -> ok 220s Test: mem_arst -> ok 223s Test: memory -> ok 224s Test: module_scope -> ok 224s Test: module_scope_case -> ok 224s Test: module_scope_func -> ok 225s Test: multiplier -> ok 225s Test: muxtree -> ok 225s Test: named_genblk -> ok 225s Test: nested_genblk_resolve -> ok 226s Test: omsp_dbg_uart -> ok 231s Test: operators -> ok 231s Test: param_attr -> ok 232s Test: paramods -> ok 237s Test: partsel -> ok 237s Test: process -> ok 237s Test: realexpr -> ok 238s Test: repwhile -> ok 238s Test: retime -> ok 240s Test: rotate -> ok 240s Test: scopes -> ok 240s Test: signed_full_slice -> ok 241s Test: signedexpr -> ok 243s Test: sincos -> ok 243s Test: string_format -> ok 243s Test: subbytes -> ok 244s Test: task_func -> ok 244s Test: undef_eqx_nex -> ok 244s Test: usb_phy_tests -> ok 245s Test: values -> ok 245s Test: verilog_primitives -> ok 246s Test: vloghammer -> ok 246s Test: wandwor -> ok 247s Test: wreduce -> ok 248s Test: arrays02 -> ok 249s Test: asgn_binop -> ok 249s Test: case_expr_extend -> ok 249s Test: case_expr_query -> ok 250s Test: defvalue -> ok 250s Test: implicit_ports -> ok 250s Test: lesser_size_cast -> ok 250s Test: local_loop_var -> ok 251s Test: macro_arg_spaces -> ok 252s Test: matching_end_labels -> ok 252s Test: memwr_port_connection -> ok 252s Test: unnamed_block_decl -> ok 252s make[1]: Leaving directory '/tmp/autopkgtest.JGlVyS/build.mfJ/src/tests/simple_abc9' 252s cd tests/hana && bash run-test.sh "" 252s make[1]: Entering directory '/tmp/autopkgtest.JGlVyS/build.mfJ/src/tests/hana' 255s Test: test_intermout -> ok 256s Test: test_parse2synthtrans -> ok 256s Test: test_parser -> ok 257s Test: test_simulation_always -> ok 258s Test: test_simulation_and -> ok 258s Test: test_simulation_buffer -> ok 259s Test: test_simulation_decoder -> ok 260s Test: test_simulation_inc -> ok 261s Test: test_simulation_mux -> ok 261s Test: test_simulation_nand -> ok 262s Test: test_simulation_nor -> ok 262s Test: test_simulation_or -> ok 262s Test: test_simulation_seq -> ok 265s Test: test_simulation_shifter -> ok 265s Test: test_simulation_sop -> ok 266s Test: test_simulation_techmap -> ok 269s Test: test_simulation_techmap_tech -> ok 269s Test: test_simulation_vlib -> ok 269s Test: test_simulation_xnor -> ok 270s Test: test_simulation_xor -> ok 270s make[1]: Leaving directory '/tmp/autopkgtest.JGlVyS/build.mfJ/src/tests/hana' 270s cd tests/asicworld && bash run-test.sh "" 270s make[1]: Entering directory '/tmp/autopkgtest.JGlVyS/build.mfJ/src/tests/asicworld' 270s Test: code_hdl_models_GrayCounter -> ok 270s Test: code_hdl_models_arbiter -> ok 277s Test: code_hdl_models_cam -> ok 277s Test: code_hdl_models_clk_div -> ok 277s Test: code_hdl_models_clk_div_45 -> ok 278s Test: code_hdl_models_d_ff_gates -> ok 278s Test: code_hdl_models_d_latch_gates -> ok 278s Test: code_hdl_models_decoder_2to4_gates -> ok 278s Test: code_hdl_models_decoder_using_assign -> ok 279s Test: code_hdl_models_decoder_using_case -> ok 279s Test: code_hdl_models_dff_async_reset -> ok 279s Test: code_hdl_models_dff_sync_reset -> ok 279s Test: code_hdl_models_encoder_4to2_gates -> ok 280s Test: code_hdl_models_encoder_using_case -> ok 280s Test: code_hdl_models_encoder_using_if -> ok 280s Test: code_hdl_models_full_adder_gates -> ok 281s Test: code_hdl_models_full_subtracter_gates -> ok 281s Test: code_hdl_models_gray_counter -> ok 281s Test: code_hdl_models_half_adder_gates -> ok 281s Test: code_hdl_models_lfsr -> ok 282s Test: code_hdl_models_lfsr_updown -> ok 282s Test: code_hdl_models_mux_2to1_gates -> ok 282s Test: code_hdl_models_mux_using_assign -> ok 282s Test: code_hdl_models_mux_using_case -> ok 283s Test: code_hdl_models_mux_using_if -> ok 283s Test: code_hdl_models_one_hot_cnt -> ok 283s Test: code_hdl_models_parallel_crc -> ok 284s Test: code_hdl_models_parity_using_assign -> ok 284s Test: code_hdl_models_parity_using_bitwise -> ok 284s Test: code_hdl_models_parity_using_function -> ok 285s Test: code_hdl_models_pri_encoder_using_assign -> ok 285s Test: code_hdl_models_rom_using_case -> ok 285s Test: code_hdl_models_serial_crc -> ok 285s Test: code_hdl_models_tff_async_reset -> ok 286s Test: code_hdl_models_tff_sync_reset -> ok 287s Test: code_hdl_models_uart -> ok 287s Test: code_hdl_models_up_counter -> ok 288s Test: code_hdl_models_up_counter_load -> ok 288s Test: code_hdl_models_up_down_counter -> ok 288s Test: code_specman_switch_fabric -> ok 289s Test: code_tidbits_asyn_reset -> ok 289s Test: code_tidbits_blocking -> ok 289s Test: code_tidbits_fsm_using_always -> ok 290s Test: code_tidbits_fsm_using_function -> ok 290s Test: code_tidbits_fsm_using_single_always -> ok 290s Test: code_tidbits_nonblocking -> ok 291s Test: code_tidbits_reg_combo_example -> ok 291s Test: code_tidbits_reg_seq_example -> ok 291s Test: code_tidbits_syn_reset -> ok 291s Test: code_tidbits_wire_example -> ok 292s Test: code_verilog_tutorial_addbit -> ok 292s Test: code_verilog_tutorial_always_example -> ok 292s Test: code_verilog_tutorial_bus_con -> ok 292s Test: code_verilog_tutorial_comment -> ok 292s Test: code_verilog_tutorial_counter -> ok 293s Test: code_verilog_tutorial_d_ff -> ok 293s Test: code_verilog_tutorial_decoder -> ok 293s Test: code_verilog_tutorial_decoder_always -> ok 293s Test: code_verilog_tutorial_escape_id -> ok 294s Test: code_verilog_tutorial_explicit -> ok 294s Test: code_verilog_tutorial_first_counter -> ok 294s Test: code_verilog_tutorial_flip_flop -> ok 295s Test: code_verilog_tutorial_fsm_full -> ok 295s Test: code_verilog_tutorial_good_code -> ok 295s Test: code_verilog_tutorial_if_else -> ok 295s Test: code_verilog_tutorial_multiply -> ok 296s Test: code_verilog_tutorial_mux_21 -> ok 296s Test: code_verilog_tutorial_n_out_primitive -> ok 296s Test: code_verilog_tutorial_parallel_if -> ok 296s Test: code_verilog_tutorial_parity -> ok 297s Test: code_verilog_tutorial_simple_function -> ok 297s Test: code_verilog_tutorial_simple_if -> ok 297s Test: code_verilog_tutorial_task_global -> ok 297s Test: code_verilog_tutorial_tri_buf -> ok 297s Test: code_verilog_tutorial_v2k_reg -> ok 298s Test: code_verilog_tutorial_which_clock -> ok 298s make[1]: Leaving directory '/tmp/autopkgtest.JGlVyS/build.mfJ/src/tests/asicworld' 298s # +cd tests/realmath && bash run-test.sh "" 298s cd tests/share && bash run-test.sh "" 298s generating tests.. 298s running tests.. 300s [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41][42][43][44][45][46][47][48][49][50][51][52][53][54][55][56][57][58][59][60][61][62][63][64][65][66][67][68][69][70][71][72][73][74][75][76][77][78][79][80][81][82][83][84][85][86][87][88][89][90][91][92][93][94][95][96][97][98][99] 300s cd tests/opt_share && bash run-test.sh "" 300s generating tests.. 300s running tests.. 300s make[1]: Entering directory '/tmp/autopkgtest.JGlVyS/build.mfJ/src/tests/opt_share' 342s [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41][42][43][44][45][46][47][48][49][50][51][52][53][54][55][56][57][58][59][60][61][62][63][64][65][66][67][68][69][70][71][72][73][74][75][76][77][78][79][80][81][82][83][84][85][86][87][88][89][90][91][92][93][94][95][96][97][98][99]make[1]: Leaving directory '/tmp/autopkgtest.JGlVyS/build.mfJ/src/tests/opt_share' 342s 342s cd tests/fsm && bash run-test.sh "" 342s generating tests.. 343s PRNG seed: 5631133914365774636 343s running tests.. 343s make[1]: Entering directory '/tmp/autopkgtest.JGlVyS/build.mfJ/src/tests/fsm' 343s [0]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 343s Users of state reg look like FSM recoding might result in larger circuit. 343s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 344s K[1]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 344s Users of state reg look like FSM recoding might result in larger circuit. 344s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 345s K[2]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 345s Users of state reg look like FSM recoding might result in larger circuit. 345s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 346s K[3]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 346s Users of state reg look like FSM recoding might result in larger circuit. 346s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 349s K[4]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 349s Users of state reg look like FSM recoding might result in larger circuit. 349s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 353s K[5]K[6]K[7]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 353s Users of state reg look like FSM recoding might result in larger circuit. 353s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 357s K[8]K[9]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 357s Users of state reg look like FSM recoding might result in larger circuit. 357s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 358s K[10]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 358s Users of state reg look like FSM recoding might result in larger circuit. 358s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 362s K[11]K[12]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 362s Users of state reg look like FSM recoding might result in larger circuit. 362s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 363s K[13]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 363s Users of state reg look like FSM recoding might result in larger circuit. 363s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 365s K[14]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 365s Users of state reg look like FSM recoding might result in larger circuit. 365s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 365s K[15]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 365s Users of state reg look like FSM recoding might result in larger circuit. 365s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 365s K[16]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 365s Users of state reg look like FSM recoding might result in larger circuit. 365s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 367s K[17]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 367s Users of state reg look like FSM recoding might result in larger circuit. 367s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 388s T[18]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 388s Users of state reg look like FSM recoding might result in larger circuit. 388s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 389s K[19]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 389s Users of state reg look like FSM recoding might result in larger circuit. 389s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 390s K[20]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 390s Users of state reg look like FSM recoding might result in larger circuit. 390s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 390s K[21]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 390s Users of state reg look like FSM recoding might result in larger circuit. 390s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 392s K[22]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 392s Users of state reg look like FSM recoding might result in larger circuit. 392s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 393s K[23]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 393s Users of state reg look like FSM recoding might result in larger circuit. 393s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 396s K[24]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 396s Users of state reg look like FSM recoding might result in larger circuit. 396s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 400s K[25]K[26]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 400s Users of state reg look like FSM recoding might result in larger circuit. 400s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 400s K[27]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 400s Users of state reg look like FSM recoding might result in larger circuit. 400s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 402s K[28]K[29]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 402s Users of state reg look like FSM recoding might result in larger circuit. 402s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 402s K[30]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 402s Users of state reg look like FSM recoding might result in larger circuit. 402s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 406s K[31]K[32]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 406s Users of state reg look like FSM recoding might result in larger circuit. 406s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 410s K[33]K[34]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 410s Users of state reg look like FSM recoding might result in larger circuit. 410s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 412s K[35]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 412s Users of state reg look like FSM recoding might result in larger circuit. 412s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 414s K[36]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 414s Users of state reg look like FSM recoding might result in larger circuit. 414s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 438s T[37]K[38]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 438s Users of state reg look like FSM recoding might result in larger circuit. 438s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 438s K[39]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 438s Users of state reg look like FSM recoding might result in larger circuit. 438s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 441s K[40]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 441s Users of state reg look like FSM recoding might result in larger circuit. 441s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 442s K[41]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 442s Users of state reg look like FSM recoding might result in larger circuit. 442s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 446s K[42]K[43]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 446s Users of state reg look like FSM recoding might result in larger circuit. 446s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 448s K[44]K[45]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 448s Users of state reg look like FSM recoding might result in larger circuit. 448s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 449s K[46]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 449s Users of state reg look like FSM recoding might result in larger circuit. 449s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 450s K[47]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 450s Users of state reg look like FSM recoding might result in larger circuit. 450s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 451s K[48]K[49]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 451s Users of state reg look like FSM recoding might result in larger circuit. 451s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 452s K 452s make[1]: Leaving directory '/tmp/autopkgtest.JGlVyS/build.mfJ/src/tests/fsm' 452s cd tests/techmap && bash run-test.sh 452s make[1]: Entering directory '/tmp/autopkgtest.JGlVyS/build.mfJ/src/tests/techmap' 453s Passed abc9.ys 453s Warning: wire '\Q' is assigned in a block at < ok 463s Test: firrtl_938 -> ok 463s Test: implicit_en -> ok 465s Test: issue00335 -> ok 466s Test: issue00710 -> ok 466s Test: no_implicit_en -> ok 467s Test: read_arst -> ok 468s Test: read_two_mux -> ok 469s Test: shared_ports -> ok 469s Test: simple_sram_byte_en -> ok 470s Test: trans_addr_enable -> ok 471s Test: trans_sdp -> ok 472s Test: trans_sp -> ok 473s Test: wide_all -> ok 473s Test: wide_read_async -> ok 474s Test: wide_read_mixed -> ok 475s Test: wide_read_sync -> ok 476s Test: wide_read_trans -> ok 477s Test: wide_thru_priority -> ok 478s Test: wide_write -> ok 478s make[1]: Leaving directory '/tmp/autopkgtest.JGlVyS/build.mfJ/src/tests/memories' 478s Testing expectations for amber23_sram_byte_en.v .. ok. 478s Testing expectations for implicit_en.v .. ok. 478s Testing expectations for issue00335.v .. ok. 478s Testing expectations for issue00710.v .. ok. 478s Testing expectations for no_implicit_en.v .. ok. 478s Testing expectations for read_arst.v .. ok. 478s Testing expectations for read_two_mux.v .. ok. 478s Testing expectations for shared_ports.v .. ok. 478s Testing expectations for simple_sram_byte_en.v .. ok. 478s Testing expectations for trans_addr_enable.v .. ok. 478s Testing expectations for trans_sdp.v .. ok. 478s Testing expectations for trans_sp.v .. ok. 478s Testing expectations for wide_all.v .. ok. 478s Testing expectations for wide_read_async.v .. ok. 479s Testing expectations for wide_read_mixed.v .. ok. 479s Testing expectations for wide_read_sync.v .. ok. 479s Testing expectations for wide_read_trans.v .. ok. 479s Testing expectations for wide_thru_priority.v .. ok. 479s Testing expectations for wide_write.v .. ok. 479s cd tests/memlib && bash run-test.sh "" 479s make[1]: Entering directory '/tmp/autopkgtest.JGlVyS/build.mfJ/src/tests/memlib' 480s Test: t_async_big -> ok 483s Test: t_async_big_block -> ok 483s Test: t_async_small -> ok 483s Test: t_async_small_block -> ok 483s Test: t_sync_big -> ok 483s Test: t_sync_big_sdp -> ok 485s Test: t_sync_big_lut -> ok 485s Test: t_sync_small -> ok 485s Test: t_sync_small_block -> ok 485s Test: t_sync_small_block_attr -> ok 486s Test: t_init_lut_zeros_zero -> ok 486s Test: t_init_lut_zeros_any -> ok 486s Test: t_init_lut_val_zero -> ok 486s Test: t_init_lut_val_any -> ok 486s Test: t_init_lut_val_no_undef -> ok 487s Test: t_init_lut_val2_any -> ok 487s Test: t_init_lut_val2_no_undef -> ok 487s Test: t_init_lut_x_none -> ok 487s Test: t_init_lut_x_zero -> ok 487s Test: t_init_lut_x_any -> ok 487s Test: t_init_lut_x_no_undef -> ok 488s Test: t_ram_18b2B -> ok 488s Test: t_ram_9b1B -> ok 488s Test: t_ram_4b1B -> ok 488s Test: t_ram_2b1B -> ok 488s Test: t_ram_1b1B -> ok 488s Test: t_init_9b1B_zeros_zero -> ok 489s Test: t_init_9b1B_zeros_any -> ok 489s Test: t_init_9b1B_val_zero -> ok 489s Test: t_init_9b1B_val_any -> ok 489s Test: t_init_9b1B_val_no_undef -> ok 489s Test: t_init_13b2B_val_any -> ok 489s Test: t_init_18b2B_val_any -> ok 490s Test: t_init_18b2B_val_no_undef -> ok 490s Test: t_init_4b1B_x_none -> ok 490s Test: t_init_4b1B_x_zero -> ok 490s Test: t_init_4b1B_x_any -> ok 490s Test: t_init_4b1B_x_no_undef -> ok 490s Test: t_clock_a4_wANYrANYsFalse -> ok 491s Test: t_clock_a4_wANYrNEGsFalse -> ok 491s Test: t_clock_a4_wANYrPOSsFalse -> ok 491s Test: t_clock_a4_wNEGrANYsFalse -> ok 491s Test: t_clock_a4_wNEGrPOSsFalse -> ok 491s Test: t_clock_a4_wNEGrNEGsFalse -> ok 491s Test: t_clock_a4_wPOSrANYsFalse -> ok 491s Test: t_clock_a4_wPOSrNEGsFalse -> ok 492s Test: t_clock_a4_wPOSrPOSsFalse -> ok 492s Test: t_clock_a4_wANYrANYsTrue -> ok 492s Test: t_clock_a4_wNEGrPOSsTrue -> ok 492s Test: t_clock_a4_wNEGrNEGsTrue -> ok 492s Test: t_clock_a4_wPOSrNEGsTrue -> ok 492s Test: t_clock_a4_wPOSrPOSsTrue -> ok 493s Test: t_unmixed -> ok 493s Test: t_mixed_9_18 -> ok 493s Test: t_mixed_18_9 -> ok 493s Test: t_mixed_36_9 -> ok 493s Test: t_mixed_4_2 -> ok 493s Test: t_tdp -> ok 493s Test: t_sync_2clk -> ok 494s Test: t_sync_shared -> ok 494s Test: t_sync_2clk_shared -> ok 494s Test: t_sync_trans_old_old -> ok 494s Test: t_sync_trans_old_new -> ok 494s Test: t_sync_trans_old_none -> ok 494s Test: t_sync_trans_new_old -> ok 495s Test: t_sync_trans_new_new -> ok 495s Test: t_sync_trans_new_none -> ok 495s Test: t_sp_nc_none -> ok 495s Test: t_sp_new_none -> ok 495s Test: t_sp_old_none -> ok 495s Test: t_sp_nc_nc -> ok 496s Test: t_sp_new_nc -> ok 496s Test: t_sp_old_nc -> ok 496s Test: t_sp_nc_new -> ok 496s Test: t_sp_new_new -> ok 496s Test: t_sp_old_new -> ok 496s Test: t_sp_nc_old -> ok 497s Test: t_sp_new_old -> ok 497s Test: t_sp_old_old -> ok 497s Test: t_sp_nc_new_only -> ok 497s Test: t_sp_new_new_only -> ok 497s Test: t_sp_old_new_only -> ok 497s Test: t_sp_nc_new_only_be -> ok 497s Test: t_sp_new_new_only_be -> ok 498s Test: t_sp_old_new_only_be -> ok 498s Test: t_sp_nc_new_be -> ok 498s Test: t_sp_new_new_be -> ok 498s Test: t_sp_old_new_be -> ok 498s Test: t_sp_nc_old_be -> ok 498s Test: t_sp_new_old_be -> ok 499s Test: t_sp_old_old_be -> ok 499s Test: t_sp_nc_nc_be -> ok 499s Test: t_sp_new_nc_be -> ok 499s Test: t_sp_old_nc_be -> ok 499s Test: t_sp_nc_auto -> ok 499s Test: t_sp_new_auto -> ok 500s Test: t_sp_old_auto -> ok 500s Test: t_sp_nc_auto_be -> ok 500s Test: t_sp_new_auto_be -> ok 500s Test: t_sp_old_auto_be -> ok 500s Test: t_sp_init_x_x -> ok 500s Test: t_sp_init_x_x_re -> ok 500s Test: t_sp_init_x_x_ce -> ok 501s Test: t_sp_init_0_x -> ok 501s Test: t_sp_init_0_x_re -> ok 501s Test: t_sp_init_0_0 -> ok 501s Test: t_sp_init_0_0_re -> ok 501s Test: t_sp_init_0_any -> ok 501s Test: t_sp_init_0_any_re -> ok 502s Test: t_sp_init_v_x -> ok 502s Test: t_sp_init_v_x_re -> ok 502s Test: t_sp_init_v_0 -> ok 502s Test: t_sp_init_v_0_re -> ok 502s Test: t_sp_init_v_any -> ok 502s Test: t_sp_init_v_any_re -> ok 502s Test: t_sp_arst_x_x -> ok 503s Test: t_sp_arst_x_x_re -> ok 503s Test: t_sp_arst_0_x -> ok 503s Test: t_sp_arst_0_x_re -> ok 503s Test: t_sp_arst_0_0 -> ok 503s Test: t_sp_arst_0_0_re -> ok 503s Test: t_sp_arst_0_any -> ok 503s Test: t_sp_arst_0_any_re -> ok 504s Test: t_sp_arst_0_init -> ok 504s Test: t_sp_arst_0_init_re -> ok 504s Test: t_sp_arst_v_x -> ok 504s Test: t_sp_arst_v_x_re -> ok 504s Test: t_sp_arst_v_0 -> ok 504s Test: t_sp_arst_v_0_re -> ok 505s Test: t_sp_arst_v_any -> ok 505s Test: t_sp_arst_v_any_re -> ok 505s Test: t_sp_arst_v_init -> ok 505s Test: t_sp_arst_v_init_re -> ok 505s Test: t_sp_arst_e_x -> ok 505s Test: t_sp_arst_e_x_re -> ok 506s Test: t_sp_arst_e_0 -> ok 506s Test: t_sp_arst_e_0_re -> ok 506s Test: t_sp_arst_e_any -> ok 506s Test: t_sp_arst_e_any_re -> ok 506s Test: t_sp_arst_e_init -> ok 506s Test: t_sp_arst_e_init_re -> ok 507s Test: t_sp_arst_n_x -> ok 507s Test: t_sp_arst_n_x_re -> ok 507s Test: t_sp_arst_n_0 -> ok 507s Test: t_sp_arst_n_0_re -> ok 507s Test: t_sp_arst_n_any -> ok 507s Test: t_sp_arst_n_any_re -> ok 508s Test: t_sp_arst_n_init -> ok 508s Test: t_sp_arst_n_init_re -> ok 508s Test: t_sp_srst_x_x -> ok 508s Test: t_sp_srst_x_x_re -> ok 508s Test: t_sp_srst_0_x -> ok 508s Test: t_sp_srst_0_x_re -> ok 509s Test: t_sp_srst_0_0 -> ok 509s Test: t_sp_srst_0_0_re -> ok 509s Test: t_sp_srst_0_any -> ok 509s Test: t_sp_srst_0_any_re -> ok 509s Test: t_sp_srst_0_init -> ok 509s Test: t_sp_srst_0_init_re -> ok 509s Test: t_sp_srst_v_x -> ok 510s Test: t_sp_srst_v_x_re -> ok 510s Test: t_sp_srst_v_0 -> ok 510s Test: t_sp_srst_v_0_re -> ok 510s Test: t_sp_srst_v_any -> ok 510s Test: t_sp_srst_v_any_re -> ok 510s Test: t_sp_srst_v_any_re_gated -> ok 511s Test: t_sp_srst_v_any_ce -> ok 511s Test: t_sp_srst_v_any_ce_gated -> ok 511s Test: t_sp_srst_v_init -> ok 511s Test: t_sp_srst_v_init_re -> ok 511s Test: t_sp_srst_e_x -> ok 511s Test: t_sp_srst_e_x_re -> ok 512s Test: t_sp_srst_e_0 -> ok 512s Test: t_sp_srst_e_0_re -> ok 512s Test: t_sp_srst_e_any -> ok 512s Test: t_sp_srst_e_any_re -> ok 512s Test: t_sp_srst_e_init -> ok 512s Test: t_sp_srst_e_init_re -> ok 513s Test: t_sp_srst_n_x -> ok 513s Test: t_sp_srst_n_x_re -> ok 513s Test: t_sp_srst_n_0 -> ok 513s Test: t_sp_srst_n_0_re -> ok 513s Test: t_sp_srst_n_any -> ok 513s Test: t_sp_srst_n_any_re -> ok 514s Test: t_sp_srst_n_init -> ok 514s Test: t_sp_srst_n_init_re -> ok 514s Test: t_sp_srst_gv_x -> ok 514s Test: t_sp_srst_gv_x_re -> ok 514s Test: t_sp_srst_gv_0 -> ok 514s Test: t_sp_srst_gv_0_re -> ok 515s Test: t_sp_srst_gv_any -> ok 515s Test: t_sp_srst_gv_any_re -> ok 515s Test: t_sp_srst_gv_any_re_gated -> ok 515s Test: t_sp_srst_gv_any_ce -> ok 515s Test: t_sp_srst_gv_any_ce_gated -> ok 516s Test: t_sp_srst_gv_init -> ok 516s Test: t_sp_srst_gv_init_re -> ok 516s Test: t_wren_a4d4_NO_BYTE -> ok 516s Test: t_wren_a5d4_NO_BYTE -> ok 516s Test: t_wren_a6d4_NO_BYTE -> ok 516s Test: t_wren_a3d8_NO_BYTE -> ok 516s Test: t_wren_a4d8_NO_BYTE -> ok 517s Test: t_wren_a4d4_W4_B4 -> ok 517s Test: t_wren_a4d8_W4_B4_separate -> ok 517s Test: t_wren_a4d8_W8_B4 -> ok 517s Test: t_wren_a4d8_W8_B4_separate -> ok 517s Test: t_wren_a4d8_W8_B8 -> ok 517s Test: t_wren_a4d8_W8_B8_separate -> ok 517s Test: t_wren_a4d2w8_W16_B4 -> ok 518s Test: t_wren_a4d2w8_W16_B4_separate -> ok 518s Test: t_wren_a4d4w4_W16_B4 -> ok 518s Test: t_wren_a4d4w4_W16_B4_separate -> ok 518s Test: t_wren_a5d4w2_W16_B4 -> ok 518s Test: t_wren_a5d4w2_W16_B4_separate -> ok 518s Test: t_wren_a5d4w4_W16_B4 -> ok 519s Test: t_wren_a5d4w4_W16_B4_separate -> ok 519s Test: t_wren_a4d8w2_W16_B4 -> ok 519s Test: t_wren_a4d8w2_W16_B4_separate -> ok 519s Test: t_wren_a5d8w1_W16_B4 -> ok 519s Test: t_wren_a5d8w1_W16_B4_separate -> ok 519s Test: t_wren_a5d8w2_W16_B4 -> ok 520s Test: t_wren_a5d8w2_W16_B4_separate -> ok 520s Test: t_wren_a4d16w1_W16_B4 -> ok 520s Test: t_wren_a4d16w1_W16_B4_separate -> ok 520s Test: t_wren_a4d4w2_W8_B8 -> ok 520s Test: t_wren_a4d4w2_W8_B8_separate -> ok 520s Test: t_wren_a4d4w1_W8_B8 -> ok 521s Test: t_wren_a4d4w1_W8_B8_separate -> ok 521s Test: t_wren_a4d8w2_W8_B8 -> ok 521s Test: t_wren_a4d8w2_W8_B8_separate -> ok 521s Test: t_wren_a3d8w2_W8_B8 -> ok 521s Test: t_wren_a3d8w2_W8_B8_separate -> ok 521s Test: t_wren_a4d4w2_W8_B4 -> ok 522s Test: t_wren_a4d4w2_W8_B4_separate -> ok 522s Test: t_wren_a4d2w4_W8_B4 -> ok 522s Test: t_wren_a4d2w4_W8_B4_separate -> ok 522s Test: t_wren_a4d4w4_W8_B4 -> ok 522s Test: t_wren_a4d4w4_W8_B4_separate -> ok 522s Test: t_wren_a4d4w4_W4_B4 -> ok 523s Test: t_wren_a4d4w4_W4_B4_separate -> ok 523s Test: t_wren_a4d4w5_W4_B4 -> ok 523s Test: t_wren_a4d4w5_W4_B4_separate -> ok 523s Test: t_geom_a4d64_wren -> ok 523s Test: t_geom_a5d32_wren -> ok 523s Test: t_geom_a5d64_wren -> ok 523s Test: t_geom_a6d16_wren -> ok 524s Test: t_geom_a6d30_wren -> ok 524s Test: t_geom_a6d64_wren -> ok 524s Test: t_geom_a7d4_wren -> ok 524s Test: t_geom_a7d6_wren -> ok 524s Test: t_geom_a7d8_wren -> ok 524s Test: t_geom_a7d17_wren -> ok 525s Test: t_geom_a8d4_wren -> ok 525s Test: t_geom_a8d6_wren -> ok 525s Test: t_geom_a9d4_wren -> ok 525s Test: t_geom_a9d8_wren -> ok 525s Test: t_geom_a9d5_wren -> ok 526s Test: t_geom_a9d6_wren -> ok 526s Test: t_geom_a3d18_9b1B -> ok 526s Test: t_geom_a4d4_9b1B -> ok 526s Test: t_geom_a4d18_9b1B -> ok 526s Test: t_geom_a5d32_9b1B -> ok 526s Test: t_geom_a6d4_9b1B -> ok 526s Test: t_geom_a7d11_9b1B -> ok 527s Test: t_geom_a7d18_9b1B -> ok 527s Test: t_geom_a11d1_9b1B -> ok 527s Test: t_wide_sdp_a6r1w1b1x1 -> ok 527s Test: t_wide_sdp_a7r1w1b1x1 -> ok 527s Test: t_wide_sdp_a8r1w1b1x1 -> ok 528s Test: t_wide_sdp_a6r0w0b0x0 -> ok 528s Test: t_wide_sdp_a6r1w0b0x0 -> ok 528s Test: t_wide_sdp_a6r2w0b0x0 -> ok 528s Test: t_wide_sdp_a6r3w0b0x0 -> ok 528s Test: t_wide_sdp_a6r4w0b0x0 -> ok 528s Test: t_wide_sdp_a6r5w0b0x0 -> ok 529s Test: t_wide_sdp_a6r0w1b0x0 -> ok 529s Test: t_wide_sdp_a6r0w1b1x0 -> ok 529s Test: t_wide_sdp_a6r0w2b0x0 -> ok 529s Test: t_wide_sdp_a6r0w2b2x0 -> ok 529s Test: t_wide_sdp_a6r0w3b2x0 -> ok 530s Test: t_wide_sdp_a6r0w4b2x0 -> ok 530s Test: t_wide_sdp_a6r0w5b2x0 -> ok 530s Test: t_wide_sdp_a7r0w0b0x0 -> ok 530s Test: t_wide_sdp_a7r1w0b0x0 -> ok 530s Test: t_wide_sdp_a7r2w0b0x0 -> ok 531s Test: t_wide_sdp_a7r3w0b0x0 -> ok 531s Test: t_wide_sdp_a7r4w0b0x0 -> ok 531s Test: t_wide_sdp_a7r5w0b0x0 -> ok 531s Test: t_wide_sdp_a7r0w1b0x0 -> ok 531s Test: t_wide_sdp_a7r0w1b1x0 -> ok 532s Test: t_wide_sdp_a7r0w2b0x0 -> ok 532s Test: t_wide_sdp_a7r0w2b2x0 -> ok 532s Test: t_wide_sdp_a7r0w3b2x0 -> ok 532s Test: t_wide_sdp_a7r0w4b2x0 -> ok 533s Test: t_wide_sdp_a7r0w5b2x0 -> ok 533s Test: t_wide_sp_mix_a6r1w1b1 -> ok 533s Test: t_wide_sp_mix_a7r1w1b1 -> ok 533s Test: t_wide_sp_mix_a8r1w1b1 -> ok 533s Test: t_wide_sp_mix_a6r0w0b0 -> ok 533s Test: t_wide_sp_mix_a6r1w0b0 -> ok 534s Test: t_wide_sp_mix_a6r2w0b0 -> ok 534s Test: t_wide_sp_mix_a6r3w0b0 -> ok 534s Test: t_wide_sp_mix_a6r4w0b0 -> ok 534s Test: t_wide_sp_mix_a6r5w0b0 -> ok 534s Test: t_wide_sp_mix_a6r0w1b0 -> ok 535s Test: t_wide_sp_mix_a6r0w1b1 -> ok 535s Test: t_wide_sp_mix_a6r0w2b0 -> ok 535s Test: t_wide_sp_mix_a6r0w2b2 -> ok 535s Test: t_wide_sp_mix_a6r0w3b2 -> ok 535s Test: t_wide_sp_mix_a6r0w4b2 -> ok 536s Test: t_wide_sp_mix_a6r0w5b2 -> ok 536s Test: t_wide_sp_mix_a7r0w0b0 -> ok 536s Test: t_wide_sp_mix_a7r1w0b0 -> ok 536s Test: t_wide_sp_mix_a7r2w0b0 -> ok 536s Test: t_wide_sp_mix_a7r3w0b0 -> ok 537s Test: t_wide_sp_mix_a7r4w0b0 -> ok 537s Test: t_wide_sp_mix_a7r5w0b0 -> ok 537s Test: t_wide_sp_mix_a7r0w1b0 -> ok 537s Test: t_wide_sp_mix_a7r0w1b1 -> ok 537s Test: t_wide_sp_mix_a7r0w2b0 -> ok 538s Test: t_wide_sp_mix_a7r0w2b2 -> ok 538s Test: t_wide_sp_mix_a7r0w3b2 -> ok 538s Test: t_wide_sp_mix_a7r0w4b2 -> ok 538s Test: t_wide_sp_mix_a7r0w5b2 -> ok 538s Test: t_wide_sp_tied_a6r1w1b1 -> ok 539s Test: t_wide_sp_tied_a7r1w1b1 -> ok 539s Test: t_wide_sp_tied_a8r1w1b1 -> ok 539s Test: t_wide_sp_tied_a6r0w0b0 -> ok 539s Test: t_wide_sp_tied_a6r1w0b0 -> ok 539s Test: t_wide_sp_tied_a6r2w0b0 -> ok 539s Test: t_wide_sp_tied_a6r3w0b0 -> ok 540s Test: t_wide_sp_tied_a6r4w0b0 -> ok 540s Test: t_wide_sp_tied_a6r5w0b0 -> ok 540s Test: t_wide_sp_tied_a6r0w1b0 -> ok 540s Test: t_wide_sp_tied_a6r0w1b1 -> ok 540s Test: t_wide_sp_tied_a6r0w2b0 -> ok 541s Test: t_wide_sp_tied_a6r0w2b2 -> ok 541s Test: t_wide_sp_tied_a6r0w3b2 -> ok 541s Test: t_wide_sp_tied_a6r0w4b2 -> ok 541s Test: t_wide_sp_tied_a6r0w5b2 -> ok 542s Test: t_wide_sp_tied_a7r0w0b0 -> ok 542s Test: t_wide_sp_tied_a7r1w0b0 -> ok 542s Test: t_wide_sp_tied_a7r2w0b0 -> ok 542s Test: t_wide_sp_tied_a7r3w0b0 -> ok 542s Test: t_wide_sp_tied_a7r4w0b0 -> ok 543s Test: t_wide_sp_tied_a7r5w0b0 -> ok 543s Test: t_wide_sp_tied_a7r0w1b0 -> ok 543s Test: t_wide_sp_tied_a7r0w1b1 -> ok 543s Test: t_wide_sp_tied_a7r0w2b0 -> ok 543s Test: t_wide_sp_tied_a7r0w2b2 -> ok 544s Test: t_wide_sp_tied_a7r0w3b2 -> ok 544s Test: t_wide_sp_tied_a7r0w4b2 -> ok 544s Test: t_wide_sp_tied_a7r0w5b2 -> ok 544s Test: t_wide_read_a6r1w1b1 -> ok 544s Test: t_wide_write_a6r1w1b1 -> ok 545s Test: t_wide_read_a7r1w1b1 -> ok 545s Test: t_wide_write_a7r1w1b1 -> ok 545s Test: t_wide_read_a8r1w1b1 -> ok 545s Test: t_wide_write_a8r1w1b1 -> ok 545s Test: t_wide_read_a6r0w0b0 -> ok 546s Test: t_wide_write_a6r0w0b0 -> ok 546s Test: t_wide_read_a6r1w0b0 -> ok 546s Test: t_wide_write_a6r1w0b0 -> ok 546s Test: t_wide_read_a6r2w0b0 -> ok 546s Test: t_wide_write_a6r2w0b0 -> ok 546s Test: t_wide_read_a6r3w0b0 -> ok 547s Test: t_wide_write_a6r3w0b0 -> ok 547s Test: t_wide_read_a6r4w0b0 -> ok 547s Test: t_wide_write_a6r4w0b0 -> ok 547s Test: t_wide_read_a6r5w0b0 -> ok 547s Test: t_wide_write_a6r5w0b0 -> ok 548s Test: t_wide_read_a6r0w1b0 -> ok 548s Test: t_wide_write_a6r0w1b0 -> ok 548s Test: t_wide_read_a6r0w1b1 -> ok 548s Test: t_wide_write_a6r0w1b1 -> ok 548s Test: t_wide_read_a6r0w2b0 -> ok 548s Test: t_wide_write_a6r0w2b0 -> ok 549s Test: t_wide_read_a6r0w2b2 -> ok 549s Test: t_wide_write_a6r0w2b2 -> ok 549s Test: t_wide_read_a6r0w3b2 -> ok 549s Test: t_wide_write_a6r0w3b2 -> ok 549s Test: t_wide_read_a6r0w4b2 -> ok 550s Test: t_wide_write_a6r0w4b2 -> ok 550s Test: t_wide_read_a6r0w5b2 -> ok 550s Test: t_wide_write_a6r0w5b2 -> ok 550s Test: t_wide_read_a7r0w0b0 -> ok 551s Test: t_wide_write_a7r0w0b0 -> ok 551s Test: t_wide_read_a7r1w0b0 -> ok 551s Test: t_wide_write_a7r1w0b0 -> ok 551s Test: t_wide_read_a7r2w0b0 -> ok 551s Test: t_wide_write_a7r2w0b0 -> ok 551s Test: t_wide_read_a7r3w0b0 -> ok 552s Test: t_wide_write_a7r3w0b0 -> ok 552s Test: t_wide_read_a7r4w0b0 -> ok 552s Test: t_wide_write_a7r4w0b0 -> ok 552s Test: t_wide_read_a7r5w0b0 -> ok 552s Test: t_wide_write_a7r5w0b0 -> ok 553s Test: t_wide_read_a7r0w1b0 -> ok 553s Test: t_wide_write_a7r0w1b0 -> ok 553s Test: t_wide_read_a7r0w1b1 -> ok 553s Test: t_wide_write_a7r0w1b1 -> ok 553s Test: t_wide_read_a7r0w2b0 -> ok 553s Test: t_wide_write_a7r0w2b0 -> ok 554s Test: t_wide_read_a7r0w2b2 -> ok 554s Test: t_wide_write_a7r0w2b2 -> ok 554s Test: t_wide_read_a7r0w3b2 -> ok 554s Test: t_wide_write_a7r0w3b2 -> ok 554s Test: t_wide_read_a7r0w4b2 -> ok 555s Test: t_wide_write_a7r0w4b2 -> ok 555s Test: t_wide_read_a7r0w5b2 -> ok 555s Test: t_wide_write_a7r0w5b2 -> ok 556s Test: t_quad_port_a2d2 -> ok 556s Test: t_quad_port_a4d2 -> ok 556s Test: t_quad_port_a5d2 -> ok 556s Test: t_quad_port_a4d4 -> ok 556s Test: t_quad_port_a6d2 -> ok 556s Test: t_quad_port_a4d8 -> ok 557s Test: t_wide_quad_a4w2r1 -> ok 557s Test: t_wide_oct_a4w2r1 -> ok 557s Test: t_wide_quad_a4w2r2 -> ok 557s Test: t_wide_oct_a4w2r2 -> ok 557s Test: t_wide_quad_a4w2r3 -> ok 557s Test: t_wide_oct_a4w2r3 -> ok 558s Test: t_wide_quad_a4w2r4 -> ok 558s Test: t_wide_oct_a4w2r4 -> ok 558s Test: t_wide_quad_a4w2r5 -> ok 558s Test: t_wide_oct_a4w2r5 -> ok 558s Test: t_wide_quad_a4w2r6 -> ok 558s Test: t_wide_oct_a4w2r6 -> ok 559s Test: t_wide_quad_a4w2r7 -> ok 559s Test: t_wide_oct_a4w2r7 -> ok 559s Test: t_wide_quad_a4w2r8 -> ok 559s Test: t_wide_oct_a4w2r8 -> ok 559s Test: t_wide_quad_a4w2r9 -> ok 559s Test: t_wide_oct_a4w2r9 -> ok 560s Test: t_wide_quad_a4w4r1 -> ok 560s Test: t_wide_oct_a4w4r1 -> ok 560s Test: t_wide_quad_a4w4r4 -> ok 560s Test: t_wide_oct_a4w4r4 -> ok 560s Test: t_wide_quad_a4w4r6 -> ok 560s Test: t_wide_oct_a4w4r6 -> ok 561s Test: t_wide_quad_a4w4r9 -> ok 561s Test: t_wide_oct_a4w4r9 -> ok 561s Test: t_wide_quad_a5w2r1 -> ok 561s Test: t_wide_oct_a5w2r1 -> ok 561s Test: t_wide_quad_a5w2r4 -> ok 561s Test: t_wide_oct_a5w2r4 -> ok 562s Test: t_wide_quad_a5w2r9 -> ok 562s Test: t_wide_oct_a5w2r9 -> ok 562s Test: t_no_reset -> ok 562s Test: t_gclken -> ok 562s Test: t_ungated -> ok 562s Test: t_gclken_ce -> ok 563s Test: t_grden -> ok 563s Test: t_grden_ce -> ok 563s Test: t_exclwr -> ok 563s Test: t_excl_rst -> ok 563s Test: t_transwr -> ok 564s Test: t_trans_rst -> ok 564s Test: t_wr_byte -> ok 564s Test: t_trans_byte -> ok 564s Test: t_wr_rst_byte -> ok 564s Test: t_rst_wr_byte -> ok 564s Test: t_rdenrst_wr_byte -> ok 564s make[1]: Leaving directory '/tmp/autopkgtest.JGlVyS/build.mfJ/src/tests/memlib' 564s cd tests/bram && bash run-test.sh "" 564s generating tests.. 565s PRNG seed: 347028 565s running tests.. 565s make[1]: Entering directory '/tmp/autopkgtest.JGlVyS/build.mfJ/src/tests/bram' 565s Passed memory_bram test 00_01. 566s Passed memory_bram test 00_02. 566s Passed memory_bram test 00_03. 567s Passed memory_bram test 00_04. 568s Passed memory_bram test 01_00. 568s Passed memory_bram test 01_02. 569s Passed memory_bram test 01_03. 569s Passed memory_bram test 01_04. 570s Passed memory_bram test 02_00. 570s Passed memory_bram test 02_01. 571s Passed memory_bram test 02_03. 571s Passed memory_bram test 02_04. 571s Passed memory_bram test 03_00. 572s Passed memory_bram test 03_01. 574s Passed memory_bram test 03_02. 574s Passed memory_bram test 03_04. 575s Passed memory_bram test 04_00. 576s Passed memory_bram test 04_01. 576s Passed memory_bram test 04_02. 577s Passed memory_bram test 04_03. 577s make[1]: Leaving directory '/tmp/autopkgtest.JGlVyS/build.mfJ/src/tests/bram' 577s cd tests/various && bash run-test.sh 577s make[1]: Entering directory '/tmp/autopkgtest.JGlVyS/build.mfJ/src/tests/various' 577s Warning: Wire abc9_test027.$abc$91$o is used but has no driver. 578s Passed abc9.ys 578s Passed aiger_dff.ys 578s Passed attrib05_port_conn.ys 578s Passed attrib07_func_call.ys 578s Passed autoname.ys 578s Passed blackbox_wb.ys 578s Passed bug1496.ys 578s Passed bug1531.ys 578s Passed bug1614.ys 578s Passed bug1710.ys 578s Warning: Yosys has only limited support for tri-state logic at the moment. (< svinterface1_tb.v:50: $finish called at 420000 (10ps) 629s svinterface1_tb.v:50: $finish called at 420000 (10ps) 629s ok 629s Test: svinterface_at_top -> svinterface_at_top_tb.v:61: $finish called at 420000 (10ps) 629s svinterface_at_top_tb_wrapper.v:61: $finish called at 420000 (10ps) 629s ERROR! 629s Test: load_and_derive ->ok 629s Test: resolve_types ->ok 629s cd tests/svtypes && bash run-test.sh "" 629s make[1]: Entering directory '/tmp/autopkgtest.JGlVyS/build.mfJ/src/tests/svtypes' 629s Passed enum_simple.ys 629s Passed logic_rom.ys 629s < ok 642s Test ../../techlibs/anlogic/cells_sim.v -> ok 642s Test ../../techlibs/coolrunner2/cells_sim.v -> ok 642s Test ../../techlibs/ecp5/cells_sim.v -> ok 642s Test ../../techlibs/efinix/cells_sim.v -> ok 642s Test ../../techlibs/gatemate/cells_sim.v -> ok 642s Test ../../techlibs/gowin/cells_sim.v -> ok 642s Test ../../techlibs/greenpak4/cells_sim.v -> ok 642s Test ../../techlibs/ice40/cells_sim.v -DICE40_HX ->../../techlibs/ice40/cells_sim.v:2231: warning: Choosing typ expression. 642s ../../techlibs/ice40/cells_sim.v:2231: warning: Choosing typ expression. 642s ../../techlibs/ice40/cells_sim.v:2233: warning: Choosing typ expression. 642s ../../techlibs/ice40/cells_sim.v:2233: warning: Choosing typ expression. 642s ../../techlibs/ice40/cells_sim.v:2235: warning: Choosing typ expression. 642s ../../techlibs/ice40/cells_sim.v:2235: warning: Choosing typ expression. 642s ../../techlibs/ice40/cells_sim.v:2237: warning: Choosing typ expression. 642s ../../techlibs/ice40/cells_sim.v:2237: warning: Choosing typ expression. 642s ../../techlibs/ice40/cells_sim.v:2239: warning: Choosing typ expression. 642s ../../techlibs/ice40/cells_sim.v:2239: warning: Choosing typ expression. 642s ok 642s Test ../../techlibs/ice40/cells_sim.v -DICE40_LP ->../../techlibs/ice40/cells_sim.v:2295: warning: Choosing typ expression. 642s ../../techlibs/ice40/cells_sim.v:2295: warning: Choosing typ expression. 642s ../../techlibs/ice40/cells_sim.v:2297: warning: Choosing typ expression. 642s ../../techlibs/ice40/cells_sim.v:2297: warning: Choosing typ expression. 642s ../../techlibs/ice40/cells_sim.v:2299: warning: Choosing typ expression. 642s ../../techlibs/ice40/cells_sim.v:2299: warning: Choosing typ expression. 642s ../../techlibs/ice40/cells_sim.v:2301: warning: Choosing typ expression. 642s ../../techlibs/ice40/cells_sim.v:2301: warning: Choosing typ expression. 642s ../../techlibs/ice40/cells_sim.v:2303: warning: Choosing typ expression. 642s ../../techlibs/ice40/cells_sim.v:2303: warning: Choosing typ expression. 642s ok 642s Test ../../techlibs/ice40/cells_sim.v -DICE40_U ->../../techlibs/ice40/cells_sim.v:2359: warning: Choosing typ expression. 642s ../../techlibs/ice40/cells_sim.v:2359: warning: Choosing typ expression. 642s ../../techlibs/ice40/cells_sim.v:2361: warning: Choosing typ expression. 642s ../../techlibs/ice40/cells_sim.v:2361: warning: Choosing typ expression. 642s ../../techlibs/ice40/cells_sim.v:2363: warning: Choosing typ expression. 642s ../../techlibs/ice40/cells_sim.v:2363: warning: Choosing typ expression. 642s ../../techlibs/ice40/cells_sim.v:2365: warning: Choosing typ expression. 642s ../../techlibs/ice40/cells_sim.v:2365: warning: Choosing typ expression. 642s ../../techlibs/ice40/cells_sim.v:2367: warning: Choosing typ expression. 642s ../../techlibs/ice40/cells_sim.v:2367: warning: Choosing typ expression. 642s ok 642s Test ../../techlibs/intel/cycloneiv/cells_sim.v -> ok 642s Test ../../techlibs/intel/cycloneive/cells_sim.v -> ok 642s Test ../../techlibs/intel/cyclone10lp/cells_sim.v -> ok 642s Test ../../techlibs/intel/max10/cells_sim.v -> ok 642s Test ../../techlibs/intel_alm/cyclonev/cells_sim.v -> ok 642s Test ../../techlibs/nexus/cells_sim.v -> ok 642s Test ../../techlibs/quicklogic/cells_sim.v -> ok 642s Test ../../techlibs/sf2/cells_sim.v -> ok 642s Test ../../techlibs/xilinx/cells_sim.v -> ok 642s Test ../../techlibs/common/simcells.v -> ok 642s Test ../../techlibs/common/simlib.v -> ok 642s cd tests/arch/ice40 && bash run-test.sh "" 642s make[1]: Entering directory '/tmp/autopkgtest.JGlVyS/build.mfJ/src/tests/arch/ice40' 643s Passed add_sub.ys 646s Passed adffs.ys 646s Warning: Resizing cell port SSCounter6o.l0.I3 from 32 bits to 1 bits. 646s Warning: Resizing cell port SSCounter6o.c0.CI from 32 bits to 1 bits. 646s Warning: Resizing cell port SSCounter6o.lien.I0 from 32 bits to 1 bits. 646s Warning: Resizing cell port SSCounter6o.lien.I1 from 32 bits to 1 bits. 647s Passed bug1597.ys 648s Passed bug1598.ys 648s Passed bug1626.ys 661s Passed bug1644.ys 662s Passed bug2061.ys 663s Passed counter.ys 664s Passed dffs.ys 671s Passed dpram.ys 672s Passed fsm.ys 672s Passed ice40_dsp.ys 673s Passed ice40_opt.ys 673s Passed ice40_wrapcarry.ys 674s Passed latches.ys 675s Passed logic.ys 680s Passed macc.ys 722s Passed memories.ys 722s Passed mul.ys 725s Passed mux.ys 725s Warning: wire '\data' is assigned in a block at rom.v:10.5-10.15. 725s Warning: wire '\data' is assigned in a block at rom.v:11.5-11.15. 725s Warning: wire '\data' is assigned in a block at rom.v:12.5-12.15. 725s Warning: wire '\data' is assigned in a block at rom.v:13.6-13.16. 725s Warning: wire '\data' is assigned in a block at rom.v:14.6-14.16. 725s Warning: wire '\data' is assigned in a block at rom.v:15.6-15.16. 725s Warning: wire '\data' is assigned in a block at rom.v:16.11-16.21. 726s Passed rom.ys 727s Passed shifter.ys 727s Warning: wire '\read_data' is assigned in a block at spram.v:19.3-19.25. 728s Passed spram.ys 729s Passed tribuf.ys 729s make[1]: Leaving directory '/tmp/autopkgtest.JGlVyS/build.mfJ/src/tests/arch/ice40' 729s cd tests/arch/xilinx && bash run-test.sh "" 729s make[1]: Entering directory '/tmp/autopkgtest.JGlVyS/build.mfJ/src/tests/arch/xilinx' 741s Warning: Whitebox '$paramod\FDRE\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. 741s Warning: Whitebox 'FDSE' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. 741s Warning: Whitebox '$paramod\FDRE_1\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. 741s Warning: Whitebox '$paramod\FDSE_1\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. 761s Passed abc9_dff.ys 765s Warning: Shift register inference not yet supported for family xc3s. 768s Passed add_sub.ys 783s Passed adffs.ys 786s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DIADI from 64 bits to 16 bits. 786s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOADO from 64 bits to 16 bits. 786s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOBDO from 64 bits to 16 bits. 786s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOPADOP from 8 bits to 2 bits. 786s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOPBDOP from 8 bits to 2 bits. 786s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.WEA from 4 bits to 2 bits. 794s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.WEBWE from 1 bits to 4 bits. 797s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DIADI from 64 bits to 16 bits. 797s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOADO from 64 bits to 16 bits. 797s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOBDO from 64 bits to 16 bits. 797s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOPADOP from 8 bits to 2 bits. 797s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOPBDOP from 8 bits to 2 bits. 797s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.WEA from 4 bits to 2 bits. 797s Warning: Selection "asym_ram_sdp_read_wider" did not match any module. 809s Passed asym_ram_sdp.ys 812s Warning: Resizing cell port block_ram.memory.0.0.DIADI from 64 bits to 16 bits. 812s Warning: Resizing cell port block_ram.memory.0.0.DOADO from 64 bits to 16 bits. 812s Warning: Resizing cell port block_ram.memory.0.0.DOBDO from 64 bits to 16 bits. 812s Warning: Resizing cell port block_ram.memory.0.0.DOPADOP from 8 bits to 2 bits. 812s Warning: Resizing cell port block_ram.memory.0.0.DOPBDOP from 8 bits to 2 bits. 812s Warning: Resizing cell port block_ram.memory.0.0.WEA from 4 bits to 2 bits. 832s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DIADI from 64 bits to 16 bits. 832s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOADO from 64 bits to 16 bits. 832s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOBDO from 64 bits to 16 bits. 832s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOPADOP from 8 bits to 2 bits. 832s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOPBDOP from 8 bits to 2 bits. 832s Warning: Resizing cell port distributed_ram_manual.memory.0.0.WEA from 4 bits to 2 bits. 832s Passed attributes_test.ys 836s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIADI from 64 bits to 16 bits. 836s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOADO from 64 bits to 16 bits. 836s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOBDO from 64 bits to 16 bits. 836s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPADOP from 8 bits to 2 bits. 836s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPBDOP from 8 bits to 2 bits. 836s Warning: Resizing cell port sync_ram_sdp.memory.0.0.WEA from 4 bits to 2 bits. 839s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIPADIP from 8 bits to 2 bits. 853s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIADI from 64 bits to 32 bits. 853s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIPADIP from 8 bits to 4 bits. 853s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOADO from 64 bits to 32 bits. 853s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOBDO from 64 bits to 32 bits. 853s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPADOP from 8 bits to 4 bits. 853s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPBDOP from 8 bits to 4 bits. 876s Passed blockram.ys 880s Passed bug1460.ys 883s Passed bug1462.ys 886s Passed bug1480.ys 890s Passed bug1598.ys 891s Warning: Wire top.\t is used but has no driver. 891s Warning: Wire top.\in is used but has no driver. 893s Passed bug1605.ys 894s Passed bug3670.ys 898s Passed counter.ys 913s Passed dffs.ys 926s Passed dsp_abc9.ys 936s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef. 936s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef. 981s Passed dsp_cascade.ys 984s Passed dsp_fastfir.ys 990s Passed dsp_simd.ys 994s Warning: Shift register inference not yet supported for family xc3se. 996s Passed fsm.ys 1008s Passed latches.ys 1011s Passed logic.ys 1043s Warning: Shift register inference not yet supported for family xc3s. 1046s Passed lutram.ys 1055s Passed macc.ys 1061s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef. 1061s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef. 1062s Passed mul.ys 1062s Warning: Replacing memory \M with list of registers. See mul_unsigned.v:25 1071s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef. 1071s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef. 1075s Passed mul_unsigned.ys 1090s Passed mux.ys 1090s Warning: Shift register inference not yet supported for family xc3se. 1100s Passed mux_lut4.ys 1107s Passed nosrl.ys 1107s Passed opt_lut_ins.ys 1117s Passed pmgen_xilinx_srl.ys 1121s Warning: Resizing cell port priority_memory.mem.0.0.ADDRARDADDR from 16 bits to 15 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.0.ADDRBWRADDR from 16 bits to 15 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.0.DINADIN from 64 bits to 32 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.0.DINBDIN from 64 bits to 32 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.0.DINPADINP from 8 bits to 4 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.0.DINPBDINP from 8 bits to 4 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.0.DOUTADOUT from 64 bits to 32 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.0.DOUTBDOUT from 64 bits to 32 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.0.DOUTPADOUTP from 8 bits to 4 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.0.DOUTPBDOUTP from 8 bits to 4 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.0.WEBWE from 4 bits to 8 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.1.ADDRARDADDR from 16 bits to 15 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.1.ADDRBWRADDR from 16 bits to 15 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.1.DINADIN from 64 bits to 32 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.1.DINBDIN from 64 bits to 32 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.1.DINPADINP from 8 bits to 4 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.1.DINPBDINP from 8 bits to 4 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.1.DOUTADOUT from 64 bits to 32 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.1.DOUTBDOUT from 64 bits to 32 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.1.DOUTPADOUTP from 8 bits to 4 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.1.DOUTPBDOUTP from 8 bits to 4 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.1.WEBWE from 4 bits to 8 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.2.ADDRARDADDR from 16 bits to 15 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.2.ADDRBWRADDR from 16 bits to 15 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.2.DINADIN from 64 bits to 32 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.2.DINBDIN from 64 bits to 32 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.2.DINPADINP from 8 bits to 4 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.2.DINPBDINP from 8 bits to 4 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.2.DOUTADOUT from 64 bits to 32 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.2.DOUTBDOUT from 64 bits to 32 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.2.DOUTPADOUTP from 8 bits to 4 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.2.DOUTPBDOUTP from 8 bits to 4 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.2.WEBWE from 4 bits to 8 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.3.ADDRARDADDR from 16 bits to 15 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.3.ADDRBWRADDR from 16 bits to 15 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.3.DINADIN from 64 bits to 32 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.3.DINBDIN from 64 bits to 32 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.3.DINPADINP from 8 bits to 4 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.3.DINPBDINP from 8 bits to 4 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.3.DOUTADOUT from 64 bits to 32 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.3.DOUTBDOUT from 64 bits to 32 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.3.DOUTPADOUTP from 8 bits to 4 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.3.DOUTPBDOUTP from 8 bits to 4 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.3.WEBWE from 4 bits to 8 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.4.ADDRARDADDR from 16 bits to 15 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.4.ADDRBWRADDR from 16 bits to 15 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.4.DINADIN from 64 bits to 32 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.4.DINBDIN from 64 bits to 32 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.4.DINPADINP from 8 bits to 4 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.4.DINPBDINP from 8 bits to 4 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.4.DOUTADOUT from 64 bits to 32 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.4.DOUTBDOUT from 64 bits to 32 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.4.DOUTPADOUTP from 8 bits to 4 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.4.DOUTPBDOUTP from 8 bits to 4 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.4.WEBWE from 4 bits to 8 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.5.ADDRARDADDR from 16 bits to 15 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.5.ADDRBWRADDR from 16 bits to 15 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.5.DINADIN from 64 bits to 32 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.5.DINBDIN from 64 bits to 32 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.5.DINPADINP from 8 bits to 4 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.5.DINPBDINP from 8 bits to 4 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.5.DOUTADOUT from 64 bits to 32 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.5.DOUTBDOUT from 64 bits to 32 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.5.DOUTPADOUTP from 8 bits to 4 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.5.DOUTPBDOUTP from 8 bits to 4 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.5.WEBWE from 4 bits to 8 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.6.ADDRARDADDR from 16 bits to 15 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.6.ADDRBWRADDR from 16 bits to 15 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.6.DINADIN from 64 bits to 32 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.6.DINBDIN from 64 bits to 32 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.6.DINPADINP from 8 bits to 4 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.6.DINPBDINP from 8 bits to 4 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.6.DOUTADOUT from 64 bits to 32 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.6.DOUTBDOUT from 64 bits to 32 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.6.DOUTPADOUTP from 8 bits to 4 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.6.DOUTPBDOUTP from 8 bits to 4 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.6.WEBWE from 4 bits to 8 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.7.ADDRARDADDR from 16 bits to 15 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.7.ADDRBWRADDR from 16 bits to 15 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.7.DINADIN from 64 bits to 32 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.7.DINBDIN from 64 bits to 32 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.7.DINPADINP from 8 bits to 4 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.7.DINPBDINP from 8 bits to 4 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.7.DOUTADOUT from 64 bits to 32 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.7.DOUTBDOUT from 64 bits to 32 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.7.DOUTPADOUTP from 8 bits to 4 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.7.DOUTPBDOUTP from 8 bits to 4 bits. 1121s Warning: Resizing cell port priority_memory.mem.0.7.WEBWE from 4 bits to 8 bits. 1125s Warning: Resizing cell port priority_memory.mem.0.0.BWE_A from 8 bits to 9 bits. 1125s Warning: Resizing cell port priority_memory.mem.0.0.BWE_B from 8 bits to 9 bits. 1135s Warning: Resizing cell port sp_write_first.mem.0.0.BWE_A from 8 bits to 9 bits. 1138s Warning: Resizing cell port sp_read_first.mem.0.0.BWE_B from 8 bits to 9 bits. 1138s Passed priority_memory.ys 1142s Passed shifter.ys 1145s Passed tribuf.ys 1149s Passed xilinx_dffopt.ys 1149s Passed xilinx_dsp.ys 1149s Passed xilinx_srl.ys 1157s Passed macc.sh 1163s Passed tribuf.sh 1163s make[1]: Leaving directory '/tmp/autopkgtest.JGlVyS/build.mfJ/src/tests/arch/xilinx' 1163s cd tests/arch/ecp5 && bash run-test.sh "" 1163s make[1]: Entering directory '/tmp/autopkgtest.JGlVyS/build.mfJ/src/tests/arch/ecp5' 1164s Passed add_sub.ys 1166s Passed adffs.ys 1167s Passed bug1459.ys 1167s Passed bug1598.ys 1168s Passed bug1630.ys 1168s Warning: Literal has a width of 16 bit, but value requires 184 bit. (<>>/,/<<>>/ {print $0}' 1556s + iverilog -o iverilog-initial_display initial_display.v 1556s + ./iverilog-initial_display 1556s + diff yosys-initial_display.log iverilog-initial_display.log 1556s + test_always_display clk -DEVENT_CLK 1556s 1556s /----------------------------------------------------------------------------\ 1556s | | 1556s | yosys -- Yosys Open SYnthesis Suite | 1556s | | 1556s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1556s | | 1556s | Permission to use, copy, modify, and/or distribute this software for any | 1556s | purpose with or without fee is hereby granted, provided that the above | 1556s | copyright notice and this permission notice appear in all copies. | 1556s | | 1556s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1556s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1556s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1556s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1556s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1556s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1556s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1556s | | 1556s \----------------------------------------------------------------------------/ 1556s 1556s Yosys 0.33 (git sha1 2584903a060) 1556s 1556s 1556s -- Running command `read_verilog -DEVENT_CLK always_display.v; proc; opt_expr -mux_bool; clean' -- 1556s 1556s 1. Executing Verilog-2005 frontend: always_display.v 1556s Parsing Verilog input from `always_display.v' to AST representation. 1556s Generating RTLIL representation for module `\m'. 1556s Successfully finished Verilog frontend. 1556s 1556s 2. Executing PROC pass (convert processes to netlists). 1556s 1556s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1556s Cleaned up 0 empty switches. 1556s 1556s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1556s Removed a total of 0 dead cases. 1556s 1556s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1556s Removed 1 redundant assignment. 1556s Promoted 1 assignment to connection. 1556s 1556s 2.4. Executing PROC_INIT pass (extract init attributes). 1556s 1556s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1556s 1556s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1556s Converted 0 switches. 1556s 1556s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1556s Creating decoders for process `\m.$proc$always_display.v:4$1'. 1556s 1556s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1556s 1556s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1556s 1556s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1556s 1556s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1556s Removing empty process `m.$proc$always_display.v:4$1'. 1556s Cleaned up 0 empty switches. 1556s 1556s 2.12. Executing OPT_EXPR pass (perform const folding). 1556s Optimizing module m. 1556s 1556s 3. Executing OPT_EXPR pass (perform const folding). 1556s Optimizing module m. 1556s Removed 0 unused cells and 1 unused wires. 1556s 1556s -- Writing to `yosys-always_display-clk-1.v' using backend `verilog' -- 1556s 1556s 4. Executing Verilog backend. 1556s 1556s 4.1. Executing BMUXMAP pass. 1556s 1556s 4.2. Executing DEMUXMAP pass. 1556s Dumping module `\m'. 1556s 1556s End of script. Logfile hash: 0de35d2746, CPU: user 0.01s system 0.00s, MEM: 10.30 MB peak 1556s Yosys 0.33 (git sha1 2584903a060) 1556s Time spent: 34% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ... 1556s + local subtest=clk 1556s + shift 1556s + ../../yosys -p 'read_verilog -DEVENT_CLK always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk-1.v 1556s + ../../yosys -p 'read_verilog yosys-always_display-clk-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk-2.v 1556s 1556s /----------------------------------------------------------------------------\ 1556s | | 1556s | yosys -- Yosys Open SYnthesis Suite | 1556s | | 1556s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1556s | | 1556s | Permission to use, copy, modify, and/or distribute this software for any | 1556s | purpose with or without fee is hereby granted, provided that the above | 1556s | copyright notice and this permission notice appear in all copies. | 1556s | | 1556s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1556s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1556s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1556s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1556s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1556s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1556s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1556s | | 1556s \----------------------------------------------------------------------------/ 1556s 1556s Yosys 0.33 (git sha1 2584903a060) 1556s 1556s 1556s -- Running command `read_verilog yosys-always_display-clk-1.v; proc; opt_expr -mux_bool; clean' -- 1556s 1556s 1. Executing Verilog-2005 frontend: yosys-always_display-clk-1.v 1556s Parsing Verilog input from `yosys-always_display-clk-1.v' to AST representation. 1556s Generating RTLIL representation for module `\m'. 1556s Successfully finished Verilog frontend. 1556s 1556s 2. Executing PROC pass (convert processes to netlists). 1556s 1556s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1556s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk-1.v:18$1'. 1556s Cleaned up 1 empty switch. 1556s 1556s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1556s Removed a total of 0 dead cases. 1556s 1556s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1556s Removed 1 redundant assignment. 1556s Promoted 1 assignment to connection. 1556s 1556s 2.4. Executing PROC_INIT pass (extract init attributes). 1556s 1556s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1556s 1556s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1556s Converted 0 switches. 1556s 1556s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1556s Creating decoders for process `\m.$proc$yosys-always_display-clk-1.v:18$1'. 1556s 1556s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1556s 1556s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1556s 1556s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1556s 1556s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1556s Removing empty process `m.$proc$yosys-always_display-clk-1.v:18$1'. 1556s Cleaned up 0 empty switches. 1556s 1556s 2.12. Executing OPT_EXPR pass (perform const folding). 1556s Optimizing module m. 1556s 1556s 3. Executing OPT_EXPR pass (perform const folding). 1556s Optimizing module m. 1556s Removed 0 unused cells and 1 unused wires. 1556s 1556s -- Writing to `yosys-always_display-clk-2.v' using backend `verilog' -- 1556s 1556s 4. Executing Verilog backend. 1556s 1556s 4.1. Executing BMUXMAP pass. 1556s 1556s 4.2. Executing DEMUXMAP pass. 1556s Dumping module `\m'. 1556s 1556s End of script. Logfile hash: e35e8bb689, CPU: user 0.01s system 0.00s, MEM: 10.21 MB peak 1556s Yosys 0.33 (git sha1 2584903a060) 1556s Time spent: 34% 2x opt_expr (0 sec), 21% 1x clean (0 sec), ... 1556s + diff yosys-always_display-clk-1.v yosys-always_display-clk-2.v 1556s + test_always_display clk_rst -DEVENT_CLK_RST 1556s + local subtest=clk_rst 1556s + shift 1556s + ../../yosys -p 'read_verilog -DEVENT_CLK_RST always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst-1.v 1556s 1556s /----------------------------------------------------------------------------\ 1556s | | 1556s | yosys -- Yosys Open SYnthesis Suite | 1556s | | 1556s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1556s | | 1556s | Permission to use, copy, modify, and/or distribute this software for any | 1556s | purpose with or without fee is hereby granted, provided that the above | 1556s | copyright notice and this permission notice appear in all copies. | 1556s | | 1556s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1556s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1556s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1556s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1556s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1556s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1556s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1556s | | 1556s \----------------------------------------------------------------------------/ 1556s 1556s Yosys 0.33 (git sha1 2584903a060) 1556s 1556s 1556s -- Running command `read_verilog -DEVENT_CLK_RST always_display.v; proc; opt_expr -mux_bool; clean' -- 1556s 1556s 1. Executing Verilog-2005 frontend: always_display.v 1556s Parsing Verilog input from `always_display.v' to AST representation. 1556s Generating RTLIL representation for module `\m'. 1556s Successfully finished Verilog frontend. 1556s 1556s 2. Executing PROC pass (convert processes to netlists). 1556s 1556s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1556s Cleaned up 0 empty switches. 1556s 1556s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1556s Removed a total of 0 dead cases. 1556s 1556s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1556s Removed 1 redundant assignment. 1556s Promoted 1 assignment to connection. 1556s 1556s 2.4. Executing PROC_INIT pass (extract init attributes). 1556s 1556s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1556s 1556s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1556s Converted 0 switches. 1556s 1556s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1556s Creating decoders for process `\m.$proc$always_display.v:7$1'. 1556s 1556s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1556s 1556s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1556s 1556s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1556s 1556s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1556s Removing empty process `m.$proc$always_display.v:7$1'. 1556s Cleaned up 0 empty switches. 1556s 1556s 2.12. Executing OPT_EXPR pass (perform const folding). 1556s Optimizing module m. 1556s 1556s 3. Executing OPT_EXPR pass (perform const folding). 1556s Optimizing module m. 1556s Removed 0 unused cells and 1 unused wires. 1556s 1556s -- Writing to `yosys-always_display-clk_rst-1.v' using backend `verilog' -- 1556s 1556s 4. Executing Verilog backend. 1556s 1556s 4.1. Executing BMUXMAP pass. 1556s 1556s 4.2. Executing DEMUXMAP pass. 1556s Dumping module `\m'. 1556s 1556s End of script. Logfile hash: c95608ddf0, CPU: user 0.00s system 0.00s, MEM: 10.46 MB peak 1556s Yosys 0.33 (git sha1 2584903a060) 1556s Time spent: 34% 2x opt_expr (0 sec), 28% 1x clean (0 sec), ... 1556s + ../../yosys -p 'read_verilog yosys-always_display-clk_rst-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst-2.v 1556s 1556s /----------------------------------------------------------------------------\ 1556s | | 1556s | yosys -- Yosys Open SYnthesis Suite | 1556s | | 1556s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1556s | | 1556s | Permission to use, copy, modify, and/or distribute this software for any | 1556s | purpose with or without fee is hereby granted, provided that the above | 1556s | copyright notice and this permission notice appear in all copies. | 1556s | | 1556s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1556s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1556s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1556s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1556s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1556s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1556s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1556s | | 1556s \----------------------------------------------------------------------------/ 1556s 1556s Yosys 0.33 (git sha1 2584903a060) 1556s 1556s 1556s -- Running command `read_verilog yosys-always_display-clk_rst-1.v; proc; opt_expr -mux_bool; clean' -- 1556s 1556s 1. Executing Verilog-2005 frontend: yosys-always_display-clk_rst-1.v 1556s Parsing Verilog input from `yosys-always_display-clk_rst-1.v' to AST representation. 1556s Generating RTLIL representation for module `\m'. 1556s Successfully finished Verilog frontend. 1556s 1556s 2. Executing PROC pass (convert processes to netlists). 1556s 1556s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1556s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_rst-1.v:18$1'. 1556s Cleaned up 1 empty switch. 1556s 1556s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1556s Removed a total of 0 dead cases. 1556s 1556s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1556s Removed 1 redundant assignment. 1556s Promoted 1 assignment to connection. 1556s 1556s 2.4. Executing PROC_INIT pass (extract init attributes). 1556s 1556s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1556s 1556s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1556s Converted 0 switches. 1556s 1556s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1556s Creating decoders for process `\m.$proc$yosys-always_display-clk_rst-1.v:18$1'. 1556s 1556s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1556s 1556s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1556s 1556s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1556s 1556s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1556s Removing empty process `m.$proc$yosys-always_display-clk_rst-1.v:18$1'. 1556s Cleaned up 0 empty switches. 1556s 1556s 2.12. Executing OPT_EXPR pass (perform const folding). 1556s Optimizing module m. 1556s 1556s 3. Executing OPT_EXPR pass (perform const folding). 1556s Optimizing module m. 1556s Removed 0 unused cells and 1 unused wires. 1556s 1556s -- Writing to `yosys-always_display-clk_rst-2.v' using backend `verilog' -- 1556s 1556s 4. Executing Verilog backend. 1556s 1556s 4.1. Executing BMUXMAP pass. 1556s 1556s 4.2. Executing DEMUXMAP pass. 1556s Dumping module `\m'. 1556s 1556s End of script. Logfile hash: faf50513c3, CPU: user 0.01s system 0.00s, MEM: 10.45 MB peak 1556s Yosys 0.33 (git sha1 2584903a060) 1556s Time spent: 34% 2x opt_expr (0 sec), 21% 1x clean (0 sec), ... 1556s 1556s /----------------------------------------------------------------------------\ 1556s | | 1556s | yosys -- Yosys Open SYnthesis Suite | 1556s | | 1556s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1556s | | 1556s | Permission to use, copy, modify, and/or distribute this software for any | 1556s | purpose with or without fee is hereby granted, provided that the above | 1556s | copyright notice and this permission notice appear in all copies. | 1556s | | 1556s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1556s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1556s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1556s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1556s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1556s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1556s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1556s | | 1556s \----------------------------------------------------------------------------/ 1556s 1556s Yosys 0.33 (git sha1 2584903a060) 1556s 1556s 1556s -- Running command `read_verilog -DEVENT_STAR always_display.v; proc; opt_expr -mux_bool; clean' -- 1556s 1556s 1. Executing Verilog-2005 frontend: always_display.v 1556s Parsing Verilog input from `always_display.v' to AST representation. 1556s Generating RTLIL representation for module `\m'. 1556s Successfully finished Verilog frontend. 1556s 1556s 2. Executing PROC pass (convert processes to netlists). 1556s 1556s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1556s Cleaned up 0 empty switches. 1556s 1556s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1556s + diff yosys-always_display-clk_rst-1.v yosys-always_display-clk_rst-2.v 1556s + test_always_display star -DEVENT_STAR 1556s + local subtest=star 1556s + shift 1556s + ../../yosys -p 'read_verilog -DEVENT_STAR always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star-1.v 1556s + ../../yosys -p 'read_verilog yosys-always_display-star-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star-2.v 1556s Removed a total of 0 dead cases. 1556s 1556s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1556s Removed 1 redundant assignment. 1556s Promoted 1 assignment to connection. 1556s 1556s 2.4. Executing PROC_INIT pass (extract init attributes). 1556s 1556s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1556s 1556s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1556s Converted 0 switches. 1556s 1556s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1556s Creating decoders for process `\m.$proc$always_display.v:10$1'. 1556s 1556s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1556s 1556s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1556s 1556s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1556s 1556s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1556s Removing empty process `m.$proc$always_display.v:10$1'. 1556s Cleaned up 0 empty switches. 1556s 1556s 2.12. Executing OPT_EXPR pass (perform const folding). 1556s Optimizing module m. 1556s 1556s 3. Executing OPT_EXPR pass (perform const folding). 1556s Optimizing module m. 1556s Removed 0 unused cells and 1 unused wires. 1556s 1556s -- Writing to `yosys-always_display-star-1.v' using backend `verilog' -- 1556s 1556s 4. Executing Verilog backend. 1556s 1556s 4.1. Executing BMUXMAP pass. 1556s 1556s 4.2. Executing DEMUXMAP pass. 1556s Dumping module `\m'. 1556s 1556s End of script. Logfile hash: 7b2c5274a5, CPU: user 0.01s system 0.00s, MEM: 10.06 MB peak 1556s Yosys 0.33 (git sha1 2584903a060) 1556s Time spent: 36% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ... 1556s 1556s /----------------------------------------------------------------------------\ 1556s | | 1556s | yosys -- Yosys Open SYnthesis Suite | 1556s | | 1556s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1556s | | 1556s | Permission to use, copy, modify, and/or distribute this software for any | 1556s | purpose with or without fee is hereby granted, provided that the above | 1556s | copyright notice and this permission notice appear in all copies. | 1556s | | 1556s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1556s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1556s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1556s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1556s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1556s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1556s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1556s | | 1556s \----------------------------------------------------------------------------/ 1556s 1556s Yosys 0.33 (git sha1 2584903a060) 1556s 1556s 1556s -- Running command `read_verilog yosys-always_display-star-1.v; proc; opt_expr -mux_bool; clean' -- 1556s 1556s 1. Executing Verilog-2005 frontend: yosys-always_display-star-1.v 1556s Parsing Verilog input from `yosys-always_display-star-1.v' to AST representation. 1556s Generating RTLIL representation for module `\m'. 1556s Successfully finished Verilog frontend. 1556s 1556s 2. Executing PROC pass (convert processes to netlists). 1556s 1556s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1556s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-star-1.v:18$1'. 1556s Cleaned up 1 empty switch. 1556s 1556s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1556s Removed a total of 0 dead cases. 1556s 1556s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1556s Removed 1 redundant assignment. 1556s Promoted 1 assignment to connection. 1556s 1556s 2.4. Executing PROC_INIT pass (extract init attributes). 1556s 1556s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1556s + diff yosys-always_display-star-1.v yosys-always_display-star-2.v 1556s + test_always_display clk_en -DEVENT_CLK -DCOND_EN 1556s + local subtest=clk_en 1556s + shift 1556s + ../../yosys -p 'read_verilog -DEVENT_CLK -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_en-1.v 1556s + ../../yosys -p 'read_verilog yosys-always_display-clk_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_en-2.v 1556s 1556s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1556s Converted 0 switches. 1556s 1556s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1556s Creating decoders for process `\m.$proc$yosys-always_display-star-1.v:18$1'. 1556s 1556s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1556s 1556s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1556s 1556s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1556s 1556s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1556s Removing empty process `m.$proc$yosys-always_display-star-1.v:18$1'. 1556s Cleaned up 0 empty switches. 1556s 1556s 2.12. Executing OPT_EXPR pass (perform const folding). 1556s Optimizing module m. 1556s 1556s 3. Executing OPT_EXPR pass (perform const folding). 1556s Optimizing module m. 1556s Removed 0 unused cells and 1 unused wires. 1556s 1556s -- Writing to `yosys-always_display-star-2.v' using backend `verilog' -- 1556s 1556s 4. Executing Verilog backend. 1556s 1556s 4.1. Executing BMUXMAP pass. 1556s 1556s 4.2. Executing DEMUXMAP pass. 1556s Dumping module `\m'. 1556s 1556s End of script. Logfile hash: 8979c5de0b, CPU: user 0.00s system 0.00s, MEM: 10.18 MB peak 1556s Yosys 0.33 (git sha1 2584903a060) 1556s Time spent: 36% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ... 1556s 1556s /----------------------------------------------------------------------------\ 1556s | | 1556s | yosys -- Yosys Open SYnthesis Suite | 1556s | | 1556s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1556s | | 1556s | Permission to use, copy, modify, and/or distribute this software for any | 1556s | purpose with or without fee is hereby granted, provided that the above | 1556s | copyright notice and this permission notice appear in all copies. | 1556s | | 1556s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1556s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1556s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1556s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1556s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1556s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1556s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1556s | | 1556s \----------------------------------------------------------------------------/ 1556s 1556s Yosys 0.33 (git sha1 2584903a060) 1556s 1556s 1556s -- Running command `read_verilog -DEVENT_CLK -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -- 1556s 1556s 1. Executing Verilog-2005 frontend: always_display.v 1556s Parsing Verilog input from `always_display.v' to AST representation. 1556s Generating RTLIL representation for module `\m'. 1556s Successfully finished Verilog frontend. 1556s 1556s 2. Executing PROC pass (convert processes to netlists). 1556s 1556s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1556s Cleaned up 0 empty switches. 1556s 1556s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1556s Removed a total of 0 dead cases. 1556s 1556s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1556s Removed 0 redundant assignments. 1556s Promoted 0 assignments to connections. 1556s 1556s 2.4. Executing PROC_INIT pass (extract init attributes). 1556s 1556s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1556s 1556s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1556s Converted 0 switches. 1556s 1556s 1556s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1556s Creating decoders for process `\m.$proc$always_display.v:4$1'. 1556s 1/1: $display$always_display.v:15$2_EN 1556s 1556s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1556s 1556s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1556s 1556s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1556s 1556s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1556s Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:4$1'. 1556s Removing empty process `m.$proc$always_display.v:4$1'. 1556s Cleaned up 1 empty switch. 1556s 1556s 2.12. Executing OPT_EXPR pass (perform const folding). 1556s Optimizing module m. 1556s 1556s 3. Executing OPT_EXPR pass (perform const folding). 1556s Optimizing module m. 1556s 1556s Removed 0 unused cells and 3 unused wires. 1556s 1556s -- Writing to `yosys-always_display-clk_en-1.v' using backend `verilog' -- 1556s 1556s 4. Executing Verilog backend. 1556s 1556s 4.1. Executing BMUXMAP pass. 1556s 1556s 4.2. Executing DEMUXMAP pass. 1556s Dumping module `\m'. 1556s 1556s End of script. Logfile hash: 4f8a3b339c, CPU: user 0.01s system 0.00s, MEM: 10.54 MB peak 1556s Yosys 0.33 (git sha1 2584903a060) 1556s Time spent: 35% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ... 1556s 1556s /----------------------------------------------------------------------------\ 1556s | | 1556s | yosys -- Yosys Open SYnthesis Suite | 1556s | | 1556s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1556s | | 1556s | Permission to use, copy, modify, and/or distribute this software for any | 1556s | purpose with or without fee is hereby granted, provided that the above | 1556s | copyright notice and this permission notice appear in all copies. | 1556s | | 1556s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1556s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1556s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1556s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1556s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1556s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1556s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1556s | | 1556s \----------------------------------------------------------------------------/ 1556s 1556s Yosys 0.33 (git sha1 2584903a060) 1556s 1556s 1556s -- Running command `read_verilog yosys-always_display-clk_en-1.v; proc; opt_expr -mux_bool; clean' -- 1556s 1556s 1. Executing Verilog-2005 frontend: yosys-always_display-clk_en-1.v 1556s Parsing Verilog input from `yosys-always_display-clk_en-1.v' to AST representation. 1556s Generating RTLIL representation for module `\m'. 1556s Successfully finished Verilog frontend. 1556s 1556s 2. Executing PROC pass (convert processes to netlists). 1556s 1556s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1556s Cleaned up 0 empty switches. 1556s 1556s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1556s Removed a total of 0 dead cases. 1556s 1556s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1556s Removed 0 redundant assignments. 1556s Promoted 0 assignments to connections. 1556s 1556s 2.4. Executing PROC_INIT pass (extract init attributes). 1556s 1556s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1556s 1556s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1556s Converted 0 switches. 1556s 1556s 1556s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1556s Creating decoders for process `\m.$proc$yosys-always_display-clk_en-1.v:18$1'. 1556s 1/1: $write$yosys-always_display-clk_en-1.v:20$2_EN 1556s 1556s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1556s 1556s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1556s 1556s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1556s 1556s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1556s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_en-1.v:18$1'. 1556s Removing empty process `m.$proc$yosys-always_display-clk_en-1.v:18$1'. 1556s Cleaned up 1 empty switch. 1556s 1556s 2.12. Executing OPT_EXPR pass (perform const folding). 1556s Optimizing module m. 1556s 1556s 3. Executing OPT_EXPR pass (perform const folding). 1556s Optimizing module m. 1556s 1556s Removed 0 unused cells and 3 unused wires. 1556s 1556s -- Writing to `yosys-always_display-clk_en-2.v' using backend `verilog' -- 1556s 1556s 4. Executing Verilog backend. 1556s 1556s 4.1. Executing BMUXMAP pass. 1556s 1556s 4.2. Executing DEMUXMAP pass. 1556s Dumping module `\m'. 1556s 1556s End of script. Logfile hash: 51e7fa3902, CPU: user 0.01s system 0.00s, MEM: 10.56 MB peak 1556s Yosys 0.33 (git sha1 2584903a060) 1556s Time spent: 35% 2x opt_expr (0 sec), 27% 1x clean (0 sec), ... 1556s 1556s /----------------------------------------------------------------------------\ 1556s | | 1556s | yosys -- Yosys Open SYnthesis Suite | 1556s | | 1556s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1556s | | 1556s | Permission to use, copy, modify, and/or distribute this software for any | 1556s | purpose with or without fee is hereby granted, provided that the above | 1556s | copyright notice and this permission notice appear in all copies. | 1556s | | 1556s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1556s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1556s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1556s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1556s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1556s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1556s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1556s | | 1556s \----------------------------------------------------------------------------/ 1556s 1556s Yosys 0.33 (git sha1 2584903a060) 1556s 1556s 1556s -- Running command `read_verilog -DEVENT_CLK_RST -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -- 1556s 1556s 1. Executing Verilog-2005 frontend: always_display.v 1556s Parsing Verilog input from `always_display.v' to AST representation. 1556s Generating RTLIL representation for module `\m'. 1556s Successfully finished Verilog frontend. 1556s 1556s 2. Executing PROC pass (convert processes to netlists). 1556s 1556s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1556s Cleaned up 0 empty switches. 1556s 1556s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1556s Removed a total of 0 dead cases. 1556s 1556s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1556s Removed 0 redundant assignments. 1556s Promoted 0 assignments to connections. 1556s 1556s 2.4. Executing PROC_INIT pass (extract init attributes). 1556s 1556s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1556s 1556s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1556s Converted 0 switches. 1556s 1556s 1556s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1556s Creating decoders for process `\m.$proc$always_display.v:7$1'. 1556s 1/1: $display$always_display.v:15$2_EN 1556s 1556s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1556s 1556s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1556s 1556s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1556s 1556s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1556s Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:7$1'. 1556s Removing empty process `m.$proc$always_display.v:7$1'. 1556s Cleaned up 1 empty switch. 1556s 1556s 2.12. Executing OPT_EXPR pass (perform const folding). 1556s Optimizing module m. 1556s 1556s 3. Executing OPT_EXPR pass (perform const folding). 1556s Optimizing module m. 1556s 1556s Removed 0 unused cells and 3 unused wires. 1556s 1556s -- Writing to `yosys-always_display-clk_rst_en-1.v' using backend `verilog' -- 1556s 1556s 4. Executing Verilog backend. 1556s 1556s 4.1. Executing BMUXMAP pass. 1556s 1556s 4.2. Executing DEMUXMAP pass. 1556s Dumping module `\m'. 1556s 1556s End of script. Logfile hash: f9b4876f33, CPU: user 0.01s system 0.00s, MEM: 10.24 MB peak 1556s Yosys 0.33 (git sha1 2584903a060) 1556s Time spent: 38% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ... 1556s + diff yosys-always_display-clk_en-1.v yosys-always_display-clk_en-2.v 1556s + test_always_display clk_rst_en -DEVENT_CLK_RST -DCOND_EN 1556s + local subtest=clk_rst_en 1556s + shift 1556s + ../../yosys -p 'read_verilog -DEVENT_CLK_RST -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst_en-1.v 1556s + ../../yosys -p 'read_verilog yosys-always_display-clk_rst_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst_en-2.v 1556s 1556s /----------------------------------------------------------------------------\ 1556s | | 1556s | yosys -- Yosys Open SYnthesis Suite | 1556s | | 1556s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1556s | | 1556s | Permission to use, copy, modify, and/or distribute this software for any | 1556s | purpose with or without fee is hereby granted, provided that the above | 1556s | copyright notice and this permission notice appear in all copies. | 1556s | | 1556s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1556s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1556s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1556s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1556s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1556s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1556s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1556s | | 1556s \----------------------------------------------------------------------------/ 1556s 1556s Yosys 0.33 (git sha1 2584903a060) 1556s 1556s 1556s -- Running command `read_verilog yosys-always_display-clk_rst_en-1.v; proc; opt_expr -mux_bool; clean' -- 1556s 1556s 1. Executing Verilog-2005 frontend: yosys-always_display-clk_rst_en-1.v 1556s Parsing Verilog input from `yosys-always_display-clk_rst_en-1.v' to AST representation. 1556s Generating RTLIL representation for module `\m'. 1556s Successfully finished Verilog frontend. 1556s 1556s 2. Executing PROC pass (convert processes to netlists). 1556s 1556s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1556s Cleaned up 0 empty switches. 1556s 1556s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1556s Removed a total of 0 dead cases. 1556s 1556s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1556s Removed 0 redundant assignments. 1556s Promoted 0 assignments to connections. 1556s 1556s 2.4. Executing PROC_INIT pass (extract init attributes). 1556s 1556s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1556s 1556s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1556s Converted 0 switches. 1556s 1556s 1556s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1556s Creating decoders for process `\m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'. 1556s 1/1: $write$yosys-always_display-clk_rst_en-1.v:20$2_EN 1556s 1556s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1556s 1556s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1556s 1556s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1556s 1556s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1556s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'. 1556s Removing empty process `m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'. 1556s Cleaned up 1 empty switch. 1556s 1556s 2.12. Executing OPT_EXPR pass (perform const folding). 1556s Optimizing module m. 1556s + diff yosys-always_display-clk_rst_en-1.v yosys-always_display-clk_rst_en-2.v 1556s + test_always_display star_en -DEVENT_STAR -DCOND_EN 1556s + local subtest=star_en 1556s + shift 1556s + ../../yosys -p 'read_verilog -DEVENT_STAR -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star_en-1.v 1556s 1556s 3. Executing OPT_EXPR pass (perform const folding). 1556s Optimizing module m. 1556s 1556s Removed 0 unused cells and 3 unused wires. 1556s 1556s -- Writing to `yosys-always_display-clk_rst_en-2.v' using backend `verilog' -- 1556s 1556s 4. Executing Verilog backend. 1556s 1556s 4.1. Executing BMUXMAP pass. 1556s 1556s 4.2. Executing DEMUXMAP pass. 1556s Dumping module `\m'. 1556s 1556s End of script. Logfile hash: 0c4b4eaa9c, CPU: user 0.01s system 0.00s, MEM: 10.34 MB peak 1556s Yosys 0.33 (git sha1 2584903a060) 1556s Time spent: 38% 2x opt_expr (0 sec), 20% 1x clean (0 sec), ... 1556s 1556s /----------------------------------------------------------------------------\ 1556s | | 1556s | yosys -- Yosys Open SYnthesis Suite | 1556s | | 1556s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1556s | | 1556s | Permission to use, copy, modify, and/or distribute this software for any | 1556s | purpose with or without fee is hereby granted, provided that the above | 1556s | copyright notice and this permission notice appear in all copies. | 1556s | | 1556s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1556s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1556s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1556s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1556s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1556s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1556s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1556s | | 1556s \----------------------------------------------------------------------------/ 1556s 1556s Yosys 0.33 (git sha1 2584903a060) 1556s 1556s 1556s -- Running command `read_verilog -DEVENT_STAR -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -- 1556s 1556s 1. Executing Verilog-2005 frontend: always_display.v 1556s Parsing Verilog input from `always_display.v' to AST representation. 1556s Generating RTLIL representation for module `\m'. 1556s Successfully finished Verilog frontend. 1556s 1556s 2. Executing PROC pass (convert processes to netlists). 1556s 1556s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1556s Cleaned up 0 empty switches. 1556s 1556s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1556s Removed a total of 0 dead cases. 1556s 1556s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1556s Removed 0 redundant assignments. 1556s Promoted 0 assignments to connections. 1556s 1556s 2.4. Executing PROC_INIT pass (extract init attributes). 1556s 1556s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1556s 1556s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1556s Converted 0 switches. 1556s 1556s 1556s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1556s Creating decoders for process `\m.$proc$always_display.v:10$1'. 1556s 1/1: $display$always_display.v:15$2_EN 1556s 1556s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1556s 1556s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1556s 1556s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1556s 1556s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1556s Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:10$1'. 1556s Removing empty process `m.$proc$always_display.v:10$1'. 1556s Cleaned up 1 empty switch. 1556s 1556s 2.12. Executing OPT_EXPR pass (perform const folding). 1556s Optimizing module m. 1556s 1556s 3. Executing OPT_EXPR pass (perform const folding). 1556s Optimizing module m. 1556s 1556s Removed 0 unused cells and 3 unused wires. 1556s 1556s -- Writing to `yosys-always_display-star_en-1.v' using backend `verilog' -- 1556s 1556s 4. Executing Verilog backend. 1556s 1556s 4.1. Executing BMUXMAP pass. 1556s 1556s 4.2. Executing DEMUXMAP pass. 1556s + ../../yosys -p 'read_verilog yosys-always_display-star_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star_en-2.v 1556s Dumping module `\m'. 1556s 1556s End of script. Logfile hash: d6a7335726, CPU: user 0.00s system 0.00s, MEM: 10.24 MB peak 1556s Yosys 0.33 (git sha1 2584903a060) 1556s Time spent: 41% 2x opt_expr (0 sec), 19% 1x clean (0 sec), ... 1556s 1556s /----------------------------------------------------------------------------\ 1556s | | 1556s | yosys -- Yosys Open SYnthesis Suite | 1556s | | 1556s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1556s | | 1556s | Permission to use, copy, modify, and/or distribute this software for any | 1556s | purpose with or without fee is hereby granted, provided that the above | 1556s | copyright notice and this permission notice appear in all copies. | 1556s | | 1556s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1556s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1556s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1556s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1556s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1556s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1556s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1556s | | 1556s \----------------------------------------------------------------------------/ 1556s 1556s Yosys 0.33 (git sha1 2584903a060) 1556s 1556s 1556s -- Running command `read_verilog yosys-always_display-star_en-1.v; proc; opt_expr -mux_bool; clean' -- 1556s 1556s 1. Executing Verilog-2005 frontend: yosys-always_display-star_en-1.v 1556s Parsing Verilog input from `yosys-always_display-star_en-1.v' to AST representation. 1556s Generating RTLIL representation for module `\m'. 1556s Successfully finished Verilog frontend. 1556s 1556s 2. Executing PROC pass (convert processes to netlists). 1556s 1556s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1556s Cleaned up 0 empty switches. 1556s 1556s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1556s Removed a total of 0 dead cases. 1556s 1556s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1556s Removed 0 redundant assignments. 1556s Promoted 0 assignments to connections. 1556s 1556s 2.4. Executing PROC_INIT pass (extract init attributes). 1556s 1556s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1556s 1556s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1556s Converted 0 switches. 1556s 1556s 1556s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1556s Creating decoders for process `\m.$proc$yosys-always_display-star_en-1.v:18$1'. 1556s 1/1: $write$yosys-always_display-star_en-1.v:20$2_EN 1556s 1556s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1556s 1556s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1556s 1556s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1556s 1556s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1556s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-star_en-1.v:18$1'. 1556s Removing empty process `m.$proc$yosys-always_display-star_en-1.v:18$1'. 1556s Cleaned up 1 empty switch. 1556s 1556s 2.12. Executing OPT_EXPR pass (perform const folding). 1556s Optimizing module m. 1556s 1556s 3. Executing OPT_EXPR pass (perform const folding). 1556s Optimizing module m. 1556s 1556s Removed 0 unused cells and 3 unused wires. 1556s 1556s -- Writing to `yosys-always_display-star_en-2.v' using backend `verilog' -- 1556s 1556s 4. Executing Verilog backend. 1556s 1556s 4.1. Executing BMUXMAP pass. 1556s 1556s 4.2. Executing DEMUXMAP pass. 1556s Dumping module `\m'. 1556s 1556s End of script. Logfile hash: 18895a2046, CPU: user 0.01s system 0.00s, MEM: 10.14 MB peak 1556s Yosys 0.33 (git sha1 2584903a060) 1556s Time spent: 36% 2x opt_expr (0 sec), 21% 1x clean (0 sec), ... 1556s + diff yosys-always_display-star_en-1.v yosys-always_display-star_en-2.v 1556s + test_roundtrip dec_unsigned -DBASE_DEC -DSIGN= 1556s + local subtest=dec_unsigned 1556s + shift 1556s + ../../yosys -p 'read_verilog -DBASE_DEC -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-dec_unsigned-1.v 1556s 1556s /----------------------------------------------------------------------------\ 1556s | | 1556s | yosys -- Yosys Open SYnthesis Suite | 1556s | | 1556s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1556s | | 1556s | Permission to use, copy, modify, and/or distribute this software for any | 1556s | purpose with or without fee is hereby granted, provided that the above | 1556s | copyright notice and this permission notice appear in all copies. | 1556s | | 1556s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1556s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1556s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1556s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1556s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1556s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1556s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1556s | | 1556s \----------------------------------------------------------------------------/ 1556s 1556s Yosys 0.33 (git sha1 2584903a060) 1556s 1556s 1556s -- Running command `read_verilog -DBASE_DEC -DSIGN= roundtrip.v; proc; clean' -- 1556s 1556s 1. Executing Verilog-2005 frontend: roundtrip.v 1556s Parsing Verilog input from `roundtrip.v' to AST representation. 1556s Generating RTLIL representation for module `\m'. 1556s Successfully finished Verilog frontend. 1556s 1556s 2. Executing PROC pass (convert processes to netlists). 1556s 1556s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1556s Cleaned up 0 empty switches. 1556s 1556s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1556s Removed a total of 0 dead cases. 1556s 1556s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1556s Removed 1 redundant assignment. 1556s Promoted 1 assignment to connection. 1556s 1556s 2.4. Executing PROC_INIT pass (extract init attributes). 1556s 1556s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1556s 1556s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1556s Converted 0 switches. 1556s 1556s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1556s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 1556s 1556s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1556s 1556s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1556s 1556s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1556s 1556s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1556s Removing empty process `m.$proc$roundtrip.v:3$1'. 1556s Cleaned up 0 empty switches. 1556s 1556s 2.12. Executing OPT_EXPR pass (perform const folding). 1556s Optimizing module m. 1556s Removed 0 unused cells and 1 unused wires. 1556s 1556s -- Writing to `yosys-roundtrip-dec_unsigned-1.v' using backend `verilog' -- 1556s 1556s 3. Executing Verilog backend. 1556s 1556s 3.1. Executing BMUXMAP pass. 1556s 1556s 3.2. Executing DEMUXMAP pass. 1556s Dumping module `\m'. 1556s 1556s End of script. Logfile hash: bfb187b86d, CPU: user 0.01s system 0.00s, MEM: 10.24 MB peak 1556s Yosys 0.33 (git sha1 2584903a060) 1556s Time spent: 26% 1x clean (0 sec), 19% 1x opt_expr (0 sec), ... 1556s 1556s /----------------------------------------------------------------------------\ 1556s | | 1556s | yosys -- Yosys Open SYnthesis Suite | 1556s | | 1556s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1556s | | 1556s | Permission to use, copy, modify, and/or distribute this software for any | 1556s | purpose with or without fee is hereby granted, provided that the above | 1556s | copyright notice and this permission notice appear in all copies. | 1556s | | 1556s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1556s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1556s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1556s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1556s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1556s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1556s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1556s | | 1556s \----------------------------------------------------------------------------/ 1556s 1556s Yosys 0.33 (git sha1 2584903a060) 1556s 1556s 1556s -- Running command `read_verilog yosys-roundtrip-dec_unsigned-1.v; proc; clean' -- 1556s 1556s 1. Executing Verilog-2005 frontend: yosys-roundtrip-dec_unsigned-1.v 1556s Parsing Verilog input from `yosys-roundtrip-dec_unsigned-1.v' to AST representation. 1556s Generating RTLIL representation for module `\m'. 1556s Successfully finished Verilog frontend. 1556s 1556s 2. Executing PROC pass (convert processes to netlists). 1556s 1556s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1556s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'. 1556s Cleaned up 1 empty switch. 1556s 1556s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1556s Removed a total of 0 dead cases. 1556s 1556s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1556s Removed 1 redundant assignment. 1556s Promoted 1 assignment to connection. 1556s 1556s 2.4. Executing PROC_INIT pass (extract init attributes). 1556s 1556s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1556s 1556s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1556s Converted 0 switches. 1556s 1556s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1556s Creating decoders for process `\m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'. 1556s 1556s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1556s 1556s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1556s 1556s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1556s 1556s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1556s Removing empty process `m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'. 1556s Cleaned up 0 empty switches. 1556s 1556s 2.12. Executing OPT_EXPR pass (perform const folding). 1556s Optimizing module m. 1556s Removed 0 unused cells and 1 unused wires. 1556s 1556s -- Writing to `yosys-roundtrip-dec_unsigned-2.v' using backend `verilog' -- 1556s 1556s 3. Executing Verilog backend. 1556s 1556s 3.1. Executing BMUXMAP pass. 1556s 1556s 3.2. Executing DEMUXMAP pass. 1556s Dumping module `\m'. 1556s 1556s End of script. Logfile hash: 4be9539e85, CPU: user 0.00s system 0.00s, MEM: 10.25 MB peak 1556s Yosys 0.33 (git sha1 2584903a060) 1556s Time spent: 26% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... 1556s + ../../yosys -p 'read_verilog yosys-roundtrip-dec_unsigned-1.v; proc; clean' -o yosys-roundtrip-dec_unsigned-2.v 1556s + diff yosys-roundtrip-dec_unsigned-1.v yosys-roundtrip-dec_unsigned-2.v 1556s + iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned roundtrip.v roundtrip_tb.v 1556s + ./iverilog-roundtrip-dec_unsigned 1556s + iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned-1 yosys-roundtrip-dec_unsigned-1.v roundtrip_tb.v 1556s + ./iverilog-roundtrip-dec_unsigned-1 1556s + iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned-2 yosys-roundtrip-dec_unsigned-2.v roundtrip_tb.v 1556s + ./iverilog-roundtrip-dec_unsigned-1 1556s + diff iverilog-roundtrip-dec_unsigned.log iverilog-roundtrip-dec_unsigned-1.log 1556s + diff iverilog-roundtrip-dec_unsigned-1.log iverilog-roundtrip-dec_unsigned-2.log 1556s + test_roundtrip dec_signed -DBASE_DEC -DSIGN=signed 1556s + local subtest=dec_signed 1556s + shift 1556s + ../../yosys -p 'read_verilog -DBASE_DEC -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-dec_signed-1.v 1556s 1556s /----------------------------------------------------------------------------\ 1556s | | 1556s | yosys -- Yosys Open SYnthesis Suite | 1556s | | 1556s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1556s | | 1556s | Permission to use, copy, modify, and/or distribute this software for any | 1556s | purpose with or without fee is hereby granted, provided that the above | 1556s | copyright notice and this permission notice appear in all copies. | 1556s | | 1556s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1556s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1556s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1556s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1556s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1556s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1556s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1556s | | 1556s \----------------------------------------------------------------------------/ 1556s 1556s Yosys 0.33 (git sha1 2584903a060) 1556s 1556s 1556s -- Running command `read_verilog -DBASE_DEC -DSIGN=signed roundtrip.v; proc; clean' -- 1556s 1556s 1. Executing Verilog-2005 frontend: roundtrip.v 1556s Parsing Verilog input from `roundtrip.v' to AST representation. 1556s Generating RTLIL representation for module `\m'. 1556s Successfully finished Verilog frontend. 1556s 1556s 2. Executing PROC pass (convert processes to netlists). 1556s 1556s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1556s Cleaned up 0 empty switches. 1556s 1556s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1556s Removed a total of 0 dead cases. 1556s 1556s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1556s Removed 1 redundant assignment. 1556s Promoted 1 assignment to connection. 1556s 1556s 2.4. Executing PROC_INIT pass (extract init attributes). 1556s 1556s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1556s 1556s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1556s Converted 0 switches. 1556s 1556s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1556s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 1556s 1556s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1556s 1556s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1556s 1556s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1556s 1556s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1556s Removing empty process `m.$proc$roundtrip.v:3$1'. 1556s Cleaned up 0 empty switches. 1556s 1556s 2.12. Executing OPT_EXPR pass (perform const folding). 1556s Optimizing module m. 1556s Removed 0 unused cells and 1 unused wires. 1556s 1556s -- Writing to `yosys-roundtrip-dec_signed-1.v' using backend `verilog' -- 1556s 1556s 3. Executing Verilog backend. 1556s + ../../yosys -p 'read_verilog yosys-roundtrip-dec_signed-1.v; proc; clean' -o yosys-roundtrip-dec_signed-2.v 1556s 1556s 3.1. Executing BMUXMAP pass. 1556s 1556s 3.2. Executing DEMUXMAP pass. 1556s Dumping module `\m'. 1556s 1556s End of script. Logfile hash: bbdfa5ca92, CPU: user 0.01s system 0.00s, MEM: 10.21 MB peak 1556s Yosys 0.33 (git sha1 2584903a060) 1556s Time spent: 26% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... 1556s 1556s /----------------------------------------------------------------------------\ 1556s | | 1556s | yosys -- Yosys Open SYnthesis Suite | 1556s | | 1556s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1556s | | 1556s | Permission to use, copy, modify, and/or distribute this software for any | 1556s | purpose with or without fee is hereby granted, provided that the above | 1556s | copyright notice and this permission notice appear in all copies. | 1556s | | 1556s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1556s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1556s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1556s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1556s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1556s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1556s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1556s | | 1556s \----------------------------------------------------------------------------/ 1556s 1556s Yosys 0.33 (git sha1 2584903a060) 1556s 1556s 1556s -- Running command `read_verilog yosys-roundtrip-dec_signed-1.v; proc; clean' -- 1556s 1556s 1. Executing Verilog-2005 frontend: yosys-roundtrip-dec_signed-1.v 1556s Parsing Verilog input from `yosys-roundtrip-dec_signed-1.v' to AST representation. 1556s Generating RTLIL representation for module `\m'. 1556s Successfully finished Verilog frontend. 1556s 1556s 2. Executing PROC pass (convert processes to netlists). 1556s 1556s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1556s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'. 1556s Cleaned up 1 empty switch. 1556s 1556s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1556s Removed a total of 0 dead cases. 1556s 1556s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1556s Removed 1 redundant assignment. 1556s Promoted 1 assignment to connection. 1556s 1556s 2.4. Executing PROC_INIT pass (extract init attributes). 1556s 1556s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1556s 1556s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1556s Converted 0 switches. 1556s 1556s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1556s Creating decoders for process `\m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'. 1556s 1556s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1556s 1556s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1556s 1556s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1556s 1556s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1556s Removing empty process `m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'. 1556s Cleaned up 0 empty switches. 1556s 1556s 2.12. Executing OPT_EXPR pass (perform const folding). 1556s Optimizing module m. 1556s Removed 0 unused cells and 1 unused wires. 1556s 1556s -- Writing to `yosys-roundtrip-dec_signed-2.v' using backend `verilog' -- 1556s 1556s 3. Executing Verilog backend. 1556s 1556s 3.1. Executing BMUXMAP pass. 1556s 1556s 3.2. Executing DEMUXMAP pass. 1556s + diff yosys-roundtrip-dec_signed-1.v yosys-roundtrip-dec_signed-2.v 1556s Dumping module `\m'. 1556s 1556s End of script. Logfile hash: b233de92a6, CPU: user 0.01s system 0.00s, MEM: 10.17 MB peak 1556s Yosys 0.33 (git sha1 2584903a060) 1556s Time spent: 27% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... 1556s + iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed roundtrip.v roundtrip_tb.v 1556s + ./iverilog-roundtrip-dec_signed 1556s + iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed-1 yosys-roundtrip-dec_signed-1.v roundtrip_tb.v 1556s + ./iverilog-roundtrip-dec_signed-1 1556s + iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed-2 yosys-roundtrip-dec_signed-2.v roundtrip_tb.v 1556s + ./iverilog-roundtrip-dec_signed-1 1557s + diff iverilog-roundtrip-dec_signed.log iverilog-roundtrip-dec_signed-1.log 1557s 1557s /----------------------------------------------------------------------------\ 1557s | | 1557s | yosys -- Yosys Open SYnthesis Suite | 1557s | | 1557s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1557s | | 1557s | Permission to use, copy, modify, and/or distribute this software for any | 1557s | purpose with or without fee is hereby granted, provided that the above | 1557s | copyright notice and this permission notice appear in all copies. | 1557s | | 1557s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1557s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1557s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1557s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1557s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1557s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1557s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1557s | | 1557s \----------------------------------------------------------------------------/ 1557s 1557s Yosys 0.33 (git sha1 2584903a060) 1557s 1557s 1557s -- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -- 1557s 1557s 1. Executing Verilog-2005 frontend: roundtrip.v 1557s Parsing Verilog input from `roundtrip.v' to AST representation. 1557s Generating RTLIL representation for module `\m'. 1557s Successfully finished Verilog frontend. 1557s 1557s 2. Executing PROC pass (convert processes to netlists). 1557s 1557s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1557s Cleaned up 0 empty switches. 1557s 1557s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1557s Removed a total of 0 dead cases. 1557s 1557s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1557s Removed 1 redundant assignment. 1557s Promoted 1 assignment to connection. 1557s 1557s 2.4. Executing PROC_INIT pass (extract init attributes). 1557s 1557s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1557s 1557s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1557s Converted 0 switches. 1557s 1557s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1557s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 1557s 1557s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1557s 1557s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1557s 1557s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1557s 1557s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1557s Removing empty process `m.$proc$roundtrip.v:3$1'. 1557s Cleaned up 0 empty switches. 1557s 1557s 2.12. Executing OPT_EXPR pass (perform const folding). 1557s Optimizing module m. 1557s Removed 0 unused cells and 1 unused wires. 1557s 1557s -- Writing to `yosys-roundtrip-hex_unsigned-1.v' using backend `verilog' -- 1557s 1557s 3. Executing Verilog backend. 1557s 1557s 3.1. Executing BMUXMAP pass. 1557s 1557s 3.2. Executing DEMUXMAP pass. 1557s Dumping module `\m'. 1557s 1557s End of script. Logfile hash: 2377f2e106, CPU: user 0.01s system 0.00s, MEM: 10.22 MB peak 1557s Yosys 0.33 (git sha1 2584903a060) 1557s Time spent: 28% 1x clean (0 sec), 18% 1x opt_expr (0 sec), ... 1557s + diff iverilog-roundtrip-dec_signed-1.log iverilog-roundtrip-dec_signed-2.log 1557s + test_roundtrip hex_unsigned -DBASE_HEX -DSIGN= 1557s + local subtest=hex_unsigned 1557s + shift 1557s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-hex_unsigned-1.v 1557s 1557s /----------------------------------------------------------------------------\ 1557s | | 1557s | yosys -- Yosys Open SYnthesis Suite | 1557s | | 1557s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1557s | | 1557s | Permission to use, copy, modify, and/or distribute this software for any | 1557s | purpose with or without fee is hereby granted, provided that the above | 1557s | copyright notice and this permission notice appear in all copies. | 1557s | | 1557s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1557s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1557s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1557s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1557s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1557s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1557s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1557s | | 1557s \----------------------------------------------------------------------------/ 1557s 1557s Yosys 0.33 (git sha1 2584903a060) 1557s 1557s 1557s -- Running command `read_verilog yosys-roundtrip-hex_unsigned-1.v; proc; clean' -- 1557s 1557s 1. Executing Verilog-2005 frontend: yosys-roundtrip-hex_unsigned-1.v 1557s Parsing Verilog input from `yosys-roundtrip-hex_unsigned-1.v' to AST representation. 1557s Generating RTLIL representation for module `\m'. 1557s Successfully finished Verilog frontend. 1557s 1557s 2. Executing PROC pass (convert processes to netlists). 1557s 1557s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1557s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'. 1557s Cleaned up 1 empty switch. 1557s 1557s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1557s Removed a total of 0 dead cases. 1557s 1557s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1557s Removed 1 redundant assignment. 1557s Promoted 1 assignment to connection. 1557s 1557s 2.4. Executing PROC_INIT pass (extract init attributes). 1557s 1557s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1557s 1557s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1557s Converted 0 switches. 1557s 1557s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1557s Creating decoders for process `\m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'. 1557s 1557s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1557s 1557s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1557s 1557s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1557s 1557s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1557s Removing empty process `m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'. 1557s Cleaned up 0 empty switches. 1557s 1557s 2.12. Executing OPT_EXPR pass (perform const folding). 1557s + ../../yosys -p 'read_verilog yosys-roundtrip-hex_unsigned-1.v; proc; clean' -o yosys-roundtrip-hex_unsigned-2.v 1557s Optimizing module m. 1557s Removed 0 unused cells and 1 unused wires. 1557s 1557s -- Writing to `yosys-roundtrip-hex_unsigned-2.v' using backend `verilog' -- 1557s 1557s 3. Executing Verilog backend. 1557s 1557s 3.1. Executing BMUXMAP pass. 1557s 1557s 3.2. Executing DEMUXMAP pass. 1557s Dumping module `\m'. 1557s 1557s End of script. Logfile hash: 06bfea69c8, CPU: user 0.01s system 0.00s, MEM: 10.30 MB peak 1557s Yosys 0.33 (git sha1 2584903a060) 1557s Time spent: 28% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... 1557s + diff yosys-roundtrip-hex_unsigned-1.v yosys-roundtrip-hex_unsigned-2.v 1557s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned roundtrip.v roundtrip_tb.v 1557s + ./iverilog-roundtrip-hex_unsigned 1557s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned-1 yosys-roundtrip-hex_unsigned-1.v roundtrip_tb.v 1557s + ./iverilog-roundtrip-hex_unsigned-1 1557s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned-2 yosys-roundtrip-hex_unsigned-2.v roundtrip_tb.v 1557s + ./iverilog-roundtrip-hex_unsigned-1 1557s + diff iverilog-roundtrip-hex_unsigned.log iverilog-roundtrip-hex_unsigned-1.log 1557s + diff iverilog-roundtrip-hex_unsigned-1.log iverilog-roundtrip-hex_unsigned-2.log 1557s + test_roundtrip hex_signed -DBASE_HEX -DSIGN=signed 1557s + local subtest=hex_signed 1557s + shift 1557s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-hex_signed-1.v 1557s 1557s /----------------------------------------------------------------------------\ 1557s | | 1557s | yosys -- Yosys Open SYnthesis Suite | 1557s | | 1557s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1557s | | 1557s | Permission to use, copy, modify, and/or distribute this software for any | 1557s | purpose with or without fee is hereby granted, provided that the above | 1557s | copyright notice and this permission notice appear in all copies. | 1557s | | 1557s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1557s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1557s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1557s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1557s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1557s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1557s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1557s | | 1557s \----------------------------------------------------------------------------/ 1557s 1557s Yosys 0.33 (git sha1 2584903a060) 1557s 1557s 1557s -- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -- 1557s 1557s 1. Executing Verilog-2005 frontend: roundtrip.v 1557s Parsing Verilog input from `roundtrip.v' to AST representation. 1557s Generating RTLIL representation for module `\m'. 1557s Successfully finished Verilog frontend. 1557s 1557s 2. Executing PROC pass (convert processes to netlists). 1557s 1557s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1557s Cleaned up 0 empty switches. 1557s 1557s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1557s Removed a total of 0 dead cases. 1557s 1557s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1557s Removed 1 redundant assignment. 1557s Promoted 1 assignment to connection. 1557s 1557s 2.4. Executing PROC_INIT pass (extract init attributes). 1557s 1557s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1557s 1557s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1557s Converted 0 switches. 1557s 1557s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1557s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 1557s 1557s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1557s 1557s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1557s 1557s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1557s 1557s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1557s Removing empty process `m.$proc$roundtrip.v:3$1'. 1557s Cleaned up 0 empty switches. 1557s 1557s 2.12. Executing OPT_EXPR pass (perform const folding). 1557s Optimizing module m. 1557s Removed 0 unused cells and 1 unused wires. 1557s 1557s -- Writing to `yosys-roundtrip-hex_signed-1.v' using backend `verilog' -- 1557s 1557s 3. Executing Verilog backend. 1557s 1557s 3.1. Executing BMUXMAP pass. 1557s 1557s 3.2. Executing DEMUXMAP pass. 1557s Dumping module `\m'. 1557s 1557s End of script. Logfile hash: 824c3b1e65, CPU: user 0.01s system 0.00s, MEM: 10.30 MB peak 1557s Yosys 0.33 (git sha1 2584903a060) 1557s Time spent: 28% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... 1557s + ../../yosys -p 'read_verilog yosys-roundtrip-hex_signed-1.v; proc; clean' -o yosys-roundtrip-hex_signed-2.v 1557s 1557s /----------------------------------------------------------------------------\ 1557s | | 1557s | yosys -- Yosys Open SYnthesis Suite | 1557s | | 1557s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1557s | | 1557s | Permission to use, copy, modify, and/or distribute this software for any | 1557s | purpose with or without fee is hereby granted, provided that the above | 1557s | copyright notice and this permission notice appear in all copies. | 1557s | | 1557s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1557s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1557s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1557s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1557s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1557s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1557s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1557s | | 1557s \----------------------------------------------------------------------------/ 1557s 1557s Yosys 0.33 (git sha1 2584903a060) 1557s 1557s 1557s -- Running command `read_verilog yosys-roundtrip-hex_signed-1.v; proc; clean' -- 1557s 1557s 1. Executing Verilog-2005 frontend: yosys-roundtrip-hex_signed-1.v 1557s Parsing Verilog input from `yosys-roundtrip-hex_signed-1.v' to AST representation. 1557s Generating RTLIL representation for module `\m'. 1557s Successfully finished Verilog frontend. 1557s 1557s 2. Executing PROC pass (convert processes to netlists). 1557s 1557s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1557s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'. 1557s Cleaned up 1 empty switch. 1557s 1557s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1557s Removed a total of 0 dead cases. 1557s 1557s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1557s Removed 1 redundant assignment. 1557s Promoted 1 assignment to connection. 1557s 1557s 2.4. Executing PROC_INIT pass (extract init attributes). 1557s 1557s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1557s 1557s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1557s Converted 0 switches. 1557s 1557s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1557s Creating decoders for process `\m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'. 1557s 1557s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1557s 1557s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1557s 1557s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1557s 1557s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1557s Removing empty process `m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'. 1557s Cleaned up 0 empty switches. 1557s 1557s 2.12. Executing OPT_EXPR pass (perform const folding). 1557s Optimizing module m. 1557s Removed 0 unused cells and 1 unused wires. 1557s 1557s -- Writing to `yosys-roundtrip-hex_signed-2.v' using backend `verilog' -- 1557s 1557s 3. Executing Verilog backend. 1557s 1557s 3.1. Executing BMUXMAP pass. 1557s 1557s 3.2. Executing DEMUXMAP pass. 1557s Dumping module `\m'. 1557s 1557s End of script. Logfile hash: f18b3fa15b, CPU: user 0.01s system 0.00s, MEM: 10.38 MB peak 1557s Yosys 0.33 (git sha1 2584903a060) 1557s Time spent: 27% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... 1557s + diff yosys-roundtrip-hex_signed-1.v yosys-roundtrip-hex_signed-2.v 1557s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed roundtrip.v roundtrip_tb.v 1557s + ./iverilog-roundtrip-hex_signed 1557s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed-1 yosys-roundtrip-hex_signed-1.v roundtrip_tb.v 1557s + ./iverilog-roundtrip-hex_signed-1 1557s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed-2 yosys-roundtrip-hex_signed-2.v roundtrip_tb.v 1557s + ./iverilog-roundtrip-hex_signed-1 1557s + diff iverilog-roundtrip-hex_signed.log iverilog-roundtrip-hex_signed-1.log 1557s + diff iverilog-roundtrip-hex_signed-1.log iverilog-roundtrip-hex_signed-2.log 1557s + test_roundtrip oct_unsigned -DBASE_HEX -DSIGN= 1557s + local subtest=oct_unsigned 1557s + shift 1557s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-oct_unsigned-1.v 1557s 1557s /----------------------------------------------------------------------------\ 1557s | | 1557s | yosys -- Yosys Open SYnthesis Suite | 1557s | | 1557s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1557s | | 1557s | Permission to use, copy, modify, and/or distribute this software for any | 1557s | purpose with or without fee is hereby granted, provided that the above | 1557s | copyright notice and this permission notice appear in all copies. | 1557s | | 1557s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1557s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1557s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1557s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1557s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1557s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1557s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1557s | | 1557s \----------------------------------------------------------------------------/ 1557s 1557s Yosys 0.33 (git sha1 2584903a060) 1557s 1557s 1557s -- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -- 1557s 1557s 1. Executing Verilog-2005 frontend: roundtrip.v 1557s Parsing Verilog input from `roundtrip.v' to AST representation. 1557s Generating RTLIL representation for module `\m'. 1557s Successfully finished Verilog frontend. 1557s 1557s 2. Executing PROC pass (convert processes to netlists). 1557s 1557s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1557s Cleaned up 0 empty switches. 1557s 1557s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1557s Removed a total of 0 dead cases. 1557s 1557s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1557s Removed 1 redundant assignment. 1557s Promoted 1 assignment to connection. 1557s 1557s 2.4. Executing PROC_INIT pass (extract init attributes). 1557s 1557s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1557s 1557s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1557s Converted 0 switches. 1557s 1557s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1557s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 1557s 1557s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1557s 1557s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1557s 1557s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1557s 1557s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1557s Removing empty process `m.$proc$roundtrip.v:3$1'. 1557s Cleaned up 0 empty switches. 1557s 1557s 2.12. Executing OPT_EXPR pass (perform const folding). 1557s Optimizing module m. 1557s Removed 0 unused cells and 1 unused wires. 1557s 1557s -- Writing to `yosys-roundtrip-oct_unsigned-1.v' using backend `verilog' -- 1557s 1557s 3. Executing Verilog backend. 1557s 1557s 3.1. Executing BMUXMAP pass. 1557s 1557s 3.2. Executing DEMUXMAP pass. 1557s Dumping module `\m'. 1557s 1557s End of script. Logfile hash: b768358a65, CPU: user 0.00s system 0.00s, MEM: 10.18 MB peak 1557s Yosys 0.33 (git sha1 2584903a060) 1557s Time spent: 27% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ... 1557s + ../../yosys -p 'read_verilog yosys-roundtrip-oct_unsigned-1.v; proc; clean' -o yosys-roundtrip-oct_unsigned-2.v 1557s 1557s /----------------------------------------------------------------------------\ 1557s | | 1557s | yosys -- Yosys Open SYnthesis Suite | 1557s | | 1557s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1557s | | 1557s | Permission to use, copy, modify, and/or distribute this software for any | 1557s | purpose with or without fee is hereby granted, provided that the above | 1557s | copyright notice and this permission notice appear in all copies. | 1557s | | 1557s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1557s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1557s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1557s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1557s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1557s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1557s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1557s | | 1557s \----------------------------------------------------------------------------/ 1557s 1557s Yosys 0.33 (git sha1 2584903a060) 1557s 1557s 1557s -- Running command `read_verilog yosys-roundtrip-oct_unsigned-1.v; proc; clean' -- 1557s 1557s 1. Executing Verilog-2005 frontend: yosys-roundtrip-oct_unsigned-1.v 1557s Parsing Verilog input from `yosys-roundtrip-oct_unsigned-1.v' to AST representation. 1557s Generating RTLIL representation for module `\m'. 1557s Successfully finished Verilog frontend. 1557s 1557s 2. Executing PROC pass (convert processes to netlists). 1557s 1557s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1557s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'. 1557s Cleaned up 1 empty switch. 1557s 1557s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1557s Removed a total of 0 dead cases. 1557s 1557s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1557s Removed 1 redundant assignment. 1557s Promoted 1 assignment to connection. 1557s 1557s 2.4. Executing PROC_INIT pass (extract init attributes). 1557s 1557s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1557s 1557s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1557s Converted 0 switches. 1557s 1557s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1557s Creating decoders for process `\m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'. 1557s 1557s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1557s 1557s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1557s 1557s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1557s 1557s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1557s Removing empty process `m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'. 1557s Cleaned up 0 empty switches. 1557s 1557s 2.12. Executing OPT_EXPR pass (perform const folding). 1557s Optimizing module m. 1557s Removed 0 unused cells and 1 unused wires. 1557s 1557s -- Writing to `yosys-roundtrip-oct_unsigned-2.v' using backend `verilog' -- 1557s 1557s 3. Executing Verilog backend. 1557s 1557s 3.1. Executing BMUXMAP pass. 1557s 1557s 3.2. Executing DEMUXMAP pass. 1557s Dumping module `\m'. 1557s 1557s End of script. Logfile hash: 762621cd95, CPU: user 0.00s system 0.00s, MEM: 10.23 MB peak 1557s Yosys 0.33 (git sha1 2584903a060) 1557s Time spent: 25% 1x clean (0 sec), 18% 1x opt_expr (0 sec), ... 1557s + diff yosys-roundtrip-oct_unsigned-1.v yosys-roundtrip-oct_unsigned-2.v 1557s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned roundtrip.v roundtrip_tb.v 1557s + ./iverilog-roundtrip-oct_unsigned 1557s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned-1 yosys-roundtrip-oct_unsigned-1.v roundtrip_tb.v 1557s + ./iverilog-roundtrip-oct_unsigned-1 1557s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned-2 yosys-roundtrip-oct_unsigned-2.v roundtrip_tb.v 1557s + ./iverilog-roundtrip-oct_unsigned-1 1557s + diff iverilog-roundtrip-oct_unsigned.log iverilog-roundtrip-oct_unsigned-1.log 1557s + diff iverilog-roundtrip-oct_unsigned-1.log iverilog-roundtrip-oct_unsigned-2.log 1557s + test_roundtrip oct_signed -DBASE_HEX -DSIGN=signed 1557s + local subtest=oct_signed 1557s + shift 1557s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-oct_signed-1.v 1557s 1557s /----------------------------------------------------------------------------\ 1557s | | 1557s | yosys -- Yosys Open SYnthesis Suite | 1557s | | 1557s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1557s | | 1557s | Permission to use, copy, modify, and/or distribute this software for any | 1557s | purpose with or without fee is hereby granted, provided that the above | 1557s | copyright notice and this permission notice appear in all copies. | 1557s | | 1557s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1557s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1557s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1557s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1557s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1557s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1557s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1557s | | 1557s \----------------------------------------------------------------------------/ 1557s 1557s Yosys 0.33 (git sha1 2584903a060) 1557s 1557s 1557s -- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -- 1557s 1557s 1. Executing Verilog-2005 frontend: roundtrip.v 1557s Parsing Verilog input from `roundtrip.v' to AST representation. 1557s Generating RTLIL representation for module `\m'. 1557s Successfully finished Verilog frontend. 1557s 1557s 2. Executing PROC pass (convert processes to netlists). 1557s 1557s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1557s Cleaned up 0 empty switches. 1557s 1557s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1557s Removed a total of 0 dead cases. 1557s 1557s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1557s Removed 1 redundant assignment. 1557s Promoted 1 assignment to connection. 1557s 1557s 2.4. Executing PROC_INIT pass (extract init attributes). 1557s 1557s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1557s 1557s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1557s Converted 0 switches. 1557s 1557s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1557s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 1557s 1557s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1557s 1557s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1557s 1557s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1557s 1557s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1557s Removing empty process `m.$proc$roundtrip.v:3$1'. 1557s Cleaned up 0 empty switches. 1557s 1557s 2.12. Executing OPT_EXPR pass (perform const folding). 1557s Optimizing module m. 1557s Removed 0 unused cells and 1 unused wires. 1557s 1557s -- Writing to `yosys-roundtrip-oct_signed-1.v' using backend `verilog' -- 1557s 1557s 3. Executing Verilog backend. 1557s 1557s 3.1. Executing BMUXMAP pass. 1557s 1557s 3.2. Executing DEMUXMAP pass. 1557s Dumping module `\m'. 1557s 1557s End of script. Logfile hash: 7ec82b15e3, CPU: user 0.01s system 0.00s, MEM: 10.21 MB peak 1557s Yosys 0.33 (git sha1 2584903a060) 1557s Time spent: 25% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... 1557s + ../../yosys -p 'read_verilog yosys-roundtrip-oct_signed-1.v; proc; clean' -o yosys-roundtrip-oct_signed-2.v 1557s 1557s /----------------------------------------------------------------------------\ 1557s | | 1557s | yosys -- Yosys Open SYnthesis Suite | 1557s | | 1557s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1557s | | 1557s | Permission to use, copy, modify, and/or distribute this software for any | 1557s | purpose with or without fee is hereby granted, provided that the above | 1557s | copyright notice and this permission notice appear in all copies. | 1557s | | 1557s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1557s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1557s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1557s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1557s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1557s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1557s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1557s | | 1557s \----------------------------------------------------------------------------/ 1557s 1557s Yosys 0.33 (git sha1 2584903a060) 1557s 1557s 1557s -- Running command `read_verilog yosys-roundtrip-oct_signed-1.v; proc; clean' -- 1557s 1557s 1. Executing Verilog-2005 frontend: yosys-roundtrip-oct_signed-1.v 1557s Parsing Verilog input from `yosys-roundtrip-oct_signed-1.v' to AST representation. 1557s Generating RTLIL representation for module `\m'. 1557s Successfully finished Verilog frontend. 1557s 1557s 2. Executing PROC pass (convert processes to netlists). 1557s 1557s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1557s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'. 1557s Cleaned up 1 empty switch. 1557s 1557s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1557s Removed a total of 0 dead cases. 1557s 1557s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1557s Removed 1 redundant assignment. 1557s Promoted 1 assignment to connection. 1557s 1557s 2.4. Executing PROC_INIT pass (extract init attributes). 1557s 1557s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1557s 1557s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1557s Converted 0 switches. 1557s 1557s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1557s Creating decoders for process `\m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'. 1557s 1557s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1557s 1557s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1557s 1557s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1557s 1557s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1557s Removing empty process `m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'. 1557s Cleaned up 0 empty switches. 1557s 1557s 2.12. Executing OPT_EXPR pass (perform const folding). 1557s Optimizing module m. 1557s Removed 0 unused cells and 1 unused wires. 1557s 1557s -- Writing to `yosys-roundtrip-oct_signed-2.v' using backend `verilog' -- 1557s 1557s 3. Executing Verilog backend. 1557s 1557s 3.1. Executing BMUXMAP pass. 1557s 1557s 3.2. Executing DEMUXMAP pass. 1557s Dumping module `\m'. 1557s 1557s End of script. Logfile hash: a747b9bd4f, CPU: user 0.01s system 0.00s, MEM: 10.41 MB peak 1557s Yosys 0.33 (git sha1 2584903a060) 1557s Time spent: 26% 1x clean (0 sec), 19% 1x opt_expr (0 sec), ... 1557s + diff yosys-roundtrip-oct_signed-1.v yosys-roundtrip-oct_signed-2.v 1557s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed roundtrip.v roundtrip_tb.v 1557s + ./iverilog-roundtrip-oct_signed 1557s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed-1 yosys-roundtrip-oct_signed-1.v roundtrip_tb.v 1557s + ./iverilog-roundtrip-oct_signed-1 1557s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed-2 yosys-roundtrip-oct_signed-2.v roundtrip_tb.v 1557s + ./iverilog-roundtrip-oct_signed-1 1557s 1557s /----------------------------------------------------------------------------\ 1557s | | 1557s | yosys -- Yosys Open SYnthesis Suite | 1557s | | 1557s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1557s | | 1557s | Permission to use, copy, modify, and/or distribute this software for any | 1557s | purpose with or without fee is hereby granted, provided that the above | 1557s | copyright notice and this permission notice appear in all copies. | 1557s | | 1557s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1557s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1557s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1557s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1557s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1557s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1557s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1557s | | 1557s \----------------------------------------------------------------------------/ 1557s 1557s Yosys 0.33 (git sha1 2584903a060) 1557s 1557s 1557s -- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -- 1557s 1557s 1. Executing Verilog-2005 frontend: roundtrip.v 1557s Parsing Verilog input from `roundtrip.v' to AST representation. 1557s Generating RTLIL representation for module `\m'. 1557s Successfully finished Verilog frontend. 1557s 1557s 2. Executing PROC pass (convert processes to netlists). 1557s 1557s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1557s Cleaned up 0 empty switches. 1557s 1557s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1557s Removed a total of 0 dead cases. 1557s 1557s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1557s Removed 1 redundant assignment. 1557s Promoted 1 assignment to connection. 1557s 1557s 2.4. Executing PROC_INIT pass (extract init attributes). 1557s 1557s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1557s 1557s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1557s Converted 0 switches. 1557s 1557s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1557s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 1557s 1557s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1557s 1557s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1557s + diff iverilog-roundtrip-oct_signed.log iverilog-roundtrip-oct_signed-1.log 1557s + diff iverilog-roundtrip-oct_signed-1.log iverilog-roundtrip-oct_signed-2.log 1557s + test_roundtrip bin_unsigned -DBASE_HEX -DSIGN= 1557s + local subtest=bin_unsigned 1557s + shift 1557s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-bin_unsigned-1.v 1557s 1557s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1557s 1557s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1557s Removing empty process `m.$proc$roundtrip.v:3$1'. 1557s Cleaned up 0 empty switches. 1557s 1557s 2.12. Executing OPT_EXPR pass (perform const folding). 1557s Optimizing module m. 1557s Removed 0 unused cells and 1 unused wires. 1557s 1557s -- Writing to `yosys-roundtrip-bin_unsigned-1.v' using backend `verilog' -- 1557s 1557s 3. Executing Verilog backend. 1557s 1557s 3.1. Executing BMUXMAP pass. 1557s 1557s 3.2. Executing DEMUXMAP pass. 1557s Dumping module `\m'. 1557s 1557s End of script. Logfile hash: 270b564880, CPU: user 0.00s system 0.00s, MEM: 10.32 MB peak 1557s Yosys 0.33 (git sha1 2584903a060) 1557s Time spent: 28% 1x clean (0 sec), 18% 1x opt_expr (0 sec), ... 1557s 1557s /----------------------------------------------------------------------------\ 1557s | | 1557s | yosys -- Yosys Open SYnthesis Suite | 1557s | | 1557s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1557s | | 1557s | Permission to use, copy, modify, and/or distribute this software for any | 1557s | purpose with or without fee is hereby granted, provided that the above | 1557s | copyright notice and this permission notice appear in all copies. | 1557s | | 1557s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1557s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1557s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1557s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1557s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1557s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1557s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1557s | | 1557s \----------------------------------------------------------------------------/ 1557s 1557s Yosys 0.33 (git sha1 2584903a060) 1557s 1557s 1557s -- Running command `read_verilog yosys-roundtrip-bin_unsigned-1.v; proc; clean' -- 1557s 1557s 1. Executing Verilog-2005 frontend: yosys-roundtrip-bin_unsigned-1.v 1557s Parsing Verilog input from `yosys-roundtrip-bin_unsigned-1.v' to AST representation. 1557s Generating RTLIL representation for module `\m'. 1557s Successfully finished Verilog frontend. 1557s 1557s 2. Executing PROC pass (convert processes to netlists). 1557s 1557s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1557s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'. 1557s Cleaned up 1 empty switch. 1557s 1557s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1557s Removed a total of 0 dead cases. 1557s 1557s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1557s Removed 1 redundant assignment. 1557s Promoted 1 assignment to connection. 1557s 1557s 2.4. Executing PROC_INIT pass (extract init attributes). 1557s 1557s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1557s 1557s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1557s Converted 0 switches. 1557s 1557s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1557s Creating decoders for process `\m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'. 1557s 1557s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1557s 1557s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1557s 1557s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1557s 1557s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1557s Removing empty process `m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'. 1557s Cleaned up 0 empty switches. 1557s 1557s 2.12. Executing OPT_EXPR pass (perform const folding). 1557s Optimizing module m. 1557s Removed 0 unused cells and 1 unused wires. 1557s 1557s -- Writing to `yosys-roundtrip-bin_unsigned-2.v' using backend `verilog' -- 1557s 1557s 3. Executing Verilog backend. 1557s 1557s 3.1. Executing BMUXMAP pass. 1557s 1557s 3.2. Executing DEMUXMAP pass. 1557s Dumping module `\m'. 1557s 1557s End of script. Logfile hash: dc9f56cb10, CPU: user 0.00s system 0.00s, MEM: 10.28 MB peak 1557s Yosys 0.33 (git sha1 2584903a060) 1557s Time spent: 26% 1x clean (0 sec), 19% 1x opt_expr (0 sec), ... 1557s + ../../yosys -p 'read_verilog yosys-roundtrip-bin_unsigned-1.v; proc; clean' -o yosys-roundtrip-bin_unsigned-2.v 1557s + diff yosys-roundtrip-bin_unsigned-1.v yosys-roundtrip-bin_unsigned-2.v 1557s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned roundtrip.v roundtrip_tb.v 1557s + ./iverilog-roundtrip-bin_unsigned 1557s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned-1 yosys-roundtrip-bin_unsigned-1.v roundtrip_tb.v 1557s + ./iverilog-roundtrip-bin_unsigned-1 1557s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned-2 yosys-roundtrip-bin_unsigned-2.v roundtrip_tb.v 1557s + ./iverilog-roundtrip-bin_unsigned-1 1557s + diff iverilog-roundtrip-bin_unsigned.log iverilog-roundtrip-bin_unsigned-1.log 1557s + diff iverilog-roundtrip-bin_unsigned-1.log iverilog-roundtrip-bin_unsigned-2.log 1557s + test_roundtrip bin_signed -DBASE_HEX -DSIGN=signed 1557s + local subtest=bin_signed 1557s + shift 1557s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-bin_signed-1.v 1557s 1557s /----------------------------------------------------------------------------\ 1557s | | 1557s | yosys -- Yosys Open SYnthesis Suite | 1557s | | 1557s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1557s | | 1557s | Permission to use, copy, modify, and/or distribute this software for any | 1557s | purpose with or without fee is hereby granted, provided that the above | 1557s | copyright notice and this permission notice appear in all copies. | 1557s | | 1557s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1557s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1557s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1557s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1557s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1557s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1557s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1557s | | 1557s \----------------------------------------------------------------------------/ 1557s 1557s Yosys 0.33 (git sha1 2584903a060) 1557s 1557s 1557s -- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -- 1557s 1557s 1. Executing Verilog-2005 frontend: roundtrip.v 1557s Parsing Verilog input from `roundtrip.v' to AST representation. 1557s Generating RTLIL representation for module `\m'. 1557s Successfully finished Verilog frontend. 1557s 1557s 2. Executing PROC pass (convert processes to netlists). 1557s 1557s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1557s Cleaned up 0 empty switches. 1557s 1557s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1557s Removed a total of 0 dead cases. 1557s 1557s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1557s Removed 1 redundant assignment. 1557s Promoted 1 assignment to connection. 1557s 1557s 2.4. Executing PROC_INIT pass (extract init attributes). 1557s 1557s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1557s 1557s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1557s Converted 0 switches. 1557s 1557s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1557s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 1557s 1557s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1557s 1557s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1557s 1557s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1557s 1557s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1557s Removing empty process `m.$proc$roundtrip.v:3$1'. 1557s Cleaned up 0 empty switches. 1557s 1557s 2.12. Executing OPT_EXPR pass (perform const folding). 1557s Optimizing module m. 1557s Removed 0 unused cells and 1 unused wires. 1557s 1557s -- Writing to `yosys-roundtrip-bin_signed-1.v' using backend `verilog' -- 1557s 1557s 3. Executing Verilog backend. 1557s 1557s 3.1. Executing BMUXMAP pass. 1557s 1557s 3.2. Executing DEMUXMAP pass. 1557s Dumping module `\m'. 1557s 1557s End of script. Logfile hash: 7709253822, CPU: user 0.00s system 0.00s, MEM: 10.24 MB peak 1557s Yosys 0.33 (git sha1 2584903a060) 1557s Time spent: 26% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... 1557s + ../../yosys -p 'read_verilog yosys-roundtrip-bin_signed-1.v; proc; clean' -o yosys-roundtrip-bin_signed-2.v 1557s 1557s /----------------------------------------------------------------------------\ 1557s | | 1557s | yosys -- Yosys Open SYnthesis Suite | 1557s | | 1557s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1557s | | 1557s | Permission to use, copy, modify, and/or distribute this software for any | 1557s | purpose with or without fee is hereby granted, provided that the above | 1557s | copyright notice and this permission notice appear in all copies. | 1557s | | 1557s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1557s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1557s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1557s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1557s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1557s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1557s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1557s | | 1557s \----------------------------------------------------------------------------/ 1557s 1557s Yosys 0.33 (git sha1 2584903a060) 1557s 1557s 1557s -- Running command `read_verilog yosys-roundtrip-bin_signed-1.v; proc; clean' -- 1557s 1557s 1. Executing Verilog-2005 frontend: yosys-roundtrip-bin_signed-1.v 1557s Parsing Verilog input from `yosys-roundtrip-bin_signed-1.v' to AST representation. 1557s Generating RTLIL representation for module `\m'. 1557s Successfully finished Verilog frontend. 1557s 1557s 2. Executing PROC pass (convert processes to netlists). 1557s 1557s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1557s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'. 1557s Cleaned up 1 empty switch. 1557s 1557s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1557s Removed a total of 0 dead cases. 1557s 1557s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1557s Removed 1 redundant assignment. 1557s Promoted 1 assignment to connection. 1557s 1557s 2.4. Executing PROC_INIT pass (extract init attributes). 1557s 1557s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1557s 1557s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1557s Converted 0 switches. 1557s 1557s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1557s Creating decoders for process `\m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'. 1557s 1557s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1557s 1557s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1557s 1557s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1557s 1557s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1557s Removing empty process `m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'. 1557s Cleaned up 0 empty switches. 1557s 1557s 2.12. Executing OPT_EXPR pass (perform const folding). 1557s Optimizing module m. 1557s Removed 0 unused cells and 1 unused wires. 1557s 1557s -- Writing to `yosys-roundtrip-bin_signed-2.v' using backend `verilog' -- 1557s 1557s 3. Executing Verilog backend. 1557s 1557s 3.1. Executing BMUXMAP pass. 1557s 1557s 3.2. Executing DEMUXMAP pass. 1557s Dumping module `\m'. 1557s 1557s End of script. Logfile hash: 7e2d8271c4, CPU: user 0.00s system 0.00s, MEM: 10.34 MB peak 1557s Yosys 0.33 (git sha1 2584903a060) 1557s Time spent: 25% 1x clean (0 sec), 19% 1x opt_expr (0 sec), ... 1557s + diff yosys-roundtrip-bin_signed-1.v yosys-roundtrip-bin_signed-2.v 1557s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed roundtrip.v roundtrip_tb.v 1557s + ./iverilog-roundtrip-bin_signed 1557s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed-1 yosys-roundtrip-bin_signed-1.v roundtrip_tb.v 1557s + ./iverilog-roundtrip-bin_signed-1 1557s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed-2 yosys-roundtrip-bin_signed-2.v roundtrip_tb.v 1557s + ./iverilog-roundtrip-bin_signed-1 1557s + diff iverilog-roundtrip-bin_signed.log iverilog-roundtrip-bin_signed-1.log 1557s + diff iverilog-roundtrip-bin_signed-1.log iverilog-roundtrip-bin_signed-2.log 1557s + test_cxxrtl always_full 1557s + local subtest=always_full 1557s + shift 1557s + ../../yosys -p 'read_verilog always_full.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_full.cc' 1557s 1557s /----------------------------------------------------------------------------\ 1557s | | 1557s | yosys -- Yosys Open SYnthesis Suite | 1557s | | 1557s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1557s | | 1557s | Permission to use, copy, modify, and/or distribute this software for any | 1557s | purpose with or without fee is hereby granted, provided that the above | 1557s | copyright notice and this permission notice appear in all copies. | 1557s | | 1557s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1557s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1557s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1557s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1557s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1557s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1557s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1557s | | 1557s \----------------------------------------------------------------------------/ 1557s 1557s Yosys 0.33 (git sha1 2584903a060) 1557s 1557s 1557s -- Running command `read_verilog always_full.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_full.cc' -- 1557s 1557s 1. Executing Verilog-2005 frontend: always_full.v 1557s Parsing Verilog input from `always_full.v' to AST representation. 1557s Generating RTLIL representation for module `\always_full'. 1557s Successfully finished Verilog frontend. 1557s 1557s 2. Executing PROC pass (convert processes to netlists). 1557s 1557s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1557s Cleaned up 0 empty switches. 1557s 1557s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1557s Removed a total of 0 dead cases. 1557s 1557s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1557s Removed 207 redundant assignments. 1557s Promoted 207 assignments to connections. 1557s 1557s 2.4. Executing PROC_INIT pass (extract init attributes). 1557s 1557s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1557s 1557s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1557s Converted 0 switches. 1557s 1557s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1557s Creating decoders for process `\always_full.$proc$always_full.v:3$1'. 1557s 1557s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1557s 1557s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1557s 1557s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1557s 1557s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1557s Removing empty process `always_full.$proc$always_full.v:3$1'. 1557s Cleaned up 0 empty switches. 1557s 1557s 2.12. Executing OPT_EXPR pass (perform const folding). 1557s Optimizing module always_full. 1557s Removed 0 unused cells and 207 unused wires. 1557s 1557s 3. Executing CXXRTL backend. 1557s 1557s 3.1. Executing HIERARCHY pass (managing design hierarchy). 1557s 1557s 3.1.1. Finding top of design hierarchy.. 1557s root of 0 design levels: always_full 1557s Automatically selected always_full as design top module. 1557s 1557s 3.1.2. Analyzing design hierarchy.. 1557s Top module: \always_full 1557s 1557s 3.1.3. Analyzing design hierarchy.. 1557s Top module: \always_full 1557s Removed 0 unused modules. 1557s 1557s 3.2. Executing FLATTEN pass (flatten design). 1557s 1557s 3.3. Executing PROC pass (convert processes to netlists). 1557s 1557s 3.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1557s Cleaned up 0 empty switches. 1557s 1557s 3.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1557s Removed a total of 0 dead cases. 1557s 1557s 3.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1557s Removed 0 redundant assignments. 1557s Promoted 0 assignments to connections. 1557s 1557s 3.3.4. Executing PROC_INIT pass (extract init attributes). 1557s 1557s 3.3.5. Executing PROC_ARST pass (detect async resets in processes). 1557s 1557s 3.3.6. Executing PROC_ROM pass (convert switches to ROMs). 1557s Converted 0 switches. 1557s 1557s 3.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1557s 1557s 3.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1557s 1557s 3.3.9. Executing PROC_DFF pass (convert process syncs to FFs). 1557s 1557s 3.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1557s 1557s 3.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1557s Cleaned up 0 empty switches. 1557s 1557s 3.3.12. Executing OPT_EXPR pass (perform const folding). 1557s Optimizing module always_full. 1557s 1557s 1557s 1557s End of script. Logfile hash: 6abd135c0a, CPU: user 0.02s system 0.00s, MEM: 11.53 MB peak 1557s Yosys 0.33 (git sha1 2584903a060) 1557s Time spent: 29% 2x read_verilog (0 sec), 21% 2x opt_expr (0 sec), ... 1557s + gcc -std=c++11 -o yosys-always_full -I../.. always_full_tb.cc -lstdc++ 1558s + ./yosys-always_full 1558s + iverilog -o iverilog-always_full always_full.v always_full_tb.v 1558s + ./iverilog-always_full 1558s + grep -v '\$finish called' 1558s + diff iverilog-always_full.log yosys-always_full.log 1558s + test_cxxrtl always_comb 1558s + local subtest=always_comb 1558s + shift 1558s + ../../yosys -p 'read_verilog always_comb.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_comb.cc' 1558s 1558s /----------------------------------------------------------------------------\ 1558s | | 1558s | yosys -- Yosys Open SYnthesis Suite | 1558s | | 1558s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1558s | | 1558s | Permission to use, copy, modify, and/or distribute this software for any | 1558s | purpose with or without fee is hereby granted, provided that the above | 1558s | copyright notice and this permission notice appear in all copies. | 1558s | | 1558s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1558s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1558s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1558s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1558s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1558s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1558s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1558s | | 1558s \----------------------------------------------------------------------------/ 1558s 1558s Yosys 0.33 (git sha1 2584903a060) 1558s 1558s 1558s -- Running command `read_verilog always_comb.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_comb.cc' -- 1558s 1558s 1. Executing Verilog-2005 frontend: always_comb.v 1558s Parsing Verilog input from `always_comb.v' to AST representation. 1558s Generating RTLIL representation for module `\top'. 1558s Generating RTLIL representation for module `\sub'. 1558s Successfully finished Verilog frontend. 1558s 1558s 2. Executing PROC pass (convert processes to netlists). 1558s 1558s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1558s Cleaned up 0 empty switches. 1558s 1558s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1558s Removed a total of 0 dead cases. 1558s 1558s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1558s Removed 0 redundant assignments. 1558s Promoted 4 assignments to connections. 1558s 1558s 2.4. Executing PROC_INIT pass (extract init attributes). 1558s Found init rule in `\top.$proc$always_comb.v:3$13'. 1558s Set init value: \b = 1'0 1558s Found init rule in `\top.$proc$always_comb.v:2$12'. 1558s Set init value: \a = 1'0 1558s 1558s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1558s 1558s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1558s Converted 0 switches. 1558s 1558s 1558s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1558s Creating decoders for process `\sub.$proc$always_comb.v:23$15'. 1558s 1/1: $display$always_comb.v:23$19_EN 1558s Creating decoders for process `\top.$proc$always_comb.v:3$13'. 1558s Creating decoders for process `\top.$proc$always_comb.v:2$12'. 1558s Creating decoders for process `\top.$proc$always_comb.v:8$1'. 1558s 1558s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1558s 1558s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1558s Creating register for signal `\top.\a' using process `\top.$proc$always_comb.v:8$1'. 1558s created $dff cell `$procdff$22' with positive edge clock. 1558s Creating register for signal `\top.\b' using process `\top.$proc$always_comb.v:8$1'. 1558s created $dff cell `$procdff$23' with positive edge clock. 1558s 1558s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1558s 1558s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1558s Found and cleaned up 1 empty switch in `\sub.$proc$always_comb.v:23$15'. 1558s Removing empty process `sub.$proc$always_comb.v:23$15'. 1558s Removing empty process `top.$proc$always_comb.v:3$13'. 1558s Removing empty process `top.$proc$always_comb.v:2$12'. 1558s Removing empty process `top.$proc$always_comb.v:8$1'. 1558s Cleaned up 1 empty switch. 1558s 1558s 2.12. Executing OPT_EXPR pass (perform const folding). 1558s Optimizing module sub. 1558s Optimizing module top. 1558s Removed 0 unused cells and 7 unused wires. 1558s 1558s 3. Executing CXXRTL backend. 1558s 1558s 3.1. Executing HIERARCHY pass (managing design hierarchy). 1558s 1558s 3.1.1. Finding top of design hierarchy.. 1558s root of 0 design levels: sub 1558s root of 1 design levels: top 1558s Automatically selected top as design top module. 1558s 1558s 3.1.2. Analyzing design hierarchy.. 1558s Top module: \top 1558s Used module: \sub 1558s 1558s 3.1.3. Analyzing design hierarchy.. 1558s Top module: \top 1558s Used module: \sub 1558s Removed 0 unused modules. 1558s 1558s 3.2. Executing FLATTEN pass (flatten design). 1558s Deleting now unused module sub. 1558s 1558s 1558s 3.3. Executing PROC pass (convert processes to netlists). 1558s 1558s 3.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1558s Cleaned up 0 empty switches. 1558s 1558s 3.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1558s Removed a total of 0 dead cases. 1558s 1558s 3.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1558s Removed 0 redundant assignments. 1558s Promoted 0 assignments to connections. 1558s 1558s 3.3.4. Executing PROC_INIT pass (extract init attributes). 1558s 1558s 3.3.5. Executing PROC_ARST pass (detect async resets in processes). 1558s 1558s 3.3.6. Executing PROC_ROM pass (convert switches to ROMs). 1558s Converted 0 switches. 1558s 1558s 3.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1558s 1558s 3.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1558s 1558s 3.3.9. Executing PROC_DFF pass (convert process syncs to FFs). 1558s 1558s 3.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1558s 1558s 3.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1558s Cleaned up 0 empty switches. 1558s 1558s 3.3.12. Executing OPT_EXPR pass (perform const folding). 1558s Optimizing module top. 1558s 1558s 1558s 1558s End of script. Logfile hash: 03fe26efda, CPU: user 0.00s system 0.01s, MEM: 10.79 MB peak 1558s Yosys 0.33 (git sha1 2584903a060) 1558s Time spent: 28% 2x opt_expr (0 sec), 18% 1x clean (0 sec), ... 1558s + gcc -std=c++11 -o yosys-always_comb -I../.. always_comb_tb.cc -lstdc++ 1559s + ./yosys-always_comb 1559s + iverilog -o iverilog-always_comb always_comb.v always_comb_tb.v 1559s + ./iverilog-always_comb 1559s + grep -v '\$finish called' 1559s + diff iverilog-always_comb.log yosys-always_comb.log 1559s 1559s /----------------------------------------------------------------------------\ 1559s | | 1559s | yosys -- Yosys Open SYnthesis Suite | 1559s | | 1559s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1559s | | 1559s | Permission to use, copy, modify, and/or distribute this software for any | 1559s | purpose with or without fee is hereby granted, provided that the above | 1559s | copyright notice and this permission notice appear in all copies. | 1559s | | 1559s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1559s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1559s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1559s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1559s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1559s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1559s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1559s | | 1559s \----------------------------------------------------------------------------/ 1559s 1559s Yosys 0.33 (git sha1 2584903a060) 1559s 1559s 1559s -- Running command `read_verilog always_full.v; prep; clean' -- 1559s 1559s 1. Executing Verilog-2005 frontend: always_full.v 1559s + ../../yosys -p 'read_verilog always_full.v; prep; clean' -o yosys-always_full-1.v 1559s Parsing Verilog input from `always_full.v' to AST representation. 1559s Generating RTLIL representation for module `\always_full'. 1559s Successfully finished Verilog frontend. 1559s 1559s 2. Executing PREP pass. 1559s 1559s 2.1. Executing HIERARCHY pass (managing design hierarchy). 1559s 1559s 2.2. Executing PROC pass (convert processes to netlists). 1559s 1559s 2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1559s Cleaned up 0 empty switches. 1559s 1559s 2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1559s Removed a total of 0 dead cases. 1559s 1559s 2.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1559s Removed 207 redundant assignments. 1559s Promoted 207 assignments to connections. 1559s 1559s 2.2.4. Executing PROC_INIT pass (extract init attributes). 1559s 1559s 2.2.5. Executing PROC_ARST pass (detect async resets in processes). 1559s 1559s 2.2.6. Executing PROC_ROM pass (convert switches to ROMs). 1559s Converted 0 switches. 1559s 1559s 2.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1559s Creating decoders for process `\always_full.$proc$always_full.v:3$1'. 1559s 1559s 2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1559s 1559s 2.2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1559s 1559s 2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1559s 1559s 2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1559s Removing empty process `always_full.$proc$always_full.v:3$1'. 1559s Cleaned up 0 empty switches. 1559s 1559s 2.2.12. Executing OPT_EXPR pass (perform const folding). 1559s Optimizing module always_full. 1559s 1559s 2.3. Executing OPT_EXPR pass (perform const folding). 1559s Optimizing module always_full. 1559s 1559s 2.4. Executing OPT_CLEAN pass (remove unused cells and wires). 1559s Finding unused cells or wires in module \always_full.. 1559s Removed 0 unused cells and 207 unused wires. 1559s 1559s 1559s 2.5. Executing CHECK pass (checking for obvious problems). 1559s Checking module always_full... 1559s Found and reported 0 problems. 1559s 1559s 2.6. Executing OPT pass (performing simple optimizations). 1559s 1559s 2.6.1. Executing OPT_EXPR pass (perform const folding). 1559s Optimizing module always_full. 1559s 1559s 2.6.2. Executing OPT_MERGE pass (detect identical cells). 1559s Finding identical cells in module `\always_full'. 1559s Removed a total of 0 cells. 1559s 1559s 2.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 1559s Running muxtree optimizer on module \always_full.. 1559s Creating internal representation of mux trees. 1559s No muxes found in this module. 1559s Removed 0 multiplexer ports. 1559s 1559s 2.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 1559s Optimizing cells in module \always_full. 1559s Performed a total of 0 changes. 1559s 1559s 2.6.5. Executing OPT_MERGE pass (detect identical cells). 1559s Finding identical cells in module `\always_full'. 1559s Removed a total of 0 cells. 1559s 1559s 2.6.6. Executing OPT_CLEAN pass (remove unused cells and wires). 1559s Finding unused cells or wires in module \always_full.. 1559s 1559s 2.6.7. Executing OPT_EXPR pass (perform const folding). 1559s Optimizing module always_full. 1559s 1559s 2.6.8. Finished OPT passes. (There is nothing left to do.) 1559s 1559s 2.7. Executing WREDUCE pass (reducing word size of cells). 1559s 1559s 2.8. Executing OPT_CLEAN pass (remove unused cells and wires). 1559s Finding unused cells or wires in module \always_full.. 1559s 1559s 2.9. Executing MEMORY_COLLECT pass (generating $mem cells). 1559s 1559s 2.10. Executing OPT pass (performing simple optimizations). 1559s 1559s 2.10.1. Executing OPT_EXPR pass (perform const folding). 1559s Optimizing module always_full. 1559s 1559s 2.10.2. Executing OPT_MERGE pass (detect identical cells). 1559s Finding identical cells in module `\always_full'. 1559s Removed a total of 0 cells. 1559s 1559s 2.10.3. Executing OPT_CLEAN pass (remove unused cells and wires). 1559s Finding unused cells or wires in module \always_full.. 1559s 1559s 2.10.4. Finished fast OPT passes. 1559s 1559s 2.11. Printing statistics. 1559s 1559s === always_full === 1559s 1559s Number of wires: 1 1559s Number of wire bits: 1 1559s Number of public wires: 1 1559s Number of public wire bits: 1 1559s Number of memories: 0 1559s Number of memory bits: 0 1559s Number of processes: 0 1559s Number of cells: 207 1559s $print 207 1559s 1559s 2.12. Executing CHECK pass (checking for obvious problems). 1559s Checking module always_full... 1559s Found and reported 0 problems. 1559s 1559s -- Writing to `yosys-always_full-1.v' using backend `verilog' -- 1559s 1559s 3. Executing Verilog backend. 1559s 1559s 3.1. Executing BMUXMAP pass. 1559s 1559s 3.2. Executing DEMUXMAP pass. 1559s Dumping module `\always_full'. 1559s 1559s End of script. Logfile hash: cfd5b76053, CPU: user 0.05s system 0.00s, MEM: 11.61 MB peak 1559s Yosys 0.33 (git sha1 2584903a060) 1559s Time spent: 20% 5x opt_expr (0 sec), 19% 4x opt_clean (0 sec), ... 1559s + iverilog -o iverilog-always_full-1 yosys-always_full-1.v always_full_tb.v 1559s + ./iverilog-always_full-1 1559s + grep -v '\$finish called' 1559s + diff iverilog-always_full.log iverilog-always_full-1.log 1559s + ../../yosys -p 'read_verilog display_lm.v' 1559s + ../../yosys -p 'read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc' 1559s 1559s /----------------------------------------------------------------------------\ 1559s | | 1559s | yosys -- Yosys Open SYnthesis Suite | 1559s | | 1559s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1559s | | 1559s | Permission to use, copy, modify, and/or distribute this software for any | 1559s | purpose with or without fee is hereby granted, provided that the above | 1559s | copyright notice and this permission notice appear in all copies. | 1559s | | 1559s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1559s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1559s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1559s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1559s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1559s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1559s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1559s | | 1559s \----------------------------------------------------------------------------/ 1559s 1559s Yosys 0.33 (git sha1 2584903a060) 1559s 1559s 1559s -- Running command `read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc' -- 1559s 1559s 1. Executing Verilog-2005 frontend: display_lm.v 1559s Parsing Verilog input from `display_lm.v' to AST representation. 1559s Generating RTLIL representation for module `\top'. 1559s Generating RTLIL representation for module `\mid'. 1559s Generating RTLIL representation for module `\bot'. 1559s %l: \bot 1559s %m: \bot 1559s Successfully finished Verilog frontend. 1559s 1559s 2. Executing CXXRTL backend. 1559s 1559s 2.1. Executing HIERARCHY pass (managing design hierarchy). 1559s 1559s 2.1.1. Finding top of design hierarchy.. 1559s root of 0 design levels: bot 1559s root of 1 design levels: mid 1559s root of 2 design levels: top 1559s Automatically selected top as design top module. 1559s 1559s 2.1.2. Analyzing design hierarchy.. 1559s Top module: \top 1559s Used module: \mid 1559s Used module: \bot 1559s 1559s 2.1.3. Analyzing design hierarchy.. 1559s Top module: \top 1559s Used module: \mid 1559s Used module: \bot 1559s Removed 0 unused modules. 1559s 1559s 2.2. Executing FLATTEN pass (flatten design). 1559s Deleting now unused module bot. 1559s Deleting now unused module mid. 1559s 1559s 1559s 2.3. Executing PROC pass (convert processes to netlists). 1559s 1559s 2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1559s Removing empty process `top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:0$3'. 1559s Cleaned up 0 empty switches. 1559s 1559s 2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1559s Removed a total of 0 dead cases. 1559s 1559s 2.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1559s Removed 1 redundant assignment. 1559s Promoted 1 assignment to connection. 1559s 1559s 2.3.4. Executing PROC_INIT pass (extract init attributes). 1559s 1559s 2.3.5. Executing PROC_ARST pass (detect async resets in processes). 1559s 1559s 2.3.6. Executing PROC_ROM pass (convert switches to ROMs). 1559s Converted 0 switches. 1559s 1559s 2.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1559s Creating decoders for process `\top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:11$1'. 1559s 1559s 2.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1559s 1559s 2.3.9. Executing PROC_DFF pass (convert process syncs to FFs). 1559s 1559s 2.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1559s 1559s 2.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1559s Removing empty process `top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:11$1'. 1559s Cleaned up 0 empty switches. 1559s 1559s 2.3.12. Executing OPT_EXPR pass (perform const folding). 1559s Optimizing module top. 1559s 1559s 1559s 1559s End of script. Logfile hash: 1b689717a7, CPU: user 0.00s system 0.00s, MEM: 9.96 MB peak 1559s Yosys 0.33 (git sha1 2584903a060) 1559s Time spent: 32% 1x opt_expr (0 sec), 16% 2x read_verilog (0 sec), ... 1559s + gcc -std=c++11 -o yosys-display_lm_cc -I../.. display_lm_tb.cc -lstdc++ 1559s + ./yosys-display_lm_cc 1559s + for log in yosys-display_lm.log yosys-display_lm_cc.log 1559s + grep '^%l: \\bot$' yosys-display_lm.log 1559s %l: \bot 1559s + grep '^%m: \\bot$' yosys-display_lm.log 1559s %m: \bot 1559s + for log in yosys-display_lm.log yosys-display_lm_cc.log 1559s + grep '^%l: \\bot$' yosys-display_lm_cc.log 1559s %l: \bot 1559s + grep '^%m: \\bot$' yosys-display_lm_cc.log 1559s %m: \bot 1559s 1559s Passed "make test". 1559s 1560s autopkgtest [22:44:06]: test yosys-testsuite: -----------------------] 1560s yosys-testsuite PASS 1560s autopkgtest [22:44:06]: test yosys-testsuite: - - - - - - - - - - results - - - - - - - - - - 1561s autopkgtest [22:44:07]: test ice: preparing testbed 1629s autopkgtest [22:45:15]: testbed dpkg architecture: amd64 1629s autopkgtest [22:45:15]: testbed apt version: 3.0.0 1629s autopkgtest [22:45:15]: @@@@@@@@@@@@@@@@@@@@ test bed setup 1630s autopkgtest [22:45:16]: testbed release detected to be: questing 1630s autopkgtest [22:45:16]: updating testbed package index (apt update) 1631s Get:1 http://ftpmaster.internal/ubuntu questing-proposed InRelease [110 kB] 1631s Hit:2 http://ftpmaster.internal/ubuntu questing InRelease 1631s Hit:3 http://ftpmaster.internal/ubuntu questing-updates InRelease 1631s Hit:4 http://ftpmaster.internal/ubuntu questing-security InRelease 1631s Get:5 http://ftpmaster.internal/ubuntu questing-proposed/multiverse Sources [30.0 kB] 1631s Get:6 http://ftpmaster.internal/ubuntu questing-proposed/main Sources [86.1 kB] 1631s Get:7 http://ftpmaster.internal/ubuntu questing-proposed/universe Sources [818 kB] 1631s Get:8 http://ftpmaster.internal/ubuntu questing-proposed/main i386 Packages [86.1 kB] 1631s Get:9 http://ftpmaster.internal/ubuntu questing-proposed/main amd64 Packages [126 kB] 1631s Get:10 http://ftpmaster.internal/ubuntu questing-proposed/universe i386 Packages [333 kB] 1631s Get:11 http://ftpmaster.internal/ubuntu questing-proposed/universe amd64 Packages [908 kB] 1631s Get:12 http://ftpmaster.internal/ubuntu questing-proposed/multiverse i386 Packages [11.3 kB] 1631s Get:13 http://ftpmaster.internal/ubuntu questing-proposed/multiverse amd64 Packages [20.3 kB] 1632s Fetched 2529 kB in 1s (2669 kB/s) 1632s Reading package lists... 1633s autopkgtest [22:45:19]: upgrading testbed (apt dist-upgrade and autopurge) 1633s Reading package lists... 1634s Building dependency tree... 1634s Reading state information... 1634s Calculating upgrade...Starting pkgProblemResolver with broken count: 0 1634s Starting 2 pkgProblemResolver with broken count: 0 1634s Done 1635s Entering ResolveByKeep 1635s 1635s Calculating upgrade... 1635s The following package was automatically installed and is no longer required: 1635s libsigsegv2 1635s Use 'sudo apt autoremove' to remove it. 1635s The following packages will be upgraded: 1635s dhcpcd-base dirmngr gawk gir1.2-glib-2.0 gnupg gnupg-l10n gnupg-utils gpg 1635s gpg-agent gpg-wks-client gpgconf gpgsm gpgv groff-base keyboxd 1635s libglib2.0-0t64 libglib2.0-data libgpg-error-l10n libgpg-error0 libnuma1 1635s libselinux1 libx11-6 libx11-data libxml2 netbase numactl openssh-client 1635s openssh-server openssh-sftp-server python3-packaging python3-wadllib 1636s 31 upgraded, 0 newly installed, 0 to remove and 0 not upgraded. 1636s Need to get 9531 kB of archives. 1636s After this operation, 880 kB disk space will be freed. 1636s Get:1 http://ftpmaster.internal/ubuntu questing-proposed/main amd64 gawk amd64 1:5.3.2-1 [522 kB] 1636s Get:2 http://ftpmaster.internal/ubuntu questing/main amd64 libselinux1 amd64 3.8.1-1 [89.8 kB] 1636s Get:3 http://ftpmaster.internal/ubuntu questing/main amd64 openssh-sftp-server amd64 1:9.9p1-3ubuntu3.1 [41.2 kB] 1636s Get:4 http://ftpmaster.internal/ubuntu questing/main amd64 openssh-server amd64 1:9.9p1-3ubuntu3.1 [625 kB] 1636s Get:5 http://ftpmaster.internal/ubuntu questing/main amd64 openssh-client amd64 1:9.9p1-3ubuntu3.1 [1080 kB] 1636s Get:6 http://ftpmaster.internal/ubuntu questing/main amd64 libgpg-error-l10n all 1.51-4 [8880 B] 1636s Get:7 http://ftpmaster.internal/ubuntu questing/main amd64 libgpg-error0 amd64 1.51-4 [76.9 kB] 1636s Get:8 http://ftpmaster.internal/ubuntu questing/main amd64 gpg-wks-client amd64 2.4.4-2ubuntu24 [71.6 kB] 1636s Get:9 http://ftpmaster.internal/ubuntu questing/main amd64 dirmngr amd64 2.4.4-2ubuntu24 [327 kB] 1636s Get:10 http://ftpmaster.internal/ubuntu questing/main amd64 gpgsm amd64 2.4.4-2ubuntu24 [236 kB] 1636s Get:11 http://ftpmaster.internal/ubuntu questing/main amd64 gnupg-utils amd64 2.4.4-2ubuntu24 [110 kB] 1636s Get:12 http://ftpmaster.internal/ubuntu questing/main amd64 gpg-agent amd64 2.4.4-2ubuntu24 [231 kB] 1636s Get:13 http://ftpmaster.internal/ubuntu questing/main amd64 gpg amd64 2.4.4-2ubuntu24 [572 kB] 1636s Get:14 http://ftpmaster.internal/ubuntu questing/main amd64 gpgconf amd64 2.4.4-2ubuntu24 [104 kB] 1636s Get:15 http://ftpmaster.internal/ubuntu questing/main amd64 gnupg all 2.4.4-2ubuntu24 [359 kB] 1636s Get:16 http://ftpmaster.internal/ubuntu questing/main amd64 keyboxd amd64 2.4.4-2ubuntu24 [78.4 kB] 1636s Get:17 http://ftpmaster.internal/ubuntu questing/main amd64 gpgv amd64 2.4.4-2ubuntu24 [160 kB] 1636s Get:18 http://ftpmaster.internal/ubuntu questing/main amd64 dhcpcd-base amd64 1:10.1.0-10 [219 kB] 1636s Get:19 http://ftpmaster.internal/ubuntu questing/main amd64 gir1.2-glib-2.0 amd64 2.84.1-2 [184 kB] 1636s Get:20 http://ftpmaster.internal/ubuntu questing/main amd64 libglib2.0-0t64 amd64 2.84.1-2 [1584 kB] 1636s Get:21 http://ftpmaster.internal/ubuntu questing/main amd64 libglib2.0-data all 2.84.1-2 [53.2 kB] 1636s Get:22 http://ftpmaster.internal/ubuntu questing/main amd64 libxml2 amd64 2.12.7+dfsg+really2.9.14-0.4ubuntu0.1 [772 kB] 1636s Get:23 http://ftpmaster.internal/ubuntu questing/main amd64 netbase all 6.5 [12.9 kB] 1636s Get:24 http://ftpmaster.internal/ubuntu questing/main amd64 groff-base amd64 1.23.0-8 [1023 kB] 1636s Get:25 http://ftpmaster.internal/ubuntu questing/main amd64 libnuma1 amd64 2.0.19-1 [23.5 kB] 1636s Get:26 http://ftpmaster.internal/ubuntu questing/main amd64 libx11-data all 2:1.8.12-1 [116 kB] 1636s Get:27 http://ftpmaster.internal/ubuntu questing/main amd64 libx11-6 amd64 2:1.8.12-1 [656 kB] 1636s Get:28 http://ftpmaster.internal/ubuntu questing/main amd64 numactl amd64 2.0.19-1 [38.8 kB] 1636s Get:29 http://ftpmaster.internal/ubuntu questing/main amd64 gnupg-l10n all 2.4.4-2ubuntu24 [66.8 kB] 1636s Get:30 http://ftpmaster.internal/ubuntu questing/main amd64 python3-packaging all 25.0-1 [52.8 kB] 1636s Get:31 http://ftpmaster.internal/ubuntu questing/main amd64 python3-wadllib all 2.0.0-3 [36.3 kB] 1637s Preconfiguring packages ... 1637s Fetched 9531 kB in 1s (10.2 MB/s) 1637s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 80527 files and directories currently installed.) 1637s Preparing to unpack .../gawk_1%3a5.3.2-1_amd64.deb ... 1637s Unpacking gawk (1:5.3.2-1) over (1:5.2.1-2build3) ... 1637s Preparing to unpack .../libselinux1_3.8.1-1_amd64.deb ... 1637s Unpacking libselinux1:amd64 (3.8.1-1) over (3.7-3ubuntu3) ... 1637s Setting up libselinux1:amd64 (3.8.1-1) ... 1637s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 80529 files and directories currently installed.) 1637s Preparing to unpack .../openssh-sftp-server_1%3a9.9p1-3ubuntu3.1_amd64.deb ... 1637s Unpacking openssh-sftp-server (1:9.9p1-3ubuntu3.1) over (1:9.9p1-3ubuntu3) ... 1637s Preparing to unpack .../openssh-server_1%3a9.9p1-3ubuntu3.1_amd64.deb ... 1637s Unpacking openssh-server (1:9.9p1-3ubuntu3.1) over (1:9.9p1-3ubuntu3) ... 1637s Preparing to unpack .../openssh-client_1%3a9.9p1-3ubuntu3.1_amd64.deb ... 1637s Unpacking openssh-client (1:9.9p1-3ubuntu3.1) over (1:9.9p1-3ubuntu3) ... 1637s Preparing to unpack .../libgpg-error-l10n_1.51-4_all.deb ... 1637s Unpacking libgpg-error-l10n (1.51-4) over (1.51-3) ... 1638s Preparing to unpack .../libgpg-error0_1.51-4_amd64.deb ... 1638s Unpacking libgpg-error0:amd64 (1.51-4) over (1.51-3) ... 1638s Setting up libgpg-error0:amd64 (1.51-4) ... 1638s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 80529 files and directories currently installed.) 1638s Preparing to unpack .../0-gpg-wks-client_2.4.4-2ubuntu24_amd64.deb ... 1638s Unpacking gpg-wks-client (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 1638s Preparing to unpack .../1-dirmngr_2.4.4-2ubuntu24_amd64.deb ... 1638s Unpacking dirmngr (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 1638s Preparing to unpack .../2-gpgsm_2.4.4-2ubuntu24_amd64.deb ... 1638s Unpacking gpgsm (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 1638s Preparing to unpack .../3-gnupg-utils_2.4.4-2ubuntu24_amd64.deb ... 1638s Unpacking gnupg-utils (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 1638s Preparing to unpack .../4-gpg-agent_2.4.4-2ubuntu24_amd64.deb ... 1638s Unpacking gpg-agent (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 1638s Preparing to unpack .../5-gpg_2.4.4-2ubuntu24_amd64.deb ... 1638s Unpacking gpg (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 1638s Preparing to unpack .../6-gpgconf_2.4.4-2ubuntu24_amd64.deb ... 1638s Unpacking gpgconf (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 1638s Preparing to unpack .../7-gnupg_2.4.4-2ubuntu24_all.deb ... 1638s Unpacking gnupg (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 1638s Preparing to unpack .../8-keyboxd_2.4.4-2ubuntu24_amd64.deb ... 1638s Unpacking keyboxd (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 1638s Preparing to unpack .../9-gpgv_2.4.4-2ubuntu24_amd64.deb ... 1638s Unpacking gpgv (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 1638s Setting up gpgv (2.4.4-2ubuntu24) ... 1638s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 80529 files and directories currently installed.) 1638s Preparing to unpack .../00-dhcpcd-base_1%3a10.1.0-10_amd64.deb ... 1638s Unpacking dhcpcd-base (1:10.1.0-10) over (1:10.1.0-8) ... 1638s Preparing to unpack .../01-gir1.2-glib-2.0_2.84.1-2_amd64.deb ... 1638s Unpacking gir1.2-glib-2.0:amd64 (2.84.1-2) over (2.84.1-1) ... 1638s Preparing to unpack .../02-libglib2.0-0t64_2.84.1-2_amd64.deb ... 1638s Unpacking libglib2.0-0t64:amd64 (2.84.1-2) over (2.84.1-1) ... 1638s Preparing to unpack .../03-libglib2.0-data_2.84.1-2_all.deb ... 1638s Unpacking libglib2.0-data (2.84.1-2) over (2.84.1-1) ... 1638s Preparing to unpack .../04-libxml2_2.12.7+dfsg+really2.9.14-0.4ubuntu0.1_amd64.deb ... 1638s Unpacking libxml2:amd64 (2.12.7+dfsg+really2.9.14-0.4ubuntu0.1) over (2.12.7+dfsg+really2.9.14-0.4) ... 1638s Preparing to unpack .../05-netbase_6.5_all.deb ... 1638s Unpacking netbase (6.5) over (6.4) ... 1638s Preparing to unpack .../06-groff-base_1.23.0-8_amd64.deb ... 1638s Unpacking groff-base (1.23.0-8) over (1.23.0-7) ... 1638s Preparing to unpack .../07-libnuma1_2.0.19-1_amd64.deb ... 1638s Unpacking libnuma1:amd64 (2.0.19-1) over (2.0.18-1build1) ... 1639s Preparing to unpack .../08-libx11-data_2%3a1.8.12-1_all.deb ... 1639s Unpacking libx11-data (2:1.8.12-1) over (2:1.8.10-2) ... 1639s Preparing to unpack .../09-libx11-6_2%3a1.8.12-1_amd64.deb ... 1639s Unpacking libx11-6:amd64 (2:1.8.12-1) over (2:1.8.10-2) ... 1639s Preparing to unpack .../10-numactl_2.0.19-1_amd64.deb ... 1639s Unpacking numactl (2.0.19-1) over (2.0.18-1build1) ... 1639s Preparing to unpack .../11-gnupg-l10n_2.4.4-2ubuntu24_all.deb ... 1639s Unpacking gnupg-l10n (2.4.4-2ubuntu24) over (2.4.4-2ubuntu23) ... 1639s Preparing to unpack .../12-python3-packaging_25.0-1_all.deb ... 1639s Unpacking python3-packaging (25.0-1) over (24.2-1) ... 1639s Preparing to unpack .../13-python3-wadllib_2.0.0-3_all.deb ... 1639s Unpacking python3-wadllib (2.0.0-3) over (2.0.0-2) ... 1639s Setting up gawk (1:5.3.2-1) ... 1639s Setting up openssh-client (1:9.9p1-3ubuntu3.1) ... 1639s Setting up libglib2.0-0t64:amd64 (2.84.1-2) ... 1639s No schema files found: doing nothing. 1639s Setting up libglib2.0-data (2.84.1-2) ... 1639s Setting up python3-packaging (25.0-1) ... 1639s Setting up libx11-data (2:1.8.12-1) ... 1639s Setting up gnupg-l10n (2.4.4-2ubuntu24) ... 1639s Setting up python3-wadllib (2.0.0-3) ... 1639s Setting up dhcpcd-base (1:10.1.0-10) ... 1639s Installing new version of config file /etc/dhcpcd.conf ... 1639s Setting up gir1.2-glib-2.0:amd64 (2.84.1-2) ... 1639s Setting up libnuma1:amd64 (2.0.19-1) ... 1639s Setting up groff-base (1.23.0-8) ... 1639s Setting up gpgconf (2.4.4-2ubuntu24) ... 1639s Setting up libx11-6:amd64 (2:1.8.12-1) ... 1639s Setting up netbase (6.5) ... 1639s Installing new version of config file /etc/ethertypes ... 1639s Installing new version of config file /etc/services ... 1639s Setting up libgpg-error-l10n (1.51-4) ... 1639s Setting up libxml2:amd64 (2.12.7+dfsg+really2.9.14-0.4ubuntu0.1) ... 1639s Setting up gpg (2.4.4-2ubuntu24) ... 1639s Setting up gnupg-utils (2.4.4-2ubuntu24) ... 1639s Setting up openssh-sftp-server (1:9.9p1-3ubuntu3.1) ... 1639s Setting up gpg-agent (2.4.4-2ubuntu24) ... 1640s Setting up numactl (2.0.19-1) ... 1640s Setting up openssh-server (1:9.9p1-3ubuntu3.1) ... 1641s Setting up gpgsm (2.4.4-2ubuntu24) ... 1641s Setting up dirmngr (2.4.4-2ubuntu24) ... 1641s Setting up keyboxd (2.4.4-2ubuntu24) ... 1641s Setting up gnupg (2.4.4-2ubuntu24) ... 1641s Setting up gpg-wks-client (2.4.4-2ubuntu24) ... 1641s Processing triggers for ufw (0.36.2-9) ... 1641s Processing triggers for man-db (2.13.1-1) ... 1643s Processing triggers for install-info (7.1.1-1) ... 1643s Processing triggers for libc-bin (2.41-6ubuntu1) ... 1643s Reading package lists... 1644s Building dependency tree... 1644s Reading state information... 1644s Starting pkgProblemResolver with broken count: 0 1644s Starting 2 pkgProblemResolver with broken count: 0 1644s Done 1644s Solving dependencies... 1645s The following packages will be REMOVED: 1645s libsigsegv2* 1645s 0 upgraded, 0 newly installed, 1 to remove and 0 not upgraded. 1645s After this operation, 48.1 kB disk space will be freed. 1645s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 80529 files and directories currently installed.) 1645s Removing libsigsegv2:amd64 (2.14-1ubuntu2) ... 1645s Processing triggers for libc-bin (2.41-6ubuntu1) ... 1645s autopkgtest [22:45:31]: rebooting testbed after setup commands that affected boot 1671s Reading package lists... 1671s Building dependency tree... 1671s Reading state information... 1672s Starting pkgProblemResolver with broken count: 0 1672s Starting 2 pkgProblemResolver with broken count: 0 1672s Done 1672s The following NEW packages will be installed: 1672s libtcl8.6 python3-click yosys yosys-abc 1672s 0 upgraded, 4 newly installed, 0 to remove and 0 not upgraded. 1672s Need to get 10.2 MB of archives. 1672s After this operation, 32.5 MB of additional disk space will be used. 1672s Get:1 http://ftpmaster.internal/ubuntu questing/main amd64 libtcl8.6 amd64 8.6.16+dfsg-1 [1086 kB] 1673s Get:2 http://ftpmaster.internal/ubuntu questing/main amd64 python3-click all 8.2.0+0.really.8.1.8-1 [80.0 kB] 1673s Get:3 http://ftpmaster.internal/ubuntu questing/universe amd64 yosys-abc amd64 0.33-5build2 [5829 kB] 1673s Get:4 http://ftpmaster.internal/ubuntu questing/universe amd64 yosys amd64 0.33-5build2 [3222 kB] 1673s Fetched 10.2 MB in 1s (9825 kB/s) 1673s Selecting previously unselected package libtcl8.6:amd64. 1674s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 80522 files and directories currently installed.) 1674s Preparing to unpack .../libtcl8.6_8.6.16+dfsg-1_amd64.deb ... 1674s Unpacking libtcl8.6:amd64 (8.6.16+dfsg-1) ... 1674s Selecting previously unselected package python3-click. 1674s Preparing to unpack .../python3-click_8.2.0+0.really.8.1.8-1_all.deb ... 1674s Unpacking python3-click (8.2.0+0.really.8.1.8-1) ... 1674s Selecting previously unselected package yosys-abc. 1674s Preparing to unpack .../yosys-abc_0.33-5build2_amd64.deb ... 1674s Unpacking yosys-abc (0.33-5build2) ... 1674s Selecting previously unselected package yosys. 1674s Preparing to unpack .../yosys_0.33-5build2_amd64.deb ... 1674s Unpacking yosys (0.33-5build2) ... 1674s Setting up yosys-abc (0.33-5build2) ... 1674s Setting up python3-click (8.2.0+0.really.8.1.8-1) ... 1674s Setting up libtcl8.6:amd64 (8.6.16+dfsg-1) ... 1674s Setting up yosys (0.33-5build2) ... 1674s Processing triggers for libc-bin (2.41-6ubuntu1) ... 1674s Processing triggers for man-db (2.13.1-1) ... 1690s autopkgtest [22:46:16]: test ice: [----------------------- 1690s 1690s /----------------------------------------------------------------------------\ 1690s | | 1690s | yosys -- Yosys Open SYnthesis Suite | 1690s | | 1690s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1690s | | 1690s | Permission to use, copy, modify, and/or distribute this software for any | 1690s | purpose with or without fee is hereby granted, provided that the above | 1690s | copyright notice and this permission notice appear in all copies. | 1690s | | 1690s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1690s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1690s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1690s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1690s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1690s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1690s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1690s | | 1690s \----------------------------------------------------------------------------/ 1690s 1690s Yosys 0.33 (git sha1 2584903a060) 1690s 1690s 1690s -- Running command `read_verilog debian/tests/design_ice.v; synth_ice40 -blif /tmp/autopkgtest.JGlVyS/autopkgtest_tmp/design_ice.blif' -- 1690s 1690s 1. Executing Verilog-2005 frontend: debian/tests/design_ice.v 1690s Parsing Verilog input from `debian/tests/design_ice.v' to AST representation. 1690s Generating RTLIL representation for module `\design_ice'. 1690s Successfully finished Verilog frontend. 1690s 1690s 2. Executing SYNTH_ICE40 pass. 1690s 1690s 2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v 1690s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation. 1690s Generating RTLIL representation for module `\SB_IO'. 1690s Generating RTLIL representation for module `\SB_GB_IO'. 1690s Generating RTLIL representation for module `\SB_GB'. 1690s Generating RTLIL representation for module `\SB_LUT4'. 1690s Generating RTLIL representation for module `\SB_CARRY'. 1690s Generating RTLIL representation for module `\SB_DFF'. 1690s Generating RTLIL representation for module `\SB_DFFE'. 1690s Generating RTLIL representation for module `\SB_DFFSR'. 1690s Generating RTLIL representation for module `\SB_DFFR'. 1690s Generating RTLIL representation for module `\SB_DFFSS'. 1690s Generating RTLIL representation for module `\SB_DFFS'. 1690s Generating RTLIL representation for module `\SB_DFFESR'. 1690s Generating RTLIL representation for module `\SB_DFFER'. 1690s Generating RTLIL representation for module `\SB_DFFESS'. 1690s Generating RTLIL representation for module `\SB_DFFES'. 1690s Generating RTLIL representation for module `\SB_DFFN'. 1690s Generating RTLIL representation for module `\SB_DFFNE'. 1690s Generating RTLIL representation for module `\SB_DFFNSR'. 1690s Generating RTLIL representation for module `\SB_DFFNR'. 1690s Generating RTLIL representation for module `\SB_DFFNSS'. 1690s Generating RTLIL representation for module `\SB_DFFNS'. 1690s Generating RTLIL representation for module `\SB_DFFNESR'. 1690s Generating RTLIL representation for module `\SB_DFFNER'. 1690s Generating RTLIL representation for module `\SB_DFFNESS'. 1690s Generating RTLIL representation for module `\SB_DFFNES'. 1690s Generating RTLIL representation for module `\SB_RAM40_4K'. 1690s Generating RTLIL representation for module `\SB_RAM40_4KNR'. 1690s Generating RTLIL representation for module `\SB_RAM40_4KNW'. 1690s Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. 1690s Generating RTLIL representation for module `\ICESTORM_LC'. 1690s Generating RTLIL representation for module `\SB_PLL40_CORE'. 1690s Generating RTLIL representation for module `\SB_PLL40_PAD'. 1690s Generating RTLIL representation for module `\SB_PLL40_2_PAD'. 1690s Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. 1690s Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. 1690s Generating RTLIL representation for module `\SB_WARMBOOT'. 1690s Generating RTLIL representation for module `\SB_SPRAM256KA'. 1690s Generating RTLIL representation for module `\SB_HFOSC'. 1690s Generating RTLIL representation for module `\SB_LFOSC'. 1690s Generating RTLIL representation for module `\SB_RGBA_DRV'. 1690s Generating RTLIL representation for module `\SB_LED_DRV_CUR'. 1690s Generating RTLIL representation for module `\SB_RGB_DRV'. 1690s Generating RTLIL representation for module `\SB_I2C'. 1690s Generating RTLIL representation for module `\SB_SPI'. 1690s Generating RTLIL representation for module `\SB_LEDDA_IP'. 1690s Generating RTLIL representation for module `\SB_FILTER_50NS'. 1690s Generating RTLIL representation for module `\SB_IO_I3C'. 1690s Generating RTLIL representation for module `\SB_IO_OD'. 1690s Generating RTLIL representation for module `\SB_MAC16'. 1690s Generating RTLIL representation for module `\ICESTORM_RAM'. 1690s Successfully finished Verilog frontend. 1690s 1690s 2.2. Executing HIERARCHY pass (managing design hierarchy). 1690s 1690s 2.2.1. Finding top of design hierarchy.. 1690s root of 0 design levels: design_ice 1690s Automatically selected design_ice as design top module. 1690s 1690s 2.2.2. Analyzing design hierarchy.. 1690s Top module: \design_ice 1690s 1690s 2.2.3. Analyzing design hierarchy.. 1690s Top module: \design_ice 1690s Removed 0 unused modules. 1690s 1690s 2.3. Executing PROC pass (convert processes to netlists). 1690s 1690s 2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1690s Cleaned up 0 empty switches. 1690s 1690s 2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1690s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243 in module SB_DFFNES. 1690s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236 in module SB_DFFNESS. 1690s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232 in module SB_DFFNER. 1690s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225 in module SB_DFFNESR. 1690s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222 in module SB_DFFNS. 1690s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219 in module SB_DFFNSS. 1690s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216 in module SB_DFFNR. 1690s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213 in module SB_DFFNSR. 1690s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205 in module SB_DFFES. 1690s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198 in module SB_DFFESS. 1690s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194 in module SB_DFFER. 1690s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187 in module SB_DFFESR. 1690s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184 in module SB_DFFS. 1690s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181 in module SB_DFFSS. 1690s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178 in module SB_DFFR. 1690s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175 in module SB_DFFSR. 1690s Marked 1 switch rules as full_case in process $proc$debian/tests/design_ice.v:6$1 in module design_ice. 1690s Removed a total of 0 dead cases. 1690s 1690s 2.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1690s Removed 8 redundant assignments. 1690s Promoted 23 assignments to connections. 1690s 1690s 2.3.4. Executing PROC_INIT pass (extract init attributes). 1690s Found init rule in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$246'. 1690s Set init value: \Q = 1'0 1690s Found init rule in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$242'. 1690s Set init value: \Q = 1'0 1690s Found init rule in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$235'. 1690s Set init value: \Q = 1'0 1690s Found init rule in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$231'. 1690s Set init value: \Q = 1'0 1690s Found init rule in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$224'. 1690s Set init value: \Q = 1'0 1690s Found init rule in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$221'. 1690s Set init value: \Q = 1'0 1690s Found init rule in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$218'. 1690s Set init value: \Q = 1'0 1690s Found init rule in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$215'. 1690s Set init value: \Q = 1'0 1690s Found init rule in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$212'. 1690s Set init value: \Q = 1'0 1690s Found init rule in `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 1690s Set init value: \Q = 1'0 1690s Found init rule in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 1690s Set init value: \Q = 1'0 1690s Found init rule in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$204'. 1690s Set init value: \Q = 1'0 1690s Found init rule in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$197'. 1690s Set init value: \Q = 1'0 1690s Found init rule in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$193'. 1690s Set init value: \Q = 1'0 1690s Found init rule in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$186'. 1690s Set init value: \Q = 1'0 1690s Found init rule in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$183'. 1690s Set init value: \Q = 1'0 1690s Found init rule in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$180'. 1690s Set init value: \Q = 1'0 1690s Found init rule in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$177'. 1690s Set init value: \Q = 1'0 1690s Found init rule in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$174'. 1690s Set init value: \Q = 1'0 1690s Found init rule in `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 1690s Set init value: \Q = 1'0 1690s Found init rule in `\design_ice.$proc$debian/tests/design_ice.v:3$2'. 1690s Set init value: \ready = 1'0 1690s 1690s 2.3.5. Executing PROC_ARST pass (detect async resets in processes). 1690s Found async reset \S in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'. 1690s Found async reset \R in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'. 1690s Found async reset \S in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222'. 1690s Found async reset \R in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216'. 1690s Found async reset \S in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'. 1690s Found async reset \R in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'. 1690s Found async reset \S in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184'. 1690s Found async reset \R in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178'. 1690s 1690s 2.3.6. Executing PROC_ROM pass (convert switches to ROMs). 1690s Converted 0 switches. 1690s 1690s 1690s 2.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1690s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$246'. 1690s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'. 1690s 1/1: $0\Q[0:0] 1690s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$242'. 1690s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236'. 1690s 1/1: $0\Q[0:0] 1690s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$235'. 1690s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'. 1690s 1/1: $0\Q[0:0] 1690s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$231'. 1690s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225'. 1690s 1/1: $0\Q[0:0] 1690s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$224'. 1690s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222'. 1690s 1/1: $0\Q[0:0] 1690s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$221'. 1690s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219'. 1690s 1/1: $0\Q[0:0] 1690s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$218'. 1690s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216'. 1690s 1/1: $0\Q[0:0] 1690s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$215'. 1690s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213'. 1690s 1/1: $0\Q[0:0] 1690s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$212'. 1690s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$211'. 1690s 1/1: $0\Q[0:0] 1690s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 1690s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$209'. 1690s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 1690s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'. 1690s 1/1: $0\Q[0:0] 1690s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$204'. 1690s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198'. 1690s 1/1: $0\Q[0:0] 1690s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$197'. 1690s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'. 1690s 1/1: $0\Q[0:0] 1690s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$193'. 1690s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187'. 1690s 1/1: $0\Q[0:0] 1690s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$186'. 1690s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184'. 1690s 1/1: $0\Q[0:0] 1690s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$183'. 1690s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181'. 1690s 1/1: $0\Q[0:0] 1690s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$180'. 1690s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178'. 1690s 1/1: $0\Q[0:0] 1690s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$177'. 1690s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175'. 1690s 1/1: $0\Q[0:0] 1690s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$174'. 1690s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$173'. 1690s 1/1: $0\Q[0:0] 1690s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 1690s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$171'. 1690s Creating decoders for process `\design_ice.$proc$debian/tests/design_ice.v:3$2'. 1690s Creating decoders for process `\design_ice.$proc$debian/tests/design_ice.v:6$1'. 1690s 1/2: $0\value[0:0] 1690s 2/2: $0\ready[0:0] 1690s 1690s 2.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1690s 1690s 2.3.9. Executing PROC_DFF pass (convert process syncs to FFs). 1690s Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'. 1690s created $adff cell `$procdff$433' with negative edge clock and positive level reset. 1690s Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236'. 1690s created $dff cell `$procdff$434' with negative edge clock. 1690s Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'. 1690s created $adff cell `$procdff$435' with negative edge clock and positive level reset. 1690s Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225'. 1690s created $dff cell `$procdff$436' with negative edge clock. 1690s Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222'. 1690s created $adff cell `$procdff$437' with negative edge clock and positive level reset. 1690s Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219'. 1690s created $dff cell `$procdff$438' with negative edge clock. 1690s Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216'. 1690s created $adff cell `$procdff$439' with negative edge clock and positive level reset. 1690s Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213'. 1690s created $dff cell `$procdff$440' with negative edge clock. 1690s Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$211'. 1690s created $dff cell `$procdff$441' with negative edge clock. 1690s Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$209'. 1690s created $dff cell `$procdff$442' with negative edge clock. 1690s Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'. 1690s created $adff cell `$procdff$443' with positive edge clock and positive level reset. 1690s Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198'. 1690s created $dff cell `$procdff$444' with positive edge clock. 1690s Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'. 1690s created $adff cell `$procdff$445' with positive edge clock and positive level reset. 1690s Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187'. 1690s created $dff cell `$procdff$446' with positive edge clock. 1690s Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184'. 1690s created $adff cell `$procdff$447' with positive edge clock and positive level reset. 1690s Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181'. 1690s created $dff cell `$procdff$448' with positive edge clock. 1690s Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178'. 1690s created $adff cell `$procdff$449' with positive edge clock and positive level reset. 1690s Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175'. 1690s created $dff cell `$procdff$450' with positive edge clock. 1690s Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$173'. 1690s created $dff cell `$procdff$451' with positive edge clock. 1690s Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$171'. 1690s created $dff cell `$procdff$452' with positive edge clock. 1690s Creating register for signal `\design_ice.\ready' using process `\design_ice.$proc$debian/tests/design_ice.v:6$1'. 1690s created $dff cell `$procdff$453' with positive edge clock. 1690s Creating register for signal `\design_ice.\value' using process `\design_ice.$proc$debian/tests/design_ice.v:6$1'. 1690s created $dff cell `$procdff$454' with positive edge clock. 1690s 1690s 2.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1690s 1690s 2.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1690s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$246'. 1690s Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'. 1690s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'. 1690s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$242'. 1690s Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236'. 1690s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236'. 1690s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$235'. 1690s Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'. 1690s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'. 1690s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$231'. 1690s Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225'. 1690s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225'. 1690s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$224'. 1690s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222'. 1690s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$221'. 1690s Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219'. 1690s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219'. 1690s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$218'. 1690s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216'. 1690s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$215'. 1690s Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213'. 1690s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213'. 1690s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$212'. 1690s Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$211'. 1690s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$211'. 1690s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 1690s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$209'. 1690s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 1690s Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'. 1690s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'. 1690s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$204'. 1690s Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198'. 1690s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198'. 1690s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$197'. 1690s Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'. 1690s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'. 1690s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$193'. 1690s Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187'. 1690s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187'. 1690s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$186'. 1690s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184'. 1690s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$183'. 1690s Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181'. 1690s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181'. 1690s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$180'. 1690s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178'. 1690s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$177'. 1690s Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175'. 1690s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175'. 1690s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$174'. 1690s Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$173'. 1690s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$173'. 1690s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 1690s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$171'. 1690s Removing empty process `design_ice.$proc$debian/tests/design_ice.v:3$2'. 1690s Found and cleaned up 1 empty switch in `\design_ice.$proc$debian/tests/design_ice.v:6$1'. 1690s Removing empty process `design_ice.$proc$debian/tests/design_ice.v:6$1'. 1690s Cleaned up 19 empty switches. 1690s 1690s 2.3.12. Executing OPT_EXPR pass (perform const folding). 1690s Optimizing module design_ice. 1690s 1690s 2.4. Executing FLATTEN pass (flatten design). 1690s 1690s 2.5. Executing TRIBUF pass. 1690s 1690s 2.6. Executing DEMINOUT pass (demote inout ports to input or output). 1690s 1690s 2.7. Executing OPT_EXPR pass (perform const folding). 1690s Optimizing module design_ice. 1690s 1690s 2.8. Executing OPT_CLEAN pass (remove unused cells and wires). 1690s Finding unused cells or wires in module \design_ice.. 1690s Removed 0 unused cells and 5 unused wires. 1690s 1690s 1690s 2.9. Executing CHECK pass (checking for obvious problems). 1690s Checking module design_ice... 1690s Found and reported 0 problems. 1690s 1690s 2.10. Executing OPT pass (performing simple optimizations). 1690s 1690s 2.10.1. Executing OPT_EXPR pass (perform const folding). 1690s Optimizing module design_ice. 1690s 1690s 2.10.2. Executing OPT_MERGE pass (detect identical cells). 1690s Finding identical cells in module `\design_ice'. 1690s Removed a total of 0 cells. 1690s 1690s 2.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 1690s Running muxtree optimizer on module \design_ice.. 1690s Creating internal representation of mux trees. 1690s Evaluating internal representation of mux trees. 1690s Replacing known input bits on port B of cell $procmux$431: \ready -> 1'1 1690s Analyzing evaluation results. 1690s Removed 0 multiplexer ports. 1690s 1690s 1690s 2.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 1690s Optimizing cells in module \design_ice. 1690s Optimizing cells in module \design_ice. 1690s Performed a total of 1 changes. 1690s 1690s 2.10.5. Executing OPT_MERGE pass (detect identical cells). 1690s Finding identical cells in module `\design_ice'. 1690s Removed a total of 0 cells. 1690s 1690s 2.10.6. Executing OPT_DFF pass (perform DFF optimizations). 1690s 1690s 2.10.7. Executing OPT_CLEAN pass (remove unused cells and wires). 1690s Finding unused cells or wires in module \design_ice.. 1690s Removed 0 unused cells and 1 unused wires. 1690s 1690s 1690s 2.10.8. Executing OPT_EXPR pass (perform const folding). 1690s Optimizing module design_ice. 1690s 1690s 2.10.9. Rerunning OPT passes. (Maybe there is more to do..) 1690s 1690s 2.10.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 1690s Running muxtree optimizer on module \design_ice.. 1690s Creating internal representation of mux trees. 1690s Evaluating internal representation of mux trees. 1690s Analyzing evaluation results. 1690s Removed 0 multiplexer ports. 1690s 1690s 1690s 2.10.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 1690s Optimizing cells in module \design_ice. 1690s Performed a total of 0 changes. 1690s 1690s 2.10.12. Executing OPT_MERGE pass (detect identical cells). 1690s Finding identical cells in module `\design_ice'. 1690s Removed a total of 0 cells. 1690s 1690s 2.10.13. Executing OPT_DFF pass (perform DFF optimizations). 1690s 1690s 2.10.14. Executing OPT_CLEAN pass (remove unused cells and wires). 1690s Finding unused cells or wires in module \design_ice.. 1690s 1690s 2.10.15. Executing OPT_EXPR pass (perform const folding). 1690s Optimizing module design_ice. 1690s 1690s 2.10.16. Finished OPT passes. (There is nothing left to do.) 1690s 1690s 2.11. Executing FSM pass (extract and optimize FSM). 1690s 1690s 2.11.1. Executing FSM_DETECT pass (finding FSMs in design). 1690s 1690s 2.11.2. Executing FSM_EXTRACT pass (extracting FSM from design). 1690s 1690s 2.11.3. Executing FSM_OPT pass (simple optimizations of FSMs). 1690s 1690s 2.11.4. Executing OPT_CLEAN pass (remove unused cells and wires). 1690s Finding unused cells or wires in module \design_ice.. 1690s 1690s 2.11.5. Executing FSM_OPT pass (simple optimizations of FSMs). 1690s 1690s 2.11.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 1690s 1690s 2.11.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 1690s 1690s 2.11.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 1690s 1690s 2.12. Executing OPT pass (performing simple optimizations). 1690s 1690s 2.12.1. Executing OPT_EXPR pass (perform const folding). 1690s Optimizing module design_ice. 1690s 1690s 2.12.2. Executing OPT_MERGE pass (detect identical cells). 1690s Finding identical cells in module `\design_ice'. 1690s Removed a total of 0 cells. 1690s 1690s 2.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 1690s Running muxtree optimizer on module \design_ice.. 1690s Creating internal representation of mux trees. 1690s Evaluating internal representation of mux trees. 1690s Analyzing evaluation results. 1690s Removed 0 multiplexer ports. 1690s 1690s 1690s 2.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 1690s Optimizing cells in module \design_ice. 1690s Performed a total of 0 changes. 1690s 1690s 2.12.5. Executing OPT_MERGE pass (detect identical cells). 1690s Finding identical cells in module `\design_ice'. 1690s Removed a total of 0 cells. 1690s 1690s 2.12.6. Executing OPT_DFF pass (perform DFF optimizations). 1690s Adding EN signal on $procdff$454 ($dff) from module design_ice (D = \I1, Q = \value). 1690s 1690s 2.12.7. Executing OPT_CLEAN pass (remove unused cells and wires). 1690s Finding unused cells or wires in module \design_ice.. 1690s Removed 1 unused cells and 1 unused wires. 1690s 1690s 1690s 2.12.8. Executing OPT_EXPR pass (perform const folding). 1690s Optimizing module design_ice. 1690s 1690s 2.12.9. Rerunning OPT passes. (Maybe there is more to do..) 1690s 1690s 2.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 1690s Running muxtree optimizer on module \design_ice.. 1690s Creating internal representation of mux trees. 1690s No muxes found in this module. 1690s Removed 0 multiplexer ports. 1690s 1690s 2.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 1690s Optimizing cells in module \design_ice. 1690s Performed a total of 0 changes. 1690s 1690s 2.12.12. Executing OPT_MERGE pass (detect identical cells). 1690s Finding identical cells in module `\design_ice'. 1690s Removed a total of 0 cells. 1690s 1690s 2.12.13. Executing OPT_DFF pass (perform DFF optimizations). 1690s 1690s 2.12.14. Executing OPT_CLEAN pass (remove unused cells and wires). 1690s Finding unused cells or wires in module \design_ice.. 1690s 1690s 2.12.15. Executing OPT_EXPR pass (perform const folding). 1690s Optimizing module design_ice. 1690s 1690s 2.12.16. Finished OPT passes. (There is nothing left to do.) 1690s 1690s 2.13. Executing WREDUCE pass (reducing word size of cells). 1690s 1690s 2.14. Executing PEEPOPT pass (run peephole optimizers). 1690s 1690s 2.15. Executing OPT_CLEAN pass (remove unused cells and wires). 1690s Finding unused cells or wires in module \design_ice.. 1690s 1690s 2.16. Executing SHARE pass (SAT-based resource sharing). 1690s 1690s 2.17. Executing TECHMAP pass (map to technology primitives). 1690s 1690s 2.17.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v 1690s Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation. 1690s Generating RTLIL representation for module `\_90_lut_cmp_'. 1690s Successfully finished Verilog frontend. 1690s 1690s 2.17.2. Continuing TECHMAP pass. 1690s No more expansions possible. 1690s 1690s 1690s 2.18. Executing OPT_EXPR pass (perform const folding). 1690s Optimizing module design_ice. 1690s 1690s 2.19. Executing OPT_CLEAN pass (remove unused cells and wires). 1690s Finding unused cells or wires in module \design_ice.. 1690s 1690s 2.20. Executing ALUMACC pass (create $alu and $macc cells). 1690s Extracting $alu and $macc cells in module design_ice: 1690s created 0 $alu and 0 $macc cells. 1690s 1690s 2.21. Executing OPT pass (performing simple optimizations). 1690s 1690s 2.21.1. Executing OPT_EXPR pass (perform const folding). 1690s Optimizing module design_ice. 1690s 1690s 2.21.2. Executing OPT_MERGE pass (detect identical cells). 1690s Finding identical cells in module `\design_ice'. 1690s Removed a total of 0 cells. 1690s 1690s 2.21.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 1690s Running muxtree optimizer on module \design_ice.. 1690s Creating internal representation of mux trees. 1690s No muxes found in this module. 1690s Removed 0 multiplexer ports. 1690s 1690s 2.21.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 1690s Optimizing cells in module \design_ice. 1690s Performed a total of 0 changes. 1690s 1690s 2.21.5. Executing OPT_MERGE pass (detect identical cells). 1690s Finding identical cells in module `\design_ice'. 1690s Removed a total of 0 cells. 1690s 1690s 2.21.6. Executing OPT_DFF pass (perform DFF optimizations). 1690s 1690s 2.21.7. Executing OPT_CLEAN pass (remove unused cells and wires). 1690s Finding unused cells or wires in module \design_ice.. 1690s 1690s 2.21.8. Executing OPT_EXPR pass (perform const folding). 1690s Optimizing module design_ice. 1690s 1690s 2.21.9. Finished OPT passes. (There is nothing left to do.) 1690s 1690s 2.22. Executing MEMORY pass. 1690s 1690s 2.22.1. Executing OPT_MEM pass (optimize memories). 1690s Performed a total of 0 transformations. 1690s 1690s 2.22.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). 1690s Performed a total of 0 transformations. 1690s 1690s 2.22.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 1690s 1690s 2.22.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 1690s 1690s 2.22.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 1690s 1690s 2.22.6. Executing OPT_CLEAN pass (remove unused cells and wires). 1690s Finding unused cells or wires in module \design_ice.. 1690s 1690s 2.22.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 1690s 1690s 2.22.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). 1690s Performed a total of 0 transformations. 1690s 1690s 2.22.9. Executing OPT_CLEAN pass (remove unused cells and wires). 1690s Finding unused cells or wires in module \design_ice.. 1690s 1690s 2.22.10. Executing MEMORY_COLLECT pass (generating $mem cells). 1690s 1690s 2.23. Executing OPT_CLEAN pass (remove unused cells and wires). 1690s Finding unused cells or wires in module \design_ice.. 1690s 1690s 2.24. Executing MEMORY_LIBMAP pass (mapping memories to cells). 1690s 1690s 2.25. Executing TECHMAP pass (map to technology primitives). 1690s 1690s 2.25.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v 1690s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation. 1690s Generating RTLIL representation for module `\$__ICE40_RAM4K_'. 1690s Successfully finished Verilog frontend. 1690s 1690s 2.25.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/spram_map.v 1690s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/spram_map.v' to AST representation. 1690s Generating RTLIL representation for module `\$__ICE40_SPRAM_'. 1690s Successfully finished Verilog frontend. 1690s 1690s 2.25.3. Continuing TECHMAP pass. 1690s No more expansions possible. 1690s 1690s 1690s 2.26. Executing ICE40_BRAMINIT pass. 1690s 1690s 2.27. Executing OPT pass (performing simple optimizations). 1690s 1690s 2.27.1. Executing OPT_EXPR pass (perform const folding). 1690s Optimizing module design_ice. 1690s 1690s 2.27.2. Executing OPT_MERGE pass (detect identical cells). 1690s Finding identical cells in module `\design_ice'. 1690s Removed a total of 0 cells. 1690s 1690s 2.27.3. Executing OPT_DFF pass (perform DFF optimizations). 1690s 1690s 2.27.4. Executing OPT_CLEAN pass (remove unused cells and wires). 1690s Finding unused cells or wires in module \design_ice.. 1690s 1690s 2.27.5. Finished fast OPT passes. 1690s 1690s 2.28. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 1690s 1690s 2.29. Executing OPT pass (performing simple optimizations). 1690s 1690s 2.29.1. Executing OPT_EXPR pass (perform const folding). 1690s Optimizing module design_ice. 1690s 1690s 2.29.2. Executing OPT_MERGE pass (detect identical cells). 1690s Finding identical cells in module `\design_ice'. 1690s Removed a total of 0 cells. 1690s 1690s 2.29.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 1690s Running muxtree optimizer on module \design_ice.. 1690s Creating internal representation of mux trees. 1690s No muxes found in this module. 1690s Removed 0 multiplexer ports. 1690s 1690s 2.29.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 1690s Optimizing cells in module \design_ice. 1690s Performed a total of 0 changes. 1690s 1690s 2.29.5. Executing OPT_MERGE pass (detect identical cells). 1690s Finding identical cells in module `\design_ice'. 1690s Removed a total of 0 cells. 1690s 1690s 2.29.6. Executing OPT_DFF pass (perform DFF optimizations). 1690s 1690s 2.29.7. Executing OPT_CLEAN pass (remove unused cells and wires). 1690s Finding unused cells or wires in module \design_ice.. 1690s 1690s 2.29.8. Executing OPT_EXPR pass (perform const folding). 1690s Optimizing module design_ice. 1690s 1690s 2.29.9. Finished OPT passes. (There is nothing left to do.) 1690s 1690s 2.30. Executing ICE40_WRAPCARRY pass (wrap carries). 1690s 1690s 2.31. Executing TECHMAP pass (map to technology primitives). 1690s 1690s 2.31.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v 1690s Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation. 1690s Generating RTLIL representation for module `\_90_simplemap_bool_ops'. 1690s Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. 1690s Generating RTLIL representation for module `\_90_simplemap_logic_ops'. 1690s Generating RTLIL representation for module `\_90_simplemap_compare_ops'. 1690s Generating RTLIL representation for module `\_90_simplemap_various'. 1690s Generating RTLIL representation for module `\_90_simplemap_registers'. 1690s Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. 1690s Generating RTLIL representation for module `\_90_shift_shiftx'. 1690s Generating RTLIL representation for module `\_90_fa'. 1690s Generating RTLIL representation for module `\_90_lcu'. 1690s Generating RTLIL representation for module `\_90_alu'. 1690s Generating RTLIL representation for module `\_90_macc'. 1690s Generating RTLIL representation for module `\_90_alumacc'. 1690s Generating RTLIL representation for module `\$__div_mod_u'. 1690s Generating RTLIL representation for module `\$__div_mod_trunc'. 1690s Generating RTLIL representation for module `\_90_div'. 1690s Generating RTLIL representation for module `\_90_mod'. 1690s Generating RTLIL representation for module `\$__div_mod_floor'. 1690s Generating RTLIL representation for module `\_90_divfloor'. 1690s Generating RTLIL representation for module `\_90_modfloor'. 1690s Generating RTLIL representation for module `\_90_pow'. 1690s Generating RTLIL representation for module `\_90_pmux'. 1690s Generating RTLIL representation for module `\_90_demux'. 1690s Generating RTLIL representation for module `\_90_lut'. 1690s Successfully finished Verilog frontend. 1690s 1690s 2.31.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v 1690s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation. 1690s Generating RTLIL representation for module `\_80_ice40_alu'. 1690s Successfully finished Verilog frontend. 1690s 1690s 2.31.3. Continuing TECHMAP pass. 1690s Using extmapper simplemap for cells of type $dffe. 1690s Using extmapper simplemap for cells of type $dff. 1690s No more expansions possible. 1690s 1690s 1690s 2.32. Executing OPT pass (performing simple optimizations). 1690s 1690s 2.32.1. Executing OPT_EXPR pass (perform const folding). 1690s Optimizing module design_ice. 1690s 1690s 2.32.2. Executing OPT_MERGE pass (detect identical cells). 1690s Finding identical cells in module `\design_ice'. 1690s Removed a total of 0 cells. 1690s 1690s 2.32.3. Executing OPT_DFF pass (perform DFF optimizations). 1690s 1690s 2.32.4. Executing OPT_CLEAN pass (remove unused cells and wires). 1690s Finding unused cells or wires in module \design_ice.. 1690s 1690s 2.32.5. Finished fast OPT passes. 1690s 1690s 2.33. Executing ICE40_OPT pass (performing simple optimizations). 1690s 1690s 2.33.1. Running ICE40 specific optimizations. 1690s 1690s 2.33.2. Executing OPT_EXPR pass (perform const folding). 1690s Optimizing module design_ice. 1690s 1690s 2.33.3. Executing OPT_MERGE pass (detect identical cells). 1690s Finding identical cells in module `\design_ice'. 1690s Removed a total of 0 cells. 1690s 1690s 2.33.4. Executing OPT_DFF pass (perform DFF optimizations). 1690s 1690s 2.33.5. Executing OPT_CLEAN pass (remove unused cells and wires). 1690s Finding unused cells or wires in module \design_ice.. 1690s 1690s 2.33.6. Finished OPT passes. (There is nothing left to do.) 1690s 1690s 2.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 1690s 1690s 2.35. Executing TECHMAP pass (map to technology primitives). 1690s 1690s 2.35.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 1690s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 1690s Generating RTLIL representation for module `\$_DFF_N_'. 1690s Generating RTLIL representation for module `\$_DFF_P_'. 1690s Generating RTLIL representation for module `\$_DFFE_NP_'. 1690s Generating RTLIL representation for module `\$_DFFE_PP_'. 1690s Generating RTLIL representation for module `\$_DFF_NP0_'. 1690s Generating RTLIL representation for module `\$_DFF_NP1_'. 1690s Generating RTLIL representation for module `\$_DFF_PP0_'. 1690s Generating RTLIL representation for module `\$_DFF_PP1_'. 1690s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 1690s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 1690s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 1690s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 1690s Generating RTLIL representation for module `\$_SDFF_NP0_'. 1690s Generating RTLIL representation for module `\$_SDFF_NP1_'. 1690s Generating RTLIL representation for module `\$_SDFF_PP0_'. 1690s Generating RTLIL representation for module `\$_SDFF_PP1_'. 1690s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 1690s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 1690s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 1690s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 1690s Successfully finished Verilog frontend. 1690s 1690s 2.35.2. Continuing TECHMAP pass. 1690s Using template \$_DFF_P_ for cells of type $_DFF_P_. 1690s Using template \$_DFFE_PP_ for cells of type $_DFFE_PP_. 1690s No more expansions possible. 1690s 1690s 1690s 2.36. Executing OPT_EXPR pass (perform const folding). 1690s Optimizing module design_ice. 1690s 1690s 2.37. Executing SIMPLEMAP pass (map simple cells to gate primitives). 1690s 1690s 2.38. Executing ICE40_OPT pass (performing simple optimizations). 1690s 1690s 2.38.1. Running ICE40 specific optimizations. 1690s 1690s 2.38.2. Executing OPT_EXPR pass (perform const folding). 1690s Optimizing module design_ice. 1690s 1690s 2.38.3. Executing OPT_MERGE pass (detect identical cells). 1690s Finding identical cells in module `\design_ice'. 1690s Removed a total of 0 cells. 1690s 1690s 2.38.4. Executing OPT_DFF pass (perform DFF optimizations). 1690s 1690s 2.38.5. Executing OPT_CLEAN pass (remove unused cells and wires). 1690s Finding unused cells or wires in module \design_ice.. 1690s Removed 0 unused cells and 9 unused wires. 1690s 1690s 1690s 2.38.6. Rerunning OPT passes. (Removed registers in this run.) 1690s 1690s 2.38.7. Running ICE40 specific optimizations. 1690s 1690s 2.38.8. Executing OPT_EXPR pass (perform const folding). 1690s Optimizing module design_ice. 1690s 1690s 2.38.9. Executing OPT_MERGE pass (detect identical cells). 1690s Finding identical cells in module `\design_ice'. 1690s Removed a total of 0 cells. 1690s 1690s 2.38.10. Executing OPT_DFF pass (perform DFF optimizations). 1690s 1690s 2.38.11. Executing OPT_CLEAN pass (remove unused cells and wires). 1690s Finding unused cells or wires in module \design_ice.. 1690s 1690s 2.38.12. Finished OPT passes. (There is nothing left to do.) 1690s 1690s 2.39. Executing TECHMAP pass (map to technology primitives). 1690s 1690s 2.39.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v 1690s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation. 1690s Generating RTLIL representation for module `\$_DLATCH_N_'. 1690s Generating RTLIL representation for module `\$_DLATCH_P_'. 1690s Successfully finished Verilog frontend. 1690s 1690s 2.39.2. Continuing TECHMAP pass. 1690s No more expansions possible. 1690s 1690s 1690s 2.40. Executing ABC pass (technology mapping using ABC). 1690s 1690s 2.40.1. Extracting gate netlist of module `\design_ice' to `/input.blif'.. 1690s Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs. 1690s Don't call ABC as there is nothing to map. 1690s Removing temp directory. 1690s 1690s 2.41. Executing ICE40_WRAPCARRY pass (wrap carries). 1690s 1690s 2.42. Executing TECHMAP pass (map to technology primitives). 1690s 1690s 2.42.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 1690s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 1690s Generating RTLIL representation for module `\$_DFF_N_'. 1690s Generating RTLIL representation for module `\$_DFF_P_'. 1690s Generating RTLIL representation for module `\$_DFFE_NP_'. 1690s Generating RTLIL representation for module `\$_DFFE_PP_'. 1690s Generating RTLIL representation for module `\$_DFF_NP0_'. 1690s Generating RTLIL representation for module `\$_DFF_NP1_'. 1690s Generating RTLIL representation for module `\$_DFF_PP0_'. 1690s Generating RTLIL representation for module `\$_DFF_PP1_'. 1690s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 1690s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 1690s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 1690s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 1690s Generating RTLIL representation for module `\$_SDFF_NP0_'. 1690s Generating RTLIL representation for module `\$_SDFF_NP1_'. 1690s Generating RTLIL representation for module `\$_SDFF_PP0_'. 1690s Generating RTLIL representation for module `\$_SDFF_PP1_'. 1690s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 1690s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 1690s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 1690s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 1690s Successfully finished Verilog frontend. 1690s 1690s 2.42.2. Continuing TECHMAP pass. 1690s No more expansions possible. 1690s 1690s 1690s 2.43. Executing OPT_LUT pass (optimize LUTs). 1690s Discovering LUTs. 1690s Number of LUTs: 0 1690s with \SB_CARRY (#0) 0 1690s with \SB_CARRY (#1) 0 1690s 1690s Eliminating LUTs. 1690s Number of LUTs: 0 1690s with \SB_CARRY (#0) 0 1690s with \SB_CARRY (#1) 0 1690s 1690s Combining LUTs. 1690s Number of LUTs: 0 1690s with \SB_CARRY (#0) 0 1690s with \SB_CARRY (#1) 0 1690s 1690s Eliminated 0 LUTs. 1690s Combined 0 LUTs. 1690s 1690s 2.44. Executing TECHMAP pass (map to technology primitives). 1690s 1690s 2.44.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v 1690s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation. 1690s Generating RTLIL representation for module `\$lut'. 1690s Successfully finished Verilog frontend. 1690s 1690s 2.44.2. Continuing TECHMAP pass. 1690s No more expansions possible. 1690s 1690s 1690s 2.45. Executing AUTONAME pass. 1690s Renamed 2 objects in module design_ice (2 iterations). 1690s 1690s 1690s 2.46. Executing HIERARCHY pass (managing design hierarchy). 1690s 1690s 2.46.1. Analyzing design hierarchy.. 1690s Top module: \design_ice 1690s 1690s 2.46.2. Analyzing design hierarchy.. 1690s Top module: \design_ice 1690s Removed 0 unused modules. 1690s 1690s 2.47. Printing statistics. 1690s 1690s === design_ice === 1690s 1690s Number of wires: 5 1690s Number of wire bits: 5 1690s Number of public wires: 5 1690s Number of public wire bits: 5 1690s Number of memories: 0 1690s Number of memory bits: 0 1690s Number of processes: 0 1690s Number of cells: 2 1690s SB_DFF 1 1690s SB_DFFE 1 1690s 1690s 2.48. Executing CHECK pass (checking for obvious problems). 1690s Checking module design_ice... 1690s Found and reported 0 problems. 1690s 1690s 2.49. Executing BLIF backend. 1690s 1690s End of script. Logfile hash: 49b1f4135a, CPU: user 0.54s system 0.02s, MEM: 19.94 MB peak 1690s Yosys 0.33 (git sha1 2584903a060) 1690s Time spent: 71% 13x read_verilog (0 sec), 8% 1x synth_ice40 (0 sec), ... 1691s autopkgtest [22:46:17]: test ice: -----------------------] 1691s autopkgtest [22:46:17]: test ice: - - - - - - - - - - results - - - - - - - - - - 1691s ice PASS 1692s autopkgtest [22:46:18]: test smtbc: preparing testbed 1692s Reading package lists... 1692s Building dependency tree... 1692s Reading state information... 1692s Starting pkgProblemResolver with broken count: 0 1693s Starting 2 pkgProblemResolver with broken count: 0 1693s Done 1693s 0 upgraded, 0 newly installed, 0 to remove and 0 not upgraded. 1694s autopkgtest [22:46:20]: test smtbc: [----------------------- 1694s autopkgtest [22:46:20]: test smtbc: -----------------------] 1695s autopkgtest [22:46:21]: test smtbc: - - - - - - - - - - results - - - - - - - - - - 1695s smtbc PASS 1695s autopkgtest [22:46:21]: @@@@@@@@@@@@@@@@@@@@ summary 1695s yosys-testsuite PASS 1695s ice PASS 1695s smtbc PASS 1712s nova [W] Skipping flock for amd64 1712s Creating nova instance adt-questing-amd64-yosys-20250505-221806-juju-7f2275-prod-proposed-migration-environment-2-7789d234-fb3b-438f-a626-4da25cd68b69 from image adt/ubuntu-questing-amd64-server-20250505.img (UUID 1da2e1b3-5892-44f7-bdef-fb8deb9e2fcb)... 1712s nova [W] Timed out waiting for b4d57bfa-4f26-432c-be85-7cbd7d4d4594 to get deleted. 1712s nova [W] Skipping flock for amd64 1712s Creating nova instance adt-questing-amd64-yosys-20250505-221806-juju-7f2275-prod-proposed-migration-environment-2-7789d234-fb3b-438f-a626-4da25cd68b69 from image adt/ubuntu-questing-amd64-server-20250505.img (UUID 1da2e1b3-5892-44f7-bdef-fb8deb9e2fcb)... 1712s nova [W] Timed out waiting for 6961119d-d1b1-476f-9315-24faac59236c to get deleted.