0s autopkgtest [18:28:18]: starting date and time: 2025-03-15 18:28:18+0000 0s autopkgtest [18:28:18]: git checkout: 325255d2 Merge branch 'pin-any-arch' into 'ubuntu/production' 0s autopkgtest [18:28:18]: host juju-7f2275-prod-proposed-migration-environment-9; command line: /home/ubuntu/autopkgtest/runner/autopkgtest --output-dir /tmp/autopkgtest-work.jza48mq4/out --timeout-copy=6000 --setup-commands 'ln -s /dev/null /etc/systemd/system/bluetooth.service; printf "http_proxy=http://squid.internal:3128\nhttps_proxy=http://squid.internal:3128\nno_proxy=127.0.0.1,127.0.1.1,login.ubuntu.com,localhost,localdomain,novalocal,internal,archive.ubuntu.com,ports.ubuntu.com,security.ubuntu.com,ddebs.ubuntu.com,changelogs.ubuntu.com,keyserver.ubuntu.com,launchpadlibrarian.net,launchpadcontent.net,launchpad.net,10.24.0.0/24,keystone.ps5.canonical.com,objectstorage.prodstack5.canonical.com,radosgw.ps5.canonical.com\n" >> /etc/environment' --apt-pocket=proposed=src:glibc --apt-upgrade yosys --timeout-short=300 --timeout-copy=20000 --timeout-build=20000 --env=ADT_TEST_TRIGGERS=glibc/2.41-1ubuntu2 -- lxd -r lxd-armhf-10.145.243.9 lxd-armhf-10.145.243.9:autopkgtest/ubuntu/plucky/armhf 21s autopkgtest [18:28:39]: testbed dpkg architecture: armhf 23s autopkgtest [18:28:41]: testbed apt version: 2.9.33 27s autopkgtest [18:28:45]: @@@@@@@@@@@@@@@@@@@@ test bed setup 29s autopkgtest [18:28:47]: testbed release detected to be: None 37s autopkgtest [18:28:55]: updating testbed package index (apt update) 39s Get:1 http://ftpmaster.internal/ubuntu plucky-proposed InRelease [126 kB] 39s Get:2 http://ftpmaster.internal/ubuntu plucky InRelease [257 kB] 39s Get:3 http://ftpmaster.internal/ubuntu plucky-updates InRelease [126 kB] 40s Get:4 http://ftpmaster.internal/ubuntu plucky-security InRelease [126 kB] 40s Get:5 http://ftpmaster.internal/ubuntu plucky-proposed/main Sources [99.7 kB] 40s Get:6 http://ftpmaster.internal/ubuntu plucky-proposed/universe Sources [379 kB] 40s Get:7 http://ftpmaster.internal/ubuntu plucky-proposed/multiverse Sources [15.8 kB] 40s Get:8 http://ftpmaster.internal/ubuntu plucky-proposed/main armhf Packages [114 kB] 40s Get:9 http://ftpmaster.internal/ubuntu plucky-proposed/main armhf c-n-f Metadata [1832 B] 40s Get:10 http://ftpmaster.internal/ubuntu plucky-proposed/restricted armhf c-n-f Metadata [116 B] 40s Get:11 http://ftpmaster.internal/ubuntu plucky-proposed/universe armhf Packages [312 kB] 40s Get:12 http://ftpmaster.internal/ubuntu plucky-proposed/universe armhf c-n-f Metadata [11.1 kB] 40s Get:13 http://ftpmaster.internal/ubuntu plucky-proposed/multiverse armhf Packages [3472 B] 40s Get:14 http://ftpmaster.internal/ubuntu plucky-proposed/multiverse armhf c-n-f Metadata [240 B] 40s Get:15 http://ftpmaster.internal/ubuntu plucky/main Sources [1394 kB] 42s Get:16 http://ftpmaster.internal/ubuntu plucky/multiverse Sources [299 kB] 42s Get:17 http://ftpmaster.internal/ubuntu plucky/universe Sources [21.0 MB] 58s Get:18 http://ftpmaster.internal/ubuntu plucky/main armhf Packages [1378 kB] 59s Get:19 http://ftpmaster.internal/ubuntu plucky/main armhf c-n-f Metadata [29.4 kB] 59s Get:20 http://ftpmaster.internal/ubuntu plucky/restricted armhf c-n-f Metadata [108 B] 59s Get:21 http://ftpmaster.internal/ubuntu plucky/universe armhf Packages [15.1 MB] 72s Get:22 http://ftpmaster.internal/ubuntu plucky/multiverse armhf Packages [172 kB] 74s Fetched 41.0 MB in 35s (1182 kB/s) 75s Reading package lists... 81s autopkgtest [18:29:39]: upgrading testbed (apt dist-upgrade and autopurge) 83s Reading package lists... 84s Building dependency tree... 84s Reading state information... 84s Calculating upgrade...Starting pkgProblemResolver with broken count: 0 84s Starting 2 pkgProblemResolver with broken count: 0 84s Done 85s Entering ResolveByKeep 85s 85s Calculating upgrade... 86s The following packages will be upgraded: 86s libc-bin libc6 locales pinentry-curses python3-jinja2 sos strace 86s 7 upgraded, 0 newly installed, 0 to remove and 0 not upgraded. 86s Need to get 8683 kB of archives. 86s After this operation, 23.6 kB of additional disk space will be used. 86s Get:1 http://ftpmaster.internal/ubuntu plucky-proposed/main armhf libc6 armhf 2.41-1ubuntu2 [2932 kB] 89s Get:2 http://ftpmaster.internal/ubuntu plucky-proposed/main armhf libc-bin armhf 2.41-1ubuntu2 [545 kB] 89s Get:3 http://ftpmaster.internal/ubuntu plucky-proposed/main armhf locales all 2.41-1ubuntu2 [4246 kB] 93s Get:4 http://ftpmaster.internal/ubuntu plucky/main armhf strace armhf 6.13+ds-1ubuntu1 [445 kB] 94s Get:5 http://ftpmaster.internal/ubuntu plucky/main armhf pinentry-curses armhf 1.3.1-2ubuntu3 [40.6 kB] 94s Get:6 http://ftpmaster.internal/ubuntu plucky/main armhf python3-jinja2 all 3.1.5-2ubuntu1 [109 kB] 94s Get:7 http://ftpmaster.internal/ubuntu plucky/main armhf sos all 4.9.0-5 [365 kB] 95s Preconfiguring packages ... 95s Fetched 8683 kB in 8s (1039 kB/s) 95s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 64655 files and directories currently installed.) 95s Preparing to unpack .../libc6_2.41-1ubuntu2_armhf.deb ... 95s Unpacking libc6:armhf (2.41-1ubuntu2) over (2.41-1ubuntu1) ... 95s Setting up libc6:armhf (2.41-1ubuntu2) ... 96s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 64655 files and directories currently installed.) 96s Preparing to unpack .../libc-bin_2.41-1ubuntu2_armhf.deb ... 96s Unpacking libc-bin (2.41-1ubuntu2) over (2.41-1ubuntu1) ... 96s Setting up libc-bin (2.41-1ubuntu2) ... 96s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 64655 files and directories currently installed.) 96s Preparing to unpack .../locales_2.41-1ubuntu2_all.deb ... 96s Unpacking locales (2.41-1ubuntu2) over (2.41-1ubuntu1) ... 96s Preparing to unpack .../strace_6.13+ds-1ubuntu1_armhf.deb ... 96s Unpacking strace (6.13+ds-1ubuntu1) over (6.11-0ubuntu1) ... 96s Preparing to unpack .../pinentry-curses_1.3.1-2ubuntu3_armhf.deb ... 96s Unpacking pinentry-curses (1.3.1-2ubuntu3) over (1.3.1-2ubuntu2) ... 96s Preparing to unpack .../python3-jinja2_3.1.5-2ubuntu1_all.deb ... 96s Unpacking python3-jinja2 (3.1.5-2ubuntu1) over (3.1.5-2) ... 96s Preparing to unpack .../archives/sos_4.9.0-5_all.deb ... 97s Unpacking sos (4.9.0-5) over (4.9.0-4) ... 97s Setting up sos (4.9.0-5) ... 97s Setting up pinentry-curses (1.3.1-2ubuntu3) ... 97s Setting up locales (2.41-1ubuntu2) ... 98s Generating locales (this might take a while)... 100s en_US.UTF-8... done 100s Generation complete. 100s Setting up python3-jinja2 (3.1.5-2ubuntu1) ... 100s Setting up strace (6.13+ds-1ubuntu1) ... 100s Processing triggers for man-db (2.13.0-1) ... 101s Processing triggers for systemd (257.3-1ubuntu3) ... 104s Reading package lists... 104s Building dependency tree... 104s Reading state information... 105s Starting pkgProblemResolver with broken count: 0 105s Starting 2 pkgProblemResolver with broken count: 0 105s Done 105s Solving dependencies... 106s 0 upgraded, 0 newly installed, 0 to remove and 0 not upgraded. 108s autopkgtest [18:30:06]: rebooting testbed after setup commands that affected boot 149s autopkgtest [18:30:47]: testbed running kernel: Linux 6.8.0-52-generic #53~22.04.1-Ubuntu SMP PREEMPT_DYNAMIC Wed Jan 15 18:10:51 UTC 2 175s autopkgtest [18:31:13]: @@@@@@@@@@@@@@@@@@@@ apt-source yosys 205s Get:1 http://ftpmaster.internal/ubuntu plucky/universe yosys 0.33-5build2 (dsc) [3069 B] 205s Get:2 http://ftpmaster.internal/ubuntu plucky/universe yosys 0.33-5build2 (tar) [6161 kB] 205s Get:3 http://ftpmaster.internal/ubuntu plucky/universe yosys 0.33-5build2 (tar) [2586 kB] 205s Get:4 http://ftpmaster.internal/ubuntu plucky/universe yosys 0.33-5build2 (diff) [30.3 kB] 205s gpgv: Signature made Mon Apr 1 04:53:46 2024 UTC 205s gpgv: using RSA key A089FB36AAFBDAD5ACC1325069F790171A210984 205s gpgv: Can't check signature: No public key 205s dpkg-source: warning: cannot verify inline signature for ./yosys_0.33-5build2.dsc: no acceptable signature found 206s autopkgtest [18:31:44]: testing package yosys version 0.33-5build2 208s autopkgtest [18:31:46]: build not needed 213s autopkgtest [18:31:51]: test yosys-testsuite: preparing testbed 215s Reading package lists... 215s Building dependency tree... 215s Reading state information... 215s Starting pkgProblemResolver with broken count: 0 216s Starting 2 pkgProblemResolver with broken count: 0 216s Done 216s The following NEW packages will be installed: 216s cpp cpp-14 cpp-14-arm-linux-gnueabihf cpp-arm-linux-gnueabihf g++ g++-14 216s g++-14-arm-linux-gnueabihf g++-arm-linux-gnueabihf gcc gcc-14 216s gcc-14-arm-linux-gnueabihf gcc-arm-linux-gnueabihf iverilog libasan8 216s libc-dev-bin libc6-dev libcc1-0 libcrypt-dev libffi-dev libgcc-14-dev 216s libgomp1 libisl23 libmpc3 libncurses-dev libpkgconf3 libreadline-dev 216s libstdc++-14-dev libtcl8.6 libubsan1 linux-libc-dev pkg-config pkgconf 216s pkgconf-bin python3-click rpcsvc-proto tcl tcl-dev tcl8.6 tcl8.6-dev yosys 216s yosys-abc yosys-dev zlib1g-dev 217s 0 upgraded, 43 newly installed, 0 to remove and 0 not upgraded. 217s Need to get 64.1 MB of archives. 217s After this operation, 184 MB of additional disk space will be used. 217s Get:1 http://ftpmaster.internal/ubuntu plucky/main armhf libisl23 armhf 0.27-1 [546 kB] 217s Get:2 http://ftpmaster.internal/ubuntu plucky/main armhf libmpc3 armhf 1.3.1-1build2 [47.1 kB] 217s Get:3 http://ftpmaster.internal/ubuntu plucky/main armhf cpp-14-arm-linux-gnueabihf armhf 14.2.0-17ubuntu3 [9220 kB] 229s Get:4 http://ftpmaster.internal/ubuntu plucky/main armhf cpp-14 armhf 14.2.0-17ubuntu3 [1030 B] 229s Get:5 http://ftpmaster.internal/ubuntu plucky/main armhf cpp-arm-linux-gnueabihf armhf 4:14.2.0-1ubuntu1 [5578 B] 229s Get:6 http://ftpmaster.internal/ubuntu plucky/main armhf cpp armhf 4:14.2.0-1ubuntu1 [22.4 kB] 229s Get:7 http://ftpmaster.internal/ubuntu plucky/main armhf libcc1-0 armhf 15-20250222-0ubuntu1 [38.9 kB] 229s Get:8 http://ftpmaster.internal/ubuntu plucky/main armhf libgomp1 armhf 15-20250222-0ubuntu1 [128 kB] 230s Get:9 http://ftpmaster.internal/ubuntu plucky/main armhf libasan8 armhf 15-20250222-0ubuntu1 [2955 kB] 233s Get:10 http://ftpmaster.internal/ubuntu plucky/main armhf libubsan1 armhf 15-20250222-0ubuntu1 [1191 kB] 235s Get:11 http://ftpmaster.internal/ubuntu plucky/main armhf libgcc-14-dev armhf 14.2.0-17ubuntu3 [897 kB] 236s Get:12 http://ftpmaster.internal/ubuntu plucky/main armhf gcc-14-arm-linux-gnueabihf armhf 14.2.0-17ubuntu3 [18.0 MB] 259s Get:13 http://ftpmaster.internal/ubuntu plucky/main armhf gcc-14 armhf 14.2.0-17ubuntu3 [506 kB] 259s Get:14 http://ftpmaster.internal/ubuntu plucky/main armhf gcc-arm-linux-gnueabihf armhf 4:14.2.0-1ubuntu1 [1218 B] 259s Get:15 http://ftpmaster.internal/ubuntu plucky/main armhf gcc armhf 4:14.2.0-1ubuntu1 [5004 B] 259s Get:16 http://ftpmaster.internal/ubuntu plucky-proposed/main armhf libc-dev-bin armhf 2.41-1ubuntu2 [23.0 kB] 259s Get:17 http://ftpmaster.internal/ubuntu plucky/main armhf linux-libc-dev armhf 6.14.0-10.10 [1683 kB] 261s Get:18 http://ftpmaster.internal/ubuntu plucky/main armhf libcrypt-dev armhf 1:4.4.38-1 [120 kB] 261s Get:19 http://ftpmaster.internal/ubuntu plucky/main armhf rpcsvc-proto armhf 1.4.2-0ubuntu7 [62.2 kB] 262s Get:20 http://ftpmaster.internal/ubuntu plucky-proposed/main armhf libc6-dev armhf 2.41-1ubuntu2 [1396 kB] 263s Get:21 http://ftpmaster.internal/ubuntu plucky/main armhf libstdc++-14-dev armhf 14.2.0-17ubuntu3 [2573 kB] 266s Get:22 http://ftpmaster.internal/ubuntu plucky/main armhf g++-14-arm-linux-gnueabihf armhf 14.2.0-17ubuntu3 [10.5 MB] 277s Get:23 http://ftpmaster.internal/ubuntu plucky/main armhf g++-14 armhf 14.2.0-17ubuntu3 [21.8 kB] 277s Get:24 http://ftpmaster.internal/ubuntu plucky/main armhf g++-arm-linux-gnueabihf armhf 4:14.2.0-1ubuntu1 [966 B] 277s Get:25 http://ftpmaster.internal/ubuntu plucky/main armhf g++ armhf 4:14.2.0-1ubuntu1 [1084 B] 277s Get:26 http://ftpmaster.internal/ubuntu plucky/universe armhf iverilog armhf 12.0-2build2 [2047 kB] 279s Get:27 http://ftpmaster.internal/ubuntu plucky/main armhf libncurses-dev armhf 6.5+20250216-2 [345 kB] 279s Get:28 http://ftpmaster.internal/ubuntu plucky/main armhf libpkgconf3 armhf 1.8.1-4 [26.6 kB] 279s Get:29 http://ftpmaster.internal/ubuntu plucky/main armhf libreadline-dev armhf 8.2-6 [153 kB] 279s Get:30 http://ftpmaster.internal/ubuntu plucky/main armhf libtcl8.6 armhf 8.6.16+dfsg-1 [909 kB] 280s Get:31 http://ftpmaster.internal/ubuntu plucky/main armhf pkgconf-bin armhf 1.8.1-4 [21.2 kB] 280s Get:32 http://ftpmaster.internal/ubuntu plucky/main armhf pkgconf armhf 1.8.1-4 [16.8 kB] 280s Get:33 http://ftpmaster.internal/ubuntu plucky/main armhf pkg-config armhf 1.8.1-4 [7362 B] 280s Get:34 http://ftpmaster.internal/ubuntu plucky/main armhf python3-click all 8.2.0+0.really.8.1.8-1 [80.0 kB] 280s Get:35 http://ftpmaster.internal/ubuntu plucky/main armhf tcl8.6 armhf 8.6.16+dfsg-1 [14.6 kB] 280s Get:36 http://ftpmaster.internal/ubuntu plucky/main armhf tcl armhf 8.6.14build1 [4124 B] 280s Get:37 http://ftpmaster.internal/ubuntu plucky/main armhf zlib1g-dev armhf 1:1.3.dfsg+really1.3.1-1ubuntu1 [880 kB] 281s Get:38 http://ftpmaster.internal/ubuntu plucky/main armhf tcl8.6-dev armhf 8.6.16+dfsg-1 [933 kB] 282s Get:39 http://ftpmaster.internal/ubuntu plucky/main armhf tcl-dev armhf 8.6.14build1 [5772 B] 282s Get:40 http://ftpmaster.internal/ubuntu plucky/universe armhf yosys-abc armhf 0.33-5build2 [5336 kB] 289s Get:41 http://ftpmaster.internal/ubuntu plucky/universe armhf yosys armhf 0.33-5build2 [3225 kB] 292s Get:42 http://ftpmaster.internal/ubuntu plucky/main armhf libffi-dev armhf 3.4.7-1 [57.2 kB] 293s Get:43 http://ftpmaster.internal/ubuntu plucky/universe armhf yosys-dev armhf 0.33-5build2 [88.4 kB] 293s Fetched 64.1 MB in 1min 16s (840 kB/s) 293s Selecting previously unselected package libisl23:armhf. 293s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 64655 files and directories currently installed.) 293s Preparing to unpack .../00-libisl23_0.27-1_armhf.deb ... 293s Unpacking libisl23:armhf (0.27-1) ... 293s Selecting previously unselected package libmpc3:armhf. 293s Preparing to unpack .../01-libmpc3_1.3.1-1build2_armhf.deb ... 293s Unpacking libmpc3:armhf (1.3.1-1build2) ... 293s Selecting previously unselected package cpp-14-arm-linux-gnueabihf. 293s Preparing to unpack .../02-cpp-14-arm-linux-gnueabihf_14.2.0-17ubuntu3_armhf.deb ... 293s Unpacking cpp-14-arm-linux-gnueabihf (14.2.0-17ubuntu3) ... 293s Selecting previously unselected package cpp-14. 293s Preparing to unpack .../03-cpp-14_14.2.0-17ubuntu3_armhf.deb ... 293s Unpacking cpp-14 (14.2.0-17ubuntu3) ... 293s Selecting previously unselected package cpp-arm-linux-gnueabihf. 293s Preparing to unpack .../04-cpp-arm-linux-gnueabihf_4%3a14.2.0-1ubuntu1_armhf.deb ... 293s Unpacking cpp-arm-linux-gnueabihf (4:14.2.0-1ubuntu1) ... 293s Selecting previously unselected package cpp. 293s Preparing to unpack .../05-cpp_4%3a14.2.0-1ubuntu1_armhf.deb ... 294s Unpacking cpp (4:14.2.0-1ubuntu1) ... 294s Selecting previously unselected package libcc1-0:armhf. 294s Preparing to unpack .../06-libcc1-0_15-20250222-0ubuntu1_armhf.deb ... 294s Unpacking libcc1-0:armhf (15-20250222-0ubuntu1) ... 294s Selecting previously unselected package libgomp1:armhf. 294s Preparing to unpack .../07-libgomp1_15-20250222-0ubuntu1_armhf.deb ... 294s Unpacking libgomp1:armhf (15-20250222-0ubuntu1) ... 294s Selecting previously unselected package libasan8:armhf. 294s Preparing to unpack .../08-libasan8_15-20250222-0ubuntu1_armhf.deb ... 294s Unpacking libasan8:armhf (15-20250222-0ubuntu1) ... 294s Selecting previously unselected package libubsan1:armhf. 294s Preparing to unpack .../09-libubsan1_15-20250222-0ubuntu1_armhf.deb ... 294s Unpacking libubsan1:armhf (15-20250222-0ubuntu1) ... 294s Selecting previously unselected package libgcc-14-dev:armhf. 294s Preparing to unpack .../10-libgcc-14-dev_14.2.0-17ubuntu3_armhf.deb ... 294s Unpacking libgcc-14-dev:armhf (14.2.0-17ubuntu3) ... 294s Selecting previously unselected package gcc-14-arm-linux-gnueabihf. 294s Preparing to unpack .../11-gcc-14-arm-linux-gnueabihf_14.2.0-17ubuntu3_armhf.deb ... 294s Unpacking gcc-14-arm-linux-gnueabihf (14.2.0-17ubuntu3) ... 294s Selecting previously unselected package gcc-14. 294s Preparing to unpack .../12-gcc-14_14.2.0-17ubuntu3_armhf.deb ... 294s Unpacking gcc-14 (14.2.0-17ubuntu3) ... 294s Selecting previously unselected package gcc-arm-linux-gnueabihf. 294s Preparing to unpack .../13-gcc-arm-linux-gnueabihf_4%3a14.2.0-1ubuntu1_armhf.deb ... 294s Unpacking gcc-arm-linux-gnueabihf (4:14.2.0-1ubuntu1) ... 294s Selecting previously unselected package gcc. 294s Preparing to unpack .../14-gcc_4%3a14.2.0-1ubuntu1_armhf.deb ... 294s Unpacking gcc (4:14.2.0-1ubuntu1) ... 294s Selecting previously unselected package libc-dev-bin. 294s Preparing to unpack .../15-libc-dev-bin_2.41-1ubuntu2_armhf.deb ... 294s Unpacking libc-dev-bin (2.41-1ubuntu2) ... 294s Selecting previously unselected package linux-libc-dev:armhf. 294s Preparing to unpack .../16-linux-libc-dev_6.14.0-10.10_armhf.deb ... 294s Unpacking linux-libc-dev:armhf (6.14.0-10.10) ... 295s Selecting previously unselected package libcrypt-dev:armhf. 295s Preparing to unpack .../17-libcrypt-dev_1%3a4.4.38-1_armhf.deb ... 295s Unpacking libcrypt-dev:armhf (1:4.4.38-1) ... 295s Selecting previously unselected package rpcsvc-proto. 295s Preparing to unpack .../18-rpcsvc-proto_1.4.2-0ubuntu7_armhf.deb ... 295s Unpacking rpcsvc-proto (1.4.2-0ubuntu7) ... 295s Selecting previously unselected package libc6-dev:armhf. 295s Preparing to unpack .../19-libc6-dev_2.41-1ubuntu2_armhf.deb ... 295s Unpacking libc6-dev:armhf (2.41-1ubuntu2) ... 295s Selecting previously unselected package libstdc++-14-dev:armhf. 295s Preparing to unpack .../20-libstdc++-14-dev_14.2.0-17ubuntu3_armhf.deb ... 295s Unpacking libstdc++-14-dev:armhf (14.2.0-17ubuntu3) ... 295s Selecting previously unselected package g++-14-arm-linux-gnueabihf. 295s Preparing to unpack .../21-g++-14-arm-linux-gnueabihf_14.2.0-17ubuntu3_armhf.deb ... 295s Unpacking g++-14-arm-linux-gnueabihf (14.2.0-17ubuntu3) ... 295s Selecting previously unselected package g++-14. 295s Preparing to unpack .../22-g++-14_14.2.0-17ubuntu3_armhf.deb ... 295s Unpacking g++-14 (14.2.0-17ubuntu3) ... 295s Selecting previously unselected package g++-arm-linux-gnueabihf. 295s Preparing to unpack .../23-g++-arm-linux-gnueabihf_4%3a14.2.0-1ubuntu1_armhf.deb ... 295s Unpacking g++-arm-linux-gnueabihf (4:14.2.0-1ubuntu1) ... 295s Selecting previously unselected package g++. 295s Preparing to unpack .../24-g++_4%3a14.2.0-1ubuntu1_armhf.deb ... 295s Unpacking g++ (4:14.2.0-1ubuntu1) ... 295s Selecting previously unselected package iverilog. 295s Preparing to unpack .../25-iverilog_12.0-2build2_armhf.deb ... 295s Unpacking iverilog (12.0-2build2) ... 295s Selecting previously unselected package libncurses-dev:armhf. 295s Preparing to unpack .../26-libncurses-dev_6.5+20250216-2_armhf.deb ... 295s Unpacking libncurses-dev:armhf (6.5+20250216-2) ... 295s Selecting previously unselected package libpkgconf3:armhf. 295s Preparing to unpack .../27-libpkgconf3_1.8.1-4_armhf.deb ... 295s Unpacking libpkgconf3:armhf (1.8.1-4) ... 295s Selecting previously unselected package libreadline-dev:armhf. 295s Preparing to unpack .../28-libreadline-dev_8.2-6_armhf.deb ... 295s Unpacking libreadline-dev:armhf (8.2-6) ... 295s Selecting previously unselected package libtcl8.6:armhf. 295s Preparing to unpack .../29-libtcl8.6_8.6.16+dfsg-1_armhf.deb ... 295s Unpacking libtcl8.6:armhf (8.6.16+dfsg-1) ... 296s Selecting previously unselected package pkgconf-bin. 296s Preparing to unpack .../30-pkgconf-bin_1.8.1-4_armhf.deb ... 296s Unpacking pkgconf-bin (1.8.1-4) ... 296s Selecting previously unselected package pkgconf:armhf. 296s Preparing to unpack .../31-pkgconf_1.8.1-4_armhf.deb ... 296s Unpacking pkgconf:armhf (1.8.1-4) ... 296s Selecting previously unselected package pkg-config:armhf. 296s Preparing to unpack .../32-pkg-config_1.8.1-4_armhf.deb ... 296s Unpacking pkg-config:armhf (1.8.1-4) ... 296s Selecting previously unselected package python3-click. 296s Preparing to unpack .../33-python3-click_8.2.0+0.really.8.1.8-1_all.deb ... 296s Unpacking python3-click (8.2.0+0.really.8.1.8-1) ... 296s Selecting previously unselected package tcl8.6. 296s Preparing to unpack .../34-tcl8.6_8.6.16+dfsg-1_armhf.deb ... 296s Unpacking tcl8.6 (8.6.16+dfsg-1) ... 296s Selecting previously unselected package tcl. 296s Preparing to unpack .../35-tcl_8.6.14build1_armhf.deb ... 296s Unpacking tcl (8.6.14build1) ... 296s Selecting previously unselected package zlib1g-dev:armhf. 296s Preparing to unpack .../36-zlib1g-dev_1%3a1.3.dfsg+really1.3.1-1ubuntu1_armhf.deb ... 296s Unpacking zlib1g-dev:armhf (1:1.3.dfsg+really1.3.1-1ubuntu1) ... 296s Selecting previously unselected package tcl8.6-dev:armhf. 296s Preparing to unpack .../37-tcl8.6-dev_8.6.16+dfsg-1_armhf.deb ... 296s Unpacking tcl8.6-dev:armhf (8.6.16+dfsg-1) ... 296s Selecting previously unselected package tcl-dev:armhf. 296s Preparing to unpack .../38-tcl-dev_8.6.14build1_armhf.deb ... 296s Unpacking tcl-dev:armhf (8.6.14build1) ... 296s Selecting previously unselected package yosys-abc. 296s Preparing to unpack .../39-yosys-abc_0.33-5build2_armhf.deb ... 296s Unpacking yosys-abc (0.33-5build2) ... 296s Selecting previously unselected package yosys. 296s Preparing to unpack .../40-yosys_0.33-5build2_armhf.deb ... 296s Unpacking yosys (0.33-5build2) ... 296s Selecting previously unselected package libffi-dev:armhf. 296s Preparing to unpack .../41-libffi-dev_3.4.7-1_armhf.deb ... 296s Unpacking libffi-dev:armhf (3.4.7-1) ... 296s Selecting previously unselected package yosys-dev. 296s Preparing to unpack .../42-yosys-dev_0.33-5build2_armhf.deb ... 296s Unpacking yosys-dev (0.33-5build2) ... 296s Setting up linux-libc-dev:armhf (6.14.0-10.10) ... 296s Setting up yosys-abc (0.33-5build2) ... 296s Setting up libgomp1:armhf (15-20250222-0ubuntu1) ... 296s Setting up python3-click (8.2.0+0.really.8.1.8-1) ... 296s Setting up libffi-dev:armhf (3.4.7-1) ... 296s Setting up iverilog (12.0-2build2) ... 296s Setting up libpkgconf3:armhf (1.8.1-4) ... 296s Setting up rpcsvc-proto (1.4.2-0ubuntu7) ... 296s Setting up libmpc3:armhf (1.3.1-1build2) ... 296s Setting up libtcl8.6:armhf (8.6.16+dfsg-1) ... 296s Setting up pkgconf-bin (1.8.1-4) ... 296s Setting up libubsan1:armhf (15-20250222-0ubuntu1) ... 296s Setting up libcrypt-dev:armhf (1:4.4.38-1) ... 296s Setting up libasan8:armhf (15-20250222-0ubuntu1) ... 296s Setting up libgcc-14-dev:armhf (14.2.0-17ubuntu3) ... 296s Setting up libisl23:armhf (0.27-1) ... 296s Setting up libc-dev-bin (2.41-1ubuntu2) ... 296s Setting up libcc1-0:armhf (15-20250222-0ubuntu1) ... 296s Setting up cpp-14-arm-linux-gnueabihf (14.2.0-17ubuntu3) ... 296s Setting up tcl8.6 (8.6.16+dfsg-1) ... 296s Setting up yosys (0.33-5build2) ... 296s Setting up gcc-14-arm-linux-gnueabihf (14.2.0-17ubuntu3) ... 296s Setting up pkgconf:armhf (1.8.1-4) ... 296s Setting up pkg-config:armhf (1.8.1-4) ... 296s Setting up cpp-14 (14.2.0-17ubuntu3) ... 296s Setting up tcl (8.6.14build1) ... 296s Setting up libc6-dev:armhf (2.41-1ubuntu2) ... 296s Setting up libstdc++-14-dev:armhf (14.2.0-17ubuntu3) ... 296s Setting up cpp-arm-linux-gnueabihf (4:14.2.0-1ubuntu1) ... 296s Setting up gcc-arm-linux-gnueabihf (4:14.2.0-1ubuntu1) ... 296s Setting up g++-14-arm-linux-gnueabihf (14.2.0-17ubuntu3) ... 296s Setting up libncurses-dev:armhf (6.5+20250216-2) ... 296s Setting up libreadline-dev:armhf (8.2-6) ... 296s Setting up gcc-14 (14.2.0-17ubuntu3) ... 297s Setting up zlib1g-dev:armhf (1:1.3.dfsg+really1.3.1-1ubuntu1) ... 297s Setting up cpp (4:14.2.0-1ubuntu1) ... 297s Setting up g++-14 (14.2.0-17ubuntu3) ... 297s Setting up g++-arm-linux-gnueabihf (4:14.2.0-1ubuntu1) ... 297s Setting up tcl8.6-dev:armhf (8.6.16+dfsg-1) ... 297s Setting up gcc (4:14.2.0-1ubuntu1) ... 297s Setting up tcl-dev:armhf (8.6.14build1) ... 297s Setting up g++ (4:14.2.0-1ubuntu1) ... 297s update-alternatives: using /usr/bin/g++ to provide /usr/bin/c++ (c++) in auto mode 297s Setting up yosys-dev (0.33-5build2) ... 297s Processing triggers for man-db (2.13.0-1) ... 297s Processing triggers for install-info (7.1.1-1) ... 297s Processing triggers for libc-bin (2.41-1ubuntu2) ... 313s autopkgtest [18:33:29]: test yosys-testsuite: [----------------------- 314s + [ 1 -ge 1 ] 314s + testdir=. 314s + shift 314s + mkdir -p . 314s + cd . 314s + ln -sf /usr/bin/yosys . 314s + ln -sf /usr/bin/yosys-abc . 314s + ln -sf /usr/bin/yosys-config . 314s + sed -i s/^test:.*/test: $(EXTRA_TARGETS)/ Makefile 314s + make test CONFIG=gcc ABCPULL=0 314s mkdir -p share/include/kernel/ 314s cp "./"/kernel/yosys.h share/include/kernel/yosys.h 314s mkdir -p share/include/kernel/ 314s cp "./"/kernel/hashlib.h share/include/kernel/hashlib.h 314s mkdir -p share/include/kernel/ 314s cp "./"/kernel/log.h share/include/kernel/log.h 314s mkdir -p share/include/kernel/ 314s cp "./"/kernel/rtlil.h share/include/kernel/rtlil.h 314s mkdir -p share/include/kernel/ 314s cp "./"/kernel/binding.h share/include/kernel/binding.h 314s mkdir -p share/include/kernel/ 314s cp "./"/kernel/register.h share/include/kernel/register.h 314s mkdir -p share/include/kernel/ 314s cp "./"/kernel/cellaigs.h share/include/kernel/cellaigs.h 314s mkdir -p share/include/kernel/ 314s cp "./"/kernel/celltypes.h share/include/kernel/celltypes.h 314s mkdir -p share/include/kernel/ 314s cp "./"/kernel/celledges.h share/include/kernel/celledges.h 314s mkdir -p share/include/kernel/ 314s cp "./"/kernel/consteval.h share/include/kernel/consteval.h 314s mkdir -p share/include/kernel/ 314s cp "./"/kernel/constids.inc share/include/kernel/constids.inc 314s mkdir -p share/include/kernel/ 314s cp "./"/kernel/sigtools.h share/include/kernel/sigtools.h 314s mkdir -p share/include/kernel/ 314s cp "./"/kernel/modtools.h share/include/kernel/modtools.h 314s mkdir -p share/include/kernel/ 314s cp "./"/kernel/macc.h share/include/kernel/macc.h 314s mkdir -p share/include/kernel/ 314s cp "./"/kernel/utils.h share/include/kernel/utils.h 314s mkdir -p share/include/kernel/ 314s cp "./"/kernel/satgen.h share/include/kernel/satgen.h 314s mkdir -p share/include/kernel/ 314s cp "./"/kernel/qcsat.h share/include/kernel/qcsat.h 314s mkdir -p share/include/kernel/ 314s cp "./"/kernel/ff.h share/include/kernel/ff.h 314s mkdir -p share/include/kernel/ 314s cp "./"/kernel/ffinit.h share/include/kernel/ffinit.h 314s mkdir -p share/include/kernel/ 314s cp "./"/kernel/fstdata.h share/include/kernel/fstdata.h 314s mkdir -p share/include/kernel/ 314s cp "./"/kernel/mem.h share/include/kernel/mem.h 314s mkdir -p share/include/kernel/ 314s cp "./"/kernel/yw.h share/include/kernel/yw.h 314s mkdir -p share/include/kernel/ 314s cp "./"/kernel/json.h share/include/kernel/json.h 314s mkdir -p share/include/libs/ezsat/ 314s cp "./"/libs/ezsat/ezsat.h share/include/libs/ezsat/ezsat.h 314s mkdir -p share/include/libs/ezsat/ 314s cp "./"/libs/ezsat/ezminisat.h share/include/libs/ezsat/ezminisat.h 314s mkdir -p share/include/libs/fst/ 314s cp "./"/libs/fst/fstapi.h share/include/libs/fst/fstapi.h 314s mkdir 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"./"/backends/cxxrtl/cxxrtl_vcd.h share/include/backends/cxxrtl/cxxrtl_vcd.h 314s mkdir -p share/include/backends/cxxrtl/ 314s cp "./"/backends/cxxrtl/cxxrtl_capi.cc share/include/backends/cxxrtl/cxxrtl_capi.cc 314s mkdir -p share/include/backends/cxxrtl/ 314s cp "./"/backends/cxxrtl/cxxrtl_capi.h share/include/backends/cxxrtl/cxxrtl_capi.h 314s mkdir -p share/include/backends/cxxrtl/ 314s cp "./"/backends/cxxrtl/cxxrtl_vcd_capi.cc share/include/backends/cxxrtl/cxxrtl_vcd_capi.cc 314s mkdir -p share/include/backends/cxxrtl/ 314s cp "./"/backends/cxxrtl/cxxrtl_vcd_capi.h share/include/backends/cxxrtl/cxxrtl_vcd_capi.h 314s mkdir -p share/python3 314s cp "./"/backends/smt2/smtio.py share/python3/smtio.py 314s mkdir -p share/python3 314s cp "./"/backends/smt2/ywio.py share/python3/ywio.py 314s mkdir -p share/achronix/speedster22i/ 314s cp "./"/techlibs/achronix/speedster22i/cells_sim.v share/achronix/speedster22i/cells_sim.v 314s mkdir -p share/achronix/speedster22i/ 314s cp "./"/techlibs/achronix/speedster22i/cells_map.v share/achronix/speedster22i/cells_map.v 314s mkdir -p share/anlogic 314s cp "./"/techlibs/anlogic/cells_map.v share/anlogic/cells_map.v 314s mkdir -p share/anlogic 314s cp "./"/techlibs/anlogic/arith_map.v share/anlogic/arith_map.v 314s mkdir -p share/anlogic 314s cp "./"/techlibs/anlogic/cells_sim.v share/anlogic/cells_sim.v 314s mkdir -p share/anlogic 314s cp "./"/techlibs/anlogic/eagle_bb.v share/anlogic/eagle_bb.v 314s mkdir -p share/anlogic 314s cp "./"/techlibs/anlogic/lutrams.txt share/anlogic/lutrams.txt 314s mkdir -p share/anlogic 314s cp "./"/techlibs/anlogic/lutrams_map.v share/anlogic/lutrams_map.v 314s mkdir -p share/anlogic 314s cp "./"/techlibs/anlogic/brams.txt share/anlogic/brams.txt 314s mkdir -p share/anlogic 314s cp "./"/techlibs/anlogic/brams_map.v share/anlogic/brams_map.v 314s mkdir -p share 314s cp "./"/techlibs/common/simlib.v share/simlib.v 314s mkdir -p share 314s cp "./"/techlibs/common/simcells.v share/simcells.v 314s mkdir -p share 314s cp "./"/techlibs/common/techmap.v share/techmap.v 314s mkdir -p share 314s cp "./"/techlibs/common/smtmap.v share/smtmap.v 314s mkdir -p share 314s cp "./"/techlibs/common/pmux2mux.v share/pmux2mux.v 314s mkdir -p share 314s cp "./"/techlibs/common/adff2dff.v share/adff2dff.v 314s mkdir -p share 314s cp "./"/techlibs/common/dff2ff.v share/dff2ff.v 314s mkdir -p share 314s cp "./"/techlibs/common/gate2lut.v share/gate2lut.v 314s mkdir -p share 314s cp "./"/techlibs/common/cmp2lut.v share/cmp2lut.v 314s mkdir -p share 314s cp "./"/techlibs/common/cells.lib share/cells.lib 314s mkdir -p share 314s cp "./"/techlibs/common/mul2dsp.v share/mul2dsp.v 314s mkdir -p share 314s cp "./"/techlibs/common/abc9_model.v share/abc9_model.v 314s mkdir -p share 314s cp "./"/techlibs/common/abc9_map.v share/abc9_map.v 314s mkdir -p share 314s cp "./"/techlibs/common/abc9_unmap.v share/abc9_unmap.v 314s mkdir -p share 314s cp "./"/techlibs/common/cmp2lcu.v share/cmp2lcu.v 314s mkdir -p share/coolrunner2 314s cp "./"/techlibs/coolrunner2/cells_latch.v share/coolrunner2/cells_latch.v 314s mkdir -p share/coolrunner2 314s cp "./"/techlibs/coolrunner2/cells_sim.v share/coolrunner2/cells_sim.v 314s mkdir -p share/coolrunner2 314s cp "./"/techlibs/coolrunner2/cells_counter_map.v share/coolrunner2/cells_counter_map.v 314s mkdir -p share/coolrunner2 314s cp "./"/techlibs/coolrunner2/tff_extract.v share/coolrunner2/tff_extract.v 314s mkdir -p share/coolrunner2 314s cp "./"/techlibs/coolrunner2/xc2_dff.lib share/coolrunner2/xc2_dff.lib 314s mkdir -p share/ecp5 314s cp "./"/techlibs/ecp5/cells_ff.vh share/ecp5/cells_ff.vh 314s mkdir -p share/ecp5 314s cp "./"/techlibs/ecp5/cells_io.vh share/ecp5/cells_io.vh 314s mkdir -p share/ecp5 314s cp "./"/techlibs/ecp5/cells_map.v share/ecp5/cells_map.v 314s mkdir -p share/ecp5 314s cp "./"/techlibs/ecp5/cells_sim.v share/ecp5/cells_sim.v 314s mkdir -p share/ecp5 314s cp "./"/techlibs/ecp5/cells_bb.v share/ecp5/cells_bb.v 314s mkdir -p share/ecp5 314s cp "./"/techlibs/ecp5/lutrams_map.v share/ecp5/lutrams_map.v 314s mkdir -p share/ecp5 314s cp "./"/techlibs/ecp5/lutrams.txt share/ecp5/lutrams.txt 314s mkdir -p share/ecp5 314s cp "./"/techlibs/ecp5/brams_map.v share/ecp5/brams_map.v 314s mkdir -p share/ecp5 314s cp "./"/techlibs/ecp5/brams.txt share/ecp5/brams.txt 314s mkdir -p share/ecp5 314s cp "./"/techlibs/ecp5/arith_map.v share/ecp5/arith_map.v 314s mkdir -p share/ecp5 314s cp "./"/techlibs/ecp5/latches_map.v share/ecp5/latches_map.v 314s mkdir -p share/ecp5 314s cp "./"/techlibs/ecp5/dsp_map.v share/ecp5/dsp_map.v 314s mkdir -p share/efinix 314s cp "./"/techlibs/efinix/cells_map.v share/efinix/cells_map.v 314s mkdir -p share/efinix 314s cp "./"/techlibs/efinix/arith_map.v share/efinix/arith_map.v 314s mkdir -p share/efinix 314s cp "./"/techlibs/efinix/cells_sim.v share/efinix/cells_sim.v 314s mkdir -p share/efinix 314s cp "./"/techlibs/efinix/brams_map.v share/efinix/brams_map.v 314s mkdir -p share/efinix 314s cp "./"/techlibs/efinix/gbuf_map.v share/efinix/gbuf_map.v 314s mkdir -p share/efinix 314s cp "./"/techlibs/efinix/brams.txt share/efinix/brams.txt 314s mkdir -p share/fabulous 314s cp "./"/techlibs/fabulous/cells_map.v share/fabulous/cells_map.v 314s mkdir -p share/fabulous 314s cp "./"/techlibs/fabulous/prims.v share/fabulous/prims.v 314s mkdir -p share/fabulous 314s cp "./"/techlibs/fabulous/latches_map.v share/fabulous/latches_map.v 314s mkdir -p share/fabulous 314s cp "./"/techlibs/fabulous/ff_map.v share/fabulous/ff_map.v 314s mkdir -p share/fabulous 314s cp "./"/techlibs/fabulous/ram_regfile.txt share/fabulous/ram_regfile.txt 314s mkdir -p share/fabulous 314s cp "./"/techlibs/fabulous/regfile_map.v share/fabulous/regfile_map.v 314s mkdir -p share/fabulous 314s cp "./"/techlibs/fabulous/io_map.v share/fabulous/io_map.v 314s mkdir -p share/fabulous 314s cp "./"/techlibs/fabulous/arith_map.v share/fabulous/arith_map.v 314s mkdir -p share/gatemate 314s cp "./"/techlibs/gatemate/reg_map.v share/gatemate/reg_map.v 314s mkdir -p share/gatemate 314s cp "./"/techlibs/gatemate/mux_map.v share/gatemate/mux_map.v 314s mkdir -p share/gatemate 314s cp "./"/techlibs/gatemate/lut_map.v share/gatemate/lut_map.v 315s mkdir -p share/gatemate 315s cp "./"/techlibs/gatemate/mul_map.v share/gatemate/mul_map.v 315s mkdir -p share/gatemate 315s cp "./"/techlibs/gatemate/arith_map.v share/gatemate/arith_map.v 315s mkdir -p share/gatemate 315s cp "./"/techlibs/gatemate/cells_sim.v share/gatemate/cells_sim.v 315s mkdir -p share/gatemate 315s cp "./"/techlibs/gatemate/cells_bb.v share/gatemate/cells_bb.v 315s mkdir -p share/gatemate 315s cp "./"/techlibs/gatemate/brams_map.v share/gatemate/brams_map.v 315s mkdir -p share/gatemate 315s cp "./"/techlibs/gatemate/brams.txt share/gatemate/brams.txt 315s mkdir -p share/gatemate 315s cp "./"/techlibs/gatemate/brams_init_20.vh share/gatemate/brams_init_20.vh 315s mkdir -p share/gatemate 315s cp "./"/techlibs/gatemate/brams_init_40.vh share/gatemate/brams_init_40.vh 315s mkdir -p share/gatemate 315s cp "./"/techlibs/gatemate/inv_map.v share/gatemate/inv_map.v 315s mkdir -p techlibs/gatemate 315s python3 techlibs/gatemate/make_lut_tree_lib.py 315s touch techlibs/gatemate/lut_tree_lib.mk 315s mkdir -p share/gatemate 315s cp techlibs/gatemate/lut_tree_cells.genlib share/gatemate/lut_tree_cells.genlib 315s mkdir -p share/gatemate 315s cp techlibs/gatemate/lut_tree_map.v share/gatemate/lut_tree_map.v 315s mkdir -p share/gowin 315s cp "./"/techlibs/gowin/cells_map.v share/gowin/cells_map.v 315s mkdir -p share/gowin 315s cp "./"/techlibs/gowin/cells_sim.v share/gowin/cells_sim.v 315s mkdir -p share/gowin 315s cp "./"/techlibs/gowin/cells_xtra.v share/gowin/cells_xtra.v 315s mkdir -p share/gowin 315s cp "./"/techlibs/gowin/arith_map.v share/gowin/arith_map.v 315s mkdir -p share/gowin 315s cp "./"/techlibs/gowin/brams_map.v share/gowin/brams_map.v 315s mkdir -p share/gowin 315s cp "./"/techlibs/gowin/brams.txt share/gowin/brams.txt 315s mkdir -p share/gowin 315s cp "./"/techlibs/gowin/lutrams_map.v share/gowin/lutrams_map.v 315s mkdir -p share/gowin 315s cp "./"/techlibs/gowin/lutrams.txt share/gowin/lutrams.txt 315s mkdir -p share/greenpak4 315s cp "./"/techlibs/greenpak4/cells_blackbox.v share/greenpak4/cells_blackbox.v 315s mkdir -p share/greenpak4 315s cp "./"/techlibs/greenpak4/cells_latch.v share/greenpak4/cells_latch.v 315s mkdir -p share/greenpak4 315s cp "./"/techlibs/greenpak4/cells_map.v share/greenpak4/cells_map.v 315s mkdir -p share/greenpak4 315s cp "./"/techlibs/greenpak4/cells_sim.v share/greenpak4/cells_sim.v 315s mkdir -p share/greenpak4 315s cp "./"/techlibs/greenpak4/cells_sim_ams.v share/greenpak4/cells_sim_ams.v 315s mkdir -p share/greenpak4 315s cp "./"/techlibs/greenpak4/cells_sim_digital.v share/greenpak4/cells_sim_digital.v 315s mkdir -p share/greenpak4 315s cp "./"/techlibs/greenpak4/cells_sim_wip.v share/greenpak4/cells_sim_wip.v 315s mkdir -p share/greenpak4 315s cp "./"/techlibs/greenpak4/gp_dff.lib share/greenpak4/gp_dff.lib 315s mkdir -p share/ice40 315s cp "./"/techlibs/ice40/arith_map.v share/ice40/arith_map.v 315s mkdir -p share/ice40 315s cp "./"/techlibs/ice40/cells_map.v share/ice40/cells_map.v 315s mkdir -p share/ice40 315s cp "./"/techlibs/ice40/ff_map.v share/ice40/ff_map.v 315s mkdir -p share/ice40 315s cp "./"/techlibs/ice40/cells_sim.v share/ice40/cells_sim.v 315s mkdir -p share/ice40 315s cp "./"/techlibs/ice40/latches_map.v share/ice40/latches_map.v 315s mkdir -p share/ice40 315s cp "./"/techlibs/ice40/brams.txt share/ice40/brams.txt 315s mkdir -p share/ice40 315s cp "./"/techlibs/ice40/brams_map.v share/ice40/brams_map.v 315s mkdir -p share/ice40 315s cp "./"/techlibs/ice40/spram.txt share/ice40/spram.txt 315s mkdir -p share/ice40 315s cp "./"/techlibs/ice40/spram_map.v share/ice40/spram_map.v 315s mkdir -p share/ice40 315s cp "./"/techlibs/ice40/dsp_map.v share/ice40/dsp_map.v 315s mkdir -p share/ice40 315s cp "./"/techlibs/ice40/abc9_model.v share/ice40/abc9_model.v 315s mkdir -p share/intel/common 315s cp "./"/techlibs/intel/common/m9k_bb.v share/intel/common/m9k_bb.v 315s mkdir -p share/intel/common 315s cp "./"/techlibs/intel/common/altpll_bb.v share/intel/common/altpll_bb.v 315s mkdir -p share/intel/common 315s cp "./"/techlibs/intel/common/brams_m9k.txt share/intel/common/brams_m9k.txt 315s mkdir -p share/intel/common 315s cp "./"/techlibs/intel/common/brams_map_m9k.v share/intel/common/brams_map_m9k.v 315s mkdir -p share/intel/common 315s cp "./"/techlibs/intel/common/ff_map.v share/intel/common/ff_map.v 315s mkdir -p share/intel/max10 315s cp "./"/techlibs/intel/max10/cells_sim.v share/intel/max10/cells_sim.v 315s mkdir -p share/intel/cyclone10lp 315s cp "./"/techlibs/intel/cyclone10lp/cells_sim.v share/intel/cyclone10lp/cells_sim.v 315s mkdir -p share/intel/cycloneiv 315s cp "./"/techlibs/intel/cycloneiv/cells_sim.v share/intel/cycloneiv/cells_sim.v 315s mkdir -p share/intel/cycloneive 315s cp "./"/techlibs/intel/cycloneive/cells_sim.v share/intel/cycloneive/cells_sim.v 315s mkdir -p share/intel/max10 315s cp "./"/techlibs/intel/max10/cells_map.v share/intel/max10/cells_map.v 315s mkdir -p share/intel/cyclone10lp 315s cp "./"/techlibs/intel/cyclone10lp/cells_map.v share/intel/cyclone10lp/cells_map.v 315s mkdir -p share/intel/cycloneiv 315s cp "./"/techlibs/intel/cycloneiv/cells_map.v share/intel/cycloneiv/cells_map.v 315s mkdir -p share/intel/cycloneive 315s cp "./"/techlibs/intel/cycloneive/cells_map.v share/intel/cycloneive/cells_map.v 315s mkdir -p share/intel_alm/common 315s cp "./"/techlibs/intel_alm/common/abc9_map.v share/intel_alm/common/abc9_map.v 315s mkdir -p share/intel_alm/common 315s cp "./"/techlibs/intel_alm/common/abc9_unmap.v share/intel_alm/common/abc9_unmap.v 315s mkdir -p share/intel_alm/common 315s cp "./"/techlibs/intel_alm/common/abc9_model.v share/intel_alm/common/abc9_model.v 315s mkdir -p share/intel_alm/common 315s cp "./"/techlibs/intel_alm/common/alm_map.v share/intel_alm/common/alm_map.v 315s mkdir -p share/intel_alm/common 315s cp "./"/techlibs/intel_alm/common/alm_sim.v share/intel_alm/common/alm_sim.v 315s mkdir -p share/intel_alm/common 315s cp "./"/techlibs/intel_alm/common/arith_alm_map.v share/intel_alm/common/arith_alm_map.v 315s mkdir -p share/intel_alm/common 315s cp "./"/techlibs/intel_alm/common/dff_map.v share/intel_alm/common/dff_map.v 315s mkdir -p share/intel_alm/common 315s cp "./"/techlibs/intel_alm/common/dff_sim.v share/intel_alm/common/dff_sim.v 315s mkdir -p share/intel_alm/common 315s cp "./"/techlibs/intel_alm/common/dsp_sim.v share/intel_alm/common/dsp_sim.v 315s mkdir -p share/intel_alm/common 315s cp "./"/techlibs/intel_alm/common/dsp_map.v share/intel_alm/common/dsp_map.v 315s mkdir -p share/intel_alm/common 315s cp "./"/techlibs/intel_alm/common/mem_sim.v share/intel_alm/common/mem_sim.v 315s mkdir -p share/intel_alm/common 315s cp "./"/techlibs/intel_alm/common/misc_sim.v share/intel_alm/common/misc_sim.v 315s mkdir -p share/intel_alm/cyclonev 315s cp "./"/techlibs/intel_alm/cyclonev/cells_sim.v share/intel_alm/cyclonev/cells_sim.v 315s mkdir -p share/intel_alm/common 315s cp "./"/techlibs/intel_alm/common/bram_m10k.txt share/intel_alm/common/bram_m10k.txt 315s mkdir -p share/intel_alm/common 315s cp "./"/techlibs/intel_alm/common/bram_m10k_map.v share/intel_alm/common/bram_m10k_map.v 315s mkdir -p share/intel_alm/common 315s cp "./"/techlibs/intel_alm/common/bram_m20k.txt share/intel_alm/common/bram_m20k.txt 315s mkdir -p share/intel_alm/common 315s cp "./"/techlibs/intel_alm/common/bram_m20k_map.v share/intel_alm/common/bram_m20k_map.v 315s mkdir -p share/intel_alm/common 315s cp "./"/techlibs/intel_alm/common/lutram_mlab.txt share/intel_alm/common/lutram_mlab.txt 315s mkdir -p share/intel_alm/common 315s cp "./"/techlibs/intel_alm/common/megafunction_bb.v share/intel_alm/common/megafunction_bb.v 315s mkdir -p share/intel_alm/common 315s cp "./"/techlibs/intel_alm/common/quartus_rename.v share/intel_alm/common/quartus_rename.v 315s mkdir -p share/lattice 315s cp "./"/techlibs/lattice/cells_ff.vh share/lattice/cells_ff.vh 315s mkdir -p share/lattice 315s cp "./"/techlibs/lattice/cells_io.vh share/lattice/cells_io.vh 315s mkdir -p share/lattice 315s cp "./"/techlibs/lattice/cells_map.v share/lattice/cells_map.v 315s mkdir -p share/lattice 315s cp "./"/techlibs/lattice/common_sim.vh share/lattice/common_sim.vh 315s mkdir -p share/lattice 315s cp "./"/techlibs/lattice/ccu2d_sim.vh share/lattice/ccu2d_sim.vh 315s mkdir -p share/lattice 315s cp "./"/techlibs/lattice/ccu2c_sim.vh share/lattice/ccu2c_sim.vh 315s mkdir -p share/lattice 315s cp "./"/techlibs/lattice/cells_sim_ecp5.v share/lattice/cells_sim_ecp5.v 315s mkdir -p share/lattice 315s cp "./"/techlibs/lattice/cells_sim_xo2.v share/lattice/cells_sim_xo2.v 315s mkdir -p share/lattice 315s cp "./"/techlibs/lattice/cells_sim_xo3.v share/lattice/cells_sim_xo3.v 315s mkdir -p share/lattice 315s cp "./"/techlibs/lattice/cells_sim_xo3d.v share/lattice/cells_sim_xo3d.v 315s mkdir -p share/lattice 315s cp "./"/techlibs/lattice/cells_bb_ecp5.v share/lattice/cells_bb_ecp5.v 315s mkdir -p share/lattice 315s cp "./"/techlibs/lattice/cells_bb_xo2.v share/lattice/cells_bb_xo2.v 315s mkdir -p share/lattice 315s cp "./"/techlibs/lattice/cells_bb_xo3.v share/lattice/cells_bb_xo3.v 315s mkdir -p share/lattice 315s cp "./"/techlibs/lattice/cells_bb_xo3d.v share/lattice/cells_bb_xo3d.v 315s mkdir -p share/lattice 315s cp "./"/techlibs/lattice/lutrams_map.v share/lattice/lutrams_map.v 315s mkdir -p share/lattice 315s cp "./"/techlibs/lattice/lutrams.txt share/lattice/lutrams.txt 315s mkdir -p share/lattice 315s cp "./"/techlibs/lattice/brams_map_16kd.v share/lattice/brams_map_16kd.v 315s mkdir -p share/lattice 315s cp "./"/techlibs/lattice/brams_16kd.txt share/lattice/brams_16kd.txt 315s mkdir -p share/lattice 315s cp "./"/techlibs/lattice/brams_map_8kc.v share/lattice/brams_map_8kc.v 315s mkdir -p share/lattice 315s cp "./"/techlibs/lattice/brams_8kc.txt share/lattice/brams_8kc.txt 315s mkdir -p share/lattice 315s cp "./"/techlibs/lattice/arith_map_ccu2c.v share/lattice/arith_map_ccu2c.v 315s mkdir -p share/lattice 315s cp "./"/techlibs/lattice/arith_map_ccu2d.v share/lattice/arith_map_ccu2d.v 315s mkdir -p share/lattice 315s cp "./"/techlibs/lattice/latches_map.v share/lattice/latches_map.v 315s mkdir -p share/lattice 315s cp "./"/techlibs/lattice/dsp_map_18x18.v share/lattice/dsp_map_18x18.v 315s mkdir -p share/nexus 315s cp "./"/techlibs/nexus/cells_map.v share/nexus/cells_map.v 315s mkdir -p share/nexus 315s cp "./"/techlibs/nexus/cells_sim.v share/nexus/cells_sim.v 315s mkdir -p share/nexus 315s cp "./"/techlibs/nexus/parse_init.vh share/nexus/parse_init.vh 315s mkdir -p share/nexus 315s cp "./"/techlibs/nexus/cells_xtra.v share/nexus/cells_xtra.v 315s mkdir -p share/nexus 315s cp "./"/techlibs/nexus/lutrams_map.v share/nexus/lutrams_map.v 315s mkdir -p share/nexus 315s cp "./"/techlibs/nexus/lutrams.txt share/nexus/lutrams.txt 315s mkdir -p share/nexus 315s cp "./"/techlibs/nexus/brams_map.v share/nexus/brams_map.v 315s mkdir -p share/nexus 315s cp "./"/techlibs/nexus/brams.txt share/nexus/brams.txt 315s mkdir -p share/nexus 315s cp "./"/techlibs/nexus/lrams_map.v share/nexus/lrams_map.v 315s mkdir -p share/nexus 315s cp "./"/techlibs/nexus/lrams.txt share/nexus/lrams.txt 315s mkdir -p share/nexus 315s cp "./"/techlibs/nexus/arith_map.v share/nexus/arith_map.v 315s mkdir -p share/nexus 315s cp "./"/techlibs/nexus/latches_map.v share/nexus/latches_map.v 315s mkdir -p share/nexus 315s cp "./"/techlibs/nexus/dsp_map.v share/nexus/dsp_map.v 315s mkdir -p share/quicklogic 315s cp "./"/techlibs/quicklogic/pp3_ffs_map.v share/quicklogic/pp3_ffs_map.v 315s mkdir -p share/quicklogic 315s cp "./"/techlibs/quicklogic/pp3_lut_map.v share/quicklogic/pp3_lut_map.v 315s mkdir -p share/quicklogic 315s cp "./"/techlibs/quicklogic/pp3_latches_map.v share/quicklogic/pp3_latches_map.v 315s mkdir -p share/quicklogic 315s cp "./"/techlibs/quicklogic/pp3_cells_map.v share/quicklogic/pp3_cells_map.v 315s mkdir -p share/quicklogic 315s cp "./"/techlibs/quicklogic/cells_sim.v share/quicklogic/cells_sim.v 315s mkdir -p share/quicklogic 315s cp "./"/techlibs/quicklogic/lut_sim.v share/quicklogic/lut_sim.v 315s mkdir -p share/quicklogic 315s cp "./"/techlibs/quicklogic/pp3_cells_sim.v share/quicklogic/pp3_cells_sim.v 315s mkdir -p share/quicklogic 315s cp "./"/techlibs/quicklogic/abc9_model.v share/quicklogic/abc9_model.v 315s mkdir -p share/quicklogic 315s cp "./"/techlibs/quicklogic/abc9_map.v share/quicklogic/abc9_map.v 315s mkdir -p share/quicklogic 315s cp "./"/techlibs/quicklogic/abc9_unmap.v share/quicklogic/abc9_unmap.v 315s mkdir -p share/sf2 315s cp "./"/techlibs/sf2/arith_map.v share/sf2/arith_map.v 315s mkdir -p share/sf2 315s cp "./"/techlibs/sf2/cells_map.v share/sf2/cells_map.v 315s mkdir -p share/sf2 315s cp "./"/techlibs/sf2/cells_sim.v share/sf2/cells_sim.v 315s mkdir -p share/xilinx 315s cp "./"/techlibs/xilinx/cells_map.v share/xilinx/cells_map.v 315s mkdir -p share/xilinx 315s cp "./"/techlibs/xilinx/cells_sim.v share/xilinx/cells_sim.v 315s mkdir -p share/xilinx 315s cp "./"/techlibs/xilinx/cells_xtra.v share/xilinx/cells_xtra.v 315s mkdir -p share/xilinx 315s cp "./"/techlibs/xilinx/lutrams_xcv.txt share/xilinx/lutrams_xcv.txt 315s mkdir -p share/xilinx 315s cp "./"/techlibs/xilinx/lutrams_xcv_map.v share/xilinx/lutrams_xcv_map.v 315s mkdir -p share/xilinx 315s cp "./"/techlibs/xilinx/lutrams_xc5v.txt share/xilinx/lutrams_xc5v.txt 315s mkdir -p share/xilinx 315s cp "./"/techlibs/xilinx/lutrams_xcu.txt share/xilinx/lutrams_xcu.txt 315s mkdir -p share/xilinx 315s cp "./"/techlibs/xilinx/lutrams_xc5v_map.v share/xilinx/lutrams_xc5v_map.v 315s mkdir -p share/xilinx 315s cp "./"/techlibs/xilinx/brams_xcv.txt share/xilinx/brams_xcv.txt 315s mkdir -p share/xilinx 315s cp "./"/techlibs/xilinx/brams_xcv_map.v share/xilinx/brams_xcv_map.v 315s mkdir -p share/xilinx 315s cp "./"/techlibs/xilinx/brams_defs.vh share/xilinx/brams_defs.vh 315s mkdir -p share/xilinx 315s cp "./"/techlibs/xilinx/brams_xc2v.txt share/xilinx/brams_xc2v.txt 315s mkdir -p share/xilinx 315s cp "./"/techlibs/xilinx/brams_xc2v_map.v share/xilinx/brams_xc2v_map.v 315s mkdir -p share/xilinx 315s cp "./"/techlibs/xilinx/brams_xc3sda.txt share/xilinx/brams_xc3sda.txt 315s mkdir -p share/xilinx 315s cp "./"/techlibs/xilinx/brams_xc3sda_map.v share/xilinx/brams_xc3sda_map.v 315s mkdir -p share/xilinx 315s cp "./"/techlibs/xilinx/brams_xc4v.txt share/xilinx/brams_xc4v.txt 315s mkdir -p share/xilinx 315s cp "./"/techlibs/xilinx/brams_xc4v_map.v share/xilinx/brams_xc4v_map.v 315s mkdir -p share/xilinx 315s cp "./"/techlibs/xilinx/brams_xc5v_map.v share/xilinx/brams_xc5v_map.v 315s mkdir -p share/xilinx 315s cp "./"/techlibs/xilinx/brams_xc6v_map.v share/xilinx/brams_xc6v_map.v 315s mkdir -p share/xilinx 315s cp "./"/techlibs/xilinx/brams_xcu_map.v share/xilinx/brams_xcu_map.v 315s mkdir -p share/xilinx 315s cp "./"/techlibs/xilinx/urams.txt share/xilinx/urams.txt 315s mkdir -p share/xilinx 315s cp "./"/techlibs/xilinx/urams_map.v share/xilinx/urams_map.v 315s mkdir -p share/xilinx 315s cp "./"/techlibs/xilinx/arith_map.v share/xilinx/arith_map.v 315s mkdir -p share/xilinx 315s cp "./"/techlibs/xilinx/ff_map.v share/xilinx/ff_map.v 315s mkdir -p share/xilinx 315s cp "./"/techlibs/xilinx/lut_map.v share/xilinx/lut_map.v 315s mkdir -p share/xilinx 315s cp "./"/techlibs/xilinx/mux_map.v share/xilinx/mux_map.v 315s mkdir -p share/xilinx 315s cp "./"/techlibs/xilinx/xc3s_mult_map.v share/xilinx/xc3s_mult_map.v 315s mkdir -p share/xilinx 315s cp "./"/techlibs/xilinx/xc3sda_dsp_map.v share/xilinx/xc3sda_dsp_map.v 315s mkdir -p share/xilinx 315s cp "./"/techlibs/xilinx/xc6s_dsp_map.v share/xilinx/xc6s_dsp_map.v 315s mkdir -p share/xilinx 315s cp "./"/techlibs/xilinx/xc4v_dsp_map.v share/xilinx/xc4v_dsp_map.v 315s mkdir -p share/xilinx 315s cp "./"/techlibs/xilinx/xc5v_dsp_map.v share/xilinx/xc5v_dsp_map.v 315s mkdir -p share/xilinx 315s cp "./"/techlibs/xilinx/xc7_dsp_map.v share/xilinx/xc7_dsp_map.v 315s mkdir -p share/xilinx 315s cp "./"/techlibs/xilinx/xcu_dsp_map.v share/xilinx/xcu_dsp_map.v 315s mkdir -p share/xilinx 315s cp "./"/techlibs/xilinx/abc9_model.v share/xilinx/abc9_model.v 315s cd tests/simple && bash run-test.sh "" 315s make[1]: Entering directory '/tmp/autopkgtest.eUlrfO/build.1OM/src/tests/simple' 315s + gcc -Wall -o /tmp/autopkgtest.eUlrfO/build.1OM/src/tests/tools/cmp_tbdata /tmp/autopkgtest.eUlrfO/build.1OM/src/tests/tools/cmp_tbdata.c 316s Test: arrays02 -> ok 318s Test: asgn_binop -> ok 319s Test: case_expr_extend -> ok 319s Test: case_expr_query -> ok 319s Test: defvalue -> ok 320s Test: implicit_ports -> ok 320s Test: lesser_size_cast -> ok 320s Test: local_loop_var -> ok 321s Test: macro_arg_spaces -> ok 321s Test: matching_end_labels -> ok 321s Test: memwr_port_connection -> ok 322s Test: unnamed_block_decl -> ok 322s Test: aes_kexp128 -> ok 322s Test: always01 -> ok 323s Test: always02 -> ok 323s Test: always03 -> ok 324s Test: arraycells -> ok 324s Test: arrays01 -> ok 325s Test: attrib01_module -> ok 325s Test: attrib02_port_decl -> ok 326s Test: attrib03_parameter -> ok 326s Test: attrib04_net_var -> ok 327s Test: attrib06_operator_suffix -> ok 327s Test: attrib08_mod_inst -> ok 327s Test: attrib09_case -> ok 328s Test: carryadd -> ok 328s Test: case_expr_const -> ok 328s Test: case_expr_non_const -> ok 338s Test: case_large -> ok 339s Test: const_branch_finish -> ok 339s Test: const_fold_func -> ok 340s Test: const_func_shadow -> ok 343s Test: constmuldivmod -> ok 343s Test: constpower -> ok 345s Test: dff_different_styles -> ok 346s Test: dff_init -> ok 348s Test: dynslice -> ok 349s Test: fiedler-cooley -> ok 349s Test: forgen01 -> ok 350s Test: forgen02 -> ok 350s Test: forloops -> ok 351s Test: fsm -> ok 351s Test: func_block -> ok 352s Test: func_recurse -> ok 353s Test: func_width_scope -> ok 353s Test: genblk_collide -> ok 353s Test: genblk_dive -> ok 353s Test: genblk_order -> ok 353s Test: genblk_port_shadow -> ok 357s Test: generate -> ok 357s Test: graphtest -> ok 357s Test: hierarchy -> ok 358s Test: hierdefparam -> ok 359s Test: i2c_master_tests -> ok 359s Test: ifdef_1 -> ok 359s Test: ifdef_2 -> ok 360s Test: localparam_attr -> ok 360s Test: loop_prefix_case -> ok 360s Test: loop_var_shadow -> ok 361s Test: loops -> ok 361s Test: macro_arg_surrounding_spaces -> ok 361s Test: macros -> ok 363s Test: mem2reg -> ok 364s Test: mem2reg_bounds_tern -> ok 365s Test: mem_arst -> ok 374s Test: memory -> ok 375s Test: module_scope -> ok 375s Test: module_scope_case -> ok 375s Test: module_scope_func -> ok 376s Test: multiplier -> ok 377s Test: muxtree -> ok 377s Test: named_genblk -> ok 379s Test: nested_genblk_resolve -> ok 379s Test: omsp_dbg_uart -> ok 384s Test: operators -> ok 384s Test: param_attr -> ok 385s Test: paramods -> ok 391s Test: partsel -> ok 392s Test: process -> ok 392s Test: realexpr -> ok 393s Test: repwhile -> ok 393s Test: retime -> ok 399s Test: rotate -> ok 400s Test: scopes -> ok 400s Test: signed_full_slice -> ok 400s Test: signedexpr -> ok 403s Test: sincos -> ok 403s Test: specify -> ok 403s Test: string_format -> ok 404s Test: subbytes -> ok 405s Test: task_func -> ok 405s Test: undef_eqx_nex -> ok 406s Test: usb_phy_tests -> ok 407s Test: values -> ok 407s Test: verilog_primitives -> ok 408s Test: vloghammer -> ok 409s Test: wandwor -> ok 410s Test: wreduce -> ok 410s make[1]: Leaving directory '/tmp/autopkgtest.eUlrfO/build.1OM/src/tests/simple' 410s cd tests/simple_abc9 && bash run-test.sh "" 410s ls: cannot access '*.sv': No such file or directory 410s make[1]: Entering directory '/tmp/autopkgtest.eUlrfO/build.1OM/src/tests/simple_abc9' 413s Test: abc9 -> ok 414s Test: aes_kexp128 -> ok 414s Test: always01 -> ok 414s Test: always02 -> ok 414s Test: always03 -> ok 415s Test: arraycells -> ok 415s Test: arrays01 -> ok 415s Test: attrib01_module -> ok 416s Test: attrib02_port_decl -> ok 416s Test: attrib03_parameter -> ok 416s Test: attrib04_net_var -> ok 417s Test: attrib06_operator_suffix -> ok 417s Test: attrib08_mod_inst -> ok 417s Test: attrib09_case -> ok 418s Test: carryadd -> ok 418s Test: case_expr_const -> ok 418s Test: case_expr_non_const -> ok 436s Test: case_large -> ok 437s Test: const_branch_finish -> ok 437s Test: const_fold_func -> ok 438s Test: const_func_shadow -> ok 441s Test: constmuldivmod -> ok 441s Test: constpower -> ok 442s Test: dff_different_styles -> ok 442s Test: dff_init -> ok 452s Test: dynslice -> ok 452s Test: fiedler-cooley -> ok 452s Test: forgen01 -> ok 453s Test: forgen02 -> ok 453s Test: forloops -> ok 453s Test: fsm -> ok 454s Test: func_block -> ok 454s Test: func_recurse -> ok 454s Test: func_width_scope -> ok 455s Test: genblk_collide -> ok 455s Test: genblk_dive -> ok 455s Test: genblk_order -> ok 455s Test: genblk_port_shadow -> ok 458s Test: generate -> ok 458s Test: graphtest -> ok 458s Test: hierarchy -> ok 459s Test: hierdefparam -> ok 460s Test: i2c_master_tests -> ok 460s Test: ifdef_1 -> ok 460s Test: ifdef_2 -> ok 460s Test: localparam_attr -> ok 460s Test: loop_prefix_case -> ok 461s Test: loop_var_shadow -> ok 461s Test: loops -> ok 461s Test: macro_arg_surrounding_spaces -> ok 462s Test: macros -> ok 463s Test: mem2reg -> ok 463s Test: mem2reg_bounds_tern -> ok 464s Test: mem_arst -> ok 469s Test: memory -> ok 469s Test: module_scope -> ok 470s Test: module_scope_case -> ok 470s Test: module_scope_func -> ok 471s Test: multiplier -> ok 471s Test: muxtree -> ok 471s Test: named_genblk -> ok 471s Test: nested_genblk_resolve -> ok 472s Test: omsp_dbg_uart -> ok 480s Test: operators -> ok 481s Test: param_attr -> ok 481s Test: paramods -> ok 488s Test: partsel -> ok 489s Test: process -> ok 489s Test: realexpr -> ok 490s Test: repwhile -> ok 490s Test: retime -> ok 492s Test: rotate -> ok 493s Test: scopes -> ok 493s Test: signed_full_slice -> ok 493s Test: signedexpr -> ok 497s Test: sincos -> ok 497s Test: string_format -> ok 497s Test: subbytes -> ok 499s Test: task_func -> ok 499s Test: undef_eqx_nex -> ok 499s Test: usb_phy_tests -> ok 500s Test: values -> ok 500s Test: verilog_primitives -> ok 500s Test: vloghammer -> ok 501s Test: wandwor -> ok 503s Test: wreduce -> ok 503s Test: arrays02 -> ok 505s Test: asgn_binop -> ok 505s Test: case_expr_extend -> ok 506s Test: case_expr_query -> ok 506s Test: defvalue -> ok 506s Test: implicit_ports -> ok 507s Test: lesser_size_cast -> ok 507s Test: local_loop_var -> ok 508s Test: macro_arg_spaces -> ok 508s Test: matching_end_labels -> ok 509s Test: memwr_port_connection -> ok 509s Test: unnamed_block_decl -> ok 509s make[1]: Leaving directory '/tmp/autopkgtest.eUlrfO/build.1OM/src/tests/simple_abc9' 509s cd tests/hana && bash run-test.sh "" 509s make[1]: Entering directory '/tmp/autopkgtest.eUlrfO/build.1OM/src/tests/hana' 513s Test: test_intermout -> ok 514s Test: test_parse2synthtrans -> ok 515s Test: test_parser -> ok 516s Test: test_simulation_always -> ok 517s Test: test_simulation_and -> ok 517s Test: test_simulation_buffer -> ok 518s Test: test_simulation_decoder -> ok 519s Test: test_simulation_inc -> ok 521s Test: test_simulation_mux -> ok 521s Test: test_simulation_nand -> ok 522s Test: test_simulation_nor -> ok 523s Test: test_simulation_or -> ok 523s Test: test_simulation_seq -> ok 526s Test: test_simulation_shifter -> ok 527s Test: test_simulation_sop -> ok 528s Test: test_simulation_techmap -> ok 531s Test: test_simulation_techmap_tech -> ok 532s Test: test_simulation_vlib -> ok 532s Test: test_simulation_xnor -> ok 533s Test: test_simulation_xor -> ok 533s make[1]: Leaving directory '/tmp/autopkgtest.eUlrfO/build.1OM/src/tests/hana' 533s cd tests/asicworld && bash run-test.sh "" 533s make[1]: Entering directory '/tmp/autopkgtest.eUlrfO/build.1OM/src/tests/asicworld' 533s Test: code_hdl_models_GrayCounter -> ok 534s Test: code_hdl_models_arbiter -> ok 544s Test: code_hdl_models_cam -> ok 544s Test: code_hdl_models_clk_div -> ok 544s Test: code_hdl_models_clk_div_45 -> ok 545s Test: code_hdl_models_d_ff_gates -> ok 545s Test: code_hdl_models_d_latch_gates -> ok 545s Test: code_hdl_models_decoder_2to4_gates -> ok 546s Test: code_hdl_models_decoder_using_assign -> ok 546s Test: code_hdl_models_decoder_using_case -> ok 546s Test: code_hdl_models_dff_async_reset -> ok 547s Test: code_hdl_models_dff_sync_reset -> ok 547s Test: code_hdl_models_encoder_4to2_gates -> ok 547s Test: code_hdl_models_encoder_using_case -> ok 548s Test: code_hdl_models_encoder_using_if -> ok 548s Test: code_hdl_models_full_adder_gates -> ok 549s Test: code_hdl_models_full_subtracter_gates -> ok 549s Test: code_hdl_models_gray_counter -> ok 549s Test: code_hdl_models_half_adder_gates -> ok 550s Test: code_hdl_models_lfsr -> ok 550s Test: code_hdl_models_lfsr_updown -> ok 550s Test: code_hdl_models_mux_2to1_gates -> ok 551s Test: code_hdl_models_mux_using_assign -> ok 551s Test: code_hdl_models_mux_using_case -> ok 551s Test: code_hdl_models_mux_using_if -> ok 552s Test: code_hdl_models_one_hot_cnt -> ok 552s Test: code_hdl_models_parallel_crc -> ok 552s Test: code_hdl_models_parity_using_assign -> ok 553s Test: code_hdl_models_parity_using_bitwise -> ok 553s Test: code_hdl_models_parity_using_function -> ok 553s Test: code_hdl_models_pri_encoder_using_assign -> ok 554s Test: code_hdl_models_rom_using_case -> ok 554s Test: code_hdl_models_serial_crc -> ok 554s Test: code_hdl_models_tff_async_reset -> ok 555s Test: code_hdl_models_tff_sync_reset -> ok 557s Test: code_hdl_models_uart -> ok 557s Test: code_hdl_models_up_counter -> ok 557s Test: code_hdl_models_up_counter_load -> ok 558s Test: code_hdl_models_up_down_counter -> ok 559s Test: code_specman_switch_fabric -> ok 559s Test: code_tidbits_asyn_reset -> ok 559s Test: code_tidbits_blocking -> ok 560s Test: code_tidbits_fsm_using_always -> ok 560s Test: code_tidbits_fsm_using_function -> ok 561s Test: code_tidbits_fsm_using_single_always -> ok 561s Test: code_tidbits_nonblocking -> ok 561s Test: code_tidbits_reg_combo_example -> ok 562s Test: code_tidbits_reg_seq_example -> ok 562s Test: code_tidbits_syn_reset -> ok 562s Test: code_tidbits_wire_example -> ok 563s Test: code_verilog_tutorial_addbit -> ok 563s Test: code_verilog_tutorial_always_example -> ok 563s Test: code_verilog_tutorial_bus_con -> ok 563s Test: code_verilog_tutorial_comment -> ok 564s Test: code_verilog_tutorial_counter -> ok 564s Test: code_verilog_tutorial_d_ff -> ok 564s Test: code_verilog_tutorial_decoder -> ok 565s Test: code_verilog_tutorial_decoder_always -> ok 565s Test: code_verilog_tutorial_escape_id -> ok 565s Test: code_verilog_tutorial_explicit -> ok 565s Test: code_verilog_tutorial_first_counter -> ok 566s Test: code_verilog_tutorial_flip_flop -> ok 566s Test: code_verilog_tutorial_fsm_full -> ok 567s Test: code_verilog_tutorial_good_code -> ok 567s Test: code_verilog_tutorial_if_else -> ok 567s Test: code_verilog_tutorial_multiply -> ok 567s Test: code_verilog_tutorial_mux_21 -> ok 568s Test: code_verilog_tutorial_n_out_primitive -> ok 568s Test: code_verilog_tutorial_parallel_if -> ok 568s Test: code_verilog_tutorial_parity -> ok 568s Test: code_verilog_tutorial_simple_function -> ok 569s Test: code_verilog_tutorial_simple_if -> ok 569s Test: code_verilog_tutorial_task_global -> ok 569s Test: code_verilog_tutorial_tri_buf -> ok 569s Test: code_verilog_tutorial_v2k_reg -> ok 570s Test: code_verilog_tutorial_which_clock -> ok 570s make[1]: Leaving directory '/tmp/autopkgtest.eUlrfO/build.1OM/src/tests/asicworld' 570s # +cd tests/realmath && bash run-test.sh "" 570s cd tests/share && bash run-test.sh "" 570s generating tests.. 570s running tests.. 572s [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41][42][43][44][45][46][47][48][49][50][51][52][53][54][55][56][57][58][59][60][61][62][63][64][65][66][67][68][69][70][71][72][73][74][75][76][77][78][79][80][81][82][83][84][85][86][87][88][89][90][91][92][93][94][95][96][97][98][99] 572s cd tests/opt_share && bash run-test.sh "" 572s generating tests.. 573s running tests.. 573s make[1]: Entering directory '/tmp/autopkgtest.eUlrfO/build.1OM/src/tests/opt_share' 626s [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41][42][43][44][45][46][47][48][49][50][51][52][53][54][55][56][57][58][59][60][61][62][63][64][65][66][67][68][69][70][71][72][73][74][75][76][77][78][79][80][81][82][83][84][85][86][87][88][89][90][91][92][93][94][95][96][97][98][99]make[1]: Leaving directory '/tmp/autopkgtest.eUlrfO/build.1OM/src/tests/opt_share' 626s 626s cd tests/fsm && bash run-test.sh "" 626s generating tests.. 626s PRNG seed: 659726133 626s running tests.. 626s make[1]: Entering directory '/tmp/autopkgtest.eUlrfO/build.1OM/src/tests/fsm' 627s [0]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 627s Users of state reg look like FSM recoding might result in larger circuit. 627s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 637s K[1]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 637s Users of state reg look like FSM recoding might result in larger circuit. 637s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 640s K[2]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 640s Users of state reg look like FSM recoding might result in larger circuit. 640s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 641s K[3]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 641s Users of state reg look like FSM recoding might result in larger circuit. 641s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 642s K[4]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 642s Users of state reg look like FSM recoding might result in larger circuit. 642s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 646s K[5]K[6]KWarning: Regarding the user-specified fsm_encoding attribute on gate.state: 646s Users of state reg look like FSM recoding might result in larger circuit. 646s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 648s [7]K[8]K[9]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 648s Users of state reg look like FSM recoding might result in larger circuit. 648s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 648s K[10]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 648s Users of state reg look like FSM recoding might result in larger circuit. 648s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 649s K[11]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 649s Users of state reg look like FSM recoding might result in larger circuit. 649s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 652s KWarning: Regarding the user-specified fsm_encoding attribute on gate.state: 652s Users of state reg look like FSM recoding might result in larger circuit. 652s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 654s [12]K[13]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 654s Users of state reg look like FSM recoding might result in larger circuit. 654s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 655s K[14]K[15]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 655s Users of state reg look like FSM recoding might result in larger circuit. 655s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 659s K[16]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 659s Users of state reg look like FSM recoding might result in larger circuit. 659s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 662s K[17]K[18]K[19]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 662s Users of state reg look like FSM recoding might result in larger circuit. 662s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 664s K[20]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 664s Users of state reg look like FSM recoding might result in larger circuit. 664s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 666s K[21]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 667s Users of state reg look like FSM recoding might result in larger circuit. 667s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 668s K[22]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 668s Users of state reg look like FSM recoding might result in larger circuit. 668s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 674s K[23]K[24]K[25]K[26]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 674s Users of state reg look like FSM recoding might result in larger circuit. 674s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 677s K[27]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 677s Users of state reg look like FSM recoding might result in larger circuit. 677s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 678s K[28]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 678s Users of state reg look like FSM recoding might result in larger circuit. 678s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 678s K[29]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 678s Users of state reg look like FSM recoding might result in larger circuit. 678s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 680s K[30]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 680s Users of state reg look like FSM recoding might result in larger circuit. 680s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 682s K[31]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 682s Users of state reg look like FSM recoding might result in larger circuit. 682s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 685s K[32]K[33]K[34]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 685s Users of state reg look like FSM recoding might result in larger circuit. 685s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 686s K[35]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 686s Users of state reg look like FSM recoding might result in larger circuit. 686s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 688s K[36]K[37]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 688s Users of state reg look like FSM recoding might result in larger circuit. 688s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 711s T[38]K[39]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 711s Users of state reg look like FSM recoding might result in larger circuit. 711s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 712s K[40]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 712s Users of state reg look like FSM recoding might result in larger circuit. 712s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 714s K[41]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 714s Users of state reg look like FSM recoding might result in larger circuit. 714s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 715s K[42]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 715s Users of state reg look like FSM recoding might result in larger circuit. 715s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 716s K[43]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 716s Users of state reg look like FSM recoding might result in larger circuit. 716s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 716s K[44]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 716s Users of state reg look like FSM recoding might result in larger circuit. 716s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 718s K[45]K[46]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 718s Users of state reg look like FSM recoding might result in larger circuit. 718s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 730s K[47]K[48]K[49]K 730s make[1]: Leaving directory '/tmp/autopkgtest.eUlrfO/build.1OM/src/tests/fsm' 730s cd tests/techmap && bash run-test.sh 730s make[1]: Entering directory '/tmp/autopkgtest.eUlrfO/build.1OM/src/tests/techmap' 731s Passed abc9.ys 731s Warning: wire '\Q' is assigned in a block at < ok 744s Test: firrtl_938 -> ok 745s Test: implicit_en -> ok 748s Test: issue00335 -> ok 749s Test: issue00710 -> ok 750s Test: no_implicit_en -> ok 751s Test: read_arst -> ok 752s Test: read_two_mux -> ok 753s Test: shared_ports -> ok 754s Test: simple_sram_byte_en -> ok 755s Test: trans_addr_enable -> ok 756s Test: trans_sdp -> ok 758s Test: trans_sp -> ok 759s Test: wide_all -> ok 760s Test: wide_read_async -> ok 761s Test: wide_read_mixed -> ok 762s Test: wide_read_sync -> ok 764s Test: wide_read_trans -> ok 765s Test: wide_thru_priority -> ok 766s Test: wide_write -> ok 766s make[1]: Leaving directory '/tmp/autopkgtest.eUlrfO/build.1OM/src/tests/memories' 766s Testing expectations for amber23_sram_byte_en.v .. ok. 766s Testing expectations for implicit_en.v .. ok. 766s Testing expectations for issue00335.v .. ok. 766s Testing expectations for issue00710.v .. ok. 767s Testing expectations for no_implicit_en.v .. ok. 767s Testing expectations for read_arst.v .. ok. 767s Testing expectations for read_two_mux.v .. ok. 767s Testing expectations for shared_ports.v .. ok. 767s Testing expectations for simple_sram_byte_en.v .. ok. 767s Testing expectations for trans_addr_enable.v .. ok. 767s Testing expectations for trans_sdp.v .. ok. 767s Testing expectations for trans_sp.v .. ok. 767s Testing expectations for wide_all.v .. ok. 767s Testing expectations for wide_read_async.v .. ok. 767s Testing expectations for wide_read_mixed.v .. ok. 767s Testing expectations for wide_read_sync.v .. ok. 767s Testing expectations for wide_read_trans.v .. ok. 767s Testing expectations for wide_thru_priority.v .. ok. 767s Testing expectations for wide_write.v .. ok. 767s cd tests/memlib && bash run-test.sh "" 768s make[1]: Entering directory '/tmp/autopkgtest.eUlrfO/build.1OM/src/tests/memlib' 770s Test: t_async_big -> ok 774s Test: t_async_big_block -> ok 774s Test: t_async_small -> ok 774s Test: t_async_small_block -> ok 774s Test: t_sync_big -> ok 775s Test: t_sync_big_sdp -> ok 777s Test: t_sync_big_lut -> ok 777s Test: t_sync_small -> ok 777s Test: t_sync_small_block -> ok 777s Test: t_sync_small_block_attr -> ok 777s Test: t_init_lut_zeros_zero -> ok 778s Test: t_init_lut_zeros_any -> ok 778s Test: t_init_lut_val_zero -> ok 778s Test: t_init_lut_val_any -> ok 778s Test: t_init_lut_val_no_undef -> ok 778s Test: t_init_lut_val2_any -> ok 779s Test: t_init_lut_val2_no_undef -> ok 779s Test: t_init_lut_x_none -> ok 779s Test: t_init_lut_x_zero -> ok 779s Test: t_init_lut_x_any -> ok 780s Test: t_init_lut_x_no_undef -> ok 780s Test: t_ram_18b2B -> ok 780s Test: t_ram_9b1B -> ok 780s Test: t_ram_4b1B -> ok 780s Test: t_ram_2b1B -> ok 780s Test: t_ram_1b1B -> ok 781s Test: t_init_9b1B_zeros_zero -> ok 781s Test: t_init_9b1B_zeros_any -> ok 781s Test: t_init_9b1B_val_zero -> ok 781s Test: t_init_9b1B_val_any -> ok 782s Test: t_init_9b1B_val_no_undef -> ok 782s Test: t_init_13b2B_val_any -> ok 782s Test: t_init_18b2B_val_any -> ok 782s Test: t_init_18b2B_val_no_undef -> ok 782s Test: t_init_4b1B_x_none -> ok 783s Test: t_init_4b1B_x_zero -> ok 783s Test: t_init_4b1B_x_any -> ok 783s Test: t_init_4b1B_x_no_undef -> ok 783s Test: t_clock_a4_wANYrANYsFalse -> ok 783s Test: t_clock_a4_wANYrNEGsFalse -> ok 784s Test: t_clock_a4_wANYrPOSsFalse -> ok 784s Test: t_clock_a4_wNEGrANYsFalse -> ok 784s Test: t_clock_a4_wNEGrPOSsFalse -> ok 784s Test: t_clock_a4_wNEGrNEGsFalse -> ok 784s Test: t_clock_a4_wPOSrANYsFalse -> ok 785s Test: t_clock_a4_wPOSrNEGsFalse -> ok 785s Test: t_clock_a4_wPOSrPOSsFalse -> ok 785s Test: t_clock_a4_wANYrANYsTrue -> ok 785s Test: t_clock_a4_wNEGrPOSsTrue -> ok 785s Test: t_clock_a4_wNEGrNEGsTrue -> ok 786s Test: t_clock_a4_wPOSrNEGsTrue -> ok 786s Test: t_clock_a4_wPOSrPOSsTrue -> ok 786s Test: t_unmixed -> ok 786s Test: t_mixed_9_18 -> ok 786s Test: t_mixed_18_9 -> ok 787s Test: t_mixed_36_9 -> ok 787s Test: t_mixed_4_2 -> ok 787s Test: t_tdp -> ok 787s Test: t_sync_2clk -> ok 787s Test: t_sync_shared -> ok 788s Test: t_sync_2clk_shared -> ok 788s Test: t_sync_trans_old_old -> ok 788s Test: t_sync_trans_old_new -> ok 788s Test: t_sync_trans_old_none -> ok 788s Test: t_sync_trans_new_old -> ok 789s Test: t_sync_trans_new_new -> ok 789s Test: t_sync_trans_new_none -> ok 789s Test: t_sp_nc_none -> ok 789s Test: t_sp_new_none -> ok 789s Test: t_sp_old_none -> ok 789s Test: t_sp_nc_nc -> ok 790s Test: t_sp_new_nc -> ok 790s Test: t_sp_old_nc -> ok 790s Test: t_sp_nc_new -> ok 790s Test: t_sp_new_new -> ok 790s Test: t_sp_old_new -> ok 791s Test: t_sp_nc_old -> ok 791s Test: t_sp_new_old -> ok 791s Test: t_sp_old_old -> ok 791s Test: t_sp_nc_new_only -> ok 791s Test: t_sp_new_new_only -> ok 791s Test: t_sp_old_new_only -> ok 792s Test: t_sp_nc_new_only_be -> ok 792s Test: t_sp_new_new_only_be -> ok 792s Test: t_sp_old_new_only_be -> ok 792s Test: t_sp_nc_new_be -> ok 792s Test: t_sp_new_new_be -> ok 793s Test: t_sp_old_new_be -> ok 793s Test: t_sp_nc_old_be -> ok 793s Test: t_sp_new_old_be -> ok 793s Test: t_sp_old_old_be -> ok 793s Test: t_sp_nc_nc_be -> ok 794s Test: t_sp_new_nc_be -> ok 794s Test: t_sp_old_nc_be -> ok 794s Test: t_sp_nc_auto -> ok 794s Test: t_sp_new_auto -> ok 794s Test: t_sp_old_auto -> ok 795s Test: t_sp_nc_auto_be -> ok 795s Test: t_sp_new_auto_be -> ok 795s Test: t_sp_old_auto_be -> ok 795s Test: t_sp_init_x_x -> ok 795s Test: t_sp_init_x_x_re -> ok 796s Test: t_sp_init_x_x_ce -> ok 796s Test: t_sp_init_0_x -> ok 796s Test: t_sp_init_0_x_re -> ok 796s Test: t_sp_init_0_0 -> ok 796s Test: t_sp_init_0_0_re -> ok 796s Test: t_sp_init_0_any -> ok 797s Test: t_sp_init_0_any_re -> ok 797s Test: t_sp_init_v_x -> ok 797s Test: t_sp_init_v_x_re -> ok 797s Test: t_sp_init_v_0 -> ok 797s Test: t_sp_init_v_0_re -> ok 798s Test: t_sp_init_v_any -> ok 798s Test: t_sp_init_v_any_re -> ok 798s Test: t_sp_arst_x_x -> ok 799s Test: t_sp_arst_x_x_re -> ok 799s Test: t_sp_arst_0_x -> ok 799s Test: t_sp_arst_0_x_re -> ok 799s Test: t_sp_arst_0_0 -> ok 799s Test: t_sp_arst_0_0_re -> ok 799s Test: t_sp_arst_0_any -> ok 799s Test: t_sp_arst_0_any_re -> ok 799s Test: t_sp_arst_0_init -> ok 800s Test: t_sp_arst_0_init_re -> ok 800s Test: t_sp_arst_v_x -> ok 800s Test: t_sp_arst_v_x_re -> ok 800s Test: t_sp_arst_v_0 -> ok 800s Test: t_sp_arst_v_0_re -> ok 801s Test: t_sp_arst_v_any -> ok 801s Test: t_sp_arst_v_any_re -> ok 801s Test: t_sp_arst_v_init -> ok 801s Test: t_sp_arst_v_init_re -> ok 801s Test: t_sp_arst_e_x -> ok 802s Test: t_sp_arst_e_x_re -> ok 802s Test: t_sp_arst_e_0 -> ok 802s Test: t_sp_arst_e_0_re -> ok 802s Test: t_sp_arst_e_any -> ok 802s Test: t_sp_arst_e_any_re -> ok 803s Test: t_sp_arst_e_init -> ok 803s Test: t_sp_arst_e_init_re -> ok 803s Test: t_sp_arst_n_x -> ok 803s Test: t_sp_arst_n_x_re -> ok 803s Test: t_sp_arst_n_0 -> ok 804s Test: t_sp_arst_n_0_re -> ok 804s Test: t_sp_arst_n_any -> ok 804s Test: t_sp_arst_n_any_re -> ok 804s Test: t_sp_arst_n_init -> ok 804s Test: t_sp_arst_n_init_re -> ok 804s Test: t_sp_srst_x_x -> ok 805s Test: t_sp_srst_x_x_re -> ok 805s Test: t_sp_srst_0_x -> ok 805s Test: t_sp_srst_0_x_re -> ok 805s Test: t_sp_srst_0_0 -> ok 805s Test: t_sp_srst_0_0_re -> ok 806s Test: t_sp_srst_0_any -> ok 806s Test: t_sp_srst_0_any_re -> ok 806s Test: t_sp_srst_0_init -> ok 806s Test: t_sp_srst_0_init_re -> ok 807s Test: t_sp_srst_v_x -> ok 807s Test: t_sp_srst_v_x_re -> ok 807s Test: t_sp_srst_v_0 -> ok 807s Test: t_sp_srst_v_0_re -> ok 807s Test: t_sp_srst_v_any -> ok 808s Test: t_sp_srst_v_any_re -> ok 808s Test: t_sp_srst_v_any_re_gated -> ok 808s Test: t_sp_srst_v_any_ce -> ok 808s Test: t_sp_srst_v_any_ce_gated -> ok 808s Test: t_sp_srst_v_init -> ok 809s Test: t_sp_srst_v_init_re -> ok 809s Test: t_sp_srst_e_x -> ok 809s Test: t_sp_srst_e_x_re -> ok 809s Test: t_sp_srst_e_0 -> ok 809s Test: t_sp_srst_e_0_re -> ok 810s Test: t_sp_srst_e_any -> ok 810s Test: t_sp_srst_e_any_re -> ok 810s Test: t_sp_srst_e_init -> ok 810s Test: t_sp_srst_e_init_re -> ok 810s Test: t_sp_srst_n_x -> ok 811s Test: t_sp_srst_n_x_re -> ok 811s Test: t_sp_srst_n_0 -> ok 811s Test: t_sp_srst_n_0_re -> ok 811s Test: t_sp_srst_n_any -> ok 811s Test: t_sp_srst_n_any_re -> ok 812s Test: t_sp_srst_n_init -> ok 812s Test: t_sp_srst_n_init_re -> ok 812s Test: t_sp_srst_gv_x -> ok 812s Test: t_sp_srst_gv_x_re -> ok 812s Test: t_sp_srst_gv_0 -> ok 813s Test: t_sp_srst_gv_0_re -> ok 813s Test: t_sp_srst_gv_any -> ok 813s Test: t_sp_srst_gv_any_re -> ok 813s Test: t_sp_srst_gv_any_re_gated -> ok 813s Test: t_sp_srst_gv_any_ce -> ok 814s Test: t_sp_srst_gv_any_ce_gated -> ok 814s Test: t_sp_srst_gv_init -> ok 814s Test: t_sp_srst_gv_init_re -> ok 814s Test: t_wren_a4d4_NO_BYTE -> ok 814s Test: t_wren_a5d4_NO_BYTE -> ok 815s Test: t_wren_a6d4_NO_BYTE -> ok 815s Test: t_wren_a3d8_NO_BYTE -> ok 815s Test: t_wren_a4d8_NO_BYTE -> ok 815s Test: t_wren_a4d4_W4_B4 -> ok 815s Test: t_wren_a4d8_W4_B4_separate -> ok 815s Test: t_wren_a4d8_W8_B4 -> ok 816s Test: t_wren_a4d8_W8_B4_separate -> ok 816s Test: t_wren_a4d8_W8_B8 -> ok 816s Test: t_wren_a4d8_W8_B8_separate -> ok 816s Test: t_wren_a4d2w8_W16_B4 -> ok 816s Test: t_wren_a4d2w8_W16_B4_separate -> ok 817s Test: t_wren_a4d4w4_W16_B4 -> ok 817s Test: t_wren_a4d4w4_W16_B4_separate -> ok 817s Test: t_wren_a5d4w2_W16_B4 -> ok 817s Test: t_wren_a5d4w2_W16_B4_separate -> ok 818s Test: t_wren_a5d4w4_W16_B4 -> ok 818s Test: t_wren_a5d4w4_W16_B4_separate -> ok 818s Test: t_wren_a4d8w2_W16_B4 -> ok 818s Test: t_wren_a4d8w2_W16_B4_separate -> ok 818s Test: t_wren_a5d8w1_W16_B4 -> ok 819s Test: t_wren_a5d8w1_W16_B4_separate -> ok 819s Test: t_wren_a5d8w2_W16_B4 -> ok 819s Test: t_wren_a5d8w2_W16_B4_separate -> ok 819s Test: t_wren_a4d16w1_W16_B4 -> ok 819s Test: t_wren_a4d16w1_W16_B4_separate -> ok 820s Test: t_wren_a4d4w2_W8_B8 -> ok 820s Test: t_wren_a4d4w2_W8_B8_separate -> ok 820s Test: t_wren_a4d4w1_W8_B8 -> ok 820s Test: t_wren_a4d4w1_W8_B8_separate -> ok 820s Test: t_wren_a4d8w2_W8_B8 -> ok 821s Test: t_wren_a4d8w2_W8_B8_separate -> ok 821s Test: t_wren_a3d8w2_W8_B8 -> ok 821s Test: t_wren_a3d8w2_W8_B8_separate -> ok 821s Test: t_wren_a4d4w2_W8_B4 -> ok 821s Test: t_wren_a4d4w2_W8_B4_separate -> ok 822s Test: t_wren_a4d2w4_W8_B4 -> ok 822s Test: t_wren_a4d2w4_W8_B4_separate -> ok 822s Test: t_wren_a4d4w4_W8_B4 -> ok 822s Test: t_wren_a4d4w4_W8_B4_separate -> ok 823s Test: t_wren_a4d4w4_W4_B4 -> ok 823s Test: t_wren_a4d4w4_W4_B4_separate -> ok 823s Test: t_wren_a4d4w5_W4_B4 -> ok 823s Test: t_wren_a4d4w5_W4_B4_separate -> ok 823s Test: t_geom_a4d64_wren -> ok 824s Test: t_geom_a5d32_wren -> ok 824s Test: t_geom_a5d64_wren -> ok 824s Test: t_geom_a6d16_wren -> ok 824s Test: t_geom_a6d30_wren -> ok 824s Test: t_geom_a6d64_wren -> ok 825s Test: t_geom_a7d4_wren -> ok 825s Test: t_geom_a7d6_wren -> ok 825s Test: t_geom_a7d8_wren -> ok 825s Test: t_geom_a7d17_wren -> ok 825s Test: t_geom_a8d4_wren -> ok 826s Test: t_geom_a8d6_wren -> ok 826s Test: t_geom_a9d4_wren -> ok 826s Test: t_geom_a9d8_wren -> ok 827s Test: t_geom_a9d5_wren -> ok 827s Test: t_geom_a9d6_wren -> ok 827s Test: t_geom_a3d18_9b1B -> ok 827s Test: t_geom_a4d4_9b1B -> ok 827s Test: t_geom_a4d18_9b1B -> ok 828s Test: t_geom_a5d32_9b1B -> ok 828s Test: t_geom_a6d4_9b1B -> ok 828s Test: t_geom_a7d11_9b1B -> ok 828s Test: t_geom_a7d18_9b1B -> ok 829s Test: t_geom_a11d1_9b1B -> ok 829s Test: t_wide_sdp_a6r1w1b1x1 -> ok 829s Test: t_wide_sdp_a7r1w1b1x1 -> ok 829s Test: t_wide_sdp_a8r1w1b1x1 -> ok 829s Test: t_wide_sdp_a6r0w0b0x0 -> ok 830s Test: t_wide_sdp_a6r1w0b0x0 -> ok 830s Test: t_wide_sdp_a6r2w0b0x0 -> ok 830s Test: t_wide_sdp_a6r3w0b0x0 -> ok 830s Test: t_wide_sdp_a6r4w0b0x0 -> ok 831s Test: t_wide_sdp_a6r5w0b0x0 -> ok 831s Test: t_wide_sdp_a6r0w1b0x0 -> ok 831s Test: t_wide_sdp_a6r0w1b1x0 -> ok 831s Test: t_wide_sdp_a6r0w2b0x0 -> ok 832s Test: t_wide_sdp_a6r0w2b2x0 -> ok 832s Test: t_wide_sdp_a6r0w3b2x0 -> ok 832s Test: t_wide_sdp_a6r0w4b2x0 -> ok 833s Test: t_wide_sdp_a6r0w5b2x0 -> ok 833s Test: t_wide_sdp_a7r0w0b0x0 -> ok 833s Test: t_wide_sdp_a7r1w0b0x0 -> ok 833s Test: t_wide_sdp_a7r2w0b0x0 -> ok 834s Test: t_wide_sdp_a7r3w0b0x0 -> ok 834s Test: t_wide_sdp_a7r4w0b0x0 -> ok 834s Test: t_wide_sdp_a7r5w0b0x0 -> ok 834s Test: t_wide_sdp_a7r0w1b0x0 -> ok 835s Test: t_wide_sdp_a7r0w1b1x0 -> ok 835s Test: t_wide_sdp_a7r0w2b0x0 -> ok 835s Test: t_wide_sdp_a7r0w2b2x0 -> ok 835s Test: t_wide_sdp_a7r0w3b2x0 -> ok 836s Test: t_wide_sdp_a7r0w4b2x0 -> ok 836s Test: t_wide_sdp_a7r0w5b2x0 -> ok 836s Test: t_wide_sp_mix_a6r1w1b1 -> ok 836s Test: t_wide_sp_mix_a7r1w1b1 -> ok 837s Test: t_wide_sp_mix_a8r1w1b1 -> ok 837s Test: t_wide_sp_mix_a6r0w0b0 -> ok 837s Test: t_wide_sp_mix_a6r1w0b0 -> ok 837s Test: t_wide_sp_mix_a6r2w0b0 -> ok 838s Test: t_wide_sp_mix_a6r3w0b0 -> ok 838s Test: t_wide_sp_mix_a6r4w0b0 -> ok 838s Test: t_wide_sp_mix_a6r5w0b0 -> ok 839s Test: t_wide_sp_mix_a6r0w1b0 -> ok 840s Test: t_wide_sp_mix_a6r0w1b1 -> ok 840s Test: t_wide_sp_mix_a6r0w2b0 -> ok 840s Test: t_wide_sp_mix_a6r0w2b2 -> ok 840s Test: t_wide_sp_mix_a6r0w3b2 -> ok 840s Test: t_wide_sp_mix_a6r0w4b2 -> ok 840s Test: t_wide_sp_mix_a6r0w5b2 -> ok 840s Test: t_wide_sp_mix_a7r0w0b0 -> ok 841s Test: t_wide_sp_mix_a7r1w0b0 -> ok 841s Test: t_wide_sp_mix_a7r2w0b0 -> ok 841s Test: t_wide_sp_mix_a7r3w0b0 -> ok 841s Test: t_wide_sp_mix_a7r4w0b0 -> ok 842s Test: t_wide_sp_mix_a7r5w0b0 -> ok 842s Test: t_wide_sp_mix_a7r0w1b0 -> ok 842s Test: t_wide_sp_mix_a7r0w1b1 -> ok 842s Test: t_wide_sp_mix_a7r0w2b0 -> ok 842s Test: t_wide_sp_mix_a7r0w2b2 -> ok 843s Test: t_wide_sp_mix_a7r0w3b2 -> ok 843s Test: t_wide_sp_mix_a7r0w4b2 -> ok 843s Test: t_wide_sp_mix_a7r0w5b2 -> ok 844s Test: t_wide_sp_tied_a6r1w1b1 -> ok 844s Test: t_wide_sp_tied_a7r1w1b1 -> ok 844s Test: t_wide_sp_tied_a8r1w1b1 -> ok 844s Test: t_wide_sp_tied_a6r0w0b0 -> ok 845s Test: t_wide_sp_tied_a6r1w0b0 -> ok 845s Test: t_wide_sp_tied_a6r2w0b0 -> ok 845s Test: t_wide_sp_tied_a6r3w0b0 -> ok 845s Test: t_wide_sp_tied_a6r4w0b0 -> ok 846s Test: t_wide_sp_tied_a6r5w0b0 -> ok 846s Test: t_wide_sp_tied_a6r0w1b0 -> ok 846s Test: t_wide_sp_tied_a6r0w1b1 -> ok 846s Test: t_wide_sp_tied_a6r0w2b0 -> ok 847s Test: t_wide_sp_tied_a6r0w2b2 -> ok 847s Test: t_wide_sp_tied_a6r0w3b2 -> ok 847s Test: t_wide_sp_tied_a6r0w4b2 -> ok 848s Test: t_wide_sp_tied_a6r0w5b2 -> ok 848s Test: t_wide_sp_tied_a7r0w0b0 -> ok 848s Test: t_wide_sp_tied_a7r1w0b0 -> ok 848s Test: t_wide_sp_tied_a7r2w0b0 -> ok 848s Test: t_wide_sp_tied_a7r3w0b0 -> ok 849s Test: t_wide_sp_tied_a7r4w0b0 -> ok 849s Test: t_wide_sp_tied_a7r5w0b0 -> ok 849s Test: t_wide_sp_tied_a7r0w1b0 -> ok 850s Test: t_wide_sp_tied_a7r0w1b1 -> ok 850s Test: t_wide_sp_tied_a7r0w2b0 -> ok 850s Test: t_wide_sp_tied_a7r0w2b2 -> ok 850s Test: t_wide_sp_tied_a7r0w3b2 -> ok 851s Test: t_wide_sp_tied_a7r0w4b2 -> ok 851s Test: t_wide_sp_tied_a7r0w5b2 -> ok 851s Test: t_wide_read_a6r1w1b1 -> ok 851s Test: t_wide_write_a6r1w1b1 -> ok 852s Test: t_wide_read_a7r1w1b1 -> ok 852s Test: t_wide_write_a7r1w1b1 -> ok 852s Test: t_wide_read_a8r1w1b1 -> ok 852s Test: t_wide_write_a8r1w1b1 -> ok 853s Test: t_wide_read_a6r0w0b0 -> ok 853s Test: t_wide_write_a6r0w0b0 -> ok 853s Test: t_wide_read_a6r1w0b0 -> ok 853s Test: t_wide_write_a6r1w0b0 -> ok 853s Test: t_wide_read_a6r2w0b0 -> ok 854s Test: t_wide_write_a6r2w0b0 -> ok 854s Test: t_wide_read_a6r3w0b0 -> ok 854s Test: t_wide_write_a6r3w0b0 -> ok 854s Test: t_wide_read_a6r4w0b0 -> ok 855s Test: t_wide_write_a6r4w0b0 -> ok 855s Test: t_wide_read_a6r5w0b0 -> ok 856s Test: t_wide_write_a6r5w0b0 -> ok 856s Test: t_wide_read_a6r0w1b0 -> ok 856s Test: t_wide_write_a6r0w1b0 -> ok 856s Test: t_wide_read_a6r0w1b1 -> ok 856s Test: t_wide_write_a6r0w1b1 -> ok 857s Test: t_wide_read_a6r0w2b0 -> ok 857s Test: t_wide_write_a6r0w2b0 -> ok 857s Test: t_wide_read_a6r0w2b2 -> ok 857s Test: t_wide_write_a6r0w2b2 -> ok 858s Test: t_wide_read_a6r0w3b2 -> ok 858s Test: t_wide_write_a6r0w3b2 -> ok 858s Test: t_wide_read_a6r0w4b2 -> ok 858s Test: t_wide_write_a6r0w4b2 -> ok 859s Test: t_wide_read_a6r0w5b2 -> ok 859s Test: t_wide_write_a6r0w5b2 -> ok 859s Test: t_wide_read_a7r0w0b0 -> ok 860s Test: t_wide_write_a7r0w0b0 -> ok 860s Test: t_wide_read_a7r1w0b0 -> ok 860s Test: t_wide_write_a7r1w0b0 -> ok 860s Test: t_wide_read_a7r2w0b0 -> ok 861s Test: t_wide_write_a7r2w0b0 -> ok 861s Test: t_wide_read_a7r3w0b0 -> ok 861s Test: t_wide_write_a7r3w0b0 -> ok 861s Test: t_wide_read_a7r4w0b0 -> ok 862s Test: t_wide_write_a7r4w0b0 -> ok 862s Test: t_wide_read_a7r5w0b0 -> ok 863s Test: t_wide_write_a7r5w0b0 -> ok 863s Test: t_wide_read_a7r0w1b0 -> ok 863s Test: t_wide_write_a7r0w1b0 -> ok 863s Test: t_wide_read_a7r0w1b1 -> ok 863s Test: t_wide_write_a7r0w1b1 -> ok 864s Test: t_wide_read_a7r0w2b0 -> ok 864s Test: t_wide_write_a7r0w2b0 -> ok 864s Test: t_wide_read_a7r0w2b2 -> ok 864s Test: t_wide_write_a7r0w2b2 -> ok 865s Test: t_wide_read_a7r0w3b2 -> ok 865s Test: t_wide_write_a7r0w3b2 -> ok 865s Test: t_wide_read_a7r0w4b2 -> ok 865s Test: t_wide_write_a7r0w4b2 -> ok 866s Test: t_wide_read_a7r0w5b2 -> ok 866s Test: t_wide_write_a7r0w5b2 -> ok 866s Test: t_quad_port_a2d2 -> ok 867s Test: t_quad_port_a4d2 -> ok 867s Test: t_quad_port_a5d2 -> ok 867s Test: t_quad_port_a4d4 -> ok 867s Test: t_quad_port_a6d2 -> ok 868s Test: t_quad_port_a4d8 -> ok 868s Test: t_wide_quad_a4w2r1 -> ok 868s Test: t_wide_oct_a4w2r1 -> ok 868s Test: t_wide_quad_a4w2r2 -> ok 868s Test: t_wide_oct_a4w2r2 -> ok 868s Test: t_wide_quad_a4w2r3 -> ok 869s Test: t_wide_oct_a4w2r3 -> ok 869s Test: t_wide_quad_a4w2r4 -> ok 869s Test: t_wide_oct_a4w2r4 -> ok 869s Test: t_wide_quad_a4w2r5 -> ok 869s Test: t_wide_oct_a4w2r5 -> ok 870s Test: t_wide_quad_a4w2r6 -> ok 870s Test: t_wide_oct_a4w2r6 -> ok 870s Test: t_wide_quad_a4w2r7 -> ok 870s Test: t_wide_oct_a4w2r7 -> ok 870s Test: t_wide_quad_a4w2r8 -> ok 871s Test: t_wide_oct_a4w2r8 -> ok 871s Test: t_wide_quad_a4w2r9 -> ok 871s Test: t_wide_oct_a4w2r9 -> ok 871s Test: t_wide_quad_a4w4r1 -> ok 871s Test: t_wide_oct_a4w4r1 -> ok 872s Test: t_wide_quad_a4w4r4 -> ok 872s Test: t_wide_oct_a4w4r4 -> ok 872s Test: t_wide_quad_a4w4r6 -> ok 872s Test: t_wide_oct_a4w4r6 -> ok 873s Test: t_wide_quad_a4w4r9 -> ok 873s Test: t_wide_oct_a4w4r9 -> ok 873s Test: t_wide_quad_a5w2r1 -> ok 873s Test: t_wide_oct_a5w2r1 -> ok 873s Test: t_wide_quad_a5w2r4 -> ok 874s Test: t_wide_oct_a5w2r4 -> ok 874s Test: t_wide_quad_a5w2r9 -> ok 874s Test: t_wide_oct_a5w2r9 -> ok 874s Test: t_no_reset -> ok 875s Test: t_gclken -> ok 875s Test: t_ungated -> ok 875s Test: t_gclken_ce -> ok 875s Test: t_grden -> ok 875s Test: t_grden_ce -> ok 876s Test: t_exclwr -> ok 876s Test: t_excl_rst -> ok 876s Test: t_transwr -> ok 876s Test: t_trans_rst -> ok 877s Test: t_wr_byte -> ok 877s Test: t_trans_byte -> ok 877s Test: t_wr_rst_byte -> ok 877s Test: t_rst_wr_byte -> ok 877s Test: t_rdenrst_wr_byte -> ok 877s make[1]: Leaving directory '/tmp/autopkgtest.eUlrfO/build.1OM/src/tests/memlib' 877s cd tests/bram && bash run-test.sh "" 877s generating tests.. 878s PRNG seed: 814467 878s running tests.. 878s make[1]: Entering directory '/tmp/autopkgtest.eUlrfO/build.1OM/src/tests/bram' 878s Passed memory_bram test 00_01. 879s Passed memory_bram test 00_02. 879s Passed memory_bram test 00_03. 880s Passed memory_bram test 00_04. 881s Passed memory_bram test 01_00. 881s Passed memory_bram test 01_02. 882s Passed memory_bram test 01_03. 883s Passed memory_bram test 01_04. 884s Passed memory_bram test 02_00. 884s Passed memory_bram test 02_01. 885s Passed memory_bram test 02_03. 886s Passed memory_bram test 02_04. 887s Passed memory_bram test 03_00. 888s Passed memory_bram test 03_01. 889s Passed memory_bram test 03_02. 890s Passed memory_bram test 03_04. 891s Passed memory_bram test 04_00. 892s Passed memory_bram test 04_01. 893s Passed memory_bram test 04_02. 894s Passed memory_bram test 04_03. 894s make[1]: Leaving directory '/tmp/autopkgtest.eUlrfO/build.1OM/src/tests/bram' 894s cd tests/various && bash run-test.sh 894s make[1]: Entering directory '/tmp/autopkgtest.eUlrfO/build.1OM/src/tests/various' 894s Warning: Wire abc9_test027.$abc$91$o is used but has no driver. 894s Passed abc9.ys 894s Passed aiger_dff.ys 894s Passed attrib05_port_conn.ys 895s Passed attrib07_func_call.ys 895s Passed autoname.ys 895s Passed blackbox_wb.ys 895s Passed bug1496.ys 895s Passed bug1531.ys 895s Passed bug1614.ys 895s Passed bug1710.ys 895s Warning: Yosys has only limited support for tri-state logic at the moment. (< svinterface1_tb.v:50: $finish called at 420000 (10ps) 972s svinterface1_tb.v:50: $finish called at 420000 (10ps) 972s ok 973s Test: svinterface_at_top -> svinterface_at_top_tb.v:61: $finish called at 420000 (10ps) 973s svinterface_at_top_tb_wrapper.v:61: $finish called at 420000 (10ps) 973s ERROR! 973s Test: load_and_derive ->ok 973s Test: resolve_types ->ok 973s cd tests/svtypes && bash run-test.sh "" 973s make[1]: Entering directory '/tmp/autopkgtest.eUlrfO/build.1OM/src/tests/svtypes' 973s Passed enum_simple.ys 973s Passed logic_rom.ys 973s < ok 989s Test ../../techlibs/anlogic/cells_sim.v -> ok 989s Test ../../techlibs/coolrunner2/cells_sim.v -> ok 989s Test ../../techlibs/ecp5/cells_sim.v -> ok 989s Test ../../techlibs/efinix/cells_sim.v -> ok 989s Test ../../techlibs/gatemate/cells_sim.v -> ok 989s Test ../../techlibs/gowin/cells_sim.v -> ok 989s Test ../../techlibs/greenpak4/cells_sim.v -> ok 989s Test ../../techlibs/ice40/cells_sim.v -DICE40_HX ->../../techlibs/ice40/cells_sim.v:2231: warning: Choosing typ expression. 989s ../../techlibs/ice40/cells_sim.v:2231: warning: Choosing typ expression. 989s ../../techlibs/ice40/cells_sim.v:2233: warning: Choosing typ expression. 989s ../../techlibs/ice40/cells_sim.v:2233: warning: Choosing typ expression. 989s ../../techlibs/ice40/cells_sim.v:2235: warning: Choosing typ expression. 989s ../../techlibs/ice40/cells_sim.v:2235: warning: Choosing typ expression. 989s ../../techlibs/ice40/cells_sim.v:2237: warning: Choosing typ expression. 989s ../../techlibs/ice40/cells_sim.v:2237: warning: Choosing typ expression. 989s ../../techlibs/ice40/cells_sim.v:2239: warning: Choosing typ expression. 989s ../../techlibs/ice40/cells_sim.v:2239: warning: Choosing typ expression. 989s ok 989s Test ../../techlibs/ice40/cells_sim.v -DICE40_LP ->../../techlibs/ice40/cells_sim.v:2295: warning: Choosing typ expression. 989s ../../techlibs/ice40/cells_sim.v:2295: warning: Choosing typ expression. 989s ../../techlibs/ice40/cells_sim.v:2297: warning: Choosing typ expression. 989s ../../techlibs/ice40/cells_sim.v:2297: warning: Choosing typ expression. 989s ../../techlibs/ice40/cells_sim.v:2299: warning: Choosing typ expression. 989s ../../techlibs/ice40/cells_sim.v:2299: warning: Choosing typ expression. 989s ../../techlibs/ice40/cells_sim.v:2301: warning: Choosing typ expression. 989s ../../techlibs/ice40/cells_sim.v:2301: warning: Choosing typ expression. 989s ../../techlibs/ice40/cells_sim.v:2303: warning: Choosing typ expression. 989s ../../techlibs/ice40/cells_sim.v:2303: warning: Choosing typ expression. 989s ok 989s Test ../../techlibs/ice40/cells_sim.v -DICE40_U ->../../techlibs/ice40/cells_sim.v:2359: warning: Choosing typ expression. 989s ../../techlibs/ice40/cells_sim.v:2359: warning: Choosing typ expression. 989s ../../techlibs/ice40/cells_sim.v:2361: warning: Choosing typ expression. 989s ../../techlibs/ice40/cells_sim.v:2361: warning: Choosing typ expression. 989s ../../techlibs/ice40/cells_sim.v:2363: warning: Choosing typ expression. 989s ../../techlibs/ice40/cells_sim.v:2363: warning: Choosing typ expression. 989s ../../techlibs/ice40/cells_sim.v:2365: warning: Choosing typ expression. 989s ../../techlibs/ice40/cells_sim.v:2365: warning: Choosing typ expression. 989s ../../techlibs/ice40/cells_sim.v:2367: warning: Choosing typ expression. 989s ../../techlibs/ice40/cells_sim.v:2367: warning: Choosing typ expression. 989s ok 989s Test ../../techlibs/intel/cyclone10lp/cells_sim.v -> ok 989s Test ../../techlibs/intel/cycloneiv/cells_sim.v -> ok 989s Test ../../techlibs/intel/cycloneive/cells_sim.v -> ok 989s Test ../../techlibs/intel/max10/cells_sim.v -> ok 989s Test ../../techlibs/intel_alm/cyclonev/cells_sim.v -> ok 989s Test ../../techlibs/nexus/cells_sim.v -> ok 989s Test ../../techlibs/quicklogic/cells_sim.v -> ok 989s Test ../../techlibs/sf2/cells_sim.v -> ok 989s Test ../../techlibs/xilinx/cells_sim.v -> ok 989s Test ../../techlibs/common/simcells.v -> ok 989s Test ../../techlibs/common/simlib.v -> ok 989s cd tests/arch/ice40 && bash run-test.sh "" 989s make[1]: Entering directory '/tmp/autopkgtest.eUlrfO/build.1OM/src/tests/arch/ice40' 991s Passed add_sub.ys 995s Passed adffs.ys 995s Warning: Resizing cell port SSCounter6o.l0.I3 from 32 bits to 1 bits. 995s Warning: Resizing cell port SSCounter6o.c0.CI from 32 bits to 1 bits. 995s Warning: Resizing cell port SSCounter6o.lien.I0 from 32 bits to 1 bits. 995s Warning: Resizing cell port SSCounter6o.lien.I1 from 32 bits to 1 bits. 996s Passed bug1597.ys 998s Passed bug1598.ys 999s Passed bug1626.ys 1021s Passed bug1644.ys 1022s Passed bug2061.ys 1023s Passed counter.ys 1025s Passed dffs.ys 1036s Passed dpram.ys 1038s Passed fsm.ys 1038s Passed ice40_dsp.ys 1039s Passed ice40_opt.ys 1039s Passed ice40_wrapcarry.ys 1042s Passed latches.ys 1043s Passed logic.ys 1050s Passed macc.ys 1118s Passed memories.ys 1119s Passed mul.ys 1124s Passed mux.ys 1124s Warning: wire '\data' is assigned in a block at rom.v:10.5-10.15. 1124s Warning: wire '\data' is assigned in a block at rom.v:11.5-11.15. 1124s Warning: wire '\data' is assigned in a block at rom.v:12.5-12.15. 1124s Warning: wire '\data' is assigned in a block at rom.v:13.6-13.16. 1124s Warning: wire '\data' is assigned in a block at rom.v:14.6-14.16. 1124s Warning: wire '\data' is assigned in a block at rom.v:15.6-15.16. 1124s Warning: wire '\data' is assigned in a block at rom.v:16.11-16.21. 1125s Passed rom.ys 1127s Passed shifter.ys 1127s Warning: wire '\read_data' is assigned in a block at spram.v:19.3-19.25. 1129s Passed spram.ys 1130s Passed tribuf.ys 1130s make[1]: Leaving directory '/tmp/autopkgtest.eUlrfO/build.1OM/src/tests/arch/ice40' 1130s cd tests/arch/xilinx && bash run-test.sh "" 1130s make[1]: Entering directory '/tmp/autopkgtest.eUlrfO/build.1OM/src/tests/arch/xilinx' 1148s Warning: Whitebox '$paramod\FDRE\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. 1148s Warning: Whitebox 'FDSE' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. 1148s Warning: Whitebox '$paramod\FDRE_1\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. 1148s Warning: Whitebox '$paramod\FDSE_1\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. 1177s Passed abc9_dff.ys 1182s Warning: Shift register inference not yet supported for family xc3s. 1186s Passed add_sub.ys 1207s Passed adffs.ys 1213s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DIADI from 64 bits to 16 bits. 1213s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOADO from 64 bits to 16 bits. 1213s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOBDO from 64 bits to 16 bits. 1213s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOPADOP from 8 bits to 2 bits. 1213s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOPBDOP from 8 bits to 2 bits. 1213s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.WEA from 4 bits to 2 bits. 1224s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.WEBWE from 1 bits to 4 bits. 1230s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DIADI from 64 bits to 16 bits. 1230s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOADO from 64 bits to 16 bits. 1230s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOBDO from 64 bits to 16 bits. 1230s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOPADOP from 8 bits to 2 bits. 1230s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOPBDOP from 8 bits to 2 bits. 1230s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.WEA from 4 bits to 2 bits. 1230s Warning: Selection "asym_ram_sdp_read_wider" did not match any module. 1247s Passed asym_ram_sdp.ys 1253s Warning: Resizing cell port block_ram.memory.0.0.DIADI from 64 bits to 16 bits. 1253s Warning: Resizing cell port block_ram.memory.0.0.DOADO from 64 bits to 16 bits. 1253s Warning: Resizing cell port block_ram.memory.0.0.DOBDO from 64 bits to 16 bits. 1253s Warning: Resizing cell port block_ram.memory.0.0.DOPADOP from 8 bits to 2 bits. 1253s Warning: Resizing cell port block_ram.memory.0.0.DOPBDOP from 8 bits to 2 bits. 1253s Warning: Resizing cell port block_ram.memory.0.0.WEA from 4 bits to 2 bits. 1282s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DIADI from 64 bits to 16 bits. 1282s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOADO from 64 bits to 16 bits. 1282s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOBDO from 64 bits to 16 bits. 1282s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOPADOP from 8 bits to 2 bits. 1282s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOPBDOP from 8 bits to 2 bits. 1282s Warning: Resizing cell port distributed_ram_manual.memory.0.0.WEA from 4 bits to 2 bits. 1282s Passed attributes_test.ys 1287s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIADI from 64 bits to 16 bits. 1287s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOADO from 64 bits to 16 bits. 1287s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOBDO from 64 bits to 16 bits. 1287s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPADOP from 8 bits to 2 bits. 1287s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPBDOP from 8 bits to 2 bits. 1287s Warning: Resizing cell port sync_ram_sdp.memory.0.0.WEA from 4 bits to 2 bits. 1293s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIPADIP from 8 bits to 2 bits. 1315s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIADI from 64 bits to 32 bits. 1315s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIPADIP from 8 bits to 4 bits. 1315s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOADO from 64 bits to 32 bits. 1315s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOBDO from 64 bits to 32 bits. 1315s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPADOP from 8 bits to 4 bits. 1315s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPBDOP from 8 bits to 4 bits. 1348s Passed blockram.ys 1353s Passed bug1460.ys 1358s Passed bug1462.ys 1363s Passed bug1480.ys 1369s Passed bug1598.ys 1371s Warning: Wire top.\t is used but has no driver. 1371s Warning: Wire top.\in is used but has no driver. 1374s Passed bug1605.ys 1375s Passed bug3670.ys 1380s Passed counter.ys 1404s Passed dffs.ys 1422s Passed dsp_abc9.ys 1436s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef. 1436s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef. 1498s Passed dsp_cascade.ys 1503s Passed dsp_fastfir.ys 1511s Passed dsp_simd.ys 1516s Warning: Shift register inference not yet supported for family xc3se. 1521s Passed fsm.ys 1537s Passed latches.ys 1543s Passed logic.ys 1593s Warning: Shift register inference not yet supported for family xc3s. 1597s Passed lutram.ys 1610s Passed macc.ys 1619s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef. 1619s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef. 1621s Passed mul.ys 1621s Warning: Replacing memory \M with list of registers. See mul_unsigned.v:25 1633s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef. 1633s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef. 1638s Passed mul_unsigned.ys 1662s Passed mux.ys 1662s Warning: Shift register inference not yet supported for family xc3se. 1677s Passed mux_lut4.ys 1689s Passed nosrl.ys 1689s Passed opt_lut_ins.ys 1703s Passed pmgen_xilinx_srl.ys 1710s Warning: Resizing cell port priority_memory.mem.0.0.ADDRARDADDR from 16 bits to 15 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.0.ADDRBWRADDR from 16 bits to 15 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.0.DINADIN from 64 bits to 32 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.0.DINBDIN from 64 bits to 32 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.0.DINPADINP from 8 bits to 4 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.0.DINPBDINP from 8 bits to 4 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.0.DOUTADOUT from 64 bits to 32 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.0.DOUTBDOUT from 64 bits to 32 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.0.DOUTPADOUTP from 8 bits to 4 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.0.DOUTPBDOUTP from 8 bits to 4 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.0.WEBWE from 4 bits to 8 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.1.ADDRARDADDR from 16 bits to 15 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.1.ADDRBWRADDR from 16 bits to 15 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.1.DINADIN from 64 bits to 32 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.1.DINBDIN from 64 bits to 32 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.1.DINPADINP from 8 bits to 4 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.1.DINPBDINP from 8 bits to 4 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.1.DOUTADOUT from 64 bits to 32 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.1.DOUTBDOUT from 64 bits to 32 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.1.DOUTPADOUTP from 8 bits to 4 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.1.DOUTPBDOUTP from 8 bits to 4 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.1.WEBWE from 4 bits to 8 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.2.ADDRARDADDR from 16 bits to 15 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.2.ADDRBWRADDR from 16 bits to 15 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.2.DINADIN from 64 bits to 32 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.2.DINBDIN from 64 bits to 32 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.2.DINPADINP from 8 bits to 4 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.2.DINPBDINP from 8 bits to 4 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.2.DOUTADOUT from 64 bits to 32 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.2.DOUTBDOUT from 64 bits to 32 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.2.DOUTPADOUTP from 8 bits to 4 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.2.DOUTPBDOUTP from 8 bits to 4 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.2.WEBWE from 4 bits to 8 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.3.ADDRARDADDR from 16 bits to 15 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.3.ADDRBWRADDR from 16 bits to 15 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.3.DINADIN from 64 bits to 32 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.3.DINBDIN from 64 bits to 32 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.3.DINPADINP from 8 bits to 4 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.3.DINPBDINP from 8 bits to 4 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.3.DOUTADOUT from 64 bits to 32 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.3.DOUTBDOUT from 64 bits to 32 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.3.DOUTPADOUTP from 8 bits to 4 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.3.DOUTPBDOUTP from 8 bits to 4 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.3.WEBWE from 4 bits to 8 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.4.ADDRARDADDR from 16 bits to 15 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.4.ADDRBWRADDR from 16 bits to 15 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.4.DINADIN from 64 bits to 32 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.4.DINBDIN from 64 bits to 32 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.4.DINPADINP from 8 bits to 4 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.4.DINPBDINP from 8 bits to 4 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.4.DOUTADOUT from 64 bits to 32 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.4.DOUTBDOUT from 64 bits to 32 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.4.DOUTPADOUTP from 8 bits to 4 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.4.DOUTPBDOUTP from 8 bits to 4 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.4.WEBWE from 4 bits to 8 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.5.ADDRARDADDR from 16 bits to 15 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.5.ADDRBWRADDR from 16 bits to 15 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.5.DINADIN from 64 bits to 32 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.5.DINBDIN from 64 bits to 32 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.5.DINPADINP from 8 bits to 4 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.5.DINPBDINP from 8 bits to 4 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.5.DOUTADOUT from 64 bits to 32 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.5.DOUTBDOUT from 64 bits to 32 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.5.DOUTPADOUTP from 8 bits to 4 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.5.DOUTPBDOUTP from 8 bits to 4 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.5.WEBWE from 4 bits to 8 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.6.ADDRARDADDR from 16 bits to 15 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.6.ADDRBWRADDR from 16 bits to 15 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.6.DINADIN from 64 bits to 32 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.6.DINBDIN from 64 bits to 32 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.6.DINPADINP from 8 bits to 4 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.6.DINPBDINP from 8 bits to 4 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.6.DOUTADOUT from 64 bits to 32 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.6.DOUTBDOUT from 64 bits to 32 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.6.DOUTPADOUTP from 8 bits to 4 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.6.DOUTPBDOUTP from 8 bits to 4 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.6.WEBWE from 4 bits to 8 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.7.ADDRARDADDR from 16 bits to 15 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.7.ADDRBWRADDR from 16 bits to 15 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.7.DINADIN from 64 bits to 32 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.7.DINBDIN from 64 bits to 32 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.7.DINPADINP from 8 bits to 4 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.7.DINPBDINP from 8 bits to 4 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.7.DOUTADOUT from 64 bits to 32 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.7.DOUTBDOUT from 64 bits to 32 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.7.DOUTPADOUTP from 8 bits to 4 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.7.DOUTPBDOUTP from 8 bits to 4 bits. 1710s Warning: Resizing cell port priority_memory.mem.0.7.WEBWE from 4 bits to 8 bits. 1715s Warning: Resizing cell port priority_memory.mem.0.0.BWE_A from 8 bits to 9 bits. 1715s Warning: Resizing cell port priority_memory.mem.0.0.BWE_B from 8 bits to 9 bits. 1730s Warning: Resizing cell port sp_write_first.mem.0.0.BWE_A from 8 bits to 9 bits. 1735s Warning: Resizing cell port sp_read_first.mem.0.0.BWE_B from 8 bits to 9 bits. 1735s Passed priority_memory.ys 1740s Passed shifter.ys 1745s Passed tribuf.ys 1750s Passed xilinx_dffopt.ys 1750s Passed xilinx_dsp.ys 1750s Passed xilinx_srl.ys 1760s Passed macc.sh 1770s Passed tribuf.sh 1770s make[1]: Leaving directory '/tmp/autopkgtest.eUlrfO/build.1OM/src/tests/arch/xilinx' 1770s cd tests/arch/ecp5 && bash run-test.sh "" 1770s make[1]: Entering directory '/tmp/autopkgtest.eUlrfO/build.1OM/src/tests/arch/ecp5' 1771s Passed add_sub.ys 1774s Passed adffs.ys 1775s Passed bug1459.ys 1776s Passed bug1598.ys 1776s Passed bug1630.ys 1776s Warning: Literal has a width of 16 bit, but value requires 184 bit. (<>>/,/<<>>/ {print $0}' 2307s + iverilog -o iverilog-initial_display initial_display.v 2307s + ./iverilog-initial_display 2307s + diff yosys-initial_display.log iverilog-initial_display.log 2307s + test_always_display clk -DEVENT_CLK 2307s + local subtest=clk 2307s + shift 2307s + ../../yosys -p 'read_verilog -DEVENT_CLK always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk-1.v 2307s 2307s /----------------------------------------------------------------------------\ 2307s | | 2307s | yosys -- Yosys Open SYnthesis Suite | 2307s | | 2307s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2307s | | 2307s | Permission to use, copy, modify, and/or distribute this software for any | 2307s | purpose with or without fee is hereby granted, provided that the above | 2307s | copyright notice and this permission notice appear in all copies. | 2307s | | 2307s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2307s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2307s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2307s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2307s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2307s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2307s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2307s | | 2307s \----------------------------------------------------------------------------/ 2307s 2307s Yosys 0.33 (git sha1 2584903a060) 2307s 2307s 2307s -- Running command `read_verilog -DEVENT_CLK always_display.v; proc; opt_expr -mux_bool; clean' -- 2307s 2307s 1. Executing Verilog-2005 frontend: always_display.v 2307s Parsing Verilog input from `always_display.v' to AST representation. 2307s Generating RTLIL representation for module `\m'. 2307s Successfully finished Verilog frontend. 2307s 2307s 2. Executing PROC pass (convert processes to netlists). 2307s 2307s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Cleaned up 0 empty switches. 2307s 2307s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2307s Removed a total of 0 dead cases. 2307s 2307s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2307s Removed 1 redundant assignment. 2307s Promoted 1 assignment to connection. 2307s 2307s 2.4. Executing PROC_INIT pass (extract init attributes). 2307s 2307s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2307s 2307s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2307s Converted 0 switches. 2307s 2307s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2307s Creating decoders for process `\m.$proc$always_display.v:4$1'. 2307s 2307s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2307s 2307s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2307s + ../../yosys -p 'read_verilog yosys-always_display-clk-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk-2.v 2307s + diff yosys-always_display-clk-1.v yosys-always_display-clk-2.v 2307s + test_always_display clk_rst -DEVENT_CLK_RST 2307s + local subtest=clk_rst 2307s + shift 2307s + ../../yosys -p 'read_verilog -DEVENT_CLK_RST always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst-1.v 2307s 2307s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2307s 2307s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Removing empty process `m.$proc$always_display.v:4$1'. 2307s Cleaned up 0 empty switches. 2307s 2307s 2.12. Executing OPT_EXPR pass (perform const folding). 2307s Optimizing module m. 2307s 2307s 3. Executing OPT_EXPR pass (perform const folding). 2307s Optimizing module m. 2307s Removed 0 unused cells and 1 unused wires. 2307s 2307s -- Writing to `yosys-always_display-clk-1.v' using backend `verilog' -- 2307s 2307s 4. Executing Verilog backend. 2307s 2307s 4.1. Executing BMUXMAP pass. 2307s 2307s 4.2. Executing DEMUXMAP pass. 2307s Dumping module `\m'. 2307s 2307s End of script. Logfile hash: 0de35d2746, CPU: user 0.01s system 0.00s, MEM: 7.25 MB peak 2307s Yosys 0.33 (git sha1 2584903a060) 2307s Time spent: 35% 2x opt_expr (0 sec), 23% 1x clean (0 sec), ... 2307s 2307s /----------------------------------------------------------------------------\ 2307s | | 2307s | yosys -- Yosys Open SYnthesis Suite | 2307s | | 2307s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2307s | | 2307s | Permission to use, copy, modify, and/or distribute this software for any | 2307s | purpose with or without fee is hereby granted, provided that the above | 2307s | copyright notice and this permission notice appear in all copies. | 2307s | | 2307s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2307s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2307s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2307s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2307s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2307s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2307s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2307s | | 2307s \----------------------------------------------------------------------------/ 2307s 2307s Yosys 0.33 (git sha1 2584903a060) 2307s 2307s 2307s -- Running command `read_verilog yosys-always_display-clk-1.v; proc; opt_expr -mux_bool; clean' -- 2307s 2307s 1. Executing Verilog-2005 frontend: yosys-always_display-clk-1.v 2307s Parsing Verilog input from `yosys-always_display-clk-1.v' to AST representation. 2307s Generating RTLIL representation for module `\m'. 2307s Successfully finished Verilog frontend. 2307s 2307s 2. Executing PROC pass (convert processes to netlists). 2307s 2307s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk-1.v:18$1'. 2307s Cleaned up 1 empty switch. 2307s 2307s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2307s Removed a total of 0 dead cases. 2307s 2307s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2307s Removed 1 redundant assignment. 2307s Promoted 1 assignment to connection. 2307s 2307s 2.4. Executing PROC_INIT pass (extract init attributes). 2307s 2307s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2307s 2307s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2307s Converted 0 switches. 2307s 2307s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2307s Creating decoders for process `\m.$proc$yosys-always_display-clk-1.v:18$1'. 2307s 2307s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2307s 2307s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2307s 2307s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2307s 2307s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Removing empty process `m.$proc$yosys-always_display-clk-1.v:18$1'. 2307s Cleaned up 0 empty switches. 2307s 2307s 2.12. Executing OPT_EXPR pass (perform const folding). 2307s Optimizing module m. 2307s 2307s 3. Executing OPT_EXPR pass (perform const folding). 2307s Optimizing module m. 2307s Removed 0 unused cells and 1 unused wires. 2307s 2307s -- Writing to `yosys-always_display-clk-2.v' using backend `verilog' -- 2307s 2307s 4. Executing Verilog backend. 2307s 2307s 4.1. Executing BMUXMAP pass. 2307s 2307s 4.2. Executing DEMUXMAP pass. 2307s Dumping module `\m'. 2307s 2307s End of script. Logfile hash: e35e8bb689, CPU: user 0.00s system 0.00s, MEM: 7.25 MB peak 2307s Yosys 0.33 (git sha1 2584903a060) 2307s Time spent: 36% 2x opt_expr (0 sec), 23% 1x clean (0 sec), ... 2307s 2307s /----------------------------------------------------------------------------\ 2307s | | 2307s | yosys -- Yosys Open SYnthesis Suite | 2307s | | 2307s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2307s | | 2307s | Permission to use, copy, modify, and/or distribute this software for any | 2307s | purpose with or without fee is hereby granted, provided that the above | 2307s | copyright notice and this permission notice appear in all copies. | 2307s | | 2307s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2307s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2307s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2307s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2307s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2307s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2307s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2307s | | 2307s \----------------------------------------------------------------------------/ 2307s 2307s Yosys 0.33 (git sha1 2584903a060) 2307s 2307s 2307s -- Running command `read_verilog -DEVENT_CLK_RST always_display.v; proc; opt_expr -mux_bool; clean' -- 2307s 2307s 1. Executing Verilog-2005 frontend: always_display.v 2307s Parsing Verilog input from `always_display.v' to AST representation. 2307s Generating RTLIL representation for module `\m'. 2307s Successfully finished Verilog frontend. 2307s 2307s 2. Executing PROC pass (convert processes to netlists). 2307s 2307s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Cleaned up 0 empty switches. 2307s 2307s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2307s Removed a total of 0 dead cases. 2307s 2307s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2307s Removed 1 redundant assignment. 2307s Promoted 1 assignment to connection. 2307s 2307s 2.4. Executing PROC_INIT pass (extract init attributes). 2307s 2307s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2307s 2307s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2307s Converted 0 switches. 2307s 2307s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2307s Creating decoders for process `\m.$proc$always_display.v:7$1'. 2307s 2307s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2307s 2307s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2307s 2307s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2307s 2307s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Removing empty process `m.$proc$always_display.v:7$1'. 2307s Cleaned up 0 empty switches. 2307s 2307s 2.12. Executing OPT_EXPR pass (perform const folding). 2307s Optimizing module m. 2307s 2307s 3. Executing OPT_EXPR pass (perform const folding). 2307s Optimizing module m. 2307s Removed 0 unused cells and 1 unused wires. 2307s 2307s -- Writing to `yosys-always_display-clk_rst-1.v' using backend `verilog' -- 2307s 2307s 4. Executing Verilog backend. 2307s 2307s 4.1. Executing BMUXMAP pass. 2307s 2307s 4.2. Executing DEMUXMAP pass. 2307s Dumping module `\m'. 2307s 2307s End of script. Logfile hash: c95608ddf0, CPU: user 0.01s system 0.00s, MEM: 7.25 MB peak 2307s Yosys 0.33 (git sha1 2584903a060) 2307s Time spent: 36% 2x opt_expr (0 sec), 24% 1x clean (0 sec), ... 2307s + ../../yosys -p 'read_verilog yosys-always_display-clk_rst-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst-2.v 2307s + diff yosys-always_display-clk_rst-1.v yosys-always_display-clk_rst-2.v 2307s + test_always_display star -DEVENT_STAR 2307s + local subtest=star 2307s + shift 2307s + ../../yosys -p 'read_verilog -DEVENT_STAR always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star-1.v 2307s + ../../yosys -p 'read_verilog yosys-always_display-star-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star-2.v 2307s + diff yosys-always_display-star-1.v yosys-always_display-star-2.v 2307s + test_always_display clk_en -DEVENT_CLK -DCOND_EN 2307s + local subtest=clk_en 2307s + shift 2307s + ../../yosys -p 'read_verilog -DEVENT_CLK -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_en-1.v 2307s 2307s /----------------------------------------------------------------------------\ 2307s | | 2307s | yosys -- Yosys Open SYnthesis Suite | 2307s | | 2307s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2307s | | 2307s | Permission to use, copy, modify, and/or distribute this software for any | 2307s | purpose with or without fee is hereby granted, provided that the above | 2307s | copyright notice and this permission notice appear in all copies. | 2307s | | 2307s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2307s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2307s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2307s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2307s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2307s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2307s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2307s | | 2307s \----------------------------------------------------------------------------/ 2307s 2307s Yosys 0.33 (git sha1 2584903a060) 2307s 2307s 2307s -- Running command `read_verilog yosys-always_display-clk_rst-1.v; proc; opt_expr -mux_bool; clean' -- 2307s 2307s 1. Executing Verilog-2005 frontend: yosys-always_display-clk_rst-1.v 2307s Parsing Verilog input from `yosys-always_display-clk_rst-1.v' to AST representation. 2307s Generating RTLIL representation for module `\m'. 2307s Successfully finished Verilog frontend. 2307s 2307s 2. Executing PROC pass (convert processes to netlists). 2307s 2307s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_rst-1.v:18$1'. 2307s Cleaned up 1 empty switch. 2307s 2307s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2307s Removed a total of 0 dead cases. 2307s 2307s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2307s Removed 1 redundant assignment. 2307s Promoted 1 assignment to connection. 2307s 2307s 2.4. Executing PROC_INIT pass (extract init attributes). 2307s 2307s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2307s 2307s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2307s Converted 0 switches. 2307s 2307s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2307s Creating decoders for process `\m.$proc$yosys-always_display-clk_rst-1.v:18$1'. 2307s 2307s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2307s 2307s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2307s 2307s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2307s 2307s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Removing empty process `m.$proc$yosys-always_display-clk_rst-1.v:18$1'. 2307s Cleaned up 0 empty switches. 2307s 2307s 2.12. Executing OPT_EXPR pass (perform const folding). 2307s Optimizing module m. 2307s 2307s 3. Executing OPT_EXPR pass (perform const folding). 2307s Optimizing module m. 2307s Removed 0 unused cells and 1 unused wires. 2307s 2307s -- Writing to `yosys-always_display-clk_rst-2.v' using backend `verilog' -- 2307s 2307s 4. Executing Verilog backend. 2307s 2307s 4.1. Executing BMUXMAP pass. 2307s 2307s 4.2. Executing DEMUXMAP pass. 2307s Dumping module `\m'. 2307s 2307s End of script. Logfile hash: faf50513c3, CPU: user 0.01s system 0.00s, MEM: 7.25 MB peak 2307s Yosys 0.33 (git sha1 2584903a060) 2307s Time spent: 36% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ... 2307s 2307s /----------------------------------------------------------------------------\ 2307s | | 2307s | yosys -- Yosys Open SYnthesis Suite | 2307s | | 2307s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2307s | | 2307s | Permission to use, copy, modify, and/or distribute this software for any | 2307s | purpose with or without fee is hereby granted, provided that the above | 2307s | copyright notice and this permission notice appear in all copies. | 2307s | | 2307s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2307s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2307s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2307s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2307s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2307s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2307s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2307s | | 2307s \----------------------------------------------------------------------------/ 2307s 2307s Yosys 0.33 (git sha1 2584903a060) 2307s 2307s 2307s -- Running command `read_verilog -DEVENT_STAR always_display.v; proc; opt_expr -mux_bool; clean' -- 2307s 2307s 1. Executing Verilog-2005 frontend: always_display.v 2307s Parsing Verilog input from `always_display.v' to AST representation. 2307s Generating RTLIL representation for module `\m'. 2307s Successfully finished Verilog frontend. 2307s 2307s 2. Executing PROC pass (convert processes to netlists). 2307s 2307s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Cleaned up 0 empty switches. 2307s 2307s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2307s Removed a total of 0 dead cases. 2307s 2307s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2307s Removed 1 redundant assignment. 2307s Promoted 1 assignment to connection. 2307s 2307s 2.4. Executing PROC_INIT pass (extract init attributes). 2307s 2307s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2307s 2307s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2307s Converted 0 switches. 2307s 2307s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2307s Creating decoders for process `\m.$proc$always_display.v:10$1'. 2307s 2307s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2307s 2307s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2307s 2307s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2307s 2307s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Removing empty process `m.$proc$always_display.v:10$1'. 2307s Cleaned up 0 empty switches. 2307s 2307s 2.12. Executing OPT_EXPR pass (perform const folding). 2307s Optimizing module m. 2307s 2307s 3. Executing OPT_EXPR pass (perform const folding). 2307s Optimizing module m. 2307s Removed 0 unused cells and 1 unused wires. 2307s 2307s -- Writing to `yosys-always_display-star-1.v' using backend `verilog' -- 2307s 2307s 4. Executing Verilog backend. 2307s 2307s 4.1. Executing BMUXMAP pass. 2307s 2307s 4.2. Executing DEMUXMAP pass. 2307s Dumping module `\m'. 2307s 2307s End of script. Logfile hash: 7b2c5274a5, CPU: user 0.01s system 0.00s, MEM: 7.12 MB peak 2307s Yosys 0.33 (git sha1 2584903a060) 2307s Time spent: 37% 2x opt_expr (0 sec), 24% 1x clean (0 sec), ... 2307s 2307s /----------------------------------------------------------------------------\ 2307s | | 2307s | yosys -- Yosys Open SYnthesis Suite | 2307s | | 2307s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2307s | | 2307s | Permission to use, copy, modify, and/or distribute this software for any | 2307s | purpose with or without fee is hereby granted, provided that the above | 2307s | copyright notice and this permission notice appear in all copies. | 2307s | | 2307s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2307s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2307s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2307s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2307s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2307s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2307s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2307s | | 2307s \----------------------------------------------------------------------------/ 2307s 2307s Yosys 0.33 (git sha1 2584903a060) 2307s 2307s 2307s -- Running command `read_verilog yosys-always_display-star-1.v; proc; opt_expr -mux_bool; clean' -- 2307s 2307s 1. Executing Verilog-2005 frontend: yosys-always_display-star-1.v 2307s Parsing Verilog input from `yosys-always_display-star-1.v' to AST representation. 2307s Generating RTLIL representation for module `\m'. 2307s Successfully finished Verilog frontend. 2307s 2307s 2. Executing PROC pass (convert processes to netlists). 2307s 2307s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-star-1.v:18$1'. 2307s Cleaned up 1 empty switch. 2307s 2307s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2307s Removed a total of 0 dead cases. 2307s 2307s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2307s Removed 1 redundant assignment. 2307s Promoted 1 assignment to connection. 2307s 2307s 2.4. Executing PROC_INIT pass (extract init attributes). 2307s 2307s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2307s 2307s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2307s Converted 0 switches. 2307s 2307s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2307s Creating decoders for process `\m.$proc$yosys-always_display-star-1.v:18$1'. 2307s 2307s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2307s 2307s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2307s 2307s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2307s 2307s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Removing empty process `m.$proc$yosys-always_display-star-1.v:18$1'. 2307s Cleaned up 0 empty switches. 2307s 2307s 2.12. Executing OPT_EXPR pass (perform const folding). 2307s Optimizing module m. 2307s 2307s 3. Executing OPT_EXPR pass (perform const folding). 2307s Optimizing module m. 2307s Removed 0 unused cells and 1 unused wires. 2307s 2307s -- Writing to `yosys-always_display-star-2.v' using backend `verilog' -- 2307s 2307s 4. Executing Verilog backend. 2307s 2307s 4.1. Executing BMUXMAP pass. 2307s 2307s 4.2. Executing DEMUXMAP pass. 2307s Dumping module `\m'. 2307s 2307s End of script. Logfile hash: 8979c5de0b, CPU: user 0.00s system 0.01s, MEM: 7.25 MB peak 2307s Yosys 0.33 (git sha1 2584903a060) 2307s Time spent: 35% 2x opt_expr (0 sec), 24% 1x clean (0 sec), ... 2307s 2307s /----------------------------------------------------------------------------\ 2307s | | 2307s | yosys -- Yosys Open SYnthesis Suite | 2307s | | 2307s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2307s | | 2307s | Permission to use, copy, modify, and/or distribute this software for any | 2307s | purpose with or without fee is hereby granted, provided that the above | 2307s | copyright notice and this permission notice appear in all copies. | 2307s | | 2307s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2307s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2307s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2307s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2307s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2307s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2307s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2307s | | 2307s \----------------------------------------------------------------------------/ 2307s 2307s Yosys 0.33 (git sha1 2584903a060) 2307s 2307s 2307s -- Running command `read_verilog -DEVENT_CLK -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -- 2307s 2307s 1. Executing Verilog-2005 frontend: always_display.v 2307s Parsing Verilog input from `always_display.v' to AST representation. 2307s Generating RTLIL representation for module `\m'. 2307s Successfully finished Verilog frontend. 2307s 2307s 2. Executing PROC pass (convert processes to netlists). 2307s 2307s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Cleaned up 0 empty switches. 2307s 2307s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2307s Removed a total of 0 dead cases. 2307s 2307s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2307s Removed 0 redundant assignments. 2307s Promoted 0 assignments to connections. 2307s 2307s 2.4. Executing PROC_INIT pass (extract init attributes). 2307s 2307s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2307s 2307s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2307s Converted 0 switches. 2307s 2307s 2307s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2307s + ../../yosys -p 'read_verilog yosys-always_display-clk_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_en-2.v 2307s + diff yosys-always_display-clk_en-1.v yosys-always_display-clk_en-2.v 2307s + test_always_display clk_rst_en -DEVENT_CLK_RST -DCOND_EN 2307s + local subtest=clk_rst_en 2307s + shift 2307s + ../../yosys -p 'read_verilog -DEVENT_CLK_RST -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst_en-1.v 2307s Creating decoders for process `\m.$proc$always_display.v:4$1'. 2307s 1/1: $display$always_display.v:15$2_EN 2307s 2307s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2307s 2307s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2307s 2307s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2307s 2307s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:4$1'. 2307s Removing empty process `m.$proc$always_display.v:4$1'. 2307s Cleaned up 1 empty switch. 2307s 2307s 2.12. Executing OPT_EXPR pass (perform const folding). 2307s Optimizing module m. 2307s 2307s 3. Executing OPT_EXPR pass (perform const folding). 2307s Optimizing module m. 2307s 2307s Removed 0 unused cells and 3 unused wires. 2307s 2307s -- Writing to `yosys-always_display-clk_en-1.v' using backend `verilog' -- 2307s 2307s 4. Executing Verilog backend. 2307s 2307s 4.1. Executing BMUXMAP pass. 2307s 2307s 4.2. Executing DEMUXMAP pass. 2307s Dumping module `\m'. 2307s 2307s End of script. Logfile hash: 4f8a3b339c, CPU: user 0.01s system 0.00s, MEM: 7.38 MB peak 2307s Yosys 0.33 (git sha1 2584903a060) 2307s Time spent: 38% 2x opt_expr (0 sec), 23% 1x clean (0 sec), ... 2307s 2307s /----------------------------------------------------------------------------\ 2307s | | 2307s | yosys -- Yosys Open SYnthesis Suite | 2307s | | 2307s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2307s | | 2307s | Permission to use, copy, modify, and/or distribute this software for any | 2307s | purpose with or without fee is hereby granted, provided that the above | 2307s | copyright notice and this permission notice appear in all copies. | 2307s | | 2307s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2307s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2307s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2307s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2307s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2307s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2307s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2307s | | 2307s \----------------------------------------------------------------------------/ 2307s 2307s Yosys 0.33 (git sha1 2584903a060) 2307s 2307s 2307s -- Running command `read_verilog yosys-always_display-clk_en-1.v; proc; opt_expr -mux_bool; clean' -- 2307s 2307s 1. Executing Verilog-2005 frontend: yosys-always_display-clk_en-1.v 2307s Parsing Verilog input from `yosys-always_display-clk_en-1.v' to AST representation. 2307s Generating RTLIL representation for module `\m'. 2307s Successfully finished Verilog frontend. 2307s 2307s 2. Executing PROC pass (convert processes to netlists). 2307s 2307s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Cleaned up 0 empty switches. 2307s 2307s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2307s Removed a total of 0 dead cases. 2307s 2307s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2307s Removed 0 redundant assignments. 2307s Promoted 0 assignments to connections. 2307s 2307s 2.4. Executing PROC_INIT pass (extract init attributes). 2307s 2307s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2307s 2307s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2307s Converted 0 switches. 2307s 2307s 2307s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2307s Creating decoders for process `\m.$proc$yosys-always_display-clk_en-1.v:18$1'. 2307s 1/1: $write$yosys-always_display-clk_en-1.v:20$2_EN 2307s 2307s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2307s 2307s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2307s 2307s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2307s 2307s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_en-1.v:18$1'. 2307s Removing empty process `m.$proc$yosys-always_display-clk_en-1.v:18$1'. 2307s Cleaned up 1 empty switch. 2307s 2307s 2.12. Executing OPT_EXPR pass (perform const folding). 2307s Optimizing module m. 2307s 2307s 3. Executing OPT_EXPR pass (perform const folding). 2307s Optimizing module m. 2307s 2307s Removed 0 unused cells and 3 unused wires. 2307s 2307s -- Writing to `yosys-always_display-clk_en-2.v' using backend `verilog' -- 2307s 2307s 4. Executing Verilog backend. 2307s 2307s 4.1. Executing BMUXMAP pass. 2307s 2307s 4.2. Executing DEMUXMAP pass. 2307s Dumping module `\m'. 2307s 2307s End of script. Logfile hash: 51e7fa3902, CPU: user 0.01s system 0.00s, MEM: 7.38 MB peak 2307s Yosys 0.33 (git sha1 2584903a060) 2307s Time spent: 37% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ... 2307s 2307s /----------------------------------------------------------------------------\ 2307s | | 2307s | yosys -- Yosys Open SYnthesis Suite | 2307s | | 2307s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2307s | | 2307s | Permission to use, copy, modify, and/or distribute this software for any | 2307s | purpose with or without fee is hereby granted, provided that the above | 2307s | copyright notice and this permission notice appear in all copies. | 2307s | | 2307s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2307s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2307s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2307s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2307s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2307s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2307s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2307s | | 2307s \----------------------------------------------------------------------------/ 2307s 2307s Yosys 0.33 (git sha1 2584903a060) 2307s 2307s 2307s -- Running command `read_verilog -DEVENT_CLK_RST -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -- 2307s 2307s 1. Executing Verilog-2005 frontend: always_display.v 2307s Parsing Verilog input from `always_display.v' to AST representation. 2307s Generating RTLIL representation for module `\m'. 2307s Successfully finished Verilog frontend. 2307s 2307s 2. Executing PROC pass (convert processes to netlists). 2307s 2307s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Cleaned up 0 empty switches. 2307s 2307s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2307s Removed a total of 0 dead cases. 2307s 2307s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2307s Removed 0 redundant assignments. 2307s Promoted 0 assignments to connections. 2307s 2307s 2.4. Executing PROC_INIT pass (extract init attributes). 2307s 2307s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2307s 2307s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2307s Converted 0 switches. 2307s 2307s 2307s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2307s Creating decoders for process `\m.$proc$always_display.v:7$1'. 2307s 1/1: $display$always_display.v:15$2_EN 2307s 2307s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2307s 2307s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2307s 2307s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2307s 2307s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:7$1'. 2307s Removing empty process `m.$proc$always_display.v:7$1'. 2307s Cleaned up 1 empty switch. 2307s 2307s 2.12. Executing OPT_EXPR pass (perform const folding). 2307s Optimizing module m. 2307s 2307s 3. Executing OPT_EXPR pass (perform const folding). 2307s Optimizing module m. 2307s 2307s Removed 0 unused cells and 3 unused wires. 2307s 2307s -- Writing to `yosys-always_display-clk_rst_en-1.v' using backend `verilog' -- 2307s 2307s 4. Executing Verilog backend. 2307s 2307s 4.1. Executing BMUXMAP pass. 2307s 2307s 4.2. Executing DEMUXMAP pass. 2307s Dumping module `\m'. 2307s 2307s End of script. Logfile hash: f9b4876f33, CPU: user 0.01s system 0.00s, MEM: 7.50 MB peak 2307s Yosys 0.33 (git sha1 2584903a060) 2307s Time spent: 37% 2x opt_expr (0 sec), 23% 1x clean (0 sec), ... 2307s + ../../yosys -p 'read_verilog yosys-always_display-clk_rst_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst_en-2.v 2307s 2307s /----------------------------------------------------------------------------\ 2307s | | 2307s | yosys -- Yosys Open SYnthesis Suite | 2307s | | 2307s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2307s | | 2307s | Permission to use, copy, modify, and/or distribute this software for any | 2307s | purpose with or without fee is hereby granted, provided that the above | 2307s | copyright notice and this permission notice appear in all copies. | 2307s | | 2307s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2307s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2307s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2307s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2307s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2307s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2307s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2307s | | 2307s \----------------------------------------------------------------------------/ 2307s 2307s Yosys 0.33 (git sha1 2584903a060) 2307s 2307s 2307s -- Running command `read_verilog yosys-always_display-clk_rst_en-1.v; proc; opt_expr -mux_bool; clean' -- 2307s 2307s 1. Executing Verilog-2005 frontend: yosys-always_display-clk_rst_en-1.v 2307s + diff yosys-always_display-clk_rst_en-1.v yosys-always_display-clk_rst_en-2.v 2307s + test_always_display star_en -DEVENT_STAR -DCOND_EN 2307s + local subtest=star_en 2307s + shift 2307s + ../../yosys -p 'read_verilog -DEVENT_STAR -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star_en-1.v 2307s + ../../yosys -p 'read_verilog yosys-always_display-star_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star_en-2.v 2307s Parsing Verilog input from `yosys-always_display-clk_rst_en-1.v' to AST representation. 2307s Generating RTLIL representation for module `\m'. 2307s Successfully finished Verilog frontend. 2307s 2307s 2. Executing PROC pass (convert processes to netlists). 2307s 2307s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Cleaned up 0 empty switches. 2307s 2307s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2307s Removed a total of 0 dead cases. 2307s 2307s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2307s Removed 0 redundant assignments. 2307s Promoted 0 assignments to connections. 2307s 2307s 2.4. Executing PROC_INIT pass (extract init attributes). 2307s 2307s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2307s 2307s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2307s Converted 0 switches. 2307s 2307s 2307s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2307s Creating decoders for process `\m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'. 2307s 1/1: $write$yosys-always_display-clk_rst_en-1.v:20$2_EN 2307s 2307s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2307s 2307s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2307s 2307s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2307s 2307s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'. 2307s Removing empty process `m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'. 2307s Cleaned up 1 empty switch. 2307s 2307s 2.12. Executing OPT_EXPR pass (perform const folding). 2307s Optimizing module m. 2307s 2307s 3. Executing OPT_EXPR pass (perform const folding). 2307s Optimizing module m. 2307s 2307s Removed 0 unused cells and 3 unused wires. 2307s 2307s -- Writing to `yosys-always_display-clk_rst_en-2.v' using backend `verilog' -- 2307s 2307s 4. Executing Verilog backend. 2307s 2307s 4.1. Executing BMUXMAP pass. 2307s 2307s 4.2. Executing DEMUXMAP pass. 2307s Dumping module `\m'. 2307s 2307s End of script. Logfile hash: 0c4b4eaa9c, CPU: user 0.01s system 0.00s, MEM: 7.38 MB peak 2307s Yosys 0.33 (git sha1 2584903a060) 2307s Time spent: 38% 2x opt_expr (0 sec), 21% 1x clean (0 sec), ... 2307s 2307s /----------------------------------------------------------------------------\ 2307s | | 2307s | yosys -- Yosys Open SYnthesis Suite | 2307s | | 2307s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2307s | | 2307s | Permission to use, copy, modify, and/or distribute this software for any | 2307s | purpose with or without fee is hereby granted, provided that the above | 2307s | copyright notice and this permission notice appear in all copies. | 2307s | | 2307s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2307s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2307s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2307s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2307s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2307s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2307s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2307s | | 2307s \----------------------------------------------------------------------------/ 2307s 2307s Yosys 0.33 (git sha1 2584903a060) 2307s 2307s 2307s -- Running command `read_verilog -DEVENT_STAR -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -- 2307s 2307s 1. Executing Verilog-2005 frontend: always_display.v 2307s Parsing Verilog input from `always_display.v' to AST representation. 2307s Generating RTLIL representation for module `\m'. 2307s Successfully finished Verilog frontend. 2307s 2307s 2. Executing PROC pass (convert processes to netlists). 2307s 2307s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Cleaned up 0 empty switches. 2307s 2307s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2307s Removed a total of 0 dead cases. 2307s 2307s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2307s Removed 0 redundant assignments. 2307s Promoted 0 assignments to connections. 2307s 2307s 2.4. Executing PROC_INIT pass (extract init attributes). 2307s 2307s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2307s 2307s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2307s Converted 0 switches. 2307s 2307s 2307s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2307s Creating decoders for process `\m.$proc$always_display.v:10$1'. 2307s 1/1: $display$always_display.v:15$2_EN 2307s 2307s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2307s 2307s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2307s 2307s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2307s 2307s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:10$1'. 2307s Removing empty process `m.$proc$always_display.v:10$1'. 2307s Cleaned up 1 empty switch. 2307s 2307s 2.12. Executing OPT_EXPR pass (perform const folding). 2307s Optimizing module m. 2307s 2307s 3. Executing OPT_EXPR pass (perform const folding). 2307s Optimizing module m. 2307s 2307s Removed 0 unused cells and 3 unused wires. 2307s 2307s -- Writing to `yosys-always_display-star_en-1.v' using backend `verilog' -- 2307s 2307s 4. Executing Verilog backend. 2307s 2307s 4.1. Executing BMUXMAP pass. 2307s 2307s 4.2. Executing DEMUXMAP pass. 2307s Dumping module `\m'. 2307s 2307s End of script. Logfile hash: d6a7335726, CPU: user 0.01s system 0.00s, MEM: 7.25 MB peak 2307s Yosys 0.33 (git sha1 2584903a060) 2307s Time spent: 39% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ... 2307s 2307s /----------------------------------------------------------------------------\ 2307s | | 2307s | yosys -- Yosys Open SYnthesis Suite | 2307s | | 2307s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2307s | | 2307s | Permission to use, copy, modify, and/or distribute this software for any | 2307s | purpose with or without fee is hereby granted, provided that the above | 2307s | copyright notice and this permission notice appear in all copies. | 2307s | | 2307s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2307s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2307s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2307s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2307s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2307s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2307s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2307s | | 2307s \----------------------------------------------------------------------------/ 2307s 2307s Yosys 0.33 (git sha1 2584903a060) 2307s 2307s 2307s -- Running command `read_verilog yosys-always_display-star_en-1.v; proc; opt_expr -mux_bool; clean' -- 2307s 2307s 1. Executing Verilog-2005 frontend: yosys-always_display-star_en-1.v 2307s Parsing Verilog input from `yosys-always_display-star_en-1.v' to AST representation. 2307s Generating RTLIL representation for module `\m'. 2307s Successfully finished Verilog frontend. 2307s 2307s 2. Executing PROC pass (convert processes to netlists). 2307s 2307s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Cleaned up 0 empty switches. 2307s 2307s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2307s Removed a total of 0 dead cases. 2307s 2307s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2307s Removed 0 redundant assignments. 2307s Promoted 0 assignments to connections. 2307s 2307s 2.4. Executing PROC_INIT pass (extract init attributes). 2307s 2307s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2307s 2307s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2307s Converted 0 switches. 2307s 2307s 2307s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2307s Creating decoders for process `\m.$proc$yosys-always_display-star_en-1.v:18$1'. 2307s 1/1: $write$yosys-always_display-star_en-1.v:20$2_EN 2307s 2307s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2307s 2307s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2307s 2307s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2307s 2307s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-star_en-1.v:18$1'. 2307s Removing empty process `m.$proc$yosys-always_display-star_en-1.v:18$1'. 2307s Cleaned up 1 empty switch. 2307s 2307s 2.12. Executing OPT_EXPR pass (perform const folding). 2307s Optimizing module m. 2307s 2307s 3. Executing OPT_EXPR pass (perform const folding). 2307s Optimizing module m. 2307s 2307s Removed 0 unused cells and 3 unused wires. 2307s 2307s -- Writing to `yosys-always_display-star_en-2.v' using backend `verilog' -- 2307s 2307s 4. Executing Verilog backend. 2307s 2307s 4.1. Executing BMUXMAP pass. 2307s 2307s 4.2. Executing DEMUXMAP pass. 2307s Dumping module `\m'. 2307s 2307s End of script. Logfile hash: 18895a2046, CPU: user 0.01s system 0.00s, MEM: 7.25 MB peak 2307s Yosys 0.33 (git sha1 2584903a060) 2307s Time spent: 38% 2x opt_expr (0 sec), 21% 1x clean (0 sec), ... 2307s + diff yosys-always_display-star_en-1.v yosys-always_display-star_en-2.v 2307s + test_roundtrip dec_unsigned -DBASE_DEC -DSIGN= 2307s + local subtest=dec_unsigned 2307s + shift 2307s + ../../yosys -p 'read_verilog -DBASE_DEC -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-dec_unsigned-1.v 2307s 2307s /----------------------------------------------------------------------------\ 2307s | | 2307s | yosys -- Yosys Open SYnthesis Suite | 2307s | | 2307s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2307s | | 2307s | Permission to use, copy, modify, and/or distribute this software for any | 2307s | purpose with or without fee is hereby granted, provided that the above | 2307s | copyright notice and this permission notice appear in all copies. | 2307s | | 2307s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2307s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2307s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2307s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2307s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2307s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2307s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2307s | | 2307s \----------------------------------------------------------------------------/ 2307s 2307s Yosys 0.33 (git sha1 2584903a060) 2307s 2307s 2307s -- Running command `read_verilog -DBASE_DEC -DSIGN= roundtrip.v; proc; clean' -- 2307s 2307s 1. Executing Verilog-2005 frontend: roundtrip.v 2307s Parsing Verilog input from `roundtrip.v' to AST representation. 2307s Generating RTLIL representation for module `\m'. 2307s Successfully finished Verilog frontend. 2307s 2307s 2. Executing PROC pass (convert processes to netlists). 2307s 2307s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Cleaned up 0 empty switches. 2307s 2307s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2307s Removed a total of 0 dead cases. 2307s 2307s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2307s Removed 1 redundant assignment. 2307s Promoted 1 assignment to connection. 2307s 2307s 2.4. Executing PROC_INIT pass (extract init attributes). 2307s 2307s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2307s + ../../yosys -p 'read_verilog yosys-roundtrip-dec_unsigned-1.v; proc; clean' -o yosys-roundtrip-dec_unsigned-2.v 2307s 2307s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2307s Converted 0 switches. 2307s 2307s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2307s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2307s 2307s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2307s 2307s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2307s 2307s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2307s 2307s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Removing empty process `m.$proc$roundtrip.v:3$1'. 2307s Cleaned up 0 empty switches. 2307s 2307s 2.12. Executing OPT_EXPR pass (perform const folding). 2307s Optimizing module m. 2307s Removed 0 unused cells and 1 unused wires. 2307s 2307s -- Writing to `yosys-roundtrip-dec_unsigned-1.v' using backend `verilog' -- 2307s 2307s 3. Executing Verilog backend. 2307s 2307s 3.1. Executing BMUXMAP pass. 2307s 2307s 3.2. Executing DEMUXMAP pass. 2307s Dumping module `\m'. 2307s 2307s End of script. Logfile hash: bfb187b86d, CPU: user 0.00s system 0.01s, MEM: 7.25 MB peak 2307s Yosys 0.33 (git sha1 2584903a060) 2307s Time spent: 30% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 2307s 2307s /----------------------------------------------------------------------------\ 2307s | | 2307s | yosys -- Yosys Open SYnthesis Suite | 2307s | | 2307s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2307s | | 2307s | Permission to use, copy, modify, and/or distribute this software for any | 2307s | purpose with or without fee is hereby granted, provided that the above | 2307s | copyright notice and this permission notice appear in all copies. | 2307s | | 2307s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2307s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2307s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2307s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2307s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2307s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2307s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2307s | | 2307s \----------------------------------------------------------------------------/ 2307s 2307s Yosys 0.33 (git sha1 2584903a060) 2307s 2307s 2307s -- Running command `read_verilog yosys-roundtrip-dec_unsigned-1.v; proc; clean' -- 2307s 2307s 1. Executing Verilog-2005 frontend: yosys-roundtrip-dec_unsigned-1.v 2307s Parsing Verilog input from `yosys-roundtrip-dec_unsigned-1.v' to AST representation. 2307s Generating RTLIL representation for module `\m'. 2307s Successfully finished Verilog frontend. 2307s 2307s 2. Executing PROC pass (convert processes to netlists). 2307s 2307s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'. 2307s Cleaned up 1 empty switch. 2307s 2307s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2307s Removed a total of 0 dead cases. 2307s 2307s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2307s Removed 1 redundant assignment. 2307s Promoted 1 assignment to connection. 2307s 2307s 2.4. Executing PROC_INIT pass (extract init attributes). 2307s 2307s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2307s 2307s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2307s Converted 0 switches. 2307s 2307s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2307s Creating decoders for process `\m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'. 2307s 2307s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2307s 2307s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2307s 2307s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2307s 2307s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Removing empty process `m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'. 2307s Cleaned up 0 empty switches. 2307s 2307s 2.12. Executing OPT_EXPR pass (perform const folding). 2307s Optimizing module m. 2307s Removed 0 unused cells and 1 unused wires. 2307s 2307s -- Writing to `yosys-roundtrip-dec_unsigned-2.v' using backend `verilog' -- 2307s 2307s 3. Executing Verilog backend. 2307s 2307s 3.1. Executing BMUXMAP pass. 2307s 2307s 3.2. Executing DEMUXMAP pass. 2307s Dumping module `\m'. 2307s 2307s End of script. Logfile hash: 4be9539e85, CPU: user 0.00s system 0.01s, MEM: 7.25 MB peak 2307s Yosys 0.33 (git sha1 2584903a060) 2307s Time spent: 27% 1x clean (0 sec), 18% 1x opt_expr (0 sec), ... 2307s + diff yosys-roundtrip-dec_unsigned-1.v yosys-roundtrip-dec_unsigned-2.v 2307s + iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned roundtrip.v roundtrip_tb.v 2307s + ./iverilog-roundtrip-dec_unsigned 2307s + iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned-1 yosys-roundtrip-dec_unsigned-1.v roundtrip_tb.v 2307s + ./iverilog-roundtrip-dec_unsigned-1 2307s + iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned-2 yosys-roundtrip-dec_unsigned-2.v roundtrip_tb.v 2307s + ./iverilog-roundtrip-dec_unsigned-1 2307s + diff iverilog-roundtrip-dec_unsigned.log iverilog-roundtrip-dec_unsigned-1.log 2307s + diff iverilog-roundtrip-dec_unsigned-1.log iverilog-roundtrip-dec_unsigned-2.log 2307s + test_roundtrip dec_signed -DBASE_DEC -DSIGN=signed 2307s + local subtest=dec_signed 2307s + shift 2307s + ../../yosys -p 'read_verilog -DBASE_DEC -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-dec_signed-1.v 2307s 2307s /----------------------------------------------------------------------------\ 2307s | | 2307s | yosys -- Yosys Open SYnthesis Suite | 2307s | | 2307s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2307s | | 2307s | Permission to use, copy, modify, and/or distribute this software for any | 2307s | purpose with or without fee is hereby granted, provided that the above | 2307s | copyright notice and this permission notice appear in all copies. | 2307s | | 2307s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2307s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2307s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2307s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2307s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2307s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2307s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2307s | | 2307s \----------------------------------------------------------------------------/ 2307s 2307s Yosys 0.33 (git sha1 2584903a060) 2307s 2307s 2307s -- Running command `read_verilog -DBASE_DEC -DSIGN=signed roundtrip.v; proc; clean' -- 2307s 2307s 1. Executing Verilog-2005 frontend: roundtrip.v 2307s Parsing Verilog input from `roundtrip.v' to AST representation. 2307s Generating RTLIL representation for module `\m'. 2307s Successfully finished Verilog frontend. 2307s 2307s 2. Executing PROC pass (convert processes to netlists). 2307s 2307s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Cleaned up 0 empty switches. 2307s 2307s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2307s Removed a total of 0 dead cases. 2307s 2307s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2307s Removed 1 redundant assignment. 2307s Promoted 1 assignment to connection. 2307s 2307s 2.4. Executing PROC_INIT pass (extract init attributes). 2307s 2307s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2307s 2307s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2307s Converted 0 switches. 2307s 2307s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2307s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2307s 2307s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2307s 2307s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2307s 2307s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2307s 2307s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Removing empty process `m.$proc$roundtrip.v:3$1'. 2307s Cleaned up 0 empty switches. 2307s 2307s 2.12. Executing OPT_EXPR pass (perform const folding). 2307s Optimizing module m. 2307s Removed 0 unused cells and 1 unused wires. 2307s 2307s -- Writing to `yosys-roundtrip-dec_signed-1.v' using backend `verilog' -- 2307s 2307s 3. Executing Verilog backend. 2307s 2307s 3.1. Executing BMUXMAP pass. 2307s 2307s 3.2. Executing DEMUXMAP pass. 2307s Dumping module `\m'. 2307s 2307s End of script. Logfile hash: bbdfa5ca92, CPU: user 0.01s system 0.00s, MEM: 7.25 MB peak 2307s Yosys 0.33 (git sha1 2584903a060) 2307s Time spent: 30% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 2307s + ../../yosys -p 'read_verilog yosys-roundtrip-dec_signed-1.v; proc; clean' -o yosys-roundtrip-dec_signed-2.v 2307s 2307s /----------------------------------------------------------------------------\ 2307s | | 2307s | yosys -- Yosys Open SYnthesis Suite | 2307s | | 2307s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2307s | | 2307s | Permission to use, copy, modify, and/or distribute this software for any | 2307s | purpose with or without fee is hereby granted, provided that the above | 2307s | copyright notice and this permission notice appear in all copies. | 2307s | | 2307s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2307s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2307s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2307s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2307s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2307s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2307s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2307s | | 2307s \----------------------------------------------------------------------------/ 2307s 2307s Yosys 0.33 (git sha1 2584903a060) 2307s 2307s 2307s -- Running command `read_verilog yosys-roundtrip-dec_signed-1.v; proc; clean' -- 2307s 2307s 1. Executing Verilog-2005 frontend: yosys-roundtrip-dec_signed-1.v 2307s Parsing Verilog input from `yosys-roundtrip-dec_signed-1.v' to AST representation. 2307s Generating RTLIL representation for module `\m'. 2307s Successfully finished Verilog frontend. 2307s 2307s 2. Executing PROC pass (convert processes to netlists). 2307s 2307s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'. 2307s Cleaned up 1 empty switch. 2307s 2307s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2307s Removed a total of 0 dead cases. 2307s 2307s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2307s Removed 1 redundant assignment. 2307s Promoted 1 assignment to connection. 2307s 2307s 2.4. Executing PROC_INIT pass (extract init attributes). 2307s 2307s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2307s 2307s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2307s Converted 0 switches. 2307s 2307s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2307s Creating decoders for process `\m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'. 2307s 2307s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2307s 2307s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2307s 2307s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2307s 2307s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Removing empty process `m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'. 2307s Cleaned up 0 empty switches. 2307s 2307s 2.12. Executing OPT_EXPR pass (perform const folding). 2307s Optimizing module m. 2307s Removed 0 unused cells and 1 unused wires. 2307s 2307s -- Writing to `yosys-roundtrip-dec_signed-2.v' using backend `verilog' -- 2307s 2307s 3. Executing Verilog backend. 2307s 2307s 3.1. Executing BMUXMAP pass. 2307s 2307s 3.2. Executing DEMUXMAP pass. 2307s Dumping module `\m'. 2307s 2307s End of script. Logfile hash: b233de92a6, CPU: user 0.01s system 0.00s, MEM: 7.25 MB peak 2307s Yosys 0.33 (git sha1 2584903a060) 2307s Time spent: 28% 1x clean (0 sec), 19% 1x opt_expr (0 sec), ... 2307s + diff yosys-roundtrip-dec_signed-1.v yosys-roundtrip-dec_signed-2.v 2307s + iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed roundtrip.v roundtrip_tb.v 2307s + ./iverilog-roundtrip-dec_signed 2307s + iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed-1 yosys-roundtrip-dec_signed-1.v roundtrip_tb.v 2307s + ./iverilog-roundtrip-dec_signed-1 2307s + iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed-2 yosys-roundtrip-dec_signed-2.v roundtrip_tb.v 2307s + ./iverilog-roundtrip-dec_signed-1 2307s + diff iverilog-roundtrip-dec_signed.log iverilog-roundtrip-dec_signed-1.log 2307s + diff iverilog-roundtrip-dec_signed-1.log iverilog-roundtrip-dec_signed-2.log 2307s + test_roundtrip hex_unsigned -DBASE_HEX -DSIGN= 2307s + local subtest=hex_unsigned 2307s + shift 2307s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-hex_unsigned-1.v 2307s 2307s /----------------------------------------------------------------------------\ 2307s | | 2307s | yosys -- Yosys Open SYnthesis Suite | 2307s | | 2307s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2307s | | 2307s | Permission to use, copy, modify, and/or distribute this software for any | 2307s | purpose with or without fee is hereby granted, provided that the above | 2307s | copyright notice and this permission notice appear in all copies. | 2307s | | 2307s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2307s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2307s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2307s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2307s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2307s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2307s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2307s | | 2307s \----------------------------------------------------------------------------/ 2307s 2307s Yosys 0.33 (git sha1 2584903a060) 2307s 2307s 2307s -- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -- 2307s 2307s 1. Executing Verilog-2005 frontend: roundtrip.v 2307s Parsing Verilog input from `roundtrip.v' to AST representation. 2307s Generating RTLIL representation for module `\m'. 2307s Successfully finished Verilog frontend. 2307s 2307s 2. Executing PROC pass (convert processes to netlists). 2307s 2307s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Cleaned up 0 empty switches. 2307s 2307s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2307s Removed a total of 0 dead cases. 2307s 2307s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2307s Removed 1 redundant assignment. 2307s Promoted 1 assignment to connection. 2307s 2307s 2.4. Executing PROC_INIT pass (extract init attributes). 2307s 2307s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2307s 2307s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2307s Converted 0 switches. 2307s 2307s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2307s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2307s 2307s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2307s 2307s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2307s 2307s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2307s 2307s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Removing empty process `m.$proc$roundtrip.v:3$1'. 2307s Cleaned up 0 empty switches. 2307s 2307s 2.12. Executing OPT_EXPR pass (perform const folding). 2307s Optimizing module m. 2307s Removed 0 unused cells and 1 unused wires. 2307s 2307s -- Writing to `yosys-roundtrip-hex_unsigned-1.v' using backend `verilog' -- 2307s 2307s 3. Executing Verilog backend. 2307s 2307s 3.1. Executing BMUXMAP pass. 2307s 2307s 3.2. Executing DEMUXMAP pass. 2307s Dumping module `\m'. 2307s 2307s End of script. Logfile hash: 2377f2e106, CPU: user 0.01s system 0.00s, MEM: 7.25 MB peak 2307s Yosys 0.33 (git sha1 2584903a060) 2307s Time spent: 30% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... 2307s + ../../yosys -p 'read_verilog yosys-roundtrip-hex_unsigned-1.v; proc; clean' -o yosys-roundtrip-hex_unsigned-2.v 2307s 2307s /----------------------------------------------------------------------------\ 2307s | | 2307s | yosys -- Yosys Open SYnthesis Suite | 2307s | | 2307s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2307s | | 2307s | Permission to use, copy, modify, and/or distribute this software for any | 2307s | purpose with or without fee is hereby granted, provided that the above | 2307s | copyright notice and this permission notice appear in all copies. | 2307s | | 2307s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2307s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2307s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2307s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2307s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2307s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2307s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2307s | | 2307s \----------------------------------------------------------------------------/ 2307s 2307s Yosys 0.33 (git sha1 2584903a060) 2307s 2307s 2307s -- Running command `read_verilog yosys-roundtrip-hex_unsigned-1.v; proc; clean' -- 2307s 2307s 1. Executing Verilog-2005 frontend: yosys-roundtrip-hex_unsigned-1.v 2307s Parsing Verilog input from `yosys-roundtrip-hex_unsigned-1.v' to AST representation. 2307s Generating RTLIL representation for module `\m'. 2307s Successfully finished Verilog frontend. 2307s 2307s 2. Executing PROC pass (convert processes to netlists). 2307s 2307s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'. 2307s Cleaned up 1 empty switch. 2307s 2307s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2307s Removed a total of 0 dead cases. 2307s 2307s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2307s Removed 1 redundant assignment. 2307s Promoted 1 assignment to connection. 2307s 2307s 2.4. Executing PROC_INIT pass (extract init attributes). 2307s 2307s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2307s 2307s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2307s Converted 0 switches. 2307s 2307s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2307s Creating decoders for process `\m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'. 2307s 2307s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2307s 2307s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2307s 2307s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2307s 2307s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Removing empty process `m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'. 2307s Cleaned up 0 empty switches. 2307s 2307s 2.12. Executing OPT_EXPR pass (perform const folding). 2307s Optimizing module m. 2307s Removed 0 unused cells and 1 unused wires. 2307s 2307s -- Writing to `yosys-roundtrip-hex_unsigned-2.v' using backend `verilog' -- 2307s 2307s 3. Executing Verilog backend. 2307s 2307s 3.1. Executing BMUXMAP pass. 2307s 2307s 3.2. Executing DEMUXMAP pass. 2307s Dumping module `\m'. 2307s 2307s End of script. Logfile hash: 06bfea69c8, CPU: user 0.01s system 0.00s, MEM: 7.25 MB peak 2307s Yosys 0.33 (git sha1 2584903a060) 2307s Time spent: 29% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... 2307s + diff yosys-roundtrip-hex_unsigned-1.v yosys-roundtrip-hex_unsigned-2.v 2307s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned roundtrip.v roundtrip_tb.v 2307s + ./iverilog-roundtrip-hex_unsigned 2307s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned-1 yosys-roundtrip-hex_unsigned-1.v roundtrip_tb.v 2307s + ./iverilog-roundtrip-hex_unsigned-1 2307s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned-2 yosys-roundtrip-hex_unsigned-2.v roundtrip_tb.v 2307s + ./iverilog-roundtrip-hex_unsigned-1 2307s + diff iverilog-roundtrip-hex_unsigned.log iverilog-roundtrip-hex_unsigned-1.log 2307s + diff iverilog-roundtrip-hex_unsigned-1.log iverilog-roundtrip-hex_unsigned-2.log 2307s + test_roundtrip hex_signed -DBASE_HEX -DSIGN=signed 2307s + local subtest=hex_signed 2307s + shift 2307s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-hex_signed-1.v 2307s 2307s /----------------------------------------------------------------------------\ 2307s | | 2307s | yosys -- Yosys Open SYnthesis Suite | 2307s | | 2307s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2307s | | 2307s | Permission to use, copy, modify, and/or distribute this software for any | 2307s | purpose with or without fee is hereby granted, provided that the above | 2307s | copyright notice and this permission notice appear in all copies. | 2307s | | 2307s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2307s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2307s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2307s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2307s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2307s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2307s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2307s | | 2307s \----------------------------------------------------------------------------/ 2307s 2307s Yosys 0.33 (git sha1 2584903a060) 2307s 2307s 2307s -- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -- 2307s 2307s 1. Executing Verilog-2005 frontend: roundtrip.v 2307s Parsing Verilog input from `roundtrip.v' to AST representation. 2307s Generating RTLIL representation for module `\m'. 2307s Successfully finished Verilog frontend. 2307s 2307s 2. Executing PROC pass (convert processes to netlists). 2307s 2307s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Cleaned up 0 empty switches. 2307s 2307s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2307s Removed a total of 0 dead cases. 2307s 2307s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2307s Removed 1 redundant assignment. 2307s Promoted 1 assignment to connection. 2307s 2307s 2.4. Executing PROC_INIT pass (extract init attributes). 2307s 2307s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2307s 2307s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2307s Converted 0 switches. 2307s 2307s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2307s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2307s 2307s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2307s 2307s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2307s 2307s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2307s 2307s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Removing empty process `m.$proc$roundtrip.v:3$1'. 2307s Cleaned up 0 empty switches. 2307s 2307s 2.12. Executing OPT_EXPR pass (perform const folding). 2307s Optimizing module m. 2307s Removed 0 unused cells and 1 unused wires. 2307s 2307s -- Writing to `yosys-roundtrip-hex_signed-1.v' using backend `verilog' -- 2307s 2307s 3. Executing Verilog backend. 2307s 2307s 3.1. Executing BMUXMAP pass. 2307s 2307s 3.2. Executing DEMUXMAP pass. 2307s Dumping module `\m'. 2307s 2307s End of script. Logfile hash: 824c3b1e65, CPU: user 0.01s system 0.00s, MEM: 7.25 MB peak 2307s Yosys 0.33 (git sha1 2584903a060) 2307s Time spent: 30% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 2307s + ../../yosys -p 'read_verilog yosys-roundtrip-hex_signed-1.v; proc; clean' -o yosys-roundtrip-hex_signed-2.v 2307s 2307s /----------------------------------------------------------------------------\ 2307s | | 2307s | yosys -- Yosys Open SYnthesis Suite | 2307s | | 2307s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2307s | | 2307s | Permission to use, copy, modify, and/or distribute this software for any | 2307s | purpose with or without fee is hereby granted, provided that the above | 2307s | copyright notice and this permission notice appear in all copies. | 2307s | | 2307s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2307s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2307s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2307s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2307s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2307s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2307s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2307s | | 2307s \----------------------------------------------------------------------------/ 2307s 2307s Yosys 0.33 (git sha1 2584903a060) 2307s 2307s 2307s -- Running command `read_verilog yosys-roundtrip-hex_signed-1.v; proc; clean' -- 2307s 2307s 1. Executing Verilog-2005 frontend: yosys-roundtrip-hex_signed-1.v 2307s Parsing Verilog input from `yosys-roundtrip-hex_signed-1.v' to AST representation. 2307s Generating RTLIL representation for module `\m'. 2307s Successfully finished Verilog frontend. 2307s 2307s 2. Executing PROC pass (convert processes to netlists). 2307s 2307s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'. 2307s Cleaned up 1 empty switch. 2307s 2307s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2307s Removed a total of 0 dead cases. 2307s 2307s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2307s Removed 1 redundant assignment. 2307s Promoted 1 assignment to connection. 2307s 2307s 2.4. Executing PROC_INIT pass (extract init attributes). 2307s 2307s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2307s 2307s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2307s Converted 0 switches. 2307s 2307s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2307s Creating decoders for process `\m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'. 2307s 2307s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2307s 2307s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2307s 2307s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2307s 2307s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Removing empty process `m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'. 2307s Cleaned up 0 empty switches. 2307s 2307s 2.12. Executing OPT_EXPR pass (perform const folding). 2307s Optimizing module m. 2307s Removed 0 unused cells and 1 unused wires. 2307s 2307s -- Writing to `yosys-roundtrip-hex_signed-2.v' using backend `verilog' -- 2307s 2307s 3. Executing Verilog backend. 2307s 2307s 3.1. Executing BMUXMAP pass. 2307s 2307s 3.2. Executing DEMUXMAP pass. 2307s Dumping module `\m'. 2307s 2307s End of script. Logfile hash: f18b3fa15b, CPU: user 0.00s system 0.00s, MEM: 7.25 MB peak 2307s Yosys 0.33 (git sha1 2584903a060) 2307s Time spent: 29% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 2307s + diff yosys-roundtrip-hex_signed-1.v yosys-roundtrip-hex_signed-2.v 2307s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed roundtrip.v roundtrip_tb.v 2307s + ./iverilog-roundtrip-hex_signed 2307s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed-1 yosys-roundtrip-hex_signed-1.v roundtrip_tb.v 2307s + ./iverilog-roundtrip-hex_signed-1 2307s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed-2 yosys-roundtrip-hex_signed-2.v roundtrip_tb.v 2307s + ./iverilog-roundtrip-hex_signed-1 2307s + diff iverilog-roundtrip-hex_signed.log iverilog-roundtrip-hex_signed-1.log 2307s + diff iverilog-roundtrip-hex_signed-1.log iverilog-roundtrip-hex_signed-2.log 2307s + test_roundtrip oct_unsigned -DBASE_HEX -DSIGN= 2307s + local subtest=oct_unsigned 2307s + shift 2307s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-oct_unsigned-1.v 2307s 2307s /----------------------------------------------------------------------------\ 2307s | | 2307s | yosys -- Yosys Open SYnthesis Suite | 2307s | | 2307s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2307s | | 2307s | Permission to use, copy, modify, and/or distribute this software for any | 2307s | purpose with or without fee is hereby granted, provided that the above | 2307s | copyright notice and this permission notice appear in all copies. | 2307s | | 2307s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2307s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2307s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2307s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2307s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2307s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2307s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2307s | | 2307s \----------------------------------------------------------------------------/ 2307s 2307s Yosys 0.33 (git sha1 2584903a060) 2307s 2307s 2307s -- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -- 2307s 2307s 1. Executing Verilog-2005 frontend: roundtrip.v 2307s Parsing Verilog input from `roundtrip.v' to AST representation. 2307s Generating RTLIL representation for module `\m'. 2307s Successfully finished Verilog frontend. 2307s 2307s 2. Executing PROC pass (convert processes to netlists). 2307s 2307s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Cleaned up 0 empty switches. 2307s 2307s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2307s Removed a total of 0 dead cases. 2307s 2307s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2307s Removed 1 redundant assignment. 2307s Promoted 1 assignment to connection. 2307s 2307s 2.4. Executing PROC_INIT pass (extract init attributes). 2307s 2307s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2307s 2307s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2307s Converted 0 switches. 2307s 2307s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2307s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2307s 2307s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2307s 2307s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2307s 2307s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2307s 2307s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Removing empty process `m.$proc$roundtrip.v:3$1'. 2307s Cleaned up 0 empty switches. 2307s 2307s 2.12. Executing OPT_EXPR pass (perform const folding). 2307s Optimizing module m. 2307s Removed 0 unused cells and 1 unused wires. 2307s 2307s -- Writing to `yosys-roundtrip-oct_unsigned-1.v' using backend `verilog' -- 2307s 2307s 3. Executing Verilog backend. 2307s 2307s 3.1. Executing BMUXMAP pass. 2307s 2307s 3.2. Executing DEMUXMAP pass. 2307s Dumping module `\m'. 2307s 2307s End of script. Logfile hash: b768358a65, CPU: user 0.01s system 0.00s, MEM: 7.38 MB peak 2307s Yosys 0.33 (git sha1 2584903a060) 2307s Time spent: 29% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... 2307s + ../../yosys -p 'read_verilog yosys-roundtrip-oct_unsigned-1.v; proc; clean' -o yosys-roundtrip-oct_unsigned-2.v 2307s 2307s /----------------------------------------------------------------------------\ 2307s | | 2307s | yosys -- Yosys Open SYnthesis Suite | 2307s | | 2307s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2307s | | 2307s | Permission to use, copy, modify, and/or distribute this software for any | 2307s | purpose with or without fee is hereby granted, provided that the above | 2307s | copyright notice and this permission notice appear in all copies. | 2307s | | 2307s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2307s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2307s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2307s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2307s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2307s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2307s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2307s | | 2307s \----------------------------------------------------------------------------/ 2307s 2307s Yosys 0.33 (git sha1 2584903a060) 2307s 2307s 2307s -- Running command `read_verilog yosys-roundtrip-oct_unsigned-1.v; proc; clean' -- 2307s 2307s 1. Executing Verilog-2005 frontend: yosys-roundtrip-oct_unsigned-1.v 2307s Parsing Verilog input from `yosys-roundtrip-oct_unsigned-1.v' to AST representation. 2307s Generating RTLIL representation for module `\m'. 2307s Successfully finished Verilog frontend. 2307s 2307s 2. Executing PROC pass (convert processes to netlists). 2307s 2307s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'. 2307s Cleaned up 1 empty switch. 2307s 2307s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2307s Removed a total of 0 dead cases. 2307s 2307s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2307s Removed 1 redundant assignment. 2307s Promoted 1 assignment to connection. 2307s 2307s 2.4. Executing PROC_INIT pass (extract init attributes). 2307s 2307s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2307s 2307s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2307s Converted 0 switches. 2307s 2307s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2307s Creating decoders for process `\m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'. 2307s 2307s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2307s 2307s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2307s 2307s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2307s 2307s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Removing empty process `m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'. 2307s Cleaned up 0 empty switches. 2307s 2307s 2.12. Executing OPT_EXPR pass (perform const folding). 2307s Optimizing module m. 2307s Removed 0 unused cells and 1 unused wires. 2307s 2307s -- Writing to `yosys-roundtrip-oct_unsigned-2.v' using backend `verilog' -- 2307s 2307s 3. Executing Verilog backend. 2307s 2307s 3.1. Executing BMUXMAP pass. 2307s 2307s 3.2. Executing DEMUXMAP pass. 2307s Dumping module `\m'. 2307s 2307s End of script. Logfile hash: 762621cd95, CPU: user 0.01s system 0.00s, MEM: 7.25 MB peak 2307s Yosys 0.33 (git sha1 2584903a060) 2307s Time spent: 28% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... 2307s + diff yosys-roundtrip-oct_unsigned-1.v yosys-roundtrip-oct_unsigned-2.v 2307s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned roundtrip.v roundtrip_tb.v 2307s + ./iverilog-roundtrip-oct_unsigned 2307s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned-1 yosys-roundtrip-oct_unsigned-1.v roundtrip_tb.v 2307s + ./iverilog-roundtrip-oct_unsigned-1 2307s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned-2 yosys-roundtrip-oct_unsigned-2.v roundtrip_tb.v 2307s + ./iverilog-roundtrip-oct_unsigned-1 2307s + diff iverilog-roundtrip-oct_unsigned.log iverilog-roundtrip-oct_unsigned-1.log 2307s + diff iverilog-roundtrip-oct_unsigned-1.log iverilog-roundtrip-oct_unsigned-2.log 2307s + test_roundtrip oct_signed -DBASE_HEX -DSIGN=signed 2307s + local subtest=oct_signed 2307s + shift 2307s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-oct_signed-1.v 2307s 2307s /----------------------------------------------------------------------------\ 2307s | | 2307s | yosys -- Yosys Open SYnthesis Suite | 2307s | | 2307s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2307s | | 2307s | Permission to use, copy, modify, and/or distribute this software for any | 2307s | purpose with or without fee is hereby granted, provided that the above | 2307s | copyright notice and this permission notice appear in all copies. | 2307s | | 2307s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2307s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2307s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2307s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2307s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2307s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2307s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2307s | | 2307s \----------------------------------------------------------------------------/ 2307s 2307s Yosys 0.33 (git sha1 2584903a060) 2307s 2307s 2307s -- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -- 2307s 2307s 1. Executing Verilog-2005 frontend: roundtrip.v 2307s Parsing Verilog input from `roundtrip.v' to AST representation. 2307s Generating RTLIL representation for module `\m'. 2307s Successfully finished Verilog frontend. 2307s 2307s 2. Executing PROC pass (convert processes to netlists). 2307s 2307s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Cleaned up 0 empty switches. 2307s 2307s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2307s Removed a total of 0 dead cases. 2307s 2307s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2307s Removed 1 redundant assignment. 2307s Promoted 1 assignment to connection. 2307s 2307s 2.4. Executing PROC_INIT pass (extract init attributes). 2307s 2307s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2307s 2307s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2307s Converted 0 switches. 2307s 2307s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2307s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2307s 2307s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2307s 2307s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2307s 2307s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2307s 2307s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Removing empty process `m.$proc$roundtrip.v:3$1'. 2307s Cleaned up 0 empty switches. 2307s 2307s 2.12. Executing OPT_EXPR pass (perform const folding). 2307s Optimizing module m. 2307s Removed 0 unused cells and 1 unused wires. 2307s 2307s -- Writing to `yosys-roundtrip-oct_signed-1.v' using backend `verilog' -- 2307s 2307s 3. Executing Verilog backend. 2307s 2307s 3.1. Executing BMUXMAP pass. 2307s 2307s 3.2. Executing DEMUXMAP pass. 2307s Dumping module `\m'. 2307s 2307s End of script. Logfile hash: 7ec82b15e3, CPU: user 0.01s system 0.00s, MEM: 7.25 MB peak 2307s Yosys 0.33 (git sha1 2584903a060) 2307s Time spent: 29% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 2307s + ../../yosys -p 'read_verilog yosys-roundtrip-oct_signed-1.v; proc; clean' -o yosys-roundtrip-oct_signed-2.v 2307s 2307s /----------------------------------------------------------------------------\ 2307s | | 2307s | yosys -- Yosys Open SYnthesis Suite | 2307s | | 2307s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2307s | | 2307s | Permission to use, copy, modify, and/or distribute this software for any | 2307s | purpose with or without fee is hereby granted, provided that the above | 2307s | copyright notice and this permission notice appear in all copies. | 2307s | | 2307s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2307s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2307s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2307s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2307s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2307s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2307s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2307s | | 2307s \----------------------------------------------------------------------------/ 2307s 2307s Yosys 0.33 (git sha1 2584903a060) 2307s 2307s 2307s -- Running command `read_verilog yosys-roundtrip-oct_signed-1.v; proc; clean' -- 2307s 2307s 1. Executing Verilog-2005 frontend: yosys-roundtrip-oct_signed-1.v 2307s Parsing Verilog input from `yosys-roundtrip-oct_signed-1.v' to AST representation. 2307s Generating RTLIL representation for module `\m'. 2307s Successfully finished Verilog frontend. 2307s 2307s 2. Executing PROC pass (convert processes to netlists). 2307s 2307s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'. 2307s Cleaned up 1 empty switch. 2307s 2307s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2307s Removed a total of 0 dead cases. 2307s 2307s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2307s Removed 1 redundant assignment. 2307s Promoted 1 assignment to connection. 2307s 2307s 2.4. Executing PROC_INIT pass (extract init attributes). 2307s 2307s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2307s 2307s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2307s Converted 0 switches. 2307s 2307s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2307s Creating decoders for process `\m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'. 2307s 2307s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2307s 2307s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2307s 2307s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2307s 2307s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Removing empty process `m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'. 2307s Cleaned up 0 empty switches. 2307s 2307s 2.12. Executing OPT_EXPR pass (perform const folding). 2307s Optimizing module m. 2307s Removed 0 unused cells and 1 unused wires. 2307s 2307s -- Writing to `yosys-roundtrip-oct_signed-2.v' using backend `verilog' -- 2307s 2307s 3. Executing Verilog backend. 2307s 2307s 3.1. Executing BMUXMAP pass. 2307s 2307s 3.2. Executing DEMUXMAP pass. 2307s Dumping module `\m'. 2307s 2307s End of script. Logfile hash: a747b9bd4f, CPU: user 0.01s system 0.00s, MEM: 7.25 MB peak 2307s Yosys 0.33 (git sha1 2584903a060) 2307s Time spent: 29% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 2307s + diff yosys-roundtrip-oct_signed-1.v yosys-roundtrip-oct_signed-2.v 2307s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed roundtrip.v roundtrip_tb.v 2307s + ./iverilog-roundtrip-oct_signed 2307s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed-1 yosys-roundtrip-oct_signed-1.v roundtrip_tb.v 2307s + ./iverilog-roundtrip-oct_signed-1 2307s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed-2 yosys-roundtrip-oct_signed-2.v roundtrip_tb.v 2307s + ./iverilog-roundtrip-oct_signed-1 2307s + diff iverilog-roundtrip-oct_signed.log iverilog-roundtrip-oct_signed-1.log 2307s + diff iverilog-roundtrip-oct_signed-1.log iverilog-roundtrip-oct_signed-2.log 2307s + test_roundtrip bin_unsigned -DBASE_HEX -DSIGN= 2307s + local subtest=bin_unsigned 2307s + shift 2307s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-bin_unsigned-1.v 2307s 2307s /----------------------------------------------------------------------------\ 2307s | | 2307s | yosys -- Yosys Open SYnthesis Suite | 2307s | | 2307s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2307s | | 2307s | Permission to use, copy, modify, and/or distribute this software for any | 2307s | purpose with or without fee is hereby granted, provided that the above | 2307s | copyright notice and this permission notice appear in all copies. | 2307s | | 2307s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2307s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2307s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2307s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2307s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2307s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2307s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2307s | | 2307s \----------------------------------------------------------------------------/ 2307s 2307s Yosys 0.33 (git sha1 2584903a060) 2307s 2307s 2307s -- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -- 2307s 2307s 1. Executing Verilog-2005 frontend: roundtrip.v 2307s Parsing Verilog input from `roundtrip.v' to AST representation. 2307s Generating RTLIL representation for module `\m'. 2307s Successfully finished Verilog frontend. 2307s 2307s 2. Executing PROC pass (convert processes to netlists). 2307s 2307s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Cleaned up 0 empty switches. 2307s 2307s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2307s Removed a total of 0 dead cases. 2307s 2307s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2307s Removed 1 redundant assignment. 2307s Promoted 1 assignment to connection. 2307s 2307s 2.4. Executing PROC_INIT pass (extract init attributes). 2307s 2307s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2307s 2307s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2307s Converted 0 switches. 2307s 2307s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2307s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2307s 2307s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2307s 2307s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2307s 2307s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2307s 2307s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Removing empty process `m.$proc$roundtrip.v:3$1'. 2307s Cleaned up 0 empty switches. 2307s 2307s 2.12. Executing OPT_EXPR pass (perform const folding). 2307s Optimizing module m. 2307s Removed 0 unused cells and 1 unused wires. 2307s 2307s -- Writing to `yosys-roundtrip-bin_unsigned-1.v' using backend `verilog' -- 2307s 2307s 3. Executing Verilog backend. 2307s 2307s 3.1. Executing BMUXMAP pass. 2307s 2307s 3.2. Executing DEMUXMAP pass. 2307s Dumping module `\m'. 2307s 2307s End of script. Logfile hash: 270b564880, CPU: user 0.01s system 0.00s, MEM: 7.25 MB peak 2307s Yosys 0.33 (git sha1 2584903a060) 2307s Time spent: 27% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 2307s + ../../yosys -p 'read_verilog yosys-roundtrip-bin_unsigned-1.v; proc; clean' -o yosys-roundtrip-bin_unsigned-2.v 2307s 2307s /----------------------------------------------------------------------------\ 2307s | | 2307s | yosys -- Yosys Open SYnthesis Suite | 2307s | | 2307s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2307s | | 2307s | Permission to use, copy, modify, and/or distribute this software for any | 2307s | purpose with or without fee is hereby granted, provided that the above | 2307s | copyright notice and this permission notice appear in all copies. | 2307s | | 2307s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2307s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2307s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2307s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2307s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2307s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2307s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2307s | | 2307s \----------------------------------------------------------------------------/ 2307s 2307s Yosys 0.33 (git sha1 2584903a060) 2307s 2307s 2307s -- Running command `read_verilog yosys-roundtrip-bin_unsigned-1.v; proc; clean' -- 2307s 2307s 1. Executing Verilog-2005 frontend: yosys-roundtrip-bin_unsigned-1.v 2307s Parsing Verilog input from `yosys-roundtrip-bin_unsigned-1.v' to AST representation. 2307s Generating RTLIL representation for module `\m'. 2307s Successfully finished Verilog frontend. 2307s 2307s 2. Executing PROC pass (convert processes to netlists). 2307s 2307s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'. 2307s Cleaned up 1 empty switch. 2307s 2307s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2307s Removed a total of 0 dead cases. 2307s 2307s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2307s Removed 1 redundant assignment. 2307s Promoted 1 assignment to connection. 2307s 2307s 2.4. Executing PROC_INIT pass (extract init attributes). 2307s 2307s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2307s 2307s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2307s Converted 0 switches. 2307s 2307s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2307s Creating decoders for process `\m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'. 2307s 2307s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2307s 2307s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2307s 2307s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2307s 2307s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Removing empty process `m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'. 2307s Cleaned up 0 empty switches. 2307s 2307s 2.12. Executing OPT_EXPR pass (perform const folding). 2307s Optimizing module m. 2307s Removed 0 unused cells and 1 unused wires. 2307s 2307s -- Writing to `yosys-roundtrip-bin_unsigned-2.v' using backend `verilog' -- 2307s 2307s 3. Executing Verilog backend. 2307s 2307s 3.1. Executing BMUXMAP pass. 2307s 2307s 3.2. Executing DEMUXMAP pass. 2307s Dumping module `\m'. 2307s 2307s End of script. Logfile hash: dc9f56cb10, CPU: user 0.00s system 0.00s, MEM: 7.25 MB peak 2307s Yosys 0.33 (git sha1 2584903a060) 2307s Time spent: 28% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... 2307s + diff yosys-roundtrip-bin_unsigned-1.v yosys-roundtrip-bin_unsigned-2.v 2307s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned roundtrip.v roundtrip_tb.v 2307s + ./iverilog-roundtrip-bin_unsigned 2307s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned-1 yosys-roundtrip-bin_unsigned-1.v roundtrip_tb.v 2307s + ./iverilog-roundtrip-bin_unsigned-1 2307s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned-2 yosys-roundtrip-bin_unsigned-2.v roundtrip_tb.v 2307s + ./iverilog-roundtrip-bin_unsigned-1 2307s + diff iverilog-roundtrip-bin_unsigned.log iverilog-roundtrip-bin_unsigned-1.log 2307s + diff iverilog-roundtrip-bin_unsigned-1.log iverilog-roundtrip-bin_unsigned-2.log 2307s + test_roundtrip bin_signed -DBASE_HEX -DSIGN=signed 2307s + local subtest=bin_signed 2307s + shift 2307s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-bin_signed-1.v 2307s 2307s /----------------------------------------------------------------------------\ 2307s | | 2307s | yosys -- Yosys Open SYnthesis Suite | 2307s | | 2307s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2307s | | 2307s | Permission to use, copy, modify, and/or distribute this software for any | 2307s | purpose with or without fee is hereby granted, provided that the above | 2307s | copyright notice and this permission notice appear in all copies. | 2307s | | 2307s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2307s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2307s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2307s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2307s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2307s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2307s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2307s | | 2307s \----------------------------------------------------------------------------/ 2307s 2307s Yosys 0.33 (git sha1 2584903a060) 2307s 2307s 2307s -- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -- 2307s 2307s 1. Executing Verilog-2005 frontend: roundtrip.v 2307s Parsing Verilog input from `roundtrip.v' to AST representation. 2307s Generating RTLIL representation for module `\m'. 2307s Successfully finished Verilog frontend. 2307s 2307s 2. Executing PROC pass (convert processes to netlists). 2307s 2307s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Cleaned up 0 empty switches. 2307s 2307s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2307s Removed a total of 0 dead cases. 2307s 2307s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2307s Removed 1 redundant assignment. 2307s Promoted 1 assignment to connection. 2307s 2307s 2.4. Executing PROC_INIT pass (extract init attributes). 2307s 2307s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2307s 2307s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2307s Converted 0 switches. 2307s 2307s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2307s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2307s 2307s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2307s 2307s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2307s 2307s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2307s 2307s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Removing empty process `m.$proc$roundtrip.v:3$1'. 2307s Cleaned up 0 empty switches. 2307s 2307s 2.12. Executing OPT_EXPR pass (perform const folding). 2307s Optimizing module m. 2307s Removed 0 unused cells and 1 unused wires. 2307s 2307s -- Writing to `yosys-roundtrip-bin_signed-1.v' using backend `verilog' -- 2307s 2307s 3. Executing Verilog backend. 2307s 2307s 3.1. Executing BMUXMAP pass. 2307s 2307s 3.2. Executing DEMUXMAP pass. 2307s Dumping module `\m'. 2307s 2307s End of script. Logfile hash: 7709253822, CPU: user 0.01s system 0.00s, MEM: 7.25 MB peak 2307s Yosys 0.33 (git sha1 2584903a060) 2307s Time spent: 28% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 2307s + ../../yosys -p 'read_verilog yosys-roundtrip-bin_signed-1.v; proc; clean' -o yosys-roundtrip-bin_signed-2.v 2307s 2307s /----------------------------------------------------------------------------\ 2307s | | 2307s | yosys -- Yosys Open SYnthesis Suite | 2307s | | 2307s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2307s | | 2307s | Permission to use, copy, modify, and/or distribute this software for any | 2307s | purpose with or without fee is hereby granted, provided that the above | 2307s | copyright notice and this permission notice appear in all copies. | 2307s | | 2307s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2307s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2307s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2307s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2307s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2307s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2307s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2307s | | 2307s \----------------------------------------------------------------------------/ 2307s 2307s Yosys 0.33 (git sha1 2584903a060) 2307s 2307s 2307s -- Running command `read_verilog yosys-roundtrip-bin_signed-1.v; proc; clean' -- 2307s 2307s 1. Executing Verilog-2005 frontend: yosys-roundtrip-bin_signed-1.v 2307s Parsing Verilog input from `yosys-roundtrip-bin_signed-1.v' to AST representation. 2307s Generating RTLIL representation for module `\m'. 2307s Successfully finished Verilog frontend. 2307s 2307s 2. Executing PROC pass (convert processes to netlists). 2307s 2307s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'. 2307s Cleaned up 1 empty switch. 2307s 2307s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2307s Removed a total of 0 dead cases. 2307s 2307s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2307s Removed 1 redundant assignment. 2307s Promoted 1 assignment to connection. 2307s 2307s 2.4. Executing PROC_INIT pass (extract init attributes). 2307s 2307s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2307s 2307s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2307s Converted 0 switches. 2307s 2307s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2307s Creating decoders for process `\m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'. 2307s 2307s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2307s 2307s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2307s 2307s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2307s 2307s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Removing empty process `m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'. 2307s Cleaned up 0 empty switches. 2307s 2307s 2.12. Executing OPT_EXPR pass (perform const folding). 2307s Optimizing module m. 2307s Removed 0 unused cells and 1 unused wires. 2307s 2307s -- Writing to `yosys-roundtrip-bin_signed-2.v' using backend `verilog' -- 2307s 2307s 3. Executing Verilog backend. 2307s 2307s 3.1. Executing BMUXMAP pass. 2307s 2307s 3.2. Executing DEMUXMAP pass. 2307s Dumping module `\m'. 2307s 2307s End of script. Logfile hash: 7e2d8271c4, CPU: user 0.01s system 0.00s, MEM: 7.25 MB peak 2307s Yosys 0.33 (git sha1 2584903a060) 2307s Time spent: 28% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 2307s + diff yosys-roundtrip-bin_signed-1.v yosys-roundtrip-bin_signed-2.v 2307s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed roundtrip.v roundtrip_tb.v 2307s + ./iverilog-roundtrip-bin_signed 2307s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed-1 yosys-roundtrip-bin_signed-1.v roundtrip_tb.v 2307s + ./iverilog-roundtrip-bin_signed-1 2307s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed-2 yosys-roundtrip-bin_signed-2.v roundtrip_tb.v 2307s + ./iverilog-roundtrip-bin_signed-1 2307s + diff iverilog-roundtrip-bin_signed.log iverilog-roundtrip-bin_signed-1.log 2307s + diff iverilog-roundtrip-bin_signed-1.log iverilog-roundtrip-bin_signed-2.log 2307s + test_cxxrtl always_full 2307s + local subtest=always_full 2307s + shift 2307s + ../../yosys -p 'read_verilog always_full.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_full.cc' 2307s 2307s /----------------------------------------------------------------------------\ 2307s | | 2307s | yosys -- Yosys Open SYnthesis Suite | 2307s | | 2307s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2307s | | 2307s | Permission to use, copy, modify, and/or distribute this software for any | 2307s | purpose with or without fee is hereby granted, provided that the above | 2307s | copyright notice and this permission notice appear in all copies. | 2307s | | 2307s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2307s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2307s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2307s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2307s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2307s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2307s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2307s | | 2307s \----------------------------------------------------------------------------/ 2307s 2307s Yosys 0.33 (git sha1 2584903a060) 2307s 2307s 2307s -- Running command `read_verilog always_full.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_full.cc' -- 2307s 2307s 1. Executing Verilog-2005 frontend: always_full.v 2307s Parsing Verilog input from `always_full.v' to AST representation. 2307s Generating RTLIL representation for module `\always_full'. 2307s Successfully finished Verilog frontend. 2307s 2307s 2. Executing PROC pass (convert processes to netlists). 2307s 2307s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Cleaned up 0 empty switches. 2307s 2307s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2307s Removed a total of 0 dead cases. 2307s 2307s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2307s Removed 207 redundant assignments. 2307s Promoted 207 assignments to connections. 2307s 2307s 2.4. Executing PROC_INIT pass (extract init attributes). 2307s 2307s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2307s 2307s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2307s Converted 0 switches. 2307s 2307s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2307s Creating decoders for process `\always_full.$proc$always_full.v:3$1'. 2307s 2307s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2307s 2307s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2307s 2307s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2307s 2307s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Removing empty process `always_full.$proc$always_full.v:3$1'. 2307s Cleaned up 0 empty switches. 2307s 2307s 2.12. Executing OPT_EXPR pass (perform const folding). 2307s Optimizing module always_full. 2307s Removed 0 unused cells and 207 unused wires. 2307s 2307s 3. Executing CXXRTL backend. 2307s 2307s 3.1. Executing HIERARCHY pass (managing design hierarchy). 2307s 2307s 3.1.1. Finding top of design hierarchy.. 2307s root of 0 design levels: always_full 2307s Automatically selected always_full as design top module. 2307s 2307s 3.1.2. Analyzing design hierarchy.. 2307s Top module: \always_full 2307s 2307s 3.1.3. Analyzing design hierarchy.. 2307s Top module: \always_full 2307s Removed 0 unused modules. 2307s 2307s 3.2. Executing FLATTEN pass (flatten design). 2307s 2307s 3.3. Executing PROC pass (convert processes to netlists). 2307s 2307s 3.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Cleaned up 0 empty switches. 2307s 2307s 3.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2307s Removed a total of 0 dead cases. 2307s 2307s 3.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2307s Removed 0 redundant assignments. 2307s Promoted 0 assignments to connections. 2307s 2307s 3.3.4. Executing PROC_INIT pass (extract init attributes). 2307s 2307s 3.3.5. Executing PROC_ARST pass (detect async resets in processes). 2307s 2307s 3.3.6. Executing PROC_ROM pass (convert switches to ROMs). 2307s Converted 0 switches. 2307s 2307s 3.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2307s 2307s 3.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2307s 2307s 3.3.9. Executing PROC_DFF pass (convert process syncs to FFs). 2307s 2307s 3.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2307s 2307s 3.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2307s Cleaned up 0 empty switches. 2307s 2307s 3.3.12. Executing OPT_EXPR pass (perform const folding). 2307s Optimizing module always_full. 2307s 2307s 2307s 2307s End of script. Logfile hash: 6abd135c0a, CPU: user 0.03s system 0.00s, MEM: 8.25 MB peak 2307s Yosys 0.33 (git sha1 2584903a060) 2307s Time spent: 23% 2x read_verilog (0 sec), 22% 2x opt_expr (0 sec), ... 2307s + gcc -std=c++11 -o yosys-always_full -I../.. always_full_tb.cc -lstdc++ 2309s + ./yosys-always_full 2309s + iverilog -o iverilog-always_full always_full.v always_full_tb.v 2309s + ./iverilog-always_full 2309s + grep -v '\$finish called' 2309s + diff iverilog-always_full.log yosys-always_full.log 2309s + test_cxxrtl always_comb 2309s + local subtest=always_comb 2309s + shift 2309s + ../../yosys -p 'read_verilog always_comb.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_comb.cc' 2309s 2309s /----------------------------------------------------------------------------\ 2309s | | 2309s | yosys -- Yosys Open SYnthesis Suite | 2309s | | 2309s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2309s | | 2309s | Permission to use, copy, modify, and/or distribute this software for any | 2309s | purpose with or without fee is hereby granted, provided that the above | 2309s | copyright notice and this permission notice appear in all copies. | 2309s | | 2309s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2309s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2309s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2309s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2309s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2309s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2309s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2309s | | 2309s \----------------------------------------------------------------------------/ 2309s 2309s Yosys 0.33 (git sha1 2584903a060) 2309s 2309s 2309s -- Running command `read_verilog always_comb.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_comb.cc' -- 2309s 2309s 1. Executing Verilog-2005 frontend: always_comb.v 2309s Parsing Verilog input from `always_comb.v' to AST representation. 2309s Generating RTLIL representation for module `\top'. 2309s Generating RTLIL representation for module `\sub'. 2309s Successfully finished Verilog frontend. 2309s 2309s 2. Executing PROC pass (convert processes to netlists). 2309s 2309s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2309s Cleaned up 0 empty switches. 2309s 2309s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2309s Removed a total of 0 dead cases. 2309s 2309s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2309s Removed 0 redundant assignments. 2309s Promoted 4 assignments to connections. 2309s 2309s 2.4. Executing PROC_INIT pass (extract init attributes). 2309s Found init rule in `\top.$proc$always_comb.v:3$13'. 2309s Set init value: \b = 1'0 2309s Found init rule in `\top.$proc$always_comb.v:2$12'. 2309s Set init value: \a = 1'0 2309s 2309s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2309s 2309s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2309s Converted 0 switches. 2309s 2309s 2309s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2309s Creating decoders for process `\sub.$proc$always_comb.v:23$15'. 2309s 1/1: $display$always_comb.v:23$19_EN 2309s Creating decoders for process `\top.$proc$always_comb.v:3$13'. 2309s Creating decoders for process `\top.$proc$always_comb.v:2$12'. 2309s Creating decoders for process `\top.$proc$always_comb.v:8$1'. 2309s 2309s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2309s 2309s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2309s Creating register for signal `\top.\a' using process `\top.$proc$always_comb.v:8$1'. 2309s created $dff cell `$procdff$22' with positive edge clock. 2309s Creating register for signal `\top.\b' using process `\top.$proc$always_comb.v:8$1'. 2309s created $dff cell `$procdff$23' with positive edge clock. 2309s 2309s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2309s 2309s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2309s Found and cleaned up 1 empty switch in `\sub.$proc$always_comb.v:23$15'. 2309s Removing empty process `sub.$proc$always_comb.v:23$15'. 2309s Removing empty process `top.$proc$always_comb.v:3$13'. 2309s Removing empty process `top.$proc$always_comb.v:2$12'. 2309s Removing empty process `top.$proc$always_comb.v:8$1'. 2309s Cleaned up 1 empty switch. 2309s 2309s 2.12. Executing OPT_EXPR pass (perform const folding). 2309s Optimizing module sub. 2309s Optimizing module top. 2309s Removed 0 unused cells and 7 unused wires. 2309s 2309s 3. Executing CXXRTL backend. 2309s + gcc -std=c++11 -o yosys-always_comb -I../.. always_comb_tb.cc -lstdc++ 2309s 2309s 3.1. Executing HIERARCHY pass (managing design hierarchy). 2309s 2309s 3.1.1. Finding top of design hierarchy.. 2309s root of 0 design levels: sub 2309s root of 1 design levels: top 2309s Automatically selected top as design top module. 2309s 2309s 3.1.2. Analyzing design hierarchy.. 2309s Top module: \top 2309s Used module: \sub 2309s 2309s 3.1.3. Analyzing design hierarchy.. 2309s Top module: \top 2309s Used module: \sub 2309s Removed 0 unused modules. 2309s 2309s 3.2. Executing FLATTEN pass (flatten design). 2309s Deleting now unused module sub. 2309s 2309s 2309s 3.3. Executing PROC pass (convert processes to netlists). 2309s 2309s 3.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2309s Cleaned up 0 empty switches. 2309s 2309s 3.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2309s Removed a total of 0 dead cases. 2309s 2309s 3.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2309s Removed 0 redundant assignments. 2309s Promoted 0 assignments to connections. 2309s 2309s 3.3.4. Executing PROC_INIT pass (extract init attributes). 2309s 2309s 3.3.5. Executing PROC_ARST pass (detect async resets in processes). 2309s 2309s 3.3.6. Executing PROC_ROM pass (convert switches to ROMs). 2309s Converted 0 switches. 2309s 2309s 3.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2309s 2309s 3.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2309s 2309s 3.3.9. Executing PROC_DFF pass (convert process syncs to FFs). 2309s 2309s 3.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2309s 2309s 3.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2309s Cleaned up 0 empty switches. 2309s 2309s 3.3.12. Executing OPT_EXPR pass (perform const folding). 2309s Optimizing module top. 2309s 2309s 2309s 2309s End of script. Logfile hash: 03fe26efda, CPU: user 0.01s system 0.00s, MEM: 7.62 MB peak 2309s Yosys 0.33 (git sha1 2584903a060) 2309s Time spent: 30% 2x opt_expr (0 sec), 20% 1x clean (0 sec), ... 2310s + ./yosys-always_comb 2310s + iverilog -o iverilog-always_comb always_comb.v always_comb_tb.v 2310s + ./iverilog-always_comb 2310s + grep -v '\$finish called' 2310s + diff iverilog-always_comb.log yosys-always_comb.log 2310s + ../../yosys -p 'read_verilog always_full.v; prep; clean' -o yosys-always_full-1.v 2310s 2310s /----------------------------------------------------------------------------\ 2310s | | 2310s | yosys -- Yosys Open SYnthesis Suite | 2310s | | 2310s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2310s | | 2310s | Permission to use, copy, modify, and/or distribute this software for any | 2310s | purpose with or without fee is hereby granted, provided that the above | 2310s | copyright notice and this permission notice appear in all copies. | 2310s | | 2310s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2310s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2310s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2310s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2310s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2310s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2310s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2310s | | 2310s \----------------------------------------------------------------------------/ 2310s 2310s Yosys 0.33 (git sha1 2584903a060) 2310s 2310s 2310s -- Running command `read_verilog always_full.v; prep; clean' -- 2310s 2310s 1. Executing Verilog-2005 frontend: always_full.v 2310s Parsing Verilog input from `always_full.v' to AST representation. 2310s Generating RTLIL representation for module `\always_full'. 2310s Successfully finished Verilog frontend. 2310s 2310s 2. Executing PREP pass. 2310s 2310s 2.1. Executing HIERARCHY pass (managing design hierarchy). 2310s 2310s 2.2. Executing PROC pass (convert processes to netlists). 2310s 2310s 2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2310s Cleaned up 0 empty switches. 2310s 2310s 2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2310s Removed a total of 0 dead cases. 2310s 2310s 2.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2310s Removed 207 redundant assignments. 2310s Promoted 207 assignments to connections. 2310s 2310s 2.2.4. Executing PROC_INIT pass (extract init attributes). 2310s 2310s 2.2.5. Executing PROC_ARST pass (detect async resets in processes). 2310s 2310s 2.2.6. Executing PROC_ROM pass (convert switches to ROMs). 2310s Converted 0 switches. 2310s 2310s 2.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2310s Creating decoders for process `\always_full.$proc$always_full.v:3$1'. 2310s 2310s 2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2310s 2310s 2.2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2310s 2310s 2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2310s 2310s 2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2310s Removing empty process `always_full.$proc$always_full.v:3$1'. 2310s Cleaned up 0 empty switches. 2310s 2310s 2.2.12. Executing OPT_EXPR pass (perform const folding). 2310s Optimizing module always_full. 2310s 2310s 2.3. Executing OPT_EXPR pass (perform const folding). 2310s Optimizing module always_full. 2310s 2310s 2.4. Executing OPT_CLEAN pass (remove unused cells and wires). 2310s Finding unused cells or wires in module \always_full.. 2310s Removed 0 unused cells and 207 unused wires. 2310s 2310s 2310s 2.5. Executing CHECK pass (checking for obvious problems). 2310s Checking module always_full... 2310s Found and reported 0 problems. 2310s 2310s 2.6. Executing OPT pass (performing simple optimizations). 2310s 2310s 2.6.1. Executing OPT_EXPR pass (perform const folding). 2310s Optimizing module always_full. 2310s 2310s 2.6.2. Executing OPT_MERGE pass (detect identical cells). 2310s Finding identical cells in module `\always_full'. 2310s Removed a total of 0 cells. 2310s 2310s 2.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 2310s Running muxtree optimizer on module \always_full.. 2310s Creating internal representation of mux trees. 2310s No muxes found in this module. 2310s Removed 0 multiplexer ports. 2310s 2310s 2.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 2310s Optimizing cells in module \always_full. 2310s Performed a total of 0 changes. 2310s 2310s 2.6.5. Executing OPT_MERGE pass (detect identical cells). 2310s Finding identical cells in module `\always_full'. 2310s Removed a total of 0 cells. 2310s 2310s 2.6.6. Executing OPT_CLEAN pass (remove unused cells and wires). 2310s Finding unused cells or wires in module \always_full.. 2310s 2310s 2.6.7. Executing OPT_EXPR pass (perform const folding). 2310s Optimizing module always_full. 2310s 2310s 2.6.8. Finished OPT passes. (There is nothing left to do.) 2310s 2310s 2.7. Executing WREDUCE pass (reducing word size of cells). 2310s 2310s 2.8. Executing OPT_CLEAN pass (remove unused cells and wires). 2310s Finding unused cells or wires in module \always_full.. 2310s 2310s 2.9. Executing MEMORY_COLLECT pass (generating $mem cells). 2310s 2310s 2.10. Executing OPT pass (performing simple optimizations). 2310s 2310s 2.10.1. Executing OPT_EXPR pass (perform const folding). 2310s Optimizing module always_full. 2310s 2310s 2.10.2. Executing OPT_MERGE pass (detect identical cells). 2310s Finding identical cells in module `\always_full'. 2310s Removed a total of 0 cells. 2310s 2310s 2.10.3. Executing OPT_CLEAN pass (remove unused cells and wires). 2310s Finding unused cells or wires in module \always_full.. 2310s 2310s 2.10.4. Finished fast OPT passes. 2310s 2310s 2.11. Printing statistics. 2310s 2310s === always_full === 2310s 2310s Number of wires: 1 2310s Number of wire bits: 1 2310s Number of public wires: 1 2310s Number of public wire bits: 1 2310s Number of memories: 0 2310s Number of memory bits: 0 2310s Number of processes: 0 2310s Number of cells: 207 2310s $print 207 2310s 2310s 2.12. Executing CHECK pass (checking for obvious problems). 2310s Checking module always_full... 2310s Found and reported 0 problems. 2310s 2310s -- Writing to `yosys-always_full-1.v' using backend `verilog' -- 2310s 2310s 3. Executing Verilog backend. 2310s 2310s 3.1. Executing BMUXMAP pass. 2310s 2310s 3.2. Executing DEMUXMAP pass. 2310s Dumping module `\always_full'. 2310s 2310s End of script. Logfile hash: cfd5b76053, CPU: user 0.07s system 0.00s, MEM: 8.12 MB peak 2310s Yosys 0.33 (git sha1 2584903a060) 2310s Time spent: 21% 5x opt_expr (0 sec), 20% 4x opt_clean (0 sec), ... 2310s + iverilog -o iverilog-always_full-1 yosys-always_full-1.v always_full_tb.v 2310s + ./iverilog-always_full-1 2310s + grep -v '\$finish called' 2310s + diff iverilog-always_full.log iverilog-always_full-1.log 2310s + ../../yosys -p 'read_verilog display_lm.v' 2310s + ../../yosys -p 'read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc' 2310s 2310s /----------------------------------------------------------------------------\ 2310s | | 2310s | yosys -- Yosys Open SYnthesis Suite | 2310s | | 2310s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2310s | | 2310s | Permission to use, copy, modify, and/or distribute this software for any | 2310s | purpose with or without fee is hereby granted, provided that the above | 2310s | copyright notice and this permission notice appear in all copies. | 2310s | | 2310s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2310s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2310s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2310s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2310s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2310s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2310s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2310s | | 2310s \----------------------------------------------------------------------------/ 2310s 2310s Yosys 0.33 (git sha1 2584903a060) 2310s 2310s 2310s -- Running command `read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc' -- 2310s 2310s 1. Executing Verilog-2005 frontend: display_lm.v 2310s Parsing Verilog input from `display_lm.v' to AST representation. 2310s Generating RTLIL representation for module `\top'. 2310s Generating RTLIL representation for module `\mid'. 2310s Generating RTLIL representation for module `\bot'. 2310s %l: \bot 2310s %m: \bot 2310s Successfully finished Verilog frontend. 2310s 2310s 2. Executing CXXRTL backend. 2310s 2310s 2.1. Executing HIERARCHY pass (managing design hierarchy). 2310s 2310s 2.1.1. Finding top of design hierarchy.. 2310s root of 0 design levels: bot 2310s root of 1 design levels: mid 2310s root of 2 design levels: top 2310s Automatically selected top as design top module. 2310s 2310s 2.1.2. Analyzing design hierarchy.. 2310s Top module: \top 2310s Used module: \mid 2310s Used module: \bot 2310s 2310s 2.1.3. Analyzing design hierarchy.. 2310s Top module: \top 2310s Used module: \mid 2310s Used module: \bot 2310s Removed 0 unused modules. 2310s 2310s 2.2. Executing FLATTEN pass (flatten design). 2310s Deleting now unused module bot. 2310s Deleting now unused module mid. 2310s 2310s 2310s 2.3. Executing PROC pass (convert processes to netlists). 2310s 2310s 2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2310s Removing empty process `top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:0$3'. 2310s Cleaned up 0 empty switches. 2310s 2310s 2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2310s Removed a total of 0 dead cases. 2310s 2310s 2.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2310s Removed 1 redundant assignment. 2310s Promoted 1 assignment to connection. 2310s 2310s 2.3.4. Executing PROC_INIT pass (extract init attributes). 2310s 2310s 2.3.5. Executing PROC_ARST pass (detect async resets in processes). 2310s 2310s 2.3.6. Executing PROC_ROM pass (convert switches to ROMs). 2310s Converted 0 switches. 2310s 2310s 2.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2310s Creating decoders for process `\top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:11$1'. 2310s 2310s 2.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2310s 2310s 2.3.9. Executing PROC_DFF pass (convert process syncs to FFs). 2310s 2310s 2.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2310s 2310s 2.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2310s Removing empty process `top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:11$1'. 2310s Cleaned up 0 empty switches. 2310s 2310s 2.3.12. Executing OPT_EXPR pass (perform const folding). 2310s Optimizing module top. 2310s 2310s 2310s 2310s End of script. Logfile hash: 1b689717a7, CPU: user 0.00s system 0.00s, MEM: 7.38 MB peak 2310s Yosys 0.33 (git sha1 2584903a060) 2310s Time spent: 36% 1x opt_expr (0 sec), 16% 2x read_verilog (0 sec), ... 2310s + gcc -std=c++11 -o yosys-display_lm_cc -I../.. display_lm_tb.cc -lstdc++ 2310s + ./yosys-display_lm_cc 2310s + for log in yosys-display_lm.log yosys-display_lm_cc.log 2310s + grep '^%l: \\bot$' yosys-display_lm.log 2310s + grep '^%m: \\bot$' yosys-display_lm.log 2310s %l: \bot 2310s %m: \bot 2310s + for log in yosys-display_lm.log yosys-display_lm_cc.log 2310s + grep '^%l: \\bot$' yosys-display_lm_cc.log 2310s %l: \bot 2310s + grep '^%m: \\bot$' yosys-display_lm_cc.log 2310s %m: \bot 2310s 2310s Passed "make test". 2310s 2311s autopkgtest [19:06:49]: test yosys-testsuite: -----------------------] 2314s yosys-testsuite PASS 2314s autopkgtest [19:06:52]: test yosys-testsuite: - - - - - - - - - - results - - - - - - - - - - 2318s autopkgtest [19:06:56]: test ice: preparing testbed 2340s autopkgtest [19:07:18]: testbed dpkg architecture: armhf 2341s autopkgtest [19:07:19]: testbed apt version: 2.9.33 2345s autopkgtest [19:07:23]: @@@@@@@@@@@@@@@@@@@@ test bed setup 2347s autopkgtest [19:07:25]: testbed release detected to be: plucky 2354s autopkgtest [19:07:32]: updating testbed package index (apt update) 2355s Get:1 http://ftpmaster.internal/ubuntu plucky-proposed InRelease [126 kB] 2356s Get:2 http://ftpmaster.internal/ubuntu plucky InRelease [257 kB] 2356s Get:3 http://ftpmaster.internal/ubuntu plucky-updates InRelease [126 kB] 2356s Get:4 http://ftpmaster.internal/ubuntu plucky-security InRelease [126 kB] 2356s Get:5 http://ftpmaster.internal/ubuntu plucky-proposed/main Sources [99.7 kB] 2356s Get:6 http://ftpmaster.internal/ubuntu plucky-proposed/universe Sources [379 kB] 2357s Get:7 http://ftpmaster.internal/ubuntu plucky-proposed/multiverse Sources [15.8 kB] 2357s Get:8 http://ftpmaster.internal/ubuntu plucky-proposed/main armhf Packages [114 kB] 2357s Get:9 http://ftpmaster.internal/ubuntu plucky-proposed/main armhf c-n-f Metadata [1832 B] 2357s Get:10 http://ftpmaster.internal/ubuntu plucky-proposed/restricted armhf c-n-f Metadata [116 B] 2357s Get:11 http://ftpmaster.internal/ubuntu plucky-proposed/universe armhf Packages [312 kB] 2357s Get:12 http://ftpmaster.internal/ubuntu plucky-proposed/universe armhf c-n-f Metadata [11.1 kB] 2357s Get:13 http://ftpmaster.internal/ubuntu plucky-proposed/multiverse armhf Packages [3472 B] 2357s Get:14 http://ftpmaster.internal/ubuntu plucky-proposed/multiverse armhf c-n-f Metadata [240 B] 2357s Get:15 http://ftpmaster.internal/ubuntu plucky/universe Sources [21.0 MB] 2371s Get:16 http://ftpmaster.internal/ubuntu plucky/main Sources [1394 kB] 2372s Get:17 http://ftpmaster.internal/ubuntu plucky/multiverse Sources [299 kB] 2372s Get:18 http://ftpmaster.internal/ubuntu plucky/main armhf Packages [1378 kB] 2373s Get:19 http://ftpmaster.internal/ubuntu plucky/main armhf c-n-f Metadata [29.4 kB] 2373s Get:20 http://ftpmaster.internal/ubuntu plucky/restricted armhf c-n-f Metadata [108 B] 2373s Get:21 http://ftpmaster.internal/ubuntu plucky/universe armhf Packages [15.1 MB] 2384s Get:22 http://ftpmaster.internal/ubuntu plucky/multiverse armhf Packages [172 kB] 2386s Fetched 41.0 MB in 30s (1360 kB/s) 2387s Reading package lists... 2392s autopkgtest [19:08:10]: upgrading testbed (apt dist-upgrade and autopurge) 2394s Reading package lists... 2394s Building dependency tree... 2394s Reading state information... 2394s Calculating upgrade...Starting pkgProblemResolver with broken count: 0 2395s Starting 2 pkgProblemResolver with broken count: 0 2395s Done 2395s Entering ResolveByKeep 2396s 2396s Calculating upgrade... 2396s The following packages will be upgraded: 2396s libc-bin libc6 locales pinentry-curses python3-jinja2 sos strace 2396s 7 upgraded, 0 newly installed, 0 to remove and 0 not upgraded. 2396s Need to get 8683 kB of archives. 2396s After this operation, 23.6 kB of additional disk space will be used. 2396s Get:1 http://ftpmaster.internal/ubuntu plucky-proposed/main armhf libc6 armhf 2.41-1ubuntu2 [2932 kB] 2398s Get:2 http://ftpmaster.internal/ubuntu plucky-proposed/main armhf libc-bin armhf 2.41-1ubuntu2 [545 kB] 2399s Get:3 http://ftpmaster.internal/ubuntu plucky-proposed/main armhf locales all 2.41-1ubuntu2 [4246 kB] 2402s Get:4 http://ftpmaster.internal/ubuntu plucky/main armhf strace armhf 6.13+ds-1ubuntu1 [445 kB] 2402s Get:5 http://ftpmaster.internal/ubuntu plucky/main armhf pinentry-curses armhf 1.3.1-2ubuntu3 [40.6 kB] 2402s Get:6 http://ftpmaster.internal/ubuntu plucky/main armhf python3-jinja2 all 3.1.5-2ubuntu1 [109 kB] 2402s Get:7 http://ftpmaster.internal/ubuntu plucky/main armhf sos all 4.9.0-5 [365 kB] 2403s Preconfiguring packages ... 2403s Fetched 8683 kB in 6s (1464 kB/s) 2403s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 64655 files and directories currently installed.) 2403s Preparing to unpack .../libc6_2.41-1ubuntu2_armhf.deb ... 2403s Unpacking libc6:armhf (2.41-1ubuntu2) over (2.41-1ubuntu1) ... 2403s Setting up libc6:armhf (2.41-1ubuntu2) ... 2403s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 64655 files and directories currently installed.) 2403s Preparing to unpack .../libc-bin_2.41-1ubuntu2_armhf.deb ... 2403s Unpacking libc-bin (2.41-1ubuntu2) over (2.41-1ubuntu1) ... 2403s Setting up libc-bin (2.41-1ubuntu2) ... 2404s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 64655 files and directories currently installed.) 2404s Preparing to unpack .../locales_2.41-1ubuntu2_all.deb ... 2404s Unpacking locales (2.41-1ubuntu2) over (2.41-1ubuntu1) ... 2404s Preparing to unpack .../strace_6.13+ds-1ubuntu1_armhf.deb ... 2404s Unpacking strace (6.13+ds-1ubuntu1) over (6.11-0ubuntu1) ... 2404s Preparing to unpack .../pinentry-curses_1.3.1-2ubuntu3_armhf.deb ... 2404s Unpacking pinentry-curses (1.3.1-2ubuntu3) over (1.3.1-2ubuntu2) ... 2404s Preparing to unpack .../python3-jinja2_3.1.5-2ubuntu1_all.deb ... 2404s Unpacking python3-jinja2 (3.1.5-2ubuntu1) over (3.1.5-2) ... 2404s Preparing to unpack .../archives/sos_4.9.0-5_all.deb ... 2404s Unpacking sos (4.9.0-5) over (4.9.0-4) ... 2405s Setting up sos (4.9.0-5) ... 2405s Setting up pinentry-curses (1.3.1-2ubuntu3) ... 2405s Setting up locales (2.41-1ubuntu2) ... 2406s Generating locales (this might take a while)... 2408s en_US.UTF-8... done 2408s Generation complete. 2408s Setting up python3-jinja2 (3.1.5-2ubuntu1) ... 2408s Setting up strace (6.13+ds-1ubuntu1) ... 2408s Processing triggers for man-db (2.13.0-1) ... 2409s Processing triggers for systemd (257.3-1ubuntu3) ... 2411s Reading package lists... 2411s Building dependency tree... 2411s Reading state information... 2412s Starting pkgProblemResolver with broken count: 0 2412s Starting 2 pkgProblemResolver with broken count: 0 2412s Done 2412s Solving dependencies... 2413s 0 upgraded, 0 newly installed, 0 to remove and 0 not upgraded. 2415s autopkgtest [19:08:33]: rebooting testbed after setup commands that affected boot 2475s Reading package lists... 2476s Building dependency tree... 2476s Reading state information... 2476s Starting pkgProblemResolver with broken count: 0 2476s Starting 2 pkgProblemResolver with broken count: 0 2476s Done 2477s The following NEW packages will be installed: 2477s libtcl8.6 python3-click yosys yosys-abc 2477s 0 upgraded, 4 newly installed, 0 to remove and 0 not upgraded. 2477s Need to get 9551 kB of archives. 2477s After this operation, 24.9 MB of additional disk space will be used. 2477s Get:1 http://ftpmaster.internal/ubuntu plucky/main armhf libtcl8.6 armhf 8.6.16+dfsg-1 [909 kB] 2478s Get:2 http://ftpmaster.internal/ubuntu plucky/main armhf python3-click all 8.2.0+0.really.8.1.8-1 [80.0 kB] 2478s Get:3 http://ftpmaster.internal/ubuntu plucky/universe armhf yosys-abc armhf 0.33-5build2 [5336 kB] 2483s Get:4 http://ftpmaster.internal/ubuntu plucky/universe armhf yosys armhf 0.33-5build2 [3225 kB] 2486s Fetched 9551 kB in 9s (1056 kB/s) 2486s Selecting previously unselected package libtcl8.6:armhf. 2486s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 64655 files and directories currently installed.) 2486s Preparing to unpack .../libtcl8.6_8.6.16+dfsg-1_armhf.deb ... 2486s Unpacking libtcl8.6:armhf (8.6.16+dfsg-1) ... 2486s Selecting previously unselected package python3-click. 2486s Preparing to unpack .../python3-click_8.2.0+0.really.8.1.8-1_all.deb ... 2486s Unpacking python3-click (8.2.0+0.really.8.1.8-1) ... 2486s Selecting previously unselected package yosys-abc. 2486s Preparing to unpack .../yosys-abc_0.33-5build2_armhf.deb ... 2486s Unpacking yosys-abc (0.33-5build2) ... 2486s Selecting previously unselected package yosys. 2486s Preparing to unpack .../yosys_0.33-5build2_armhf.deb ... 2486s Unpacking yosys (0.33-5build2) ... 2487s Setting up yosys-abc (0.33-5build2) ... 2487s Setting up python3-click (8.2.0+0.really.8.1.8-1) ... 2487s Setting up libtcl8.6:armhf (8.6.16+dfsg-1) ... 2487s Setting up yosys (0.33-5build2) ... 2487s Processing triggers for libc-bin (2.41-1ubuntu2) ... 2487s Processing triggers for man-db (2.13.0-1) ... 2507s autopkgtest [19:10:05]: test ice: [----------------------- 2509s 2509s /----------------------------------------------------------------------------\ 2509s | | 2509s | yosys -- Yosys Open SYnthesis Suite | 2509s | | 2509s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2509s | | 2509s | Permission to use, copy, modify, and/or distribute this software for any | 2509s | purpose with or without fee is hereby granted, provided that the above | 2509s | copyright notice and this permission notice appear in all copies. | 2509s | | 2509s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2509s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2509s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2509s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2509s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2509s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2509s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2509s | | 2509s \----------------------------------------------------------------------------/ 2509s 2509s Yosys 0.33 (git sha1 2584903a060) 2509s 2509s 2509s -- Running command `read_verilog debian/tests/design_ice.v; synth_ice40 -blif /tmp/autopkgtest.eUlrfO/autopkgtest_tmp/design_ice.blif' -- 2509s 2509s 1. Executing Verilog-2005 frontend: debian/tests/design_ice.v 2509s Parsing Verilog input from `debian/tests/design_ice.v' to AST representation. 2509s Generating RTLIL representation for module `\design_ice'. 2509s Successfully finished Verilog frontend. 2509s 2509s 2. Executing SYNTH_ICE40 pass. 2509s 2509s 2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v 2509s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation. 2509s Generating RTLIL representation for module `\SB_IO'. 2509s Generating RTLIL representation for module `\SB_GB_IO'. 2509s Generating RTLIL representation for module `\SB_GB'. 2509s Generating RTLIL representation for module `\SB_LUT4'. 2509s Generating RTLIL representation for module `\SB_CARRY'. 2509s Generating RTLIL representation for module `\SB_DFF'. 2509s Generating RTLIL representation for module `\SB_DFFE'. 2509s Generating RTLIL representation for module `\SB_DFFSR'. 2509s Generating RTLIL representation for module `\SB_DFFR'. 2509s Generating RTLIL representation for module `\SB_DFFSS'. 2509s Generating RTLIL representation for module `\SB_DFFS'. 2509s Generating RTLIL representation for module `\SB_DFFESR'. 2509s Generating RTLIL representation for module `\SB_DFFER'. 2509s Generating RTLIL representation for module `\SB_DFFESS'. 2509s Generating RTLIL representation for module `\SB_DFFES'. 2509s Generating RTLIL representation for module `\SB_DFFN'. 2509s Generating RTLIL representation for module `\SB_DFFNE'. 2509s Generating RTLIL representation for module `\SB_DFFNSR'. 2509s Generating RTLIL representation for module `\SB_DFFNR'. 2509s Generating RTLIL representation for module `\SB_DFFNSS'. 2509s Generating RTLIL representation for module `\SB_DFFNS'. 2509s Generating RTLIL representation for module `\SB_DFFNESR'. 2509s Generating RTLIL representation for module `\SB_DFFNER'. 2509s Generating RTLIL representation for module `\SB_DFFNESS'. 2509s Generating RTLIL representation for module `\SB_DFFNES'. 2509s Generating RTLIL representation for module `\SB_RAM40_4K'. 2509s Generating RTLIL representation for module `\SB_RAM40_4KNR'. 2509s Generating RTLIL representation for module `\SB_RAM40_4KNW'. 2509s Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. 2509s Generating RTLIL representation for module `\ICESTORM_LC'. 2509s Generating RTLIL representation for module `\SB_PLL40_CORE'. 2509s Generating RTLIL representation for module `\SB_PLL40_PAD'. 2509s Generating RTLIL representation for module `\SB_PLL40_2_PAD'. 2509s Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. 2509s Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. 2509s Generating RTLIL representation for module `\SB_WARMBOOT'. 2509s Generating RTLIL representation for module `\SB_SPRAM256KA'. 2509s Generating RTLIL representation for module `\SB_HFOSC'. 2509s Generating RTLIL representation for module `\SB_LFOSC'. 2509s Generating RTLIL representation for module `\SB_RGBA_DRV'. 2509s Generating RTLIL representation for module `\SB_LED_DRV_CUR'. 2509s Generating RTLIL representation for module `\SB_RGB_DRV'. 2509s Generating RTLIL representation for module `\SB_I2C'. 2509s Generating RTLIL representation for module `\SB_SPI'. 2509s Generating RTLIL representation for module `\SB_LEDDA_IP'. 2509s Generating RTLIL representation for module `\SB_FILTER_50NS'. 2509s Generating RTLIL representation for module `\SB_IO_I3C'. 2509s Generating RTLIL representation for module `\SB_IO_OD'. 2509s Generating RTLIL representation for module `\SB_MAC16'. 2509s Generating RTLIL representation for module `\ICESTORM_RAM'. 2509s Successfully finished Verilog frontend. 2509s 2509s 2.2. Executing HIERARCHY pass (managing design hierarchy). 2509s 2509s 2.2.1. Finding top of design hierarchy.. 2509s root of 0 design levels: design_ice 2509s Automatically selected design_ice as design top module. 2509s 2509s 2.2.2. Analyzing design hierarchy.. 2509s Top module: \design_ice 2509s 2509s 2.2.3. Analyzing design hierarchy.. 2509s Top module: \design_ice 2509s Removed 0 unused modules. 2509s 2509s 2.3. Executing PROC pass (convert processes to netlists). 2509s 2509s 2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2509s Cleaned up 0 empty switches. 2509s 2509s 2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2509s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243 in module SB_DFFNES. 2509s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236 in module SB_DFFNESS. 2509s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232 in module SB_DFFNER. 2509s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225 in module SB_DFFNESR. 2509s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222 in module SB_DFFNS. 2509s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219 in module SB_DFFNSS. 2509s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216 in module SB_DFFNR. 2509s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213 in module SB_DFFNSR. 2509s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205 in module SB_DFFES. 2509s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198 in module SB_DFFESS. 2509s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194 in module SB_DFFER. 2509s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187 in module SB_DFFESR. 2509s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184 in module SB_DFFS. 2509s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181 in module SB_DFFSS. 2509s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178 in module SB_DFFR. 2509s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175 in module SB_DFFSR. 2509s Marked 1 switch rules as full_case in process $proc$debian/tests/design_ice.v:6$1 in module design_ice. 2509s Removed a total of 0 dead cases. 2509s 2509s 2.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2509s Removed 8 redundant assignments. 2509s Promoted 23 assignments to connections. 2509s 2509s 2.3.4. Executing PROC_INIT pass (extract init attributes). 2509s Found init rule in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$246'. 2509s Set init value: \Q = 1'0 2509s Found init rule in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$242'. 2509s Set init value: \Q = 1'0 2509s Found init rule in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$235'. 2509s Set init value: \Q = 1'0 2509s Found init rule in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$231'. 2509s Set init value: \Q = 1'0 2509s Found init rule in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$224'. 2509s Set init value: \Q = 1'0 2509s Found init rule in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$221'. 2509s Set init value: \Q = 1'0 2509s Found init rule in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$218'. 2509s Set init value: \Q = 1'0 2509s Found init rule in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$215'. 2509s Set init value: \Q = 1'0 2509s Found init rule in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$212'. 2509s Set init value: \Q = 1'0 2509s Found init rule in `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 2509s Set init value: \Q = 1'0 2509s Found init rule in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 2509s Set init value: \Q = 1'0 2509s Found init rule in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$204'. 2509s Set init value: \Q = 1'0 2509s Found init rule in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$197'. 2509s Set init value: \Q = 1'0 2509s Found init rule in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$193'. 2509s Set init value: \Q = 1'0 2509s Found init rule in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$186'. 2509s Set init value: \Q = 1'0 2509s Found init rule in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$183'. 2509s Set init value: \Q = 1'0 2509s Found init rule in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$180'. 2509s Set init value: \Q = 1'0 2509s Found init rule in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$177'. 2509s Set init value: \Q = 1'0 2509s Found init rule in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$174'. 2509s Set init value: \Q = 1'0 2509s Found init rule in `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 2509s Set init value: \Q = 1'0 2509s Found init rule in `\design_ice.$proc$debian/tests/design_ice.v:3$2'. 2509s Set init value: \ready = 1'0 2509s 2509s 2.3.5. Executing PROC_ARST pass (detect async resets in processes). 2509s Found async reset \S in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'. 2509s Found async reset \R in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'. 2509s Found async reset \S in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222'. 2509s Found async reset \R in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216'. 2509s Found async reset \S in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'. 2509s Found async reset \R in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'. 2509s Found async reset \S in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184'. 2509s Found async reset \R in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178'. 2509s 2509s 2.3.6. Executing PROC_ROM pass (convert switches to ROMs). 2509s Converted 0 switches. 2509s 2509s 2509s 2.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2509s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$246'. 2509s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'. 2509s 1/1: $0\Q[0:0] 2509s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$242'. 2509s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236'. 2509s 1/1: $0\Q[0:0] 2509s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$235'. 2509s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'. 2509s 1/1: $0\Q[0:0] 2509s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$231'. 2509s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225'. 2509s 1/1: $0\Q[0:0] 2509s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$224'. 2509s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222'. 2509s 1/1: $0\Q[0:0] 2509s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$221'. 2509s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219'. 2509s 1/1: $0\Q[0:0] 2509s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$218'. 2509s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216'. 2509s 1/1: $0\Q[0:0] 2509s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$215'. 2509s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213'. 2509s 1/1: $0\Q[0:0] 2509s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$212'. 2509s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$211'. 2509s 1/1: $0\Q[0:0] 2509s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 2509s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$209'. 2509s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 2509s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'. 2509s 1/1: $0\Q[0:0] 2509s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$204'. 2509s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198'. 2509s 1/1: $0\Q[0:0] 2509s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$197'. 2509s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'. 2509s 1/1: $0\Q[0:0] 2509s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$193'. 2509s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187'. 2509s 1/1: $0\Q[0:0] 2509s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$186'. 2509s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184'. 2509s 1/1: $0\Q[0:0] 2509s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$183'. 2509s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181'. 2509s 1/1: $0\Q[0:0] 2509s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$180'. 2509s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178'. 2509s 1/1: $0\Q[0:0] 2509s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$177'. 2509s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175'. 2509s 1/1: $0\Q[0:0] 2509s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$174'. 2509s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$173'. 2509s 1/1: $0\Q[0:0] 2509s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 2509s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$171'. 2509s Creating decoders for process `\design_ice.$proc$debian/tests/design_ice.v:3$2'. 2509s Creating decoders for process `\design_ice.$proc$debian/tests/design_ice.v:6$1'. 2509s 1/2: $0\value[0:0] 2509s 2/2: $0\ready[0:0] 2509s 2509s 2.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2509s 2509s 2.3.9. Executing PROC_DFF pass (convert process syncs to FFs). 2509s Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'. 2509s created $adff cell `$procdff$433' with negative edge clock and positive level reset. 2509s Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236'. 2509s created $dff cell `$procdff$434' with negative edge clock. 2509s Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'. 2509s created $adff cell `$procdff$435' with negative edge clock and positive level reset. 2509s Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225'. 2509s created $dff cell `$procdff$436' with negative edge clock. 2509s Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222'. 2509s created $adff cell `$procdff$437' with negative edge clock and positive level reset. 2509s Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219'. 2509s created $dff cell `$procdff$438' with negative edge clock. 2509s Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216'. 2509s created $adff cell `$procdff$439' with negative edge clock and positive level reset. 2509s Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213'. 2509s created $dff cell `$procdff$440' with negative edge clock. 2509s Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$211'. 2509s created $dff cell `$procdff$441' with negative edge clock. 2509s Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$209'. 2509s created $dff cell `$procdff$442' with negative edge clock. 2509s Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'. 2509s created $adff cell `$procdff$443' with positive edge clock and positive level reset. 2509s Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198'. 2509s created $dff cell `$procdff$444' with positive edge clock. 2509s Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'. 2509s created $adff cell `$procdff$445' with positive edge clock and positive level reset. 2509s Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187'. 2509s created $dff cell `$procdff$446' with positive edge clock. 2509s Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184'. 2509s created $adff cell `$procdff$447' with positive edge clock and positive level reset. 2509s Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181'. 2509s created $dff cell `$procdff$448' with positive edge clock. 2509s Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178'. 2509s created $adff cell `$procdff$449' with positive edge clock and positive level reset. 2509s Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175'. 2509s created $dff cell `$procdff$450' with positive edge clock. 2509s Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$173'. 2509s created $dff cell `$procdff$451' with positive edge clock. 2509s Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$171'. 2509s created $dff cell `$procdff$452' with positive edge clock. 2509s Creating register for signal `\design_ice.\ready' using process `\design_ice.$proc$debian/tests/design_ice.v:6$1'. 2509s created $dff cell `$procdff$453' with positive edge clock. 2509s Creating register for signal `\design_ice.\value' using process `\design_ice.$proc$debian/tests/design_ice.v:6$1'. 2509s created $dff cell `$procdff$454' with positive edge clock. 2509s 2509s 2.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2509s 2509s 2.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2509s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$246'. 2509s Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'. 2509s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'. 2509s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$242'. 2509s Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236'. 2509s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236'. 2509s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$235'. 2509s Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'. 2509s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'. 2509s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$231'. 2509s Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225'. 2509s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225'. 2509s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$224'. 2509s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222'. 2509s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$221'. 2509s Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219'. 2509s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219'. 2509s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$218'. 2509s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216'. 2509s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$215'. 2509s Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213'. 2509s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213'. 2509s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$212'. 2509s Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$211'. 2509s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$211'. 2509s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 2509s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$209'. 2509s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 2509s Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'. 2509s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'. 2509s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$204'. 2509s Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198'. 2509s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198'. 2509s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$197'. 2509s Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'. 2509s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'. 2509s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$193'. 2509s Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187'. 2509s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187'. 2509s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$186'. 2509s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184'. 2509s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$183'. 2509s Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181'. 2509s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181'. 2509s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$180'. 2509s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178'. 2509s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$177'. 2509s Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175'. 2509s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175'. 2509s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$174'. 2509s Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$173'. 2509s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$173'. 2509s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 2509s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$171'. 2509s Removing empty process `design_ice.$proc$debian/tests/design_ice.v:3$2'. 2509s Found and cleaned up 1 empty switch in `\design_ice.$proc$debian/tests/design_ice.v:6$1'. 2509s Removing empty process `design_ice.$proc$debian/tests/design_ice.v:6$1'. 2509s Cleaned up 19 empty switches. 2509s 2509s 2.3.12. Executing OPT_EXPR pass (perform const folding). 2509s Optimizing module design_ice. 2509s 2509s 2.4. Executing FLATTEN pass (flatten design). 2509s 2509s 2.5. Executing TRIBUF pass. 2509s 2509s 2.6. Executing DEMINOUT pass (demote inout ports to input or output). 2509s 2509s 2.7. Executing OPT_EXPR pass (perform const folding). 2509s Optimizing module design_ice. 2509s 2509s 2.8. Executing OPT_CLEAN pass (remove unused cells and wires). 2509s Finding unused cells or wires in module \design_ice.. 2509s Removed 0 unused cells and 5 unused wires. 2509s 2509s 2509s 2.9. Executing CHECK pass (checking for obvious problems). 2509s Checking module design_ice... 2509s Found and reported 0 problems. 2509s 2509s 2.10. Executing OPT pass (performing simple optimizations). 2509s 2509s 2.10.1. Executing OPT_EXPR pass (perform const folding). 2509s Optimizing module design_ice. 2509s 2509s 2.10.2. Executing OPT_MERGE pass (detect identical cells). 2509s Finding identical cells in module `\design_ice'. 2509s Removed a total of 0 cells. 2509s 2509s 2.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 2509s Running muxtree optimizer on module \design_ice.. 2509s Creating internal representation of mux trees. 2509s Evaluating internal representation of mux trees. 2509s Replacing known input bits on port B of cell $procmux$431: \ready -> 1'1 2509s Analyzing evaluation results. 2509s Removed 0 multiplexer ports. 2509s 2509s 2509s 2.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 2509s Optimizing cells in module \design_ice. 2509s Optimizing cells in module \design_ice. 2509s Performed a total of 1 changes. 2509s 2509s 2.10.5. Executing OPT_MERGE pass (detect identical cells). 2509s Finding identical cells in module `\design_ice'. 2509s Removed a total of 0 cells. 2509s 2509s 2.10.6. Executing OPT_DFF pass (perform DFF optimizations). 2509s 2509s 2.10.7. Executing OPT_CLEAN pass (remove unused cells and wires). 2509s Finding unused cells or wires in module \design_ice.. 2509s Removed 0 unused cells and 1 unused wires. 2509s 2509s 2509s 2.10.8. Executing OPT_EXPR pass (perform const folding). 2509s Optimizing module design_ice. 2509s 2509s 2.10.9. Rerunning OPT passes. (Maybe there is more to do..) 2509s 2509s 2.10.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 2509s Running muxtree optimizer on module \design_ice.. 2509s Creating internal representation of mux trees. 2509s Evaluating internal representation of mux trees. 2509s Analyzing evaluation results. 2509s Removed 0 multiplexer ports. 2509s 2509s 2509s 2.10.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 2509s Optimizing cells in module \design_ice. 2509s Performed a total of 0 changes. 2509s 2509s 2.10.12. Executing OPT_MERGE pass (detect identical cells). 2509s Finding identical cells in module `\design_ice'. 2509s Removed a total of 0 cells. 2509s 2509s 2.10.13. Executing OPT_DFF pass (perform DFF optimizations). 2509s 2509s 2.10.14. Executing OPT_CLEAN pass (remove unused cells and wires). 2509s Finding unused cells or wires in module \design_ice.. 2509s 2509s 2.10.15. Executing OPT_EXPR pass (perform const folding). 2509s Optimizing module design_ice. 2509s 2509s 2.10.16. Finished OPT passes. (There is nothing left to do.) 2509s 2509s 2.11. Executing FSM pass (extract and optimize FSM). 2509s 2509s 2.11.1. Executing FSM_DETECT pass (finding FSMs in design). 2509s 2509s 2.11.2. Executing FSM_EXTRACT pass (extracting FSM from design). 2509s 2509s 2.11.3. Executing FSM_OPT pass (simple optimizations of FSMs). 2509s 2509s 2.11.4. Executing OPT_CLEAN pass (remove unused cells and wires). 2509s Finding unused cells or wires in module \design_ice.. 2509s 2509s 2.11.5. Executing FSM_OPT pass (simple optimizations of FSMs). 2509s 2509s 2.11.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 2509s 2509s 2.11.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 2509s 2509s 2.11.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 2509s 2509s 2.12. Executing OPT pass (performing simple optimizations). 2509s 2509s 2.12.1. Executing OPT_EXPR pass (perform const folding). 2509s Optimizing module design_ice. 2509s 2509s 2.12.2. Executing OPT_MERGE pass (detect identical cells). 2509s Finding identical cells in module `\design_ice'. 2509s Removed a total of 0 cells. 2509s 2509s 2.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 2509s Running muxtree optimizer on module \design_ice.. 2509s Creating internal representation of mux trees. 2509s Evaluating internal representation of mux trees. 2509s Analyzing evaluation results. 2509s Removed 0 multiplexer ports. 2509s 2509s 2509s 2.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 2509s Optimizing cells in module \design_ice. 2509s Performed a total of 0 changes. 2509s 2509s 2.12.5. Executing OPT_MERGE pass (detect identical cells). 2509s Finding identical cells in module `\design_ice'. 2509s Removed a total of 0 cells. 2509s 2509s 2.12.6. Executing OPT_DFF pass (perform DFF optimizations). 2509s Adding EN signal on $procdff$454 ($dff) from module design_ice (D = \I1, Q = \value). 2509s 2509s 2.12.7. Executing OPT_CLEAN pass (remove unused cells and wires). 2509s Finding unused cells or wires in module \design_ice.. 2509s Removed 1 unused cells and 1 unused wires. 2509s 2509s 2509s 2.12.8. Executing OPT_EXPR pass (perform const folding). 2509s Optimizing module design_ice. 2509s 2509s 2.12.9. Rerunning OPT passes. (Maybe there is more to do..) 2509s 2509s 2.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 2509s Running muxtree optimizer on module \design_ice.. 2509s Creating internal representation of mux trees. 2509s No muxes found in this module. 2509s Removed 0 multiplexer ports. 2509s 2509s 2.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 2509s Optimizing cells in module \design_ice. 2509s Performed a total of 0 changes. 2509s 2509s 2.12.12. Executing OPT_MERGE pass (detect identical cells). 2509s Finding identical cells in module `\design_ice'. 2509s Removed a total of 0 cells. 2509s 2509s 2.12.13. Executing OPT_DFF pass (perform DFF optimizations). 2509s 2509s 2.12.14. Executing OPT_CLEAN pass (remove unused cells and wires). 2509s Finding unused cells or wires in module \design_ice.. 2509s 2509s 2.12.15. Executing OPT_EXPR pass (perform const folding). 2509s Optimizing module design_ice. 2509s 2509s 2.12.16. Finished OPT passes. (There is nothing left to do.) 2509s 2509s 2.13. Executing WREDUCE pass (reducing word size of cells). 2509s 2509s 2.14. Executing PEEPOPT pass (run peephole optimizers). 2509s 2509s 2.15. Executing OPT_CLEAN pass (remove unused cells and wires). 2509s Finding unused cells or wires in module \design_ice.. 2509s 2509s 2.16. Executing SHARE pass (SAT-based resource sharing). 2509s 2509s 2.17. Executing TECHMAP pass (map to technology primitives). 2509s 2509s 2.17.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v 2509s Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation. 2509s Generating RTLIL representation for module `\_90_lut_cmp_'. 2509s Successfully finished Verilog frontend. 2509s 2509s 2.17.2. Continuing TECHMAP pass. 2509s No more expansions possible. 2509s 2509s 2509s 2.18. Executing OPT_EXPR pass (perform const folding). 2509s Optimizing module design_ice. 2509s 2509s 2.19. Executing OPT_CLEAN pass (remove unused cells and wires). 2509s Finding unused cells or wires in module \design_ice.. 2509s 2509s 2.20. Executing ALUMACC pass (create $alu and $macc cells). 2509s Extracting $alu and $macc cells in module design_ice: 2509s created 0 $alu and 0 $macc cells. 2509s 2509s 2.21. Executing OPT pass (performing simple optimizations). 2509s 2509s 2.21.1. Executing OPT_EXPR pass (perform const folding). 2509s Optimizing module design_ice. 2509s 2509s 2.21.2. Executing OPT_MERGE pass (detect identical cells). 2509s Finding identical cells in module `\design_ice'. 2509s Removed a total of 0 cells. 2509s 2509s 2.21.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 2509s Running muxtree optimizer on module \design_ice.. 2509s Creating internal representation of mux trees. 2509s No muxes found in this module. 2509s Removed 0 multiplexer ports. 2509s 2509s 2.21.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 2509s Optimizing cells in module \design_ice. 2509s Performed a total of 0 changes. 2509s 2509s 2.21.5. Executing OPT_MERGE pass (detect identical cells). 2509s Finding identical cells in module `\design_ice'. 2509s Removed a total of 0 cells. 2509s 2509s 2.21.6. Executing OPT_DFF pass (perform DFF optimizations). 2509s 2509s 2.21.7. Executing OPT_CLEAN pass (remove unused cells and wires). 2509s Finding unused cells or wires in module \design_ice.. 2509s 2509s 2.21.8. Executing OPT_EXPR pass (perform const folding). 2509s Optimizing module design_ice. 2509s 2509s 2.21.9. Finished OPT passes. (There is nothing left to do.) 2509s 2509s 2.22. Executing MEMORY pass. 2509s 2509s 2.22.1. Executing OPT_MEM pass (optimize memories). 2509s Performed a total of 0 transformations. 2509s 2509s 2.22.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). 2509s Performed a total of 0 transformations. 2509s 2509s 2.22.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 2509s 2509s 2.22.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 2509s 2509s 2.22.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 2509s 2509s 2.22.6. Executing OPT_CLEAN pass (remove unused cells and wires). 2509s Finding unused cells or wires in module \design_ice.. 2509s 2509s 2.22.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 2509s 2509s 2.22.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). 2509s Performed a total of 0 transformations. 2509s 2509s 2.22.9. Executing OPT_CLEAN pass (remove unused cells and wires). 2509s Finding unused cells or wires in module \design_ice.. 2509s 2509s 2.22.10. Executing MEMORY_COLLECT pass (generating $mem cells). 2509s 2509s 2.23. Executing OPT_CLEAN pass (remove unused cells and wires). 2509s Finding unused cells or wires in module \design_ice.. 2509s 2509s 2.24. Executing MEMORY_LIBMAP pass (mapping memories to cells). 2509s 2509s 2.25. Executing TECHMAP pass (map to technology primitives). 2509s 2509s 2.25.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v 2509s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation. 2509s Generating RTLIL representation for module `\$__ICE40_RAM4K_'. 2509s Successfully finished Verilog frontend. 2509s 2509s 2.25.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/spram_map.v 2509s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/spram_map.v' to AST representation. 2509s Generating RTLIL representation for module `\$__ICE40_SPRAM_'. 2509s Successfully finished Verilog frontend. 2509s 2509s 2.25.3. Continuing TECHMAP pass. 2509s No more expansions possible. 2509s 2509s 2509s 2.26. Executing ICE40_BRAMINIT pass. 2509s 2509s 2.27. Executing OPT pass (performing simple optimizations). 2509s 2509s 2.27.1. Executing OPT_EXPR pass (perform const folding). 2509s Optimizing module design_ice. 2509s 2509s 2.27.2. Executing OPT_MERGE pass (detect identical cells). 2509s Finding identical cells in module `\design_ice'. 2509s Removed a total of 0 cells. 2509s 2509s 2.27.3. Executing OPT_DFF pass (perform DFF optimizations). 2509s 2509s 2.27.4. Executing OPT_CLEAN pass (remove unused cells and wires). 2509s Finding unused cells or wires in module \design_ice.. 2509s 2509s 2.27.5. Finished fast OPT passes. 2509s 2509s 2.28. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 2509s 2509s 2.29. Executing OPT pass (performing simple optimizations). 2509s 2509s 2.29.1. Executing OPT_EXPR pass (perform const folding). 2509s Optimizing module design_ice. 2509s 2509s 2.29.2. Executing OPT_MERGE pass (detect identical cells). 2509s Finding identical cells in module `\design_ice'. 2509s Removed a total of 0 cells. 2509s 2509s 2.29.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 2509s Running muxtree optimizer on module \design_ice.. 2509s Creating internal representation of mux trees. 2509s No muxes found in this module. 2509s Removed 0 multiplexer ports. 2509s 2509s 2.29.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 2509s Optimizing cells in module \design_ice. 2509s Performed a total of 0 changes. 2509s 2509s 2.29.5. Executing OPT_MERGE pass (detect identical cells). 2509s Finding identical cells in module `\design_ice'. 2509s Removed a total of 0 cells. 2509s 2509s 2.29.6. Executing OPT_DFF pass (perform DFF optimizations). 2509s 2509s 2.29.7. Executing OPT_CLEAN pass (remove unused cells and wires). 2509s Finding unused cells or wires in module \design_ice.. 2509s 2509s 2.29.8. Executing OPT_EXPR pass (perform const folding). 2509s Optimizing module design_ice. 2509s 2509s 2.29.9. Finished OPT passes. (There is nothing left to do.) 2509s 2509s 2.30. Executing ICE40_WRAPCARRY pass (wrap carries). 2509s 2509s 2.31. Executing TECHMAP pass (map to technology primitives). 2509s 2509s 2.31.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v 2509s Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation. 2509s Generating RTLIL representation for module `\_90_simplemap_bool_ops'. 2509s Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. 2509s Generating RTLIL representation for module `\_90_simplemap_logic_ops'. 2509s Generating RTLIL representation for module `\_90_simplemap_compare_ops'. 2509s Generating RTLIL representation for module `\_90_simplemap_various'. 2509s Generating RTLIL representation for module `\_90_simplemap_registers'. 2509s Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. 2509s Generating RTLIL representation for module `\_90_shift_shiftx'. 2509s Generating RTLIL representation for module `\_90_fa'. 2509s Generating RTLIL representation for module `\_90_lcu'. 2509s Generating RTLIL representation for module `\_90_alu'. 2509s Generating RTLIL representation for module `\_90_macc'. 2509s Generating RTLIL representation for module `\_90_alumacc'. 2509s Generating RTLIL representation for module `\$__div_mod_u'. 2509s Generating RTLIL representation for module `\$__div_mod_trunc'. 2509s Generating RTLIL representation for module `\_90_div'. 2509s Generating RTLIL representation for module `\_90_mod'. 2509s Generating RTLIL representation for module `\$__div_mod_floor'. 2509s Generating RTLIL representation for module `\_90_divfloor'. 2509s Generating RTLIL representation for module `\_90_modfloor'. 2509s Generating RTLIL representation for module `\_90_pow'. 2509s Generating RTLIL representation for module `\_90_pmux'. 2509s Generating RTLIL representation for module `\_90_demux'. 2509s Generating RTLIL representation for module `\_90_lut'. 2509s Successfully finished Verilog frontend. 2509s 2509s 2.31.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v 2509s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation. 2509s Generating RTLIL representation for module `\_80_ice40_alu'. 2509s Successfully finished Verilog frontend. 2509s 2509s 2.31.3. Continuing TECHMAP pass. 2509s Using extmapper simplemap for cells of type $dffe. 2509s Using extmapper simplemap for cells of type $dff. 2509s No more expansions possible. 2509s 2509s 2509s 2.32. Executing OPT pass (performing simple optimizations). 2509s 2509s 2.32.1. Executing OPT_EXPR pass (perform const folding). 2509s Optimizing module design_ice. 2509s 2509s 2.32.2. Executing OPT_MERGE pass (detect identical cells). 2509s Finding identical cells in module `\design_ice'. 2509s Removed a total of 0 cells. 2509s 2509s 2.32.3. Executing OPT_DFF pass (perform DFF optimizations). 2509s 2509s 2.32.4. Executing OPT_CLEAN pass (remove unused cells and wires). 2509s Finding unused cells or wires in module \design_ice.. 2509s 2509s 2.32.5. Finished fast OPT passes. 2509s 2509s 2.33. Executing ICE40_OPT pass (performing simple optimizations). 2509s 2509s 2.33.1. Running ICE40 specific optimizations. 2509s 2509s 2.33.2. Executing OPT_EXPR pass (perform const folding). 2509s Optimizing module design_ice. 2509s 2509s 2.33.3. Executing OPT_MERGE pass (detect identical cells). 2509s Finding identical cells in module `\design_ice'. 2509s Removed a total of 0 cells. 2509s 2509s 2.33.4. Executing OPT_DFF pass (perform DFF optimizations). 2509s 2509s 2.33.5. Executing OPT_CLEAN pass (remove unused cells and wires). 2509s Finding unused cells or wires in module \design_ice.. 2509s 2509s 2.33.6. Finished OPT passes. (There is nothing left to do.) 2509s 2509s 2.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 2509s 2509s 2.35. Executing TECHMAP pass (map to technology primitives). 2509s 2509s 2.35.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 2509s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 2509s Generating RTLIL representation for module `\$_DFF_N_'. 2509s Generating RTLIL representation for module `\$_DFF_P_'. 2509s Generating RTLIL representation for module `\$_DFFE_NP_'. 2509s Generating RTLIL representation for module `\$_DFFE_PP_'. 2509s Generating RTLIL representation for module `\$_DFF_NP0_'. 2509s Generating RTLIL representation for module `\$_DFF_NP1_'. 2509s Generating RTLIL representation for module `\$_DFF_PP0_'. 2509s Generating RTLIL representation for module `\$_DFF_PP1_'. 2509s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 2509s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 2509s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 2509s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 2509s Generating RTLIL representation for module `\$_SDFF_NP0_'. 2509s Generating RTLIL representation for module `\$_SDFF_NP1_'. 2509s Generating RTLIL representation for module `\$_SDFF_PP0_'. 2509s Generating RTLIL representation for module `\$_SDFF_PP1_'. 2509s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 2509s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 2509s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 2509s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 2509s Successfully finished Verilog frontend. 2509s 2509s 2.35.2. Continuing TECHMAP pass. 2509s Using template \$_DFF_P_ for cells of type $_DFF_P_. 2509s Using template \$_DFFE_PP_ for cells of type $_DFFE_PP_. 2509s No more expansions possible. 2509s 2509s 2509s 2.36. Executing OPT_EXPR pass (perform const folding). 2509s Optimizing module design_ice. 2509s 2509s 2.37. Executing SIMPLEMAP pass (map simple cells to gate primitives). 2509s 2509s 2.38. Executing ICE40_OPT pass (performing simple optimizations). 2509s 2509s 2.38.1. Running ICE40 specific optimizations. 2509s 2509s 2.38.2. Executing OPT_EXPR pass (perform const folding). 2509s Optimizing module design_ice. 2509s 2509s 2.38.3. Executing OPT_MERGE pass (detect identical cells). 2509s Finding identical cells in module `\design_ice'. 2509s Removed a total of 0 cells. 2509s 2509s 2.38.4. Executing OPT_DFF pass (perform DFF optimizations). 2509s 2509s 2.38.5. Executing OPT_CLEAN pass (remove unused cells and wires). 2509s Finding unused cells or wires in module \design_ice.. 2509s Removed 0 unused cells and 9 unused wires. 2509s 2509s 2509s 2.38.6. Rerunning OPT passes. (Removed registers in this run.) 2509s 2509s 2.38.7. Running ICE40 specific optimizations. 2509s 2509s 2.38.8. Executing OPT_EXPR pass (perform const folding). 2509s Optimizing module design_ice. 2509s 2509s 2.38.9. Executing OPT_MERGE pass (detect identical cells). 2509s Finding identical cells in module `\design_ice'. 2509s Removed a total of 0 cells. 2509s 2509s 2.38.10. Executing OPT_DFF pass (perform DFF optimizations). 2509s 2509s 2.38.11. Executing OPT_CLEAN pass (remove unused cells and wires). 2509s Finding unused cells or wires in module \design_ice.. 2509s 2509s 2.38.12. Finished OPT passes. (There is nothing left to do.) 2509s 2509s 2.39. Executing TECHMAP pass (map to technology primitives). 2509s 2509s 2.39.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v 2509s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation. 2509s Generating RTLIL representation for module `\$_DLATCH_N_'. 2509s Generating RTLIL representation for module `\$_DLATCH_P_'. 2509s Successfully finished Verilog frontend. 2509s 2509s 2.39.2. Continuing TECHMAP pass. 2509s No more expansions possible. 2509s 2509s 2509s 2.40. Executing ABC pass (technology mapping using ABC). 2509s 2509s 2.40.1. Extracting gate netlist of module `\design_ice' to `/input.blif'.. 2509s Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs. 2509s Don't call ABC as there is nothing to map. 2509s Removing temp directory. 2509s 2509s 2.41. Executing ICE40_WRAPCARRY pass (wrap carries). 2509s 2509s 2.42. Executing TECHMAP pass (map to technology primitives). 2509s 2509s 2.42.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 2509s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 2509s Generating RTLIL representation for module `\$_DFF_N_'. 2509s Generating RTLIL representation for module `\$_DFF_P_'. 2509s Generating RTLIL representation for module `\$_DFFE_NP_'. 2509s Generating RTLIL representation for module `\$_DFFE_PP_'. 2509s Generating RTLIL representation for module `\$_DFF_NP0_'. 2509s Generating RTLIL representation for module `\$_DFF_NP1_'. 2509s Generating RTLIL representation for module `\$_DFF_PP0_'. 2509s Generating RTLIL representation for module `\$_DFF_PP1_'. 2509s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 2509s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 2509s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 2509s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 2509s Generating RTLIL representation for module `\$_SDFF_NP0_'. 2509s Generating RTLIL representation for module `\$_SDFF_NP1_'. 2509s Generating RTLIL representation for module `\$_SDFF_PP0_'. 2509s Generating RTLIL representation for module `\$_SDFF_PP1_'. 2509s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 2509s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 2509s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 2509s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 2509s Successfully finished Verilog frontend. 2509s 2509s 2.42.2. Continuing TECHMAP pass. 2509s No more expansions possible. 2509s 2509s 2509s 2.43. Executing OPT_LUT pass (optimize LUTs). 2509s Discovering LUTs. 2509s Number of LUTs: 0 2509s with \SB_CARRY (#0) 0 2509s with \SB_CARRY (#1) 0 2509s 2509s Eliminating LUTs. 2509s Number of LUTs: 0 2509s with \SB_CARRY (#0) 0 2509s with \SB_CARRY (#1) 0 2509s 2509s Combining LUTs. 2509s Number of LUTs: 0 2509s with \SB_CARRY (#0) 0 2509s with \SB_CARRY (#1) 0 2509s 2509s Eliminated 0 LUTs. 2509s Combined 0 LUTs. 2509s 2509s 2.44. Executing TECHMAP pass (map to technology primitives). 2509s 2509s 2.44.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v 2509s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation. 2509s Generating RTLIL representation for module `\$lut'. 2509s Successfully finished Verilog frontend. 2509s 2509s 2.44.2. Continuing TECHMAP pass. 2509s No more expansions possible. 2509s 2509s 2509s 2.45. Executing AUTONAME pass. 2509s Renamed 2 objects in module design_ice (2 iterations). 2509s 2509s 2509s 2.46. Executing HIERARCHY pass (managing design hierarchy). 2509s 2509s 2.46.1. Analyzing design hierarchy.. 2509s Top module: \design_ice 2509s 2509s 2.46.2. Analyzing design hierarchy.. 2509s Top module: \design_ice 2509s Removed 0 unused modules. 2509s 2509s 2.47. Printing statistics. 2509s 2509s === design_ice === 2509s 2509s Number of wires: 5 2509s Number of wire bits: 5 2509s Number of public wires: 5 2509s Number of public wire bits: 5 2509s Number of memories: 0 2509s Number of memory bits: 0 2509s Number of processes: 0 2509s Number of cells: 2 2509s SB_DFF 1 2509s SB_DFFE 1 2509s 2509s 2.48. Executing CHECK pass (checking for obvious problems). 2509s Checking module design_ice... 2509s Found and reported 0 problems. 2509s 2509s 2.49. Executing BLIF backend. 2509s 2509s End of script. Logfile hash: 2f0f4cb58f, CPU: user 0.88s system 0.02s, MEM: 13.75 MB peak 2509s Yosys 0.33 (git sha1 2584903a060) 2509s Time spent: 73% 13x read_verilog (0 sec), 7% 1x synth_ice40 (0 sec), ... 2510s autopkgtest [19:10:08]: test ice: -----------------------] 2513s ice PASS 2513s autopkgtest [19:10:11]: test ice: - - - - - - - - - - results - - - - - - - - - - 2518s autopkgtest [19:10:16]: test smtbc: preparing testbed 2519s Reading package lists... 2520s Building dependency tree... 2520s Reading state information... 2520s Starting pkgProblemResolver with broken count: 0 2520s Starting 2 pkgProblemResolver with broken count: 0 2520s Done 2521s 0 upgraded, 0 newly installed, 0 to remove and 0 not upgraded. 2528s autopkgtest [19:10:26]: test smtbc: [----------------------- 2530s autopkgtest [19:10:28]: test smtbc: -----------------------] 2534s smtbc PASS 2534s autopkgtest [19:10:32]: test smtbc: - - - - - - - - - - results - - - - - - - - - - 2537s autopkgtest [19:10:35]: @@@@@@@@@@@@@@@@@@@@ summary 2537s yosys-testsuite PASS 2537s ice PASS 2537s smtbc PASS