0s autopkgtest [17:41:30]: starting date and time: 2025-03-15 17:41:30+0000 0s autopkgtest [17:41:30]: git checkout: 325255d2 Merge branch 'pin-any-arch' into 'ubuntu/production' 0s autopkgtest [17:41:30]: host juju-7f2275-prod-proposed-migration-environment-15; command line: /home/ubuntu/autopkgtest/runner/autopkgtest --output-dir /tmp/autopkgtest-work.f06rdtz5/out --timeout-copy=6000 --setup-commands /home/ubuntu/autopkgtest-cloud/worker-config-production/setup-canonical.sh --apt-pocket=proposed=src:glibc --apt-upgrade yosys --timeout-short=300 --timeout-copy=20000 --timeout-build=20000 --env=ADT_TEST_TRIGGERS=glibc/2.41-1ubuntu2 -- ssh -s /home/ubuntu/autopkgtest/ssh-setup/nova -- --flavor autopkgtest --security-groups autopkgtest-juju-7f2275-prod-proposed-migration-environment-15@bos03-arm64-27.secgroup --name adt-plucky-arm64-yosys-20250315-174129-juju-7f2275-prod-proposed-migration-environment-15-39d412b6-f4d7-4093-a6ab-b77872e4ce22 --image adt/ubuntu-plucky-arm64-server --keyname testbed-juju-7f2275-prod-proposed-migration-environment-15 --net-id=net_prod-proposed-migration -e TERM=linux -e ''"'"'http_proxy=http://squid.internal:3128'"'"'' -e ''"'"'https_proxy=http://squid.internal:3128'"'"'' -e ''"'"'no_proxy=127.0.0.1,127.0.1.1,login.ubuntu.com,localhost,localdomain,novalocal,internal,archive.ubuntu.com,ports.ubuntu.com,security.ubuntu.com,ddebs.ubuntu.com,changelogs.ubuntu.com,keyserver.ubuntu.com,launchpadlibrarian.net,launchpadcontent.net,launchpad.net,10.24.0.0/24,keystone.ps5.canonical.com,objectstorage.prodstack5.canonical.com,radosgw.ps5.canonical.com'"'"'' --mirror=http://ftpmaster.internal/ubuntu/ 179s autopkgtest [17:44:29]: testbed dpkg architecture: arm64 179s autopkgtest [17:44:29]: testbed apt version: 2.9.33 181s autopkgtest [17:44:31]: @@@@@@@@@@@@@@@@@@@@ test bed setup 183s autopkgtest [17:44:33]: testbed release detected to be: None 184s autopkgtest [17:44:34]: updating testbed package index (apt update) 185s Get:1 http://ftpmaster.internal/ubuntu plucky-proposed InRelease [126 kB] 185s Hit:2 http://ftpmaster.internal/ubuntu plucky InRelease 185s Hit:3 http://ftpmaster.internal/ubuntu plucky-updates InRelease 185s Hit:4 http://ftpmaster.internal/ubuntu plucky-security InRelease 185s Get:5 http://ftpmaster.internal/ubuntu plucky-proposed/multiverse Sources [15.8 kB] 185s Get:6 http://ftpmaster.internal/ubuntu plucky-proposed/universe Sources [379 kB] 185s Get:7 http://ftpmaster.internal/ubuntu plucky-proposed/main Sources [99.7 kB] 185s Get:8 http://ftpmaster.internal/ubuntu plucky-proposed/main arm64 Packages [111 kB] 185s Get:9 http://ftpmaster.internal/ubuntu plucky-proposed/main arm64 c-n-f Metadata [1856 B] 185s Get:10 http://ftpmaster.internal/ubuntu plucky-proposed/restricted arm64 c-n-f Metadata [116 B] 185s Get:11 http://ftpmaster.internal/ubuntu plucky-proposed/universe arm64 Packages [324 kB] 185s Get:12 http://ftpmaster.internal/ubuntu plucky-proposed/universe arm64 c-n-f Metadata [14.7 kB] 185s Get:13 http://ftpmaster.internal/ubuntu plucky-proposed/multiverse arm64 Packages [4948 B] 185s Get:14 http://ftpmaster.internal/ubuntu plucky-proposed/multiverse arm64 c-n-f Metadata [268 B] 186s Fetched 1078 kB in 1s (1169 kB/s) 187s Reading package lists... 187s + lsb_release --codename --short 187s + RELEASE=plucky 187s + cat 187s + [ plucky != trusty ] 187s + DEBIAN_FRONTEND=noninteractive eatmydata apt-get -y --allow-downgrades -o Dpkg::Options::=--force-confnew dist-upgrade 187s Reading package lists... 188s Building dependency tree... 188s Reading state information... 188s Calculating upgrade... 189s Calculating upgrade... 189s The following packages will be upgraded: 189s pinentry-curses python3-jinja2 strace 189s 3 upgraded, 0 newly installed, 0 to remove and 0 not upgraded. 189s Need to get 647 kB of archives. 189s After this operation, 11.3 kB of additional disk space will be used. 189s Get:1 http://ftpmaster.internal/ubuntu plucky/main arm64 strace arm64 6.13+ds-1ubuntu1 [499 kB] 190s Get:2 http://ftpmaster.internal/ubuntu plucky/main arm64 pinentry-curses arm64 1.3.1-2ubuntu3 [39.2 kB] 190s Get:3 http://ftpmaster.internal/ubuntu plucky/main arm64 python3-jinja2 all 3.1.5-2ubuntu1 [109 kB] 190s Fetched 647 kB in 1s (1055 kB/s) 191s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 117701 files and directories currently installed.) 191s Preparing to unpack .../strace_6.13+ds-1ubuntu1_arm64.deb ... 191s Unpacking strace (6.13+ds-1ubuntu1) over (6.11-0ubuntu1) ... 191s Preparing to unpack .../pinentry-curses_1.3.1-2ubuntu3_arm64.deb ... 191s Unpacking pinentry-curses (1.3.1-2ubuntu3) over (1.3.1-2ubuntu2) ... 191s Preparing to unpack .../python3-jinja2_3.1.5-2ubuntu1_all.deb ... 191s Unpacking python3-jinja2 (3.1.5-2ubuntu1) over (3.1.5-2) ... 191s Setting up pinentry-curses (1.3.1-2ubuntu3) ... 191s Setting up python3-jinja2 (3.1.5-2ubuntu1) ... 191s Setting up strace (6.13+ds-1ubuntu1) ... 191s Processing triggers for man-db (2.13.0-1) ... 192s + rm /etc/apt/preferences.d/force-downgrade-to-release.pref 192s + /usr/lib/apt/apt-helper analyze-pattern ?true 192s + + uname -r 192s sed s/\./\\./g 192s + running_kernel_pattern=^linux-.*6\.14\.0-10-generic.* 192s + apt list ?obsolete 192s + tail -n+2 192s + cut -d/ -f1 192s + grep -v ^linux-.*6\.14\.0-10-generic.* 193s + obsolete_pkgs=linux-headers-6.11.0-8-generic 193s linux-headers-6.11.0-8 193s linux-image-6.11.0-8-generic 193s linux-modules-6.11.0-8-generic 193s linux-tools-6.11.0-8-generic 193s linux-tools-6.11.0-8 193s + DEBIAN_FRONTEND=noninteractive eatmydata apt-get -y purge --autoremove linux-headers-6.11.0-8-generic linux-headers-6.11.0-8 linux-image-6.11.0-8-generic linux-modules-6.11.0-8-generic linux-tools-6.11.0-8-generic linux-tools-6.11.0-8 193s Reading package lists... 193s Building dependency tree... 193s Reading state information... 194s Solving dependencies... 194s The following packages will be REMOVED: 194s libnsl2* libpython3.12-minimal* libpython3.12-stdlib* libpython3.12t64* 194s libunwind8* linux-headers-6.11.0-8* linux-headers-6.11.0-8-generic* 194s linux-image-6.11.0-8-generic* linux-modules-6.11.0-8-generic* 194s linux-tools-6.11.0-8* linux-tools-6.11.0-8-generic* 195s 0 upgraded, 0 newly installed, 11 to remove and 5 not upgraded. 195s After this operation, 267 MB disk space will be freed. 195s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 117701 files and directories currently installed.) 195s Removing linux-tools-6.11.0-8-generic (6.11.0-8.8) ... 195s Removing linux-tools-6.11.0-8 (6.11.0-8.8) ... 195s Removing libpython3.12t64:arm64 (3.12.9-1) ... 195s Removing libpython3.12-stdlib:arm64 (3.12.9-1) ... 195s Removing libnsl2:arm64 (1.3.0-3build3) ... 195s Removing libpython3.12-minimal:arm64 (3.12.9-1) ... 195s Removing libunwind8:arm64 (1.6.2-3.1) ... 195s Removing linux-headers-6.11.0-8-generic (6.11.0-8.8) ... 195s Removing linux-headers-6.11.0-8 (6.11.0-8.8) ... 197s Removing linux-image-6.11.0-8-generic (6.11.0-8.8) ... 197s I: /boot/vmlinuz.old is now a symlink to vmlinuz-6.14.0-10-generic 197s I: /boot/initrd.img.old is now a symlink to initrd.img-6.14.0-10-generic 197s /etc/kernel/postrm.d/initramfs-tools: 197s update-initramfs: Deleting /boot/initrd.img-6.11.0-8-generic 197s /etc/kernel/postrm.d/zz-flash-kernel: 197s flash-kernel: Kernel 6.11.0-8-generic has been removed. 197s flash-kernel: A higher version (6.14.0-10-generic) is still installed, no reflashing required. 197s /etc/kernel/postrm.d/zz-update-grub: 197s Sourcing file `/etc/default/grub' 197s Sourcing file `/etc/default/grub.d/50-cloudimg-settings.cfg' 197s Generating grub configuration file ... 198s Found linux image: /boot/vmlinuz-6.14.0-10-generic 198s Found initrd image: /boot/initrd.img-6.14.0-10-generic 198s Warning: os-prober will not be executed to detect other bootable partitions. 198s Systems on them will not be added to the GRUB boot configuration. 198s Check GRUB_DISABLE_OS_PROBER documentation entry. 198s Adding boot menu entry for UEFI Firmware Settings ... 198s done 198s Removing linux-modules-6.11.0-8-generic (6.11.0-8.8) ... 198s Processing triggers for libc-bin (2.41-1ubuntu1) ... 198s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 81650 files and directories currently installed.) 198s Purging configuration files for linux-image-6.11.0-8-generic (6.11.0-8.8) ... 199s Purging configuration files for libpython3.12-minimal:arm64 (3.12.9-1) ... 199s Purging configuration files for linux-modules-6.11.0-8-generic (6.11.0-8.8) ... 199s + grep -q trusty /etc/lsb-release 199s + [ ! -d /usr/share/doc/unattended-upgrades ] 199s + [ ! -d /usr/share/doc/lxd ] 199s + [ ! -d /usr/share/doc/lxd-client ] 199s + [ ! -d /usr/share/doc/snapd ] 199s + type iptables 199s + cat 199s + chmod 755 /etc/rc.local 199s + . /etc/rc.local 199s + iptables -w -t mangle -A FORWARD -p tcp --tcp-flags SYN,RST SYN -j TCPMSS --clamp-mss-to-pmtu 199s + iptables -A OUTPUT -d 10.255.255.1/32 -p tcp -j DROP 199s + iptables -A OUTPUT -d 10.255.255.2/32 -p tcp -j DROP 199s + uname -m 199s + [ aarch64 = ppc64le ] 199s + [ -d /run/systemd/system ] 199s + systemd-detect-virt --quiet --vm 199s + mkdir -p /etc/systemd/system/systemd-random-seed.service.d/ 199s + cat 199s + grep -q lz4 /etc/initramfs-tools/initramfs.conf 199s + echo COMPRESS=lz4 199s autopkgtest [17:44:49]: upgrading testbed (apt dist-upgrade and autopurge) 199s Reading package lists... 199s Building dependency tree... 199s Reading state information... 200s Calculating upgrade...Starting pkgProblemResolver with broken count: 0 200s Starting 2 pkgProblemResolver with broken count: 0 200s Done 201s Entering ResolveByKeep 201s 202s Calculating upgrade... 202s The following packages will be upgraded: 202s libc-bin libc-dev-bin libc6 libc6-dev locales 202s 5 upgraded, 0 newly installed, 0 to remove and 0 not upgraded. 202s Need to get 9530 kB of archives. 202s After this operation, 0 B of additional disk space will be used. 202s Get:1 http://ftpmaster.internal/ubuntu plucky-proposed/main arm64 libc6-dev arm64 2.41-1ubuntu2 [1750 kB] 203s Get:2 http://ftpmaster.internal/ubuntu plucky-proposed/main arm64 libc-dev-bin arm64 2.41-1ubuntu2 [24.0 kB] 203s Get:3 http://ftpmaster.internal/ubuntu plucky-proposed/main arm64 libc6 arm64 2.41-1ubuntu2 [2910 kB] 203s Get:4 http://ftpmaster.internal/ubuntu plucky-proposed/main arm64 libc-bin arm64 2.41-1ubuntu2 [600 kB] 203s Get:5 http://ftpmaster.internal/ubuntu plucky-proposed/main arm64 locales all 2.41-1ubuntu2 [4246 kB] 204s Preconfiguring packages ... 204s Fetched 9530 kB in 2s (5797 kB/s) 204s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 81647 files and directories currently installed.) 204s Preparing to unpack .../libc6-dev_2.41-1ubuntu2_arm64.deb ... 204s Unpacking libc6-dev:arm64 (2.41-1ubuntu2) over (2.41-1ubuntu1) ... 204s Preparing to unpack .../libc-dev-bin_2.41-1ubuntu2_arm64.deb ... 204s Unpacking libc-dev-bin (2.41-1ubuntu2) over (2.41-1ubuntu1) ... 204s Preparing to unpack .../libc6_2.41-1ubuntu2_arm64.deb ... 205s Unpacking libc6:arm64 (2.41-1ubuntu2) over (2.41-1ubuntu1) ... 205s Setting up libc6:arm64 (2.41-1ubuntu2) ... 205s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 81647 files and directories currently installed.) 205s Preparing to unpack .../libc-bin_2.41-1ubuntu2_arm64.deb ... 205s Unpacking libc-bin (2.41-1ubuntu2) over (2.41-1ubuntu1) ... 205s Setting up libc-bin (2.41-1ubuntu2) ... 205s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 81647 files and directories currently installed.) 205s Preparing to unpack .../locales_2.41-1ubuntu2_all.deb ... 205s Unpacking locales (2.41-1ubuntu2) over (2.41-1ubuntu1) ... 205s Setting up locales (2.41-1ubuntu2) ... 206s Generating locales (this might take a while)... 208s en_US.UTF-8... done 208s Generation complete. 208s Setting up libc-dev-bin (2.41-1ubuntu2) ... 208s Setting up libc6-dev:arm64 (2.41-1ubuntu2) ... 208s Processing triggers for man-db (2.13.0-1) ... 209s Processing triggers for systemd (257.3-1ubuntu3) ... 210s Reading package lists... 210s Building dependency tree... 210s Reading state information... 211s Starting pkgProblemResolver with broken count: 0 211s Starting 2 pkgProblemResolver with broken count: 0 211s Done 211s Solving dependencies... 212s 0 upgraded, 0 newly installed, 0 to remove and 0 not upgraded. 212s autopkgtest [17:45:02]: rebooting testbed after setup commands that affected boot 237s autopkgtest [17:45:27]: testbed running kernel: Linux 6.14.0-10-generic #10-Ubuntu SMP PREEMPT_DYNAMIC Wed Mar 12 15:45:31 UTC 2025 240s autopkgtest [17:45:30]: @@@@@@@@@@@@@@@@@@@@ apt-source yosys 246s Get:1 http://ftpmaster.internal/ubuntu plucky/universe yosys 0.33-5build2 (dsc) [3069 B] 246s Get:2 http://ftpmaster.internal/ubuntu plucky/universe yosys 0.33-5build2 (tar) [6161 kB] 246s Get:3 http://ftpmaster.internal/ubuntu plucky/universe yosys 0.33-5build2 (tar) [2586 kB] 246s Get:4 http://ftpmaster.internal/ubuntu plucky/universe yosys 0.33-5build2 (diff) [30.3 kB] 247s gpgv: Signature made Mon Apr 1 04:53:46 2024 UTC 247s gpgv: using RSA key A089FB36AAFBDAD5ACC1325069F790171A210984 247s gpgv: Can't check signature: No public key 247s dpkg-source: warning: cannot verify inline signature for ./yosys_0.33-5build2.dsc: no acceptable signature found 247s autopkgtest [17:45:37]: testing package yosys version 0.33-5build2 248s autopkgtest [17:45:38]: build not needed 253s autopkgtest [17:45:43]: test yosys-testsuite: preparing testbed 254s Reading package lists... 254s Building dependency tree... 254s Reading state information... 254s Starting pkgProblemResolver with broken count: 0 254s Starting 2 pkgProblemResolver with broken count: 0 254s Done 255s The following NEW packages will be installed: 255s cpp cpp-14 cpp-14-aarch64-linux-gnu cpp-aarch64-linux-gnu g++ g++-14 255s g++-14-aarch64-linux-gnu g++-aarch64-linux-gnu gcc gcc-14 255s gcc-14-aarch64-linux-gnu gcc-aarch64-linux-gnu iverilog libasan8 libcc1-0 255s libffi-dev libgcc-14-dev libgomp1 libhwasan0 libisl23 libitm1 liblsan0 255s libmpc3 libncurses-dev libpkgconf3 libreadline-dev libstdc++-14-dev 255s libtcl8.6 libtsan2 libubsan1 pkg-config pkgconf pkgconf-bin python3-click 255s tcl tcl-dev tcl8.6 tcl8.6-dev yosys yosys-abc yosys-dev zlib1g-dev 255s 0 upgraded, 42 newly installed, 0 to remove and 0 not upgraded. 255s Need to get 74.6 MB of archives. 255s After this operation, 258 MB of additional disk space will be used. 255s Get:1 http://ftpmaster.internal/ubuntu plucky/main arm64 libisl23 arm64 0.27-1 [676 kB] 256s Get:2 http://ftpmaster.internal/ubuntu plucky/main arm64 libmpc3 arm64 1.3.1-1build2 [56.8 kB] 256s Get:3 http://ftpmaster.internal/ubuntu plucky/main arm64 cpp-14-aarch64-linux-gnu arm64 14.2.0-17ubuntu3 [10.6 MB] 260s Get:4 http://ftpmaster.internal/ubuntu plucky/main arm64 cpp-14 arm64 14.2.0-17ubuntu3 [1028 B] 260s Get:5 http://ftpmaster.internal/ubuntu plucky/main arm64 cpp-aarch64-linux-gnu arm64 4:14.2.0-1ubuntu1 [5558 B] 260s Get:6 http://ftpmaster.internal/ubuntu plucky/main arm64 cpp arm64 4:14.2.0-1ubuntu1 [22.4 kB] 260s Get:7 http://ftpmaster.internal/ubuntu plucky/main arm64 libcc1-0 arm64 15-20250222-0ubuntu1 [44.2 kB] 260s Get:8 http://ftpmaster.internal/ubuntu plucky/main arm64 libgomp1 arm64 15-20250222-0ubuntu1 [146 kB] 260s Get:9 http://ftpmaster.internal/ubuntu plucky/main arm64 libitm1 arm64 15-20250222-0ubuntu1 [28.0 kB] 260s Get:10 http://ftpmaster.internal/ubuntu plucky/main arm64 libasan8 arm64 15-20250222-0ubuntu1 [2924 kB] 262s Get:11 http://ftpmaster.internal/ubuntu plucky/main arm64 liblsan0 arm64 15-20250222-0ubuntu1 [1319 kB] 262s Get:12 http://ftpmaster.internal/ubuntu plucky/main arm64 libtsan2 arm64 15-20250222-0ubuntu1 [2694 kB] 264s Get:13 http://ftpmaster.internal/ubuntu plucky/main arm64 libubsan1 arm64 15-20250222-0ubuntu1 [1178 kB] 264s Get:14 http://ftpmaster.internal/ubuntu plucky/main arm64 libhwasan0 arm64 15-20250222-0ubuntu1 [1642 kB] 265s Get:15 http://ftpmaster.internal/ubuntu plucky/main arm64 libgcc-14-dev arm64 14.2.0-17ubuntu3 [2593 kB] 265s Get:16 http://ftpmaster.internal/ubuntu plucky/main arm64 gcc-14-aarch64-linux-gnu arm64 14.2.0-17ubuntu3 [20.9 MB] 270s Get:17 http://ftpmaster.internal/ubuntu plucky/main arm64 gcc-14 arm64 14.2.0-17ubuntu3 [526 kB] 270s Get:18 http://ftpmaster.internal/ubuntu plucky/main arm64 gcc-aarch64-linux-gnu arm64 4:14.2.0-1ubuntu1 [1200 B] 270s Get:19 http://ftpmaster.internal/ubuntu plucky/main arm64 gcc arm64 4:14.2.0-1ubuntu1 [4998 B] 270s Get:20 http://ftpmaster.internal/ubuntu plucky/main arm64 libstdc++-14-dev arm64 14.2.0-17ubuntu3 [2499 kB] 271s Get:21 http://ftpmaster.internal/ubuntu plucky/main arm64 g++-14-aarch64-linux-gnu arm64 14.2.0-17ubuntu3 [12.1 MB] 274s Get:22 http://ftpmaster.internal/ubuntu plucky/main arm64 g++-14 arm64 14.2.0-17ubuntu3 [21.8 kB] 274s Get:23 http://ftpmaster.internal/ubuntu plucky/main arm64 g++-aarch64-linux-gnu arm64 4:14.2.0-1ubuntu1 [956 B] 274s Get:24 http://ftpmaster.internal/ubuntu plucky/main arm64 g++ arm64 4:14.2.0-1ubuntu1 [1080 B] 274s Get:25 http://ftpmaster.internal/ubuntu plucky/universe arm64 iverilog arm64 12.0-2build2 [2065 kB] 275s Get:26 http://ftpmaster.internal/ubuntu plucky/main arm64 libncurses-dev arm64 6.5+20250216-2 [389 kB] 275s Get:27 http://ftpmaster.internal/ubuntu plucky/main arm64 libpkgconf3 arm64 1.8.1-4 [31.4 kB] 275s Get:28 http://ftpmaster.internal/ubuntu plucky/main arm64 libreadline-dev arm64 8.2-6 [179 kB] 275s Get:29 http://ftpmaster.internal/ubuntu plucky/main arm64 libtcl8.6 arm64 8.6.16+dfsg-1 [987 kB] 275s Get:30 http://ftpmaster.internal/ubuntu plucky/main arm64 pkgconf-bin arm64 1.8.1-4 [20.9 kB] 275s Get:31 http://ftpmaster.internal/ubuntu plucky/main arm64 pkgconf arm64 1.8.1-4 [16.7 kB] 275s Get:32 http://ftpmaster.internal/ubuntu plucky/main arm64 pkg-config arm64 1.8.1-4 [7362 B] 275s Get:33 http://ftpmaster.internal/ubuntu plucky/main arm64 python3-click all 8.2.0+0.really.8.1.8-1 [80.0 kB] 276s Get:34 http://ftpmaster.internal/ubuntu plucky/main arm64 tcl8.6 arm64 8.6.16+dfsg-1 [14.8 kB] 276s Get:35 http://ftpmaster.internal/ubuntu plucky/main arm64 tcl arm64 8.6.14build1 [4124 B] 276s Get:36 http://ftpmaster.internal/ubuntu plucky/main arm64 zlib1g-dev arm64 1:1.3.dfsg+really1.3.1-1ubuntu1 [894 kB] 276s Get:37 http://ftpmaster.internal/ubuntu plucky/main arm64 tcl8.6-dev arm64 8.6.16+dfsg-1 [1036 kB] 276s Get:38 http://ftpmaster.internal/ubuntu plucky/main arm64 tcl-dev arm64 8.6.14build1 [5766 B] 276s Get:39 http://ftpmaster.internal/ubuntu plucky/universe arm64 yosys-abc arm64 0.33-5build2 [5605 kB] 277s Get:40 http://ftpmaster.internal/ubuntu plucky/universe arm64 yosys arm64 0.33-5build2 [3098 kB] 278s Get:41 http://ftpmaster.internal/ubuntu plucky/main arm64 libffi-dev arm64 3.4.7-1 [59.5 kB] 278s Get:42 http://ftpmaster.internal/ubuntu plucky/universe arm64 yosys-dev arm64 0.33-5build2 [88.4 kB] 279s Fetched 74.6 MB in 23s (3207 kB/s) 279s Selecting previously unselected package libisl23:arm64. 279s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 81647 files and directories currently installed.) 279s Preparing to unpack .../00-libisl23_0.27-1_arm64.deb ... 279s Unpacking libisl23:arm64 (0.27-1) ... 279s Selecting previously unselected package libmpc3:arm64. 279s Preparing to unpack .../01-libmpc3_1.3.1-1build2_arm64.deb ... 279s Unpacking libmpc3:arm64 (1.3.1-1build2) ... 279s Selecting previously unselected package cpp-14-aarch64-linux-gnu. 279s Preparing to unpack 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libubsan1:arm64 (15-20250222-0ubuntu1) ... 283s Setting up zlib1g-dev:arm64 (1:1.3.dfsg+really1.3.1-1ubuntu1) ... 283s Setting up libhwasan0:arm64 (15-20250222-0ubuntu1) ... 283s Setting up libasan8:arm64 (15-20250222-0ubuntu1) ... 283s Setting up libtsan2:arm64 (15-20250222-0ubuntu1) ... 283s Setting up libisl23:arm64 (0.27-1) ... 283s Setting up libcc1-0:arm64 (15-20250222-0ubuntu1) ... 283s Setting up liblsan0:arm64 (15-20250222-0ubuntu1) ... 283s Setting up libitm1:arm64 (15-20250222-0ubuntu1) ... 283s Setting up tcl8.6 (8.6.16+dfsg-1) ... 283s Setting up tcl8.6-dev:arm64 (8.6.16+dfsg-1) ... 283s Setting up yosys (0.33-5build2) ... 283s Setting up pkgconf:arm64 (1.8.1-4) ... 283s Setting up pkg-config:arm64 (1.8.1-4) ... 283s Setting up cpp-14-aarch64-linux-gnu (14.2.0-17ubuntu3) ... 283s Setting up tcl (8.6.14build1) ... 283s Setting up libgcc-14-dev:arm64 (14.2.0-17ubuntu3) ... 283s Setting up libstdc++-14-dev:arm64 (14.2.0-17ubuntu3) ... 283s Setting up cpp-aarch64-linux-gnu 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testdir=. 287s + shift 287s + mkdir -p . 287s + cd . 287s + ln -sf /usr/bin/yosys . 287s + ln -sf /usr/bin/yosys-abc . 287s + ln -sf /usr/bin/yosys-config . 287s + sed -i s/^test:.*/test: $(EXTRA_TARGETS)/ Makefile 287s + make test CONFIG=gcc ABCPULL=0 287s mkdir -p share/include/kernel/ 287s cp "./"/kernel/yosys.h share/include/kernel/yosys.h 287s mkdir -p share/include/kernel/ 287s cp "./"/kernel/hashlib.h share/include/kernel/hashlib.h 287s mkdir -p share/include/kernel/ 287s cp "./"/kernel/log.h share/include/kernel/log.h 287s mkdir -p share/include/kernel/ 287s cp "./"/kernel/rtlil.h share/include/kernel/rtlil.h 287s mkdir -p share/include/kernel/ 287s cp "./"/kernel/binding.h share/include/kernel/binding.h 287s mkdir -p share/include/kernel/ 287s cp "./"/kernel/register.h share/include/kernel/register.h 287s mkdir -p share/include/kernel/ 287s cp "./"/kernel/cellaigs.h share/include/kernel/cellaigs.h 287s mkdir -p share/include/kernel/ 287s cp "./"/kernel/celltypes.h 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share/ecp5 287s cp "./"/techlibs/ecp5/brams_map.v share/ecp5/brams_map.v 287s mkdir -p share/ecp5 287s cp "./"/techlibs/ecp5/brams.txt share/ecp5/brams.txt 287s mkdir -p share/ecp5 287s cp "./"/techlibs/ecp5/arith_map.v share/ecp5/arith_map.v 287s mkdir -p share/ecp5 287s cp "./"/techlibs/ecp5/latches_map.v share/ecp5/latches_map.v 287s mkdir -p share/ecp5 287s cp "./"/techlibs/ecp5/dsp_map.v share/ecp5/dsp_map.v 287s mkdir -p share/efinix 287s cp "./"/techlibs/efinix/cells_map.v share/efinix/cells_map.v 287s mkdir -p share/efinix 287s cp "./"/techlibs/efinix/arith_map.v share/efinix/arith_map.v 287s mkdir -p share/efinix 287s cp "./"/techlibs/efinix/cells_sim.v share/efinix/cells_sim.v 287s mkdir -p share/efinix 287s cp "./"/techlibs/efinix/brams_map.v share/efinix/brams_map.v 287s mkdir -p share/efinix 287s cp "./"/techlibs/efinix/gbuf_map.v share/efinix/gbuf_map.v 287s mkdir -p share/efinix 287s cp "./"/techlibs/efinix/brams.txt share/efinix/brams.txt 287s mkdir -p share/fabulous 287s cp "./"/techlibs/fabulous/cells_map.v share/fabulous/cells_map.v 287s mkdir -p share/fabulous 287s cp "./"/techlibs/fabulous/prims.v share/fabulous/prims.v 287s mkdir -p share/fabulous 287s cp "./"/techlibs/fabulous/latches_map.v share/fabulous/latches_map.v 287s mkdir -p share/fabulous 287s cp "./"/techlibs/fabulous/ff_map.v share/fabulous/ff_map.v 287s mkdir -p share/fabulous 287s cp "./"/techlibs/fabulous/ram_regfile.txt share/fabulous/ram_regfile.txt 287s mkdir -p share/fabulous 287s cp "./"/techlibs/fabulous/regfile_map.v share/fabulous/regfile_map.v 287s mkdir -p share/fabulous 287s cp "./"/techlibs/fabulous/io_map.v share/fabulous/io_map.v 287s mkdir -p share/fabulous 287s cp "./"/techlibs/fabulous/arith_map.v share/fabulous/arith_map.v 287s mkdir -p share/gatemate 287s cp "./"/techlibs/gatemate/reg_map.v share/gatemate/reg_map.v 287s mkdir -p share/gatemate 287s cp "./"/techlibs/gatemate/mux_map.v share/gatemate/mux_map.v 287s mkdir -p share/gatemate 287s cp "./"/techlibs/gatemate/lut_map.v share/gatemate/lut_map.v 287s mkdir -p share/gatemate 287s cp "./"/techlibs/gatemate/mul_map.v share/gatemate/mul_map.v 287s mkdir -p share/gatemate 287s cp "./"/techlibs/gatemate/arith_map.v share/gatemate/arith_map.v 287s mkdir -p share/gatemate 287s cp "./"/techlibs/gatemate/cells_sim.v share/gatemate/cells_sim.v 287s mkdir -p share/gatemate 287s cp "./"/techlibs/gatemate/cells_bb.v share/gatemate/cells_bb.v 287s mkdir -p share/gatemate 287s cp "./"/techlibs/gatemate/brams_map.v share/gatemate/brams_map.v 287s mkdir -p share/gatemate 287s cp "./"/techlibs/gatemate/brams.txt share/gatemate/brams.txt 287s mkdir -p share/gatemate 287s cp "./"/techlibs/gatemate/brams_init_20.vh share/gatemate/brams_init_20.vh 287s mkdir -p share/gatemate 287s cp "./"/techlibs/gatemate/brams_init_40.vh share/gatemate/brams_init_40.vh 287s mkdir -p share/gatemate 287s cp "./"/techlibs/gatemate/inv_map.v share/gatemate/inv_map.v 287s mkdir -p techlibs/gatemate 287s python3 techlibs/gatemate/make_lut_tree_lib.py 287s touch techlibs/gatemate/lut_tree_lib.mk 287s mkdir -p share/gatemate 287s cp techlibs/gatemate/lut_tree_cells.genlib share/gatemate/lut_tree_cells.genlib 287s mkdir -p share/gatemate 287s cp techlibs/gatemate/lut_tree_map.v share/gatemate/lut_tree_map.v 287s mkdir -p share/gowin 287s cp "./"/techlibs/gowin/cells_map.v share/gowin/cells_map.v 287s mkdir -p share/gowin 287s cp "./"/techlibs/gowin/cells_sim.v share/gowin/cells_sim.v 287s mkdir -p share/gowin 287s cp "./"/techlibs/gowin/cells_xtra.v share/gowin/cells_xtra.v 287s mkdir -p share/gowin 287s cp "./"/techlibs/gowin/arith_map.v share/gowin/arith_map.v 287s mkdir -p share/gowin 287s cp "./"/techlibs/gowin/brams_map.v share/gowin/brams_map.v 287s mkdir -p share/gowin 287s cp "./"/techlibs/gowin/brams.txt share/gowin/brams.txt 287s mkdir -p share/gowin 287s cp "./"/techlibs/gowin/lutrams_map.v share/gowin/lutrams_map.v 287s mkdir -p share/gowin 287s cp "./"/techlibs/gowin/lutrams.txt share/gowin/lutrams.txt 287s mkdir -p share/greenpak4 287s cp "./"/techlibs/greenpak4/cells_blackbox.v share/greenpak4/cells_blackbox.v 287s mkdir -p share/greenpak4 287s cp "./"/techlibs/greenpak4/cells_latch.v share/greenpak4/cells_latch.v 287s mkdir -p share/greenpak4 287s cp "./"/techlibs/greenpak4/cells_map.v share/greenpak4/cells_map.v 287s mkdir -p share/greenpak4 287s cp "./"/techlibs/greenpak4/cells_sim.v share/greenpak4/cells_sim.v 287s mkdir -p share/greenpak4 287s cp "./"/techlibs/greenpak4/cells_sim_ams.v share/greenpak4/cells_sim_ams.v 287s mkdir -p share/greenpak4 287s cp "./"/techlibs/greenpak4/cells_sim_digital.v share/greenpak4/cells_sim_digital.v 287s mkdir -p share/greenpak4 287s cp "./"/techlibs/greenpak4/cells_sim_wip.v share/greenpak4/cells_sim_wip.v 287s mkdir -p share/greenpak4 287s cp "./"/techlibs/greenpak4/gp_dff.lib share/greenpak4/gp_dff.lib 287s mkdir -p share/ice40 287s cp "./"/techlibs/ice40/arith_map.v share/ice40/arith_map.v 287s mkdir -p share/ice40 287s cp "./"/techlibs/ice40/cells_map.v share/ice40/cells_map.v 287s mkdir -p share/ice40 287s cp "./"/techlibs/ice40/ff_map.v share/ice40/ff_map.v 287s mkdir -p share/ice40 287s cp "./"/techlibs/ice40/cells_sim.v share/ice40/cells_sim.v 287s mkdir -p share/ice40 287s cp "./"/techlibs/ice40/latches_map.v share/ice40/latches_map.v 287s mkdir -p share/ice40 287s cp "./"/techlibs/ice40/brams.txt share/ice40/brams.txt 287s mkdir -p share/ice40 287s cp "./"/techlibs/ice40/brams_map.v share/ice40/brams_map.v 287s mkdir -p share/ice40 287s cp "./"/techlibs/ice40/spram.txt share/ice40/spram.txt 287s mkdir -p share/ice40 287s cp "./"/techlibs/ice40/spram_map.v share/ice40/spram_map.v 287s mkdir -p share/ice40 287s cp "./"/techlibs/ice40/dsp_map.v share/ice40/dsp_map.v 287s mkdir -p share/ice40 287s cp "./"/techlibs/ice40/abc9_model.v share/ice40/abc9_model.v 287s mkdir -p share/intel/common 287s cp "./"/techlibs/intel/common/m9k_bb.v share/intel/common/m9k_bb.v 287s mkdir -p share/intel/common 287s cp "./"/techlibs/intel/common/altpll_bb.v share/intel/common/altpll_bb.v 287s mkdir -p share/intel/common 287s cp "./"/techlibs/intel/common/brams_m9k.txt share/intel/common/brams_m9k.txt 287s mkdir -p share/intel/common 287s cp "./"/techlibs/intel/common/brams_map_m9k.v share/intel/common/brams_map_m9k.v 287s mkdir -p share/intel/common 287s cp "./"/techlibs/intel/common/ff_map.v share/intel/common/ff_map.v 288s mkdir -p share/intel/max10 288s cp "./"/techlibs/intel/max10/cells_sim.v share/intel/max10/cells_sim.v 288s mkdir -p share/intel/cyclone10lp 288s cp "./"/techlibs/intel/cyclone10lp/cells_sim.v share/intel/cyclone10lp/cells_sim.v 288s mkdir -p share/intel/cycloneiv 288s cp "./"/techlibs/intel/cycloneiv/cells_sim.v share/intel/cycloneiv/cells_sim.v 288s mkdir -p share/intel/cycloneive 288s cp "./"/techlibs/intel/cycloneive/cells_sim.v share/intel/cycloneive/cells_sim.v 288s mkdir -p share/intel/max10 288s cp "./"/techlibs/intel/max10/cells_map.v share/intel/max10/cells_map.v 288s mkdir -p share/intel/cyclone10lp 288s cp "./"/techlibs/intel/cyclone10lp/cells_map.v share/intel/cyclone10lp/cells_map.v 288s mkdir -p share/intel/cycloneiv 288s cp "./"/techlibs/intel/cycloneiv/cells_map.v share/intel/cycloneiv/cells_map.v 288s mkdir -p share/intel/cycloneive 288s cp "./"/techlibs/intel/cycloneive/cells_map.v share/intel/cycloneive/cells_map.v 288s mkdir -p share/intel_alm/common 288s cp "./"/techlibs/intel_alm/common/abc9_map.v share/intel_alm/common/abc9_map.v 288s mkdir -p share/intel_alm/common 288s cp "./"/techlibs/intel_alm/common/abc9_unmap.v share/intel_alm/common/abc9_unmap.v 288s mkdir -p share/intel_alm/common 288s cp "./"/techlibs/intel_alm/common/abc9_model.v share/intel_alm/common/abc9_model.v 288s mkdir -p share/intel_alm/common 288s cp "./"/techlibs/intel_alm/common/alm_map.v share/intel_alm/common/alm_map.v 288s mkdir -p share/intel_alm/common 288s cp "./"/techlibs/intel_alm/common/alm_sim.v share/intel_alm/common/alm_sim.v 288s mkdir -p share/intel_alm/common 288s cp "./"/techlibs/intel_alm/common/arith_alm_map.v share/intel_alm/common/arith_alm_map.v 288s mkdir -p share/intel_alm/common 288s cp "./"/techlibs/intel_alm/common/dff_map.v share/intel_alm/common/dff_map.v 288s mkdir -p share/intel_alm/common 288s cp "./"/techlibs/intel_alm/common/dff_sim.v share/intel_alm/common/dff_sim.v 288s mkdir -p share/intel_alm/common 288s cp "./"/techlibs/intel_alm/common/dsp_sim.v share/intel_alm/common/dsp_sim.v 288s mkdir -p share/intel_alm/common 288s cp "./"/techlibs/intel_alm/common/dsp_map.v share/intel_alm/common/dsp_map.v 288s mkdir -p share/intel_alm/common 288s cp "./"/techlibs/intel_alm/common/mem_sim.v share/intel_alm/common/mem_sim.v 288s mkdir -p share/intel_alm/common 288s cp "./"/techlibs/intel_alm/common/misc_sim.v share/intel_alm/common/misc_sim.v 288s mkdir -p share/intel_alm/cyclonev 288s cp "./"/techlibs/intel_alm/cyclonev/cells_sim.v share/intel_alm/cyclonev/cells_sim.v 288s mkdir -p share/intel_alm/common 288s cp "./"/techlibs/intel_alm/common/bram_m10k.txt share/intel_alm/common/bram_m10k.txt 288s mkdir -p share/intel_alm/common 288s cp "./"/techlibs/intel_alm/common/bram_m10k_map.v share/intel_alm/common/bram_m10k_map.v 288s mkdir -p share/intel_alm/common 288s cp "./"/techlibs/intel_alm/common/bram_m20k.txt share/intel_alm/common/bram_m20k.txt 288s mkdir -p share/intel_alm/common 288s cp "./"/techlibs/intel_alm/common/bram_m20k_map.v share/intel_alm/common/bram_m20k_map.v 288s mkdir -p share/intel_alm/common 288s cp "./"/techlibs/intel_alm/common/lutram_mlab.txt share/intel_alm/common/lutram_mlab.txt 288s mkdir -p share/intel_alm/common 288s cp "./"/techlibs/intel_alm/common/megafunction_bb.v share/intel_alm/common/megafunction_bb.v 288s mkdir -p share/intel_alm/common 288s cp "./"/techlibs/intel_alm/common/quartus_rename.v share/intel_alm/common/quartus_rename.v 288s mkdir -p share/lattice 288s cp "./"/techlibs/lattice/cells_ff.vh share/lattice/cells_ff.vh 288s mkdir -p share/lattice 288s cp "./"/techlibs/lattice/cells_io.vh share/lattice/cells_io.vh 288s mkdir -p share/lattice 288s cp "./"/techlibs/lattice/cells_map.v share/lattice/cells_map.v 288s mkdir -p share/lattice 288s cp "./"/techlibs/lattice/common_sim.vh share/lattice/common_sim.vh 288s mkdir -p share/lattice 288s cp "./"/techlibs/lattice/ccu2d_sim.vh share/lattice/ccu2d_sim.vh 288s mkdir -p share/lattice 288s cp "./"/techlibs/lattice/ccu2c_sim.vh share/lattice/ccu2c_sim.vh 288s mkdir -p share/lattice 288s cp "./"/techlibs/lattice/cells_sim_ecp5.v share/lattice/cells_sim_ecp5.v 288s mkdir -p share/lattice 288s cp "./"/techlibs/lattice/cells_sim_xo2.v share/lattice/cells_sim_xo2.v 288s mkdir -p share/lattice 288s cp "./"/techlibs/lattice/cells_sim_xo3.v share/lattice/cells_sim_xo3.v 288s mkdir -p share/lattice 288s cp "./"/techlibs/lattice/cells_sim_xo3d.v share/lattice/cells_sim_xo3d.v 288s mkdir -p share/lattice 288s cp "./"/techlibs/lattice/cells_bb_ecp5.v share/lattice/cells_bb_ecp5.v 288s mkdir -p share/lattice 288s cp "./"/techlibs/lattice/cells_bb_xo2.v share/lattice/cells_bb_xo2.v 288s mkdir -p share/lattice 288s cp "./"/techlibs/lattice/cells_bb_xo3.v share/lattice/cells_bb_xo3.v 288s mkdir -p share/lattice 288s cp "./"/techlibs/lattice/cells_bb_xo3d.v share/lattice/cells_bb_xo3d.v 288s mkdir -p share/lattice 288s cp "./"/techlibs/lattice/lutrams_map.v share/lattice/lutrams_map.v 288s mkdir -p share/lattice 288s cp "./"/techlibs/lattice/lutrams.txt share/lattice/lutrams.txt 288s mkdir -p share/lattice 288s cp "./"/techlibs/lattice/brams_map_16kd.v share/lattice/brams_map_16kd.v 288s mkdir -p share/lattice 288s cp "./"/techlibs/lattice/brams_16kd.txt share/lattice/brams_16kd.txt 288s mkdir -p share/lattice 288s cp "./"/techlibs/lattice/brams_map_8kc.v share/lattice/brams_map_8kc.v 288s mkdir -p share/lattice 288s cp "./"/techlibs/lattice/brams_8kc.txt share/lattice/brams_8kc.txt 288s mkdir -p share/lattice 288s cp "./"/techlibs/lattice/arith_map_ccu2c.v share/lattice/arith_map_ccu2c.v 288s mkdir -p share/lattice 288s cp "./"/techlibs/lattice/arith_map_ccu2d.v share/lattice/arith_map_ccu2d.v 288s mkdir -p share/lattice 288s cp "./"/techlibs/lattice/latches_map.v share/lattice/latches_map.v 288s mkdir -p share/lattice 288s cp "./"/techlibs/lattice/dsp_map_18x18.v share/lattice/dsp_map_18x18.v 288s mkdir -p share/nexus 288s cp "./"/techlibs/nexus/cells_map.v share/nexus/cells_map.v 288s mkdir -p share/nexus 288s cp "./"/techlibs/nexus/cells_sim.v share/nexus/cells_sim.v 288s mkdir -p share/nexus 288s cp "./"/techlibs/nexus/parse_init.vh share/nexus/parse_init.vh 288s mkdir -p share/nexus 288s cp "./"/techlibs/nexus/cells_xtra.v share/nexus/cells_xtra.v 288s mkdir -p share/nexus 288s cp "./"/techlibs/nexus/lutrams_map.v share/nexus/lutrams_map.v 288s mkdir -p share/nexus 288s cp "./"/techlibs/nexus/lutrams.txt share/nexus/lutrams.txt 288s mkdir -p share/nexus 288s cp "./"/techlibs/nexus/brams_map.v share/nexus/brams_map.v 288s mkdir -p share/nexus 288s cp "./"/techlibs/nexus/brams.txt share/nexus/brams.txt 288s mkdir -p share/nexus 288s cp "./"/techlibs/nexus/lrams_map.v share/nexus/lrams_map.v 288s mkdir -p share/nexus 288s cp "./"/techlibs/nexus/lrams.txt share/nexus/lrams.txt 288s mkdir -p share/nexus 288s cp "./"/techlibs/nexus/arith_map.v share/nexus/arith_map.v 288s mkdir -p share/nexus 288s cp "./"/techlibs/nexus/latches_map.v share/nexus/latches_map.v 288s mkdir -p share/nexus 288s cp "./"/techlibs/nexus/dsp_map.v share/nexus/dsp_map.v 288s mkdir -p share/quicklogic 288s cp "./"/techlibs/quicklogic/pp3_ffs_map.v share/quicklogic/pp3_ffs_map.v 288s mkdir -p share/quicklogic 288s cp "./"/techlibs/quicklogic/pp3_lut_map.v share/quicklogic/pp3_lut_map.v 288s mkdir -p share/quicklogic 288s cp "./"/techlibs/quicklogic/pp3_latches_map.v share/quicklogic/pp3_latches_map.v 288s mkdir -p share/quicklogic 288s cp "./"/techlibs/quicklogic/pp3_cells_map.v share/quicklogic/pp3_cells_map.v 288s mkdir -p share/quicklogic 288s cp "./"/techlibs/quicklogic/cells_sim.v share/quicklogic/cells_sim.v 288s mkdir -p share/quicklogic 288s cp "./"/techlibs/quicklogic/lut_sim.v share/quicklogic/lut_sim.v 288s mkdir -p share/quicklogic 288s cp "./"/techlibs/quicklogic/pp3_cells_sim.v share/quicklogic/pp3_cells_sim.v 288s mkdir -p share/quicklogic 288s cp "./"/techlibs/quicklogic/abc9_model.v share/quicklogic/abc9_model.v 288s mkdir -p share/quicklogic 288s cp "./"/techlibs/quicklogic/abc9_map.v share/quicklogic/abc9_map.v 288s mkdir -p share/quicklogic 288s cp "./"/techlibs/quicklogic/abc9_unmap.v share/quicklogic/abc9_unmap.v 288s mkdir -p share/sf2 288s cp "./"/techlibs/sf2/arith_map.v share/sf2/arith_map.v 288s mkdir -p share/sf2 288s cp "./"/techlibs/sf2/cells_map.v share/sf2/cells_map.v 288s mkdir -p share/sf2 288s cp "./"/techlibs/sf2/cells_sim.v share/sf2/cells_sim.v 288s mkdir -p share/xilinx 288s cp "./"/techlibs/xilinx/cells_map.v share/xilinx/cells_map.v 288s mkdir -p share/xilinx 288s cp "./"/techlibs/xilinx/cells_sim.v share/xilinx/cells_sim.v 288s mkdir -p share/xilinx 288s cp "./"/techlibs/xilinx/cells_xtra.v share/xilinx/cells_xtra.v 288s mkdir -p share/xilinx 288s cp "./"/techlibs/xilinx/lutrams_xcv.txt share/xilinx/lutrams_xcv.txt 288s mkdir -p share/xilinx 288s cp "./"/techlibs/xilinx/lutrams_xcv_map.v share/xilinx/lutrams_xcv_map.v 288s mkdir -p share/xilinx 288s cp "./"/techlibs/xilinx/lutrams_xc5v.txt share/xilinx/lutrams_xc5v.txt 288s mkdir -p share/xilinx 288s cp "./"/techlibs/xilinx/lutrams_xcu.txt share/xilinx/lutrams_xcu.txt 288s mkdir -p share/xilinx 288s cp "./"/techlibs/xilinx/lutrams_xc5v_map.v share/xilinx/lutrams_xc5v_map.v 288s mkdir -p share/xilinx 288s cp "./"/techlibs/xilinx/brams_xcv.txt share/xilinx/brams_xcv.txt 288s mkdir -p share/xilinx 288s cp "./"/techlibs/xilinx/brams_xcv_map.v share/xilinx/brams_xcv_map.v 288s mkdir -p share/xilinx 288s cp "./"/techlibs/xilinx/brams_defs.vh share/xilinx/brams_defs.vh 288s mkdir -p share/xilinx 288s cp "./"/techlibs/xilinx/brams_xc2v.txt share/xilinx/brams_xc2v.txt 288s mkdir -p share/xilinx 288s cp "./"/techlibs/xilinx/brams_xc2v_map.v share/xilinx/brams_xc2v_map.v 288s mkdir -p share/xilinx 288s cp "./"/techlibs/xilinx/brams_xc3sda.txt share/xilinx/brams_xc3sda.txt 288s mkdir -p share/xilinx 288s cp "./"/techlibs/xilinx/brams_xc3sda_map.v share/xilinx/brams_xc3sda_map.v 288s mkdir -p share/xilinx 288s cp "./"/techlibs/xilinx/brams_xc4v.txt share/xilinx/brams_xc4v.txt 288s mkdir -p share/xilinx 288s cp "./"/techlibs/xilinx/brams_xc4v_map.v share/xilinx/brams_xc4v_map.v 288s mkdir -p share/xilinx 288s cp "./"/techlibs/xilinx/brams_xc5v_map.v share/xilinx/brams_xc5v_map.v 288s mkdir -p share/xilinx 288s cp "./"/techlibs/xilinx/brams_xc6v_map.v share/xilinx/brams_xc6v_map.v 288s mkdir -p share/xilinx 288s cp "./"/techlibs/xilinx/brams_xcu_map.v share/xilinx/brams_xcu_map.v 288s mkdir -p share/xilinx 288s cp "./"/techlibs/xilinx/urams.txt share/xilinx/urams.txt 288s mkdir -p share/xilinx 288s cp "./"/techlibs/xilinx/urams_map.v share/xilinx/urams_map.v 288s mkdir -p share/xilinx 288s cp "./"/techlibs/xilinx/arith_map.v share/xilinx/arith_map.v 288s mkdir -p share/xilinx 288s cp "./"/techlibs/xilinx/ff_map.v share/xilinx/ff_map.v 288s mkdir -p share/xilinx 288s cp "./"/techlibs/xilinx/lut_map.v share/xilinx/lut_map.v 288s mkdir -p share/xilinx 288s cp "./"/techlibs/xilinx/mux_map.v share/xilinx/mux_map.v 288s mkdir -p share/xilinx 288s cp "./"/techlibs/xilinx/xc3s_mult_map.v share/xilinx/xc3s_mult_map.v 288s mkdir -p share/xilinx 288s cp "./"/techlibs/xilinx/xc3sda_dsp_map.v share/xilinx/xc3sda_dsp_map.v 288s mkdir -p share/xilinx 288s cp "./"/techlibs/xilinx/xc6s_dsp_map.v share/xilinx/xc6s_dsp_map.v 288s mkdir -p share/xilinx 288s cp "./"/techlibs/xilinx/xc4v_dsp_map.v share/xilinx/xc4v_dsp_map.v 288s mkdir -p share/xilinx 288s cp "./"/techlibs/xilinx/xc5v_dsp_map.v share/xilinx/xc5v_dsp_map.v 288s mkdir -p share/xilinx 288s cp "./"/techlibs/xilinx/xc7_dsp_map.v share/xilinx/xc7_dsp_map.v 288s mkdir -p share/xilinx 288s cp "./"/techlibs/xilinx/xcu_dsp_map.v share/xilinx/xcu_dsp_map.v 288s mkdir -p share/xilinx 288s cp "./"/techlibs/xilinx/abc9_model.v share/xilinx/abc9_model.v 288s cd tests/simple && bash run-test.sh "" 288s make[1]: Entering directory '/tmp/autopkgtest.5LcWtj/build.uCa/src/tests/simple' 288s + gcc -Wall -o /tmp/autopkgtest.5LcWtj/build.uCa/src/tests/tools/cmp_tbdata /tmp/autopkgtest.5LcWtj/build.uCa/src/tests/tools/cmp_tbdata.c 289s Test: arrays02 -> ok 291s Test: asgn_binop -> ok 291s Test: case_expr_extend -> ok 292s Test: case_expr_query -> ok 292s Test: defvalue -> ok 293s Test: implicit_ports -> ok 293s Test: lesser_size_cast -> ok 293s Test: local_loop_var -> ok 294s Test: macro_arg_spaces -> ok 294s Test: matching_end_labels -> ok 294s Test: memwr_port_connection -> ok 294s Test: unnamed_block_decl -> ok 295s Test: aes_kexp128 -> ok 295s Test: always01 -> ok 295s Test: always02 -> ok 296s Test: always03 -> ok 296s Test: arraycells -> ok 297s Test: arrays01 -> ok 297s Test: attrib01_module -> ok 298s Test: attrib02_port_decl -> ok 298s Test: attrib03_parameter -> ok 298s Test: attrib04_net_var -> ok 299s Test: attrib06_operator_suffix -> ok 299s Test: attrib08_mod_inst -> ok 301s Test: attrib09_case -> ok 301s Test: carryadd -> ok 301s Test: case_expr_const -> ok 301s Test: case_expr_non_const -> ok 309s Test: case_large -> ok 309s Test: const_branch_finish -> ok 310s Test: const_fold_func -> ok 310s Test: const_func_shadow -> ok 313s Test: constmuldivmod -> ok 313s Test: constpower -> ok 314s Test: dff_different_styles -> ok 315s Test: dff_init -> ok 317s Test: dynslice -> ok 318s Test: fiedler-cooley -> ok 318s Test: forgen01 -> ok 318s Test: forgen02 -> ok 319s Test: forloops -> ok 319s Test: fsm -> ok 320s Test: func_block -> ok 320s Test: func_recurse -> ok 321s Test: func_width_scope -> ok 322s Test: genblk_collide -> ok 322s Test: genblk_dive -> ok 322s Test: genblk_order -> ok 322s Test: genblk_port_shadow -> ok 325s Test: generate -> ok 325s Test: graphtest -> ok 325s Test: hierarchy -> ok 326s Test: hierdefparam -> ok 327s Test: i2c_master_tests -> ok 327s Test: ifdef_1 -> ok 327s Test: ifdef_2 -> ok 327s Test: localparam_attr -> ok 327s Test: loop_prefix_case -> ok 328s Test: loop_var_shadow -> ok 328s Test: loops -> ok 328s Test: macro_arg_surrounding_spaces -> ok 329s Test: macros -> ok 331s Test: mem2reg -> ok 331s Test: mem2reg_bounds_tern -> ok 334s Test: mem_arst -> ok 340s Test: memory -> ok 341s Test: module_scope -> ok 341s Test: module_scope_case -> ok 341s Test: module_scope_func -> ok 342s Test: multiplier -> ok 343s Test: muxtree -> ok 343s Test: named_genblk -> ok 343s Test: nested_genblk_resolve -> ok 344s Test: omsp_dbg_uart -> ok 349s Test: operators -> ok 349s Test: param_attr -> ok 350s Test: paramods -> ok 355s Test: partsel -> ok 356s Test: process -> ok 356s Test: realexpr -> ok 357s Test: repwhile -> ok 357s Test: retime -> ok 362s Test: rotate -> ok 363s Test: scopes -> ok 364s Test: signed_full_slice -> ok 364s Test: signedexpr -> ok 365s Test: sincos -> ok 366s Test: specify -> ok 366s Test: string_format -> ok 367s Test: subbytes -> ok 368s Test: task_func -> ok 368s Test: undef_eqx_nex -> ok 368s Test: usb_phy_tests -> ok 369s Test: values -> ok 369s Test: verilog_primitives -> ok 371s Test: vloghammer -> ok 371s Test: wandwor -> ok 373s Test: wreduce -> ok 373s make[1]: Leaving directory '/tmp/autopkgtest.5LcWtj/build.uCa/src/tests/simple' 373s cd tests/simple_abc9 && bash run-test.sh "" 373s ls: cannot access '*.sv': No such file or directory 373s make[1]: Entering directory '/tmp/autopkgtest.5LcWtj/build.uCa/src/tests/simple_abc9' 376s Test: abc9 -> ok 376s Test: aes_kexp128 -> ok 376s Test: always01 -> ok 377s Test: always02 -> ok 377s Test: always03 -> ok 377s Test: arraycells -> ok 377s Test: arrays01 -> ok 378s Test: attrib01_module -> ok 378s Test: attrib02_port_decl -> ok 378s Test: attrib03_parameter -> ok 379s Test: attrib04_net_var -> ok 379s Test: attrib06_operator_suffix -> ok 379s Test: attrib08_mod_inst -> ok 380s Test: attrib09_case -> ok 380s Test: carryadd -> ok 380s Test: case_expr_const -> ok 380s Test: case_expr_non_const -> ok 396s Test: case_large -> ok 396s Test: const_branch_finish -> ok 396s Test: const_fold_func -> ok 397s Test: const_func_shadow -> ok 400s Test: constmuldivmod -> ok 400s Test: constpower -> ok 401s Test: dff_different_styles -> ok 401s Test: dff_init -> ok 411s Test: dynslice -> ok 411s Test: fiedler-cooley -> ok 412s Test: forgen01 -> ok 412s Test: forgen02 -> ok 412s Test: forloops -> ok 413s Test: fsm -> ok 413s Test: func_block -> ok 413s Test: func_recurse -> ok 413s Test: func_width_scope -> ok 414s Test: genblk_collide -> ok 414s Test: genblk_dive -> ok 414s Test: genblk_order -> ok 414s Test: genblk_port_shadow -> ok 417s Test: generate -> ok 417s Test: graphtest -> ok 417s Test: hierarchy -> ok 418s Test: hierdefparam -> ok 418s Test: i2c_master_tests -> ok 418s Test: ifdef_1 -> ok 419s Test: ifdef_2 -> ok 419s Test: localparam_attr -> ok 419s Test: loop_prefix_case -> ok 419s Test: loop_var_shadow -> ok 420s Test: loops -> ok 420s Test: macro_arg_surrounding_spaces -> ok 420s Test: macros -> ok 421s Test: mem2reg -> ok 422s Test: mem2reg_bounds_tern -> ok 422s Test: mem_arst -> ok 426s Test: memory -> ok 427s Test: module_scope -> ok 427s Test: module_scope_case -> ok 427s Test: module_scope_func -> ok 428s Test: multiplier -> ok 429s Test: muxtree -> ok 429s Test: named_genblk -> ok 429s Test: nested_genblk_resolve -> ok 429s Test: omsp_dbg_uart -> ok 437s Test: operators -> ok 437s Test: param_attr -> ok 438s Test: paramods -> ok 444s Test: partsel -> ok 444s Test: process -> ok 445s Test: realexpr -> ok 445s Test: repwhile -> ok 445s Test: retime -> ok 447s Test: rotate -> ok 448s Test: scopes -> ok 448s Test: signed_full_slice -> ok 448s Test: signedexpr -> ok 451s Test: sincos -> ok 451s Test: string_format -> ok 452s Test: subbytes -> ok 453s Test: task_func -> ok 453s Test: undef_eqx_nex -> ok 453s Test: usb_phy_tests -> ok 453s Test: values -> ok 454s Test: verilog_primitives -> ok 454s Test: vloghammer -> ok 455s Test: wandwor -> ok 457s Test: wreduce -> ok 457s Test: arrays02 -> ok 459s Test: asgn_binop -> ok 459s Test: case_expr_extend -> ok 459s Test: case_expr_query -> ok 459s Test: defvalue -> ok 460s Test: implicit_ports -> ok 460s Test: lesser_size_cast -> ok 460s Test: local_loop_var -> ok 461s Test: macro_arg_spaces -> ok 461s Test: matching_end_labels -> ok 462s Test: memwr_port_connection -> ok 462s Test: unnamed_block_decl -> ok 462s make[1]: Leaving directory '/tmp/autopkgtest.5LcWtj/build.uCa/src/tests/simple_abc9' 462s cd tests/hana && bash run-test.sh "" 462s make[1]: Entering directory '/tmp/autopkgtest.5LcWtj/build.uCa/src/tests/hana' 466s Test: test_intermout -> ok 466s Test: test_parse2synthtrans -> ok 467s Test: test_parser -> ok 468s Test: test_simulation_always -> ok 469s Test: test_simulation_and -> ok 469s Test: test_simulation_buffer -> ok 470s Test: test_simulation_decoder -> ok 471s Test: test_simulation_inc -> ok 473s Test: test_simulation_mux -> ok 473s Test: test_simulation_nand -> ok 474s Test: test_simulation_nor -> ok 474s Test: test_simulation_or -> ok 475s Test: test_simulation_seq -> ok 477s Test: test_simulation_shifter -> ok 478s Test: test_simulation_sop -> ok 479s Test: test_simulation_techmap -> ok 482s Test: test_simulation_techmap_tech -> ok 482s Test: test_simulation_vlib -> ok 483s Test: test_simulation_xnor -> ok 483s Test: test_simulation_xor -> ok 483s make[1]: Leaving directory '/tmp/autopkgtest.5LcWtj/build.uCa/src/tests/hana' 483s cd tests/asicworld && bash run-test.sh "" 483s make[1]: Entering directory '/tmp/autopkgtest.5LcWtj/build.uCa/src/tests/asicworld' 484s Test: code_hdl_models_GrayCounter -> ok 484s Test: code_hdl_models_arbiter -> ok 492s Test: code_hdl_models_cam -> ok 493s Test: code_hdl_models_clk_div -> ok 493s Test: code_hdl_models_clk_div_45 -> ok 493s Test: code_hdl_models_d_ff_gates -> ok 494s Test: code_hdl_models_d_latch_gates -> ok 494s Test: code_hdl_models_decoder_2to4_gates -> ok 494s Test: code_hdl_models_decoder_using_assign -> ok 495s Test: code_hdl_models_decoder_using_case -> ok 495s Test: code_hdl_models_dff_async_reset -> ok 495s Test: code_hdl_models_dff_sync_reset -> ok 495s Test: code_hdl_models_encoder_4to2_gates -> ok 496s Test: code_hdl_models_encoder_using_case -> ok 496s Test: code_hdl_models_encoder_using_if -> ok 497s Test: code_hdl_models_full_adder_gates -> ok 497s Test: code_hdl_models_full_subtracter_gates -> ok 497s Test: code_hdl_models_gray_counter -> ok 497s Test: code_hdl_models_half_adder_gates -> ok 498s Test: code_hdl_models_lfsr -> ok 498s Test: code_hdl_models_lfsr_updown -> ok 498s Test: code_hdl_models_mux_2to1_gates -> ok 499s Test: code_hdl_models_mux_using_assign -> ok 499s Test: code_hdl_models_mux_using_case -> ok 499s Test: code_hdl_models_mux_using_if -> ok 499s Test: code_hdl_models_one_hot_cnt -> ok 500s Test: code_hdl_models_parallel_crc -> ok 500s Test: code_hdl_models_parity_using_assign -> ok 500s Test: code_hdl_models_parity_using_bitwise -> ok 501s Test: code_hdl_models_parity_using_function -> ok 501s Test: code_hdl_models_pri_encoder_using_assign -> ok 501s Test: code_hdl_models_rom_using_case -> ok 502s Test: code_hdl_models_serial_crc -> ok 502s Test: code_hdl_models_tff_async_reset -> ok 502s Test: code_hdl_models_tff_sync_reset -> ok 504s Test: code_hdl_models_uart -> ok 504s Test: code_hdl_models_up_counter -> ok 505s Test: code_hdl_models_up_counter_load -> ok 505s Test: code_hdl_models_up_down_counter -> ok 506s Test: code_specman_switch_fabric -> ok 506s Test: code_tidbits_asyn_reset -> ok 506s Test: code_tidbits_blocking -> ok 507s Test: code_tidbits_fsm_using_always -> ok 507s Test: code_tidbits_fsm_using_function -> ok 507s Test: code_tidbits_fsm_using_single_always -> ok 508s Test: code_tidbits_nonblocking -> ok 508s Test: code_tidbits_reg_combo_example -> ok 508s Test: code_tidbits_reg_seq_example -> ok 508s Test: code_tidbits_syn_reset -> ok 509s Test: code_tidbits_wire_example -> ok 509s Test: code_verilog_tutorial_addbit -> ok 509s Test: code_verilog_tutorial_always_example -> ok 509s Test: code_verilog_tutorial_bus_con -> ok 510s Test: code_verilog_tutorial_comment -> ok 510s Test: code_verilog_tutorial_counter -> ok 510s Test: code_verilog_tutorial_d_ff -> ok 510s Test: code_verilog_tutorial_decoder -> ok 511s Test: code_verilog_tutorial_decoder_always -> ok 511s Test: code_verilog_tutorial_escape_id -> ok 511s Test: code_verilog_tutorial_explicit -> ok 512s Test: code_verilog_tutorial_first_counter -> ok 512s Test: code_verilog_tutorial_flip_flop -> ok 513s Test: code_verilog_tutorial_fsm_full -> ok 513s Test: code_verilog_tutorial_good_code -> ok 513s Test: code_verilog_tutorial_if_else -> ok 513s Test: code_verilog_tutorial_multiply -> ok 513s Test: code_verilog_tutorial_mux_21 -> ok 514s Test: code_verilog_tutorial_n_out_primitive -> ok 514s Test: code_verilog_tutorial_parallel_if -> ok 514s Test: code_verilog_tutorial_parity -> ok 514s Test: code_verilog_tutorial_simple_function -> ok 514s Test: code_verilog_tutorial_simple_if -> ok 515s Test: code_verilog_tutorial_task_global -> ok 515s Test: code_verilog_tutorial_tri_buf -> ok 515s Test: code_verilog_tutorial_v2k_reg -> ok 515s Test: code_verilog_tutorial_which_clock -> ok 515s make[1]: Leaving directory '/tmp/autopkgtest.5LcWtj/build.uCa/src/tests/asicworld' 515s # +cd tests/realmath && bash run-test.sh "" 515s cd tests/share && bash run-test.sh "" 515s generating tests.. 515s running tests.. 518s [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41][42][43][44][45][46][47][48][49][50][51][52][53][54][55][56][57][58][59][60][61][62][63][64][65][66][67][68][69][70][71][72][73][74][75][76][77][78][79][80][81][82][83][84][85][86][87][88][89][90][91][92][93][94][95][96][97][98][99] 518s cd tests/opt_share && bash run-test.sh "" 518s generating tests.. 518s running tests.. 518s make[1]: Entering directory '/tmp/autopkgtest.5LcWtj/build.uCa/src/tests/opt_share' 532s [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41][42][43][44][45][46][47][48][49][50][51][52][53][54][55][56][57][58][59][60][61][62][63][64][65][66][67][68][69][70][71][72][73][74][75][76][77][78][79][80][81][82][83][84][85][86][87][88][89][90][91][92][93][94][95][96][97][98][99]make[1]: Leaving directory '/tmp/autopkgtest.5LcWtj/build.uCa/src/tests/opt_share' 532s 532s cd tests/fsm && bash run-test.sh "" 532s generating tests.. 532s PRNG seed: 7090595494936147030 532s running tests.. 532s make[1]: Entering directory '/tmp/autopkgtest.5LcWtj/build.uCa/src/tests/fsm' 532s [0]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 532s Users of state reg look like FSM recoding might result in larger circuit. 532s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 536s K[1]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 536s Users of state reg look like FSM recoding might result in larger circuit. 536s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 538s K[2]K[3]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 538s Users of state reg look like FSM recoding might result in larger circuit. 538s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 539s K[4]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 539s Users of state reg look like FSM recoding might result in larger circuit. 539s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 540s K[5]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 540s Users of state reg look like FSM recoding might result in larger circuit. 540s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 565s T[6]K[7]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 565s Users of state reg look like FSM recoding might result in larger circuit. 565s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 565s K[8]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 565s Users of state reg look like FSM recoding might result in larger circuit. 565s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 568s K[9]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 568s Users of state reg look like FSM recoding might result in larger circuit. 568s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 570s K[10]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 570s Users of state reg look like FSM recoding might result in larger circuit. 570s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 595s T[11]K[12]K[13]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 595s Users of state reg look like FSM recoding might result in larger circuit. 595s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 598s K[14]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 598s Users of state reg look like FSM recoding might result in larger circuit. 598s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 600s K[15]K[16]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 600s Users of state reg look like FSM recoding might result in larger circuit. 600s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 601s K[17]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 601s Users of state reg look like FSM recoding might result in larger circuit. 601s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 603s K[18]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 603s Users of state reg look like FSM recoding might result in larger circuit. 603s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 604s K[19]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 604s Users of state reg look like FSM recoding might result in larger circuit. 604s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 604s K[20]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 604s Users of state reg look like FSM recoding might result in larger circuit. 604s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 611s K[21]K[22]K[23]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 611s Users of state reg look like FSM recoding might result in larger circuit. 611s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 612s K[24]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 612s Users of state reg look like FSM recoding might result in larger circuit. 612s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 616s K[25]K[26]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 616s Users of state reg look like FSM recoding might result in larger circuit. 616s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 619s K[27]K[28]K[29]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 619s Users of state reg look like FSM recoding might result in larger circuit. 619s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 631s K[30]K[31]K[32]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 631s Users of state reg look like FSM recoding might result in larger circuit. 631s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 639s K[33]K[34]K[35]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 639s Users of state reg look like FSM recoding might result in larger circuit. 639s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 643s K[36]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 643s Users of state reg look like FSM recoding might result in larger circuit. 643s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 649s K[37]K[38]K[39]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 649s Users of state reg look like FSM recoding might result in larger circuit. 649s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 651s K[40]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 651s Users of state reg look like FSM recoding might result in larger circuit. 651s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 654s K[41]K[42]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 654s Users of state reg look like FSM recoding might result in larger circuit. 654s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 656s K[43]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 656s Users of state reg look like FSM recoding might result in larger circuit. 656s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 658s K[44]K[45]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 658s Users of state reg look like FSM recoding might result in larger circuit. 658s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 660s K[46]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 660s Users of state reg look like FSM recoding might result in larger circuit. 660s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 662s K[47]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 662s Users of state reg look like FSM recoding might result in larger circuit. 662s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 664s K[48]K[49]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 664s Users of state reg look like FSM recoding might result in larger circuit. 664s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 665s K 665s make[1]: Leaving directory '/tmp/autopkgtest.5LcWtj/build.uCa/src/tests/fsm' 665s cd tests/techmap && bash run-test.sh 665s make[1]: Entering directory '/tmp/autopkgtest.5LcWtj/build.uCa/src/tests/techmap' 666s Passed abc9.ys 666s Warning: wire '\Q' is assigned in a block at < ok 678s Test: firrtl_938 -> ok 679s Test: implicit_en -> ok 681s Test: issue00335 -> ok 682s Test: issue00710 -> ok 683s Test: no_implicit_en -> ok 684s Test: read_arst -> ok 685s Test: read_two_mux -> ok 686s Test: shared_ports -> ok 686s Test: simple_sram_byte_en -> ok 688s Test: trans_addr_enable -> ok 689s Test: trans_sdp -> ok 690s Test: trans_sp -> ok 691s Test: wide_all -> ok 692s Test: wide_read_async -> ok 693s Test: wide_read_mixed -> ok 694s Test: wide_read_sync -> ok 695s Test: wide_read_trans -> ok 696s Test: wide_thru_priority -> ok 697s Test: wide_write -> ok 697s make[1]: Leaving directory '/tmp/autopkgtest.5LcWtj/build.uCa/src/tests/memories' 697s Testing expectations for amber23_sram_byte_en.v .. ok. 697s Testing expectations for implicit_en.v .. ok. 697s Testing expectations for issue00335.v .. ok. 697s Testing expectations for issue00710.v .. ok. 697s Testing expectations for no_implicit_en.v .. ok. 697s Testing expectations for read_arst.v .. ok. 697s Testing expectations for read_two_mux.v .. ok. 697s Testing expectations for shared_ports.v .. ok. 698s Testing expectations for simple_sram_byte_en.v .. ok. 698s Testing expectations for trans_addr_enable.v .. ok. 698s Testing expectations for trans_sdp.v .. ok. 698s Testing expectations for trans_sp.v .. ok. 698s Testing expectations for wide_all.v .. ok. 698s Testing expectations for wide_read_async.v .. ok. 698s Testing expectations for wide_read_mixed.v .. ok. 698s Testing expectations for wide_read_sync.v .. ok. 698s Testing expectations for wide_read_trans.v .. ok. 698s Testing expectations for wide_thru_priority.v .. ok. 698s Testing expectations for wide_write.v .. ok. 698s cd tests/memlib && bash run-test.sh "" 698s make[1]: Entering directory '/tmp/autopkgtest.5LcWtj/build.uCa/src/tests/memlib' 700s Test: t_async_big -> ok 703s Test: t_async_big_block -> ok 703s Test: t_async_small -> ok 703s Test: t_async_small_block -> ok 703s Test: t_sync_big -> ok 704s Test: t_sync_big_sdp -> ok 705s Test: t_sync_big_lut -> ok 705s Test: t_sync_small -> ok 705s Test: t_sync_small_block -> ok 706s Test: t_sync_small_block_attr -> ok 706s Test: t_init_lut_zeros_zero -> ok 706s Test: t_init_lut_zeros_any -> ok 706s Test: t_init_lut_val_zero -> ok 706s Test: t_init_lut_val_any -> ok 706s Test: t_init_lut_val_no_undef -> ok 707s Test: t_init_lut_val2_any -> ok 707s Test: t_init_lut_val2_no_undef -> ok 707s Test: t_init_lut_x_none -> ok 707s Test: t_init_lut_x_zero -> ok 707s Test: t_init_lut_x_any -> ok 708s Test: t_init_lut_x_no_undef -> ok 708s Test: t_ram_18b2B -> ok 708s Test: t_ram_9b1B -> ok 708s Test: t_ram_4b1B -> ok 708s Test: t_ram_2b1B -> ok 708s Test: t_ram_1b1B -> ok 709s Test: t_init_9b1B_zeros_zero -> ok 709s Test: t_init_9b1B_zeros_any -> ok 709s Test: t_init_9b1B_val_zero -> ok 709s Test: t_init_9b1B_val_any -> ok 709s Test: t_init_9b1B_val_no_undef -> ok 709s Test: t_init_13b2B_val_any -> ok 710s Test: t_init_18b2B_val_any -> ok 710s Test: t_init_18b2B_val_no_undef -> ok 710s Test: t_init_4b1B_x_none -> ok 710s Test: t_init_4b1B_x_zero -> ok 710s Test: t_init_4b1B_x_any -> ok 711s Test: t_init_4b1B_x_no_undef -> ok 711s Test: t_clock_a4_wANYrANYsFalse -> ok 711s Test: t_clock_a4_wANYrNEGsFalse -> ok 711s Test: t_clock_a4_wANYrPOSsFalse -> ok 711s Test: t_clock_a4_wNEGrANYsFalse -> ok 711s Test: t_clock_a4_wNEGrPOSsFalse -> ok 711s Test: t_clock_a4_wNEGrNEGsFalse -> ok 712s Test: t_clock_a4_wPOSrANYsFalse -> ok 712s Test: t_clock_a4_wPOSrNEGsFalse -> ok 712s Test: t_clock_a4_wPOSrPOSsFalse -> ok 712s Test: t_clock_a4_wANYrANYsTrue -> ok 712s Test: t_clock_a4_wNEGrPOSsTrue -> ok 712s Test: t_clock_a4_wNEGrNEGsTrue -> ok 713s Test: t_clock_a4_wPOSrNEGsTrue -> ok 713s Test: t_clock_a4_wPOSrPOSsTrue -> ok 713s Test: t_unmixed -> ok 713s Test: t_mixed_9_18 -> ok 713s Test: t_mixed_18_9 -> ok 714s Test: t_mixed_36_9 -> ok 714s Test: t_mixed_4_2 -> ok 714s Test: t_tdp -> ok 714s Test: t_sync_2clk -> ok 714s Test: t_sync_shared -> ok 714s Test: t_sync_2clk_shared -> ok 715s Test: t_sync_trans_old_old -> ok 715s Test: t_sync_trans_old_new -> ok 715s Test: t_sync_trans_old_none -> ok 715s Test: t_sync_trans_new_old -> ok 715s Test: t_sync_trans_new_new -> ok 715s Test: t_sync_trans_new_none -> ok 716s Test: t_sp_nc_none -> ok 716s Test: t_sp_new_none -> ok 716s Test: t_sp_old_none -> ok 716s Test: t_sp_nc_nc -> ok 716s Test: t_sp_new_nc -> ok 716s Test: t_sp_old_nc -> ok 717s Test: t_sp_nc_new -> ok 717s Test: t_sp_new_new -> ok 717s Test: t_sp_old_new -> ok 717s Test: t_sp_nc_old -> ok 717s Test: t_sp_new_old -> ok 717s Test: t_sp_old_old -> ok 718s Test: t_sp_nc_new_only -> ok 718s Test: t_sp_new_new_only -> ok 718s Test: t_sp_old_new_only -> ok 718s Test: t_sp_nc_new_only_be -> ok 718s Test: t_sp_new_new_only_be -> ok 718s Test: t_sp_old_new_only_be -> ok 719s Test: t_sp_nc_new_be -> ok 719s Test: t_sp_new_new_be -> ok 719s Test: t_sp_old_new_be -> ok 719s Test: t_sp_nc_old_be -> ok 719s Test: t_sp_new_old_be -> ok 719s Test: t_sp_old_old_be -> ok 720s Test: t_sp_nc_nc_be -> ok 720s Test: t_sp_new_nc_be -> ok 720s Test: t_sp_old_nc_be -> ok 720s Test: t_sp_nc_auto -> ok 721s Test: t_sp_new_auto -> ok 721s Test: t_sp_old_auto -> ok 721s Test: t_sp_nc_auto_be -> ok 721s Test: t_sp_new_auto_be -> ok 721s Test: t_sp_old_auto_be -> ok 721s Test: t_sp_init_x_x -> ok 721s Test: t_sp_init_x_x_re -> ok 721s Test: t_sp_init_x_x_ce -> ok 721s Test: t_sp_init_0_x -> ok 722s Test: t_sp_init_0_x_re -> ok 722s Test: t_sp_init_0_0 -> ok 722s Test: t_sp_init_0_0_re -> ok 722s Test: t_sp_init_0_any -> ok 722s Test: t_sp_init_0_any_re -> ok 722s Test: t_sp_init_v_x -> ok 723s Test: t_sp_init_v_x_re -> ok 723s Test: t_sp_init_v_0 -> ok 723s Test: t_sp_init_v_0_re -> ok 723s Test: t_sp_init_v_any -> ok 723s Test: t_sp_init_v_any_re -> ok 723s Test: t_sp_arst_x_x -> ok 724s Test: t_sp_arst_x_x_re -> ok 724s Test: t_sp_arst_0_x -> ok 724s Test: t_sp_arst_0_x_re -> ok 724s Test: t_sp_arst_0_0 -> ok 724s Test: t_sp_arst_0_0_re -> ok 724s Test: t_sp_arst_0_any -> ok 724s Test: t_sp_arst_0_any_re -> ok 725s Test: t_sp_arst_0_init -> ok 725s Test: t_sp_arst_0_init_re -> ok 725s Test: t_sp_arst_v_x -> ok 725s Test: t_sp_arst_v_x_re -> ok 725s Test: t_sp_arst_v_0 -> ok 725s Test: t_sp_arst_v_0_re -> ok 726s Test: t_sp_arst_v_any -> ok 726s Test: t_sp_arst_v_any_re -> ok 726s Test: t_sp_arst_v_init -> ok 726s Test: t_sp_arst_v_init_re -> ok 726s Test: t_sp_arst_e_x -> ok 726s Test: t_sp_arst_e_x_re -> ok 727s Test: t_sp_arst_e_0 -> ok 727s Test: t_sp_arst_e_0_re -> ok 727s Test: t_sp_arst_e_any -> ok 727s Test: t_sp_arst_e_any_re -> ok 727s Test: t_sp_arst_e_init -> ok 727s Test: t_sp_arst_e_init_re -> ok 728s Test: t_sp_arst_n_x -> ok 728s Test: t_sp_arst_n_x_re -> ok 728s Test: t_sp_arst_n_0 -> ok 728s Test: t_sp_arst_n_0_re -> ok 728s Test: t_sp_arst_n_any -> ok 728s Test: t_sp_arst_n_any_re -> ok 729s Test: t_sp_arst_n_init -> ok 729s Test: t_sp_arst_n_init_re -> ok 729s Test: t_sp_srst_x_x -> ok 729s Test: t_sp_srst_x_x_re -> ok 729s Test: t_sp_srst_0_x -> ok 729s Test: t_sp_srst_0_x_re -> ok 730s Test: t_sp_srst_0_0 -> ok 730s Test: t_sp_srst_0_0_re -> ok 730s Test: t_sp_srst_0_any -> ok 730s Test: t_sp_srst_0_any_re -> ok 730s Test: t_sp_srst_0_init -> ok 731s Test: t_sp_srst_0_init_re -> ok 731s Test: t_sp_srst_v_x -> ok 731s Test: t_sp_srst_v_x_re -> ok 731s Test: t_sp_srst_v_0 -> ok 731s Test: t_sp_srst_v_0_re -> ok 731s Test: t_sp_srst_v_any -> ok 732s Test: t_sp_srst_v_any_re -> ok 732s Test: t_sp_srst_v_any_re_gated -> ok 732s Test: t_sp_srst_v_any_ce -> ok 732s Test: t_sp_srst_v_any_ce_gated -> ok 732s Test: t_sp_srst_v_init -> ok 732s Test: t_sp_srst_v_init_re -> ok 733s Test: t_sp_srst_e_x -> ok 733s Test: t_sp_srst_e_x_re -> ok 733s Test: t_sp_srst_e_0 -> ok 733s Test: t_sp_srst_e_0_re -> ok 733s Test: t_sp_srst_e_any -> ok 733s Test: t_sp_srst_e_any_re -> ok 734s Test: t_sp_srst_e_init -> ok 734s Test: t_sp_srst_e_init_re -> ok 734s Test: t_sp_srst_n_x -> ok 734s Test: t_sp_srst_n_x_re -> ok 734s Test: t_sp_srst_n_0 -> ok 734s Test: t_sp_srst_n_0_re -> ok 735s Test: t_sp_srst_n_any -> ok 735s Test: t_sp_srst_n_any_re -> ok 735s Test: t_sp_srst_n_init -> ok 735s Test: t_sp_srst_n_init_re -> ok 735s Test: t_sp_srst_gv_x -> ok 735s Test: t_sp_srst_gv_x_re -> ok 736s Test: t_sp_srst_gv_0 -> ok 736s Test: t_sp_srst_gv_0_re -> ok 736s Test: t_sp_srst_gv_any -> ok 736s Test: t_sp_srst_gv_any_re -> ok 736s Test: t_sp_srst_gv_any_re_gated -> ok 736s Test: t_sp_srst_gv_any_ce -> ok 737s Test: t_sp_srst_gv_any_ce_gated -> ok 737s Test: t_sp_srst_gv_init -> ok 737s Test: t_sp_srst_gv_init_re -> ok 737s Test: t_wren_a4d4_NO_BYTE -> ok 737s Test: t_wren_a5d4_NO_BYTE -> ok 737s Test: t_wren_a6d4_NO_BYTE -> ok 738s Test: t_wren_a3d8_NO_BYTE -> ok 738s Test: t_wren_a4d8_NO_BYTE -> ok 738s Test: t_wren_a4d4_W4_B4 -> ok 738s Test: t_wren_a4d8_W4_B4_separate -> ok 738s Test: t_wren_a4d8_W8_B4 -> ok 738s Test: t_wren_a4d8_W8_B4_separate -> ok 739s Test: t_wren_a4d8_W8_B8 -> ok 739s Test: t_wren_a4d8_W8_B8_separate -> ok 739s Test: t_wren_a4d2w8_W16_B4 -> ok 739s Test: t_wren_a4d2w8_W16_B4_separate -> ok 739s Test: t_wren_a4d4w4_W16_B4 -> ok 740s Test: t_wren_a4d4w4_W16_B4_separate -> ok 740s Test: t_wren_a5d4w2_W16_B4 -> ok 740s Test: t_wren_a5d4w2_W16_B4_separate -> ok 740s Test: t_wren_a5d4w4_W16_B4 -> ok 740s Test: t_wren_a5d4w4_W16_B4_separate -> ok 740s Test: t_wren_a4d8w2_W16_B4 -> ok 741s Test: t_wren_a4d8w2_W16_B4_separate -> ok 741s Test: t_wren_a5d8w1_W16_B4 -> ok 741s Test: t_wren_a5d8w1_W16_B4_separate -> ok 741s Test: t_wren_a5d8w2_W16_B4 -> ok 741s Test: t_wren_a5d8w2_W16_B4_separate -> ok 742s Test: t_wren_a4d16w1_W16_B4 -> ok 742s Test: t_wren_a4d16w1_W16_B4_separate -> ok 742s Test: t_wren_a4d4w2_W8_B8 -> ok 742s Test: t_wren_a4d4w2_W8_B8_separate -> ok 742s Test: t_wren_a4d4w1_W8_B8 -> ok 742s Test: t_wren_a4d4w1_W8_B8_separate -> ok 743s Test: t_wren_a4d8w2_W8_B8 -> ok 743s Test: t_wren_a4d8w2_W8_B8_separate -> ok 743s Test: t_wren_a3d8w2_W8_B8 -> ok 743s Test: t_wren_a3d8w2_W8_B8_separate -> ok 743s Test: t_wren_a4d4w2_W8_B4 -> ok 743s Test: t_wren_a4d4w2_W8_B4_separate -> ok 744s Test: t_wren_a4d2w4_W8_B4 -> ok 744s Test: t_wren_a4d2w4_W8_B4_separate -> ok 744s Test: t_wren_a4d4w4_W8_B4 -> ok 744s Test: t_wren_a4d4w4_W8_B4_separate -> ok 744s Test: t_wren_a4d4w4_W4_B4 -> ok 745s Test: t_wren_a4d4w4_W4_B4_separate -> ok 745s Test: t_wren_a4d4w5_W4_B4 -> ok 745s Test: t_wren_a4d4w5_W4_B4_separate -> ok 745s Test: t_geom_a4d64_wren -> ok 745s Test: t_geom_a5d32_wren -> ok 745s Test: t_geom_a5d64_wren -> ok 746s Test: t_geom_a6d16_wren -> ok 746s Test: t_geom_a6d30_wren -> ok 746s Test: t_geom_a6d64_wren -> ok 746s Test: t_geom_a7d4_wren -> ok 746s Test: t_geom_a7d6_wren -> ok 746s Test: t_geom_a7d8_wren -> ok 747s Test: t_geom_a7d17_wren -> ok 747s Test: t_geom_a8d4_wren -> ok 747s Test: t_geom_a8d6_wren -> ok 747s Test: t_geom_a9d4_wren -> ok 747s Test: t_geom_a9d8_wren -> ok 748s Test: t_geom_a9d5_wren -> ok 748s Test: t_geom_a9d6_wren -> ok 748s Test: t_geom_a3d18_9b1B -> ok 748s Test: t_geom_a4d4_9b1B -> ok 748s Test: t_geom_a4d18_9b1B -> ok 748s Test: t_geom_a5d32_9b1B -> ok 749s Test: t_geom_a6d4_9b1B -> ok 749s Test: t_geom_a7d11_9b1B -> ok 749s Test: t_geom_a7d18_9b1B -> ok 749s Test: t_geom_a11d1_9b1B -> ok 749s Test: t_wide_sdp_a6r1w1b1x1 -> ok 749s Test: t_wide_sdp_a7r1w1b1x1 -> ok 750s Test: t_wide_sdp_a8r1w1b1x1 -> ok 750s Test: t_wide_sdp_a6r0w0b0x0 -> ok 750s Test: t_wide_sdp_a6r1w0b0x0 -> ok 750s Test: t_wide_sdp_a6r2w0b0x0 -> ok 750s Test: t_wide_sdp_a6r3w0b0x0 -> ok 751s Test: t_wide_sdp_a6r4w0b0x0 -> ok 751s Test: t_wide_sdp_a6r5w0b0x0 -> ok 751s Test: t_wide_sdp_a6r0w1b0x0 -> ok 751s Test: t_wide_sdp_a6r0w1b1x0 -> ok 751s Test: t_wide_sdp_a6r0w2b0x0 -> ok 752s Test: t_wide_sdp_a6r0w2b2x0 -> ok 752s Test: t_wide_sdp_a6r0w3b2x0 -> ok 752s Test: t_wide_sdp_a6r0w4b2x0 -> ok 752s Test: t_wide_sdp_a6r0w5b2x0 -> ok 753s Test: t_wide_sdp_a7r0w0b0x0 -> ok 753s Test: t_wide_sdp_a7r1w0b0x0 -> ok 753s Test: t_wide_sdp_a7r2w0b0x0 -> ok 753s Test: t_wide_sdp_a7r3w0b0x0 -> ok 753s Test: t_wide_sdp_a7r4w0b0x0 -> ok 754s Test: t_wide_sdp_a7r5w0b0x0 -> ok 754s Test: t_wide_sdp_a7r0w1b0x0 -> ok 754s Test: t_wide_sdp_a7r0w1b1x0 -> ok 754s Test: t_wide_sdp_a7r0w2b0x0 -> ok 754s Test: t_wide_sdp_a7r0w2b2x0 -> ok 755s Test: t_wide_sdp_a7r0w3b2x0 -> ok 755s Test: t_wide_sdp_a7r0w4b2x0 -> ok 756s Test: t_wide_sdp_a7r0w5b2x0 -> ok 756s Test: t_wide_sp_mix_a6r1w1b1 -> ok 756s Test: t_wide_sp_mix_a7r1w1b1 -> ok 756s Test: t_wide_sp_mix_a8r1w1b1 -> ok 756s Test: t_wide_sp_mix_a6r0w0b0 -> ok 756s Test: t_wide_sp_mix_a6r1w0b0 -> ok 756s Test: t_wide_sp_mix_a6r2w0b0 -> ok 757s Test: t_wide_sp_mix_a6r3w0b0 -> ok 757s Test: t_wide_sp_mix_a6r4w0b0 -> ok 757s Test: t_wide_sp_mix_a6r5w0b0 -> ok 757s Test: t_wide_sp_mix_a6r0w1b0 -> ok 757s Test: t_wide_sp_mix_a6r0w1b1 -> ok 758s Test: t_wide_sp_mix_a6r0w2b0 -> ok 758s Test: t_wide_sp_mix_a6r0w2b2 -> ok 758s Test: t_wide_sp_mix_a6r0w3b2 -> ok 758s Test: t_wide_sp_mix_a6r0w4b2 -> ok 759s Test: t_wide_sp_mix_a6r0w5b2 -> ok 759s Test: t_wide_sp_mix_a7r0w0b0 -> ok 759s Test: t_wide_sp_mix_a7r1w0b0 -> ok 759s Test: t_wide_sp_mix_a7r2w0b0 -> ok 759s Test: t_wide_sp_mix_a7r3w0b0 -> ok 759s Test: t_wide_sp_mix_a7r4w0b0 -> ok 760s Test: t_wide_sp_mix_a7r5w0b0 -> ok 760s Test: t_wide_sp_mix_a7r0w1b0 -> ok 760s Test: t_wide_sp_mix_a7r0w1b1 -> ok 760s Test: t_wide_sp_mix_a7r0w2b0 -> ok 760s Test: t_wide_sp_mix_a7r0w2b2 -> ok 761s Test: t_wide_sp_mix_a7r0w3b2 -> ok 761s Test: t_wide_sp_mix_a7r0w4b2 -> ok 762s Test: t_wide_sp_mix_a7r0w5b2 -> ok 762s Test: t_wide_sp_tied_a6r1w1b1 -> ok 762s Test: t_wide_sp_tied_a7r1w1b1 -> ok 762s Test: t_wide_sp_tied_a8r1w1b1 -> ok 762s Test: t_wide_sp_tied_a6r0w0b0 -> ok 762s Test: t_wide_sp_tied_a6r1w0b0 -> ok 762s Test: t_wide_sp_tied_a6r2w0b0 -> ok 763s Test: t_wide_sp_tied_a6r3w0b0 -> ok 763s Test: t_wide_sp_tied_a6r4w0b0 -> ok 763s Test: t_wide_sp_tied_a6r5w0b0 -> ok 763s Test: t_wide_sp_tied_a6r0w1b0 -> ok 763s Test: t_wide_sp_tied_a6r0w1b1 -> ok 764s Test: t_wide_sp_tied_a6r0w2b0 -> ok 764s Test: t_wide_sp_tied_a6r0w2b2 -> ok 764s Test: t_wide_sp_tied_a6r0w3b2 -> ok 764s Test: t_wide_sp_tied_a6r0w4b2 -> ok 765s Test: t_wide_sp_tied_a6r0w5b2 -> ok 765s Test: t_wide_sp_tied_a7r0w0b0 -> ok 765s Test: t_wide_sp_tied_a7r1w0b0 -> ok 765s Test: t_wide_sp_tied_a7r2w0b0 -> ok 765s Test: t_wide_sp_tied_a7r3w0b0 -> ok 765s Test: t_wide_sp_tied_a7r4w0b0 -> ok 766s Test: t_wide_sp_tied_a7r5w0b0 -> ok 766s Test: t_wide_sp_tied_a7r0w1b0 -> ok 766s Test: t_wide_sp_tied_a7r0w1b1 -> ok 766s Test: t_wide_sp_tied_a7r0w2b0 -> ok 766s Test: t_wide_sp_tied_a7r0w2b2 -> ok 767s Test: t_wide_sp_tied_a7r0w3b2 -> ok 767s Test: t_wide_sp_tied_a7r0w4b2 -> ok 767s Test: t_wide_sp_tied_a7r0w5b2 -> ok 767s Test: t_wide_read_a6r1w1b1 -> ok 768s Test: t_wide_write_a6r1w1b1 -> ok 768s Test: t_wide_read_a7r1w1b1 -> ok 768s Test: t_wide_write_a7r1w1b1 -> ok 768s Test: t_wide_read_a8r1w1b1 -> ok 768s Test: t_wide_write_a8r1w1b1 -> ok 768s Test: t_wide_read_a6r0w0b0 -> ok 769s Test: t_wide_write_a6r0w0b0 -> ok 769s Test: t_wide_read_a6r1w0b0 -> ok 769s Test: t_wide_write_a6r1w0b0 -> ok 769s Test: t_wide_read_a6r2w0b0 -> ok 769s Test: t_wide_write_a6r2w0b0 -> ok 770s Test: t_wide_read_a6r3w0b0 -> ok 770s Test: t_wide_write_a6r3w0b0 -> ok 770s Test: t_wide_read_a6r4w0b0 -> ok 770s Test: t_wide_write_a6r4w0b0 -> ok 770s Test: t_wide_read_a6r5w0b0 -> ok 771s Test: t_wide_write_a6r5w0b0 -> ok 771s Test: t_wide_read_a6r0w1b0 -> ok 771s Test: t_wide_write_a6r0w1b0 -> ok 771s Test: t_wide_read_a6r0w1b1 -> ok 771s Test: t_wide_write_a6r0w1b1 -> ok 772s Test: t_wide_read_a6r0w2b0 -> ok 772s Test: t_wide_write_a6r0w2b0 -> ok 772s Test: t_wide_read_a6r0w2b2 -> ok 772s Test: t_wide_write_a6r0w2b2 -> ok 772s Test: t_wide_read_a6r0w3b2 -> ok 773s Test: t_wide_write_a6r0w3b2 -> ok 773s Test: t_wide_read_a6r0w4b2 -> ok 773s Test: t_wide_write_a6r0w4b2 -> ok 773s Test: t_wide_read_a6r0w5b2 -> ok 774s Test: t_wide_write_a6r0w5b2 -> ok 774s Test: t_wide_read_a7r0w0b0 -> ok 774s Test: t_wide_write_a7r0w0b0 -> ok 774s Test: t_wide_read_a7r1w0b0 -> ok 774s Test: t_wide_write_a7r1w0b0 -> ok 775s Test: t_wide_read_a7r2w0b0 -> ok 775s Test: t_wide_write_a7r2w0b0 -> ok 775s Test: t_wide_read_a7r3w0b0 -> ok 775s Test: t_wide_write_a7r3w0b0 -> ok 775s Test: t_wide_read_a7r4w0b0 -> ok 776s Test: t_wide_write_a7r4w0b0 -> ok 776s Test: t_wide_read_a7r5w0b0 -> ok 776s Test: t_wide_write_a7r5w0b0 -> ok 776s Test: t_wide_read_a7r0w1b0 -> ok 776s Test: t_wide_write_a7r0w1b0 -> ok 777s Test: t_wide_read_a7r0w1b1 -> ok 777s Test: t_wide_write_a7r0w1b1 -> ok 777s Test: t_wide_read_a7r0w2b0 -> ok 777s Test: t_wide_write_a7r0w2b0 -> ok 777s Test: t_wide_read_a7r0w2b2 -> ok 778s Test: t_wide_write_a7r0w2b2 -> ok 778s Test: t_wide_read_a7r0w3b2 -> ok 778s Test: t_wide_write_a7r0w3b2 -> ok 778s Test: t_wide_read_a7r0w4b2 -> ok 778s Test: t_wide_write_a7r0w4b2 -> ok 779s Test: t_wide_read_a7r0w5b2 -> ok 779s Test: t_wide_write_a7r0w5b2 -> ok 779s Test: t_quad_port_a2d2 -> ok 779s Test: t_quad_port_a4d2 -> ok 780s Test: t_quad_port_a5d2 -> ok 780s Test: t_quad_port_a4d4 -> ok 780s Test: t_quad_port_a6d2 -> ok 780s Test: t_quad_port_a4d8 -> ok 780s Test: t_wide_quad_a4w2r1 -> ok 781s Test: t_wide_oct_a4w2r1 -> ok 781s Test: t_wide_quad_a4w2r2 -> ok 781s Test: t_wide_oct_a4w2r2 -> ok 781s Test: t_wide_quad_a4w2r3 -> ok 781s Test: t_wide_oct_a4w2r3 -> ok 781s Test: t_wide_quad_a4w2r4 -> ok 781s Test: t_wide_oct_a4w2r4 -> ok 782s Test: t_wide_quad_a4w2r5 -> ok 782s Test: t_wide_oct_a4w2r5 -> ok 782s Test: t_wide_quad_a4w2r6 -> ok 782s Test: t_wide_oct_a4w2r6 -> ok 782s Test: t_wide_quad_a4w2r7 -> ok 783s Test: t_wide_oct_a4w2r7 -> ok 783s Test: t_wide_quad_a4w2r8 -> ok 783s Test: t_wide_oct_a4w2r8 -> ok 783s Test: t_wide_quad_a4w2r9 -> ok 783s Test: t_wide_oct_a4w2r9 -> ok 783s Test: t_wide_quad_a4w4r1 -> ok 784s Test: t_wide_oct_a4w4r1 -> ok 784s Test: t_wide_quad_a4w4r4 -> ok 784s Test: t_wide_oct_a4w4r4 -> ok 784s Test: t_wide_quad_a4w4r6 -> ok 784s Test: t_wide_oct_a4w4r6 -> ok 784s Test: t_wide_quad_a4w4r9 -> ok 785s Test: t_wide_oct_a4w4r9 -> ok 785s Test: t_wide_quad_a5w2r1 -> ok 785s Test: t_wide_oct_a5w2r1 -> ok 785s Test: t_wide_quad_a5w2r4 -> ok 785s Test: t_wide_oct_a5w2r4 -> ok 785s Test: t_wide_quad_a5w2r9 -> ok 786s Test: t_wide_oct_a5w2r9 -> ok 786s Test: t_no_reset -> ok 787s Test: t_gclken -> ok 787s Test: t_ungated -> ok 787s Test: t_gclken_ce -> ok 787s Test: t_grden -> ok 787s Test: t_grden_ce -> ok 787s Test: t_exclwr -> ok 787s Test: t_excl_rst -> ok 787s Test: t_transwr -> ok 788s Test: t_trans_rst -> ok 788s Test: t_wr_byte -> ok 788s Test: t_trans_byte -> ok 788s Test: t_wr_rst_byte -> ok 788s Test: t_rst_wr_byte -> ok 789s Test: t_rdenrst_wr_byte -> ok 789s make[1]: Leaving directory '/tmp/autopkgtest.5LcWtj/build.uCa/src/tests/memlib' 789s cd tests/bram && bash run-test.sh "" 789s generating tests.. 789s PRNG seed: 354220 789s running tests.. 789s make[1]: Entering directory '/tmp/autopkgtest.5LcWtj/build.uCa/src/tests/bram' 790s Passed memory_bram test 00_01. 790s Passed memory_bram test 00_02. 791s Passed memory_bram test 00_03. 792s Passed memory_bram test 00_04. 793s Passed memory_bram test 01_00. 794s Passed memory_bram test 01_02. 794s Passed memory_bram test 01_03. 795s Passed memory_bram test 01_04. 796s Passed memory_bram test 02_00. 797s Passed memory_bram test 02_01. 798s Passed memory_bram test 02_03. 799s Passed memory_bram test 02_04. 799s Passed memory_bram test 03_00. 800s Passed memory_bram test 03_01. 800s Passed memory_bram test 03_02. 801s Passed memory_bram test 03_04. 802s Passed memory_bram test 04_00. 802s Passed memory_bram test 04_01. 803s Passed memory_bram test 04_02. 804s Passed memory_bram test 04_03. 804s make[1]: Leaving directory '/tmp/autopkgtest.5LcWtj/build.uCa/src/tests/bram' 804s cd tests/various && bash run-test.sh 804s make[1]: Entering directory '/tmp/autopkgtest.5LcWtj/build.uCa/src/tests/various' 804s Warning: Wire abc9_test027.$abc$91$o is used but has no driver. 804s Passed abc9.ys 804s Passed aiger_dff.ys 804s Passed attrib05_port_conn.ys 804s Passed attrib07_func_call.ys 804s Passed autoname.ys 804s Passed blackbox_wb.ys 804s Passed bug1496.ys 804s Passed bug1531.ys 804s Passed bug1614.ys 804s Passed bug1710.ys 804s Passed bug1745.ys 804s Warning: Yosys has only limited support for tri-state logic at the moment. (< svinterface1_tb.v:50: $finish called at 420000 (10ps) 873s svinterface1_tb.v:50: $finish called at 420000 (10ps) 873s ok 873s Test: svinterface_at_top -> svinterface_at_top_tb.v:61: $finish called at 420000 (10ps) 874s svinterface_at_top_tb_wrapper.v:61: $finish called at 420000 (10ps) 874s ERROR! 874s Test: load_and_derive ->ok 874s Test: resolve_types ->ok 874s cd tests/svtypes && bash run-test.sh "" 874s make[1]: Entering directory '/tmp/autopkgtest.5LcWtj/build.uCa/src/tests/svtypes' 874s Passed enum_simple.ys 874s Passed logic_rom.ys 874s < ok 888s Test ../../techlibs/anlogic/cells_sim.v -> ok 888s Test ../../techlibs/coolrunner2/cells_sim.v -> ok 888s Test ../../techlibs/ecp5/cells_sim.v -> ok 888s Test ../../techlibs/efinix/cells_sim.v -> ok 888s Test ../../techlibs/gatemate/cells_sim.v -> ok 888s Test ../../techlibs/gowin/cells_sim.v -> ok 888s Test ../../techlibs/greenpak4/cells_sim.v -> ok 888s Test ../../techlibs/ice40/cells_sim.v -DICE40_HX ->../../techlibs/ice40/cells_sim.v:2231: warning: Choosing typ expression. 888s ../../techlibs/ice40/cells_sim.v:2231: warning: Choosing typ expression. 888s ../../techlibs/ice40/cells_sim.v:2233: warning: Choosing typ expression. 888s ../../techlibs/ice40/cells_sim.v:2233: warning: Choosing typ expression. 888s ../../techlibs/ice40/cells_sim.v:2235: warning: Choosing typ expression. 888s ../../techlibs/ice40/cells_sim.v:2235: warning: Choosing typ expression. 888s ../../techlibs/ice40/cells_sim.v:2237: warning: Choosing typ expression. 888s ../../techlibs/ice40/cells_sim.v:2237: warning: Choosing typ expression. 888s ../../techlibs/ice40/cells_sim.v:2239: warning: Choosing typ expression. 888s ../../techlibs/ice40/cells_sim.v:2239: warning: Choosing typ expression. 888s ok 888s Test ../../techlibs/ice40/cells_sim.v -DICE40_LP ->../../techlibs/ice40/cells_sim.v:2295: warning: Choosing typ expression. ok 888s Test ../../techlibs/ice40/cells_sim.v -DICE40_U -> 888s ../../techlibs/ice40/cells_sim.v:2295: warning: Choosing typ expression. 888s ../../techlibs/ice40/cells_sim.v:2297: warning: Choosing typ expression. 888s ../../techlibs/ice40/cells_sim.v:2297: warning: Choosing typ expression. 888s ../../techlibs/ice40/cells_sim.v:2299: warning: Choosing typ expression. 888s ../../techlibs/ice40/cells_sim.v:2299: warning: Choosing typ expression. 888s ../../techlibs/ice40/cells_sim.v:2301: warning: Choosing typ expression. 888s ../../techlibs/ice40/cells_sim.v:2301: warning: Choosing typ expression. 888s ../../techlibs/ice40/cells_sim.v:2303: warning: Choosing typ expression. 888s ../../techlibs/ice40/cells_sim.v:2303: warning: Choosing typ expression. 888s ../../techlibs/ice40/cells_sim.v:2359: warning: Choosing typ expression. 888s ../../techlibs/ice40/cells_sim.v:2359: warning: Choosing typ expression. 888s ../../techlibs/ice40/cells_sim.v:2361: warning: Choosing typ expression. 888s ../../techlibs/ice40/cells_sim.v:2361: warning: Choosing typ expression. 888s ../../techlibs/ice40/cells_sim.v:2363: warning: Choosing typ expression. 888s ../../techlibs/ice40/cells_sim.v:2363: warning: Choosing typ expression. 888s ../../techlibs/ice40/cells_sim.v:2365: warning: Choosing typ expression. 888s ../../techlibs/ice40/cells_sim.v:2365: warning: Choosing typ expression. 888s ../../techlibs/ice40/cells_sim.v:2367: warning: Choosing typ expression. 888s ../../techlibs/ice40/cells_sim.v:2367: warning: Choosing typ expression. 888s ok 888s Test ../../techlibs/intel/cyclone10lp/cells_sim.v -> ok 888s Test ../../techlibs/intel/max10/cells_sim.v -> ok 888s Test ../../techlibs/intel/cycloneive/cells_sim.v -> ok 888s Test ../../techlibs/intel/cycloneiv/cells_sim.v -> ok 888s Test ../../techlibs/intel_alm/cyclonev/cells_sim.v -> ok 888s Test ../../techlibs/nexus/cells_sim.v -> ok 888s Test ../../techlibs/quicklogic/cells_sim.v -> ok 888s Test ../../techlibs/sf2/cells_sim.v -> ok 888s Test ../../techlibs/xilinx/cells_sim.v -> ok 888s Test ../../techlibs/common/simcells.v -> ok 888s Test ../../techlibs/common/simlib.v -> ok 888s cd tests/arch/ice40 && bash run-test.sh "" 888s make[1]: Entering directory '/tmp/autopkgtest.5LcWtj/build.uCa/src/tests/arch/ice40' 889s Passed add_sub.ys 892s Passed adffs.ys 893s Warning: Resizing cell port SSCounter6o.l0.I3 from 32 bits to 1 bits. 893s Warning: Resizing cell port SSCounter6o.c0.CI from 32 bits to 1 bits. 893s Warning: Resizing cell port SSCounter6o.lien.I0 from 32 bits to 1 bits. 893s Warning: Resizing cell port SSCounter6o.lien.I1 from 32 bits to 1 bits. 893s Passed bug1597.ys 894s Passed bug1598.ys 895s Passed bug1626.ys 911s Passed bug1644.ys 912s Passed bug2061.ys 913s Passed counter.ys 914s Passed dffs.ys 923s Passed dpram.ys 924s Passed fsm.ys 924s Passed ice40_dsp.ys 925s Passed ice40_opt.ys 925s Passed ice40_wrapcarry.ys 928s Passed latches.ys 929s Passed logic.ys 934s Passed macc.ys 986s Passed memories.ys 987s Passed mul.ys 991s Passed mux.ys 991s Warning: wire '\data' is assigned in a block at rom.v:10.5-10.15. 991s Warning: wire '\data' is assigned in a block at rom.v:11.5-11.15. 991s Warning: wire '\data' is assigned in a block at rom.v:12.5-12.15. 991s Warning: wire '\data' is assigned in a block at rom.v:13.6-13.16. 991s Warning: wire '\data' is assigned in a block at rom.v:14.6-14.16. 991s Warning: wire '\data' is assigned in a block at rom.v:15.6-15.16. 991s Warning: wire '\data' is assigned in a block at rom.v:16.11-16.21. 992s Passed rom.ys 992s Passed shifter.ys 992s Warning: wire '\read_data' is assigned in a block at spram.v:19.3-19.25. 994s Passed spram.ys 995s Passed tribuf.ys 995s make[1]: Leaving directory '/tmp/autopkgtest.5LcWtj/build.uCa/src/tests/arch/ice40' 995s cd tests/arch/xilinx && bash run-test.sh "" 995s make[1]: Entering directory '/tmp/autopkgtest.5LcWtj/build.uCa/src/tests/arch/xilinx' 1010s Warning: Whitebox '$paramod\FDRE\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. 1010s Warning: Whitebox 'FDSE' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. 1010s Warning: Whitebox '$paramod\FDRE_1\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. 1010s Warning: Whitebox '$paramod\FDSE_1\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. 1034s Passed abc9_dff.ys 1039s Warning: Shift register inference not yet supported for family xc3s. 1042s Passed add_sub.ys 1060s Passed adffs.ys 1065s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DIADI from 64 bits to 16 bits. 1065s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOADO from 64 bits to 16 bits. 1065s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOBDO from 64 bits to 16 bits. 1065s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOPADOP from 8 bits to 2 bits. 1065s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOPBDOP from 8 bits to 2 bits. 1065s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.WEA from 4 bits to 2 bits. 1074s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.WEBWE from 1 bits to 4 bits. 1079s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DIADI from 64 bits to 16 bits. 1079s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOADO from 64 bits to 16 bits. 1079s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOBDO from 64 bits to 16 bits. 1079s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOPADOP from 8 bits to 2 bits. 1079s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOPBDOP from 8 bits to 2 bits. 1079s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.WEA from 4 bits to 2 bits. 1079s Warning: Selection "asym_ram_sdp_read_wider" did not match any module. 1093s Passed asym_ram_sdp.ys 1097s Warning: Resizing cell port block_ram.memory.0.0.DIADI from 64 bits to 16 bits. 1097s Warning: Resizing cell port block_ram.memory.0.0.DOADO from 64 bits to 16 bits. 1097s Warning: Resizing cell port block_ram.memory.0.0.DOBDO from 64 bits to 16 bits. 1097s Warning: Resizing cell port block_ram.memory.0.0.DOPADOP from 8 bits to 2 bits. 1097s Warning: Resizing cell port block_ram.memory.0.0.DOPBDOP from 8 bits to 2 bits. 1097s Warning: Resizing cell port block_ram.memory.0.0.WEA from 4 bits to 2 bits. 1122s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DIADI from 64 bits to 16 bits. 1122s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOADO from 64 bits to 16 bits. 1122s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOBDO from 64 bits to 16 bits. 1122s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOPADOP from 8 bits to 2 bits. 1122s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOPBDOP from 8 bits to 2 bits. 1122s Warning: Resizing cell port distributed_ram_manual.memory.0.0.WEA from 4 bits to 2 bits. 1122s Passed attributes_test.ys 1126s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIADI from 64 bits to 16 bits. 1126s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOADO from 64 bits to 16 bits. 1126s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOBDO from 64 bits to 16 bits. 1126s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPADOP from 8 bits to 2 bits. 1126s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPBDOP from 8 bits to 2 bits. 1126s Warning: Resizing cell port sync_ram_sdp.memory.0.0.WEA from 4 bits to 2 bits. 1131s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIPADIP from 8 bits to 2 bits. 1149s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIADI from 64 bits to 32 bits. 1149s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIPADIP from 8 bits to 4 bits. 1149s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOADO from 64 bits to 32 bits. 1149s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOBDO from 64 bits to 32 bits. 1149s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPADOP from 8 bits to 4 bits. 1149s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPBDOP from 8 bits to 4 bits. 1177s Passed blockram.ys 1181s Passed bug1460.ys 1185s Passed bug1462.ys 1189s Passed bug1480.ys 1195s Passed bug1598.ys 1196s Warning: Wire top.\t is used but has no driver. 1196s Warning: Wire top.\in is used but has no driver. 1198s Passed bug1605.ys 1199s Passed bug3670.ys 1204s Passed counter.ys 1224s Passed dffs.ys 1240s Passed dsp_abc9.ys 1252s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef. 1252s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef. 1306s Passed dsp_cascade.ys 1310s Passed dsp_fastfir.ys 1317s Passed dsp_simd.ys 1322s Warning: Shift register inference not yet supported for family xc3se. 1326s Passed fsm.ys 1339s Passed latches.ys 1344s Passed logic.ys 1386s Warning: Shift register inference not yet supported for family xc3s. 1390s Passed lutram.ys 1402s Passed macc.ys 1410s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef. 1410s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef. 1412s Passed mul.ys 1412s Warning: Replacing memory \M with list of registers. See mul_unsigned.v:25 1422s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef. 1422s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef. 1427s Passed mul_unsigned.ys 1446s Passed mux.ys 1446s Warning: Shift register inference not yet supported for family xc3se. 1459s Passed mux_lut4.ys 1467s Passed nosrl.ys 1468s Passed opt_lut_ins.ys 1479s Passed pmgen_xilinx_srl.ys 1485s Warning: Resizing cell port priority_memory.mem.0.0.ADDRARDADDR from 16 bits to 15 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.0.ADDRBWRADDR from 16 bits to 15 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.0.DINADIN from 64 bits to 32 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.0.DINBDIN from 64 bits to 32 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.0.DINPADINP from 8 bits to 4 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.0.DINPBDINP from 8 bits to 4 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.0.DOUTADOUT from 64 bits to 32 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.0.DOUTBDOUT from 64 bits to 32 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.0.DOUTPADOUTP from 8 bits to 4 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.0.DOUTPBDOUTP from 8 bits to 4 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.0.WEBWE from 4 bits to 8 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.1.ADDRARDADDR from 16 bits to 15 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.1.ADDRBWRADDR from 16 bits to 15 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.1.DINADIN from 64 bits to 32 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.1.DINBDIN from 64 bits to 32 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.1.DINPADINP from 8 bits to 4 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.1.DINPBDINP from 8 bits to 4 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.1.DOUTADOUT from 64 bits to 32 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.1.DOUTBDOUT from 64 bits to 32 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.1.DOUTPADOUTP from 8 bits to 4 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.1.DOUTPBDOUTP from 8 bits to 4 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.1.WEBWE from 4 bits to 8 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.2.ADDRARDADDR from 16 bits to 15 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.2.ADDRBWRADDR from 16 bits to 15 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.2.DINADIN from 64 bits to 32 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.2.DINBDIN from 64 bits to 32 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.2.DINPADINP from 8 bits to 4 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.2.DINPBDINP from 8 bits to 4 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.2.DOUTADOUT from 64 bits to 32 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.2.DOUTBDOUT from 64 bits to 32 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.2.DOUTPADOUTP from 8 bits to 4 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.2.DOUTPBDOUTP from 8 bits to 4 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.2.WEBWE from 4 bits to 8 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.3.ADDRARDADDR from 16 bits to 15 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.3.ADDRBWRADDR from 16 bits to 15 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.3.DINADIN from 64 bits to 32 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.3.DINBDIN from 64 bits to 32 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.3.DINPADINP from 8 bits to 4 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.3.DINPBDINP from 8 bits to 4 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.3.DOUTADOUT from 64 bits to 32 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.3.DOUTBDOUT from 64 bits to 32 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.3.DOUTPADOUTP from 8 bits to 4 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.3.DOUTPBDOUTP from 8 bits to 4 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.3.WEBWE from 4 bits to 8 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.4.ADDRARDADDR from 16 bits to 15 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.4.ADDRBWRADDR from 16 bits to 15 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.4.DINADIN from 64 bits to 32 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.4.DINBDIN from 64 bits to 32 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.4.DINPADINP from 8 bits to 4 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.4.DINPBDINP from 8 bits to 4 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.4.DOUTADOUT from 64 bits to 32 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.4.DOUTBDOUT from 64 bits to 32 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.4.DOUTPADOUTP from 8 bits to 4 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.4.DOUTPBDOUTP from 8 bits to 4 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.4.WEBWE from 4 bits to 8 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.5.ADDRARDADDR from 16 bits to 15 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.5.ADDRBWRADDR from 16 bits to 15 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.5.DINADIN from 64 bits to 32 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.5.DINBDIN from 64 bits to 32 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.5.DINPADINP from 8 bits to 4 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.5.DINPBDINP from 8 bits to 4 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.5.DOUTADOUT from 64 bits to 32 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.5.DOUTBDOUT from 64 bits to 32 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.5.DOUTPADOUTP from 8 bits to 4 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.5.DOUTPBDOUTP from 8 bits to 4 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.5.WEBWE from 4 bits to 8 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.6.ADDRARDADDR from 16 bits to 15 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.6.ADDRBWRADDR from 16 bits to 15 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.6.DINADIN from 64 bits to 32 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.6.DINBDIN from 64 bits to 32 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.6.DINPADINP from 8 bits to 4 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.6.DINPBDINP from 8 bits to 4 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.6.DOUTADOUT from 64 bits to 32 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.6.DOUTBDOUT from 64 bits to 32 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.6.DOUTPADOUTP from 8 bits to 4 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.6.DOUTPBDOUTP from 8 bits to 4 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.6.WEBWE from 4 bits to 8 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.7.ADDRARDADDR from 16 bits to 15 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.7.ADDRBWRADDR from 16 bits to 15 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.7.DINADIN from 64 bits to 32 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.7.DINBDIN from 64 bits to 32 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.7.DINPADINP from 8 bits to 4 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.7.DINPBDINP from 8 bits to 4 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.7.DOUTADOUT from 64 bits to 32 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.7.DOUTBDOUT from 64 bits to 32 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.7.DOUTPADOUTP from 8 bits to 4 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.7.DOUTPBDOUTP from 8 bits to 4 bits. 1485s Warning: Resizing cell port priority_memory.mem.0.7.WEBWE from 4 bits to 8 bits. 1489s Warning: Resizing cell port priority_memory.mem.0.0.BWE_A from 8 bits to 9 bits. 1489s Warning: Resizing cell port priority_memory.mem.0.0.BWE_B from 8 bits to 9 bits. 1501s Warning: Resizing cell port sp_write_first.mem.0.0.BWE_A from 8 bits to 9 bits. 1506s Warning: Resizing cell port sp_read_first.mem.0.0.BWE_B from 8 bits to 9 bits. 1506s Passed priority_memory.ys 1513s Passed shifter.ys 1515s Passed tribuf.ys 1519s Passed xilinx_dffopt.ys 1519s Passed xilinx_dsp.ys 1519s Passed xilinx_srl.ys 1528s Passed macc.sh 1536s Passed tribuf.sh 1536s make[1]: Leaving directory '/tmp/autopkgtest.5LcWtj/build.uCa/src/tests/arch/xilinx' 1536s cd tests/arch/ecp5 && bash run-test.sh "" 1536s make[1]: Entering directory '/tmp/autopkgtest.5LcWtj/build.uCa/src/tests/arch/ecp5' 1537s Passed add_sub.ys 1539s Passed adffs.ys 1540s Passed bug1459.ys 1541s Passed bug1598.ys 1541s Passed bug1630.ys 1541s Warning: Literal has a width of 16 bit, but value requires 184 bit. (<>>/,/<<>>/ {print $0}' 2015s + iverilog -o iverilog-initial_display initial_display.v 2015s + ./iverilog-initial_display 2015s + diff yosys-initial_display.log iverilog-initial_display.log 2015s 2015s /----------------------------------------------------------------------------\ 2015s | | 2015s | yosys -- Yosys Open SYnthesis Suite | 2015s | | 2015s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2015s | | 2015s | Permission to use, copy, modify, and/or distribute this software for any | 2015s | purpose with or without fee is hereby granted, provided that the above | 2015s | copyright notice and this permission notice appear in all copies. | 2015s | | 2015s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2015s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2015s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2015s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2015s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2015s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2015s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2015s | | 2015s \----------------------------------------------------------------------------/ 2015s 2015s Yosys 0.33 (git sha1 2584903a060) 2015s 2015s 2015s -- Running command `read_verilog -DEVENT_CLK always_display.v; proc; opt_expr -mux_bool; clean' -- 2015s 2015s 1. Executing Verilog-2005 frontend: always_display.v 2015s Parsing Verilog input from `always_display.v' to AST representation. 2015s Generating RTLIL representation for module `\m'. 2015s Successfully finished Verilog frontend. 2015s 2015s 2. Executing PROC pass (convert processes to netlists). 2015s 2015s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2015s Cleaned up 0 empty switches. 2015s 2015s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2015s Removed a total of 0 dead cases. 2015s 2015s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2015s Removed 1 redundant assignment. 2015s Promoted 1 assignment to connection. 2015s 2015s 2.4. Executing PROC_INIT pass (extract init attributes). 2015s 2015s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2015s 2015s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2015s Converted 0 switches. 2015s 2015s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2015s Creating decoders for process `\m.$proc$always_display.v:4$1'. 2015s 2015s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2015s 2015s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2015s 2015s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2015s 2015s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2015s Removing empty process `m.$proc$always_display.v:4$1'. 2015s Cleaned up 0 empty switches. 2015s 2015s 2.12. Executing OPT_EXPR pass (perform const folding). 2015s Optimizing module m. 2015s 2015s 3. Executing OPT_EXPR pass (perform const folding). 2015s Optimizing module m. 2015s Removed 0 unused cells and 1 unused wires. 2015s 2015s -- Writing to `yosys-always_display-clk-1.v' using backend `verilog' -- 2015s 2015s 4. Executing Verilog backend. 2015s 2015s 4.1. Executing BMUXMAP pass. 2015s 2015s 4.2. Executing DEMUXMAP pass. 2015s Dumping module `\m'. 2015s 2015s End of script. Logfile hash: 0de35d2746, CPU: user 0.00s system 0.01s, MEM: 9.52 MB peak 2015s Yosys 0.33 (git sha1 2584903a060) 2015s Time spent: 37% 2x opt_expr (0 sec), 23% 1x clean (0 sec), ... 2015s + test_always_display clk -DEVENT_CLK 2015s + local subtest=clk 2015s + shift 2015s + ../../yosys -p 'read_verilog -DEVENT_CLK always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk-1.v 2015s + ../../yosys -p 'read_verilog yosys-always_display-clk-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk-2.v 2015s 2015s /----------------------------------------------------------------------------\ 2015s | | 2015s | yosys -- Yosys Open SYnthesis Suite | 2015s | | 2015s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2015s | | 2015s | Permission to use, copy, modify, and/or distribute this software for any | 2015s | purpose with or without fee is hereby granted, provided that the above | 2015s | copyright notice and this permission notice appear in all copies. | 2015s | | 2015s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2015s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2015s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2015s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2015s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2015s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2015s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2015s | | 2015s \----------------------------------------------------------------------------/ 2015s 2015s Yosys 0.33 (git sha1 2584903a060) 2015s 2015s 2015s -- Running command `read_verilog yosys-always_display-clk-1.v; proc; opt_expr -mux_bool; clean' -- 2015s 2015s 1. Executing Verilog-2005 frontend: yosys-always_display-clk-1.v 2015s Parsing Verilog input from `yosys-always_display-clk-1.v' to AST representation. 2015s Generating RTLIL representation for module `\m'. 2015s Successfully finished Verilog frontend. 2015s 2015s 2. Executing PROC pass (convert processes to netlists). 2015s 2015s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2015s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk-1.v:18$1'. 2015s Cleaned up 1 empty switch. 2015s 2015s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2015s Removed a total of 0 dead cases. 2015s 2015s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2015s Removed 1 redundant assignment. 2015s Promoted 1 assignment to connection. 2015s 2015s 2.4. Executing PROC_INIT pass (extract init attributes). 2015s 2015s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2015s 2015s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2015s Converted 0 switches. 2015s 2015s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2015s Creating decoders for process `\m.$proc$yosys-always_display-clk-1.v:18$1'. 2015s 2015s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2015s 2015s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2015s 2015s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2015s 2015s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2015s + diff yosys-always_display-clk-1.v yosys-always_display-clk-2.v 2015s + test_always_display clk_rst -DEVENT_CLK_RST 2015s + local subtest=clk_rst 2015s + shift 2015s + ../../yosys -p 'read_verilog -DEVENT_CLK_RST always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst-1.v 2015s Removing empty process `m.$proc$yosys-always_display-clk-1.v:18$1'. 2015s Cleaned up 0 empty switches. 2015s 2015s 2.12. Executing OPT_EXPR pass (perform const folding). 2015s Optimizing module m. 2015s 2015s 3. Executing OPT_EXPR pass (perform const folding). 2015s Optimizing module m. 2015s Removed 0 unused cells and 1 unused wires. 2015s 2015s -- Writing to `yosys-always_display-clk-2.v' using backend `verilog' -- 2015s 2015s 4. Executing Verilog backend. 2015s 2015s 4.1. Executing BMUXMAP pass. 2015s 2015s 4.2. Executing DEMUXMAP pass. 2015s Dumping module `\m'. 2015s 2015s End of script. Logfile hash: e35e8bb689, CPU: user 0.01s system 0.00s, MEM: 9.54 MB peak 2015s Yosys 0.33 (git sha1 2584903a060) 2015s Time spent: 34% 2x opt_expr (0 sec), 23% 1x clean (0 sec), ... 2015s 2015s /----------------------------------------------------------------------------\ 2015s | | 2015s | yosys -- Yosys Open SYnthesis Suite | 2015s | | 2015s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2015s | | 2015s | Permission to use, copy, modify, and/or distribute this software for any | 2015s | purpose with or without fee is hereby granted, provided that the above | 2015s | copyright notice and this permission notice appear in all copies. | 2015s | | 2015s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2015s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2015s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2015s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2015s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2015s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2015s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2015s | | 2015s \----------------------------------------------------------------------------/ 2015s 2015s Yosys 0.33 (git sha1 2584903a060) 2015s 2015s 2015s -- Running command `read_verilog -DEVENT_CLK_RST always_display.v; proc; opt_expr -mux_bool; clean' -- 2015s 2015s 1. Executing Verilog-2005 frontend: always_display.v 2015s Parsing Verilog input from `always_display.v' to AST representation. 2015s Generating RTLIL representation for module `\m'. 2015s Successfully finished Verilog frontend. 2015s 2015s 2. Executing PROC pass (convert processes to netlists). 2015s 2015s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2015s Cleaned up 0 empty switches. 2015s 2015s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2015s Removed a total of 0 dead cases. 2015s 2015s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2015s Removed 1 redundant assignment. 2015s Promoted 1 assignment to connection. 2015s 2015s 2.4. Executing PROC_INIT pass (extract init attributes). 2015s 2015s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2015s 2015s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2015s Converted 0 switches. 2015s 2015s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2015s Creating decoders for process `\m.$proc$always_display.v:7$1'. 2015s 2015s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2015s + ../../yosys -p 'read_verilog yosys-always_display-clk_rst-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst-2.v 2015s 2015s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2015s 2015s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2015s 2015s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2015s Removing empty process `m.$proc$always_display.v:7$1'. 2015s Cleaned up 0 empty switches. 2015s 2015s 2.12. Executing OPT_EXPR pass (perform const folding). 2015s Optimizing module m. 2015s 2015s 3. Executing OPT_EXPR pass (perform const folding). 2015s Optimizing module m. 2015s Removed 0 unused cells and 1 unused wires. 2015s 2015s -- Writing to `yosys-always_display-clk_rst-1.v' using backend `verilog' -- 2015s 2015s 4. Executing Verilog backend. 2015s 2015s 4.1. Executing BMUXMAP pass. 2015s 2015s 4.2. Executing DEMUXMAP pass. 2015s Dumping module `\m'. 2015s 2015s End of script. Logfile hash: c95608ddf0, CPU: user 0.01s system 0.00s, MEM: 9.54 MB peak 2015s Yosys 0.33 (git sha1 2584903a060) 2015s Time spent: 36% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ... 2015s 2015s /----------------------------------------------------------------------------\ 2015s | | 2015s | yosys -- Yosys Open SYnthesis Suite | 2015s | | 2015s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2015s | | 2015s | Permission to use, copy, modify, and/or distribute this software for any | 2015s | purpose with or without fee is hereby granted, provided that the above | 2015s | copyright notice and this permission notice appear in all copies. | 2015s | | 2015s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2015s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2015s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2015s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2015s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2015s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2015s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2015s | | 2015s \----------------------------------------------------------------------------/ 2015s 2015s Yosys 0.33 (git sha1 2584903a060) 2015s 2015s 2015s -- Running command `read_verilog yosys-always_display-clk_rst-1.v; proc; opt_expr -mux_bool; clean' -- 2015s 2015s 1. Executing Verilog-2005 frontend: yosys-always_display-clk_rst-1.v 2015s Parsing Verilog input from `yosys-always_display-clk_rst-1.v' to AST representation. 2015s Generating RTLIL representation for module `\m'. 2015s Successfully finished Verilog frontend. 2015s 2015s 2. Executing PROC pass (convert processes to netlists). 2015s 2015s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2015s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_rst-1.v:18$1'. 2015s Cleaned up 1 empty switch. 2015s 2015s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2015s Removed a total of 0 dead cases. 2015s 2015s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2015s Removed 1 redundant assignment. 2015s Promoted 1 assignment to connection. 2015s 2015s 2.4. Executing PROC_INIT pass (extract init attributes). 2015s 2015s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2015s 2015s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2015s Converted 0 switches. 2015s 2015s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2015s Creating decoders for process `\m.$proc$yosys-always_display-clk_rst-1.v:18$1'. 2015s 2015s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2015s 2015s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2015s 2015s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2015s 2015s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2015s Removing empty process `m.$proc$yosys-always_display-clk_rst-1.v:18$1'. 2015s Cleaned up 0 empty switches. 2015s 2015s 2.12. Executing OPT_EXPR pass (perform const folding). 2015s Optimizing module m. 2015s 2015s 3. Executing OPT_EXPR pass (perform const folding). 2015s Optimizing module m. 2015s + diff yosys-always_display-clk_rst-1.v yosys-always_display-clk_rst-2.v 2015s + test_always_display star -DEVENT_STAR 2015s + local subtest=star 2015s + shift 2015s + ../../yosys -p 'read_verilog -DEVENT_STAR always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star-1.v 2015s Removed 0 unused cells and 1 unused wires. 2015s 2015s -- Writing to `yosys-always_display-clk_rst-2.v' using backend `verilog' -- 2015s 2015s 4. Executing Verilog backend. 2015s 2015s 4.1. Executing BMUXMAP pass. 2015s 2015s 4.2. Executing DEMUXMAP pass. 2015s Dumping module `\m'. 2015s 2015s End of script. Logfile hash: faf50513c3, CPU: user 0.01s system 0.00s, MEM: 9.54 MB peak 2015s Yosys 0.33 (git sha1 2584903a060) 2015s Time spent: 34% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ... 2015s 2015s /----------------------------------------------------------------------------\ 2015s | | 2015s | yosys -- Yosys Open SYnthesis Suite | 2015s | | 2015s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2015s | | 2015s | Permission to use, copy, modify, and/or distribute this software for any | 2015s | purpose with or without fee is hereby granted, provided that the above | 2015s | copyright notice and this permission notice appear in all copies. | 2015s | | 2015s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2015s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2015s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2015s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2015s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2015s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2015s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2015s | | 2015s \----------------------------------------------------------------------------/ 2015s 2015s Yosys 0.33 (git sha1 2584903a060) 2015s 2015s 2015s -- Running command `read_verilog -DEVENT_STAR always_display.v; proc; opt_expr -mux_bool; clean' -- 2015s 2015s 1. Executing Verilog-2005 frontend: always_display.v 2016s + ../../yosys -p 'read_verilog yosys-always_display-star-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star-2.v 2016s + diff yosys-always_display-star-1.v yosys-always_display-star-2.v 2016s + test_always_display clk_en -DEVENT_CLK -DCOND_EN 2016s + local subtest=clk_en 2016s + shift 2016s + ../../yosys -p 'read_verilog -DEVENT_CLK -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_en-1.v 2016s Parsing Verilog input from `always_display.v' to AST representation. 2016s Generating RTLIL representation for module `\m'. 2016s Successfully finished Verilog frontend. 2016s 2016s 2. Executing PROC pass (convert processes to netlists). 2016s 2016s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Cleaned up 0 empty switches. 2016s 2016s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2016s Removed a total of 0 dead cases. 2016s 2016s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2016s Removed 1 redundant assignment. 2016s Promoted 1 assignment to connection. 2016s 2016s 2.4. Executing PROC_INIT pass (extract init attributes). 2016s 2016s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2016s 2016s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2016s Converted 0 switches. 2016s 2016s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2016s Creating decoders for process `\m.$proc$always_display.v:10$1'. 2016s 2016s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2016s 2016s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2016s 2016s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2016s 2016s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Removing empty process `m.$proc$always_display.v:10$1'. 2016s Cleaned up 0 empty switches. 2016s 2016s 2.12. Executing OPT_EXPR pass (perform const folding). 2016s Optimizing module m. 2016s 2016s 3. Executing OPT_EXPR pass (perform const folding). 2016s Optimizing module m. 2016s Removed 0 unused cells and 1 unused wires. 2016s 2016s -- Writing to `yosys-always_display-star-1.v' using backend `verilog' -- 2016s 2016s 4. Executing Verilog backend. 2016s 2016s 4.1. Executing BMUXMAP pass. 2016s 2016s 4.2. Executing DEMUXMAP pass. 2016s Dumping module `\m'. 2016s 2016s End of script. Logfile hash: 7b2c5274a5, CPU: user 0.00s system 0.00s, MEM: 9.54 MB peak 2016s Yosys 0.33 (git sha1 2584903a060) 2016s Time spent: 37% 2x opt_expr (0 sec), 23% 1x clean (0 sec), ... 2016s 2016s /----------------------------------------------------------------------------\ 2016s | | 2016s | yosys -- Yosys Open SYnthesis Suite | 2016s | | 2016s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2016s | | 2016s | Permission to use, copy, modify, and/or distribute this software for any | 2016s | purpose with or without fee is hereby granted, provided that the above | 2016s | copyright notice and this permission notice appear in all copies. | 2016s | | 2016s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2016s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2016s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2016s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2016s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2016s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2016s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2016s | | 2016s \----------------------------------------------------------------------------/ 2016s 2016s Yosys 0.33 (git sha1 2584903a060) 2016s 2016s 2016s -- Running command `read_verilog yosys-always_display-star-1.v; proc; opt_expr -mux_bool; clean' -- 2016s 2016s 1. Executing Verilog-2005 frontend: yosys-always_display-star-1.v 2016s Parsing Verilog input from `yosys-always_display-star-1.v' to AST representation. 2016s Generating RTLIL representation for module `\m'. 2016s Successfully finished Verilog frontend. 2016s 2016s 2. Executing PROC pass (convert processes to netlists). 2016s 2016s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-star-1.v:18$1'. 2016s Cleaned up 1 empty switch. 2016s 2016s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2016s Removed a total of 0 dead cases. 2016s 2016s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2016s Removed 1 redundant assignment. 2016s Promoted 1 assignment to connection. 2016s 2016s 2.4. Executing PROC_INIT pass (extract init attributes). 2016s 2016s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2016s 2016s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2016s Converted 0 switches. 2016s 2016s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2016s Creating decoders for process `\m.$proc$yosys-always_display-star-1.v:18$1'. 2016s 2016s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2016s 2016s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2016s 2016s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2016s 2016s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Removing empty process `m.$proc$yosys-always_display-star-1.v:18$1'. 2016s Cleaned up 0 empty switches. 2016s 2016s 2.12. Executing OPT_EXPR pass (perform const folding). 2016s Optimizing module m. 2016s 2016s 3. Executing OPT_EXPR pass (perform const folding). 2016s Optimizing module m. 2016s Removed 0 unused cells and 1 unused wires. 2016s 2016s -- Writing to `yosys-always_display-star-2.v' using backend `verilog' -- 2016s 2016s 4. Executing Verilog backend. 2016s 2016s 4.1. Executing BMUXMAP pass. 2016s 2016s 4.2. Executing DEMUXMAP pass. 2016s Dumping module `\m'. 2016s 2016s End of script. Logfile hash: 8979c5de0b, CPU: user 0.00s system 0.00s, MEM: 9.52 MB peak 2016s Yosys 0.33 (git sha1 2584903a060) 2016s Time spent: 35% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ... 2016s 2016s /----------------------------------------------------------------------------\ 2016s | | 2016s | yosys -- Yosys Open SYnthesis Suite | 2016s | | 2016s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2016s | | 2016s | Permission to use, copy, modify, and/or distribute this software for any | 2016s | purpose with or without fee is hereby granted, provided that the above | 2016s | copyright notice and this permission notice appear in all copies. | 2016s | | 2016s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2016s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2016s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2016s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2016s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2016s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2016s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2016s | | 2016s \----------------------------------------------------------------------------/ 2016s 2016s Yosys 0.33 (git sha1 2584903a060) 2016s 2016s 2016s -- Running command `read_verilog -DEVENT_CLK -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -- 2016s 2016s 1. Executing Verilog-2005 frontend: always_display.v 2016s Parsing Verilog input from `always_display.v' to AST representation. 2016s Generating RTLIL representation for module `\m'. 2016s Successfully finished Verilog frontend. 2016s 2016s 2. Executing PROC pass (convert processes to netlists). 2016s 2016s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Cleaned up 0 empty switches. 2016s 2016s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2016s Removed a total of 0 dead cases. 2016s 2016s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2016s Removed 0 redundant assignments. 2016s Promoted 0 assignments to connections. 2016s 2016s 2.4. Executing PROC_INIT pass (extract init attributes). 2016s 2016s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2016s 2016s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2016s Converted 0 switches. 2016s 2016s 2016s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2016s Creating decoders for process `\m.$proc$always_display.v:4$1'. 2016s 1/1: $display$always_display.v:15$2_EN 2016s 2016s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2016s 2016s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2016s 2016s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2016s 2016s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:4$1'. 2016s Removing empty process `m.$proc$always_display.v:4$1'. 2016s Cleaned up 1 empty switch. 2016s 2016s 2.12. Executing OPT_EXPR pass (perform const folding). 2016s + ../../yosys -p 'read_verilog yosys-always_display-clk_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_en-2.v 2016s Optimizing module m. 2016s 2016s 3. Executing OPT_EXPR pass (perform const folding). 2016s Optimizing module m. 2016s 2016s Removed 0 unused cells and 3 unused wires. 2016s 2016s -- Writing to `yosys-always_display-clk_en-1.v' using backend `verilog' -- 2016s 2016s 4. Executing Verilog backend. 2016s 2016s 4.1. Executing BMUXMAP pass. 2016s 2016s 4.2. Executing DEMUXMAP pass. 2016s Dumping module `\m'. 2016s 2016s End of script. Logfile hash: 4f8a3b339c, CPU: user 0.01s system 0.00s, MEM: 9.66 MB peak 2016s Yosys 0.33 (git sha1 2584903a060) 2016s Time spent: 38% 2x opt_expr (0 sec), 20% 1x clean (0 sec), ... 2016s 2016s /----------------------------------------------------------------------------\ 2016s | | 2016s | yosys -- Yosys Open SYnthesis Suite | 2016s | | 2016s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2016s | | 2016s | Permission to use, copy, modify, and/or distribute this software for any | 2016s | purpose with or without fee is hereby granted, provided that the above | 2016s | copyright notice and this permission notice appear in all copies. | 2016s | | 2016s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2016s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2016s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2016s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2016s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2016s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2016s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2016s | | 2016s \----------------------------------------------------------------------------/ 2016s 2016s Yosys 0.33 (git sha1 2584903a060) 2016s 2016s 2016s -- Running command `read_verilog yosys-always_display-clk_en-1.v; proc; opt_expr -mux_bool; clean' -- 2016s 2016s 1. Executing Verilog-2005 frontend: yosys-always_display-clk_en-1.v 2016s Parsing Verilog input from `yosys-always_display-clk_en-1.v' to AST representation. 2016s Generating RTLIL representation for module `\m'. 2016s Successfully finished Verilog frontend. 2016s 2016s 2. Executing PROC pass (convert processes to netlists). 2016s 2016s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Cleaned up 0 empty switches. 2016s 2016s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2016s Removed a total of 0 dead cases. 2016s 2016s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2016s Removed 0 redundant assignments. 2016s Promoted 0 assignments to connections. 2016s 2016s 2.4. Executing PROC_INIT pass (extract init attributes). 2016s 2016s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2016s 2016s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2016s Converted 0 switches. 2016s 2016s 2016s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2016s Creating decoders for process `\m.$proc$yosys-always_display-clk_en-1.v:18$1'. 2016s 1/1: $write$yosys-always_display-clk_en-1.v:20$2_EN 2016s 2016s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2016s 2016s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2016s 2016s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2016s 2016s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_en-1.v:18$1'. 2016s Removing empty process `m.$proc$yosys-always_display-clk_en-1.v:18$1'. 2016s Cleaned up 1 empty switch. 2016s 2016s 2.12. Executing OPT_EXPR pass (perform const folding). 2016s Optimizing module m. 2016s 2016s 3. Executing OPT_EXPR pass (perform const folding). 2016s Optimizing module m. 2016s 2016s Removed 0 unused cells and 3 unused wires. 2016s 2016s -- Writing to `yosys-always_display-clk_en-2.v' using backend `verilog' -- 2016s 2016s 4. Executing Verilog backend. 2016s 2016s 4.1. Executing BMUXMAP pass. 2016s 2016s 4.2. Executing DEMUXMAP pass. 2016s Dumping module `\m'. 2016s 2016s End of script. Logfile hash: 51e7fa3902, CPU: user 0.01s system 0.00s, MEM: 9.66 MB peak 2016s Yosys 0.33 (git sha1 2584903a060) 2016s Time spent: 36% 2x opt_expr (0 sec), 20% 1x clean (0 sec), ... 2016s + diff yosys-always_display-clk_en-1.v yosys-always_display-clk_en-2.v 2016s + test_always_display clk_rst_en -DEVENT_CLK_RST -DCOND_EN 2016s + local subtest=clk_rst_en 2016s + shift 2016s + ../../yosys -p 'read_verilog -DEVENT_CLK_RST -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst_en-1.v 2016s 2016s /----------------------------------------------------------------------------\ 2016s | | 2016s | yosys -- Yosys Open SYnthesis Suite | 2016s | | 2016s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2016s | | 2016s | Permission to use, copy, modify, and/or distribute this software for any | 2016s | purpose with or without fee is hereby granted, provided that the above | 2016s | copyright notice and this permission notice appear in all copies. | 2016s | | 2016s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2016s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2016s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2016s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2016s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2016s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2016s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2016s | | 2016s \----------------------------------------------------------------------------/ 2016s 2016s Yosys 0.33 (git sha1 2584903a060) 2016s 2016s 2016s -- Running command `read_verilog -DEVENT_CLK_RST -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -- 2016s 2016s 1. Executing Verilog-2005 frontend: always_display.v 2016s Parsing Verilog input from `always_display.v' to AST representation. 2016s Generating RTLIL representation for module `\m'. 2016s Successfully finished Verilog frontend. 2016s 2016s 2. Executing PROC pass (convert processes to netlists). 2016s 2016s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Cleaned up 0 empty switches. 2016s 2016s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2016s Removed a total of 0 dead cases. 2016s 2016s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2016s Removed 0 redundant assignments. 2016s Promoted 0 assignments to connections. 2016s 2016s 2.4. Executing PROC_INIT pass (extract init attributes). 2016s 2016s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2016s 2016s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2016s Converted 0 switches. 2016s 2016s 2016s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2016s Creating decoders for process `\m.$proc$always_display.v:7$1'. 2016s 1/1: $display$always_display.v:15$2_EN 2016s 2016s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2016s 2016s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2016s 2016s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2016s + ../../yosys -p 'read_verilog yosys-always_display-clk_rst_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst_en-2.v 2016s 2016s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:7$1'. 2016s Removing empty process `m.$proc$always_display.v:7$1'. 2016s Cleaned up 1 empty switch. 2016s 2016s 2.12. Executing OPT_EXPR pass (perform const folding). 2016s Optimizing module m. 2016s 2016s 3. Executing OPT_EXPR pass (perform const folding). 2016s Optimizing module m. 2016s 2016s Removed 0 unused cells and 3 unused wires. 2016s 2016s -- Writing to `yosys-always_display-clk_rst_en-1.v' using backend `verilog' -- 2016s 2016s 4. Executing Verilog backend. 2016s 2016s 4.1. Executing BMUXMAP pass. 2016s 2016s 4.2. Executing DEMUXMAP pass. 2016s Dumping module `\m'. 2016s 2016s End of script. Logfile hash: f9b4876f33, CPU: user 0.01s system 0.00s, MEM: 9.66 MB peak 2016s Yosys 0.33 (git sha1 2584903a060) 2016s Time spent: 38% 2x opt_expr (0 sec), 20% 1x clean (0 sec), ... 2016s 2016s /----------------------------------------------------------------------------\ 2016s | | 2016s | yosys -- Yosys Open SYnthesis Suite | 2016s | | 2016s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2016s | | 2016s | Permission to use, copy, modify, and/or distribute this software for any | 2016s | purpose with or without fee is hereby granted, provided that the above | 2016s | copyright notice and this permission notice appear in all copies. | 2016s | | 2016s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2016s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2016s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2016s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2016s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2016s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2016s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2016s | | 2016s \----------------------------------------------------------------------------/ 2016s 2016s Yosys 0.33 (git sha1 2584903a060) 2016s 2016s 2016s -- Running command `read_verilog yosys-always_display-clk_rst_en-1.v; proc; opt_expr -mux_bool; clean' -- 2016s 2016s 1. Executing Verilog-2005 frontend: yosys-always_display-clk_rst_en-1.v 2016s Parsing Verilog input from `yosys-always_display-clk_rst_en-1.v' to AST representation. 2016s Generating RTLIL representation for module `\m'. 2016s Successfully finished Verilog frontend. 2016s 2016s 2. Executing PROC pass (convert processes to netlists). 2016s 2016s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Cleaned up 0 empty switches. 2016s 2016s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2016s Removed a total of 0 dead cases. 2016s 2016s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2016s Removed 0 redundant assignments. 2016s Promoted 0 assignments to connections. 2016s 2016s 2.4. Executing PROC_INIT pass (extract init attributes). 2016s 2016s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2016s 2016s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2016s Converted 0 switches. 2016s 2016s 2016s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2016s Creating decoders for process `\m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'. 2016s 1/1: $write$yosys-always_display-clk_rst_en-1.v:20$2_EN 2016s 2016s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2016s 2016s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2016s 2016s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2016s 2016s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'. 2016s Removing empty process `m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'. 2016s Cleaned up 1 empty switch. 2016s 2016s 2.12. Executing OPT_EXPR pass (perform const folding). 2016s Optimizing module m. 2016s 2016s 3. Executing OPT_EXPR pass (perform const folding). 2016s Optimizing module m. 2016s 2016s + diff yosys-always_display-clk_rst_en-1.v yosys-always_display-clk_rst_en-2.v 2016s + test_always_display star_en -DEVENT_STAR -DCOND_EN 2016s + local subtest=star_en 2016s + shift 2016s + ../../yosys -p 'read_verilog -DEVENT_STAR -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star_en-1.v 2016s Removed 0 unused cells and 3 unused wires. 2016s 2016s -- Writing to `yosys-always_display-clk_rst_en-2.v' using backend `verilog' -- 2016s 2016s 4. Executing Verilog backend. 2016s 2016s 4.1. Executing BMUXMAP pass. 2016s 2016s 4.2. Executing DEMUXMAP pass. 2016s Dumping module `\m'. 2016s 2016s End of script. Logfile hash: 0c4b4eaa9c, CPU: user 0.01s system 0.00s, MEM: 9.66 MB peak 2016s Yosys 0.33 (git sha1 2584903a060) 2016s Time spent: 37% 2x opt_expr (0 sec), 21% 1x clean (0 sec), ... 2016s 2016s /----------------------------------------------------------------------------\ 2016s | | 2016s | yosys -- Yosys Open SYnthesis Suite | 2016s | | 2016s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2016s | | 2016s | Permission to use, copy, modify, and/or distribute this software for any | 2016s | purpose with or without fee is hereby granted, provided that the above | 2016s | copyright notice and this permission notice appear in all copies. | 2016s | | 2016s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2016s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2016s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2016s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2016s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2016s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2016s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2016s | | 2016s \----------------------------------------------------------------------------/ 2016s 2016s Yosys 0.33 (git sha1 2584903a060) 2016s 2016s 2016s -- Running command `read_verilog -DEVENT_STAR -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -- 2016s 2016s 1. Executing Verilog-2005 frontend: always_display.v 2016s Parsing Verilog input from `always_display.v' to AST representation. 2016s Generating RTLIL representation for module `\m'. 2016s Successfully finished Verilog frontend. 2016s 2016s 2. Executing PROC pass (convert processes to netlists). 2016s 2016s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Cleaned up 0 empty switches. 2016s 2016s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2016s Removed a total of 0 dead cases. 2016s 2016s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2016s Removed 0 redundant assignments. 2016s Promoted 0 assignments to connections. 2016s 2016s 2.4. Executing PROC_INIT pass (extract init attributes). 2016s 2016s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2016s 2016s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2016s Converted 0 switches. 2016s 2016s 2016s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2016s Creating decoders for process `\m.$proc$always_display.v:10$1'. 2016s 1/1: $display$always_display.v:15$2_EN 2016s 2016s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2016s 2016s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2016s 2016s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2016s 2016s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:10$1'. 2016s Removing empty process `m.$proc$always_display.v:10$1'. 2016s Cleaned up 1 empty switch. 2016s 2016s 2.12. Executing OPT_EXPR pass (perform const folding). 2016s Optimizing module m. 2016s 2016s 3. Executing OPT_EXPR pass (perform const folding). 2016s Optimizing module m. 2016s 2016s Removed 0 unused cells and 3 unused wires. 2016s 2016s -- Writing to `yosys-always_display-star_en-1.v' using backend `verilog' -- 2016s 2016s 4. Executing Verilog backend. 2016s + ../../yosys -p 'read_verilog yosys-always_display-star_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star_en-2.v 2016s + diff yosys-always_display-star_en-1.v yosys-always_display-star_en-2.v 2016s + test_roundtrip dec_unsigned -DBASE_DEC -DSIGN= 2016s + local subtest=dec_unsigned 2016s + shift 2016s + ../../yosys -p 'read_verilog -DBASE_DEC -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-dec_unsigned-1.v 2016s + ../../yosys -p 'read_verilog yosys-roundtrip-dec_unsigned-1.v; proc; clean' -o yosys-roundtrip-dec_unsigned-2.v 2016s 2016s 4.1. Executing BMUXMAP pass. 2016s 2016s 4.2. Executing DEMUXMAP pass. 2016s Dumping module `\m'. 2016s 2016s End of script. Logfile hash: d6a7335726, CPU: user 0.01s system 0.00s, MEM: 9.54 MB peak 2016s Yosys 0.33 (git sha1 2584903a060) 2016s Time spent: 37% 2x opt_expr (0 sec), 21% 1x clean (0 sec), ... 2016s 2016s /----------------------------------------------------------------------------\ 2016s | | 2016s | yosys -- Yosys Open SYnthesis Suite | 2016s | | 2016s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2016s | | 2016s | Permission to use, copy, modify, and/or distribute this software for any | 2016s | purpose with or without fee is hereby granted, provided that the above | 2016s | copyright notice and this permission notice appear in all copies. | 2016s | | 2016s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2016s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2016s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2016s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2016s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2016s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2016s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2016s | | 2016s \----------------------------------------------------------------------------/ 2016s 2016s Yosys 0.33 (git sha1 2584903a060) 2016s 2016s 2016s -- Running command `read_verilog yosys-always_display-star_en-1.v; proc; opt_expr -mux_bool; clean' -- 2016s 2016s 1. Executing Verilog-2005 frontend: yosys-always_display-star_en-1.v 2016s Parsing Verilog input from `yosys-always_display-star_en-1.v' to AST representation. 2016s Generating RTLIL representation for module `\m'. 2016s Successfully finished Verilog frontend. 2016s 2016s 2. Executing PROC pass (convert processes to netlists). 2016s 2016s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Cleaned up 0 empty switches. 2016s 2016s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2016s Removed a total of 0 dead cases. 2016s 2016s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2016s Removed 0 redundant assignments. 2016s Promoted 0 assignments to connections. 2016s 2016s 2.4. Executing PROC_INIT pass (extract init attributes). 2016s 2016s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2016s 2016s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2016s Converted 0 switches. 2016s 2016s 2016s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2016s Creating decoders for process `\m.$proc$yosys-always_display-star_en-1.v:18$1'. 2016s 1/1: $write$yosys-always_display-star_en-1.v:20$2_EN 2016s 2016s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2016s 2016s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2016s 2016s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2016s 2016s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-star_en-1.v:18$1'. 2016s Removing empty process `m.$proc$yosys-always_display-star_en-1.v:18$1'. 2016s Cleaned up 1 empty switch. 2016s 2016s 2.12. Executing OPT_EXPR pass (perform const folding). 2016s Optimizing module m. 2016s 2016s 3. Executing OPT_EXPR pass (perform const folding). 2016s Optimizing module m. 2016s 2016s Removed 0 unused cells and 3 unused wires. 2016s 2016s -- Writing to `yosys-always_display-star_en-2.v' using backend `verilog' -- 2016s 2016s 4. Executing Verilog backend. 2016s 2016s 4.1. Executing BMUXMAP pass. 2016s 2016s 4.2. Executing DEMUXMAP pass. 2016s Dumping module `\m'. 2016s 2016s End of script. Logfile hash: 18895a2046, CPU: user 0.01s system 0.00s, MEM: 9.54 MB peak 2016s Yosys 0.33 (git sha1 2584903a060) 2016s Time spent: 36% 2x opt_expr (0 sec), 21% 1x clean (0 sec), ... 2016s 2016s /----------------------------------------------------------------------------\ 2016s | | 2016s | yosys -- Yosys Open SYnthesis Suite | 2016s | | 2016s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2016s | | 2016s | Permission to use, copy, modify, and/or distribute this software for any | 2016s | purpose with or without fee is hereby granted, provided that the above | 2016s | copyright notice and this permission notice appear in all copies. | 2016s | | 2016s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2016s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2016s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2016s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2016s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2016s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2016s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2016s | | 2016s \----------------------------------------------------------------------------/ 2016s 2016s Yosys 0.33 (git sha1 2584903a060) 2016s 2016s 2016s -- Running command `read_verilog -DBASE_DEC -DSIGN= roundtrip.v; proc; clean' -- 2016s 2016s 1. Executing Verilog-2005 frontend: roundtrip.v 2016s Parsing Verilog input from `roundtrip.v' to AST representation. 2016s Generating RTLIL representation for module `\m'. 2016s Successfully finished Verilog frontend. 2016s 2016s 2. Executing PROC pass (convert processes to netlists). 2016s 2016s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Cleaned up 0 empty switches. 2016s 2016s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2016s Removed a total of 0 dead cases. 2016s 2016s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2016s Removed 1 redundant assignment. 2016s Promoted 1 assignment to connection. 2016s 2016s 2.4. Executing PROC_INIT pass (extract init attributes). 2016s 2016s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2016s 2016s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2016s Converted 0 switches. 2016s 2016s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2016s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2016s 2016s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2016s 2016s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2016s 2016s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2016s 2016s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Removing empty process `m.$proc$roundtrip.v:3$1'. 2016s Cleaned up 0 empty switches. 2016s 2016s 2.12. Executing OPT_EXPR pass (perform const folding). 2016s Optimizing module m. 2016s Removed 0 unused cells and 1 unused wires. 2016s 2016s -- Writing to `yosys-roundtrip-dec_unsigned-1.v' using backend `verilog' -- 2016s 2016s 3. Executing Verilog backend. 2016s 2016s 3.1. Executing BMUXMAP pass. 2016s 2016s 3.2. Executing DEMUXMAP pass. 2016s Dumping module `\m'. 2016s 2016s End of script. Logfile hash: bfb187b86d, CPU: user 0.01s system 0.00s, MEM: 9.52 MB peak 2016s Yosys 0.33 (git sha1 2584903a060) 2016s Time spent: 28% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 2016s 2016s /----------------------------------------------------------------------------\ 2016s | | 2016s | yosys -- Yosys Open SYnthesis Suite | 2016s | | 2016s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2016s | | 2016s | Permission to use, copy, modify, and/or distribute this software for any | 2016s | purpose with or without fee is hereby granted, provided that the above | 2016s | copyright notice and this permission notice appear in all copies. | 2016s | | 2016s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2016s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2016s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2016s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2016s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2016s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2016s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2016s | | 2016s \----------------------------------------------------------------------------/ 2016s 2016s Yosys 0.33 (git sha1 2584903a060) 2016s 2016s 2016s -- Running command `read_verilog yosys-roundtrip-dec_unsigned-1.v; proc; clean' -- 2016s 2016s 1. Executing Verilog-2005 frontend: yosys-roundtrip-dec_unsigned-1.v 2016s Parsing Verilog input from `yosys-roundtrip-dec_unsigned-1.v' to AST representation. 2016s Generating RTLIL representation for module `\m'. 2016s Successfully finished Verilog frontend. 2016s 2016s 2. Executing PROC pass (convert processes to netlists). 2016s 2016s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'. 2016s Cleaned up 1 empty switch. 2016s 2016s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2016s Removed a total of 0 dead cases. 2016s 2016s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2016s Removed 1 redundant assignment. 2016s Promoted 1 assignment to connection. 2016s 2016s 2.4. Executing PROC_INIT pass (extract init attributes). 2016s 2016s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2016s 2016s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2016s Converted 0 switches. 2016s 2016s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2016s Creating decoders for process `\m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'. 2016s 2016s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2016s 2016s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2016s 2016s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2016s 2016s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Removing empty process `m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'. 2016s Cleaned up 0 empty switches. 2016s 2016s 2.12. Executing OPT_EXPR pass (perform const folding). 2016s Optimizing module m. 2016s Removed 0 unused cells and 1 unused wires. 2016s 2016s -- Writing to `yosys-roundtrip-dec_unsigned-2.v' using backend `verilog' -- 2016s 2016s 3. Executing Verilog backend. 2016s 2016s 3.1. Executing BMUXMAP pass. 2016s 2016s 3.2. Executing DEMUXMAP pass. 2016s Dumping module `\m'. 2016s 2016s End of script. Logfile hash: 4be9539e85, CPU: user 0.01s system 0.00s, MEM: 9.53 MB peak 2016s Yosys 0.33 (git sha1 2584903a060) 2016s Time spent: 26% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 2016s + diff yosys-roundtrip-dec_unsigned-1.v yosys-roundtrip-dec_unsigned-2.v 2016s + iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned roundtrip.v roundtrip_tb.v 2016s + ./iverilog-roundtrip-dec_unsigned 2016s + iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned-1 yosys-roundtrip-dec_unsigned-1.v roundtrip_tb.v 2016s + ./iverilog-roundtrip-dec_unsigned-1 2016s + iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned-2 yosys-roundtrip-dec_unsigned-2.v roundtrip_tb.v 2016s + ./iverilog-roundtrip-dec_unsigned-1 2016s + diff iverilog-roundtrip-dec_unsigned.log iverilog-roundtrip-dec_unsigned-1.log 2016s + diff iverilog-roundtrip-dec_unsigned-1.log iverilog-roundtrip-dec_unsigned-2.log 2016s + test_roundtrip dec_signed -DBASE_DEC -DSIGN=signed 2016s + local subtest=dec_signed 2016s + shift 2016s + ../../yosys -p 'read_verilog -DBASE_DEC -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-dec_signed-1.v 2016s 2016s /----------------------------------------------------------------------------\ 2016s | | 2016s | yosys -- Yosys Open SYnthesis Suite | 2016s | | 2016s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2016s | | 2016s | Permission to use, copy, modify, and/or distribute this software for any | 2016s | purpose with or without fee is hereby granted, provided that the above | 2016s | copyright notice and this permission notice appear in all copies. | 2016s | | 2016s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2016s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2016s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2016s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2016s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2016s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2016s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2016s | | 2016s \----------------------------------------------------------------------------/ 2016s 2016s Yosys 0.33 (git sha1 2584903a060) 2016s 2016s 2016s -- Running command `read_verilog -DBASE_DEC -DSIGN=signed roundtrip.v; proc; clean' -- 2016s 2016s 1. Executing Verilog-2005 frontend: roundtrip.v 2016s Parsing Verilog input from `roundtrip.v' to AST representation. 2016s Generating RTLIL representation for module `\m'. 2016s Successfully finished Verilog frontend. 2016s 2016s 2. Executing PROC pass (convert processes to netlists). 2016s 2016s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Cleaned up 0 empty switches. 2016s 2016s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2016s Removed a total of 0 dead cases. 2016s 2016s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2016s Removed 1 redundant assignment. 2016s Promoted 1 assignment to connection. 2016s 2016s 2.4. Executing PROC_INIT pass (extract init attributes). 2016s 2016s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2016s 2016s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2016s Converted 0 switches. 2016s 2016s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2016s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2016s 2016s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2016s 2016s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2016s 2016s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2016s 2016s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Removing empty process `m.$proc$roundtrip.v:3$1'. 2016s Cleaned up 0 empty switches. 2016s 2016s 2.12. Executing OPT_EXPR pass (perform const folding). 2016s Optimizing module m. 2016s Removed 0 unused cells and 1 unused wires. 2016s 2016s -- Writing to `yosys-roundtrip-dec_signed-1.v' using backend `verilog' -- 2016s 2016s 3. Executing Verilog backend. 2016s 2016s 3.1. Executing BMUXMAP pass. 2016s 2016s 3.2. Executing DEMUXMAP pass. 2016s Dumping module `\m'. 2016s 2016s End of script. Logfile hash: bbdfa5ca92, CPU: user 0.01s system 0.00s, MEM: 9.53 MB peak 2016s Yosys 0.33 (git sha1 2584903a060) 2016s Time spent: 26% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... 2016s + ../../yosys -p 'read_verilog yosys-roundtrip-dec_signed-1.v; proc; clean' -o yosys-roundtrip-dec_signed-2.v 2016s 2016s /----------------------------------------------------------------------------\ 2016s | | 2016s | yosys -- Yosys Open SYnthesis Suite | 2016s | | 2016s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2016s | | 2016s | Permission to use, copy, modify, and/or distribute this software for any | 2016s | purpose with or without fee is hereby granted, provided that the above | 2016s | copyright notice and this permission notice appear in all copies. | 2016s | | 2016s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2016s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2016s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2016s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2016s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2016s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2016s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2016s | | 2016s \----------------------------------------------------------------------------/ 2016s 2016s Yosys 0.33 (git sha1 2584903a060) 2016s 2016s 2016s -- Running command `read_verilog yosys-roundtrip-dec_signed-1.v; proc; clean' -- 2016s 2016s 1. Executing Verilog-2005 frontend: yosys-roundtrip-dec_signed-1.v 2016s Parsing Verilog input from `yosys-roundtrip-dec_signed-1.v' to AST representation. 2016s Generating RTLIL representation for module `\m'. 2016s Successfully finished Verilog frontend. 2016s 2016s 2. Executing PROC pass (convert processes to netlists). 2016s 2016s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'. 2016s Cleaned up 1 empty switch. 2016s 2016s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2016s Removed a total of 0 dead cases. 2016s 2016s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2016s Removed 1 redundant assignment. 2016s Promoted 1 assignment to connection. 2016s 2016s 2.4. Executing PROC_INIT pass (extract init attributes). 2016s 2016s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2016s 2016s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2016s Converted 0 switches. 2016s 2016s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2016s Creating decoders for process `\m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'. 2016s 2016s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2016s 2016s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2016s 2016s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2016s 2016s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Removing empty process `m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'. 2016s Cleaned up 0 empty switches. 2016s 2016s 2.12. Executing OPT_EXPR pass (perform const folding). 2016s Optimizing module m. 2016s Removed 0 unused cells and 1 unused wires. 2016s 2016s -- Writing to `yosys-roundtrip-dec_signed-2.v' using backend `verilog' -- 2016s 2016s 3. Executing Verilog backend. 2016s 2016s 3.1. Executing BMUXMAP pass. 2016s 2016s 3.2. Executing DEMUXMAP pass. 2016s Dumping module `\m'. 2016s 2016s End of script. Logfile hash: b233de92a6, CPU: user 0.01s system 0.00s, MEM: 9.64 MB peak 2016s Yosys 0.33 (git sha1 2584903a060) 2016s Time spent: 24% 1x clean (0 sec), 19% 1x opt_expr (0 sec), ... 2016s + diff yosys-roundtrip-dec_signed-1.v yosys-roundtrip-dec_signed-2.v 2016s + iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed roundtrip.v roundtrip_tb.v 2016s + ./iverilog-roundtrip-dec_signed 2016s + iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed-1 yosys-roundtrip-dec_signed-1.v roundtrip_tb.v 2016s + ./iverilog-roundtrip-dec_signed-1 2016s + iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed-2 yosys-roundtrip-dec_signed-2.v roundtrip_tb.v 2016s + ./iverilog-roundtrip-dec_signed-1 2016s + diff iverilog-roundtrip-dec_signed.log iverilog-roundtrip-dec_signed-1.log 2016s + diff iverilog-roundtrip-dec_signed-1.log iverilog-roundtrip-dec_signed-2.log 2016s + test_roundtrip hex_unsigned -DBASE_HEX -DSIGN= 2016s + local subtest=hex_unsigned 2016s + shift 2016s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-hex_unsigned-1.v 2016s 2016s /----------------------------------------------------------------------------\ 2016s | | 2016s | yosys -- Yosys Open SYnthesis Suite | 2016s | | 2016s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2016s | | 2016s | Permission to use, copy, modify, and/or distribute this software for any | 2016s | purpose with or without fee is hereby granted, provided that the above | 2016s | copyright notice and this permission notice appear in all copies. | 2016s | | 2016s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2016s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2016s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2016s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2016s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2016s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2016s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2016s | | 2016s \----------------------------------------------------------------------------/ 2016s 2016s Yosys 0.33 (git sha1 2584903a060) 2016s 2016s 2016s -- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -- 2016s 2016s 1. Executing Verilog-2005 frontend: roundtrip.v 2016s Parsing Verilog input from `roundtrip.v' to AST representation. 2016s Generating RTLIL representation for module `\m'. 2016s Successfully finished Verilog frontend. 2016s 2016s 2. Executing PROC pass (convert processes to netlists). 2016s 2016s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Cleaned up 0 empty switches. 2016s 2016s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2016s Removed a total of 0 dead cases. 2016s 2016s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2016s Removed 1 redundant assignment. 2016s Promoted 1 assignment to connection. 2016s 2016s 2.4. Executing PROC_INIT pass (extract init attributes). 2016s 2016s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2016s 2016s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2016s Converted 0 switches. 2016s 2016s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2016s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2016s 2016s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2016s 2016s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2016s 2016s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2016s 2016s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Removing empty process `m.$proc$roundtrip.v:3$1'. 2016s Cleaned up 0 empty switches. 2016s 2016s 2.12. Executing OPT_EXPR pass (perform const folding). 2016s Optimizing module m. 2016s Removed 0 unused cells and 1 unused wires. 2016s 2016s -- Writing to `yosys-roundtrip-hex_unsigned-1.v' using backend `verilog' -- 2016s 2016s 3. Executing Verilog backend. 2016s 2016s 3.1. Executing BMUXMAP pass. 2016s 2016s 3.2. Executing DEMUXMAP pass. 2016s Dumping module `\m'. 2016s 2016s End of script. Logfile hash: 2377f2e106, CPU: user 0.01s system 0.00s, MEM: 9.54 MB peak 2016s Yosys 0.33 (git sha1 2584903a060) 2016s Time spent: 28% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ... 2016s + ../../yosys -p 'read_verilog yosys-roundtrip-hex_unsigned-1.v; proc; clean' -o yosys-roundtrip-hex_unsigned-2.v 2016s 2016s /----------------------------------------------------------------------------\ 2016s | | 2016s | yosys -- Yosys Open SYnthesis Suite | 2016s | | 2016s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2016s | | 2016s | Permission to use, copy, modify, and/or distribute this software for any | 2016s | purpose with or without fee is hereby granted, provided that the above | 2016s | copyright notice and this permission notice appear in all copies. | 2016s | | 2016s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2016s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2016s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2016s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2016s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2016s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2016s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2016s | | 2016s \----------------------------------------------------------------------------/ 2016s 2016s Yosys 0.33 (git sha1 2584903a060) 2016s 2016s 2016s -- Running command `read_verilog yosys-roundtrip-hex_unsigned-1.v; proc; clean' -- 2016s 2016s 1. Executing Verilog-2005 frontend: yosys-roundtrip-hex_unsigned-1.v 2016s Parsing Verilog input from `yosys-roundtrip-hex_unsigned-1.v' to AST representation. 2016s Generating RTLIL representation for module `\m'. 2016s Successfully finished Verilog frontend. 2016s 2016s 2. Executing PROC pass (convert processes to netlists). 2016s 2016s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'. 2016s Cleaned up 1 empty switch. 2016s 2016s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2016s Removed a total of 0 dead cases. 2016s 2016s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2016s Removed 1 redundant assignment. 2016s Promoted 1 assignment to connection. 2016s 2016s 2.4. Executing PROC_INIT pass (extract init attributes). 2016s 2016s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2016s 2016s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2016s Converted 0 switches. 2016s 2016s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2016s Creating decoders for process `\m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'. 2016s 2016s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2016s 2016s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2016s 2016s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2016s 2016s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Removing empty process `m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'. 2016s Cleaned up 0 empty switches. 2016s 2016s 2.12. Executing OPT_EXPR pass (perform const folding). 2016s Optimizing module m. 2016s Removed 0 unused cells and 1 unused wires. 2016s 2016s -- Writing to `yosys-roundtrip-hex_unsigned-2.v' using backend `verilog' -- 2016s 2016s 3. Executing Verilog backend. 2016s 2016s 3.1. Executing BMUXMAP pass. 2016s 2016s 3.2. Executing DEMUXMAP pass. 2016s Dumping module `\m'. 2016s 2016s End of script. Logfile hash: 06bfea69c8, CPU: user 0.01s system 0.00s, MEM: 9.52 MB peak 2016s Yosys 0.33 (git sha1 2584903a060) 2016s Time spent: 27% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... 2016s + diff yosys-roundtrip-hex_unsigned-1.v yosys-roundtrip-hex_unsigned-2.v 2016s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned roundtrip.v roundtrip_tb.v 2016s + ./iverilog-roundtrip-hex_unsigned 2016s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned-1 yosys-roundtrip-hex_unsigned-1.v roundtrip_tb.v 2016s + ./iverilog-roundtrip-hex_unsigned-1 2016s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned-2 yosys-roundtrip-hex_unsigned-2.v roundtrip_tb.v 2016s + ./iverilog-roundtrip-hex_unsigned-1 2016s + diff iverilog-roundtrip-hex_unsigned.log iverilog-roundtrip-hex_unsigned-1.log 2016s + diff iverilog-roundtrip-hex_unsigned-1.log iverilog-roundtrip-hex_unsigned-2.log 2016s + test_roundtrip hex_signed -DBASE_HEX -DSIGN=signed 2016s + local subtest=hex_signed 2016s + shift 2016s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-hex_signed-1.v 2016s 2016s /----------------------------------------------------------------------------\ 2016s | | 2016s | yosys -- Yosys Open SYnthesis Suite | 2016s | | 2016s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2016s | | 2016s | Permission to use, copy, modify, and/or distribute this software for any | 2016s | purpose with or without fee is hereby granted, provided that the above | 2016s | copyright notice and this permission notice appear in all copies. | 2016s | | 2016s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2016s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2016s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2016s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2016s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2016s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2016s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2016s | | 2016s \----------------------------------------------------------------------------/ 2016s 2016s Yosys 0.33 (git sha1 2584903a060) 2016s 2016s 2016s -- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -- 2016s 2016s 1. Executing Verilog-2005 frontend: roundtrip.v 2016s Parsing Verilog input from `roundtrip.v' to AST representation. 2016s Generating RTLIL representation for module `\m'. 2016s Successfully finished Verilog frontend. 2016s 2016s 2. Executing PROC pass (convert processes to netlists). 2016s 2016s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Cleaned up 0 empty switches. 2016s 2016s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2016s Removed a total of 0 dead cases. 2016s 2016s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2016s Removed 1 redundant assignment. 2016s Promoted 1 assignment to connection. 2016s 2016s 2.4. Executing PROC_INIT pass (extract init attributes). 2016s 2016s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2016s 2016s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2016s Converted 0 switches. 2016s 2016s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2016s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2016s 2016s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2016s 2016s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2016s 2016s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2016s 2016s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Removing empty process `m.$proc$roundtrip.v:3$1'. 2016s Cleaned up 0 empty switches. 2016s 2016s 2.12. Executing OPT_EXPR pass (perform const folding). 2016s Optimizing module m. 2016s Removed 0 unused cells and 1 unused wires. 2016s 2016s -- Writing to `yosys-roundtrip-hex_signed-1.v' using backend `verilog' -- 2016s 2016s 3. Executing Verilog backend. 2016s 2016s 3.1. Executing BMUXMAP pass. 2016s 2016s 3.2. Executing DEMUXMAP pass. 2016s Dumping module `\m'. 2016s 2016s End of script. Logfile hash: 824c3b1e65, CPU: user 0.00s system 0.00s, MEM: 9.54 MB peak 2016s Yosys 0.33 (git sha1 2584903a060) 2016s Time spent: 27% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ... 2016s + ../../yosys -p 'read_verilog yosys-roundtrip-hex_signed-1.v; proc; clean' -o yosys-roundtrip-hex_signed-2.v 2016s 2016s /----------------------------------------------------------------------------\ 2016s | | 2016s | yosys -- Yosys Open SYnthesis Suite | 2016s | | 2016s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2016s | | 2016s | Permission to use, copy, modify, and/or distribute this software for any | 2016s | purpose with or without fee is hereby granted, provided that the above | 2016s | copyright notice and this permission notice appear in all copies. | 2016s | | 2016s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2016s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2016s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2016s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2016s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2016s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2016s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2016s | | 2016s \----------------------------------------------------------------------------/ 2016s 2016s Yosys 0.33 (git sha1 2584903a060) 2016s 2016s 2016s -- Running command `read_verilog yosys-roundtrip-hex_signed-1.v; proc; clean' -- 2016s 2016s 1. Executing Verilog-2005 frontend: yosys-roundtrip-hex_signed-1.v 2016s Parsing Verilog input from `yosys-roundtrip-hex_signed-1.v' to AST representation. 2016s Generating RTLIL representation for module `\m'. 2016s Successfully finished Verilog frontend. 2016s 2016s 2. Executing PROC pass (convert processes to netlists). 2016s 2016s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'. 2016s Cleaned up 1 empty switch. 2016s 2016s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2016s Removed a total of 0 dead cases. 2016s 2016s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2016s Removed 1 redundant assignment. 2016s Promoted 1 assignment to connection. 2016s 2016s 2.4. Executing PROC_INIT pass (extract init attributes). 2016s 2016s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2016s 2016s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2016s Converted 0 switches. 2016s 2016s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2016s Creating decoders for process `\m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'. 2016s 2016s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2016s 2016s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2016s 2016s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2016s 2016s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Removing empty process `m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'. 2016s Cleaned up 0 empty switches. 2016s 2016s 2.12. Executing OPT_EXPR pass (perform const folding). 2016s Optimizing module m. 2016s Removed 0 unused cells and 1 unused wires. 2016s 2016s -- Writing to `yosys-roundtrip-hex_signed-2.v' using backend `verilog' -- 2016s 2016s 3. Executing Verilog backend. 2016s 2016s 3.1. Executing BMUXMAP pass. 2016s 2016s 3.2. Executing DEMUXMAP pass. 2016s Dumping module `\m'. 2016s 2016s End of script. Logfile hash: f18b3fa15b, CPU: user 0.00s system 0.00s, MEM: 9.53 MB peak 2016s Yosys 0.33 (git sha1 2584903a060) 2016s Time spent: 27% 1x clean (0 sec), 19% 1x opt_expr (0 sec), ... 2016s + diff yosys-roundtrip-hex_signed-1.v yosys-roundtrip-hex_signed-2.v 2016s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed roundtrip.v roundtrip_tb.v 2016s + ./iverilog-roundtrip-hex_signed 2016s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed-1 yosys-roundtrip-hex_signed-1.v roundtrip_tb.v 2016s + ./iverilog-roundtrip-hex_signed-1 2016s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed-2 yosys-roundtrip-hex_signed-2.v roundtrip_tb.v 2016s + ./iverilog-roundtrip-hex_signed-1 2016s + diff iverilog-roundtrip-hex_signed.log iverilog-roundtrip-hex_signed-1.log 2016s + diff iverilog-roundtrip-hex_signed-1.log iverilog-roundtrip-hex_signed-2.log 2016s + test_roundtrip oct_unsigned -DBASE_HEX -DSIGN= 2016s + local subtest=oct_unsigned 2016s + shift 2016s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-oct_unsigned-1.v 2016s 2016s /----------------------------------------------------------------------------\ 2016s | | 2016s | yosys -- Yosys Open SYnthesis Suite | 2016s | | 2016s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2016s | | 2016s | Permission to use, copy, modify, and/or distribute this software for any | 2016s | purpose with or without fee is hereby granted, provided that the above | 2016s | copyright notice and this permission notice appear in all copies. | 2016s | | 2016s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2016s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2016s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2016s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2016s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2016s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2016s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2016s | | 2016s \----------------------------------------------------------------------------/ 2016s 2016s Yosys 0.33 (git sha1 2584903a060) 2016s 2016s 2016s -- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -- 2016s 2016s 1. Executing Verilog-2005 frontend: roundtrip.v 2016s Parsing Verilog input from `roundtrip.v' to AST representation. 2016s Generating RTLIL representation for module `\m'. 2016s Successfully finished Verilog frontend. 2016s 2016s 2. Executing PROC pass (convert processes to netlists). 2016s 2016s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Cleaned up 0 empty switches. 2016s 2016s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2016s Removed a total of 0 dead cases. 2016s 2016s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2016s Removed 1 redundant assignment. 2016s Promoted 1 assignment to connection. 2016s 2016s 2.4. Executing PROC_INIT pass (extract init attributes). 2016s 2016s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2016s 2016s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2016s Converted 0 switches. 2016s 2016s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2016s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2016s 2016s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2016s 2016s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2016s 2016s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2016s 2016s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Removing empty process `m.$proc$roundtrip.v:3$1'. 2016s Cleaned up 0 empty switches. 2016s 2016s 2.12. Executing OPT_EXPR pass (perform const folding). 2016s Optimizing module m. 2016s Removed 0 unused cells and 1 unused wires. 2016s 2016s -- Writing to `yosys-roundtrip-oct_unsigned-1.v' using backend `verilog' -- 2016s 2016s 3. Executing Verilog backend. 2016s 2016s 3.1. Executing BMUXMAP pass. 2016s 2016s 3.2. Executing DEMUXMAP pass. 2016s Dumping module `\m'. 2016s 2016s End of script. Logfile hash: b768358a65, CPU: user 0.00s system 0.00s, MEM: 9.54 MB peak 2016s Yosys 0.33 (git sha1 2584903a060) 2016s Time spent: 28% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 2016s + ../../yosys -p 'read_verilog yosys-roundtrip-oct_unsigned-1.v; proc; clean' -o yosys-roundtrip-oct_unsigned-2.v 2016s 2016s /----------------------------------------------------------------------------\ 2016s | | 2016s | yosys -- Yosys Open SYnthesis Suite | 2016s | | 2016s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2016s | | 2016s | Permission to use, copy, modify, and/or distribute this software for any | 2016s | purpose with or without fee is hereby granted, provided that the above | 2016s | copyright notice and this permission notice appear in all copies. | 2016s | | 2016s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2016s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2016s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2016s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2016s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2016s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2016s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2016s | | 2016s \----------------------------------------------------------------------------/ 2016s 2016s Yosys 0.33 (git sha1 2584903a060) 2016s 2016s 2016s -- Running command `read_verilog yosys-roundtrip-oct_unsigned-1.v; proc; clean' -- 2016s 2016s 1. Executing Verilog-2005 frontend: yosys-roundtrip-oct_unsigned-1.v 2016s Parsing Verilog input from `yosys-roundtrip-oct_unsigned-1.v' to AST representation. 2016s Generating RTLIL representation for module `\m'. 2016s Successfully finished Verilog frontend. 2016s 2016s 2. Executing PROC pass (convert processes to netlists). 2016s 2016s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'. 2016s Cleaned up 1 empty switch. 2016s 2016s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2016s Removed a total of 0 dead cases. 2016s 2016s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2016s Removed 1 redundant assignment. 2016s Promoted 1 assignment to connection. 2016s 2016s 2.4. Executing PROC_INIT pass (extract init attributes). 2016s 2016s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2016s 2016s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2016s Converted 0 switches. 2016s 2016s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2016s Creating decoders for process `\m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'. 2016s 2016s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2016s 2016s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2016s 2016s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2016s 2016s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Removing empty process `m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'. 2016s Cleaned up 0 empty switches. 2016s 2016s 2.12. Executing OPT_EXPR pass (perform const folding). 2016s Optimizing module m. 2016s Removed 0 unused cells and 1 unused wires. 2016s 2016s -- Writing to `yosys-roundtrip-oct_unsigned-2.v' using backend `verilog' -- 2016s 2016s 3. Executing Verilog backend. 2016s 2016s 3.1. Executing BMUXMAP pass. 2016s 2016s 3.2. Executing DEMUXMAP pass. 2016s Dumping module `\m'. 2016s 2016s End of script. Logfile hash: 762621cd95, CPU: user 0.01s system 0.00s, MEM: 9.53 MB peak 2016s Yosys 0.33 (git sha1 2584903a060) 2016s Time spent: 27% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 2016s + diff yosys-roundtrip-oct_unsigned-1.v yosys-roundtrip-oct_unsigned-2.v 2016s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned roundtrip.v roundtrip_tb.v 2016s + ./iverilog-roundtrip-oct_unsigned 2016s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned-1 yosys-roundtrip-oct_unsigned-1.v roundtrip_tb.v 2016s + ./iverilog-roundtrip-oct_unsigned-1 2016s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned-2 yosys-roundtrip-oct_unsigned-2.v roundtrip_tb.v 2016s + ./iverilog-roundtrip-oct_unsigned-1 2016s + diff iverilog-roundtrip-oct_unsigned.log iverilog-roundtrip-oct_unsigned-1.log 2016s + diff iverilog-roundtrip-oct_unsigned-1.log iverilog-roundtrip-oct_unsigned-2.log 2016s + test_roundtrip oct_signed -DBASE_HEX -DSIGN=signed 2016s + local subtest=oct_signed 2016s + shift 2016s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-oct_signed-1.v 2016s 2016s /----------------------------------------------------------------------------\ 2016s | | 2016s | yosys -- Yosys Open SYnthesis Suite | 2016s | | 2016s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2016s | | 2016s | Permission to use, copy, modify, and/or distribute this software for any | 2016s | purpose with or without fee is hereby granted, provided that the above | 2016s | copyright notice and this permission notice appear in all copies. | 2016s | | 2016s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2016s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2016s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2016s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2016s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2016s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2016s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2016s | | 2016s \----------------------------------------------------------------------------/ 2016s 2016s Yosys 0.33 (git sha1 2584903a060) 2016s 2016s 2016s -- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -- 2016s 2016s 1. Executing Verilog-2005 frontend: roundtrip.v 2016s Parsing Verilog input from `roundtrip.v' to AST representation. 2016s Generating RTLIL representation for module `\m'. 2016s Successfully finished Verilog frontend. 2016s 2016s 2. Executing PROC pass (convert processes to netlists). 2016s 2016s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Cleaned up 0 empty switches. 2016s 2016s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2016s Removed a total of 0 dead cases. 2016s 2016s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2016s Removed 1 redundant assignment. 2016s Promoted 1 assignment to connection. 2016s 2016s 2.4. Executing PROC_INIT pass (extract init attributes). 2016s 2016s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2016s 2016s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2016s Converted 0 switches. 2016s 2016s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2016s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2016s 2016s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2016s 2016s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2016s 2016s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2016s 2016s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Removing empty process `m.$proc$roundtrip.v:3$1'. 2016s Cleaned up 0 empty switches. 2016s 2016s 2.12. Executing OPT_EXPR pass (perform const folding). 2016s Optimizing module m. 2016s Removed 0 unused cells and 1 unused wires. 2016s 2016s -- Writing to `yosys-roundtrip-oct_signed-1.v' using backend `verilog' -- 2016s 2016s 3. Executing Verilog backend. 2016s 2016s 3.1. Executing BMUXMAP pass. 2016s 2016s 3.2. Executing DEMUXMAP pass. 2016s Dumping module `\m'. 2016s 2016s End of script. Logfile hash: 7ec82b15e3, CPU: user 0.01s system 0.00s, MEM: 9.54 MB peak 2016s Yosys 0.33 (git sha1 2584903a060) 2016s Time spent: 27% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... 2016s + ../../yosys -p 'read_verilog yosys-roundtrip-oct_signed-1.v; proc; clean' -o yosys-roundtrip-oct_signed-2.v 2016s 2016s /----------------------------------------------------------------------------\ 2016s | | 2016s | yosys -- Yosys Open SYnthesis Suite | 2016s | | 2016s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2016s | | 2016s | Permission to use, copy, modify, and/or distribute this software for any | 2016s | purpose with or without fee is hereby granted, provided that the above | 2016s | copyright notice and this permission notice appear in all copies. | 2016s | | 2016s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2016s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2016s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2016s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2016s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2016s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2016s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2016s | | 2016s \----------------------------------------------------------------------------/ 2016s 2016s Yosys 0.33 (git sha1 2584903a060) 2016s 2016s 2016s -- Running command `read_verilog yosys-roundtrip-oct_signed-1.v; proc; clean' -- 2016s 2016s 1. Executing Verilog-2005 frontend: yosys-roundtrip-oct_signed-1.v 2016s Parsing Verilog input from `yosys-roundtrip-oct_signed-1.v' to AST representation. 2016s Generating RTLIL representation for module `\m'. 2016s Successfully finished Verilog frontend. 2016s 2016s 2. Executing PROC pass (convert processes to netlists). 2016s 2016s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'. 2016s Cleaned up 1 empty switch. 2016s 2016s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2016s Removed a total of 0 dead cases. 2016s 2016s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2016s Removed 1 redundant assignment. 2016s Promoted 1 assignment to connection. 2016s 2016s 2.4. Executing PROC_INIT pass (extract init attributes). 2016s 2016s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2016s 2016s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2016s Converted 0 switches. 2016s 2016s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2016s Creating decoders for process `\m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'. 2016s 2016s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2016s 2016s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2016s 2016s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2016s 2016s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Removing empty process `m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'. 2016s Cleaned up 0 empty switches. 2016s 2016s 2.12. Executing OPT_EXPR pass (perform const folding). 2016s Optimizing module m. 2016s Removed 0 unused cells and 1 unused wires. 2016s 2016s -- Writing to `yosys-roundtrip-oct_signed-2.v' using backend `verilog' -- 2016s 2016s 3. Executing Verilog backend. 2016s 2016s 3.1. Executing BMUXMAP pass. 2016s 2016s 3.2. Executing DEMUXMAP pass. 2016s Dumping module `\m'. 2016s 2016s End of script. Logfile hash: a747b9bd4f, CPU: user 0.01s system 0.00s, MEM: 9.53 MB peak 2016s Yosys 0.33 (git sha1 2584903a060) 2016s Time spent: 28% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 2016s + diff yosys-roundtrip-oct_signed-1.v yosys-roundtrip-oct_signed-2.v 2016s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed roundtrip.v roundtrip_tb.v 2016s + ./iverilog-roundtrip-oct_signed 2016s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed-1 yosys-roundtrip-oct_signed-1.v roundtrip_tb.v 2016s + ./iverilog-roundtrip-oct_signed-1 2016s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed-2 yosys-roundtrip-oct_signed-2.v roundtrip_tb.v 2016s + ./iverilog-roundtrip-oct_signed-1 2016s + diff iverilog-roundtrip-oct_signed.log iverilog-roundtrip-oct_signed-1.log 2016s + diff iverilog-roundtrip-oct_signed-1.log iverilog-roundtrip-oct_signed-2.log 2016s + test_roundtrip bin_unsigned -DBASE_HEX -DSIGN= 2016s + local subtest=bin_unsigned 2016s + shift 2016s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-bin_unsigned-1.v 2016s 2016s /----------------------------------------------------------------------------\ 2016s | | 2016s | yosys -- Yosys Open SYnthesis Suite | 2016s | | 2016s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2016s | | 2016s | Permission to use, copy, modify, and/or distribute this software for any | 2016s | purpose with or without fee is hereby granted, provided that the above | 2016s | copyright notice and this permission notice appear in all copies. | 2016s | | 2016s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2016s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2016s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2016s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2016s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2016s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2016s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2016s | | 2016s \----------------------------------------------------------------------------/ 2016s 2016s Yosys 0.33 (git sha1 2584903a060) 2016s 2016s 2016s -- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -- 2016s 2016s 1. Executing Verilog-2005 frontend: roundtrip.v 2016s Parsing Verilog input from `roundtrip.v' to AST representation. 2016s Generating RTLIL representation for module `\m'. 2016s Successfully finished Verilog frontend. 2016s 2016s 2. Executing PROC pass (convert processes to netlists). 2016s 2016s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Cleaned up 0 empty switches. 2016s 2016s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2016s Removed a total of 0 dead cases. 2016s 2016s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2016s Removed 1 redundant assignment. 2016s Promoted 1 assignment to connection. 2016s 2016s 2.4. Executing PROC_INIT pass (extract init attributes). 2016s 2016s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2016s 2016s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2016s Converted 0 switches. 2016s 2016s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2016s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2016s 2016s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2016s 2016s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2016s 2016s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2016s 2016s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Removing empty process `m.$proc$roundtrip.v:3$1'. 2016s Cleaned up 0 empty switches. 2016s 2016s 2.12. Executing OPT_EXPR pass (perform const folding). 2016s Optimizing module m. 2016s Removed 0 unused cells and 1 unused wires. 2016s 2016s -- Writing to `yosys-roundtrip-bin_unsigned-1.v' using backend `verilog' -- 2016s 2016s 3. Executing Verilog backend. 2016s 2016s 3.1. Executing BMUXMAP pass. 2016s 2016s 3.2. Executing DEMUXMAP pass. 2016s Dumping module `\m'. 2016s 2016s End of script. Logfile hash: 270b564880, CPU: user 0.00s system 0.01s, MEM: 9.52 MB peak 2016s Yosys 0.33 (git sha1 2584903a060) 2016s Time spent: 28% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ... 2016s + ../../yosys -p 'read_verilog yosys-roundtrip-bin_unsigned-1.v; proc; clean' -o yosys-roundtrip-bin_unsigned-2.v 2016s 2016s /----------------------------------------------------------------------------\ 2016s | | 2016s | yosys -- Yosys Open SYnthesis Suite | 2016s | | 2016s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2016s | | 2016s | Permission to use, copy, modify, and/or distribute this software for any | 2016s | purpose with or without fee is hereby granted, provided that the above | 2016s | copyright notice and this permission notice appear in all copies. | 2016s | | 2016s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2016s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2016s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2016s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2016s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2016s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2016s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2016s | | 2016s \----------------------------------------------------------------------------/ 2016s 2016s Yosys 0.33 (git sha1 2584903a060) 2016s 2016s 2016s -- Running command `read_verilog yosys-roundtrip-bin_unsigned-1.v; proc; clean' -- 2016s 2016s 1. Executing Verilog-2005 frontend: yosys-roundtrip-bin_unsigned-1.v 2016s Parsing Verilog input from `yosys-roundtrip-bin_unsigned-1.v' to AST representation. 2016s Generating RTLIL representation for module `\m'. 2016s Successfully finished Verilog frontend. 2016s 2016s 2. Executing PROC pass (convert processes to netlists). 2016s 2016s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'. 2016s Cleaned up 1 empty switch. 2016s 2016s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2016s Removed a total of 0 dead cases. 2016s 2016s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2016s Removed 1 redundant assignment. 2016s Promoted 1 assignment to connection. 2016s 2016s 2.4. Executing PROC_INIT pass (extract init attributes). 2016s 2016s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2016s 2016s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2016s Converted 0 switches. 2016s 2016s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2016s Creating decoders for process `\m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'. 2016s 2016s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2016s 2016s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2016s 2016s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2016s 2016s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Removing empty process `m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'. 2016s Cleaned up 0 empty switches. 2016s 2016s 2.12. Executing OPT_EXPR pass (perform const folding). 2016s Optimizing module m. 2016s Removed 0 unused cells and 1 unused wires. 2016s 2016s -- Writing to `yosys-roundtrip-bin_unsigned-2.v' using backend `verilog' -- 2016s 2016s 3. Executing Verilog backend. 2016s 2016s 3.1. Executing BMUXMAP pass. 2016s 2016s 3.2. Executing DEMUXMAP pass. 2016s Dumping module `\m'. 2016s 2016s End of script. Logfile hash: dc9f56cb10, CPU: user 0.01s system 0.00s, MEM: 9.54 MB peak 2016s Yosys 0.33 (git sha1 2584903a060) 2016s Time spent: 27% 1x clean (0 sec), 19% 1x opt_expr (0 sec), ... 2016s + diff yosys-roundtrip-bin_unsigned-1.v yosys-roundtrip-bin_unsigned-2.v 2016s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned roundtrip.v roundtrip_tb.v 2016s + ./iverilog-roundtrip-bin_unsigned 2016s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned-1 yosys-roundtrip-bin_unsigned-1.v roundtrip_tb.v 2016s + ./iverilog-roundtrip-bin_unsigned-1 2016s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned-2 yosys-roundtrip-bin_unsigned-2.v roundtrip_tb.v 2016s + ./iverilog-roundtrip-bin_unsigned-1 2016s + diff iverilog-roundtrip-bin_unsigned.log iverilog-roundtrip-bin_unsigned-1.log 2016s + diff iverilog-roundtrip-bin_unsigned-1.log iverilog-roundtrip-bin_unsigned-2.log 2016s + test_roundtrip bin_signed -DBASE_HEX -DSIGN=signed 2016s + local subtest=bin_signed 2016s + shift 2016s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-bin_signed-1.v 2016s 2016s /----------------------------------------------------------------------------\ 2016s | | 2016s | yosys -- Yosys Open SYnthesis Suite | 2016s | | 2016s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2016s | | 2016s | Permission to use, copy, modify, and/or distribute this software for any | 2016s | purpose with or without fee is hereby granted, provided that the above | 2016s | copyright notice and this permission notice appear in all copies. | 2016s | | 2016s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2016s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2016s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2016s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2016s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2016s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2016s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2016s | | 2016s \----------------------------------------------------------------------------/ 2016s 2016s Yosys 0.33 (git sha1 2584903a060) 2016s 2016s 2016s -- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -- 2016s 2016s 1. Executing Verilog-2005 frontend: roundtrip.v 2016s Parsing Verilog input from `roundtrip.v' to AST representation. 2016s Generating RTLIL representation for module `\m'. 2016s Successfully finished Verilog frontend. 2016s 2016s 2. Executing PROC pass (convert processes to netlists). 2016s 2016s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Cleaned up 0 empty switches. 2016s 2016s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2016s Removed a total of 0 dead cases. 2016s 2016s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2016s Removed 1 redundant assignment. 2016s Promoted 1 assignment to connection. 2016s 2016s 2.4. Executing PROC_INIT pass (extract init attributes). 2016s 2016s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2016s 2016s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2016s Converted 0 switches. 2016s 2016s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2016s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2016s 2016s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2016s 2016s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2016s 2016s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2016s 2016s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Removing empty process `m.$proc$roundtrip.v:3$1'. 2016s Cleaned up 0 empty switches. 2016s 2016s 2.12. Executing OPT_EXPR pass (perform const folding). 2016s Optimizing module m. 2016s Removed 0 unused cells and 1 unused wires. 2016s 2016s -- Writing to `yosys-roundtrip-bin_signed-1.v' using backend `verilog' -- 2016s 2016s 3. Executing Verilog backend. 2016s 2016s 3.1. Executing BMUXMAP pass. 2016s 2016s 3.2. Executing DEMUXMAP pass. 2016s Dumping module `\m'. 2016s 2016s End of script. Logfile hash: 7709253822, CPU: user 0.01s system 0.00s, MEM: 9.52 MB peak 2016s Yosys 0.33 (git sha1 2584903a060) 2016s Time spent: 28% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... 2016s + ../../yosys -p 'read_verilog yosys-roundtrip-bin_signed-1.v; proc; clean' -o yosys-roundtrip-bin_signed-2.v 2016s 2016s /----------------------------------------------------------------------------\ 2016s | | 2016s | yosys -- Yosys Open SYnthesis Suite | 2016s | | 2016s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2016s | | 2016s | Permission to use, copy, modify, and/or distribute this software for any | 2016s | purpose with or without fee is hereby granted, provided that the above | 2016s | copyright notice and this permission notice appear in all copies. | 2016s | | 2016s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2016s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2016s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2016s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2016s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2016s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2016s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2016s | | 2016s \----------------------------------------------------------------------------/ 2016s 2016s Yosys 0.33 (git sha1 2584903a060) 2016s 2016s 2016s -- Running command `read_verilog yosys-roundtrip-bin_signed-1.v; proc; clean' -- 2016s 2016s 1. Executing Verilog-2005 frontend: yosys-roundtrip-bin_signed-1.v 2016s Parsing Verilog input from `yosys-roundtrip-bin_signed-1.v' to AST representation. 2016s Generating RTLIL representation for module `\m'. 2016s Successfully finished Verilog frontend. 2016s 2016s 2. Executing PROC pass (convert processes to netlists). 2016s 2016s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'. 2016s Cleaned up 1 empty switch. 2016s 2016s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2016s Removed a total of 0 dead cases. 2016s 2016s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2016s Removed 1 redundant assignment. 2016s Promoted 1 assignment to connection. 2016s 2016s 2.4. Executing PROC_INIT pass (extract init attributes). 2016s 2016s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2016s 2016s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2016s Converted 0 switches. 2016s 2016s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2016s Creating decoders for process `\m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'. 2016s 2016s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2016s 2016s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2016s 2016s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2016s 2016s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Removing empty process `m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'. 2016s Cleaned up 0 empty switches. 2016s 2016s 2.12. Executing OPT_EXPR pass (perform const folding). 2016s Optimizing module m. 2016s Removed 0 unused cells and 1 unused wires. 2016s 2016s -- Writing to `yosys-roundtrip-bin_signed-2.v' using backend `verilog' -- 2016s 2016s 3. Executing Verilog backend. 2016s 2016s 3.1. Executing BMUXMAP pass. 2016s 2016s 3.2. Executing DEMUXMAP pass. 2016s Dumping module `\m'. 2016s 2016s End of script. Logfile hash: 7e2d8271c4, CPU: user 0.01s system 0.00s, MEM: 9.52 MB peak 2016s Yosys 0.33 (git sha1 2584903a060) 2016s Time spent: 28% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... 2016s + diff yosys-roundtrip-bin_signed-1.v yosys-roundtrip-bin_signed-2.v 2016s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed roundtrip.v roundtrip_tb.v 2016s + ./iverilog-roundtrip-bin_signed 2016s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed-1 yosys-roundtrip-bin_signed-1.v roundtrip_tb.v 2016s + ./iverilog-roundtrip-bin_signed-1 2016s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed-2 yosys-roundtrip-bin_signed-2.v roundtrip_tb.v 2016s + ./iverilog-roundtrip-bin_signed-1 2016s + diff iverilog-roundtrip-bin_signed.log iverilog-roundtrip-bin_signed-1.log 2016s + diff iverilog-roundtrip-bin_signed-1.log iverilog-roundtrip-bin_signed-2.log 2016s + test_cxxrtl always_full 2016s + local subtest=always_full 2016s + shift 2016s + ../../yosys -p 'read_verilog always_full.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_full.cc' 2016s 2016s /----------------------------------------------------------------------------\ 2016s | | 2016s | yosys -- Yosys Open SYnthesis Suite | 2016s | | 2016s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2016s | | 2016s | Permission to use, copy, modify, and/or distribute this software for any | 2016s | purpose with or without fee is hereby granted, provided that the above | 2016s | copyright notice and this permission notice appear in all copies. | 2016s | | 2016s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2016s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2016s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2016s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2016s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2016s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2016s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2016s | | 2016s \----------------------------------------------------------------------------/ 2016s 2016s Yosys 0.33 (git sha1 2584903a060) 2016s 2016s 2016s -- Running command `read_verilog always_full.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_full.cc' -- 2016s 2016s 1. Executing Verilog-2005 frontend: always_full.v 2016s Parsing Verilog input from `always_full.v' to AST representation. 2016s Generating RTLIL representation for module `\always_full'. 2016s Successfully finished Verilog frontend. 2016s 2016s 2. Executing PROC pass (convert processes to netlists). 2016s 2016s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Cleaned up 0 empty switches. 2016s 2016s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2016s Removed a total of 0 dead cases. 2016s 2016s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2016s Removed 207 redundant assignments. 2016s Promoted 207 assignments to connections. 2016s 2016s 2.4. Executing PROC_INIT pass (extract init attributes). 2016s 2016s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2016s 2016s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2016s Converted 0 switches. 2016s 2016s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2016s Creating decoders for process `\always_full.$proc$always_full.v:3$1'. 2016s 2016s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2016s 2016s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2016s 2016s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2016s 2016s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Removing empty process `always_full.$proc$always_full.v:3$1'. 2016s Cleaned up 0 empty switches. 2016s 2016s 2.12. Executing OPT_EXPR pass (perform const folding). 2016s Optimizing module always_full. 2016s Removed 0 unused cells and 207 unused wires. 2016s 2016s 3. Executing CXXRTL backend. 2016s 2016s 3.1. Executing HIERARCHY pass (managing design hierarchy). 2016s 2016s 3.1.1. Finding top of design hierarchy.. 2016s root of 0 design levels: always_full 2016s Automatically selected always_full as design top module. 2016s 2016s 3.1.2. Analyzing design hierarchy.. 2016s Top module: \always_full 2016s 2016s 3.1.3. Analyzing design hierarchy.. 2016s Top module: \always_full 2016s Removed 0 unused modules. 2016s 2016s 3.2. Executing FLATTEN pass (flatten design). 2016s 2016s 3.3. Executing PROC pass (convert processes to netlists). 2016s 2016s 3.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Cleaned up 0 empty switches. 2016s 2016s 3.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2016s Removed a total of 0 dead cases. 2016s 2016s 3.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2016s Removed 0 redundant assignments. 2016s Promoted 0 assignments to connections. 2016s 2016s 3.3.4. Executing PROC_INIT pass (extract init attributes). 2016s 2016s 3.3.5. Executing PROC_ARST pass (detect async resets in processes). 2016s 2016s 3.3.6. Executing PROC_ROM pass (convert switches to ROMs). 2016s Converted 0 switches. 2016s 2016s 3.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2016s 2016s 3.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2016s 2016s 3.3.9. Executing PROC_DFF pass (convert process syncs to FFs). 2016s 2016s 3.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2016s 2016s 3.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2016s Cleaned up 0 empty switches. 2016s 2016s 3.3.12. Executing OPT_EXPR pass (perform const folding). 2016s Optimizing module always_full. 2016s 2016s 2016s 2016s End of script. Logfile hash: 6abd135c0a, CPU: user 0.02s system 0.00s, MEM: 10.79 MB peak 2016s Yosys 0.33 (git sha1 2584903a060) 2016s Time spent: 27% 2x read_verilog (0 sec), 21% 2x opt_expr (0 sec), ... 2016s + gcc -std=c++11 -o yosys-always_full -I../.. always_full_tb.cc -lstdc++ 2017s + ./yosys-always_full 2017s + iverilog -o iverilog-always_full always_full.v always_full_tb.v 2017s + ./iverilog-always_full 2017s + grep -v '\$finish called' 2017s + diff iverilog-always_full.log yosys-always_full.log 2017s + test_cxxrtl always_comb 2017s + local subtest=always_comb 2017s + shift 2017s + ../../yosys -p 'read_verilog always_comb.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_comb.cc' 2017s 2017s /----------------------------------------------------------------------------\ 2017s | | 2017s | yosys -- Yosys Open SYnthesis Suite | 2017s | | 2017s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2017s | | 2017s | Permission to use, copy, modify, and/or distribute this software for any | 2017s | purpose with or without fee is hereby granted, provided that the above | 2017s | copyright notice and this permission notice appear in all copies. | 2017s | | 2017s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2017s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2017s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2017s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2017s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2017s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2017s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2017s | | 2017s \----------------------------------------------------------------------------/ 2017s 2017s Yosys 0.33 (git sha1 2584903a060) 2017s 2017s 2017s -- Running command `read_verilog always_comb.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_comb.cc' -- 2017s 2017s 1. Executing Verilog-2005 frontend: always_comb.v 2017s Parsing Verilog input from `always_comb.v' to AST representation. 2017s Generating RTLIL representation for module `\top'. 2017s Generating RTLIL representation for module `\sub'. 2017s Successfully finished Verilog frontend. 2017s 2017s 2. Executing PROC pass (convert processes to netlists). 2017s 2017s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2017s Cleaned up 0 empty switches. 2017s 2017s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2017s Removed a total of 0 dead cases. 2017s 2017s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2017s Removed 0 redundant assignments. 2017s Promoted 4 assignments to connections. 2017s 2017s 2.4. Executing PROC_INIT pass (extract init attributes). 2017s Found init rule in `\top.$proc$always_comb.v:3$13'. 2017s Set init value: \b = 1'0 2017s Found init rule in `\top.$proc$always_comb.v:2$12'. 2017s Set init value: \a = 1'0 2017s 2017s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2017s 2017s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2017s Converted 0 switches. 2017s 2017s 2017s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2017s Creating decoders for process `\sub.$proc$always_comb.v:23$15'. 2017s 1/1: $display$always_comb.v:23$19_EN 2017s Creating decoders for process `\top.$proc$always_comb.v:3$13'. 2017s Creating decoders for process `\top.$proc$always_comb.v:2$12'. 2017s Creating decoders for process `\top.$proc$always_comb.v:8$1'. 2017s 2017s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2017s 2017s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2017s Creating register for signal `\top.\a' using process `\top.$proc$always_comb.v:8$1'. 2017s created $dff cell `$procdff$22' with positive edge clock. 2017s Creating register for signal `\top.\b' using process `\top.$proc$always_comb.v:8$1'. 2017s created $dff cell `$procdff$23' with positive edge clock. 2017s 2017s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2017s 2017s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2017s Found and cleaned up 1 empty switch in `\sub.$proc$always_comb.v:23$15'. 2017s Removing empty process `sub.$proc$always_comb.v:23$15'. 2017s Removing empty process `top.$proc$always_comb.v:3$13'. 2017s Removing empty process `top.$proc$always_comb.v:2$12'. 2017s Removing empty process `top.$proc$always_comb.v:8$1'. 2017s Cleaned up 1 empty switch. 2017s 2017s 2.12. Executing OPT_EXPR pass (perform const folding). 2017s Optimizing module sub. 2017s Optimizing module top. 2017s Removed 0 unused cells and 7 unused wires. 2017s 2017s 3. Executing CXXRTL backend. 2017s 2017s 3.1. Executing HIERARCHY pass (managing design hierarchy). 2017s 2017s 3.1.1. Finding top of design hierarchy.. 2017s root of 0 design levels: sub 2017s root of 1 design levels: top 2017s Automatically selected top as design top module. 2017s 2017s 3.1.2. Analyzing design hierarchy.. 2017s Top module: \top 2017s Used module: \sub 2017s 2017s 3.1.3. Analyzing design hierarchy.. 2017s Top module: \top 2017s Used module: \sub 2017s Removed 0 unused modules. 2017s 2017s 3.2. Executing FLATTEN pass (flatten design). 2017s Deleting now unused module sub. 2017s 2017s 2017s 3.3. Executing PROC pass (convert processes to netlists). 2017s 2017s 3.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2017s Cleaned up 0 empty switches. 2017s 2017s 3.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2017s Removed a total of 0 dead cases. 2017s 2017s 3.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2017s Removed 0 redundant assignments. 2017s Promoted 0 assignments to connections. 2017s 2017s 3.3.4. Executing PROC_INIT pass (extract init attributes). 2017s 2017s 3.3.5. Executing PROC_ARST pass (detect async resets in processes). 2017s 2017s 3.3.6. Executing PROC_ROM pass (convert switches to ROMs). 2017s Converted 0 switches. 2017s 2017s 3.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2017s 2017s 3.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2017s 2017s 3.3.9. Executing PROC_DFF pass (convert process syncs to FFs). 2017s 2017s 3.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2017s 2017s 3.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2017s Cleaned up 0 empty switches. 2017s 2017s 3.3.12. Executing OPT_EXPR pass (perform const folding). 2017s Optimizing module top. 2017s + gcc -std=c++11 -o yosys-always_comb -I../.. always_comb_tb.cc -lstdc++ 2017s 2017s 2017s 2017s End of script. Logfile hash: 03fe26efda, CPU: user 0.01s system 0.00s, MEM: 10.04 MB peak 2017s Yosys 0.33 (git sha1 2584903a060) 2017s Time spent: 29% 2x opt_expr (0 sec), 19% 1x clean (0 sec), ... 2018s + ./yosys-always_comb 2018s + iverilog -o iverilog-always_comb always_comb.v always_comb_tb.v 2018s + ./iverilog-always_comb 2018s + grep -v '\$finish called' 2018s + diff iverilog-always_comb.log yosys-always_comb.log 2018s + ../../yosys -p 'read_verilog always_full.v; prep; clean' -o yosys-always_full-1.v 2018s 2018s /----------------------------------------------------------------------------\ 2018s | | 2018s | yosys -- Yosys Open SYnthesis Suite | 2018s | | 2018s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2018s | | 2018s | Permission to use, copy, modify, and/or distribute this software for any | 2018s | purpose with or without fee is hereby granted, provided that the above | 2018s | copyright notice and this permission notice appear in all copies. | 2018s | | 2018s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2018s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2018s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2018s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2018s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2018s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2018s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2018s | | 2018s \----------------------------------------------------------------------------/ 2018s 2018s Yosys 0.33 (git sha1 2584903a060) 2018s 2018s 2018s -- Running command `read_verilog always_full.v; prep; clean' -- 2018s 2018s 1. Executing Verilog-2005 frontend: always_full.v 2018s Parsing Verilog input from `always_full.v' to AST representation. 2018s Generating RTLIL representation for module `\always_full'. 2018s Successfully finished Verilog frontend. 2018s 2018s 2. Executing PREP pass. 2018s 2018s 2.1. Executing HIERARCHY pass (managing design hierarchy). 2018s 2018s 2.2. Executing PROC pass (convert processes to netlists). 2018s 2018s 2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2018s Cleaned up 0 empty switches. 2018s 2018s 2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2018s Removed a total of 0 dead cases. 2018s 2018s 2.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2018s Removed 207 redundant assignments. 2018s Promoted 207 assignments to connections. 2018s 2018s 2.2.4. Executing PROC_INIT pass (extract init attributes). 2018s 2018s 2.2.5. Executing PROC_ARST pass (detect async resets in processes). 2018s 2018s 2.2.6. Executing PROC_ROM pass (convert switches to ROMs). 2018s Converted 0 switches. 2018s 2018s 2.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2018s Creating decoders for process `\always_full.$proc$always_full.v:3$1'. 2018s 2018s 2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2018s 2018s 2.2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2018s 2018s 2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2018s 2018s 2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2018s Removing empty process `always_full.$proc$always_full.v:3$1'. 2018s Cleaned up 0 empty switches. 2018s 2018s 2.2.12. Executing OPT_EXPR pass (perform const folding). 2018s Optimizing module always_full. 2018s 2018s 2.3. Executing OPT_EXPR pass (perform const folding). 2018s Optimizing module always_full. 2018s 2018s 2.4. Executing OPT_CLEAN pass (remove unused cells and wires). 2018s Finding unused cells or wires in module \always_full.. 2018s Removed 0 unused cells and 207 unused wires. 2018s 2018s 2018s 2.5. Executing CHECK pass (checking for obvious problems). 2018s Checking module always_full... 2018s Found and reported 0 problems. 2018s 2018s 2.6. Executing OPT pass (performing simple optimizations). 2018s 2018s 2.6.1. Executing OPT_EXPR pass (perform const folding). 2018s Optimizing module always_full. 2018s 2018s 2.6.2. Executing OPT_MERGE pass (detect identical cells). 2018s Finding identical cells in module `\always_full'. 2018s Removed a total of 0 cells. 2018s 2018s 2.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 2018s Running muxtree optimizer on module \always_full.. 2018s Creating internal representation of mux trees. 2018s No muxes found in this module. 2018s Removed 0 multiplexer ports. 2018s 2018s 2.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 2018s Optimizing cells in module \always_full. 2018s Performed a total of 0 changes. 2018s 2018s 2.6.5. Executing OPT_MERGE pass (detect identical cells). 2018s Finding identical cells in module `\always_full'. 2018s Removed a total of 0 cells. 2018s 2018s 2.6.6. Executing OPT_CLEAN pass (remove unused cells and wires). 2018s Finding unused cells or wires in module \always_full.. 2018s 2018s 2.6.7. Executing OPT_EXPR pass (perform const folding). 2018s Optimizing module always_full. 2018s 2018s 2.6.8. Finished OPT passes. (There is nothing left to do.) 2018s 2018s 2.7. Executing WREDUCE pass (reducing word size of cells). 2018s 2018s 2.8. Executing OPT_CLEAN pass (remove unused cells and wires). 2018s Finding unused cells or wires in module \always_full.. 2018s 2018s 2.9. Executing MEMORY_COLLECT pass (generating $mem cells). 2018s 2018s 2.10. Executing OPT pass (performing simple optimizations). 2018s 2018s 2.10.1. Executing OPT_EXPR pass (perform const folding). 2018s Optimizing module always_full. 2018s 2018s 2.10.2. Executing OPT_MERGE pass (detect identical cells). 2018s Finding identical cells in module `\always_full'. 2018s Removed a total of 0 cells. 2018s 2018s 2.10.3. Executing OPT_CLEAN pass (remove unused cells and wires). 2018s Finding unused cells or wires in module \always_full.. 2018s 2018s 2.10.4. Finished fast OPT passes. 2018s 2018s 2.11. Printing statistics. 2018s 2018s === always_full === 2018s 2018s Number of wires: 1 2018s Number of wire bits: 1 2018s Number of public wires: 1 2018s Number of public wire bits: 1 2018s Number of memories: 0 2018s Number of memory bits: 0 2018s Number of processes: 0 2018s Number of cells: 207 2018s $print 207 2018s 2018s 2.12. Executing CHECK pass (checking for obvious problems). 2018s Checking module always_full... 2018s Found and reported 0 problems. 2018s 2018s -- Writing to `yosys-always_full-1.v' using backend `verilog' -- 2018s 2018s 3. Executing Verilog backend. 2018s 2018s 3.1. Executing BMUXMAP pass. 2018s 2018s 3.2. Executing DEMUXMAP pass. 2018s Dumping module `\always_full'. 2018s 2018s End of script. Logfile hash: cfd5b76053, CPU: user 0.06s system 0.00s, MEM: 10.91 MB peak 2018s Yosys 0.33 (git sha1 2584903a060) 2018s Time spent: 20% 5x opt_expr (0 sec), 20% 4x opt_clean (0 sec), ... 2018s + iverilog -o iverilog-always_full-1 yosys-always_full-1.v always_full_tb.v 2018s + ./iverilog-always_full-1 2018s + grep -v '\$finish called' 2018s + diff iverilog-always_full.log iverilog-always_full-1.log 2018s + ../../yosys -p 'read_verilog display_lm.v' 2018s + ../../yosys -p 'read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc' 2018s 2018s /----------------------------------------------------------------------------\ 2018s | | 2018s | yosys -- Yosys Open SYnthesis Suite | 2018s | | 2018s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2018s | | 2018s | Permission to use, copy, modify, and/or distribute this software for any | 2018s | purpose with or without fee is hereby granted, provided that the above | 2018s | copyright notice and this permission notice appear in all copies. | 2018s | | 2018s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2018s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2018s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2018s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2018s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2018s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2018s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2018s | | 2018s \----------------------------------------------------------------------------/ 2018s 2018s Yosys 0.33 (git sha1 2584903a060) 2018s 2018s 2018s -- Running command `read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc' -- 2018s 2018s 1. Executing Verilog-2005 frontend: display_lm.v 2018s Parsing Verilog input from `display_lm.v' to AST representation. 2018s Generating RTLIL representation for module `\top'. 2018s Generating RTLIL representation for module `\mid'. 2018s Generating RTLIL representation for module `\bot'. 2018s %l: \bot 2018s %m: \bot 2018s Successfully finished Verilog frontend. 2018s 2018s 2. Executing CXXRTL backend. 2018s 2018s 2.1. Executing HIERARCHY pass (managing design hierarchy). 2018s 2018s 2.1.1. Finding top of design hierarchy.. 2018s root of 0 design levels: bot 2018s root of 1 design levels: mid 2018s root of 2 design levels: top 2018s Automatically selected top as design top module. 2018s 2018s 2.1.2. Analyzing design hierarchy.. 2018s Top module: \top 2018s Used module: \mid 2018s Used module: \bot 2018s 2018s 2.1.3. Analyzing design hierarchy.. 2018s Top module: \top 2018s Used module: \mid 2018s Used module: \bot 2018s Removed 0 unused modules. 2018s 2018s 2.2. Executing FLATTEN pass (flatten design). 2018s Deleting now unused module bot. 2018s Deleting now unused module mid. 2018s 2018s 2018s 2.3. Executing PROC pass (convert processes to netlists). 2018s 2018s 2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2018s Removing empty process `top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:0$3'. 2018s Cleaned up 0 empty switches. 2018s 2018s 2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2018s Removed a total of 0 dead cases. 2018s 2018s 2.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2018s Removed 1 redundant assignment. 2018s Promoted 1 assignment to connection. 2018s 2018s 2.3.4. Executing PROC_INIT pass (extract init attributes). 2018s 2018s 2.3.5. Executing PROC_ARST pass (detect async resets in processes). 2018s 2018s 2.3.6. Executing PROC_ROM pass (convert switches to ROMs). 2018s Converted 0 switches. 2018s 2018s 2.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2018s Creating decoders for process `\top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:11$1'. 2018s 2018s 2.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2018s 2018s 2.3.9. Executing PROC_DFF pass (convert process syncs to FFs). 2018s 2018s 2.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2018s 2018s 2.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2018s Removing empty process `top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:11$1'. 2018s Cleaned up 0 empty switches. 2018s 2018s 2.3.12. Executing OPT_EXPR pass (perform const folding). 2018s Optimizing module top. 2018s 2018s 2018s 2018s End of script. Logfile hash: 1b689717a7, CPU: user 0.01s system 0.00s, MEM: 9.79 MB peak 2018s Yosys 0.33 (git sha1 2584903a060) 2018s Time spent: 34% 1x opt_expr (0 sec), 16% 2x read_verilog (0 sec), ... 2018s + gcc -std=c++11 -o yosys-display_lm_cc -I../.. display_lm_tb.cc -lstdc++ 2019s + ./yosys-display_lm_cc 2019s %l: \bot 2019s %m: \bot 2019s + for log in yosys-display_lm.log yosys-display_lm_cc.log 2019s + grep '^%l: \\bot$' yosys-display_lm.log 2019s + grep '^%m: \\bot$' yosys-display_lm.log 2019s + for log in yosys-display_lm.log yosys-display_lm_cc.log 2019s + grep '^%l: \\bot$' yosys-display_lm_cc.log 2019s %l: \bot 2019s %m: \bot 2019s + grep '^%m: \\bot$' yosys-display_lm_cc.log 2019s 2019s Passed "make test". 2019s 2019s autopkgtest [18:15:09]: test yosys-testsuite: -----------------------] 2020s autopkgtest [18:15:10]: test yosys-testsuite: - - - - - - - - - - results - - - - - - - - - - 2020s yosys-testsuite PASS 2021s autopkgtest [18:15:11]: test ice: preparing testbed 2134s autopkgtest [18:17:04]: testbed dpkg architecture: arm64 2134s autopkgtest [18:17:04]: testbed apt version: 2.9.33 2135s autopkgtest [18:17:05]: @@@@@@@@@@@@@@@@@@@@ test bed setup 2135s autopkgtest [18:17:05]: testbed release detected to be: plucky 2136s autopkgtest [18:17:06]: updating testbed package index (apt update) 2136s Get:1 http://ftpmaster.internal/ubuntu plucky-proposed InRelease [126 kB] 2137s Hit:2 http://ftpmaster.internal/ubuntu plucky InRelease 2137s Hit:3 http://ftpmaster.internal/ubuntu plucky-updates InRelease 2137s Hit:4 http://ftpmaster.internal/ubuntu plucky-security InRelease 2137s Get:5 http://ftpmaster.internal/ubuntu plucky-proposed/multiverse Sources [15.8 kB] 2137s Get:6 http://ftpmaster.internal/ubuntu plucky-proposed/universe Sources [379 kB] 2137s Get:7 http://ftpmaster.internal/ubuntu plucky-proposed/main Sources [99.7 kB] 2137s Get:8 http://ftpmaster.internal/ubuntu plucky-proposed/main arm64 Packages [111 kB] 2137s Get:9 http://ftpmaster.internal/ubuntu plucky-proposed/main arm64 c-n-f Metadata [1856 B] 2137s Get:10 http://ftpmaster.internal/ubuntu plucky-proposed/restricted arm64 c-n-f Metadata [116 B] 2137s Get:11 http://ftpmaster.internal/ubuntu plucky-proposed/universe arm64 Packages [324 kB] 2138s Get:12 http://ftpmaster.internal/ubuntu plucky-proposed/universe arm64 c-n-f Metadata [14.7 kB] 2138s Get:13 http://ftpmaster.internal/ubuntu plucky-proposed/multiverse arm64 Packages [4948 B] 2138s Get:14 http://ftpmaster.internal/ubuntu plucky-proposed/multiverse arm64 c-n-f Metadata [268 B] 2138s Fetched 1078 kB in 2s (696 kB/s) 2139s Reading package lists... 2140s + lsb_release --codename --short 2140s + RELEASE=plucky 2140s + cat 2140s + [ plucky != trusty ] 2140s + DEBIAN_FRONTEND=noninteractive eatmydata apt-get -y --allow-downgrades -o Dpkg::Options::=--force-confnew dist-upgrade 2140s Reading package lists... 2140s Building dependency tree... 2140s Reading state information... 2140s Calculating upgrade... 2141s Calculating upgrade... 2141s The following packages will be upgraded: 2141s pinentry-curses python3-jinja2 strace 2141s 3 upgraded, 0 newly installed, 0 to remove and 0 not upgraded. 2141s Need to get 647 kB of archives. 2141s After this operation, 11.3 kB of additional disk space will be used. 2141s Get:1 http://ftpmaster.internal/ubuntu plucky/main arm64 strace arm64 6.13+ds-1ubuntu1 [499 kB] 2142s Get:2 http://ftpmaster.internal/ubuntu plucky/main arm64 pinentry-curses arm64 1.3.1-2ubuntu3 [39.2 kB] 2142s Get:3 http://ftpmaster.internal/ubuntu plucky/main arm64 python3-jinja2 all 3.1.5-2ubuntu1 [109 kB] 2142s Fetched 647 kB in 1s (702 kB/s) 2143s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 117701 files and directories currently installed.) 2143s Preparing to unpack .../strace_6.13+ds-1ubuntu1_arm64.deb ... 2143s Unpacking strace (6.13+ds-1ubuntu1) over (6.11-0ubuntu1) ... 2143s Preparing to unpack .../pinentry-curses_1.3.1-2ubuntu3_arm64.deb ... 2143s Unpacking pinentry-curses (1.3.1-2ubuntu3) over (1.3.1-2ubuntu2) ... 2143s Preparing to unpack .../python3-jinja2_3.1.5-2ubuntu1_all.deb ... 2143s Unpacking python3-jinja2 (3.1.5-2ubuntu1) over (3.1.5-2) ... 2143s Setting up pinentry-curses (1.3.1-2ubuntu3) ... 2143s Setting up python3-jinja2 (3.1.5-2ubuntu1) ... 2144s Setting up strace (6.13+ds-1ubuntu1) ... 2144s Processing triggers for man-db (2.13.0-1) ... 2144s + rm /etc/apt/preferences.d/force-downgrade-to-release.pref 2144s + /usr/lib/apt/apt-helper analyze-pattern ?true 2144s + uname -r 2144s + sed s/\./\\./g 2144s + running_kernel_pattern=^linux-.*6\.14\.0-10-generic.* 2145s + apt list ?obsolete 2145s + + tail -n+2 2145s cut -d/ -f1 2145s + grep -v ^linux-.*6\.14\.0-10-generic.* 2146s + obsolete_pkgs=linux-headers-6.11.0-8-generic 2146s linux-headers-6.11.0-8 2146s linux-image-6.11.0-8-generic 2146s linux-modules-6.11.0-8-generic 2146s linux-tools-6.11.0-8-generic 2146s linux-tools-6.11.0-8 2146s + DEBIAN_FRONTEND=noninteractive eatmydata apt-get -y purge --autoremove linux-headers-6.11.0-8-generic linux-headers-6.11.0-8 linux-image-6.11.0-8-generic linux-modules-6.11.0-8-generic linux-tools-6.11.0-8-generic linux-tools-6.11.0-8 2146s Reading package lists... 2146s Building dependency tree... 2146s Reading state information... 2146s Solving dependencies... 2146s The following packages will be REMOVED: 2146s libnsl2* libpython3.12-minimal* libpython3.12-stdlib* libpython3.12t64* 2146s libunwind8* linux-headers-6.11.0-8* linux-headers-6.11.0-8-generic* 2146s linux-image-6.11.0-8-generic* linux-modules-6.11.0-8-generic* 2146s linux-tools-6.11.0-8* linux-tools-6.11.0-8-generic* 2146s 0 upgraded, 0 newly installed, 11 to remove and 5 not upgraded. 2146s After this operation, 267 MB disk space will be freed. 2146s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 117701 files and directories currently installed.) 2146s Removing linux-tools-6.11.0-8-generic (6.11.0-8.8) ... 2146s Removing linux-tools-6.11.0-8 (6.11.0-8.8) ... 2147s Removing libpython3.12t64:arm64 (3.12.9-1) ... 2147s Removing libpython3.12-stdlib:arm64 (3.12.9-1) ... 2147s Removing libnsl2:arm64 (1.3.0-3build3) ... 2147s Removing libpython3.12-minimal:arm64 (3.12.9-1) ... 2147s Removing libunwind8:arm64 (1.6.2-3.1) ... 2147s Removing linux-headers-6.11.0-8-generic (6.11.0-8.8) ... 2147s Removing linux-headers-6.11.0-8 (6.11.0-8.8) ... 2149s Removing linux-image-6.11.0-8-generic (6.11.0-8.8) ... 2149s I: /boot/vmlinuz.old is now a symlink to vmlinuz-6.14.0-10-generic 2149s I: /boot/initrd.img.old is now a symlink to initrd.img-6.14.0-10-generic 2149s /etc/kernel/postrm.d/initramfs-tools: 2149s update-initramfs: Deleting /boot/initrd.img-6.11.0-8-generic 2149s /etc/kernel/postrm.d/zz-flash-kernel: 2149s flash-kernel: Kernel 6.11.0-8-generic has been removed. 2149s flash-kernel: A higher version (6.14.0-10-generic) is still installed, no reflashing required. 2150s /etc/kernel/postrm.d/zz-update-grub: 2150s Sourcing file `/etc/default/grub' 2150s Sourcing file `/etc/default/grub.d/50-cloudimg-settings.cfg' 2150s Generating grub configuration file ... 2150s Found linux image: /boot/vmlinuz-6.14.0-10-generic 2150s Found initrd image: /boot/initrd.img-6.14.0-10-generic 2150s Warning: os-prober will not be executed to detect other bootable partitions. 2150s Systems on them will not be added to the GRUB boot configuration. 2150s Check GRUB_DISABLE_OS_PROBER documentation entry. 2150s Adding boot menu entry for UEFI Firmware Settings ... 2150s done 2150s Removing linux-modules-6.11.0-8-generic (6.11.0-8.8) ... 2150s Processing triggers for libc-bin (2.41-1ubuntu1) ... 2151s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 81650 files and directories currently installed.) 2151s Purging configuration files for linux-image-6.11.0-8-generic (6.11.0-8.8) ... 2151s Purging configuration files for libpython3.12-minimal:arm64 (3.12.9-1) ... 2151s Purging configuration files for linux-modules-6.11.0-8-generic (6.11.0-8.8) ... 2151s + grep -q trusty /etc/lsb-release 2151s + [ ! -d /usr/share/doc/unattended-upgrades ] 2151s + [ ! -d /usr/share/doc/lxd ] 2151s + [ ! -d /usr/share/doc/lxd-client ] 2151s + [ ! -d /usr/share/doc/snapd ] 2151s + type iptables 2151s + cat 2151s + chmod 755 /etc/rc.local 2151s + . /etc/rc.local 2151s + iptables -w -t mangle -A FORWARD -p tcp --tcp-flags SYN,RST SYN -j TCPMSS --clamp-mss-to-pmtu 2151s + iptables -A OUTPUT -d 10.255.255.1/32 -p tcp -j DROP 2151s + iptables -A OUTPUT -d 10.255.255.2/32 -p tcp -j DROP 2151s + uname -m 2151s + [ aarch64 = ppc64le ] 2151s + [ -d /run/systemd/system ] 2151s + systemd-detect-virt --quiet --vm 2151s + mkdir -p /etc/systemd/system/systemd-random-seed.service.d/ 2151s + cat 2151s + grep -q lz4 /etc/initramfs-tools/initramfs.conf 2151s + echo COMPRESS=lz4 2151s autopkgtest [18:17:21]: upgrading testbed (apt dist-upgrade and autopurge) 2151s Reading package lists... 2151s Building dependency tree... 2151s Reading state information... 2152s Calculating upgrade...Starting pkgProblemResolver with broken count: 0 2152s Starting 2 pkgProblemResolver with broken count: 0 2152s Done 2153s Entering ResolveByKeep 2153s 2153s Calculating upgrade... 2153s The following packages will be upgraded: 2153s libc-bin libc-dev-bin libc6 libc6-dev locales 2154s 5 upgraded, 0 newly installed, 0 to remove and 0 not upgraded. 2154s Need to get 9530 kB of archives. 2154s After this operation, 0 B of additional disk space will be used. 2154s Get:1 http://ftpmaster.internal/ubuntu plucky-proposed/main arm64 libc6-dev arm64 2.41-1ubuntu2 [1750 kB] 2155s Get:2 http://ftpmaster.internal/ubuntu plucky-proposed/main arm64 libc-dev-bin arm64 2.41-1ubuntu2 [24.0 kB] 2155s Get:3 http://ftpmaster.internal/ubuntu plucky-proposed/main arm64 libc6 arm64 2.41-1ubuntu2 [2910 kB] 2158s Get:4 http://ftpmaster.internal/ubuntu plucky-proposed/main arm64 libc-bin arm64 2.41-1ubuntu2 [600 kB] 2158s Get:5 http://ftpmaster.internal/ubuntu plucky-proposed/main arm64 locales all 2.41-1ubuntu2 [4246 kB] 2162s Preconfiguring packages ... 2162s Fetched 9530 kB in 8s (1141 kB/s) 2162s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 81647 files and directories currently installed.) 2162s Preparing to unpack .../libc6-dev_2.41-1ubuntu2_arm64.deb ... 2162s Unpacking libc6-dev:arm64 (2.41-1ubuntu2) over (2.41-1ubuntu1) ... 2163s Preparing to unpack .../libc-dev-bin_2.41-1ubuntu2_arm64.deb ... 2163s Unpacking libc-dev-bin (2.41-1ubuntu2) over (2.41-1ubuntu1) ... 2163s Preparing to unpack .../libc6_2.41-1ubuntu2_arm64.deb ... 2163s Unpacking libc6:arm64 (2.41-1ubuntu2) over (2.41-1ubuntu1) ... 2163s Setting up libc6:arm64 (2.41-1ubuntu2) ... 2163s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 81647 files and directories currently installed.) 2163s Preparing to unpack .../libc-bin_2.41-1ubuntu2_arm64.deb ... 2163s Unpacking libc-bin (2.41-1ubuntu2) over (2.41-1ubuntu1) ... 2163s Setting up libc-bin (2.41-1ubuntu2) ... 2163s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 81647 files and directories currently installed.) 2163s Preparing to unpack .../locales_2.41-1ubuntu2_all.deb ... 2163s Unpacking locales (2.41-1ubuntu2) over (2.41-1ubuntu1) ... 2164s Setting up locales (2.41-1ubuntu2) ... 2164s Generating locales (this might take a while)... 2167s en_US.UTF-8... done 2167s Generation complete. 2167s Setting up libc-dev-bin (2.41-1ubuntu2) ... 2167s Setting up libc6-dev:arm64 (2.41-1ubuntu2) ... 2167s Processing triggers for man-db (2.13.0-1) ... 2167s Processing triggers for systemd (257.3-1ubuntu3) ... 2168s Reading package lists... 2168s Building dependency tree... 2168s Reading state information... 2169s Starting pkgProblemResolver with broken count: 0 2169s Starting 2 pkgProblemResolver with broken count: 0 2169s Done 2169s Solving dependencies... 2170s 0 upgraded, 0 newly installed, 0 to remove and 0 not upgraded. 2170s autopkgtest [18:17:40]: rebooting testbed after setup commands that affected boot 2197s Reading package lists... 2197s Building dependency tree... 2197s Reading state information... 2197s Starting pkgProblemResolver with broken count: 0 2197s Starting 2 pkgProblemResolver with broken count: 0 2197s Done 2197s The following NEW packages will be installed: 2197s libtcl8.6 python3-click yosys yosys-abc 2197s 0 upgraded, 4 newly installed, 0 to remove and 0 not upgraded. 2197s Need to get 9770 kB of archives. 2197s After this operation, 32.3 MB of additional disk space will be used. 2197s Get:1 http://ftpmaster.internal/ubuntu plucky/main arm64 libtcl8.6 arm64 8.6.16+dfsg-1 [987 kB] 2199s Get:2 http://ftpmaster.internal/ubuntu plucky/main arm64 python3-click all 8.2.0+0.really.8.1.8-1 [80.0 kB] 2199s Get:3 http://ftpmaster.internal/ubuntu plucky/universe arm64 yosys-abc arm64 0.33-5build2 [5605 kB] 2204s Get:4 http://ftpmaster.internal/ubuntu plucky/universe arm64 yosys arm64 0.33-5build2 [3098 kB] 2207s Fetched 9770 kB in 9s (1063 kB/s) 2207s Selecting previously unselected package libtcl8.6:arm64. 2207s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 81647 files and directories currently installed.) 2207s Preparing to unpack .../libtcl8.6_8.6.16+dfsg-1_arm64.deb ... 2207s Unpacking libtcl8.6:arm64 (8.6.16+dfsg-1) ... 2207s Selecting previously unselected package python3-click. 2207s Preparing to unpack .../python3-click_8.2.0+0.really.8.1.8-1_all.deb ... 2207s Unpacking python3-click (8.2.0+0.really.8.1.8-1) ... 2207s Selecting previously unselected package yosys-abc. 2207s Preparing to unpack .../yosys-abc_0.33-5build2_arm64.deb ... 2207s Unpacking yosys-abc (0.33-5build2) ... 2207s Selecting previously unselected package yosys. 2207s Preparing to unpack .../yosys_0.33-5build2_arm64.deb ... 2207s Unpacking yosys (0.33-5build2) ... 2207s Setting up yosys-abc (0.33-5build2) ... 2207s Setting up python3-click (8.2.0+0.really.8.1.8-1) ... 2208s Setting up libtcl8.6:arm64 (8.6.16+dfsg-1) ... 2208s Setting up yosys (0.33-5build2) ... 2208s Processing triggers for libc-bin (2.41-1ubuntu2) ... 2208s Processing triggers for man-db (2.13.0-1) ... 2223s autopkgtest [18:18:33]: test ice: [----------------------- 2223s 2223s /----------------------------------------------------------------------------\ 2223s | | 2223s | yosys -- Yosys Open SYnthesis Suite | 2223s | | 2223s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2223s | | 2223s | Permission to use, copy, modify, and/or distribute this software for any | 2223s | purpose with or without fee is hereby granted, provided that the above | 2223s | copyright notice and this permission notice appear in all copies. | 2223s | | 2223s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2223s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2223s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2223s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2223s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2223s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2223s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2223s | | 2223s \----------------------------------------------------------------------------/ 2223s 2223s Yosys 0.33 (git sha1 2584903a060) 2223s 2223s 2223s -- Running command `read_verilog debian/tests/design_ice.v; synth_ice40 -blif /tmp/autopkgtest.5LcWtj/autopkgtest_tmp/design_ice.blif' -- 2223s 2223s 1. Executing Verilog-2005 frontend: debian/tests/design_ice.v 2223s Parsing Verilog input from `debian/tests/design_ice.v' to AST representation. 2223s Generating RTLIL representation for module `\design_ice'. 2223s Successfully finished Verilog frontend. 2223s 2223s 2. Executing SYNTH_ICE40 pass. 2223s 2223s 2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v 2224s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation. 2224s Generating RTLIL representation for module `\SB_IO'. 2224s Generating RTLIL representation for module `\SB_GB_IO'. 2224s Generating RTLIL representation for module `\SB_GB'. 2224s Generating RTLIL representation for module `\SB_LUT4'. 2224s Generating RTLIL representation for module `\SB_CARRY'. 2224s Generating RTLIL representation for module `\SB_DFF'. 2224s Generating RTLIL representation for module `\SB_DFFE'. 2224s Generating RTLIL representation for module `\SB_DFFSR'. 2224s Generating RTLIL representation for module `\SB_DFFR'. 2224s Generating RTLIL representation for module `\SB_DFFSS'. 2224s Generating RTLIL representation for module `\SB_DFFS'. 2224s Generating RTLIL representation for module `\SB_DFFESR'. 2224s Generating RTLIL representation for module `\SB_DFFER'. 2224s Generating RTLIL representation for module `\SB_DFFESS'. 2224s Generating RTLIL representation for module `\SB_DFFES'. 2224s Generating RTLIL representation for module `\SB_DFFN'. 2224s Generating RTLIL representation for module `\SB_DFFNE'. 2224s Generating RTLIL representation for module `\SB_DFFNSR'. 2224s Generating RTLIL representation for module `\SB_DFFNR'. 2224s Generating RTLIL representation for module `\SB_DFFNSS'. 2224s Generating RTLIL representation for module `\SB_DFFNS'. 2224s Generating RTLIL representation for module `\SB_DFFNESR'. 2224s Generating RTLIL representation for module `\SB_DFFNER'. 2224s Generating RTLIL representation for module `\SB_DFFNESS'. 2224s Generating RTLIL representation for module `\SB_DFFNES'. 2224s Generating RTLIL representation for module `\SB_RAM40_4K'. 2224s Generating RTLIL representation for module `\SB_RAM40_4KNR'. 2224s Generating RTLIL representation for module `\SB_RAM40_4KNW'. 2224s Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. 2224s Generating RTLIL representation for module `\ICESTORM_LC'. 2224s Generating RTLIL representation for module `\SB_PLL40_CORE'. 2224s Generating RTLIL representation for module `\SB_PLL40_PAD'. 2224s Generating RTLIL representation for module `\SB_PLL40_2_PAD'. 2224s Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. 2224s Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. 2224s Generating RTLIL representation for module `\SB_WARMBOOT'. 2224s Generating RTLIL representation for module `\SB_SPRAM256KA'. 2224s Generating RTLIL representation for module `\SB_HFOSC'. 2224s Generating RTLIL representation for module `\SB_LFOSC'. 2224s Generating RTLIL representation for module `\SB_RGBA_DRV'. 2224s Generating RTLIL representation for module `\SB_LED_DRV_CUR'. 2224s Generating RTLIL representation for module `\SB_RGB_DRV'. 2224s Generating RTLIL representation for module `\SB_I2C'. 2224s Generating RTLIL representation for module `\SB_SPI'. 2224s Generating RTLIL representation for module `\SB_LEDDA_IP'. 2224s Generating RTLIL representation for module `\SB_FILTER_50NS'. 2224s Generating RTLIL representation for module `\SB_IO_I3C'. 2224s Generating RTLIL representation for module `\SB_IO_OD'. 2224s Generating RTLIL representation for module `\SB_MAC16'. 2224s Generating RTLIL representation for module `\ICESTORM_RAM'. 2224s Successfully finished Verilog frontend. 2224s 2224s 2.2. Executing HIERARCHY pass (managing design hierarchy). 2224s 2224s 2.2.1. Finding top of design hierarchy.. 2224s root of 0 design levels: design_ice 2224s Automatically selected design_ice as design top module. 2224s 2224s 2.2.2. Analyzing design hierarchy.. 2224s Top module: \design_ice 2224s 2224s 2.2.3. Analyzing design hierarchy.. 2224s Top module: \design_ice 2224s Removed 0 unused modules. 2224s 2224s 2.3. Executing PROC pass (convert processes to netlists). 2224s 2224s 2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2224s Cleaned up 0 empty switches. 2224s 2224s 2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2224s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243 in module SB_DFFNES. 2224s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236 in module SB_DFFNESS. 2224s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232 in module SB_DFFNER. 2224s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225 in module SB_DFFNESR. 2224s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222 in module SB_DFFNS. 2224s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219 in module SB_DFFNSS. 2224s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216 in module SB_DFFNR. 2224s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213 in module SB_DFFNSR. 2224s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205 in module SB_DFFES. 2224s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198 in module SB_DFFESS. 2224s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194 in module SB_DFFER. 2224s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187 in module SB_DFFESR. 2224s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184 in module SB_DFFS. 2224s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181 in module SB_DFFSS. 2224s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178 in module SB_DFFR. 2224s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175 in module SB_DFFSR. 2224s Marked 1 switch rules as full_case in process $proc$debian/tests/design_ice.v:6$1 in module design_ice. 2224s Removed a total of 0 dead cases. 2224s 2224s 2.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2224s Removed 8 redundant assignments. 2224s Promoted 23 assignments to connections. 2224s 2224s 2.3.4. Executing PROC_INIT pass (extract init attributes). 2224s Found init rule in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$246'. 2224s Set init value: \Q = 1'0 2224s Found init rule in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$242'. 2224s Set init value: \Q = 1'0 2224s Found init rule in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$235'. 2224s Set init value: \Q = 1'0 2224s Found init rule in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$231'. 2224s Set init value: \Q = 1'0 2224s Found init rule in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$224'. 2224s Set init value: \Q = 1'0 2224s Found init rule in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$221'. 2224s Set init value: \Q = 1'0 2224s Found init rule in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$218'. 2224s Set init value: \Q = 1'0 2224s Found init rule in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$215'. 2224s Set init value: \Q = 1'0 2224s Found init rule in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$212'. 2224s Set init value: \Q = 1'0 2224s Found init rule in `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 2224s Set init value: \Q = 1'0 2224s Found init rule in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 2224s Set init value: \Q = 1'0 2224s Found init rule in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$204'. 2224s Set init value: \Q = 1'0 2224s Found init rule in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$197'. 2224s Set init value: \Q = 1'0 2224s Found init rule in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$193'. 2224s Set init value: \Q = 1'0 2224s Found init rule in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$186'. 2224s Set init value: \Q = 1'0 2224s Found init rule in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$183'. 2224s Set init value: \Q = 1'0 2224s Found init rule in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$180'. 2224s Set init value: \Q = 1'0 2224s Found init rule in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$177'. 2224s Set init value: \Q = 1'0 2224s Found init rule in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$174'. 2224s Set init value: \Q = 1'0 2224s Found init rule in `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 2224s Set init value: \Q = 1'0 2224s Found init rule in `\design_ice.$proc$debian/tests/design_ice.v:3$2'. 2224s Set init value: \ready = 1'0 2224s 2224s 2.3.5. Executing PROC_ARST pass (detect async resets in processes). 2224s Found async reset \S in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'. 2224s Found async reset \R in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'. 2224s Found async reset \S in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222'. 2224s Found async reset \R in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216'. 2224s Found async reset \S in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'. 2224s Found async reset \R in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'. 2224s Found async reset \S in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184'. 2224s Found async reset \R in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178'. 2224s 2224s 2.3.6. Executing PROC_ROM pass (convert switches to ROMs). 2224s Converted 0 switches. 2224s 2224s 2224s 2.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2224s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$246'. 2224s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'. 2224s 1/1: $0\Q[0:0] 2224s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$242'. 2224s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236'. 2224s 1/1: $0\Q[0:0] 2224s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$235'. 2224s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'. 2224s 1/1: $0\Q[0:0] 2224s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$231'. 2224s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225'. 2224s 1/1: $0\Q[0:0] 2224s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$224'. 2224s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222'. 2224s 1/1: $0\Q[0:0] 2224s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$221'. 2224s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219'. 2224s 1/1: $0\Q[0:0] 2224s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$218'. 2224s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216'. 2224s 1/1: $0\Q[0:0] 2224s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$215'. 2224s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213'. 2224s 1/1: $0\Q[0:0] 2224s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$212'. 2224s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$211'. 2224s 1/1: $0\Q[0:0] 2224s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 2224s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$209'. 2224s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 2224s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'. 2224s 1/1: $0\Q[0:0] 2224s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$204'. 2224s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198'. 2224s 1/1: $0\Q[0:0] 2224s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$197'. 2224s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'. 2224s 1/1: $0\Q[0:0] 2224s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$193'. 2224s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187'. 2224s 1/1: $0\Q[0:0] 2224s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$186'. 2224s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184'. 2224s 1/1: $0\Q[0:0] 2224s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$183'. 2224s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181'. 2224s 1/1: $0\Q[0:0] 2224s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$180'. 2224s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178'. 2224s 1/1: $0\Q[0:0] 2224s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$177'. 2224s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175'. 2224s 1/1: $0\Q[0:0] 2224s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$174'. 2224s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$173'. 2224s 1/1: $0\Q[0:0] 2224s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 2224s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$171'. 2224s Creating decoders for process `\design_ice.$proc$debian/tests/design_ice.v:3$2'. 2224s Creating decoders for process `\design_ice.$proc$debian/tests/design_ice.v:6$1'. 2224s 1/2: $0\value[0:0] 2224s 2/2: $0\ready[0:0] 2224s 2224s 2.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2224s 2224s 2.3.9. Executing PROC_DFF pass (convert process syncs to FFs). 2224s Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'. 2224s created $adff cell `$procdff$433' with negative edge clock and positive level reset. 2224s Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236'. 2224s created $dff cell `$procdff$434' with negative edge clock. 2224s Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'. 2224s created $adff cell `$procdff$435' with negative edge clock and positive level reset. 2224s Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225'. 2224s created $dff cell `$procdff$436' with negative edge clock. 2224s Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222'. 2224s created $adff cell `$procdff$437' with negative edge clock and positive level reset. 2224s Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219'. 2224s created $dff cell `$procdff$438' with negative edge clock. 2224s Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216'. 2224s created $adff cell `$procdff$439' with negative edge clock and positive level reset. 2224s Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213'. 2224s created $dff cell `$procdff$440' with negative edge clock. 2224s Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$211'. 2224s created $dff cell `$procdff$441' with negative edge clock. 2224s Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$209'. 2224s created $dff cell `$procdff$442' with negative edge clock. 2224s Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'. 2224s created $adff cell `$procdff$443' with positive edge clock and positive level reset. 2224s Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198'. 2224s created $dff cell `$procdff$444' with positive edge clock. 2224s Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'. 2224s created $adff cell `$procdff$445' with positive edge clock and positive level reset. 2224s Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187'. 2224s created $dff cell `$procdff$446' with positive edge clock. 2224s Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184'. 2224s created $adff cell `$procdff$447' with positive edge clock and positive level reset. 2224s Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181'. 2224s created $dff cell `$procdff$448' with positive edge clock. 2224s Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178'. 2224s created $adff cell `$procdff$449' with positive edge clock and positive level reset. 2224s Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175'. 2224s created $dff cell `$procdff$450' with positive edge clock. 2224s Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$173'. 2224s created $dff cell `$procdff$451' with positive edge clock. 2224s Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$171'. 2224s created $dff cell `$procdff$452' with positive edge clock. 2224s Creating register for signal `\design_ice.\ready' using process `\design_ice.$proc$debian/tests/design_ice.v:6$1'. 2224s created $dff cell `$procdff$453' with positive edge clock. 2224s Creating register for signal `\design_ice.\value' using process `\design_ice.$proc$debian/tests/design_ice.v:6$1'. 2224s created $dff cell `$procdff$454' with positive edge clock. 2224s 2224s 2.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2224s 2224s 2.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2224s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$246'. 2224s Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'. 2224s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'. 2224s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$242'. 2224s Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236'. 2224s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236'. 2224s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$235'. 2224s Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'. 2224s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'. 2224s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$231'. 2224s Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225'. 2224s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225'. 2224s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$224'. 2224s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222'. 2224s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$221'. 2224s Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219'. 2224s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219'. 2224s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$218'. 2224s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216'. 2224s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$215'. 2224s Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213'. 2224s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213'. 2224s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$212'. 2224s Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$211'. 2224s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$211'. 2224s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 2224s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$209'. 2224s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 2224s Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'. 2224s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'. 2224s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$204'. 2224s Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198'. 2224s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198'. 2224s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$197'. 2224s Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'. 2224s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'. 2224s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$193'. 2224s Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187'. 2224s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187'. 2224s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$186'. 2224s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184'. 2224s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$183'. 2224s Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181'. 2224s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181'. 2224s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$180'. 2224s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178'. 2224s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$177'. 2224s Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175'. 2224s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175'. 2224s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$174'. 2224s Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$173'. 2224s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$173'. 2224s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 2224s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$171'. 2224s Removing empty process `design_ice.$proc$debian/tests/design_ice.v:3$2'. 2224s Found and cleaned up 1 empty switch in `\design_ice.$proc$debian/tests/design_ice.v:6$1'. 2224s Removing empty process `design_ice.$proc$debian/tests/design_ice.v:6$1'. 2224s Cleaned up 19 empty switches. 2224s 2224s 2.3.12. Executing OPT_EXPR pass (perform const folding). 2224s Optimizing module design_ice. 2224s 2224s 2.4. Executing FLATTEN pass (flatten design). 2224s 2224s 2.5. Executing TRIBUF pass. 2224s 2224s 2.6. Executing DEMINOUT pass (demote inout ports to input or output). 2224s 2224s 2.7. Executing OPT_EXPR pass (perform const folding). 2224s Optimizing module design_ice. 2224s 2224s 2.8. Executing OPT_CLEAN pass (remove unused cells and wires). 2224s Finding unused cells or wires in module \design_ice.. 2224s Removed 0 unused cells and 5 unused wires. 2224s 2224s 2224s 2.9. Executing CHECK pass (checking for obvious problems). 2224s Checking module design_ice... 2224s Found and reported 0 problems. 2224s 2224s 2.10. Executing OPT pass (performing simple optimizations). 2224s 2224s 2.10.1. Executing OPT_EXPR pass (perform const folding). 2224s Optimizing module design_ice. 2224s 2224s 2.10.2. Executing OPT_MERGE pass (detect identical cells). 2224s Finding identical cells in module `\design_ice'. 2224s Removed a total of 0 cells. 2224s 2224s 2.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 2224s Running muxtree optimizer on module \design_ice.. 2224s Creating internal representation of mux trees. 2224s Evaluating internal representation of mux trees. 2224s Replacing known input bits on port B of cell $procmux$431: \ready -> 1'1 2224s Analyzing evaluation results. 2224s Removed 0 multiplexer ports. 2224s 2224s 2224s 2.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 2224s Optimizing cells in module \design_ice. 2224s Optimizing cells in module \design_ice. 2224s Performed a total of 1 changes. 2224s 2224s 2.10.5. Executing OPT_MERGE pass (detect identical cells). 2224s Finding identical cells in module `\design_ice'. 2224s Removed a total of 0 cells. 2224s 2224s 2.10.6. Executing OPT_DFF pass (perform DFF optimizations). 2224s 2224s 2.10.7. Executing OPT_CLEAN pass (remove unused cells and wires). 2224s Finding unused cells or wires in module \design_ice.. 2224s Removed 0 unused cells and 1 unused wires. 2224s 2224s 2224s 2.10.8. Executing OPT_EXPR pass (perform const folding). 2224s Optimizing module design_ice. 2224s 2224s 2.10.9. Rerunning OPT passes. (Maybe there is more to do..) 2224s 2224s 2.10.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 2224s Running muxtree optimizer on module \design_ice.. 2224s Creating internal representation of mux trees. 2224s Evaluating internal representation of mux trees. 2224s Analyzing evaluation results. 2224s Removed 0 multiplexer ports. 2224s 2224s 2224s 2.10.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 2224s Optimizing cells in module \design_ice. 2224s Performed a total of 0 changes. 2224s 2224s 2.10.12. Executing OPT_MERGE pass (detect identical cells). 2224s Finding identical cells in module `\design_ice'. 2224s Removed a total of 0 cells. 2224s 2224s 2.10.13. Executing OPT_DFF pass (perform DFF optimizations). 2224s 2224s 2.10.14. Executing OPT_CLEAN pass (remove unused cells and wires). 2224s Finding unused cells or wires in module \design_ice.. 2224s 2224s 2.10.15. Executing OPT_EXPR pass (perform const folding). 2224s Optimizing module design_ice. 2224s 2224s 2.10.16. Finished OPT passes. (There is nothing left to do.) 2224s 2224s 2.11. Executing FSM pass (extract and optimize FSM). 2224s 2224s 2.11.1. Executing FSM_DETECT pass (finding FSMs in design). 2224s 2224s 2.11.2. Executing FSM_EXTRACT pass (extracting FSM from design). 2224s 2224s 2.11.3. Executing FSM_OPT pass (simple optimizations of FSMs). 2224s 2224s 2.11.4. Executing OPT_CLEAN pass (remove unused cells and wires). 2224s Finding unused cells or wires in module \design_ice.. 2224s 2224s 2.11.5. Executing FSM_OPT pass (simple optimizations of FSMs). 2224s 2224s 2.11.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 2224s 2224s 2.11.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 2224s 2224s 2.11.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 2224s 2224s 2.12. Executing OPT pass (performing simple optimizations). 2224s 2224s 2.12.1. Executing OPT_EXPR pass (perform const folding). 2224s Optimizing module design_ice. 2224s 2224s 2.12.2. Executing OPT_MERGE pass (detect identical cells). 2224s Finding identical cells in module `\design_ice'. 2224s Removed a total of 0 cells. 2224s 2224s 2.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 2224s Running muxtree optimizer on module \design_ice.. 2224s Creating internal representation of mux trees. 2224s Evaluating internal representation of mux trees. 2224s Analyzing evaluation results. 2224s Removed 0 multiplexer ports. 2224s 2224s 2224s 2.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 2224s Optimizing cells in module \design_ice. 2224s Performed a total of 0 changes. 2224s 2224s 2.12.5. Executing OPT_MERGE pass (detect identical cells). 2224s Finding identical cells in module `\design_ice'. 2224s Removed a total of 0 cells. 2224s 2224s 2.12.6. Executing OPT_DFF pass (perform DFF optimizations). 2224s Adding EN signal on $procdff$454 ($dff) from module design_ice (D = \I1, Q = \value). 2224s 2224s 2.12.7. Executing OPT_CLEAN pass (remove unused cells and wires). 2224s Finding unused cells or wires in module \design_ice.. 2224s Removed 1 unused cells and 1 unused wires. 2224s 2224s 2224s 2.12.8. Executing OPT_EXPR pass (perform const folding). 2224s Optimizing module design_ice. 2224s 2224s 2.12.9. Rerunning OPT passes. (Maybe there is more to do..) 2224s 2224s 2.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 2224s Running muxtree optimizer on module \design_ice.. 2224s Creating internal representation of mux trees. 2224s No muxes found in this module. 2224s Removed 0 multiplexer ports. 2224s 2224s 2.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 2224s Optimizing cells in module \design_ice. 2224s Performed a total of 0 changes. 2224s 2224s 2.12.12. Executing OPT_MERGE pass (detect identical cells). 2224s Finding identical cells in module `\design_ice'. 2224s Removed a total of 0 cells. 2224s 2224s 2.12.13. Executing OPT_DFF pass (perform DFF optimizations). 2224s 2224s 2.12.14. Executing OPT_CLEAN pass (remove unused cells and wires). 2224s Finding unused cells or wires in module \design_ice.. 2224s 2224s 2.12.15. Executing OPT_EXPR pass (perform const folding). 2224s Optimizing module design_ice. 2224s 2224s 2.12.16. Finished OPT passes. (There is nothing left to do.) 2224s 2224s 2.13. Executing WREDUCE pass (reducing word size of cells). 2224s 2224s 2.14. Executing PEEPOPT pass (run peephole optimizers). 2224s 2224s 2.15. Executing OPT_CLEAN pass (remove unused cells and wires). 2224s Finding unused cells or wires in module \design_ice.. 2224s 2224s 2.16. Executing SHARE pass (SAT-based resource sharing). 2224s 2224s 2.17. Executing TECHMAP pass (map to technology primitives). 2224s 2224s 2.17.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v 2224s Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation. 2224s Generating RTLIL representation for module `\_90_lut_cmp_'. 2224s Successfully finished Verilog frontend. 2224s 2224s 2.17.2. Continuing TECHMAP pass. 2224s No more expansions possible. 2224s 2224s 2224s 2.18. Executing OPT_EXPR pass (perform const folding). 2224s Optimizing module design_ice. 2224s 2224s 2.19. Executing OPT_CLEAN pass (remove unused cells and wires). 2224s Finding unused cells or wires in module \design_ice.. 2224s 2224s 2.20. Executing ALUMACC pass (create $alu and $macc cells). 2224s Extracting $alu and $macc cells in module design_ice: 2224s created 0 $alu and 0 $macc cells. 2224s 2224s 2.21. Executing OPT pass (performing simple optimizations). 2224s 2224s 2.21.1. Executing OPT_EXPR pass (perform const folding). 2224s Optimizing module design_ice. 2224s 2224s 2.21.2. Executing OPT_MERGE pass (detect identical cells). 2224s Finding identical cells in module `\design_ice'. 2224s Removed a total of 0 cells. 2224s 2224s 2.21.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 2224s Running muxtree optimizer on module \design_ice.. 2224s Creating internal representation of mux trees. 2224s No muxes found in this module. 2224s Removed 0 multiplexer ports. 2224s 2224s 2.21.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 2224s Optimizing cells in module \design_ice. 2224s Performed a total of 0 changes. 2224s 2224s 2.21.5. Executing OPT_MERGE pass (detect identical cells). 2224s Finding identical cells in module `\design_ice'. 2224s Removed a total of 0 cells. 2224s 2224s 2.21.6. Executing OPT_DFF pass (perform DFF optimizations). 2224s 2224s 2.21.7. Executing OPT_CLEAN pass (remove unused cells and wires). 2224s Finding unused cells or wires in module \design_ice.. 2224s 2224s 2.21.8. Executing OPT_EXPR pass (perform const folding). 2224s Optimizing module design_ice. 2224s 2224s 2.21.9. Finished OPT passes. (There is nothing left to do.) 2224s 2224s 2.22. Executing MEMORY pass. 2224s 2224s 2.22.1. Executing OPT_MEM pass (optimize memories). 2224s Performed a total of 0 transformations. 2224s 2224s 2.22.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). 2224s Performed a total of 0 transformations. 2224s 2224s 2.22.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 2224s 2224s 2.22.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 2224s 2224s 2.22.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 2224s 2224s 2.22.6. Executing OPT_CLEAN pass (remove unused cells and wires). 2224s Finding unused cells or wires in module \design_ice.. 2224s 2224s 2.22.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 2224s 2224s 2.22.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). 2224s Performed a total of 0 transformations. 2224s 2224s 2.22.9. Executing OPT_CLEAN pass (remove unused cells and wires). 2224s Finding unused cells or wires in module \design_ice.. 2224s 2224s 2.22.10. Executing MEMORY_COLLECT pass (generating $mem cells). 2224s 2224s 2.23. Executing OPT_CLEAN pass (remove unused cells and wires). 2224s Finding unused cells or wires in module \design_ice.. 2224s 2224s 2.24. Executing MEMORY_LIBMAP pass (mapping memories to cells). 2224s 2224s 2.25. Executing TECHMAP pass (map to technology primitives). 2224s 2224s 2.25.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v 2224s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation. 2224s Generating RTLIL representation for module `\$__ICE40_RAM4K_'. 2224s Successfully finished Verilog frontend. 2224s 2224s 2.25.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/spram_map.v 2224s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/spram_map.v' to AST representation. 2224s Generating RTLIL representation for module `\$__ICE40_SPRAM_'. 2224s Successfully finished Verilog frontend. 2224s 2224s 2.25.3. Continuing TECHMAP pass. 2224s No more expansions possible. 2224s 2224s 2224s 2.26. Executing ICE40_BRAMINIT pass. 2224s 2224s 2.27. Executing OPT pass (performing simple optimizations). 2224s 2224s 2.27.1. Executing OPT_EXPR pass (perform const folding). 2224s Optimizing module design_ice. 2224s 2224s 2.27.2. Executing OPT_MERGE pass (detect identical cells). 2224s Finding identical cells in module `\design_ice'. 2224s Removed a total of 0 cells. 2224s 2224s 2.27.3. Executing OPT_DFF pass (perform DFF optimizations). 2224s 2224s 2.27.4. Executing OPT_CLEAN pass (remove unused cells and wires). 2224s Finding unused cells or wires in module \design_ice.. 2224s 2224s 2.27.5. Finished fast OPT passes. 2224s 2224s 2.28. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 2224s 2224s 2.29. Executing OPT pass (performing simple optimizations). 2224s 2224s 2.29.1. Executing OPT_EXPR pass (perform const folding). 2224s Optimizing module design_ice. 2224s 2224s 2.29.2. Executing OPT_MERGE pass (detect identical cells). 2224s Finding identical cells in module `\design_ice'. 2224s Removed a total of 0 cells. 2224s 2224s 2.29.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 2224s Running muxtree optimizer on module \design_ice.. 2224s Creating internal representation of mux trees. 2224s No muxes found in this module. 2224s Removed 0 multiplexer ports. 2224s 2224s 2.29.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 2224s Optimizing cells in module \design_ice. 2224s Performed a total of 0 changes. 2224s 2224s 2.29.5. Executing OPT_MERGE pass (detect identical cells). 2224s Finding identical cells in module `\design_ice'. 2224s Removed a total of 0 cells. 2224s 2224s 2.29.6. Executing OPT_DFF pass (perform DFF optimizations). 2224s 2224s 2.29.7. Executing OPT_CLEAN pass (remove unused cells and wires). 2224s Finding unused cells or wires in module \design_ice.. 2224s 2224s 2.29.8. Executing OPT_EXPR pass (perform const folding). 2224s Optimizing module design_ice. 2224s 2224s 2.29.9. Finished OPT passes. (There is nothing left to do.) 2224s 2224s 2.30. Executing ICE40_WRAPCARRY pass (wrap carries). 2224s 2224s 2.31. Executing TECHMAP pass (map to technology primitives). 2224s 2224s 2.31.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v 2224s Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation. 2224s Generating RTLIL representation for module `\_90_simplemap_bool_ops'. 2224s Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. 2224s Generating RTLIL representation for module `\_90_simplemap_logic_ops'. 2224s Generating RTLIL representation for module `\_90_simplemap_compare_ops'. 2224s Generating RTLIL representation for module `\_90_simplemap_various'. 2224s Generating RTLIL representation for module `\_90_simplemap_registers'. 2224s Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. 2224s Generating RTLIL representation for module `\_90_shift_shiftx'. 2224s Generating RTLIL representation for module `\_90_fa'. 2224s Generating RTLIL representation for module `\_90_lcu'. 2224s Generating RTLIL representation for module `\_90_alu'. 2224s Generating RTLIL representation for module `\_90_macc'. 2224s Generating RTLIL representation for module `\_90_alumacc'. 2224s Generating RTLIL representation for module `\$__div_mod_u'. 2224s Generating RTLIL representation for module `\$__div_mod_trunc'. 2224s Generating RTLIL representation for module `\_90_div'. 2224s Generating RTLIL representation for module `\_90_mod'. 2224s Generating RTLIL representation for module `\$__div_mod_floor'. 2224s Generating RTLIL representation for module `\_90_divfloor'. 2224s Generating RTLIL representation for module `\_90_modfloor'. 2224s Generating RTLIL representation for module `\_90_pow'. 2224s Generating RTLIL representation for module `\_90_pmux'. 2224s Generating RTLIL representation for module `\_90_demux'. 2224s Generating RTLIL representation for module `\_90_lut'. 2224s Successfully finished Verilog frontend. 2224s 2224s 2.31.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v 2224s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation. 2224s Generating RTLIL representation for module `\_80_ice40_alu'. 2224s Successfully finished Verilog frontend. 2224s 2224s 2.31.3. Continuing TECHMAP pass. 2224s Using extmapper simplemap for cells of type $dffe. 2224s Using extmapper simplemap for cells of type $dff. 2224s No more expansions possible. 2224s 2224s 2224s 2.32. Executing OPT pass (performing simple optimizations). 2224s 2224s 2.32.1. Executing OPT_EXPR pass (perform const folding). 2224s Optimizing module design_ice. 2224s 2224s 2.32.2. Executing OPT_MERGE pass (detect identical cells). 2224s Finding identical cells in module `\design_ice'. 2224s Removed a total of 0 cells. 2224s 2224s 2.32.3. Executing OPT_DFF pass (perform DFF optimizations). 2224s 2224s 2.32.4. Executing OPT_CLEAN pass (remove unused cells and wires). 2224s Finding unused cells or wires in module \design_ice.. 2224s 2224s 2.32.5. Finished fast OPT passes. 2224s 2224s 2.33. Executing ICE40_OPT pass (performing simple optimizations). 2224s 2224s 2.33.1. Running ICE40 specific optimizations. 2224s 2224s 2.33.2. Executing OPT_EXPR pass (perform const folding). 2224s Optimizing module design_ice. 2224s 2224s 2.33.3. Executing OPT_MERGE pass (detect identical cells). 2224s Finding identical cells in module `\design_ice'. 2224s Removed a total of 0 cells. 2224s 2224s 2.33.4. Executing OPT_DFF pass (perform DFF optimizations). 2224s 2224s 2.33.5. Executing OPT_CLEAN pass (remove unused cells and wires). 2224s Finding unused cells or wires in module \design_ice.. 2224s 2224s 2.33.6. Finished OPT passes. (There is nothing left to do.) 2224s 2224s 2.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 2224s 2224s 2.35. Executing TECHMAP pass (map to technology primitives). 2224s 2224s 2.35.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 2224s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 2224s Generating RTLIL representation for module `\$_DFF_N_'. 2224s Generating RTLIL representation for module `\$_DFF_P_'. 2224s Generating RTLIL representation for module `\$_DFFE_NP_'. 2224s Generating RTLIL representation for module `\$_DFFE_PP_'. 2224s Generating RTLIL representation for module `\$_DFF_NP0_'. 2224s Generating RTLIL representation for module `\$_DFF_NP1_'. 2224s Generating RTLIL representation for module `\$_DFF_PP0_'. 2224s Generating RTLIL representation for module `\$_DFF_PP1_'. 2224s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 2224s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 2224s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 2224s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 2224s Generating RTLIL representation for module `\$_SDFF_NP0_'. 2224s Generating RTLIL representation for module `\$_SDFF_NP1_'. 2224s Generating RTLIL representation for module `\$_SDFF_PP0_'. 2224s Generating RTLIL representation for module `\$_SDFF_PP1_'. 2224s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 2224s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 2224s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 2224s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 2224s Successfully finished Verilog frontend. 2224s 2224s 2.35.2. Continuing TECHMAP pass. 2224s Using template \$_DFF_P_ for cells of type $_DFF_P_. 2224s Using template \$_DFFE_PP_ for cells of type $_DFFE_PP_. 2224s No more expansions possible. 2224s 2224s 2224s 2.36. Executing OPT_EXPR pass (perform const folding). 2224s Optimizing module design_ice. 2224s 2224s 2.37. Executing SIMPLEMAP pass (map simple cells to gate primitives). 2224s 2224s 2.38. Executing ICE40_OPT pass (performing simple optimizations). 2224s 2224s 2.38.1. Running ICE40 specific optimizations. 2224s 2224s 2.38.2. Executing OPT_EXPR pass (perform const folding). 2224s Optimizing module design_ice. 2224s 2224s 2.38.3. Executing OPT_MERGE pass (detect identical cells). 2224s Finding identical cells in module `\design_ice'. 2224s Removed a total of 0 cells. 2224s 2224s 2.38.4. Executing OPT_DFF pass (perform DFF optimizations). 2224s 2224s 2.38.5. Executing OPT_CLEAN pass (remove unused cells and wires). 2224s Finding unused cells or wires in module \design_ice.. 2224s Removed 0 unused cells and 9 unused wires. 2224s 2224s 2224s 2.38.6. Rerunning OPT passes. (Removed registers in this run.) 2224s 2224s 2.38.7. Running ICE40 specific optimizations. 2224s 2224s 2.38.8. Executing OPT_EXPR pass (perform const folding). 2224s Optimizing module design_ice. 2224s 2224s 2.38.9. Executing OPT_MERGE pass (detect identical cells). 2224s Finding identical cells in module `\design_ice'. 2224s Removed a total of 0 cells. 2224s 2224s 2.38.10. Executing OPT_DFF pass (perform DFF optimizations). 2224s 2224s 2.38.11. Executing OPT_CLEAN pass (remove unused cells and wires). 2224s Finding unused cells or wires in module \design_ice.. 2224s 2224s 2.38.12. Finished OPT passes. (There is nothing left to do.) 2224s 2224s 2.39. Executing TECHMAP pass (map to technology primitives). 2224s 2224s 2.39.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v 2224s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation. 2224s Generating RTLIL representation for module `\$_DLATCH_N_'. 2224s Generating RTLIL representation for module `\$_DLATCH_P_'. 2224s Successfully finished Verilog frontend. 2224s 2224s 2.39.2. Continuing TECHMAP pass. 2224s No more expansions possible. 2224s 2224s 2224s 2.40. Executing ABC pass (technology mapping using ABC). 2224s 2224s 2.40.1. Extracting gate netlist of module `\design_ice' to `/input.blif'.. 2224s Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs. 2224s Don't call ABC as there is nothing to map. 2224s Removing temp directory. 2224s 2224s 2.41. Executing ICE40_WRAPCARRY pass (wrap carries). 2224s 2224s 2.42. Executing TECHMAP pass (map to technology primitives). 2224s 2224s 2.42.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 2224s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 2224s Generating RTLIL representation for module `\$_DFF_N_'. 2224s Generating RTLIL representation for module `\$_DFF_P_'. 2224s Generating RTLIL representation for module `\$_DFFE_NP_'. 2224s Generating RTLIL representation for module `\$_DFFE_PP_'. 2224s Generating RTLIL representation for module `\$_DFF_NP0_'. 2224s Generating RTLIL representation for module `\$_DFF_NP1_'. 2224s Generating RTLIL representation for module `\$_DFF_PP0_'. 2224s Generating RTLIL representation for module `\$_DFF_PP1_'. 2224s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 2224s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 2224s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 2224s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 2224s Generating RTLIL representation for module `\$_SDFF_NP0_'. 2224s Generating RTLIL representation for module `\$_SDFF_NP1_'. 2224s Generating RTLIL representation for module `\$_SDFF_PP0_'. 2224s Generating RTLIL representation for module `\$_SDFF_PP1_'. 2224s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 2224s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 2224s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 2224s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 2224s Successfully finished Verilog frontend. 2224s 2224s 2.42.2. Continuing TECHMAP pass. 2224s No more expansions possible. 2224s 2224s 2224s 2.43. Executing OPT_LUT pass (optimize LUTs). 2224s Discovering LUTs. 2224s Number of LUTs: 0 2224s with \SB_CARRY (#0) 0 2224s with \SB_CARRY (#1) 0 2224s 2224s Eliminating LUTs. 2224s Number of LUTs: 0 2224s with \SB_CARRY (#0) 0 2224s with \SB_CARRY (#1) 0 2224s 2224s Combining LUTs. 2224s Number of LUTs: 0 2224s with \SB_CARRY (#0) 0 2224s with \SB_CARRY (#1) 0 2224s 2224s Eliminated 0 LUTs. 2224s Combined 0 LUTs. 2224s 2224s 2.44. Executing TECHMAP pass (map to technology primitives). 2224s 2224s 2.44.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v 2224s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation. 2224s Generating RTLIL representation for module `\$lut'. 2224s Successfully finished Verilog frontend. 2224s 2224s 2.44.2. Continuing TECHMAP pass. 2224s No more expansions possible. 2224s 2224s 2224s 2.45. Executing AUTONAME pass. 2224s Renamed 2 objects in module design_ice (2 iterations). 2224s 2224s 2224s 2.46. Executing HIERARCHY pass (managing design hierarchy). 2224s 2224s 2.46.1. Analyzing design hierarchy.. 2224s Top module: \design_ice 2224s 2224s 2.46.2. Analyzing design hierarchy.. 2224s Top module: \design_ice 2224s Removed 0 unused modules. 2224s 2224s 2.47. Printing statistics. 2224s 2224s === design_ice === 2224s 2224s Number of wires: 5 2224s Number of wire bits: 5 2224s Number of public wires: 5 2224s Number of public wire bits: 5 2224s Number of memories: 0 2224s Number of memory bits: 0 2224s Number of processes: 0 2224s Number of cells: 2 2224s SB_DFF 1 2224s SB_DFFE 1 2224s 2224s 2.48. Executing CHECK pass (checking for obvious problems). 2224s Checking module design_ice... 2224s Found and reported 0 problems. 2224s 2224s 2.49. Executing BLIF backend. 2224s 2224s End of script. Logfile hash: f379d43797, CPU: user 0.65s system 0.03s, MEM: 19.04 MB peak 2224s Yosys 0.33 (git sha1 2584903a060) 2224s Time spent: 68% 13x read_verilog (0 sec), 8% 1x synth_ice40 (0 sec), ... 2224s autopkgtest [18:18:34]: test ice: -----------------------] 2225s autopkgtest [18:18:35]: test ice: - - - - - - - - - - results - - - - - - - - - - 2225s ice PASS 2225s autopkgtest [18:18:35]: test smtbc: preparing testbed 2225s Reading package lists... 2226s Building dependency tree... 2226s Reading state information... 2226s Starting pkgProblemResolver with broken count: 0 2226s Starting 2 pkgProblemResolver with broken count: 0 2226s Done 2227s 0 upgraded, 0 newly installed, 0 to remove and 0 not upgraded. 2228s autopkgtest [18:18:38]: test smtbc: [----------------------- 2228s autopkgtest [18:18:38]: test smtbc: -----------------------] 2229s autopkgtest [18:18:39]: test smtbc: - - - - - - - - - - results - - - - - - - - - - 2229s smtbc PASS 2229s autopkgtest [18:18:39]: @@@@@@@@@@@@@@@@@@@@ summary 2229s yosys-testsuite PASS 2229s ice PASS 2229s smtbc PASS 2247s nova [W] Using flock in prodstack6-arm64 2247s flock: timeout while waiting to get lock 2247s Creating nova instance adt-plucky-arm64-yosys-20250315-174129-juju-7f2275-prod-proposed-migration-environment-15-39d412b6-f4d7-4093-a6ab-b77872e4ce22 from image adt/ubuntu-plucky-arm64-server-20250315.img (UUID bd6e766c-b51f-4b53-86d6-23aa4d18f524)... 2247s nova [W] Timed out waiting for b8f58d74-1ebf-4225-b274-348d9bebfd15 to get deleted. 2247s nova [W] Using flock in prodstack6-arm64 2247s Creating nova instance adt-plucky-arm64-yosys-20250315-174129-juju-7f2275-prod-proposed-migration-environment-15-39d412b6-f4d7-4093-a6ab-b77872e4ce22 from image adt/ubuntu-plucky-arm64-server-20250315.img (UUID bd6e766c-b51f-4b53-86d6-23aa4d18f524)... 2247s nova [W] Timed out waiting for 20368287-1543-434f-9d20-1263b75f3a70 to get deleted.