0s autopkgtest [23:54:43]: starting date and time: 2025-03-15 23:54:43+0000 0s autopkgtest [23:54:43]: git checkout: 325255d2 Merge branch 'pin-any-arch' into 'ubuntu/production' 0s autopkgtest [23:54:43]: host juju-7f2275-prod-proposed-migration-environment-2; command line: /home/ubuntu/autopkgtest/runner/autopkgtest --output-dir /tmp/autopkgtest-work.e6jbfp7y/out --timeout-copy=6000 --setup-commands /home/ubuntu/autopkgtest-cloud/worker-config-production/setup-canonical.sh --apt-pocket=proposed=src:glibc --apt-upgrade yosys --timeout-short=300 --timeout-copy=20000 --timeout-build=20000 --env=ADT_TEST_TRIGGERS=glibc/2.41-1ubuntu2 -- ssh -s /home/ubuntu/autopkgtest/ssh-setup/nova -- --flavor builder-cpu2-ram4-disk20 --security-groups autopkgtest-juju-7f2275-prod-proposed-migration-environment-2@bos03-18.secgroup --name adt-plucky-amd64-yosys-20250315-235443-juju-7f2275-prod-proposed-migration-environment-2-6475d2f7-471d-4373-ae33-3e58b1c59995 --image adt/ubuntu-plucky-amd64-server --keyname testbed-juju-7f2275-prod-proposed-migration-environment-2 --net-id=net_prod-proposed-migration-amd64 -e TERM=linux -e ''"'"'http_proxy=http://squid.internal:3128'"'"'' -e ''"'"'https_proxy=http://squid.internal:3128'"'"'' -e ''"'"'no_proxy=127.0.0.1,127.0.1.1,login.ubuntu.com,localhost,localdomain,novalocal,internal,archive.ubuntu.com,ports.ubuntu.com,security.ubuntu.com,ddebs.ubuntu.com,changelogs.ubuntu.com,keyserver.ubuntu.com,launchpadlibrarian.net,launchpadcontent.net,launchpad.net,10.24.0.0/24,keystone.ps5.canonical.com,objectstorage.prodstack5.canonical.com,radosgw.ps5.canonical.com'"'"'' --mirror=http://ftpmaster.internal/ubuntu/ 48s autopkgtest [23:55:31]: testbed dpkg architecture: amd64 48s autopkgtest [23:55:31]: testbed apt version: 2.9.31ubuntu1 48s autopkgtest [23:55:31]: @@@@@@@@@@@@@@@@@@@@ test bed setup 48s autopkgtest [23:55:31]: testbed release detected to be: None 49s autopkgtest [23:55:32]: updating testbed package index (apt update) 50s Get:1 http://ftpmaster.internal/ubuntu plucky-proposed InRelease [126 kB] 50s Hit:2 http://ftpmaster.internal/ubuntu plucky InRelease 50s Hit:3 http://ftpmaster.internal/ubuntu plucky-updates InRelease 50s Hit:4 http://ftpmaster.internal/ubuntu plucky-security InRelease 50s Get:5 http://ftpmaster.internal/ubuntu plucky-proposed/universe Sources [369 kB] 50s Get:6 http://ftpmaster.internal/ubuntu plucky-proposed/main Sources [44.1 kB] 50s Get:7 http://ftpmaster.internal/ubuntu plucky-proposed/multiverse Sources [14.5 kB] 50s Get:8 http://ftpmaster.internal/ubuntu plucky-proposed/main i386 Packages [67.4 kB] 50s Get:9 http://ftpmaster.internal/ubuntu plucky-proposed/main amd64 Packages [85.7 kB] 50s Get:10 http://ftpmaster.internal/ubuntu plucky-proposed/main amd64 c-n-f Metadata [1852 B] 50s Get:11 http://ftpmaster.internal/ubuntu plucky-proposed/restricted amd64 c-n-f Metadata [116 B] 50s Get:12 http://ftpmaster.internal/ubuntu plucky-proposed/universe i386 Packages [174 kB] 50s Get:13 http://ftpmaster.internal/ubuntu plucky-proposed/universe amd64 Packages [342 kB] 50s Get:14 http://ftpmaster.internal/ubuntu plucky-proposed/universe amd64 c-n-f Metadata [15.3 kB] 50s Get:15 http://ftpmaster.internal/ubuntu plucky-proposed/multiverse amd64 Packages [16.1 kB] 50s Get:16 http://ftpmaster.internal/ubuntu plucky-proposed/multiverse i386 Packages [8544 B] 50s Get:17 http://ftpmaster.internal/ubuntu plucky-proposed/multiverse amd64 c-n-f Metadata [628 B] 51s Fetched 1265 kB in 1s (1493 kB/s) 52s Reading package lists... 52s Reading package lists... 52s Building dependency tree... 52s Reading state information... 53s Calculating upgrade... 53s Calculating upgrade... 53s The following package was automatically installed and is no longer required: 53s libnl-genl-3-200 53s Use 'sudo apt autoremove' to remove it. 53s The following NEW packages will be installed: 53s bpftool libdebuginfod-common libdebuginfod1t64 linux-headers-6.14.0-10 53s linux-headers-6.14.0-10-generic linux-image-6.14.0-10-generic 53s linux-modules-6.14.0-10-generic linux-modules-extra-6.14.0-10-generic 53s linux-perf linux-tools-6.14.0-10 linux-tools-6.14.0-10-generic pnp.ids 53s The following packages will be upgraded: 53s apparmor apt apt-utils binutils binutils-common binutils-x86-64-linux-gnu 53s cloud-init cloud-init-base curl dosfstools exfatprogs fwupd gcc-15-base 53s gir1.2-girepository-2.0 gir1.2-glib-2.0 htop hwdata initramfs-tools 53s initramfs-tools-bin initramfs-tools-core libapparmor1 libapt-pkg7.0 53s libassuan9 libatomic1 libaudit-common libaudit1 libbinutils libbrotli1 53s libc-bin libc-dev-bin libc6 libc6-dev libcap-ng0 libctf-nobfd0 libctf0 53s libcurl3t64-gnutls libcurl4t64 libestr0 libftdi1-2 libfwupd3 libgcc-s1 53s libgirepository-1.0-1 libglib2.0-0t64 libglib2.0-data libgpgme11t64 53s libgprofng0 libjemalloc2 liblz4-1 liblzma5 libmm-glib0 libncurses6 53s libncursesw6 libnewt0.52 libnl-3-200 libnl-genl-3-200 libnl-route-3-200 53s libnss-systemd libpam-systemd libparted2t64 libpci3 libpython3-stdlib 53s libpython3.13 libpython3.13-minimal libpython3.13-stdlib libseccomp2 53s libselinux1 libsemanage-common libsemanage2 libsframe1 libsqlite3-0 53s libstdc++6 libsystemd-shared libsystemd0 libtinfo6 libudev1 libxml2 53s linux-firmware linux-generic linux-headers-generic linux-headers-virtual 53s linux-image-generic linux-image-virtual linux-libc-dev linux-tools-common 53s linux-virtual locales media-types ncurses-base ncurses-bin ncurses-term 53s parted pci.ids pciutils pinentry-curses python-apt-common python3 53s python3-apt python3-bcrypt python3-cffi-backend python3-dbus python3-gi 53s python3-jinja2 python3-lazr.uri python3-markupsafe python3-minimal 53s python3-newt python3-rpds-py python3-systemd python3-yaml python3.13 53s python3.13-gdbm python3.13-minimal rsync rsyslog strace systemd 53s systemd-cryptsetup systemd-resolved systemd-sysv systemd-timesyncd 53s ubuntu-kernel-accessories ubuntu-minimal ubuntu-standard udev whiptail 53s xz-utils 53s 126 upgraded, 12 newly installed, 0 to remove and 0 not upgraded. 53s Need to get 829 MB of archives. 53s After this operation, 325 MB of additional disk space will be used. 53s Get:1 http://ftpmaster.internal/ubuntu plucky/main amd64 ncurses-bin amd64 6.5+20250216-2 [194 kB] 54s Get:2 http://ftpmaster.internal/ubuntu plucky/main amd64 libc-dev-bin amd64 2.41-1ubuntu1 [24.7 kB] 54s Get:3 http://ftpmaster.internal/ubuntu plucky/main amd64 libc6-dev amd64 2.41-1ubuntu1 [2182 kB] 54s Get:4 http://ftpmaster.internal/ubuntu plucky/main amd64 locales all 2.41-1ubuntu1 [4246 kB] 54s Get:5 http://ftpmaster.internal/ubuntu plucky/main amd64 libc6 amd64 2.41-1ubuntu1 [3327 kB] 54s Get:6 http://ftpmaster.internal/ubuntu plucky/main amd64 libc-bin amd64 2.41-1ubuntu1 [701 kB] 54s Get:7 http://ftpmaster.internal/ubuntu plucky/main amd64 linux-libc-dev amd64 6.14.0-10.10 [1723 kB] 54s Get:8 http://ftpmaster.internal/ubuntu plucky/main amd64 libatomic1 amd64 15-20250222-0ubuntu1 [10.4 kB] 54s Get:9 http://ftpmaster.internal/ubuntu plucky/main amd64 gcc-15-base amd64 15-20250222-0ubuntu1 [53.4 kB] 54s Get:10 http://ftpmaster.internal/ubuntu plucky/main amd64 libgcc-s1 amd64 15-20250222-0ubuntu1 [77.8 kB] 54s Get:11 http://ftpmaster.internal/ubuntu plucky/main amd64 libstdc++6 amd64 15-20250222-0ubuntu1 [798 kB] 54s Get:12 http://ftpmaster.internal/ubuntu plucky/main amd64 ncurses-base all 6.5+20250216-2 [25.9 kB] 54s Get:13 http://ftpmaster.internal/ubuntu plucky/main amd64 ncurses-term all 6.5+20250216-2 [276 kB] 54s Get:14 http://ftpmaster.internal/ubuntu plucky/main amd64 liblz4-1 amd64 1.10.0-4 [66.4 kB] 54s Get:15 http://ftpmaster.internal/ubuntu plucky/main amd64 liblzma5 amd64 5.6.4-1 [157 kB] 54s Get:16 http://ftpmaster.internal/ubuntu plucky/main amd64 libsystemd0 amd64 257.3-1ubuntu3 [595 kB] 54s Get:17 http://ftpmaster.internal/ubuntu plucky/main amd64 libnss-systemd amd64 257.3-1ubuntu3 [199 kB] 54s Get:18 http://ftpmaster.internal/ubuntu plucky/main amd64 systemd-sysv amd64 257.3-1ubuntu3 [11.9 kB] 54s Get:19 http://ftpmaster.internal/ubuntu plucky/main amd64 systemd-resolved amd64 257.3-1ubuntu3 [345 kB] 54s Get:20 http://ftpmaster.internal/ubuntu plucky/main amd64 libpam-systemd amd64 257.3-1ubuntu3 [302 kB] 54s Get:21 http://ftpmaster.internal/ubuntu plucky/main amd64 libsystemd-shared amd64 257.3-1ubuntu3 [2371 kB] 54s Get:22 http://ftpmaster.internal/ubuntu plucky/main amd64 systemd amd64 257.3-1ubuntu3 [3052 kB] 54s Get:23 http://ftpmaster.internal/ubuntu plucky/main amd64 systemd-timesyncd amd64 257.3-1ubuntu3 [42.1 kB] 54s Get:24 http://ftpmaster.internal/ubuntu plucky/main amd64 systemd-cryptsetup amd64 257.3-1ubuntu3 [124 kB] 54s Get:25 http://ftpmaster.internal/ubuntu plucky/main amd64 udev amd64 257.3-1ubuntu3 [1404 kB] 54s Get:26 http://ftpmaster.internal/ubuntu plucky/main amd64 libudev1 amd64 257.3-1ubuntu3 [215 kB] 54s Get:27 http://ftpmaster.internal/ubuntu plucky/main amd64 libaudit-common all 1:4.0.2-2ubuntu2 [6628 B] 54s Get:28 http://ftpmaster.internal/ubuntu plucky/main amd64 libcap-ng0 amd64 0.8.5-4build1 [15.6 kB] 54s Get:29 http://ftpmaster.internal/ubuntu plucky/main amd64 libaudit1 amd64 1:4.0.2-2ubuntu2 [54.0 kB] 54s Get:30 http://ftpmaster.internal/ubuntu plucky/main amd64 libseccomp2 amd64 2.5.5-1ubuntu6 [53.5 kB] 54s Get:31 http://ftpmaster.internal/ubuntu plucky/main amd64 libselinux1 amd64 3.7-3ubuntu3 [87.3 kB] 54s Get:32 http://ftpmaster.internal/ubuntu plucky/main amd64 libapparmor1 amd64 4.1.0~beta5-0ubuntu8 [55.0 kB] 55s Get:33 http://ftpmaster.internal/ubuntu plucky/main amd64 libapt-pkg7.0 amd64 2.9.33 [1138 kB] 55s Get:34 http://ftpmaster.internal/ubuntu plucky/main amd64 apt amd64 2.9.33 [1439 kB] 55s Get:35 http://ftpmaster.internal/ubuntu plucky/main amd64 apt-utils amd64 2.9.33 [222 kB] 55s Get:36 http://ftpmaster.internal/ubuntu plucky/main amd64 python3-minimal amd64 3.13.2-2 [27.7 kB] 55s Get:37 http://ftpmaster.internal/ubuntu plucky/main amd64 python3 amd64 3.13.2-2 [24.0 kB] 55s Get:38 http://ftpmaster.internal/ubuntu plucky/main amd64 libpython3.13 amd64 3.13.2-2 [2341 kB] 55s Get:39 http://ftpmaster.internal/ubuntu plucky/main amd64 media-types all 13.0.0 [29.9 kB] 55s Get:40 http://ftpmaster.internal/ubuntu plucky/main amd64 libncurses6 amd64 6.5+20250216-2 [126 kB] 55s Get:41 http://ftpmaster.internal/ubuntu plucky/main amd64 libncursesw6 amd64 6.5+20250216-2 [165 kB] 55s Get:42 http://ftpmaster.internal/ubuntu plucky/main amd64 libtinfo6 amd64 6.5+20250216-2 [119 kB] 55s Get:43 http://ftpmaster.internal/ubuntu plucky/main amd64 libsqlite3-0 amd64 3.46.1-2 [715 kB] 55s Get:44 http://ftpmaster.internal/ubuntu plucky/main amd64 python3.13 amd64 3.13.2-2 [735 kB] 55s Get:45 http://ftpmaster.internal/ubuntu plucky/main amd64 python3.13-minimal amd64 3.13.2-2 [2365 kB] 55s Get:46 http://ftpmaster.internal/ubuntu plucky/main amd64 libpython3.13-minimal amd64 3.13.2-2 [883 kB] 55s Get:47 http://ftpmaster.internal/ubuntu plucky/main amd64 libpython3.13-stdlib amd64 3.13.2-2 [2066 kB] 55s Get:48 http://ftpmaster.internal/ubuntu plucky/main amd64 libpython3-stdlib amd64 3.13.2-2 [10.4 kB] 55s Get:49 http://ftpmaster.internal/ubuntu plucky/main amd64 rsync amd64 3.4.1+ds1-3 [482 kB] 55s Get:50 http://ftpmaster.internal/ubuntu plucky/main amd64 libdebuginfod-common all 0.192-4 [15.4 kB] 55s Get:51 http://ftpmaster.internal/ubuntu plucky/main amd64 libsemanage-common all 3.7-2.1build1 [7268 B] 55s Get:52 http://ftpmaster.internal/ubuntu plucky/main amd64 libsemanage2 amd64 3.7-2.1build1 [106 kB] 55s Get:53 http://ftpmaster.internal/ubuntu plucky/main amd64 libassuan9 amd64 3.0.2-2 [43.1 kB] 55s Get:54 http://ftpmaster.internal/ubuntu plucky/main amd64 gir1.2-girepository-2.0 amd64 1.83.4-1 [25.3 kB] 55s Get:55 http://ftpmaster.internal/ubuntu plucky/main amd64 gir1.2-glib-2.0 amd64 2.84.0-1 [184 kB] 55s Get:56 http://ftpmaster.internal/ubuntu plucky/main amd64 libglib2.0-0t64 amd64 2.84.0-1 [1669 kB] 55s Get:57 http://ftpmaster.internal/ubuntu plucky/main amd64 libgirepository-1.0-1 amd64 1.83.4-1 [89.5 kB] 55s Get:58 http://ftpmaster.internal/ubuntu plucky/main amd64 libestr0 amd64 0.1.11-2 [8340 B] 55s Get:59 http://ftpmaster.internal/ubuntu plucky/main amd64 libglib2.0-data all 2.84.0-1 [53.0 kB] 55s Get:60 http://ftpmaster.internal/ubuntu plucky/main amd64 python3-newt amd64 0.52.24-4ubuntu2 [21.1 kB] 55s Get:61 http://ftpmaster.internal/ubuntu plucky/main amd64 libnewt0.52 amd64 0.52.24-4ubuntu2 [55.7 kB] 55s Get:62 http://ftpmaster.internal/ubuntu plucky/main amd64 libxml2 amd64 2.12.7+dfsg+really2.9.14-0.2ubuntu5 [772 kB] 55s Get:63 http://ftpmaster.internal/ubuntu plucky/main amd64 python-apt-common all 2.9.9build1 [21.3 kB] 55s Get:64 http://ftpmaster.internal/ubuntu plucky/main amd64 python3-apt amd64 2.9.9build1 [172 kB] 55s Get:65 http://ftpmaster.internal/ubuntu plucky/main amd64 python3-cffi-backend amd64 1.17.1-2build2 [96.6 kB] 55s Get:66 http://ftpmaster.internal/ubuntu plucky/main amd64 python3-dbus amd64 1.3.2-5build5 [102 kB] 55s Get:67 http://ftpmaster.internal/ubuntu plucky/main amd64 python3-gi amd64 3.50.0-4build1 [252 kB] 55s Get:68 http://ftpmaster.internal/ubuntu plucky/main amd64 python3-yaml amd64 6.0.2-1build2 [144 kB] 55s Get:69 http://ftpmaster.internal/ubuntu plucky/main amd64 rsyslog amd64 8.2412.0-2ubuntu2 [555 kB] 55s Get:70 http://ftpmaster.internal/ubuntu plucky/main amd64 whiptail amd64 0.52.24-4ubuntu2 [19.1 kB] 55s Get:71 http://ftpmaster.internal/ubuntu plucky/main amd64 ubuntu-minimal amd64 1.549 [11.5 kB] 55s Get:72 http://ftpmaster.internal/ubuntu plucky/main amd64 apparmor amd64 4.1.0~beta5-0ubuntu8 [701 kB] 55s Get:73 http://ftpmaster.internal/ubuntu plucky/main amd64 dosfstools amd64 4.2-1.2 [95.0 kB] 55s Get:74 http://ftpmaster.internal/ubuntu plucky/main amd64 libnl-genl-3-200 amd64 3.7.0-1 [12.2 kB] 55s Get:75 http://ftpmaster.internal/ubuntu plucky/main amd64 libnl-route-3-200 amd64 3.7.0-1 [191 kB] 55s Get:76 http://ftpmaster.internal/ubuntu plucky/main amd64 libnl-3-200 amd64 3.7.0-1 [64.9 kB] 55s Get:77 http://ftpmaster.internal/ubuntu plucky/main amd64 parted amd64 3.6-5 [53.9 kB] 55s Get:78 http://ftpmaster.internal/ubuntu plucky/main amd64 libparted2t64 amd64 3.6-5 [158 kB] 55s Get:79 http://ftpmaster.internal/ubuntu plucky/main amd64 pci.ids all 0.0~2025.03.09-1 [285 kB] 55s Get:80 http://ftpmaster.internal/ubuntu plucky/main amd64 pciutils amd64 1:3.13.0-2 [110 kB] 55s Get:81 http://ftpmaster.internal/ubuntu plucky/main amd64 libpci3 amd64 1:3.13.0-2 [39.8 kB] 55s Get:82 http://ftpmaster.internal/ubuntu plucky/main amd64 strace amd64 6.13+ds-1ubuntu1 [622 kB] 55s Get:83 http://ftpmaster.internal/ubuntu plucky/main amd64 xz-utils amd64 5.6.4-1 [278 kB] 55s Get:84 http://ftpmaster.internal/ubuntu plucky/main amd64 ubuntu-standard amd64 1.549 [11.5 kB] 55s Get:85 http://ftpmaster.internal/ubuntu plucky/main amd64 libgprofng0 amd64 2.44-3ubuntu1 [886 kB] 55s Get:86 http://ftpmaster.internal/ubuntu plucky/main amd64 libctf0 amd64 2.44-3ubuntu1 [96.5 kB] 55s Get:87 http://ftpmaster.internal/ubuntu plucky/main amd64 libctf-nobfd0 amd64 2.44-3ubuntu1 [98.9 kB] 55s Get:88 http://ftpmaster.internal/ubuntu plucky/main amd64 binutils-x86-64-linux-gnu amd64 2.44-3ubuntu1 [1108 kB] 56s Get:89 http://ftpmaster.internal/ubuntu plucky/main amd64 libbinutils amd64 2.44-3ubuntu1 [585 kB] 56s Get:90 http://ftpmaster.internal/ubuntu plucky/main amd64 binutils amd64 2.44-3ubuntu1 [208 kB] 56s Get:91 http://ftpmaster.internal/ubuntu plucky/main amd64 binutils-common amd64 2.44-3ubuntu1 [215 kB] 56s Get:92 http://ftpmaster.internal/ubuntu plucky/main amd64 libsframe1 amd64 2.44-3ubuntu1 [14.8 kB] 56s Get:93 http://ftpmaster.internal/ubuntu plucky/main amd64 hwdata all 0.393-3 [1562 B] 56s Get:94 http://ftpmaster.internal/ubuntu plucky/main amd64 pnp.ids all 0.393-3 [29.5 kB] 56s Get:95 http://ftpmaster.internal/ubuntu plucky/main amd64 linux-tools-common all 6.14.0-10.10 [295 kB] 56s Get:96 http://ftpmaster.internal/ubuntu plucky/main amd64 bpftool amd64 7.6.0+6.14.0-10.10 [1147 kB] 56s Get:97 http://ftpmaster.internal/ubuntu plucky/main amd64 python3-markupsafe amd64 2.1.5-1build4 [13.4 kB] 56s Get:98 http://ftpmaster.internal/ubuntu plucky/main amd64 python3-jinja2 all 3.1.5-2ubuntu1 [109 kB] 56s Get:99 http://ftpmaster.internal/ubuntu plucky/main amd64 cloud-init-base all 25.1-0ubuntu3 [616 kB] 56s Get:100 http://ftpmaster.internal/ubuntu plucky/main amd64 libbrotli1 amd64 1.1.0-2build4 [365 kB] 56s Get:101 http://ftpmaster.internal/ubuntu plucky/main amd64 curl amd64 8.12.1-3ubuntu1 [258 kB] 56s Get:102 http://ftpmaster.internal/ubuntu plucky/main amd64 libcurl4t64 amd64 8.12.1-3ubuntu1 [437 kB] 56s Get:103 http://ftpmaster.internal/ubuntu plucky/main amd64 exfatprogs amd64 1.2.8-1 [76.3 kB] 56s Get:104 http://ftpmaster.internal/ubuntu plucky/main amd64 libcurl3t64-gnutls amd64 8.12.1-3ubuntu1 [432 kB] 56s Get:105 http://ftpmaster.internal/ubuntu plucky/main amd64 fwupd amd64 2.0.6-4 [5408 kB] 57s Get:106 http://ftpmaster.internal/ubuntu plucky/main amd64 libfwupd3 amd64 2.0.6-4 [136 kB] 57s Get:107 http://ftpmaster.internal/ubuntu plucky/main amd64 libmm-glib0 amd64 1.23.4-0ubuntu3 [251 kB] 57s Get:108 http://ftpmaster.internal/ubuntu plucky/main amd64 htop amd64 3.4.0-2 [195 kB] 57s Get:109 http://ftpmaster.internal/ubuntu plucky/main amd64 linux-firmware amd64 20250310.git9e1370d3-0ubuntu1 [571 MB] 71s Get:110 http://ftpmaster.internal/ubuntu plucky/main amd64 initramfs-tools all 0.146ubuntu1 [7920 B] 71s Get:111 http://ftpmaster.internal/ubuntu plucky/main amd64 initramfs-tools-core all 0.146ubuntu1 [51.9 kB] 71s Get:112 http://ftpmaster.internal/ubuntu plucky/main amd64 initramfs-tools-bin amd64 0.146ubuntu1 [26.2 kB] 71s Get:113 http://ftpmaster.internal/ubuntu plucky/main amd64 libdebuginfod1t64 amd64 0.192-4 [21.0 kB] 71s Get:114 http://ftpmaster.internal/ubuntu plucky/main amd64 libftdi1-2 amd64 1.5-8build1 [30.2 kB] 71s Get:115 http://ftpmaster.internal/ubuntu plucky/main amd64 libgpgme11t64 amd64 1.24.2-1ubuntu2 [155 kB] 71s Get:116 http://ftpmaster.internal/ubuntu plucky/main amd64 libjemalloc2 amd64 5.3.0-3 [277 kB] 71s Get:117 http://ftpmaster.internal/ubuntu plucky/main amd64 linux-modules-6.14.0-10-generic amd64 6.14.0-10.10 [41.2 MB] 72s Get:118 http://ftpmaster.internal/ubuntu plucky/main amd64 linux-image-6.14.0-10-generic amd64 6.14.0-10.10 [15.3 MB] 72s Get:119 http://ftpmaster.internal/ubuntu plucky/main amd64 linux-modules-extra-6.14.0-10-generic amd64 6.14.0-10.10 [120 MB] 75s Get:120 http://ftpmaster.internal/ubuntu plucky/main amd64 linux-generic amd64 6.14.0-10.10 [1730 B] 75s Get:121 http://ftpmaster.internal/ubuntu plucky/main amd64 linux-image-generic amd64 6.14.0-10.10 [11.1 kB] 75s Get:122 http://ftpmaster.internal/ubuntu plucky/main amd64 linux-virtual amd64 6.14.0-10.10 [1722 B] 75s Get:123 http://ftpmaster.internal/ubuntu plucky/main amd64 linux-image-virtual amd64 6.14.0-10.10 [11.1 kB] 75s Get:124 http://ftpmaster.internal/ubuntu plucky/main amd64 linux-headers-virtual amd64 6.14.0-10.10 [1642 B] 75s Get:125 http://ftpmaster.internal/ubuntu plucky/main amd64 linux-headers-6.14.0-10 all 6.14.0-10.10 [14.2 MB] 76s Get:126 http://ftpmaster.internal/ubuntu plucky/main amd64 linux-headers-6.14.0-10-generic amd64 6.14.0-10.10 [3915 kB] 76s Get:127 http://ftpmaster.internal/ubuntu plucky/main amd64 linux-headers-generic amd64 6.14.0-10.10 [11.0 kB] 76s Get:128 http://ftpmaster.internal/ubuntu plucky/main amd64 linux-perf amd64 6.14.0-10.10 [4122 kB] 76s Get:129 http://ftpmaster.internal/ubuntu plucky/main amd64 linux-tools-6.14.0-10 amd64 6.14.0-10.10 [1394 kB] 76s Get:130 http://ftpmaster.internal/ubuntu plucky/main amd64 linux-tools-6.14.0-10-generic amd64 6.14.0-10.10 [830 B] 76s Get:131 http://ftpmaster.internal/ubuntu plucky/main amd64 pinentry-curses amd64 1.3.1-2ubuntu3 [42.3 kB] 76s Get:132 http://ftpmaster.internal/ubuntu plucky/main amd64 python3-lazr.uri all 1.0.6-6 [13.7 kB] 76s Get:133 http://ftpmaster.internal/ubuntu plucky/main amd64 python3-rpds-py amd64 0.21.0-2ubuntu2 [278 kB] 76s Get:134 http://ftpmaster.internal/ubuntu plucky/main amd64 python3-systemd amd64 235-1build6 [43.9 kB] 76s Get:135 http://ftpmaster.internal/ubuntu plucky/main amd64 python3.13-gdbm amd64 3.13.2-2 [31.9 kB] 76s Get:136 http://ftpmaster.internal/ubuntu plucky/main amd64 ubuntu-kernel-accessories amd64 1.549 [11.2 kB] 76s Get:137 http://ftpmaster.internal/ubuntu plucky/main amd64 cloud-init all 25.1-0ubuntu3 [2100 B] 76s Get:138 http://ftpmaster.internal/ubuntu plucky/main amd64 python3-bcrypt amd64 4.2.0-2.1build1 [221 kB] 77s Preconfiguring packages ... 77s Fetched 829 MB in 23s (36.3 MB/s) 77s (Reading database ... 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(Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 109140 files and directories currently installed.) 77s Preparing to unpack .../libc-dev-bin_2.41-1ubuntu1_amd64.deb ... 77s Unpacking libc-dev-bin (2.41-1ubuntu1) over (2.40-4ubuntu1) ... 77s Preparing to unpack .../libc6-dev_2.41-1ubuntu1_amd64.deb ... 77s Unpacking libc6-dev:amd64 (2.41-1ubuntu1) over (2.40-4ubuntu1) ... 77s Preparing to unpack .../locales_2.41-1ubuntu1_all.deb ... 77s Unpacking locales (2.41-1ubuntu1) over (2.40-4ubuntu1) ... 78s Preparing to unpack .../libc6_2.41-1ubuntu1_amd64.deb ... 78s Checking for services that may need to be restarted... 78s Checking init scripts... 78s Checking for services that may need to be restarted... 78s Checking init scripts... 78s Stopping some services possibly affected by the upgrade (will be restarted later): 78s cron: stopping...done. 78s 78s Unpacking libc6:amd64 (2.41-1ubuntu1) over (2.40-4ubuntu1) ... 78s Setting up libc6:amd64 (2.41-1ubuntu1) ... 78s Checking for services that may need to be restarted... 78s Checking init scripts... 78s Restarting services possibly affected by the upgrade: 78s cron: restarting...done. 78s 78s Services restarted successfully. 78s (Reading database ... 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(Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 109146 files and directories currently installed.) 82s Preparing to unpack .../libaudit1_1%3a4.0.2-2ubuntu2_amd64.deb ... 82s Unpacking libaudit1:amd64 (1:4.0.2-2ubuntu2) over (1:4.0.2-2ubuntu1) ... 82s Setting up libaudit1:amd64 (1:4.0.2-2ubuntu2) ... 82s (Reading database ... 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(Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 109146 files and directories currently installed.) 82s Preparing to unpack .../libselinux1_3.7-3ubuntu3_amd64.deb ... 82s Unpacking libselinux1:amd64 (3.7-3ubuntu3) over (3.7-3ubuntu2) ... 82s Setting up libselinux1:amd64 (3.7-3ubuntu3) ... 82s (Reading database ... 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(Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 109146 files and directories currently installed.) 83s Preparing to unpack .../apt-utils_2.9.33_amd64.deb ... 83s Unpacking apt-utils (2.9.33) over (2.9.31ubuntu1) ... 83s Preparing to unpack .../python3-minimal_3.13.2-2_amd64.deb ... 83s Unpacking python3-minimal (3.13.2-2) over (3.13.2-1) ... 83s Setting up python3-minimal (3.13.2-2) ... 83s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 109146 files and directories currently installed.) 83s Preparing to unpack .../0-python3_3.13.2-2_amd64.deb ... 83s Unpacking python3 (3.13.2-2) over (3.13.2-1) ... 83s Preparing to unpack .../1-libpython3.13_3.13.2-2_amd64.deb ... 83s Unpacking libpython3.13:amd64 (3.13.2-2) over (3.13.2-1) ... 84s Preparing to unpack .../2-media-types_13.0.0_all.deb ... 84s Unpacking media-types (13.0.0) over (12.0.0) ... 84s Preparing to unpack .../3-libncurses6_6.5+20250216-2_amd64.deb ... 84s Unpacking libncurses6:amd64 (6.5+20250216-2) over (6.5+20250216-1) ... 84s Preparing to unpack .../4-libncursesw6_6.5+20250216-2_amd64.deb ... 84s Unpacking libncursesw6:amd64 (6.5+20250216-2) over (6.5+20250216-1) ... 84s Preparing to unpack .../5-libtinfo6_6.5+20250216-2_amd64.deb ... 84s Unpacking libtinfo6:amd64 (6.5+20250216-2) over (6.5+20250216-1) ... 84s Setting up libtinfo6:amd64 (6.5+20250216-2) ... 84s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 109146 files and directories currently installed.) 84s Preparing to unpack .../0-libsqlite3-0_3.46.1-2_amd64.deb ... 84s Unpacking libsqlite3-0:amd64 (3.46.1-2) over (3.46.1-1) ... 84s Preparing to unpack .../1-python3.13_3.13.2-2_amd64.deb ... 84s Unpacking python3.13 (3.13.2-2) over (3.13.2-1) ... 84s Preparing to unpack .../2-python3.13-minimal_3.13.2-2_amd64.deb ... 84s Unpacking python3.13-minimal (3.13.2-2) over (3.13.2-1) ... 84s Preparing to unpack .../3-libpython3.13-minimal_3.13.2-2_amd64.deb ... 84s Unpacking libpython3.13-minimal:amd64 (3.13.2-2) over (3.13.2-1) ... 84s Preparing to unpack .../4-libpython3.13-stdlib_3.13.2-2_amd64.deb ... 84s Unpacking libpython3.13-stdlib:amd64 (3.13.2-2) over (3.13.2-1) ... 84s Preparing to unpack .../5-libpython3-stdlib_3.13.2-2_amd64.deb ... 84s Unpacking libpython3-stdlib:amd64 (3.13.2-2) over (3.13.2-1) ... 84s Preparing to unpack .../6-rsync_3.4.1+ds1-3_amd64.deb ... 84s Unpacking rsync (3.4.1+ds1-3) over (3.4.1-0syncable1) ... 84s Selecting previously unselected package libdebuginfod-common. 84s Preparing to unpack .../7-libdebuginfod-common_0.192-4_all.deb ... 84s Unpacking libdebuginfod-common (0.192-4) ... 84s Preparing to unpack .../8-libsemanage-common_3.7-2.1build1_all.deb ... 84s Unpacking libsemanage-common (3.7-2.1build1) over (3.7-2.1) ... 84s Setting up libsemanage-common (3.7-2.1build1) ... 85s (Reading database ... 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unpack .../29-xz-utils_5.6.4-1_amd64.deb ... 87s Unpacking xz-utils (5.6.4-1) over (5.6.3-1) ... 88s Preparing to unpack .../30-ubuntu-standard_1.549_amd64.deb ... 88s Unpacking ubuntu-standard (1.549) over (1.548) ... 88s Preparing to unpack .../31-libgprofng0_2.44-3ubuntu1_amd64.deb ... 88s Unpacking libgprofng0:amd64 (2.44-3ubuntu1) over (2.44-2ubuntu1) ... 88s Preparing to unpack .../32-libctf0_2.44-3ubuntu1_amd64.deb ... 88s Unpacking libctf0:amd64 (2.44-3ubuntu1) over (2.44-2ubuntu1) ... 88s Preparing to unpack .../33-libctf-nobfd0_2.44-3ubuntu1_amd64.deb ... 88s Unpacking libctf-nobfd0:amd64 (2.44-3ubuntu1) over (2.44-2ubuntu1) ... 88s Preparing to unpack .../34-binutils-x86-64-linux-gnu_2.44-3ubuntu1_amd64.deb ... 88s Unpacking binutils-x86-64-linux-gnu (2.44-3ubuntu1) over (2.44-2ubuntu1) ... 88s Preparing to unpack .../35-libbinutils_2.44-3ubuntu1_amd64.deb ... 88s Unpacking libbinutils:amd64 (2.44-3ubuntu1) over (2.44-2ubuntu1) ... 88s Preparing to unpack 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unpack .../80-python3-systemd_235-1build6_amd64.deb ... 98s Unpacking python3-systemd (235-1build6) over (235-1build5) ... 98s Preparing to unpack .../81-python3.13-gdbm_3.13.2-2_amd64.deb ... 98s Unpacking python3.13-gdbm (3.13.2-2) over (3.13.2-1) ... 99s Preparing to unpack .../82-ubuntu-kernel-accessories_1.549_amd64.deb ... 99s Unpacking ubuntu-kernel-accessories (1.549) over (1.548) ... 99s Preparing to unpack .../83-cloud-init_25.1-0ubuntu3_all.deb ... 99s Unpacking cloud-init (25.1-0ubuntu3) over (25.1-0ubuntu2) ... 99s Preparing to unpack .../84-python3-bcrypt_4.2.0-2.1build1_amd64.deb ... 99s Unpacking python3-bcrypt (4.2.0-2.1build1) over (4.2.0-2.1) ... 99s Setting up linux-headers-6.14.0-10 (6.14.0-10.10) ... 99s Setting up media-types (13.0.0) ... 99s Installing new version of config file /etc/mime.types ... 99s Setting up linux-headers-6.14.0-10-generic (6.14.0-10.10) ... 99s Setting up ubuntu-kernel-accessories (1.549) ... 99s Setting up libapparmor1:amd64 (4.1.0~beta5-0ubuntu8) ... 99s Setting up pci.ids (0.0~2025.03.09-1) ... 99s Setting up libnewt0.52:amd64 (0.52.24-4ubuntu2) ... 99s Setting up apt-utils (2.9.33) ... 99s Setting up libdebuginfod-common (0.192-4) ... 99s Setting up exfatprogs (1.2.8-1) ... 99s Setting up linux-firmware (20250310.git9e1370d3-0ubuntu1) ... 99s Setting up bpftool (7.6.0+6.14.0-10.10) ... 99s Setting up libestr0:amd64 (0.1.11-2) ... 99s Setting up libbrotli1:amd64 (1.1.0-2build4) ... 99s Setting up libsqlite3-0:amd64 (3.46.1-2) ... 99s Setting up dosfstools (4.2-1.2) ... 99s Setting up rsyslog (8.2412.0-2ubuntu2) ... 99s info: The user `syslog' is already a member of `adm'. 100s Setting up binutils-common:amd64 (2.44-3ubuntu1) ... 100s Setting up libcurl3t64-gnutls:amd64 (8.12.1-3ubuntu1) ... 100s Setting up linux-libc-dev:amd64 (6.14.0-10.10) ... 100s Setting up libctf-nobfd0:amd64 (2.44-3ubuntu1) ... 100s Setting up systemd (257.3-1ubuntu3) ... 100s /usr/lib/tmpfiles.d/legacy.conf:14: Duplicate line for path "/run/lock", ignoring. 100s Created symlink '/run/systemd/system/tmp.mount' → '/dev/null'. 100s /usr/lib/tmpfiles.d/legacy.conf:14: Duplicate line for path "/run/lock", ignoring. 101s Setting up libparted2t64:amd64 (3.6-5) ... 101s Removing 'diversion of /lib/x86_64-linux-gnu/libparted.so.2 to /lib/x86_64-linux-gnu/libparted.so.2.usr-is-merged by libparted2t64' 101s Removing 'diversion of /lib/x86_64-linux-gnu/libparted.so.2.0.5 to /lib/x86_64-linux-gnu/libparted.so.2.0.5.usr-is-merged by libparted2t64' 101s Setting up linux-headers-generic (6.14.0-10.10) ... 101s Setting up libjemalloc2:amd64 (5.3.0-3) ... 101s Setting up locales (2.41-1ubuntu1) ... 101s Installing new version of config file /etc/locale.alias ... 102s Generating locales (this might take a while)... 103s en_US.UTF-8... done 103s Generation complete. 103s Setting up libsframe1:amd64 (2.44-3ubuntu1) ... 103s Setting up libpython3.13-minimal:amd64 (3.13.2-2) ... 103s Setting up apparmor (4.1.0~beta5-0ubuntu8) ... 103s Installing new version of config file /etc/apparmor.d/fusermount3 ... 103s Installing new version of config file /etc/apparmor.d/lsusb ... 103s Installing new version of config file /etc/apparmor.d/openvpn ... 104s Reloading AppArmor profiles 105s Setting up libftdi1-2:amd64 (1.5-8build1) ... 105s Setting up libglib2.0-data (2.84.0-1) ... 105s Setting up systemd-cryptsetup (257.3-1ubuntu3) ... 105s Setting up libncurses6:amd64 (6.5+20250216-2) ... 105s Setting up strace (6.13+ds-1ubuntu1) ... 105s Setting up xz-utils (5.6.4-1) ... 105s Setting up systemd-timesyncd (257.3-1ubuntu3) ... 106s systemd-time-wait-sync.service is a disabled or a static unit not running, not starting it. 106s Setting up libatomic1:amd64 (15-20250222-0ubuntu1) ... 106s Setting up udev (257.3-1ubuntu3) ... 107s Setting up linux-modules-6.14.0-10-generic (6.14.0-10.10) ... 109s Setting up libncursesw6:amd64 (6.5+20250216-2) ... 109s Setting up libpci3:amd64 (1:3.13.0-2) ... 109s Setting up whiptail (0.52.24-4ubuntu2) ... 109s Setting up python-apt-common (2.9.9build1) ... 109s Setting up pnp.ids (0.393-3) ... 109s Setting up libnl-3-200:amd64 (3.7.0-1) ... 109s Setting up python3.13-minimal (3.13.2-2) ... 109s Setting up libgpgme11t64:amd64 (1.24.2-1ubuntu2) ... 109s Setting up libbinutils:amd64 (2.44-3ubuntu1) ... 109s Setting up libc-dev-bin (2.41-1ubuntu1) ... 109s Setting up libpython3.13-stdlib:amd64 (3.13.2-2) ... 109s Setting up libxml2:amd64 (2.12.7+dfsg+really2.9.14-0.2ubuntu5) ... 110s Setting up rsync (3.4.1+ds1-3) ... 110s rsync.service is a disabled or a static unit not running, not starting it. 110s Setting up python3.13-gdbm (3.13.2-2) ... 110s Setting up libpython3-stdlib:amd64 (3.13.2-2) ... 110s Setting up systemd-resolved (257.3-1ubuntu3) ... 111s Setting up initramfs-tools-bin (0.146ubuntu1) ... 111s Setting up ncurses-term (6.5+20250216-2) ... 111s Setting up libctf0:amd64 (2.44-3ubuntu1) ... 111s Setting up libpython3.13:amd64 (3.13.2-2) ... 111s Setting up pinentry-curses (1.3.1-2ubuntu3) ... 111s Setting up libdebuginfod1t64:amd64 (0.192-4) ... 111s Setting up systemd-sysv (257.3-1ubuntu3) ... 111s Setting up linux-headers-virtual (6.14.0-10.10) ... 111s Setting up libcurl4t64:amd64 (8.12.1-3ubuntu1) ... 111s Setting up python3.13 (3.13.2-2) ... 112s Setting up htop (3.4.0-2) ... 112s Setting up linux-image-6.14.0-10-generic (6.14.0-10.10) ... 114s I: /boot/vmlinuz.old is now a symlink to vmlinuz-6.12.0-16-generic 114s I: /boot/initrd.img.old is now a symlink to initrd.img-6.12.0-16-generic 114s I: /boot/vmlinuz is now a symlink to vmlinuz-6.14.0-10-generic 114s I: /boot/initrd.img is now a symlink to initrd.img-6.14.0-10-generic 114s Setting up parted (3.6-5) ... 114s Setting up libnss-systemd:amd64 (257.3-1ubuntu3) ... 114s Setting up python3 (3.13.2-2) ... 114s Setting up python3-newt:amd64 (0.52.24-4ubuntu2) ... 114s Setting up python3-markupsafe (2.1.5-1build4) ... 114s Setting up linux-modules-extra-6.14.0-10-generic (6.14.0-10.10) ... 116s Setting up libnl-route-3-200:amd64 (3.7.0-1) ... 116s Setting up hwdata (0.393-3) ... 116s Setting up python3-jinja2 (3.1.5-2ubuntu1) ... 116s Setting up libglib2.0-0t64:amd64 (2.84.0-1) ... 116s No schema files found: doing nothing. 116s Setting up libgprofng0:amd64 (2.44-3ubuntu1) ... 116s Setting up linux-perf (6.14.0-10.10) ... 116s Setting up gir1.2-glib-2.0:amd64 (2.84.0-1) ... 116s Setting up pciutils (1:3.13.0-2) ... 116s Setting up python3-rpds-py (0.21.0-2ubuntu2) ... 116s Setting up libmm-glib0:amd64 (1.23.4-0ubuntu3) ... 116s Setting up libnl-genl-3-200:amd64 (3.7.0-1) ... 116s Setting up libpam-systemd:amd64 (257.3-1ubuntu3) ... 117s Setting up libc6-dev:amd64 (2.41-1ubuntu1) ... 117s Setting up libgirepository-1.0-1:amd64 (1.83.4-1) ... 117s Setting up curl (8.12.1-3ubuntu1) ... 117s Setting up linux-image-virtual (6.14.0-10.10) ... 117s Setting up initramfs-tools-core (0.146ubuntu1) ... 117s Setting up linux-tools-common (6.14.0-10.10) ... 117s Setting up python3-systemd (235-1build6) ... 117s Setting up python3-cffi-backend:amd64 (1.17.1-2build2) ... 117s Setting up binutils-x86-64-linux-gnu (2.44-3ubuntu1) ... 117s Setting up linux-image-generic (6.14.0-10.10) ... 117s Setting up python3-dbus (1.3.2-5build5) ... 117s Setting up linux-tools-6.14.0-10 (6.14.0-10.10) ... 117s Setting up initramfs-tools (0.146ubuntu1) ... 117s Installing new version of config file /etc/kernel/postinst.d/initramfs-tools ... 117s Installing new version of config file /etc/kernel/postrm.d/initramfs-tools ... 117s update-initramfs: deferring update (trigger activated) 117s Setting up linux-generic (6.14.0-10.10) ... 117s Setting up ubuntu-minimal (1.549) ... 117s Setting up python3-apt (2.9.9build1) ... 117s Setting up python3-bcrypt (4.2.0-2.1build1) ... 117s Setting up python3-yaml (6.0.2-1build2) ... 117s Setting up libfwupd3:amd64 (2.0.6-4) ... 117s Setting up python3-lazr.uri (1.0.6-6) ... 117s Setting up binutils (2.44-3ubuntu1) ... 117s Setting up ubuntu-standard (1.549) ... 117s Setting up cloud-init-base (25.1-0ubuntu3) ... 119s Setting up linux-virtual (6.14.0-10.10) ... 119s Setting up gir1.2-girepository-2.0:amd64 (1.83.4-1) ... 119s Setting up python3-gi (3.50.0-4build1) ... 119s Setting up linux-tools-6.14.0-10-generic (6.14.0-10.10) ... 119s Setting up fwupd (2.0.6-4) ... 119s fwupd-refresh.service is a disabled or a static unit not running, not starting it. 119s fwupd.service is a disabled or a static unit not running, not starting it. 119s Setting up cloud-init (25.1-0ubuntu3) ... 119s Processing triggers for man-db (2.13.0-1) ... 121s Processing triggers for dbus (1.16.2-1ubuntu1) ... 121s Processing triggers for shared-mime-info (2.4-5) ... 121s Warning: program compiled against libxml 212 using older 209 121s Processing triggers for libc-bin (2.41-1ubuntu1) ... 121s Processing triggers for linux-image-6.14.0-10-generic (6.14.0-10.10) ... 121s /etc/kernel/postinst.d/initramfs-tools: 121s update-initramfs: Generating /boot/initrd.img-6.14.0-10-generic 121s W: No lz4 in /usr/bin:/sbin:/bin, using gzip 132s /etc/kernel/postinst.d/zz-update-grub: 132s Sourcing file `/etc/default/grub' 132s Sourcing file `/etc/default/grub.d/50-cloudimg-settings.cfg' 132s Sourcing file `/etc/default/grub.d/90-autopkgtest.cfg' 132s Generating grub configuration file ... 132s Found linux image: /boot/vmlinuz-6.14.0-10-generic 132s Found initrd image: /boot/initrd.img-6.14.0-10-generic 132s Found linux image: /boot/vmlinuz-6.12.0-16-generic 132s Found initrd image: /boot/initrd.img-6.12.0-16-generic 132s Found linux image: /boot/vmlinuz-6.11.0-8-generic 132s Found initrd image: /boot/initrd.img-6.11.0-8-generic 132s Warning: os-prober will not be executed to detect other bootable partitions. 132s Systems on them will not be added to the GRUB boot configuration. 132s Check GRUB_DISABLE_OS_PROBER documentation entry. 132s Adding boot menu entry for UEFI Firmware Settings ... 132s done 132s Processing triggers for initramfs-tools (0.146ubuntu1) ... 132s update-initramfs: Generating /boot/initrd.img-6.14.0-10-generic 132s W: No lz4 in /usr/bin:/sbin:/bin, using gzip 143s Reading package lists... 143s Building dependency tree... 143s Reading state information... 143s Solving dependencies... 143s The following packages will be REMOVED: 143s libnl-genl-3-200* libnsl2* libpython3.12-minimal* libpython3.12-stdlib* 143s libpython3.12t64* linux-headers-6.11.0-8* linux-headers-6.11.0-8-generic* 143s linux-headers-6.12.0-16* linux-headers-6.12.0-16-generic* 143s linux-image-6.11.0-8-generic* linux-image-6.12.0-16-generic* 143s linux-modules-6.11.0-8-generic* linux-modules-6.12.0-16-generic* 143s linux-modules-extra-6.12.0-16-generic* linux-tools-6.11.0-8* 143s linux-tools-6.11.0-8-generic* linux-tools-6.12.0-16* 143s linux-tools-6.12.0-16-generic* 143s 0 upgraded, 0 newly installed, 18 to remove and 5 not upgraded. 143s After this operation, 545 MB disk space will be freed. 144s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 148643 files and directories currently installed.) 144s Removing libnl-genl-3-200:amd64 (3.7.0-1) ... 144s Removing linux-tools-6.11.0-8-generic (6.11.0-8.8) ... 144s Removing linux-tools-6.11.0-8 (6.11.0-8.8) ... 144s Removing libpython3.12t64:amd64 (3.12.9-1) ... 144s Removing libpython3.12-stdlib:amd64 (3.12.9-1) ... 144s Removing libnsl2:amd64 (1.3.0-3build3) ... 144s Removing libpython3.12-minimal:amd64 (3.12.9-1) ... 144s Removing linux-headers-6.11.0-8-generic (6.11.0-8.8) ... 144s Removing linux-headers-6.11.0-8 (6.11.0-8.8) ... 146s Removing linux-headers-6.12.0-16-generic (6.12.0-16.16) ... 147s Removing linux-headers-6.12.0-16 (6.12.0-16.16) ... 149s Removing linux-image-6.11.0-8-generic (6.11.0-8.8) ... 149s /etc/kernel/postrm.d/initramfs-tools: 149s update-initramfs: Deleting /boot/initrd.img-6.11.0-8-generic 149s /etc/kernel/postrm.d/zz-update-grub: 149s Sourcing file `/etc/default/grub' 149s Sourcing file `/etc/default/grub.d/50-cloudimg-settings.cfg' 149s Sourcing file `/etc/default/grub.d/90-autopkgtest.cfg' 149s Generating grub configuration file ... 149s Found linux image: /boot/vmlinuz-6.14.0-10-generic 149s Found initrd image: /boot/initrd.img-6.14.0-10-generic 150s Found linux image: /boot/vmlinuz-6.12.0-16-generic 150s Found initrd image: /boot/initrd.img-6.12.0-16-generic 150s Warning: os-prober will not be executed to detect other bootable partitions. 150s Systems on them will not be added to the GRUB boot configuration. 150s Check GRUB_DISABLE_OS_PROBER documentation entry. 150s Adding boot menu entry for UEFI Firmware Settings ... 150s done 150s Removing linux-image-6.12.0-16-generic (6.12.0-16.16) ... 150s W: Removing the running kernel 150s I: /boot/vmlinuz.old is now a symlink to vmlinuz-6.14.0-10-generic 150s I: /boot/initrd.img.old is now a symlink to initrd.img-6.14.0-10-generic 150s /etc/kernel/postrm.d/initramfs-tools: 150s update-initramfs: Deleting /boot/initrd.img-6.12.0-16-generic 150s /etc/kernel/postrm.d/zz-update-grub: 150s Sourcing file `/etc/default/grub' 150s Sourcing file `/etc/default/grub.d/50-cloudimg-settings.cfg' 150s Sourcing file `/etc/default/grub.d/90-autopkgtest.cfg' 150s Generating grub configuration file ... 150s Found linux image: /boot/vmlinuz-6.14.0-10-generic 150s Found initrd image: /boot/initrd.img-6.14.0-10-generic 151s Warning: os-prober will not be executed to detect other bootable partitions. 151s Systems on them will not be added to the GRUB boot configuration. 151s Check GRUB_DISABLE_OS_PROBER documentation entry. 151s Adding boot menu entry for UEFI Firmware Settings ... 151s done 151s Removing linux-modules-6.11.0-8-generic (6.11.0-8.8) ... 151s Removing linux-modules-extra-6.12.0-16-generic (6.12.0-16.16) ... 152s Removing linux-modules-6.12.0-16-generic (6.12.0-16.16) ... 152s Removing linux-tools-6.12.0-16-generic (6.12.0-16.16) ... 152s Removing linux-tools-6.12.0-16 (6.12.0-16.16) ... 152s Processing triggers for libc-bin (2.41-1ubuntu1) ... 153s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 76972 files and directories currently installed.) 153s Purging configuration files for linux-image-6.11.0-8-generic (6.11.0-8.8) ... 153s Purging configuration files for libpython3.12-minimal:amd64 (3.12.9-1) ... 153s Purging configuration files for linux-modules-extra-6.12.0-16-generic (6.12.0-16.16) ... 153s Purging configuration files for linux-modules-6.12.0-16-generic (6.12.0-16.16) ... 153s dpkg: warning: while removing linux-modules-6.12.0-16-generic, directory '/lib/modules/6.12.0-16-generic' not empty so not removed 153s Purging configuration files for linux-modules-6.11.0-8-generic (6.11.0-8.8) ... 153s Purging configuration files for linux-image-6.12.0-16-generic (6.12.0-16.16) ... 153s rmdir: failed to remove '/lib/modules/6.12.0-16-generic': Directory not empty 153s autopkgtest [23:57:16]: upgrading testbed (apt dist-upgrade and autopurge) 153s Reading package lists... 153s Building dependency tree... 153s Reading state information... 154s Calculating upgrade...Starting pkgProblemResolver with broken count: 0 154s Starting 2 pkgProblemResolver with broken count: 0 154s Done 154s Entering ResolveByKeep 154s 155s Calculating upgrade... 155s The following packages will be upgraded: 155s libc-bin libc-dev-bin libc6 libc6-dev locales 155s 5 upgraded, 0 newly installed, 0 to remove and 0 not upgraded. 155s Need to get 10.5 MB of archives. 155s After this operation, 1024 B of additional disk space will be used. 155s Get:1 http://ftpmaster.internal/ubuntu plucky-proposed/main amd64 libc6-dev amd64 2.41-1ubuntu2 [2183 kB] 156s Get:2 http://ftpmaster.internal/ubuntu plucky-proposed/main amd64 libc-dev-bin amd64 2.41-1ubuntu2 [24.7 kB] 156s Get:3 http://ftpmaster.internal/ubuntu plucky-proposed/main amd64 libc6 amd64 2.41-1ubuntu2 [3327 kB] 156s Get:4 http://ftpmaster.internal/ubuntu plucky-proposed/main amd64 libc-bin amd64 2.41-1ubuntu2 [700 kB] 156s Get:5 http://ftpmaster.internal/ubuntu plucky-proposed/main amd64 locales all 2.41-1ubuntu2 [4246 kB] 156s Preconfiguring packages ... 156s Fetched 10.5 MB in 1s (8897 kB/s) 156s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 76968 files and directories currently installed.) 156s Preparing to unpack .../libc6-dev_2.41-1ubuntu2_amd64.deb ... 156s Unpacking libc6-dev:amd64 (2.41-1ubuntu2) over (2.41-1ubuntu1) ... 157s Preparing to unpack .../libc-dev-bin_2.41-1ubuntu2_amd64.deb ... 157s Unpacking libc-dev-bin (2.41-1ubuntu2) over (2.41-1ubuntu1) ... 157s Preparing to unpack .../libc6_2.41-1ubuntu2_amd64.deb ... 157s Unpacking libc6:amd64 (2.41-1ubuntu2) over (2.41-1ubuntu1) ... 157s Setting up libc6:amd64 (2.41-1ubuntu2) ... 157s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 76968 files and directories currently installed.) 157s Preparing to unpack .../libc-bin_2.41-1ubuntu2_amd64.deb ... 157s Unpacking libc-bin (2.41-1ubuntu2) over (2.41-1ubuntu1) ... 157s Setting up libc-bin (2.41-1ubuntu2) ... 157s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 76968 files and directories currently installed.) 157s Preparing to unpack .../locales_2.41-1ubuntu2_all.deb ... 157s Unpacking locales (2.41-1ubuntu2) over (2.41-1ubuntu1) ... 157s Setting up locales (2.41-1ubuntu2) ... 158s Generating locales (this might take a while)... 159s en_US.UTF-8... done 159s Generation complete. 160s Setting up libc-dev-bin (2.41-1ubuntu2) ... 160s Setting up libc6-dev:amd64 (2.41-1ubuntu2) ... 160s Processing triggers for man-db (2.13.0-1) ... 160s Processing triggers for systemd (257.3-1ubuntu3) ... 161s Reading package lists... 161s Building dependency tree... 161s Reading state information... 162s Starting pkgProblemResolver with broken count: 0 162s Starting 2 pkgProblemResolver with broken count: 0 162s Done 162s Solving dependencies... 162s 0 upgraded, 0 newly installed, 0 to remove and 0 not upgraded. 162s autopkgtest [23:57:25]: rebooting testbed after setup commands that affected boot 186s autopkgtest [23:57:49]: testbed running kernel: Linux 6.14.0-10-generic #10-Ubuntu SMP PREEMPT_DYNAMIC Wed Mar 12 16:07:00 UTC 2025 189s autopkgtest [23:57:52]: @@@@@@@@@@@@@@@@@@@@ apt-source yosys 193s Get:1 http://ftpmaster.internal/ubuntu plucky/universe yosys 0.33-5build2 (dsc) [3069 B] 193s Get:2 http://ftpmaster.internal/ubuntu plucky/universe yosys 0.33-5build2 (tar) [6161 kB] 193s Get:3 http://ftpmaster.internal/ubuntu plucky/universe yosys 0.33-5build2 (tar) [2586 kB] 193s Get:4 http://ftpmaster.internal/ubuntu plucky/universe yosys 0.33-5build2 (diff) [30.3 kB] 193s gpgv: Signature made Mon Apr 1 04:53:46 2024 UTC 193s gpgv: using RSA key A089FB36AAFBDAD5ACC1325069F790171A210984 193s gpgv: Can't check signature: No public key 193s dpkg-source: warning: cannot verify inline signature for ./yosys_0.33-5build2.dsc: no acceptable signature found 193s autopkgtest [23:57:56]: testing package yosys version 0.33-5build2 194s autopkgtest [23:57:57]: build not needed 198s autopkgtest [23:58:01]: test yosys-testsuite: preparing testbed 199s Reading package lists... 199s Building dependency tree... 199s Reading state information... 199s Starting pkgProblemResolver with broken count: 0 199s Starting 2 pkgProblemResolver with broken count: 0 199s Done 200s The following NEW packages will be installed: 200s cpp cpp-14 cpp-14-x86-64-linux-gnu cpp-x86-64-linux-gnu g++ g++-14 200s g++-14-x86-64-linux-gnu g++-x86-64-linux-gnu gcc gcc-14 200s gcc-14-x86-64-linux-gnu gcc-x86-64-linux-gnu iverilog libasan8 libcc1-0 200s libffi-dev libgcc-14-dev libgomp1 libhwasan0 libisl23 libitm1 liblsan0 200s libmpc3 libncurses-dev libpkgconf3 libquadmath0 libreadline-dev 200s libstdc++-14-dev libtcl8.6 libtsan2 libubsan1 pkg-config pkgconf pkgconf-bin 200s python3-click tcl tcl-dev tcl8.6 tcl8.6-dev yosys yosys-abc yosys-dev 200s zlib1g-dev 200s 0 upgraded, 43 newly installed, 0 to remove and 0 not upgraded. 200s Need to get 80.8 MB of archives. 200s After this operation, 273 MB of additional disk space will be used. 200s Get:1 http://ftpmaster.internal/ubuntu plucky/main amd64 libisl23 amd64 0.27-1 [685 kB] 200s Get:2 http://ftpmaster.internal/ubuntu plucky/main amd64 libmpc3 amd64 1.3.1-1build2 [55.3 kB] 200s Get:3 http://ftpmaster.internal/ubuntu plucky/main amd64 cpp-14-x86-64-linux-gnu amd64 14.2.0-17ubuntu3 [11.9 MB] 201s Get:4 http://ftpmaster.internal/ubuntu plucky/main amd64 cpp-14 amd64 14.2.0-17ubuntu3 [1030 B] 201s Get:5 http://ftpmaster.internal/ubuntu plucky/main amd64 cpp-x86-64-linux-gnu amd64 4:14.2.0-1ubuntu1 [5586 B] 201s Get:6 http://ftpmaster.internal/ubuntu plucky/main amd64 cpp amd64 4:14.2.0-1ubuntu1 [22.4 kB] 201s Get:7 http://ftpmaster.internal/ubuntu plucky/main amd64 libcc1-0 amd64 15-20250222-0ubuntu1 [47.0 kB] 201s Get:8 http://ftpmaster.internal/ubuntu plucky/main amd64 libgomp1 amd64 15-20250222-0ubuntu1 [148 kB] 201s Get:9 http://ftpmaster.internal/ubuntu plucky/main amd64 libitm1 amd64 15-20250222-0ubuntu1 [28.6 kB] 201s Get:10 http://ftpmaster.internal/ubuntu plucky/main amd64 libasan8 amd64 15-20250222-0ubuntu1 [3055 kB] 201s Get:11 http://ftpmaster.internal/ubuntu plucky/main amd64 liblsan0 amd64 15-20250222-0ubuntu1 [1355 kB] 201s Get:12 http://ftpmaster.internal/ubuntu plucky/main amd64 libtsan2 amd64 15-20250222-0ubuntu1 [2756 kB] 201s Get:13 http://ftpmaster.internal/ubuntu plucky/main amd64 libubsan1 amd64 15-20250222-0ubuntu1 [1205 kB] 201s Get:14 http://ftpmaster.internal/ubuntu plucky/main amd64 libhwasan0 amd64 15-20250222-0ubuntu1 [1677 kB] 201s Get:15 http://ftpmaster.internal/ubuntu plucky/main amd64 libquadmath0 amd64 15-20250222-0ubuntu1 [152 kB] 201s Get:16 http://ftpmaster.internal/ubuntu plucky/main amd64 libgcc-14-dev amd64 14.2.0-17ubuntu3 [2816 kB] 201s Get:17 http://ftpmaster.internal/ubuntu plucky/main amd64 gcc-14-x86-64-linux-gnu amd64 14.2.0-17ubuntu3 [23.3 MB] 202s Get:18 http://ftpmaster.internal/ubuntu plucky/main amd64 gcc-14 amd64 14.2.0-17ubuntu3 [536 kB] 202s Get:19 http://ftpmaster.internal/ubuntu plucky/main amd64 gcc-x86-64-linux-gnu amd64 4:14.2.0-1ubuntu1 [1208 B] 202s Get:20 http://ftpmaster.internal/ubuntu plucky/main amd64 gcc amd64 4:14.2.0-1ubuntu1 [5004 B] 202s Get:21 http://ftpmaster.internal/ubuntu plucky/main amd64 libstdc++-14-dev amd64 14.2.0-17ubuntu3 [2486 kB] 202s Get:22 http://ftpmaster.internal/ubuntu plucky/main amd64 g++-14-x86-64-linux-gnu amd64 14.2.0-17ubuntu3 [13.4 MB] 202s Get:23 http://ftpmaster.internal/ubuntu plucky/main amd64 g++-14 amd64 14.2.0-17ubuntu3 [21.8 kB] 202s Get:24 http://ftpmaster.internal/ubuntu plucky/main amd64 g++-x86-64-linux-gnu amd64 4:14.2.0-1ubuntu1 [968 B] 202s Get:25 http://ftpmaster.internal/ubuntu plucky/main amd64 g++ amd64 4:14.2.0-1ubuntu1 [1100 B] 202s Get:26 http://ftpmaster.internal/ubuntu plucky/universe amd64 iverilog amd64 12.0-2build2 [2126 kB] 202s Get:27 http://ftpmaster.internal/ubuntu plucky/main amd64 libncurses-dev amd64 6.5+20250216-2 [424 kB] 202s Get:28 http://ftpmaster.internal/ubuntu plucky/main amd64 libpkgconf3 amd64 1.8.1-4 [32.3 kB] 202s Get:29 http://ftpmaster.internal/ubuntu plucky/main amd64 libreadline-dev amd64 8.2-6 [184 kB] 202s Get:30 http://ftpmaster.internal/ubuntu plucky/main amd64 libtcl8.6 amd64 8.6.16+dfsg-1 [1086 kB] 202s Get:31 http://ftpmaster.internal/ubuntu plucky/main amd64 pkgconf-bin amd64 1.8.1-4 [21.6 kB] 202s Get:32 http://ftpmaster.internal/ubuntu plucky/main amd64 pkgconf amd64 1.8.1-4 [16.8 kB] 202s Get:33 http://ftpmaster.internal/ubuntu plucky/main amd64 pkg-config amd64 1.8.1-4 [7362 B] 202s Get:34 http://ftpmaster.internal/ubuntu plucky/main amd64 python3-click all 8.2.0+0.really.8.1.8-1 [80.0 kB] 202s Get:35 http://ftpmaster.internal/ubuntu plucky/main amd64 tcl8.6 amd64 8.6.16+dfsg-1 [14.9 kB] 202s Get:36 http://ftpmaster.internal/ubuntu plucky/main amd64 tcl amd64 8.6.14build1 [4124 B] 202s Get:37 http://ftpmaster.internal/ubuntu plucky/main amd64 zlib1g-dev amd64 1:1.3.dfsg+really1.3.1-1ubuntu1 [895 kB] 202s Get:38 http://ftpmaster.internal/ubuntu plucky/main amd64 tcl8.6-dev amd64 8.6.16+dfsg-1 [1081 kB] 202s Get:39 http://ftpmaster.internal/ubuntu plucky/main amd64 tcl-dev amd64 8.6.14build1 [5782 B] 202s Get:40 http://ftpmaster.internal/ubuntu plucky/universe amd64 yosys-abc amd64 0.33-5build2 [5829 kB] 202s Get:41 http://ftpmaster.internal/ubuntu plucky/universe amd64 yosys amd64 0.33-5build2 [3222 kB] 202s Get:42 http://ftpmaster.internal/ubuntu plucky/main amd64 libffi-dev amd64 3.4.7-1 [65.5 kB] 202s Get:43 http://ftpmaster.internal/ubuntu plucky/universe amd64 yosys-dev amd64 0.33-5build2 [88.4 kB] 203s Fetched 80.8 MB in 3s (30.6 MB/s) 203s Selecting previously unselected package libisl23:amd64. 203s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 76968 files and directories currently installed.) 203s Preparing to unpack .../00-libisl23_0.27-1_amd64.deb ... 203s Unpacking libisl23:amd64 (0.27-1) ... 203s Selecting previously unselected package libmpc3:amd64. 203s Preparing to unpack .../01-libmpc3_1.3.1-1build2_amd64.deb ... 203s Unpacking libmpc3:amd64 (1.3.1-1build2) ... 203s Selecting previously unselected package cpp-14-x86-64-linux-gnu. 203s Preparing to unpack .../02-cpp-14-x86-64-linux-gnu_14.2.0-17ubuntu3_amd64.deb ... 203s Unpacking cpp-14-x86-64-linux-gnu (14.2.0-17ubuntu3) ... 203s Selecting previously unselected package cpp-14. 203s Preparing to unpack .../03-cpp-14_14.2.0-17ubuntu3_amd64.deb ... 203s Unpacking cpp-14 (14.2.0-17ubuntu3) ... 203s Selecting previously unselected package cpp-x86-64-linux-gnu. 203s Preparing to unpack .../04-cpp-x86-64-linux-gnu_4%3a14.2.0-1ubuntu1_amd64.deb ... 203s Unpacking cpp-x86-64-linux-gnu (4:14.2.0-1ubuntu1) ... 203s Selecting previously unselected package cpp. 203s Preparing to unpack .../05-cpp_4%3a14.2.0-1ubuntu1_amd64.deb ... 203s Unpacking cpp (4:14.2.0-1ubuntu1) ... 203s Selecting previously unselected package libcc1-0:amd64. 203s Preparing to unpack .../06-libcc1-0_15-20250222-0ubuntu1_amd64.deb ... 203s Unpacking libcc1-0:amd64 (15-20250222-0ubuntu1) ... 203s Selecting previously unselected package libgomp1:amd64. 203s Preparing to unpack .../07-libgomp1_15-20250222-0ubuntu1_amd64.deb ... 203s Unpacking libgomp1:amd64 (15-20250222-0ubuntu1) ... 203s Selecting previously unselected package libitm1:amd64. 203s Preparing to unpack .../08-libitm1_15-20250222-0ubuntu1_amd64.deb ... 203s Unpacking libitm1:amd64 (15-20250222-0ubuntu1) ... 203s Selecting previously unselected package libasan8:amd64. 203s Preparing to unpack .../09-libasan8_15-20250222-0ubuntu1_amd64.deb ... 203s Unpacking libasan8:amd64 (15-20250222-0ubuntu1) ... 203s Selecting previously unselected package liblsan0:amd64. 203s Preparing to unpack .../10-liblsan0_15-20250222-0ubuntu1_amd64.deb ... 203s Unpacking liblsan0:amd64 (15-20250222-0ubuntu1) ... 203s Selecting previously unselected package libtsan2:amd64. 203s Preparing to unpack .../11-libtsan2_15-20250222-0ubuntu1_amd64.deb ... 203s Unpacking libtsan2:amd64 (15-20250222-0ubuntu1) ... 204s Selecting previously unselected package libubsan1:amd64. 204s Preparing to unpack .../12-libubsan1_15-20250222-0ubuntu1_amd64.deb ... 204s Unpacking libubsan1:amd64 (15-20250222-0ubuntu1) ... 204s Selecting previously unselected package libhwasan0:amd64. 204s Preparing to unpack .../13-libhwasan0_15-20250222-0ubuntu1_amd64.deb ... 204s Unpacking libhwasan0:amd64 (15-20250222-0ubuntu1) ... 204s Selecting previously unselected package libquadmath0:amd64. 204s Preparing to unpack .../14-libquadmath0_15-20250222-0ubuntu1_amd64.deb ... 204s Unpacking libquadmath0:amd64 (15-20250222-0ubuntu1) ... 204s Selecting previously unselected package libgcc-14-dev:amd64. 204s Preparing to unpack .../15-libgcc-14-dev_14.2.0-17ubuntu3_amd64.deb ... 204s Unpacking libgcc-14-dev:amd64 (14.2.0-17ubuntu3) ... 204s Selecting previously unselected package gcc-14-x86-64-linux-gnu. 204s Preparing to unpack .../16-gcc-14-x86-64-linux-gnu_14.2.0-17ubuntu3_amd64.deb ... 204s Unpacking gcc-14-x86-64-linux-gnu (14.2.0-17ubuntu3) ... 204s Selecting previously unselected package gcc-14. 204s Preparing to unpack .../17-gcc-14_14.2.0-17ubuntu3_amd64.deb ... 204s Unpacking gcc-14 (14.2.0-17ubuntu3) ... 204s Selecting previously unselected package gcc-x86-64-linux-gnu. 204s Preparing to unpack .../18-gcc-x86-64-linux-gnu_4%3a14.2.0-1ubuntu1_amd64.deb ... 204s Unpacking gcc-x86-64-linux-gnu (4:14.2.0-1ubuntu1) ... 204s Selecting previously unselected package gcc. 204s Preparing to unpack .../19-gcc_4%3a14.2.0-1ubuntu1_amd64.deb ... 204s Unpacking gcc (4:14.2.0-1ubuntu1) ... 204s Selecting previously unselected package libstdc++-14-dev:amd64. 204s Preparing to unpack .../20-libstdc++-14-dev_14.2.0-17ubuntu3_amd64.deb ... 204s Unpacking libstdc++-14-dev:amd64 (14.2.0-17ubuntu3) ... 204s Selecting previously unselected package g++-14-x86-64-linux-gnu. 204s Preparing to unpack .../21-g++-14-x86-64-linux-gnu_14.2.0-17ubuntu3_amd64.deb ... 204s Unpacking g++-14-x86-64-linux-gnu (14.2.0-17ubuntu3) ... 205s Selecting previously unselected package g++-14. 205s Preparing to unpack .../22-g++-14_14.2.0-17ubuntu3_amd64.deb ... 205s Unpacking g++-14 (14.2.0-17ubuntu3) ... 205s Selecting previously unselected package g++-x86-64-linux-gnu. 205s Preparing to unpack .../23-g++-x86-64-linux-gnu_4%3a14.2.0-1ubuntu1_amd64.deb ... 205s Unpacking g++-x86-64-linux-gnu (4:14.2.0-1ubuntu1) ... 205s Selecting previously unselected package g++. 205s Preparing to unpack .../24-g++_4%3a14.2.0-1ubuntu1_amd64.deb ... 205s Unpacking g++ (4:14.2.0-1ubuntu1) ... 205s Selecting previously unselected package iverilog. 205s Preparing to unpack .../25-iverilog_12.0-2build2_amd64.deb ... 205s Unpacking iverilog (12.0-2build2) ... 205s Selecting previously unselected package libncurses-dev:amd64. 205s Preparing to unpack .../26-libncurses-dev_6.5+20250216-2_amd64.deb ... 205s Unpacking libncurses-dev:amd64 (6.5+20250216-2) ... 205s Selecting previously unselected package libpkgconf3:amd64. 205s Preparing to unpack .../27-libpkgconf3_1.8.1-4_amd64.deb ... 205s Unpacking libpkgconf3:amd64 (1.8.1-4) ... 205s Selecting previously unselected package libreadline-dev:amd64. 205s Preparing to unpack .../28-libreadline-dev_8.2-6_amd64.deb ... 205s Unpacking libreadline-dev:amd64 (8.2-6) ... 205s Selecting previously unselected package libtcl8.6:amd64. 205s Preparing to unpack .../29-libtcl8.6_8.6.16+dfsg-1_amd64.deb ... 205s Unpacking libtcl8.6:amd64 (8.6.16+dfsg-1) ... 205s Selecting previously unselected package pkgconf-bin. 205s Preparing to unpack .../30-pkgconf-bin_1.8.1-4_amd64.deb ... 205s Unpacking pkgconf-bin (1.8.1-4) ... 205s Selecting previously unselected package pkgconf:amd64. 205s Preparing to unpack .../31-pkgconf_1.8.1-4_amd64.deb ... 205s Unpacking pkgconf:amd64 (1.8.1-4) ... 205s Selecting previously unselected package pkg-config:amd64. 205s Preparing to unpack .../32-pkg-config_1.8.1-4_amd64.deb ... 205s Unpacking pkg-config:amd64 (1.8.1-4) ... 205s Selecting previously unselected package python3-click. 205s Preparing to unpack .../33-python3-click_8.2.0+0.really.8.1.8-1_all.deb ... 205s Unpacking python3-click (8.2.0+0.really.8.1.8-1) ... 205s Selecting previously unselected package tcl8.6. 205s Preparing to unpack .../34-tcl8.6_8.6.16+dfsg-1_amd64.deb ... 205s Unpacking tcl8.6 (8.6.16+dfsg-1) ... 205s Selecting previously unselected package tcl. 205s Preparing to unpack .../35-tcl_8.6.14build1_amd64.deb ... 205s Unpacking tcl (8.6.14build1) ... 205s Selecting previously unselected package zlib1g-dev:amd64. 205s Preparing to unpack .../36-zlib1g-dev_1%3a1.3.dfsg+really1.3.1-1ubuntu1_amd64.deb ... 205s Unpacking zlib1g-dev:amd64 (1:1.3.dfsg+really1.3.1-1ubuntu1) ... 205s Selecting previously unselected package tcl8.6-dev:amd64. 205s Preparing to unpack .../37-tcl8.6-dev_8.6.16+dfsg-1_amd64.deb ... 205s Unpacking tcl8.6-dev:amd64 (8.6.16+dfsg-1) ... 205s Selecting previously unselected package tcl-dev:amd64. 205s Preparing to unpack .../38-tcl-dev_8.6.14build1_amd64.deb ... 205s Unpacking tcl-dev:amd64 (8.6.14build1) ... 205s Selecting previously unselected package yosys-abc. 205s Preparing to unpack .../39-yosys-abc_0.33-5build2_amd64.deb ... 205s Unpacking yosys-abc (0.33-5build2) ... 205s Selecting previously unselected package yosys. 205s Preparing to unpack .../40-yosys_0.33-5build2_amd64.deb ... 205s Unpacking yosys (0.33-5build2) ... 205s Selecting previously unselected package libffi-dev:amd64. 205s Preparing to unpack .../41-libffi-dev_3.4.7-1_amd64.deb ... 205s Unpacking libffi-dev:amd64 (3.4.7-1) ... 205s Selecting previously unselected package yosys-dev. 205s Preparing to unpack .../42-yosys-dev_0.33-5build2_amd64.deb ... 205s Unpacking yosys-dev (0.33-5build2) ... 205s Setting up libncurses-dev:amd64 (6.5+20250216-2) ... 205s Setting up yosys-abc (0.33-5build2) ... 205s Setting up libreadline-dev:amd64 (8.2-6) ... 205s Setting up libgomp1:amd64 (15-20250222-0ubuntu1) ... 205s Setting up python3-click (8.2.0+0.really.8.1.8-1) ... 206s Setting up libffi-dev:amd64 (3.4.7-1) ... 206s Setting up iverilog (12.0-2build2) ... 206s Setting up libpkgconf3:amd64 (1.8.1-4) ... 206s Setting up libquadmath0:amd64 (15-20250222-0ubuntu1) ... 206s Setting up libmpc3:amd64 (1.3.1-1build2) ... 206s Setting up libtcl8.6:amd64 (8.6.16+dfsg-1) ... 206s Setting up pkgconf-bin (1.8.1-4) ... 206s Setting up libubsan1:amd64 (15-20250222-0ubuntu1) ... 206s Setting up zlib1g-dev:amd64 (1:1.3.dfsg+really1.3.1-1ubuntu1) ... 206s Setting up libhwasan0:amd64 (15-20250222-0ubuntu1) ... 206s Setting up libasan8:amd64 (15-20250222-0ubuntu1) ... 206s Setting up libtsan2:amd64 (15-20250222-0ubuntu1) ... 206s Setting up libisl23:amd64 (0.27-1) ... 206s Setting up libcc1-0:amd64 (15-20250222-0ubuntu1) ... 206s Setting up liblsan0:amd64 (15-20250222-0ubuntu1) ... 206s Setting up libitm1:amd64 (15-20250222-0ubuntu1) ... 206s Setting up tcl8.6 (8.6.16+dfsg-1) ... 206s Setting up tcl8.6-dev:amd64 (8.6.16+dfsg-1) ... 206s Setting up yosys (0.33-5build2) ... 206s Setting up pkgconf:amd64 (1.8.1-4) ... 206s Setting up pkg-config:amd64 (1.8.1-4) ... 206s Setting up cpp-14-x86-64-linux-gnu (14.2.0-17ubuntu3) ... 206s Setting up cpp-14 (14.2.0-17ubuntu3) ... 206s Setting up tcl (8.6.14build1) ... 206s Setting up libgcc-14-dev:amd64 (14.2.0-17ubuntu3) ... 206s Setting up libstdc++-14-dev:amd64 (14.2.0-17ubuntu3) ... 206s Setting up cpp-x86-64-linux-gnu (4:14.2.0-1ubuntu1) ... 206s Setting up tcl-dev:amd64 (8.6.14build1) ... 206s Setting up cpp (4:14.2.0-1ubuntu1) ... 206s Setting up gcc-14-x86-64-linux-gnu (14.2.0-17ubuntu3) ... 206s Setting up yosys-dev (0.33-5build2) ... 206s Setting up gcc-x86-64-linux-gnu (4:14.2.0-1ubuntu1) ... 206s Setting up gcc-14 (14.2.0-17ubuntu3) ... 206s Setting up g++-14-x86-64-linux-gnu (14.2.0-17ubuntu3) ... 206s Setting up g++-x86-64-linux-gnu (4:14.2.0-1ubuntu1) ... 206s Setting up g++-14 (14.2.0-17ubuntu3) ... 206s Setting up gcc (4:14.2.0-1ubuntu1) ... 206s Setting up g++ (4:14.2.0-1ubuntu1) ... 206s update-alternatives: using /usr/bin/g++ to provide /usr/bin/c++ (c++) in auto mode 206s Processing triggers for libc-bin (2.41-1ubuntu2) ... 206s Processing triggers for man-db (2.13.0-1) ... 207s Processing triggers for install-info (7.1.1-1) ... 209s autopkgtest [23:58:12]: test yosys-testsuite: [----------------------- 209s + [ 1 -ge 1 ] 209s + testdir=. 209s + shift 209s + mkdir -p . 209s + cd . 209s + ln -sf /usr/bin/yosys . 209s + ln -sf /usr/bin/yosys-abc . 209s + ln -sf /usr/bin/yosys-config . 209s + sed -i s/^test:.*/test: $(EXTRA_TARGETS)/ Makefile 209s + make test CONFIG=gcc ABCPULL=0 209s mkdir -p share/include/kernel/ 209s cp "./"/kernel/yosys.h share/include/kernel/yosys.h 209s mkdir -p share/include/kernel/ 209s cp "./"/kernel/hashlib.h share/include/kernel/hashlib.h 209s mkdir -p share/include/kernel/ 209s cp "./"/kernel/log.h share/include/kernel/log.h 209s mkdir -p share/include/kernel/ 209s cp "./"/kernel/rtlil.h share/include/kernel/rtlil.h 209s mkdir -p share/include/kernel/ 209s cp "./"/kernel/binding.h share/include/kernel/binding.h 209s mkdir -p share/include/kernel/ 209s cp "./"/kernel/register.h share/include/kernel/register.h 209s mkdir -p share/include/kernel/ 209s cp "./"/kernel/cellaigs.h share/include/kernel/cellaigs.h 209s mkdir -p share/include/kernel/ 209s cp "./"/kernel/celltypes.h share/include/kernel/celltypes.h 209s mkdir -p share/include/kernel/ 209s cp "./"/kernel/celledges.h share/include/kernel/celledges.h 209s mkdir -p share/include/kernel/ 209s cp "./"/kernel/consteval.h share/include/kernel/consteval.h 209s mkdir -p share/include/kernel/ 209s cp "./"/kernel/constids.inc share/include/kernel/constids.inc 209s mkdir -p share/include/kernel/ 209s cp "./"/kernel/sigtools.h share/include/kernel/sigtools.h 209s mkdir -p share/include/kernel/ 209s cp "./"/kernel/modtools.h share/include/kernel/modtools.h 209s mkdir -p share/include/kernel/ 209s cp "./"/kernel/macc.h share/include/kernel/macc.h 209s mkdir -p share/include/kernel/ 209s cp "./"/kernel/utils.h share/include/kernel/utils.h 209s mkdir -p share/include/kernel/ 209s cp "./"/kernel/satgen.h share/include/kernel/satgen.h 209s mkdir -p share/include/kernel/ 209s cp "./"/kernel/qcsat.h share/include/kernel/qcsat.h 209s mkdir -p share/include/kernel/ 209s cp "./"/kernel/ff.h share/include/kernel/ff.h 209s mkdir -p share/include/kernel/ 209s cp "./"/kernel/ffinit.h share/include/kernel/ffinit.h 209s mkdir -p share/include/kernel/ 209s cp "./"/kernel/fstdata.h share/include/kernel/fstdata.h 209s mkdir -p share/include/kernel/ 209s cp "./"/kernel/mem.h share/include/kernel/mem.h 209s mkdir -p share/include/kernel/ 209s cp "./"/kernel/yw.h share/include/kernel/yw.h 209s mkdir -p share/include/kernel/ 209s cp "./"/kernel/json.h share/include/kernel/json.h 209s mkdir -p share/include/libs/ezsat/ 209s cp "./"/libs/ezsat/ezsat.h share/include/libs/ezsat/ezsat.h 209s mkdir -p share/include/libs/ezsat/ 209s cp "./"/libs/ezsat/ezminisat.h share/include/libs/ezsat/ezminisat.h 209s mkdir -p share/include/libs/fst/ 209s cp "./"/libs/fst/fstapi.h share/include/libs/fst/fstapi.h 209s mkdir -p share/include/libs/sha1/ 209s cp "./"/libs/sha1/sha1.h share/include/libs/sha1/sha1.h 209s mkdir -p share/include/libs/json11/ 209s cp "./"/libs/json11/json11.hpp share/include/libs/json11/json11.hpp 209s mkdir -p share/include/passes/fsm/ 209s cp "./"/passes/fsm/fsmdata.h share/include/passes/fsm/fsmdata.h 209s mkdir -p share/include/frontends/ast/ 209s cp "./"/frontends/ast/ast.h share/include/frontends/ast/ast.h 209s mkdir -p share/include/frontends/ast/ 209s cp "./"/frontends/ast/ast_binding.h share/include/frontends/ast/ast_binding.h 209s mkdir -p share/include/frontends/blif/ 209s cp "./"/frontends/blif/blifparse.h share/include/frontends/blif/blifparse.h 209s mkdir -p share/include/backends/rtlil/ 209s cp "./"/backends/rtlil/rtlil_backend.h share/include/backends/rtlil/rtlil_backend.h 209s mkdir -p share/include/backends/cxxrtl/ 209s cp "./"/backends/cxxrtl/cxxrtl.h share/include/backends/cxxrtl/cxxrtl.h 209s mkdir -p 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"./"/techlibs/efinix/brams_map.v share/efinix/brams_map.v 209s mkdir -p share/efinix 209s cp "./"/techlibs/efinix/gbuf_map.v share/efinix/gbuf_map.v 209s mkdir -p share/efinix 209s cp "./"/techlibs/efinix/brams.txt share/efinix/brams.txt 209s mkdir -p share/fabulous 209s cp "./"/techlibs/fabulous/cells_map.v share/fabulous/cells_map.v 209s mkdir -p share/fabulous 209s cp "./"/techlibs/fabulous/prims.v share/fabulous/prims.v 209s mkdir -p share/fabulous 209s cp "./"/techlibs/fabulous/latches_map.v share/fabulous/latches_map.v 209s mkdir -p share/fabulous 209s cp "./"/techlibs/fabulous/ff_map.v share/fabulous/ff_map.v 209s mkdir -p share/fabulous 209s cp "./"/techlibs/fabulous/ram_regfile.txt share/fabulous/ram_regfile.txt 209s mkdir -p share/fabulous 209s cp "./"/techlibs/fabulous/regfile_map.v share/fabulous/regfile_map.v 209s mkdir -p share/fabulous 209s cp "./"/techlibs/fabulous/io_map.v share/fabulous/io_map.v 209s mkdir -p share/fabulous 209s cp "./"/techlibs/fabulous/arith_map.v share/fabulous/arith_map.v 209s mkdir -p share/gatemate 209s cp "./"/techlibs/gatemate/reg_map.v share/gatemate/reg_map.v 209s mkdir -p share/gatemate 209s cp "./"/techlibs/gatemate/mux_map.v share/gatemate/mux_map.v 209s mkdir -p share/gatemate 209s cp "./"/techlibs/gatemate/lut_map.v share/gatemate/lut_map.v 209s mkdir -p share/gatemate 209s cp "./"/techlibs/gatemate/mul_map.v share/gatemate/mul_map.v 209s mkdir -p share/gatemate 209s cp "./"/techlibs/gatemate/arith_map.v share/gatemate/arith_map.v 209s mkdir -p share/gatemate 209s cp "./"/techlibs/gatemate/cells_sim.v share/gatemate/cells_sim.v 209s mkdir -p share/gatemate 209s cp "./"/techlibs/gatemate/cells_bb.v share/gatemate/cells_bb.v 209s mkdir -p share/gatemate 209s cp "./"/techlibs/gatemate/brams_map.v share/gatemate/brams_map.v 209s mkdir -p share/gatemate 209s cp "./"/techlibs/gatemate/brams.txt share/gatemate/brams.txt 209s mkdir -p share/gatemate 209s cp "./"/techlibs/gatemate/brams_init_20.vh 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"./"/techlibs/gowin/brams_map.v share/gowin/brams_map.v 209s mkdir -p share/gowin 209s cp "./"/techlibs/gowin/brams.txt share/gowin/brams.txt 209s mkdir -p share/gowin 209s cp "./"/techlibs/gowin/lutrams_map.v share/gowin/lutrams_map.v 209s mkdir -p share/gowin 209s cp "./"/techlibs/gowin/lutrams.txt share/gowin/lutrams.txt 209s mkdir -p share/greenpak4 209s cp "./"/techlibs/greenpak4/cells_blackbox.v share/greenpak4/cells_blackbox.v 209s mkdir -p share/greenpak4 209s cp "./"/techlibs/greenpak4/cells_latch.v share/greenpak4/cells_latch.v 209s mkdir -p share/greenpak4 209s cp "./"/techlibs/greenpak4/cells_map.v share/greenpak4/cells_map.v 209s mkdir -p share/greenpak4 209s cp "./"/techlibs/greenpak4/cells_sim.v share/greenpak4/cells_sim.v 209s mkdir -p share/greenpak4 209s cp "./"/techlibs/greenpak4/cells_sim_ams.v share/greenpak4/cells_sim_ams.v 209s mkdir -p share/greenpak4 209s cp "./"/techlibs/greenpak4/cells_sim_digital.v share/greenpak4/cells_sim_digital.v 209s mkdir -p share/greenpak4 209s cp "./"/techlibs/greenpak4/cells_sim_wip.v share/greenpak4/cells_sim_wip.v 209s mkdir -p share/greenpak4 209s cp "./"/techlibs/greenpak4/gp_dff.lib share/greenpak4/gp_dff.lib 209s mkdir -p share/ice40 209s cp "./"/techlibs/ice40/arith_map.v share/ice40/arith_map.v 209s mkdir -p share/ice40 209s cp "./"/techlibs/ice40/cells_map.v share/ice40/cells_map.v 209s mkdir -p share/ice40 209s cp "./"/techlibs/ice40/ff_map.v share/ice40/ff_map.v 209s mkdir -p share/ice40 209s cp "./"/techlibs/ice40/cells_sim.v share/ice40/cells_sim.v 209s mkdir -p share/ice40 209s cp "./"/techlibs/ice40/latches_map.v share/ice40/latches_map.v 209s mkdir -p share/ice40 209s cp "./"/techlibs/ice40/brams.txt share/ice40/brams.txt 209s mkdir -p share/ice40 209s cp "./"/techlibs/ice40/brams_map.v share/ice40/brams_map.v 209s mkdir -p share/ice40 209s cp "./"/techlibs/ice40/spram.txt share/ice40/spram.txt 209s mkdir -p share/ice40 209s cp "./"/techlibs/ice40/spram_map.v share/ice40/spram_map.v 209s mkdir -p share/ice40 209s cp "./"/techlibs/ice40/dsp_map.v share/ice40/dsp_map.v 209s mkdir -p share/ice40 209s cp "./"/techlibs/ice40/abc9_model.v share/ice40/abc9_model.v 209s mkdir -p share/intel/common 209s cp "./"/techlibs/intel/common/m9k_bb.v share/intel/common/m9k_bb.v 209s mkdir -p share/intel/common 209s cp "./"/techlibs/intel/common/altpll_bb.v share/intel/common/altpll_bb.v 209s mkdir -p share/intel/common 209s cp "./"/techlibs/intel/common/brams_m9k.txt share/intel/common/brams_m9k.txt 209s mkdir -p share/intel/common 209s cp "./"/techlibs/intel/common/brams_map_m9k.v share/intel/common/brams_map_m9k.v 209s mkdir -p share/intel/common 209s cp "./"/techlibs/intel/common/ff_map.v share/intel/common/ff_map.v 209s mkdir -p share/intel/max10 209s cp "./"/techlibs/intel/max10/cells_sim.v share/intel/max10/cells_sim.v 209s mkdir -p share/intel/cyclone10lp 209s cp "./"/techlibs/intel/cyclone10lp/cells_sim.v share/intel/cyclone10lp/cells_sim.v 209s mkdir -p share/intel/cycloneiv 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share/intel_alm/common 210s cp "./"/techlibs/intel_alm/common/megafunction_bb.v share/intel_alm/common/megafunction_bb.v 210s mkdir -p share/intel_alm/common 210s cp "./"/techlibs/intel_alm/common/quartus_rename.v share/intel_alm/common/quartus_rename.v 210s mkdir -p share/lattice 210s cp "./"/techlibs/lattice/cells_ff.vh share/lattice/cells_ff.vh 210s mkdir -p share/lattice 210s cp "./"/techlibs/lattice/cells_io.vh share/lattice/cells_io.vh 210s mkdir -p share/lattice 210s cp "./"/techlibs/lattice/cells_map.v share/lattice/cells_map.v 210s mkdir -p share/lattice 210s cp "./"/techlibs/lattice/common_sim.vh share/lattice/common_sim.vh 210s mkdir -p share/lattice 210s cp "./"/techlibs/lattice/ccu2d_sim.vh share/lattice/ccu2d_sim.vh 210s mkdir -p share/lattice 210s cp "./"/techlibs/lattice/ccu2c_sim.vh share/lattice/ccu2c_sim.vh 210s mkdir -p share/lattice 210s cp "./"/techlibs/lattice/cells_sim_ecp5.v share/lattice/cells_sim_ecp5.v 210s mkdir -p share/lattice 210s cp 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mkdir -p share/lattice 210s cp "./"/techlibs/lattice/brams_16kd.txt share/lattice/brams_16kd.txt 210s mkdir -p share/lattice 210s cp "./"/techlibs/lattice/brams_map_8kc.v share/lattice/brams_map_8kc.v 210s mkdir -p share/lattice 210s cp "./"/techlibs/lattice/brams_8kc.txt share/lattice/brams_8kc.txt 210s mkdir -p share/lattice 210s cp "./"/techlibs/lattice/arith_map_ccu2c.v share/lattice/arith_map_ccu2c.v 210s mkdir -p share/lattice 210s cp "./"/techlibs/lattice/arith_map_ccu2d.v share/lattice/arith_map_ccu2d.v 210s mkdir -p share/lattice 210s cp "./"/techlibs/lattice/latches_map.v share/lattice/latches_map.v 210s mkdir -p share/lattice 210s cp "./"/techlibs/lattice/dsp_map_18x18.v share/lattice/dsp_map_18x18.v 210s mkdir -p share/nexus 210s cp "./"/techlibs/nexus/cells_map.v share/nexus/cells_map.v 210s mkdir -p share/nexus 210s cp "./"/techlibs/nexus/cells_sim.v share/nexus/cells_sim.v 210s mkdir -p share/nexus 210s cp "./"/techlibs/nexus/parse_init.vh share/nexus/parse_init.vh 210s mkdir -p share/nexus 210s cp "./"/techlibs/nexus/cells_xtra.v share/nexus/cells_xtra.v 210s mkdir -p share/nexus 210s cp "./"/techlibs/nexus/lutrams_map.v share/nexus/lutrams_map.v 210s mkdir -p share/nexus 210s cp "./"/techlibs/nexus/lutrams.txt share/nexus/lutrams.txt 210s mkdir -p share/nexus 210s cp "./"/techlibs/nexus/brams_map.v share/nexus/brams_map.v 210s mkdir -p share/nexus 210s cp "./"/techlibs/nexus/brams.txt share/nexus/brams.txt 210s mkdir -p share/nexus 210s cp "./"/techlibs/nexus/lrams_map.v share/nexus/lrams_map.v 210s mkdir -p share/nexus 210s cp "./"/techlibs/nexus/lrams.txt share/nexus/lrams.txt 210s mkdir -p share/nexus 210s cp "./"/techlibs/nexus/arith_map.v share/nexus/arith_map.v 210s mkdir -p share/nexus 210s cp "./"/techlibs/nexus/latches_map.v share/nexus/latches_map.v 210s mkdir -p share/nexus 210s cp "./"/techlibs/nexus/dsp_map.v share/nexus/dsp_map.v 210s mkdir -p share/quicklogic 210s cp "./"/techlibs/quicklogic/pp3_ffs_map.v share/quicklogic/pp3_ffs_map.v 210s mkdir -p share/quicklogic 210s cp "./"/techlibs/quicklogic/pp3_lut_map.v share/quicklogic/pp3_lut_map.v 210s mkdir -p share/quicklogic 210s cp "./"/techlibs/quicklogic/pp3_latches_map.v share/quicklogic/pp3_latches_map.v 210s mkdir -p share/quicklogic 210s cp "./"/techlibs/quicklogic/pp3_cells_map.v share/quicklogic/pp3_cells_map.v 210s mkdir -p share/quicklogic 210s cp "./"/techlibs/quicklogic/cells_sim.v share/quicklogic/cells_sim.v 210s mkdir -p share/quicklogic 210s cp "./"/techlibs/quicklogic/lut_sim.v share/quicklogic/lut_sim.v 210s mkdir -p share/quicklogic 210s cp "./"/techlibs/quicklogic/pp3_cells_sim.v share/quicklogic/pp3_cells_sim.v 210s mkdir -p share/quicklogic 210s cp "./"/techlibs/quicklogic/abc9_model.v share/quicklogic/abc9_model.v 210s mkdir -p share/quicklogic 210s cp "./"/techlibs/quicklogic/abc9_map.v share/quicklogic/abc9_map.v 210s mkdir -p share/quicklogic 210s cp "./"/techlibs/quicklogic/abc9_unmap.v share/quicklogic/abc9_unmap.v 210s mkdir -p share/sf2 210s cp "./"/techlibs/sf2/arith_map.v share/sf2/arith_map.v 210s mkdir -p share/sf2 210s cp "./"/techlibs/sf2/cells_map.v share/sf2/cells_map.v 210s mkdir -p share/sf2 210s cp "./"/techlibs/sf2/cells_sim.v share/sf2/cells_sim.v 210s mkdir -p share/xilinx 210s cp "./"/techlibs/xilinx/cells_map.v share/xilinx/cells_map.v 210s mkdir -p share/xilinx 210s cp "./"/techlibs/xilinx/cells_sim.v share/xilinx/cells_sim.v 210s mkdir -p share/xilinx 210s cp "./"/techlibs/xilinx/cells_xtra.v share/xilinx/cells_xtra.v 210s mkdir -p share/xilinx 210s cp "./"/techlibs/xilinx/lutrams_xcv.txt share/xilinx/lutrams_xcv.txt 210s mkdir -p share/xilinx 210s cp "./"/techlibs/xilinx/lutrams_xcv_map.v share/xilinx/lutrams_xcv_map.v 210s mkdir -p share/xilinx 210s cp "./"/techlibs/xilinx/lutrams_xc5v.txt share/xilinx/lutrams_xc5v.txt 210s mkdir -p share/xilinx 210s cp "./"/techlibs/xilinx/lutrams_xcu.txt share/xilinx/lutrams_xcu.txt 210s mkdir -p share/xilinx 210s cp "./"/techlibs/xilinx/lutrams_xc5v_map.v share/xilinx/lutrams_xc5v_map.v 210s mkdir -p share/xilinx 210s cp "./"/techlibs/xilinx/brams_xcv.txt share/xilinx/brams_xcv.txt 210s mkdir -p share/xilinx 210s cp "./"/techlibs/xilinx/brams_xcv_map.v share/xilinx/brams_xcv_map.v 210s mkdir -p share/xilinx 210s cp "./"/techlibs/xilinx/brams_defs.vh share/xilinx/brams_defs.vh 210s mkdir -p share/xilinx 210s cp "./"/techlibs/xilinx/brams_xc2v.txt share/xilinx/brams_xc2v.txt 210s mkdir -p share/xilinx 210s cp "./"/techlibs/xilinx/brams_xc2v_map.v share/xilinx/brams_xc2v_map.v 210s mkdir -p share/xilinx 210s cp "./"/techlibs/xilinx/brams_xc3sda.txt share/xilinx/brams_xc3sda.txt 210s mkdir -p share/xilinx 210s cp "./"/techlibs/xilinx/brams_xc3sda_map.v share/xilinx/brams_xc3sda_map.v 210s mkdir -p share/xilinx 210s cp "./"/techlibs/xilinx/brams_xc4v.txt share/xilinx/brams_xc4v.txt 210s mkdir -p share/xilinx 210s cp "./"/techlibs/xilinx/brams_xc4v_map.v share/xilinx/brams_xc4v_map.v 210s mkdir -p share/xilinx 210s cp "./"/techlibs/xilinx/brams_xc5v_map.v share/xilinx/brams_xc5v_map.v 210s mkdir -p share/xilinx 210s cp "./"/techlibs/xilinx/brams_xc6v_map.v share/xilinx/brams_xc6v_map.v 210s mkdir -p share/xilinx 210s cp "./"/techlibs/xilinx/brams_xcu_map.v share/xilinx/brams_xcu_map.v 210s mkdir -p share/xilinx 210s cp "./"/techlibs/xilinx/urams.txt share/xilinx/urams.txt 210s mkdir -p share/xilinx 210s cp "./"/techlibs/xilinx/urams_map.v share/xilinx/urams_map.v 210s mkdir -p share/xilinx 210s cp "./"/techlibs/xilinx/arith_map.v share/xilinx/arith_map.v 210s mkdir -p share/xilinx 210s cp "./"/techlibs/xilinx/ff_map.v share/xilinx/ff_map.v 210s mkdir -p share/xilinx 210s cp "./"/techlibs/xilinx/lut_map.v share/xilinx/lut_map.v 210s mkdir -p share/xilinx 210s cp "./"/techlibs/xilinx/mux_map.v share/xilinx/mux_map.v 210s mkdir -p share/xilinx 210s cp "./"/techlibs/xilinx/xc3s_mult_map.v share/xilinx/xc3s_mult_map.v 210s mkdir -p share/xilinx 210s cp "./"/techlibs/xilinx/xc3sda_dsp_map.v share/xilinx/xc3sda_dsp_map.v 210s mkdir -p share/xilinx 210s cp "./"/techlibs/xilinx/xc6s_dsp_map.v share/xilinx/xc6s_dsp_map.v 210s mkdir -p share/xilinx 210s cp "./"/techlibs/xilinx/xc4v_dsp_map.v share/xilinx/xc4v_dsp_map.v 210s mkdir -p share/xilinx 210s cp "./"/techlibs/xilinx/xc5v_dsp_map.v share/xilinx/xc5v_dsp_map.v 210s mkdir -p share/xilinx 210s cp "./"/techlibs/xilinx/xc7_dsp_map.v share/xilinx/xc7_dsp_map.v 210s mkdir -p share/xilinx 210s cp "./"/techlibs/xilinx/xcu_dsp_map.v share/xilinx/xcu_dsp_map.v 210s mkdir -p share/xilinx 210s cp "./"/techlibs/xilinx/abc9_model.v share/xilinx/abc9_model.v 210s cd tests/simple && bash run-test.sh "" 210s make[1]: Entering directory '/tmp/autopkgtest.dZoNHp/build.YkG/src/tests/simple' 210s + gcc -Wall -o /tmp/autopkgtest.dZoNHp/build.YkG/src/tests/tools/cmp_tbdata /tmp/autopkgtest.dZoNHp/build.YkG/src/tests/tools/cmp_tbdata.c 210s Test: arrays02 -> ok 212s Test: asgn_binop -> ok 212s Test: case_expr_extend -> ok 213s Test: case_expr_query -> ok 213s Test: defvalue -> ok 213s Test: implicit_ports -> ok 214s Test: lesser_size_cast -> ok 214s Test: local_loop_var -> ok 214s Test: macro_arg_spaces -> ok 215s Test: matching_end_labels -> ok 215s Test: memwr_port_connection -> ok 215s Test: unnamed_block_decl -> ok 215s Test: aes_kexp128 -> ok 216s Test: always01 -> ok 216s Test: always02 -> ok 216s Test: always03 -> ok 217s Test: arraycells -> ok 217s Test: arrays01 -> ok 217s Test: attrib01_module -> ok 217s Test: attrib02_port_decl -> ok 218s Test: attrib03_parameter -> ok 218s Test: attrib04_net_var -> ok 219s Test: attrib06_operator_suffix -> ok 219s Test: attrib08_mod_inst -> ok 219s Test: attrib09_case -> ok 220s Test: carryadd -> ok 220s Test: case_expr_const -> ok 220s Test: case_expr_non_const -> ok 228s Test: case_large -> ok 228s Test: const_branch_finish -> ok 228s Test: const_fold_func -> ok 229s Test: const_func_shadow -> ok 231s Test: constmuldivmod -> ok 231s Test: constpower -> ok 232s Test: dff_different_styles -> ok 232s Test: dff_init -> ok 235s Test: dynslice -> ok 235s Test: fiedler-cooley -> ok 235s Test: forgen01 -> ok 236s Test: forgen02 -> ok 236s Test: forloops -> ok 237s Test: fsm -> ok 237s Test: func_block -> ok 237s Test: func_recurse -> ok 238s Test: func_width_scope -> ok 238s Test: genblk_collide -> ok 238s Test: genblk_dive -> ok 239s Test: genblk_order -> ok 239s Test: genblk_port_shadow -> ok 241s Test: generate -> ok 241s Test: graphtest -> ok 242s Test: hierarchy -> ok 242s Test: hierdefparam -> ok 243s Test: i2c_master_tests -> ok 243s Test: ifdef_1 -> ok 243s Test: ifdef_2 -> ok 243s Test: localparam_attr -> ok 243s Test: loop_prefix_case -> ok 244s Test: loop_var_shadow -> ok 244s Test: loops -> ok 244s Test: macro_arg_surrounding_spaces -> ok 245s Test: macros -> ok 246s Test: mem2reg -> ok 246s Test: mem2reg_bounds_tern -> ok 247s Test: mem_arst -> ok 254s Test: memory -> ok 254s Test: module_scope -> ok 254s Test: module_scope_case -> ok 255s Test: module_scope_func -> ok 256s Test: multiplier -> ok 256s Test: muxtree -> ok 256s Test: named_genblk -> ok 256s Test: nested_genblk_resolve -> ok 257s Test: omsp_dbg_uart -> ok 261s Test: operators -> ok 261s Test: param_attr -> ok 262s Test: paramods -> ok 266s Test: partsel -> ok 267s Test: process -> ok 267s Test: realexpr -> ok 268s Test: repwhile -> ok 268s Test: retime -> ok 272s Test: rotate -> ok 273s Test: scopes -> ok 273s Test: signed_full_slice -> ok 273s Test: signedexpr -> ok 275s Test: sincos -> ok 275s Test: specify -> ok 275s Test: string_format -> ok 276s Test: subbytes -> ok 277s Test: task_func -> ok 277s Test: undef_eqx_nex -> ok 277s Test: usb_phy_tests -> ok 278s Test: values -> ok 278s Test: verilog_primitives -> ok 279s Test: vloghammer -> ok 280s Test: wandwor -> ok 281s Test: wreduce -> ok 281s make[1]: Leaving directory '/tmp/autopkgtest.dZoNHp/build.YkG/src/tests/simple' 281s cd tests/simple_abc9 && bash run-test.sh "" 281s make[1]: Entering directory '/tmp/autopkgtest.dZoNHp/build.YkG/src/tests/simple_abc9' 281s ls: cannot access '*.sv': No such file or directory 283s Test: abc9 -> ok 283s Test: aes_kexp128 -> ok 284s Test: always01 -> ok 284s Test: always02 -> ok 284s Test: always03 -> ok 284s Test: arraycells -> ok 284s Test: arrays01 -> ok 285s Test: attrib01_module -> ok 285s Test: attrib02_port_decl -> ok 285s Test: attrib03_parameter -> ok 285s Test: attrib04_net_var -> ok 286s Test: attrib06_operator_suffix -> ok 286s Test: attrib08_mod_inst -> ok 286s Test: attrib09_case -> ok 286s Test: carryadd -> ok 287s Test: case_expr_const -> ok 287s Test: case_expr_non_const -> ok 300s Test: case_large -> ok 301s Test: const_branch_finish -> ok 301s Test: const_fold_func -> ok 301s Test: const_func_shadow -> ok 304s Test: constmuldivmod -> ok 304s Test: constpower -> ok 304s Test: dff_different_styles -> ok 305s Test: dff_init -> ok 312s Test: dynslice -> ok 313s Test: fiedler-cooley -> ok 313s Test: forgen01 -> ok 313s Test: forgen02 -> ok 313s Test: forloops -> ok 314s Test: fsm -> ok 314s Test: func_block -> ok 314s Test: func_recurse -> ok 314s Test: func_width_scope -> ok 315s Test: genblk_collide -> ok 315s Test: genblk_dive -> ok 315s Test: genblk_order -> ok 315s Test: genblk_port_shadow -> ok 317s Test: generate -> ok 317s Test: graphtest -> ok 317s Test: hierarchy -> ok 318s Test: hierdefparam -> ok 318s Test: i2c_master_tests -> ok 318s Test: ifdef_1 -> ok 319s Test: ifdef_2 -> ok 319s Test: localparam_attr -> ok 319s Test: loop_prefix_case -> ok 319s Test: loop_var_shadow -> ok 320s Test: loops -> ok 320s Test: macro_arg_surrounding_spaces -> ok 320s Test: macros -> ok 321s Test: mem2reg -> ok 322s Test: mem2reg_bounds_tern -> ok 322s Test: mem_arst -> ok 325s Test: memory -> ok 326s Test: module_scope -> ok 326s Test: module_scope_case -> ok 326s Test: module_scope_func -> ok 327s Test: multiplier -> ok 327s Test: muxtree -> ok 327s Test: named_genblk -> ok 327s Test: nested_genblk_resolve -> ok 328s Test: omsp_dbg_uart -> ok 333s Test: operators -> ok 333s Test: param_attr -> ok 334s Test: paramods -> ok 339s Test: partsel -> ok 339s Test: process -> ok 340s Test: realexpr -> ok 340s Test: repwhile -> ok 341s Test: retime -> ok 342s Test: rotate -> ok 343s Test: scopes -> ok 343s Test: signed_full_slice -> ok 343s Test: signedexpr -> ok 345s Test: sincos -> ok 346s Test: string_format -> ok 346s Test: subbytes -> ok 347s Test: task_func -> ok 347s Test: undef_eqx_nex -> ok 347s Test: usb_phy_tests -> ok 348s Test: values -> ok 348s Test: verilog_primitives -> ok 348s Test: vloghammer -> ok 349s Test: wandwor -> ok 350s Test: wreduce -> ok 350s Test: arrays02 -> ok 352s Test: asgn_binop -> ok 352s Test: case_expr_extend -> ok 352s Test: case_expr_query -> ok 352s Test: defvalue -> ok 353s Test: implicit_ports -> ok 353s Test: lesser_size_cast -> ok 353s Test: local_loop_var -> ok 354s Test: macro_arg_spaces -> ok 354s Test: matching_end_labels -> ok 355s Test: memwr_port_connection -> ok 355s Test: unnamed_block_decl -> ok 355s make[1]: Leaving directory '/tmp/autopkgtest.dZoNHp/build.YkG/src/tests/simple_abc9' 355s cd tests/hana && bash run-test.sh "" 355s make[1]: Entering directory '/tmp/autopkgtest.dZoNHp/build.YkG/src/tests/hana' 358s Test: test_intermout -> ok 358s Test: test_parse2synthtrans -> ok 359s Test: test_parser -> ok 360s Test: test_simulation_always -> ok 361s Test: test_simulation_and -> ok 361s Test: test_simulation_buffer -> ok 362s Test: test_simulation_decoder -> ok 362s Test: test_simulation_inc -> ok 364s Test: test_simulation_mux -> ok 364s Test: test_simulation_nand -> ok 365s Test: test_simulation_nor -> ok 365s Test: test_simulation_or -> ok 365s Test: test_simulation_seq -> ok 368s Test: test_simulation_shifter -> ok 368s Test: test_simulation_sop -> ok 369s Test: test_simulation_techmap -> ok 372s Test: test_simulation_techmap_tech -> ok 372s Test: test_simulation_vlib -> ok 372s Test: test_simulation_xnor -> ok 373s Test: test_simulation_xor -> ok 373s make[1]: Leaving directory '/tmp/autopkgtest.dZoNHp/build.YkG/src/tests/hana' 373s cd tests/asicworld && bash run-test.sh "" 373s make[1]: Entering directory '/tmp/autopkgtest.dZoNHp/build.YkG/src/tests/asicworld' 373s Test: code_hdl_models_GrayCounter -> ok 373s Test: code_hdl_models_arbiter -> ok 380s Test: code_hdl_models_cam -> ok 380s Test: code_hdl_models_clk_div -> ok 381s Test: code_hdl_models_clk_div_45 -> ok 381s Test: code_hdl_models_d_ff_gates -> ok 381s Test: code_hdl_models_d_latch_gates -> ok 381s Test: code_hdl_models_decoder_2to4_gates -> ok 382s Test: code_hdl_models_decoder_using_assign -> ok 382s Test: code_hdl_models_decoder_using_case -> ok 382s Test: code_hdl_models_dff_async_reset -> ok 383s Test: code_hdl_models_dff_sync_reset -> ok 383s Test: code_hdl_models_encoder_4to2_gates -> ok 383s Test: code_hdl_models_encoder_using_case -> ok 384s Test: code_hdl_models_encoder_using_if -> ok 384s Test: code_hdl_models_full_adder_gates -> ok 384s Test: code_hdl_models_full_subtracter_gates -> ok 384s Test: code_hdl_models_gray_counter -> ok 385s Test: code_hdl_models_half_adder_gates -> ok 385s Test: code_hdl_models_lfsr -> ok 385s Test: code_hdl_models_lfsr_updown -> ok 386s Test: code_hdl_models_mux_2to1_gates -> ok 386s Test: code_hdl_models_mux_using_assign -> ok 386s Test: code_hdl_models_mux_using_case -> ok 386s Test: code_hdl_models_mux_using_if -> ok 387s Test: code_hdl_models_one_hot_cnt -> ok 387s Test: code_hdl_models_parallel_crc -> ok 387s Test: code_hdl_models_parity_using_assign -> ok 387s Test: code_hdl_models_parity_using_bitwise -> ok 388s Test: code_hdl_models_parity_using_function -> ok 388s Test: code_hdl_models_pri_encoder_using_assign -> ok 388s Test: code_hdl_models_rom_using_case -> ok 389s Test: code_hdl_models_serial_crc -> ok 389s Test: code_hdl_models_tff_async_reset -> ok 389s Test: code_hdl_models_tff_sync_reset -> ok 390s Test: code_hdl_models_uart -> ok 391s Test: code_hdl_models_up_counter -> ok 391s Test: code_hdl_models_up_counter_load -> ok 391s Test: code_hdl_models_up_down_counter -> ok 392s Test: code_specman_switch_fabric -> ok 392s Test: code_tidbits_asyn_reset -> ok 392s Test: code_tidbits_blocking -> ok 393s Test: code_tidbits_fsm_using_always -> ok 393s Test: code_tidbits_fsm_using_function -> ok 394s Test: code_tidbits_fsm_using_single_always -> ok 394s Test: code_tidbits_nonblocking -> ok 394s Test: code_tidbits_reg_combo_example -> ok 394s Test: code_tidbits_reg_seq_example -> ok 395s Test: code_tidbits_syn_reset -> ok 395s Test: code_tidbits_wire_example -> ok 395s Test: code_verilog_tutorial_addbit -> ok 395s Test: code_verilog_tutorial_always_example -> ok 396s Test: code_verilog_tutorial_bus_con -> ok 396s Test: code_verilog_tutorial_comment -> ok 396s Test: code_verilog_tutorial_counter -> ok 396s Test: code_verilog_tutorial_d_ff -> ok 397s Test: code_verilog_tutorial_decoder -> ok 397s Test: code_verilog_tutorial_decoder_always -> ok 397s Test: code_verilog_tutorial_escape_id -> ok 397s Test: code_verilog_tutorial_explicit -> ok 398s Test: code_verilog_tutorial_first_counter -> ok 398s Test: code_verilog_tutorial_flip_flop -> ok 399s Test: code_verilog_tutorial_fsm_full -> ok 399s Test: code_verilog_tutorial_good_code -> ok 399s Test: code_verilog_tutorial_if_else -> ok 399s Test: code_verilog_tutorial_multiply -> ok 399s Test: code_verilog_tutorial_mux_21 -> ok 400s Test: code_verilog_tutorial_n_out_primitive -> ok 400s Test: code_verilog_tutorial_parallel_if -> ok 400s Test: code_verilog_tutorial_parity -> ok 400s Test: code_verilog_tutorial_simple_function -> ok 400s Test: code_verilog_tutorial_simple_if -> ok 401s Test: code_verilog_tutorial_task_global -> ok 401s Test: code_verilog_tutorial_tri_buf -> ok 401s Test: code_verilog_tutorial_v2k_reg -> ok 401s Test: code_verilog_tutorial_which_clock -> ok 401s make[1]: Leaving directory '/tmp/autopkgtest.dZoNHp/build.YkG/src/tests/asicworld' 401s # +cd tests/realmath && bash run-test.sh "" 401s cd tests/share && bash run-test.sh "" 401s generating tests.. 401s running tests.. 406s [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41][42][43][44][45][46][47][48][49][50][51][52][53][54][55][56][57][58][59][60][61][62][63][64][65][66][67][68][69][70][71][72][73][74][75][76][77][78][79][80][81][82][83][84][85][86][87][88][89][90][91][92][93][94][95][96][97][98][99] 406s cd tests/opt_share && bash run-test.sh "" 406s generating tests.. 406s running tests.. 406s make[1]: Entering directory '/tmp/autopkgtest.dZoNHp/build.YkG/src/tests/opt_share' 438s [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41][42][43][44][45][46][47][48][49][50][51][52][53][54][55][56][57][58][59][60][61][62][63][64][65][66][67][68][69][70][71][72][73][74][75][76][77][78][79][80][81][82][83][84][85][86][87][88][89][90][91][92][93][94][95][96][97][98][99]make[1]: Leaving directory '/tmp/autopkgtest.dZoNHp/build.YkG/src/tests/opt_share' 438s 438s cd tests/fsm && bash run-test.sh "" 438s generating tests.. 438s PRNG seed: 357963077390799581 438s running tests.. 438s make[1]: Entering directory '/tmp/autopkgtest.dZoNHp/build.YkG/src/tests/fsm' 439s [0]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 439s Users of state reg look like FSM recoding might result in larger circuit. 439s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 442s K[1]K[2]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 442s Users of state reg look like FSM recoding might result in larger circuit. 442s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 443s K[3]K[4]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 443s Users of state reg look like FSM recoding might result in larger circuit. 443s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 446s K[5]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 446s Users of state reg look like FSM recoding might result in larger circuit. 446s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 448s K[6]K[7]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 448s Users of state reg look like FSM recoding might result in larger circuit. 448s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 453s K[8]K[9]K[10]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 453s Users of state reg look like FSM recoding might result in larger circuit. 453s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 453s K[11]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 453s Users of state reg look like FSM recoding might result in larger circuit. 453s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 455s K[12]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 455s Users of state reg look like FSM recoding might result in larger circuit. 455s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 456s K[13]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 456s Users of state reg look like FSM recoding might result in larger circuit. 456s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 458s K[14]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 458s Users of state reg look like FSM recoding might result in larger circuit. 458s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 461s K[15]K[16]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 461s Users of state reg look like FSM recoding might result in larger circuit. 461s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 470s K[17]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 470s Users of state reg look like FSM recoding might result in larger circuit. 470s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 474s K[18]K[19]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 474s Users of state reg look like FSM recoding might result in larger circuit. 474s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 476s K[20]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 476s Users of state reg look like FSM recoding might result in larger circuit. 476s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 478s K[21]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 478s Users of state reg look like FSM recoding might result in larger circuit. 478s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 481s K[22]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 481s Users of state reg look like FSM recoding might result in larger circuit. 481s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 481s K[23]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 481s Users of state reg look like FSM recoding might result in larger circuit. 481s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 483s K[24]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 483s Users of state reg look like FSM recoding might result in larger circuit. 483s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 486s K[25]K[26]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 486s Users of state reg look like FSM recoding might result in larger circuit. 486s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 489s K[27]K[28]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 489s Users of state reg look like FSM recoding might result in larger circuit. 489s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 492s K[29]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 492s Users of state reg look like FSM recoding might result in larger circuit. 492s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 492s K[30]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 492s Users of state reg look like FSM recoding might result in larger circuit. 492s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 492s K[31]K[32]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 492s Users of state reg look like FSM recoding might result in larger circuit. 492s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 493s K[33]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 493s Users of state reg look like FSM recoding might result in larger circuit. 493s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 494s K[34]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 494s Users of state reg look like FSM recoding might result in larger circuit. 494s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 496s K[35]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 496s Users of state reg look like FSM recoding might result in larger circuit. 496s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 499s K[36]K[37]K[38]K[39]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 499s Users of state reg look like FSM recoding might result in larger circuit. 499s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 501s K[40]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 501s Users of state reg look like FSM recoding might result in larger circuit. 501s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 502s K[41]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 502s Users of state reg look like FSM recoding might result in larger circuit. 502s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 504s K[42]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 504s Users of state reg look like FSM recoding might result in larger circuit. 504s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 505s K[43]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 505s Users of state reg look like FSM recoding might result in larger circuit. 505s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 507s K[44]K[45]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 507s Users of state reg look like FSM recoding might result in larger circuit. 507s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 513s K[46]K[47]K[48]K[49]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 513s Users of state reg look like FSM recoding might result in larger circuit. 513s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 521s K 521s make[1]: Leaving directory '/tmp/autopkgtest.dZoNHp/build.YkG/src/tests/fsm' 521s cd tests/techmap && bash run-test.sh 521s make[1]: Entering directory '/tmp/autopkgtest.dZoNHp/build.YkG/src/tests/techmap' 522s Passed abc9.ys 522s Warning: wire '\Q' is assigned in a block at < ok 532s Test: firrtl_938 -> ok 533s Test: implicit_en -> ok 535s Test: issue00335 -> ok 536s Test: issue00710 -> ok 536s Test: no_implicit_en -> ok 537s Test: read_arst -> ok 538s Test: read_two_mux -> ok 539s Test: shared_ports -> ok 539s Test: simple_sram_byte_en -> ok 540s Test: trans_addr_enable -> ok 541s Test: trans_sdp -> ok 542s Test: trans_sp -> ok 543s Test: wide_all -> ok 543s Test: wide_read_async -> ok 544s Test: wide_read_mixed -> ok 545s Test: wide_read_sync -> ok 546s Test: wide_read_trans -> ok 547s Test: wide_thru_priority -> ok 548s Test: wide_write -> ok 548s make[1]: Leaving directory '/tmp/autopkgtest.dZoNHp/build.YkG/src/tests/memories' 548s Testing expectations for amber23_sram_byte_en.v .. ok. 548s Testing expectations for implicit_en.v .. ok. 548s Testing expectations for issue00335.v .. ok. 548s Testing expectations for issue00710.v .. ok. 548s Testing expectations for no_implicit_en.v .. ok. 548s Testing expectations for read_arst.v .. ok. 548s Testing expectations for read_two_mux.v .. ok. 549s Testing expectations for shared_ports.v .. ok. 549s Testing expectations for simple_sram_byte_en.v .. ok. 549s Testing expectations for trans_addr_enable.v .. ok. 549s Testing expectations for trans_sdp.v .. ok. 549s Testing expectations for trans_sp.v .. ok. 549s Testing expectations for wide_all.v .. ok. 549s Testing expectations for wide_read_async.v .. ok. 549s Testing expectations for wide_read_mixed.v .. ok. 549s Testing expectations for wide_read_sync.v .. ok. 549s Testing expectations for wide_read_trans.v .. ok. 549s Testing expectations for wide_thru_priority.v .. ok. 549s Testing expectations for wide_write.v .. ok. 549s cd tests/memlib && bash run-test.sh "" 549s make[1]: Entering directory '/tmp/autopkgtest.dZoNHp/build.YkG/src/tests/memlib' 551s Test: t_async_big -> ok 553s Test: t_async_big_block -> ok 554s Test: t_async_small -> ok 554s Test: t_async_small_block -> ok 554s Test: t_sync_big -> ok 554s Test: t_sync_big_sdp -> ok 556s Test: t_sync_big_lut -> ok 556s Test: t_sync_small -> ok 556s Test: t_sync_small_block -> ok 556s Test: t_sync_small_block_attr -> ok 556s Test: t_init_lut_zeros_zero -> ok 557s Test: t_init_lut_zeros_any -> ok 557s Test: t_init_lut_val_zero -> ok 557s Test: t_init_lut_val_any -> ok 557s Test: t_init_lut_val_no_undef -> ok 557s Test: t_init_lut_val2_any -> ok 558s Test: t_init_lut_val2_no_undef -> ok 558s Test: t_init_lut_x_none -> ok 558s Test: t_init_lut_x_zero -> ok 558s Test: t_init_lut_x_any -> ok 558s Test: t_init_lut_x_no_undef -> ok 558s Test: t_ram_18b2B -> ok 559s Test: t_ram_9b1B -> ok 559s Test: t_ram_4b1B -> ok 559s Test: t_ram_2b1B -> ok 559s Test: t_ram_1b1B -> ok 559s Test: t_init_9b1B_zeros_zero -> ok 559s Test: t_init_9b1B_zeros_any -> ok 560s Test: t_init_9b1B_val_zero -> ok 560s Test: t_init_9b1B_val_any -> ok 560s Test: t_init_9b1B_val_no_undef -> ok 560s Test: t_init_13b2B_val_any -> ok 560s Test: t_init_18b2B_val_any -> ok 561s Test: t_init_18b2B_val_no_undef -> ok 561s Test: t_init_4b1B_x_none -> ok 561s Test: t_init_4b1B_x_zero -> ok 561s Test: t_init_4b1B_x_any -> ok 561s Test: t_init_4b1B_x_no_undef -> ok 561s Test: t_clock_a4_wANYrANYsFalse -> ok 562s Test: t_clock_a4_wANYrNEGsFalse -> ok 562s Test: t_clock_a4_wANYrPOSsFalse -> ok 562s Test: t_clock_a4_wNEGrANYsFalse -> ok 562s Test: t_clock_a4_wNEGrPOSsFalse -> ok 562s Test: t_clock_a4_wNEGrNEGsFalse -> ok 563s Test: t_clock_a4_wPOSrANYsFalse -> ok 563s Test: t_clock_a4_wPOSrNEGsFalse -> ok 563s Test: t_clock_a4_wPOSrPOSsFalse -> ok 563s Test: t_clock_a4_wANYrANYsTrue -> ok 563s Test: t_clock_a4_wNEGrPOSsTrue -> ok 563s Test: t_clock_a4_wNEGrNEGsTrue -> ok 564s Test: t_clock_a4_wPOSrNEGsTrue -> ok 564s Test: t_clock_a4_wPOSrPOSsTrue -> ok 564s Test: t_unmixed -> ok 564s Test: t_mixed_9_18 -> ok 564s Test: t_mixed_18_9 -> ok 565s Test: t_mixed_36_9 -> ok 565s Test: t_mixed_4_2 -> ok 565s Test: t_tdp -> ok 565s Test: t_sync_2clk -> ok 565s Test: t_sync_shared -> ok 566s Test: t_sync_2clk_shared -> ok 566s Test: t_sync_trans_old_old -> ok 566s Test: t_sync_trans_old_new -> ok 566s Test: t_sync_trans_old_none -> ok 567s Test: t_sync_trans_new_old -> ok 567s Test: t_sync_trans_new_new -> ok 567s Test: t_sync_trans_new_none -> ok 567s Test: t_sp_nc_none -> ok 567s Test: t_sp_new_none -> ok 568s Test: t_sp_old_none -> ok 568s Test: t_sp_nc_nc -> ok 568s Test: t_sp_new_nc -> ok 568s Test: t_sp_old_nc -> ok 568s Test: t_sp_nc_new -> ok 568s Test: t_sp_new_new -> ok 569s Test: t_sp_old_new -> ok 569s Test: t_sp_nc_old -> ok 569s Test: t_sp_new_old -> ok 569s Test: t_sp_old_old -> ok 569s Test: t_sp_nc_new_only -> ok 569s Test: t_sp_new_new_only -> ok 570s Test: t_sp_old_new_only -> ok 570s Test: t_sp_nc_new_only_be -> ok 570s Test: t_sp_new_new_only_be -> ok 570s Test: t_sp_old_new_only_be -> ok 570s Test: t_sp_nc_new_be -> ok 570s Test: t_sp_new_new_be -> ok 571s Test: t_sp_old_new_be -> ok 571s Test: t_sp_nc_old_be -> ok 571s Test: t_sp_new_old_be -> ok 571s Test: t_sp_old_old_be -> ok 571s Test: t_sp_nc_nc_be -> ok 572s Test: t_sp_new_nc_be -> ok 572s Test: t_sp_old_nc_be -> ok 572s Test: t_sp_nc_auto -> ok 572s Test: t_sp_new_auto -> ok 572s Test: t_sp_old_auto -> ok 572s Test: t_sp_nc_auto_be -> ok 573s Test: t_sp_new_auto_be -> ok 573s Test: t_sp_old_auto_be -> ok 573s Test: t_sp_init_x_x -> ok 573s Test: t_sp_init_x_x_re -> ok 573s Test: t_sp_init_x_x_ce -> ok 574s Test: t_sp_init_0_x -> ok 574s Test: t_sp_init_0_x_re -> ok 574s Test: t_sp_init_0_0 -> ok 574s Test: t_sp_init_0_0_re -> ok 574s Test: t_sp_init_0_any -> ok 574s Test: t_sp_init_0_any_re -> ok 575s Test: t_sp_init_v_x -> ok 575s Test: t_sp_init_v_x_re -> ok 575s Test: t_sp_init_v_0 -> ok 575s Test: t_sp_init_v_0_re -> ok 575s Test: t_sp_init_v_any -> ok 575s Test: t_sp_init_v_any_re -> ok 576s Test: t_sp_arst_x_x -> ok 576s Test: t_sp_arst_x_x_re -> ok 576s Test: t_sp_arst_0_x -> ok 576s Test: t_sp_arst_0_x_re -> ok 576s Test: t_sp_arst_0_0 -> ok 576s Test: t_sp_arst_0_0_re -> ok 576s Test: t_sp_arst_0_any -> ok 577s Test: t_sp_arst_0_any_re -> ok 577s Test: t_sp_arst_0_init -> ok 577s Test: t_sp_arst_0_init_re -> ok 577s Test: t_sp_arst_v_x -> ok 577s Test: t_sp_arst_v_x_re -> ok 577s Test: t_sp_arst_v_0 -> ok 578s Test: t_sp_arst_v_0_re -> ok 578s Test: t_sp_arst_v_any -> ok 578s Test: t_sp_arst_v_any_re -> ok 578s Test: t_sp_arst_v_init -> ok 578s Test: t_sp_arst_v_init_re -> ok 579s Test: t_sp_arst_e_x -> ok 579s Test: t_sp_arst_e_x_re -> ok 579s Test: t_sp_arst_e_0 -> ok 579s Test: t_sp_arst_e_0_re -> ok 579s Test: t_sp_arst_e_any -> ok 580s Test: t_sp_arst_e_any_re -> ok 580s Test: t_sp_arst_e_init -> ok 580s Test: t_sp_arst_e_init_re -> ok 580s Test: t_sp_arst_n_x -> ok 580s Test: t_sp_arst_n_x_re -> ok 581s Test: t_sp_arst_n_0 -> ok 581s Test: t_sp_arst_n_0_re -> ok 581s Test: t_sp_arst_n_any -> ok 581s Test: t_sp_arst_n_any_re -> ok 581s Test: t_sp_arst_n_init -> ok 581s Test: t_sp_arst_n_init_re -> ok 582s Test: t_sp_srst_x_x -> ok 582s Test: t_sp_srst_x_x_re -> ok 582s Test: t_sp_srst_0_x -> ok 582s Test: t_sp_srst_0_x_re -> ok 582s Test: t_sp_srst_0_0 -> ok 582s Test: t_sp_srst_0_0_re -> ok 583s Test: t_sp_srst_0_any -> ok 583s Test: t_sp_srst_0_any_re -> ok 583s Test: t_sp_srst_0_init -> ok 583s Test: t_sp_srst_0_init_re -> ok 583s Test: t_sp_srst_v_x -> ok 583s Test: t_sp_srst_v_x_re -> ok 584s Test: t_sp_srst_v_0 -> ok 584s Test: t_sp_srst_v_0_re -> ok 584s Test: t_sp_srst_v_any -> ok 584s Test: t_sp_srst_v_any_re -> ok 584s Test: t_sp_srst_v_any_re_gated -> ok 585s Test: t_sp_srst_v_any_ce -> ok 585s Test: t_sp_srst_v_any_ce_gated -> ok 585s Test: t_sp_srst_v_init -> ok 585s Test: t_sp_srst_v_init_re -> ok 585s Test: t_sp_srst_e_x -> ok 585s Test: t_sp_srst_e_x_re -> ok 586s Test: t_sp_srst_e_0 -> ok 586s Test: t_sp_srst_e_0_re -> ok 586s Test: t_sp_srst_e_any -> ok 586s Test: t_sp_srst_e_any_re -> ok 586s Test: t_sp_srst_e_init -> ok 587s Test: t_sp_srst_e_init_re -> ok 587s Test: t_sp_srst_n_x -> ok 587s Test: t_sp_srst_n_x_re -> ok 587s Test: t_sp_srst_n_0 -> ok 587s Test: t_sp_srst_n_0_re -> ok 587s Test: t_sp_srst_n_any -> ok 588s Test: t_sp_srst_n_any_re -> ok 588s Test: t_sp_srst_n_init -> ok 588s Test: t_sp_srst_n_init_re -> ok 588s Test: t_sp_srst_gv_x -> ok 588s Test: t_sp_srst_gv_x_re -> ok 589s Test: t_sp_srst_gv_0 -> ok 589s Test: t_sp_srst_gv_0_re -> ok 589s Test: t_sp_srst_gv_any -> ok 589s Test: t_sp_srst_gv_any_re -> ok 589s Test: t_sp_srst_gv_any_re_gated -> ok 589s Test: t_sp_srst_gv_any_ce -> ok 590s Test: t_sp_srst_gv_any_ce_gated -> ok 590s Test: t_sp_srst_gv_init -> ok 590s Test: t_sp_srst_gv_init_re -> ok 590s Test: t_wren_a4d4_NO_BYTE -> ok 590s Test: t_wren_a5d4_NO_BYTE -> ok 590s Test: t_wren_a6d4_NO_BYTE -> ok 591s Test: t_wren_a3d8_NO_BYTE -> ok 591s Test: t_wren_a4d8_NO_BYTE -> ok 591s Test: t_wren_a4d4_W4_B4 -> ok 591s Test: t_wren_a4d8_W4_B4_separate -> ok 591s Test: t_wren_a4d8_W8_B4 -> ok 591s Test: t_wren_a4d8_W8_B4_separate -> ok 592s Test: t_wren_a4d8_W8_B8 -> ok 592s Test: t_wren_a4d8_W8_B8_separate -> ok 592s Test: t_wren_a4d2w8_W16_B4 -> ok 592s Test: t_wren_a4d2w8_W16_B4_separate -> ok 592s Test: t_wren_a4d4w4_W16_B4 -> ok 593s Test: t_wren_a4d4w4_W16_B4_separate -> ok 593s Test: t_wren_a5d4w2_W16_B4 -> ok 593s Test: t_wren_a5d4w2_W16_B4_separate -> ok 593s Test: t_wren_a5d4w4_W16_B4 -> ok 593s Test: t_wren_a5d4w4_W16_B4_separate -> ok 593s Test: t_wren_a4d8w2_W16_B4 -> ok 594s Test: t_wren_a4d8w2_W16_B4_separate -> ok 594s Test: t_wren_a5d8w1_W16_B4 -> ok 594s Test: t_wren_a5d8w1_W16_B4_separate -> ok 594s Test: t_wren_a5d8w2_W16_B4 -> ok 594s Test: t_wren_a5d8w2_W16_B4_separate -> ok 594s Test: t_wren_a4d16w1_W16_B4 -> ok 595s Test: t_wren_a4d16w1_W16_B4_separate -> ok 595s Test: t_wren_a4d4w2_W8_B8 -> ok 595s Test: t_wren_a4d4w2_W8_B8_separate -> ok 595s Test: t_wren_a4d4w1_W8_B8 -> ok 595s Test: t_wren_a4d4w1_W8_B8_separate -> ok 595s Test: t_wren_a4d8w2_W8_B8 -> ok 596s Test: t_wren_a4d8w2_W8_B8_separate -> ok 596s Test: t_wren_a3d8w2_W8_B8 -> ok 596s Test: t_wren_a3d8w2_W8_B8_separate -> ok 596s Test: t_wren_a4d4w2_W8_B4 -> ok 596s Test: t_wren_a4d4w2_W8_B4_separate -> ok 596s Test: t_wren_a4d2w4_W8_B4 -> ok 597s Test: t_wren_a4d2w4_W8_B4_separate -> ok 597s Test: t_wren_a4d4w4_W8_B4 -> ok 597s Test: t_wren_a4d4w4_W8_B4_separate -> ok 597s Test: t_wren_a4d4w4_W4_B4 -> ok 597s Test: t_wren_a4d4w4_W4_B4_separate -> ok 598s Test: t_wren_a4d4w5_W4_B4 -> ok 598s Test: t_wren_a4d4w5_W4_B4_separate -> ok 598s Test: t_geom_a4d64_wren -> ok 598s Test: t_geom_a5d32_wren -> ok 598s Test: t_geom_a5d64_wren -> ok 598s Test: t_geom_a6d16_wren -> ok 599s Test: t_geom_a6d30_wren -> ok 599s Test: t_geom_a6d64_wren -> ok 599s Test: t_geom_a7d4_wren -> ok 599s Test: t_geom_a7d6_wren -> ok 599s Test: t_geom_a7d8_wren -> ok 599s Test: t_geom_a7d17_wren -> ok 600s Test: t_geom_a8d4_wren -> ok 600s Test: t_geom_a8d6_wren -> ok 600s Test: t_geom_a9d4_wren -> ok 600s Test: t_geom_a9d8_wren -> ok 600s Test: t_geom_a9d5_wren -> ok 601s Test: t_geom_a9d6_wren -> ok 601s Test: t_geom_a3d18_9b1B -> ok 601s Test: t_geom_a4d4_9b1B -> ok 601s Test: t_geom_a4d18_9b1B -> ok 601s Test: t_geom_a5d32_9b1B -> ok 601s Test: t_geom_a6d4_9b1B -> ok 602s Test: t_geom_a7d11_9b1B -> ok 602s Test: t_geom_a7d18_9b1B -> ok 602s Test: t_geom_a11d1_9b1B -> ok 602s Test: t_wide_sdp_a6r1w1b1x1 -> ok 602s Test: t_wide_sdp_a7r1w1b1x1 -> ok 603s Test: t_wide_sdp_a8r1w1b1x1 -> ok 603s Test: t_wide_sdp_a6r0w0b0x0 -> ok 603s Test: t_wide_sdp_a6r1w0b0x0 -> ok 603s Test: t_wide_sdp_a6r2w0b0x0 -> ok 603s Test: t_wide_sdp_a6r3w0b0x0 -> ok 604s Test: t_wide_sdp_a6r4w0b0x0 -> ok 604s Test: t_wide_sdp_a6r5w0b0x0 -> ok 604s Test: t_wide_sdp_a6r0w1b0x0 -> ok 604s Test: t_wide_sdp_a6r0w1b1x0 -> ok 604s Test: t_wide_sdp_a6r0w2b0x0 -> ok 605s Test: t_wide_sdp_a6r0w2b2x0 -> ok 605s Test: t_wide_sdp_a6r0w3b2x0 -> ok 605s Test: t_wide_sdp_a6r0w4b2x0 -> ok 605s Test: t_wide_sdp_a6r0w5b2x0 -> ok 606s Test: t_wide_sdp_a7r0w0b0x0 -> ok 606s Test: t_wide_sdp_a7r1w0b0x0 -> ok 606s Test: t_wide_sdp_a7r2w0b0x0 -> ok 606s Test: t_wide_sdp_a7r3w0b0x0 -> ok 606s Test: t_wide_sdp_a7r4w0b0x0 -> ok 607s Test: t_wide_sdp_a7r5w0b0x0 -> ok 607s Test: t_wide_sdp_a7r0w1b0x0 -> ok 607s Test: t_wide_sdp_a7r0w1b1x0 -> ok 607s Test: t_wide_sdp_a7r0w2b0x0 -> ok 608s Test: t_wide_sdp_a7r0w2b2x0 -> ok 608s Test: t_wide_sdp_a7r0w3b2x0 -> ok 608s Test: t_wide_sdp_a7r0w4b2x0 -> ok 608s Test: t_wide_sdp_a7r0w5b2x0 -> ok 608s Test: t_wide_sp_mix_a6r1w1b1 -> ok 609s Test: t_wide_sp_mix_a7r1w1b1 -> ok 609s Test: t_wide_sp_mix_a8r1w1b1 -> ok 609s Test: t_wide_sp_mix_a6r0w0b0 -> ok 609s Test: t_wide_sp_mix_a6r1w0b0 -> ok 609s Test: t_wide_sp_mix_a6r2w0b0 -> ok 610s Test: t_wide_sp_mix_a6r3w0b0 -> ok 610s Test: t_wide_sp_mix_a6r4w0b0 -> ok 610s Test: t_wide_sp_mix_a6r5w0b0 -> ok 610s Test: t_wide_sp_mix_a6r0w1b0 -> ok 610s Test: t_wide_sp_mix_a6r0w1b1 -> ok 611s Test: t_wide_sp_mix_a6r0w2b0 -> ok 611s Test: t_wide_sp_mix_a6r0w2b2 -> ok 611s Test: t_wide_sp_mix_a6r0w3b2 -> ok 611s Test: t_wide_sp_mix_a6r0w4b2 -> ok 612s Test: t_wide_sp_mix_a6r0w5b2 -> ok 612s Test: t_wide_sp_mix_a7r0w0b0 -> ok 612s Test: t_wide_sp_mix_a7r1w0b0 -> ok 612s Test: t_wide_sp_mix_a7r2w0b0 -> ok 612s Test: t_wide_sp_mix_a7r3w0b0 -> ok 613s Test: t_wide_sp_mix_a7r4w0b0 -> ok 613s Test: t_wide_sp_mix_a7r5w0b0 -> ok 613s Test: t_wide_sp_mix_a7r0w1b0 -> ok 613s Test: t_wide_sp_mix_a7r0w1b1 -> ok 613s Test: t_wide_sp_mix_a7r0w2b0 -> ok 614s Test: t_wide_sp_mix_a7r0w2b2 -> ok 614s Test: t_wide_sp_mix_a7r0w3b2 -> ok 614s Test: t_wide_sp_mix_a7r0w4b2 -> ok 614s Test: t_wide_sp_mix_a7r0w5b2 -> ok 615s Test: t_wide_sp_tied_a6r1w1b1 -> ok 615s Test: t_wide_sp_tied_a7r1w1b1 -> ok 615s Test: t_wide_sp_tied_a8r1w1b1 -> ok 615s Test: t_wide_sp_tied_a6r0w0b0 -> ok 615s Test: t_wide_sp_tied_a6r1w0b0 -> ok 615s Test: t_wide_sp_tied_a6r2w0b0 -> ok 616s Test: t_wide_sp_tied_a6r3w0b0 -> ok 616s Test: t_wide_sp_tied_a6r4w0b0 -> ok 616s Test: t_wide_sp_tied_a6r5w0b0 -> ok 616s Test: t_wide_sp_tied_a6r0w1b0 -> ok 617s Test: t_wide_sp_tied_a6r0w1b1 -> ok 617s Test: t_wide_sp_tied_a6r0w2b0 -> ok 617s Test: t_wide_sp_tied_a6r0w2b2 -> ok 617s Test: t_wide_sp_tied_a6r0w3b2 -> ok 617s Test: t_wide_sp_tied_a6r0w4b2 -> ok 618s Test: t_wide_sp_tied_a6r0w5b2 -> ok 618s Test: t_wide_sp_tied_a7r0w0b0 -> ok 618s Test: t_wide_sp_tied_a7r1w0b0 -> ok 618s Test: t_wide_sp_tied_a7r2w0b0 -> ok 619s Test: t_wide_sp_tied_a7r3w0b0 -> ok 619s Test: t_wide_sp_tied_a7r4w0b0 -> ok 619s Test: t_wide_sp_tied_a7r5w0b0 -> ok 619s Test: t_wide_sp_tied_a7r0w1b0 -> ok 620s Test: t_wide_sp_tied_a7r0w1b1 -> ok 620s Test: t_wide_sp_tied_a7r0w2b0 -> ok 620s Test: t_wide_sp_tied_a7r0w2b2 -> ok 620s Test: t_wide_sp_tied_a7r0w3b2 -> ok 620s Test: t_wide_sp_tied_a7r0w4b2 -> ok 621s Test: t_wide_sp_tied_a7r0w5b2 -> ok 621s Test: t_wide_read_a6r1w1b1 -> ok 621s Test: t_wide_write_a6r1w1b1 -> ok 621s Test: t_wide_read_a7r1w1b1 -> ok 621s Test: t_wide_write_a7r1w1b1 -> ok 622s Test: t_wide_read_a8r1w1b1 -> ok 622s Test: t_wide_write_a8r1w1b1 -> ok 622s Test: t_wide_read_a6r0w0b0 -> ok 622s Test: t_wide_write_a6r0w0b0 -> ok 622s Test: t_wide_read_a6r1w0b0 -> ok 623s Test: t_wide_write_a6r1w0b0 -> ok 623s Test: t_wide_read_a6r2w0b0 -> ok 623s Test: t_wide_write_a6r2w0b0 -> ok 623s Test: t_wide_read_a6r3w0b0 -> ok 623s Test: t_wide_write_a6r3w0b0 -> ok 624s Test: t_wide_read_a6r4w0b0 -> ok 624s Test: t_wide_write_a6r4w0b0 -> ok 624s Test: t_wide_read_a6r5w0b0 -> ok 624s Test: t_wide_write_a6r5w0b0 -> ok 625s Test: t_wide_read_a6r0w1b0 -> ok 625s Test: t_wide_write_a6r0w1b0 -> ok 625s Test: t_wide_read_a6r0w1b1 -> ok 625s Test: t_wide_write_a6r0w1b1 -> ok 625s Test: t_wide_read_a6r0w2b0 -> ok 625s Test: t_wide_write_a6r0w2b0 -> ok 626s Test: t_wide_read_a6r0w2b2 -> ok 626s Test: t_wide_write_a6r0w2b2 -> ok 626s Test: t_wide_read_a6r0w3b2 -> ok 626s Test: t_wide_write_a6r0w3b2 -> ok 626s Test: t_wide_read_a6r0w4b2 -> ok 627s Test: t_wide_write_a6r0w4b2 -> ok 627s Test: t_wide_read_a6r0w5b2 -> ok 627s Test: t_wide_write_a6r0w5b2 -> ok 627s Test: t_wide_read_a7r0w0b0 -> ok 628s Test: t_wide_write_a7r0w0b0 -> ok 628s Test: t_wide_read_a7r1w0b0 -> ok 628s Test: t_wide_write_a7r1w0b0 -> ok 628s Test: t_wide_read_a7r2w0b0 -> ok 628s Test: t_wide_write_a7r2w0b0 -> ok 629s Test: t_wide_read_a7r3w0b0 -> ok 629s Test: t_wide_write_a7r3w0b0 -> ok 629s Test: t_wide_read_a7r4w0b0 -> ok 629s Test: t_wide_write_a7r4w0b0 -> ok 629s Test: t_wide_read_a7r5w0b0 -> ok 630s Test: t_wide_write_a7r5w0b0 -> ok 630s Test: t_wide_read_a7r0w1b0 -> ok 630s Test: t_wide_write_a7r0w1b0 -> ok 630s Test: t_wide_read_a7r0w1b1 -> ok 630s Test: t_wide_write_a7r0w1b1 -> ok 631s Test: t_wide_read_a7r0w2b0 -> ok 631s Test: t_wide_write_a7r0w2b0 -> ok 631s Test: t_wide_read_a7r0w2b2 -> ok 631s Test: t_wide_write_a7r0w2b2 -> ok 632s Test: t_wide_read_a7r0w3b2 -> ok 632s Test: t_wide_write_a7r0w3b2 -> ok 632s Test: t_wide_read_a7r0w4b2 -> ok 632s Test: t_wide_write_a7r0w4b2 -> ok 633s Test: t_wide_read_a7r0w5b2 -> ok 633s Test: t_wide_write_a7r0w5b2 -> ok 633s Test: t_quad_port_a2d2 -> ok 633s Test: t_quad_port_a4d2 -> ok 633s Test: t_quad_port_a5d2 -> ok 634s Test: t_quad_port_a4d4 -> ok 634s Test: t_quad_port_a6d2 -> ok 634s Test: t_quad_port_a4d8 -> ok 634s Test: t_wide_quad_a4w2r1 -> ok 634s Test: t_wide_oct_a4w2r1 -> ok 635s Test: t_wide_quad_a4w2r2 -> ok 635s Test: t_wide_oct_a4w2r2 -> ok 635s Test: t_wide_quad_a4w2r3 -> ok 635s Test: t_wide_oct_a4w2r3 -> ok 635s Test: t_wide_quad_a4w2r4 -> ok 636s Test: t_wide_oct_a4w2r4 -> ok 636s Test: t_wide_quad_a4w2r5 -> ok 636s Test: t_wide_oct_a4w2r5 -> ok 636s Test: t_wide_quad_a4w2r6 -> ok 636s Test: t_wide_oct_a4w2r6 -> ok 636s Test: t_wide_quad_a4w2r7 -> ok 637s Test: t_wide_oct_a4w2r7 -> ok 637s Test: t_wide_quad_a4w2r8 -> ok 637s Test: t_wide_oct_a4w2r8 -> ok 637s Test: t_wide_quad_a4w2r9 -> ok 637s Test: t_wide_oct_a4w2r9 -> ok 638s Test: t_wide_quad_a4w4r1 -> ok 638s Test: t_wide_oct_a4w4r1 -> ok 638s Test: t_wide_quad_a4w4r4 -> ok 638s Test: t_wide_oct_a4w4r4 -> ok 638s Test: t_wide_quad_a4w4r6 -> ok 639s Test: t_wide_oct_a4w4r6 -> ok 639s Test: t_wide_quad_a4w4r9 -> ok 639s Test: t_wide_oct_a4w4r9 -> ok 639s Test: t_wide_quad_a5w2r1 -> ok 639s Test: t_wide_oct_a5w2r1 -> ok 639s Test: t_wide_quad_a5w2r4 -> ok 640s Test: t_wide_oct_a5w2r4 -> ok 640s Test: t_wide_quad_a5w2r9 -> ok 640s Test: t_wide_oct_a5w2r9 -> ok 640s Test: t_no_reset -> ok 640s Test: t_gclken -> ok 640s Test: t_ungated -> ok 641s Test: t_gclken_ce -> ok 641s Test: t_grden -> ok 641s Test: t_grden_ce -> ok 641s Test: t_exclwr -> ok 641s Test: t_excl_rst -> ok 642s Test: t_transwr -> ok 642s Test: t_trans_rst -> ok 642s Test: t_wr_byte -> ok 642s Test: t_trans_byte -> ok 642s Test: t_wr_rst_byte -> ok 643s Test: t_rst_wr_byte -> ok 643s Test: t_rdenrst_wr_byte -> ok 643s make[1]: Leaving directory '/tmp/autopkgtest.dZoNHp/build.YkG/src/tests/memlib' 643s cd tests/bram && bash run-test.sh "" 643s generating tests.. 643s PRNG seed: 345363 643s running tests.. 643s make[1]: Entering directory '/tmp/autopkgtest.dZoNHp/build.YkG/src/tests/bram' 644s Passed memory_bram test 00_01. 644s Passed memory_bram test 00_02. 645s Passed memory_bram test 00_03. 645s Passed memory_bram test 00_04. 646s Passed memory_bram test 01_00. 647s Passed memory_bram test 01_02. 648s Passed memory_bram test 01_03. 649s Passed memory_bram test 01_04. 650s Passed memory_bram test 02_00. 651s Passed memory_bram test 02_01. 651s Passed memory_bram test 02_03. 653s Passed memory_bram test 02_04. 654s Passed memory_bram test 03_00. 655s Passed memory_bram test 03_01. 656s Passed memory_bram test 03_02. 657s Passed memory_bram test 03_04. 658s Passed memory_bram test 04_00. 658s Passed memory_bram test 04_01. 659s Passed memory_bram test 04_02. 660s Passed memory_bram test 04_03. 660s make[1]: Leaving directory '/tmp/autopkgtest.dZoNHp/build.YkG/src/tests/bram' 660s cd tests/various && bash run-test.sh 660s make[1]: Entering directory '/tmp/autopkgtest.dZoNHp/build.YkG/src/tests/various' 660s Warning: Wire abc9_test027.$abc$91$o is used but has no driver. 660s Passed abc9.ys 660s Passed aiger_dff.ys 660s Passed attrib05_port_conn.ys 660s Passed attrib07_func_call.ys 660s Passed autoname.ys 660s Passed blackbox_wb.ys 660s Passed bug1496.ys 660s Passed bug1531.ys 660s Passed bug1614.ys 660s Passed bug1710.ys 660s Warning: Yosys has only limited support for tri-state logic at the moment. (< svinterface1_tb.v:50: $finish called at 420000 (10ps) 716s svinterface1_tb.v:50: $finish called at 420000 (10ps) 716s ok 716s Test: svinterface_at_top -> svinterface_at_top_tb.v:61: $finish called at 420000 (10ps) 716s svinterface_at_top_tb_wrapper.v:61: $finish called at 420000 (10ps) 716s ERROR! 716s Test: load_and_derive ->ok 716s Test: resolve_types ->ok 716s cd tests/svtypes && bash run-test.sh "" 716s make[1]: Entering directory '/tmp/autopkgtest.dZoNHp/build.YkG/src/tests/svtypes' 716s Passed enum_simple.ys 716s Passed logic_rom.ys 716s < ok 729s Test ../../techlibs/anlogic/cells_sim.v -> ok 729s Test ../../techlibs/coolrunner2/cells_sim.v -> ok 729s Test ../../techlibs/ecp5/cells_sim.v -> ok 729s Test ../../techlibs/efinix/cells_sim.v -> ok 730s Test ../../techlibs/gatemate/cells_sim.v -> ok 730s Test ../../techlibs/gowin/cells_sim.v -> ok 730s Test ../../techlibs/greenpak4/cells_sim.v -> ok 730s Test ../../techlibs/ice40/cells_sim.v -DICE40_HX ->../../techlibs/ice40/cells_sim.v:2231: warning: Choosing typ expression. 730s ../../techlibs/ice40/cells_sim.v:2231: warning: Choosing typ expression. 730s ../../techlibs/ice40/cells_sim.v:2233: warning: Choosing typ expression. 730s ../../techlibs/ice40/cells_sim.v:2233: warning: Choosing typ expression. 730s ../../techlibs/ice40/cells_sim.v:2235: warning: Choosing typ expression. 730s ../../techlibs/ice40/cells_sim.v:2235: warning: Choosing typ expression. 730s ../../techlibs/ice40/cells_sim.v:2237: warning: Choosing typ expression. 730s ../../techlibs/ice40/cells_sim.v:2237: warning: Choosing typ expression. 730s ../../techlibs/ice40/cells_sim.v:2239: warning: Choosing typ expression. 730s ../../techlibs/ice40/cells_sim.v:2239: warning: Choosing typ expression. 730s ok 730s Test ../../techlibs/ice40/cells_sim.v -DICE40_LP ->../../techlibs/ice40/cells_sim.v:2295: warning: Choosing typ expression. 730s ../../techlibs/ice40/cells_sim.v:2295: warning: Choosing typ expression. 730s ok 730s Test ../../techlibs/ice40/cells_sim.v -DICE40_U ->../../techlibs/ice40/cells_sim.v:2297: warning: Choosing typ expression. 730s ../../techlibs/ice40/cells_sim.v:2297: warning: Choosing typ expression. 730s ../../techlibs/ice40/cells_sim.v:2299: warning: Choosing typ expression. 730s ../../techlibs/ice40/cells_sim.v:2299: warning: Choosing typ expression. 730s ../../techlibs/ice40/cells_sim.v:2301: warning: Choosing typ expression. 730s ../../techlibs/ice40/cells_sim.v:2301: warning: Choosing typ expression. 730s ../../techlibs/ice40/cells_sim.v:2303: warning: Choosing typ expression. 730s ../../techlibs/ice40/cells_sim.v:2303: warning: Choosing typ expression. 730s ../../techlibs/ice40/cells_sim.v:2359: warning: Choosing typ expression. 730s ../../techlibs/ice40/cells_sim.v:2359: warning: Choosing typ expression. 730s ../../techlibs/ice40/cells_sim.v:2361: warning: Choosing typ expression. 730s ../../techlibs/ice40/cells_sim.v:2361: warning: Choosing typ expression. 730s ../../techlibs/ice40/cells_sim.v:2363: warning: Choosing typ expression. 730s ../../techlibs/ice40/cells_sim.v:2363: warning: Choosing typ expression. 730s ../../techlibs/ice40/cells_sim.v:2365: warning: Choosing typ expression. 730s ../../techlibs/ice40/cells_sim.v:2365: warning: Choosing typ expression. 730s ../../techlibs/ice40/cells_sim.v:2367: warning: Choosing typ expression. 730s ../../techlibs/ice40/cells_sim.v:2367: warning: Choosing typ expression. 730s ok 730s Test ../../techlibs/intel/cyclone10lp/cells_sim.v -> ok 730s Test ../../techlibs/intel/max10/cells_sim.v -> ok 730s Test ../../techlibs/intel/cycloneive/cells_sim.v -> ok 730s Test ../../techlibs/intel/cycloneiv/cells_sim.v -> ok 730s Test ../../techlibs/intel_alm/cyclonev/cells_sim.v -> ok 730s Test ../../techlibs/nexus/cells_sim.v -> ok 730s Test ../../techlibs/quicklogic/cells_sim.v -> ok 730s Test ../../techlibs/sf2/cells_sim.v -> ok 730s Test ../../techlibs/xilinx/cells_sim.v -> ok 730s Test ../../techlibs/common/simcells.v -> ok 730s Test ../../techlibs/common/simlib.v -> ok 730s cd tests/arch/ice40 && bash run-test.sh "" 730s make[1]: Entering directory '/tmp/autopkgtest.dZoNHp/build.YkG/src/tests/arch/ice40' 731s Passed add_sub.ys 733s Passed adffs.ys 733s Warning: Resizing cell port SSCounter6o.l0.I3 from 32 bits to 1 bits. 733s Warning: Resizing cell port SSCounter6o.c0.CI from 32 bits to 1 bits. 733s Warning: Resizing cell port SSCounter6o.lien.I0 from 32 bits to 1 bits. 733s Warning: Resizing cell port SSCounter6o.lien.I1 from 32 bits to 1 bits. 734s Passed bug1597.ys 735s Passed bug1598.ys 736s Passed bug1626.ys 749s Passed bug1644.ys 750s Passed bug2061.ys 751s Passed counter.ys 752s Passed dffs.ys 759s Passed dpram.ys 760s Passed fsm.ys 760s Passed ice40_dsp.ys 761s Passed ice40_opt.ys 761s Passed ice40_wrapcarry.ys 763s Passed latches.ys 764s Passed logic.ys 769s Passed macc.ys 813s Passed memories.ys 813s Passed mul.ys 816s Passed mux.ys 817s Warning: wire '\data' is assigned in a block at rom.v:10.5-10.15. 817s Warning: wire '\data' is assigned in a block at rom.v:11.5-11.15. 817s Warning: wire '\data' is assigned in a block at rom.v:12.5-12.15. 817s Warning: wire '\data' is assigned in a block at rom.v:13.6-13.16. 817s Warning: wire '\data' is assigned in a block at rom.v:14.6-14.16. 817s Warning: wire '\data' is assigned in a block at rom.v:15.6-15.16. 817s Warning: wire '\data' is assigned in a block at rom.v:16.11-16.21. 817s Passed rom.ys 818s Passed shifter.ys 818s Warning: wire '\read_data' is assigned in a block at spram.v:19.3-19.25. 819s Passed spram.ys 820s Passed tribuf.ys 820s make[1]: Leaving directory '/tmp/autopkgtest.dZoNHp/build.YkG/src/tests/arch/ice40' 820s cd tests/arch/xilinx && bash run-test.sh "" 820s make[1]: Entering directory '/tmp/autopkgtest.dZoNHp/build.YkG/src/tests/arch/xilinx' 833s Warning: Whitebox '$paramod\FDRE\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. 833s Warning: Whitebox 'FDSE' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. 833s Warning: Whitebox '$paramod\FDRE_1\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. 833s Warning: Whitebox '$paramod\FDSE_1\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. 854s Passed abc9_dff.ys 858s Warning: Shift register inference not yet supported for family xc3s. 860s Passed add_sub.ys 875s Passed adffs.ys 879s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DIADI from 64 bits to 16 bits. 879s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOADO from 64 bits to 16 bits. 879s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOBDO from 64 bits to 16 bits. 879s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOPADOP from 8 bits to 2 bits. 879s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOPBDOP from 8 bits to 2 bits. 879s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.WEA from 4 bits to 2 bits. 887s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.WEBWE from 1 bits to 4 bits. 890s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DIADI from 64 bits to 16 bits. 890s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOADO from 64 bits to 16 bits. 890s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOBDO from 64 bits to 16 bits. 890s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOPADOP from 8 bits to 2 bits. 890s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOPBDOP from 8 bits to 2 bits. 890s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.WEA from 4 bits to 2 bits. 891s Warning: Selection "asym_ram_sdp_read_wider" did not match any module. 902s Passed asym_ram_sdp.ys 906s Warning: Resizing cell port block_ram.memory.0.0.DIADI from 64 bits to 16 bits. 906s Warning: Resizing cell port block_ram.memory.0.0.DOADO from 64 bits to 16 bits. 906s Warning: Resizing cell port block_ram.memory.0.0.DOBDO from 64 bits to 16 bits. 906s Warning: Resizing cell port block_ram.memory.0.0.DOPADOP from 8 bits to 2 bits. 906s Warning: Resizing cell port block_ram.memory.0.0.DOPBDOP from 8 bits to 2 bits. 906s Warning: Resizing cell port block_ram.memory.0.0.WEA from 4 bits to 2 bits. 927s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DIADI from 64 bits to 16 bits. 927s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOADO from 64 bits to 16 bits. 927s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOBDO from 64 bits to 16 bits. 927s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOPADOP from 8 bits to 2 bits. 927s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOPBDOP from 8 bits to 2 bits. 927s Warning: Resizing cell port distributed_ram_manual.memory.0.0.WEA from 4 bits to 2 bits. 927s Passed attributes_test.ys 931s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIADI from 64 bits to 16 bits. 931s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOADO from 64 bits to 16 bits. 931s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOBDO from 64 bits to 16 bits. 931s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPADOP from 8 bits to 2 bits. 931s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPBDOP from 8 bits to 2 bits. 931s Warning: Resizing cell port sync_ram_sdp.memory.0.0.WEA from 4 bits to 2 bits. 935s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIPADIP from 8 bits to 2 bits. 950s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIADI from 64 bits to 32 bits. 950s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIPADIP from 8 bits to 4 bits. 950s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOADO from 64 bits to 32 bits. 950s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOBDO from 64 bits to 32 bits. 950s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPADOP from 8 bits to 4 bits. 950s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPBDOP from 8 bits to 4 bits. 974s Passed blockram.ys 977s Passed bug1460.ys 981s Passed bug1462.ys 984s Passed bug1480.ys 989s Passed bug1598.ys 990s Warning: Wire top.\t is used but has no driver. 990s Warning: Wire top.\in is used but has no driver. 993s Passed bug1605.ys 993s Passed bug3670.ys 997s Passed counter.ys 1014s Passed dffs.ys 1027s Passed dsp_abc9.ys 1040s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef. 1040s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef. 1087s Passed dsp_cascade.ys 1090s Passed dsp_fastfir.ys 1096s Passed dsp_simd.ys 1100s Warning: Shift register inference not yet supported for family xc3se. 1103s Passed fsm.ys 1115s Passed latches.ys 1119s Passed logic.ys 1152s Warning: Shift register inference not yet supported for family xc3s. 1155s Passed lutram.ys 1164s Passed macc.ys 1170s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef. 1170s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef. 1171s Passed mul.ys 1171s Warning: Replacing memory \M with list of registers. See mul_unsigned.v:25 1180s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef. 1180s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef. 1184s Passed mul_unsigned.ys 1199s Passed mux.ys 1199s Warning: Shift register inference not yet supported for family xc3se. 1209s Passed mux_lut4.ys 1216s Passed nosrl.ys 1216s Passed opt_lut_ins.ys 1226s Passed pmgen_xilinx_srl.ys 1230s Warning: Resizing cell port priority_memory.mem.0.0.ADDRARDADDR from 16 bits to 15 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.0.ADDRBWRADDR from 16 bits to 15 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.0.DINADIN from 64 bits to 32 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.0.DINBDIN from 64 bits to 32 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.0.DINPADINP from 8 bits to 4 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.0.DINPBDINP from 8 bits to 4 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.0.DOUTADOUT from 64 bits to 32 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.0.DOUTBDOUT from 64 bits to 32 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.0.DOUTPADOUTP from 8 bits to 4 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.0.DOUTPBDOUTP from 8 bits to 4 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.0.WEBWE from 4 bits to 8 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.1.ADDRARDADDR from 16 bits to 15 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.1.ADDRBWRADDR from 16 bits to 15 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.1.DINADIN from 64 bits to 32 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.1.DINBDIN from 64 bits to 32 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.1.DINPADINP from 8 bits to 4 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.1.DINPBDINP from 8 bits to 4 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.1.DOUTADOUT from 64 bits to 32 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.1.DOUTBDOUT from 64 bits to 32 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.1.DOUTPADOUTP from 8 bits to 4 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.1.DOUTPBDOUTP from 8 bits to 4 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.1.WEBWE from 4 bits to 8 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.2.ADDRARDADDR from 16 bits to 15 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.2.ADDRBWRADDR from 16 bits to 15 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.2.DINADIN from 64 bits to 32 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.2.DINBDIN from 64 bits to 32 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.2.DINPADINP from 8 bits to 4 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.2.DINPBDINP from 8 bits to 4 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.2.DOUTADOUT from 64 bits to 32 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.2.DOUTBDOUT from 64 bits to 32 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.2.DOUTPADOUTP from 8 bits to 4 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.2.DOUTPBDOUTP from 8 bits to 4 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.2.WEBWE from 4 bits to 8 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.3.ADDRARDADDR from 16 bits to 15 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.3.ADDRBWRADDR from 16 bits to 15 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.3.DINADIN from 64 bits to 32 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.3.DINBDIN from 64 bits to 32 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.3.DINPADINP from 8 bits to 4 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.3.DINPBDINP from 8 bits to 4 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.3.DOUTADOUT from 64 bits to 32 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.3.DOUTBDOUT from 64 bits to 32 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.3.DOUTPADOUTP from 8 bits to 4 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.3.DOUTPBDOUTP from 8 bits to 4 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.3.WEBWE from 4 bits to 8 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.4.ADDRARDADDR from 16 bits to 15 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.4.ADDRBWRADDR from 16 bits to 15 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.4.DINADIN from 64 bits to 32 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.4.DINBDIN from 64 bits to 32 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.4.DINPADINP from 8 bits to 4 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.4.DINPBDINP from 8 bits to 4 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.4.DOUTADOUT from 64 bits to 32 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.4.DOUTBDOUT from 64 bits to 32 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.4.DOUTPADOUTP from 8 bits to 4 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.4.DOUTPBDOUTP from 8 bits to 4 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.4.WEBWE from 4 bits to 8 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.5.ADDRARDADDR from 16 bits to 15 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.5.ADDRBWRADDR from 16 bits to 15 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.5.DINADIN from 64 bits to 32 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.5.DINBDIN from 64 bits to 32 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.5.DINPADINP from 8 bits to 4 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.5.DINPBDINP from 8 bits to 4 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.5.DOUTADOUT from 64 bits to 32 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.5.DOUTBDOUT from 64 bits to 32 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.5.DOUTPADOUTP from 8 bits to 4 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.5.DOUTPBDOUTP from 8 bits to 4 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.5.WEBWE from 4 bits to 8 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.6.ADDRARDADDR from 16 bits to 15 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.6.ADDRBWRADDR from 16 bits to 15 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.6.DINADIN from 64 bits to 32 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.6.DINBDIN from 64 bits to 32 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.6.DINPADINP from 8 bits to 4 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.6.DINPBDINP from 8 bits to 4 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.6.DOUTADOUT from 64 bits to 32 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.6.DOUTBDOUT from 64 bits to 32 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.6.DOUTPADOUTP from 8 bits to 4 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.6.DOUTPBDOUTP from 8 bits to 4 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.6.WEBWE from 4 bits to 8 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.7.ADDRARDADDR from 16 bits to 15 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.7.ADDRBWRADDR from 16 bits to 15 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.7.DINADIN from 64 bits to 32 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.7.DINBDIN from 64 bits to 32 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.7.DINPADINP from 8 bits to 4 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.7.DINPBDINP from 8 bits to 4 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.7.DOUTADOUT from 64 bits to 32 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.7.DOUTBDOUT from 64 bits to 32 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.7.DOUTPADOUTP from 8 bits to 4 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.7.DOUTPBDOUTP from 8 bits to 4 bits. 1230s Warning: Resizing cell port priority_memory.mem.0.7.WEBWE from 4 bits to 8 bits. 1234s Warning: Resizing cell port priority_memory.mem.0.0.BWE_A from 8 bits to 9 bits. 1234s Warning: Resizing cell port priority_memory.mem.0.0.BWE_B from 8 bits to 9 bits. 1244s Warning: Resizing cell port sp_write_first.mem.0.0.BWE_A from 8 bits to 9 bits. 1247s Warning: Resizing cell port sp_read_first.mem.0.0.BWE_B from 8 bits to 9 bits. 1248s Passed priority_memory.ys 1251s Passed shifter.ys 1255s Passed tribuf.ys 1258s Passed xilinx_dffopt.ys 1258s Passed xilinx_dsp.ys 1259s Passed xilinx_srl.ys 1266s Passed macc.sh 1273s Passed tribuf.sh 1273s make[1]: Leaving directory '/tmp/autopkgtest.dZoNHp/build.YkG/src/tests/arch/xilinx' 1273s cd tests/arch/ecp5 && bash run-test.sh "" 1273s make[1]: Entering directory '/tmp/autopkgtest.dZoNHp/build.YkG/src/tests/arch/ecp5' 1273s Passed add_sub.ys 1275s Passed adffs.ys 1276s Passed bug1459.ys 1277s Passed bug1598.ys 1277s Passed bug1630.ys 1277s Warning: Literal has a width of 16 bit, but value requires 184 bit. (<>>/,/<<>>/ {print $0}' 1661s + iverilog -o iverilog-initial_display initial_display.v 1661s + ./iverilog-initial_display 1661s + diff yosys-initial_display.log iverilog-initial_display.log 1661s + test_always_display clk -DEVENT_CLK 1661s + local subtest=clk 1661s + shift 1661s + ../../yosys -p 'read_verilog -DEVENT_CLK always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk-1.v 1661s + ../../yosys -p 'read_verilog yosys-always_display-clk-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk-2.v 1661s 1661s /----------------------------------------------------------------------------\ 1661s | | 1661s | yosys -- Yosys Open SYnthesis Suite | 1661s | | 1661s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1661s | | 1661s | Permission to use, copy, modify, and/or distribute this software for any | 1661s | purpose with or without fee is hereby granted, provided that the above | 1661s | copyright notice and this permission notice appear in all copies. | 1661s | | 1661s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1661s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1661s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1661s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1661s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1661s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1661s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1661s | | 1661s \----------------------------------------------------------------------------/ 1661s 1661s Yosys 0.33 (git sha1 2584903a060) 1661s 1661s 1661s -- Running command `read_verilog -DEVENT_CLK always_display.v; proc; opt_expr -mux_bool; clean' -- 1661s 1661s 1. Executing Verilog-2005 frontend: always_display.v 1661s Parsing Verilog input from `always_display.v' to AST representation. 1661s Generating RTLIL representation for module `\m'. 1661s Successfully finished Verilog frontend. 1661s 1661s 2. Executing PROC pass (convert processes to netlists). 1661s 1661s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Cleaned up 0 empty switches. 1661s 1661s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1661s Removed a total of 0 dead cases. 1661s 1661s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1661s Removed 1 redundant assignment. 1661s Promoted 1 assignment to connection. 1661s 1661s 2.4. Executing PROC_INIT pass (extract init attributes). 1661s 1661s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1661s 1661s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1661s Converted 0 switches. 1661s 1661s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1661s Creating decoders for process `\m.$proc$always_display.v:4$1'. 1661s 1661s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1661s 1661s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1661s 1661s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1661s 1661s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Removing empty process `m.$proc$always_display.v:4$1'. 1661s Cleaned up 0 empty switches. 1661s 1661s 2.12. Executing OPT_EXPR pass (perform const folding). 1661s Optimizing module m. 1661s 1661s 3. Executing OPT_EXPR pass (perform const folding). 1661s Optimizing module m. 1661s Removed 0 unused cells and 1 unused wires. 1661s 1661s -- Writing to `yosys-always_display-clk-1.v' using backend `verilog' -- 1661s 1661s 4. Executing Verilog backend. 1661s 1661s 4.1. Executing BMUXMAP pass. 1661s 1661s 4.2. Executing DEMUXMAP pass. 1661s Dumping module `\m'. 1661s 1661s End of script. Logfile hash: 0de35d2746, CPU: user 0.01s system 0.00s, MEM: 10.37 MB peak 1661s Yosys 0.33 (git sha1 2584903a060) 1661s Time spent: 35% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ... 1661s 1661s /----------------------------------------------------------------------------\ 1661s | | 1661s | yosys -- Yosys Open SYnthesis Suite | 1661s | | 1661s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1661s | | 1661s | Permission to use, copy, modify, and/or distribute this software for any | 1661s | purpose with or without fee is hereby granted, provided that the above | 1661s | copyright notice and this permission notice appear in all copies. | 1661s | | 1661s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1661s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1661s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1661s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1661s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1661s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1661s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1661s | | 1661s \----------------------------------------------------------------------------/ 1661s 1661s Yosys 0.33 (git sha1 2584903a060) 1661s 1661s 1661s -- Running command `read_verilog yosys-always_display-clk-1.v; proc; opt_expr -mux_bool; clean' -- 1661s 1661s 1. Executing Verilog-2005 frontend: yosys-always_display-clk-1.v 1661s Parsing Verilog input from `yosys-always_display-clk-1.v' to AST representation. 1661s Generating RTLIL representation for module `\m'. 1661s Successfully finished Verilog frontend. 1661s 1661s 2. Executing PROC pass (convert processes to netlists). 1661s 1661s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk-1.v:18$1'. 1661s Cleaned up 1 empty switch. 1661s 1661s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1661s Removed a total of 0 dead cases. 1661s 1661s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1661s Removed 1 redundant assignment. 1661s Promoted 1 assignment to connection. 1661s 1661s 2.4. Executing PROC_INIT pass (extract init attributes). 1661s 1661s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1661s 1661s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1661s Converted 0 switches. 1661s 1661s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1661s Creating decoders for process `\m.$proc$yosys-always_display-clk-1.v:18$1'. 1661s 1661s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1661s 1661s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1661s 1661s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1661s 1661s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Removing empty process `m.$proc$yosys-always_display-clk-1.v:18$1'. 1661s Cleaned up 0 empty switches. 1661s 1661s 2.12. Executing OPT_EXPR pass (perform const folding). 1661s Optimizing module m. 1661s 1661s 3. Executing OPT_EXPR pass (perform const folding). 1661s Optimizing module m. 1661s Removed 0 unused cells and 1 unused wires. 1661s 1661s -- Writing to `yosys-always_display-clk-2.v' using backend `verilog' -- 1661s 1661s 4. Executing Verilog backend. 1661s 1661s 4.1. Executing BMUXMAP pass. 1661s 1661s 4.2. Executing DEMUXMAP pass. 1661s Dumping module `\m'. 1661s 1661s End of script. Logfile hash: e35e8bb689, CPU: user 0.01s system 0.00s, MEM: 10.37 MB peak 1661s Yosys 0.33 (git sha1 2584903a060) 1661s Time spent: 35% 2x opt_expr (0 sec), 21% 1x clean (0 sec), ... 1661s 1661s /----------------------------------------------------------------------------\ 1661s | | 1661s | yosys -- Yosys Open SYnthesis Suite | 1661s | | 1661s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1661s | | 1661s | Permission to use, copy, modify, and/or distribute this software for any | 1661s | purpose with or without fee is hereby granted, provided that the above | 1661s | copyright notice and this permission notice appear in all copies. | 1661s | | 1661s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1661s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1661s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1661s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1661s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1661s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1661s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1661s | | 1661s \----------------------------------------------------------------------------/ 1661s 1661s Yosys 0.33 (git sha1 2584903a060) 1661s 1661s 1661s -- Running command `read_verilog -DEVENT_CLK_RST always_display.v; proc; opt_expr -mux_bool; clean' -- 1661s 1661s 1. Executing Verilog-2005 frontend: always_display.v 1661s Parsing Verilog input from `always_display.v' to AST representation. 1661s Generating RTLIL representation for module `\m'. 1661s Successfully finished Verilog frontend. 1661s 1661s 2. Executing PROC pass (convert processes to netlists). 1661s 1661s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Cleaned up 0 empty switches. 1661s 1661s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1661s Removed a total of 0 dead cases. 1661s 1661s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1661s Removed 1 redundant assignment. 1661s Promoted 1 assignment to connection. 1661s 1661s 2.4. Executing PROC_INIT pass (extract init attributes). 1661s 1661s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1661s 1661s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1661s Converted 0 switches. 1661s 1661s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1661s Creating decoders for process `\m.$proc$always_display.v:7$1'. 1661s 1661s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1661s 1661s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1661s 1661s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1661s 1661s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Removing empty process `m.$proc$always_display.v:7$1'. 1661s Cleaned up 0 empty switches. 1661s 1661s 2.12. Executing OPT_EXPR pass (perform const folding). 1661s Optimizing module m. 1661s 1661s 3. Executing OPT_EXPR pass (perform const folding). 1661s Optimizing module m. 1661s + diff yosys-always_display-clk-1.v yosys-always_display-clk-2.v 1661s + test_always_display clk_rst -DEVENT_CLK_RST 1661s + local subtest=clk_rst 1661s + shift 1661s + ../../yosys -p 'read_verilog -DEVENT_CLK_RST always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst-1.v 1661s Removed 0 unused cells and 1 unused wires. 1661s 1661s -- Writing to `yosys-always_display-clk_rst-1.v' using backend `verilog' -- 1661s 1661s 4. Executing Verilog backend. 1661s 1661s 4.1. Executing BMUXMAP pass. 1661s 1661s 4.2. Executing DEMUXMAP pass. 1661s Dumping module `\m'. 1661s 1661s End of script. Logfile hash: c95608ddf0, CPU: user 0.01s system 0.00s, MEM: 10.25 MB peak 1661s Yosys 0.33 (git sha1 2584903a060) 1661s Time spent: 36% 2x opt_expr (0 sec), 21% 1x clean (0 sec), ... 1661s 1661s /----------------------------------------------------------------------------\ 1661s | | 1661s | yosys -- Yosys Open SYnthesis Suite | 1661s | | 1661s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1661s | | 1661s | Permission to use, copy, modify, and/or distribute this software for any | 1661s | purpose with or without fee is hereby granted, provided that the above | 1661s | copyright notice and this permission notice appear in all copies. | 1661s | | 1661s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1661s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1661s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1661s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1661s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1661s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1661s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1661s | | 1661s \----------------------------------------------------------------------------/ 1661s 1661s Yosys 0.33 (git sha1 2584903a060) 1661s 1661s 1661s -- Running command `read_verilog yosys-always_display-clk_rst-1.v; proc; opt_expr -mux_bool; clean' -- 1661s 1661s 1. Executing Verilog-2005 frontend: yosys-always_display-clk_rst-1.v 1661s Parsing Verilog input from `yosys-always_display-clk_rst-1.v' to AST representation. 1661s Generating RTLIL representation for module `\m'. 1661s Successfully finished Verilog frontend. 1661s 1661s 2. Executing PROC pass (convert processes to netlists). 1661s 1661s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_rst-1.v:18$1'. 1661s Cleaned up 1 empty switch. 1661s 1661s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1661s Removed a total of 0 dead cases. 1661s 1661s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1661s Removed 1 redundant assignment. 1661s Promoted 1 assignment to connection. 1661s 1661s 2.4. Executing PROC_INIT pass (extract init attributes). 1661s 1661s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1661s 1661s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1661s Converted 0 switches. 1661s 1661s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1661s Creating decoders for process `\m.$proc$yosys-always_display-clk_rst-1.v:18$1'. 1661s 1661s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1661s 1661s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1661s 1661s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1661s 1661s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Removing empty process `m.$proc$yosys-always_display-clk_rst-1.v:18$1'. 1661s Cleaned up 0 empty switches. 1661s 1661s 2.12. Executing OPT_EXPR pass (perform const folding). 1661s Optimizing module m. 1661s 1661s 3. Executing OPT_EXPR pass (perform const folding). 1661s Optimizing module m. 1661s Removed 0 unused cells and 1 unused wires. 1661s 1661s -- Writing to `yosys-always_display-clk_rst-2.v' using backend `verilog' -- 1661s 1661s 4. Executing Verilog backend. 1661s 1661s 4.1. Executing BMUXMAP pass. 1661s 1661s 4.2. Executing DEMUXMAP pass. 1661s Dumping module `\m'. 1661s 1661s End of script. Logfile hash: faf50513c3, CPU: user 0.00s system 0.00s, MEM: 10.38 MB peak 1661s Yosys 0.33 (git sha1 2584903a060) 1661s Time spent: 34% 2x opt_expr (0 sec), 21% 1x clean (0 sec), ... 1661s + ../../yosys -p 'read_verilog yosys-always_display-clk_rst-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst-2.v 1661s + diff yosys-always_display-clk_rst-1.v yosys-always_display-clk_rst-2.v 1661s + test_always_display star -DEVENT_STAR 1661s + local subtest=star 1661s + shift 1661s 1661s /----------------------------------------------------------------------------\ 1661s | | 1661s | yosys -- Yosys Open SYnthesis Suite | 1661s | | 1661s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1661s | | 1661s | Permission to use, copy, modify, and/or distribute this software for any | 1661s | purpose with or without fee is hereby granted, provided that the above | 1661s | copyright notice and this permission notice appear in all copies. | 1661s | | 1661s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1661s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1661s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1661s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1661s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1661s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1661s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1661s | | 1661s \----------------------------------------------------------------------------/ 1661s 1661s Yosys 0.33 (git sha1 2584903a060) 1661s 1661s 1661s -- Running command `read_verilog -DEVENT_STAR always_display.v; proc; opt_expr -mux_bool; clean' -- 1661s 1661s 1. Executing Verilog-2005 frontend: always_display.v 1661s Parsing Verilog input from `always_display.v' to AST representation. 1661s Generating RTLIL representation for module `\m'. 1661s Successfully finished Verilog frontend. 1661s 1661s 2. Executing PROC pass (convert processes to netlists). 1661s 1661s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Cleaned up 0 empty switches. 1661s 1661s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1661s Removed a total of 0 dead cases. 1661s 1661s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1661s Removed 1 redundant assignment. 1661s Promoted 1 assignment to connection. 1661s 1661s 2.4. Executing PROC_INIT pass (extract init attributes). 1661s 1661s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1661s 1661s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1661s + ../../yosys -p 'read_verilog -DEVENT_STAR always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star-1.v 1661s Converted 0 switches. 1661s 1661s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1661s Creating decoders for process `\m.$proc$always_display.v:10$1'. 1661s 1661s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1661s 1661s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1661s 1661s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1661s 1661s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Removing empty process `m.$proc$always_display.v:10$1'. 1661s Cleaned up 0 empty switches. 1661s 1661s 2.12. Executing OPT_EXPR pass (perform const folding). 1661s Optimizing module m. 1661s 1661s 3. Executing OPT_EXPR pass (perform const folding). 1661s Optimizing module m. 1661s Removed 0 unused cells and 1 unused wires. 1661s 1661s -- Writing to `yosys-always_display-star-1.v' using backend `verilog' -- 1661s 1661s 4. Executing Verilog backend. 1661s 1661s 4.1. Executing BMUXMAP pass. 1661s 1661s 4.2. Executing DEMUXMAP pass. 1661s Dumping module `\m'. 1661s 1661s End of script. Logfile hash: 7b2c5274a5, CPU: user 0.00s system 0.00s, MEM: 10.07 MB peak 1661s Yosys 0.33 (git sha1 2584903a060) 1661s Time spent: 35% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ... 1661s 1661s /----------------------------------------------------------------------------\ 1661s | | 1661s | yosys -- Yosys Open SYnthesis Suite | 1661s | | 1661s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1661s | | 1661s | Permission to use, copy, modify, and/or distribute this software for any | 1661s | purpose with or without fee is hereby granted, provided that the above | 1661s | copyright notice and this permission notice appear in all copies. | 1661s | | 1661s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1661s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1661s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1661s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1661s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1661s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1661s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1661s | | 1661s \----------------------------------------------------------------------------/ 1661s 1661s Yosys 0.33 (git sha1 2584903a060) 1661s 1661s 1661s -- Running command `read_verilog yosys-always_display-star-1.v; proc; opt_expr -mux_bool; clean' -- 1661s 1661s 1. Executing Verilog-2005 frontend: yosys-always_display-star-1.v 1661s Parsing Verilog input from `yosys-always_display-star-1.v' to AST representation. 1661s Generating RTLIL representation for module `\m'. 1661s Successfully finished Verilog frontend. 1661s 1661s 2. Executing PROC pass (convert processes to netlists). 1661s 1661s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-star-1.v:18$1'. 1661s Cleaned up 1 empty switch. 1661s 1661s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1661s Removed a total of 0 dead cases. 1661s 1661s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1661s Removed 1 redundant assignment. 1661s Promoted 1 assignment to connection. 1661s 1661s 2.4. Executing PROC_INIT pass (extract init attributes). 1661s 1661s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1661s 1661s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1661s Converted 0 switches. 1661s 1661s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1661s Creating decoders for process `\m.$proc$yosys-always_display-star-1.v:18$1'. 1661s 1661s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1661s 1661s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1661s 1661s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1661s 1661s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Removing empty process `m.$proc$yosys-always_display-star-1.v:18$1'. 1661s Cleaned up 0 empty switches. 1661s 1661s 2.12. Executing OPT_EXPR pass (perform const folding). 1661s Optimizing module m. 1661s 1661s 3. Executing OPT_EXPR pass (perform const folding). 1661s Optimizing module m. 1661s Removed 0 unused cells and 1 unused wires. 1661s 1661s -- Writing to `yosys-always_display-star-2.v' using backend `verilog' -- 1661s 1661s 4. Executing Verilog backend. 1661s + ../../yosys -p 'read_verilog yosys-always_display-star-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star-2.v 1661s + diff yosys-always_display-star-1.v yosys-always_display-star-2.v 1661s + test_always_display clk_en -DEVENT_CLK -DCOND_EN 1661s + local subtest=clk_en 1661s + shift 1661s + ../../yosys -p 'read_verilog -DEVENT_CLK -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_en-1.v 1661s + ../../yosys -p 'read_verilog yosys-always_display-clk_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_en-2.v 1661s + diff yosys-always_display-clk_en-1.v yosys-always_display-clk_en-2.v 1661s + test_always_display clk_rst_en -DEVENT_CLK_RST -DCOND_EN 1661s + local subtest=clk_rst_en 1661s + shift 1661s + ../../yosys -p 'read_verilog -DEVENT_CLK_RST -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst_en-1.v 1661s 1661s 4.1. Executing BMUXMAP pass. 1661s 1661s 4.2. Executing DEMUXMAP pass. 1661s Dumping module `\m'. 1661s 1661s End of script. Logfile hash: 8979c5de0b, CPU: user 0.00s system 0.00s, MEM: 10.20 MB peak 1661s Yosys 0.33 (git sha1 2584903a060) 1661s Time spent: 35% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ... 1661s 1661s /----------------------------------------------------------------------------\ 1661s | | 1661s | yosys -- Yosys Open SYnthesis Suite | 1661s | | 1661s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1661s | | 1661s | Permission to use, copy, modify, and/or distribute this software for any | 1661s | purpose with or without fee is hereby granted, provided that the above | 1661s | copyright notice and this permission notice appear in all copies. | 1661s | | 1661s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1661s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1661s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1661s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1661s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1661s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1661s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1661s | | 1661s \----------------------------------------------------------------------------/ 1661s 1661s Yosys 0.33 (git sha1 2584903a060) 1661s 1661s 1661s -- Running command `read_verilog -DEVENT_CLK -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -- 1661s 1661s 1. Executing Verilog-2005 frontend: always_display.v 1661s Parsing Verilog input from `always_display.v' to AST representation. 1661s Generating RTLIL representation for module `\m'. 1661s Successfully finished Verilog frontend. 1661s 1661s 2. Executing PROC pass (convert processes to netlists). 1661s 1661s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Cleaned up 0 empty switches. 1661s 1661s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1661s Removed a total of 0 dead cases. 1661s 1661s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1661s Removed 0 redundant assignments. 1661s Promoted 0 assignments to connections. 1661s 1661s 2.4. Executing PROC_INIT pass (extract init attributes). 1661s 1661s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1661s 1661s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1661s Converted 0 switches. 1661s 1661s 1661s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1661s Creating decoders for process `\m.$proc$always_display.v:4$1'. 1661s 1/1: $display$always_display.v:15$2_EN 1661s 1661s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1661s 1661s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1661s 1661s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1661s 1661s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:4$1'. 1661s Removing empty process `m.$proc$always_display.v:4$1'. 1661s Cleaned up 1 empty switch. 1661s 1661s 2.12. Executing OPT_EXPR pass (perform const folding). 1661s Optimizing module m. 1661s 1661s 3. Executing OPT_EXPR pass (perform const folding). 1661s Optimizing module m. 1661s 1661s Removed 0 unused cells and 3 unused wires. 1661s 1661s -- Writing to `yosys-always_display-clk_en-1.v' using backend `verilog' -- 1661s 1661s 4. Executing Verilog backend. 1661s 1661s 4.1. Executing BMUXMAP pass. 1661s 1661s 4.2. Executing DEMUXMAP pass. 1661s Dumping module `\m'. 1661s 1661s End of script. Logfile hash: 4f8a3b339c, CPU: user 0.00s system 0.00s, MEM: 10.51 MB peak 1661s Yosys 0.33 (git sha1 2584903a060) 1661s Time spent: 38% 2x opt_expr (0 sec), 20% 1x clean (0 sec), ... 1661s 1661s /----------------------------------------------------------------------------\ 1661s | | 1661s | yosys -- Yosys Open SYnthesis Suite | 1661s | | 1661s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1661s | | 1661s | Permission to use, copy, modify, and/or distribute this software for any | 1661s | purpose with or without fee is hereby granted, provided that the above | 1661s | copyright notice and this permission notice appear in all copies. | 1661s | | 1661s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1661s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1661s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1661s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1661s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1661s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1661s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1661s | | 1661s \----------------------------------------------------------------------------/ 1661s 1661s Yosys 0.33 (git sha1 2584903a060) 1661s 1661s 1661s -- Running command `read_verilog yosys-always_display-clk_en-1.v; proc; opt_expr -mux_bool; clean' -- 1661s 1661s 1. Executing Verilog-2005 frontend: yosys-always_display-clk_en-1.v 1661s Parsing Verilog input from `yosys-always_display-clk_en-1.v' to AST representation. 1661s Generating RTLIL representation for module `\m'. 1661s Successfully finished Verilog frontend. 1661s 1661s 2. Executing PROC pass (convert processes to netlists). 1661s 1661s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Cleaned up 0 empty switches. 1661s 1661s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1661s Removed a total of 0 dead cases. 1661s 1661s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1661s Removed 0 redundant assignments. 1661s Promoted 0 assignments to connections. 1661s 1661s 2.4. Executing PROC_INIT pass (extract init attributes). 1661s 1661s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1661s 1661s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1661s Converted 0 switches. 1661s 1661s 1661s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1661s Creating decoders for process `\m.$proc$yosys-always_display-clk_en-1.v:18$1'. 1661s 1/1: $write$yosys-always_display-clk_en-1.v:20$2_EN 1661s 1661s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1661s 1661s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1661s 1661s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1661s 1661s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_en-1.v:18$1'. 1661s Removing empty process `m.$proc$yosys-always_display-clk_en-1.v:18$1'. 1661s Cleaned up 1 empty switch. 1661s 1661s 2.12. Executing OPT_EXPR pass (perform const folding). 1661s Optimizing module m. 1661s 1661s 3. Executing OPT_EXPR pass (perform const folding). 1661s Optimizing module m. 1661s 1661s Removed 0 unused cells and 3 unused wires. 1661s 1661s -- Writing to `yosys-always_display-clk_en-2.v' using backend `verilog' -- 1661s 1661s 4. Executing Verilog backend. 1661s 1661s 4.1. Executing BMUXMAP pass. 1661s 1661s 4.2. Executing DEMUXMAP pass. 1661s Dumping module `\m'. 1661s 1661s End of script. Logfile hash: 51e7fa3902, CPU: user 0.00s system 0.00s, MEM: 10.43 MB peak 1661s Yosys 0.33 (git sha1 2584903a060) 1661s Time spent: 36% 2x opt_expr (0 sec), 20% 1x clean (0 sec), ... 1661s + ../../yosys -p 'read_verilog yosys-always_display-clk_rst_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst_en-2.v 1661s + diff yosys-always_display-clk_rst_en-1.v yosys-always_display-clk_rst_en-2.v 1661s + test_always_display star_en -DEVENT_STAR -DCOND_EN 1661s + local subtest=star_en 1661s + shift 1661s + ../../yosys -p 'read_verilog -DEVENT_STAR -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star_en-1.v 1661s + ../../yosys -p 'read_verilog yosys-always_display-star_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star_en-2.v 1661s 1661s /----------------------------------------------------------------------------\ 1661s | | 1661s | yosys -- Yosys Open SYnthesis Suite | 1661s | | 1661s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1661s | | 1661s | Permission to use, copy, modify, and/or distribute this software for any | 1661s | purpose with or without fee is hereby granted, provided that the above | 1661s | copyright notice and this permission notice appear in all copies. | 1661s | | 1661s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1661s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1661s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1661s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1661s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1661s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1661s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1661s | | 1661s \----------------------------------------------------------------------------/ 1661s 1661s Yosys 0.33 (git sha1 2584903a060) 1661s 1661s 1661s -- Running command `read_verilog -DEVENT_CLK_RST -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -- 1661s 1661s 1. Executing Verilog-2005 frontend: always_display.v 1661s Parsing Verilog input from `always_display.v' to AST representation. 1661s Generating RTLIL representation for module `\m'. 1661s Successfully finished Verilog frontend. 1661s 1661s 2. Executing PROC pass (convert processes to netlists). 1661s 1661s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Cleaned up 0 empty switches. 1661s 1661s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1661s Removed a total of 0 dead cases. 1661s 1661s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1661s Removed 0 redundant assignments. 1661s Promoted 0 assignments to connections. 1661s 1661s 2.4. Executing PROC_INIT pass (extract init attributes). 1661s 1661s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1661s 1661s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1661s Converted 0 switches. 1661s 1661s 1661s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1661s Creating decoders for process `\m.$proc$always_display.v:7$1'. 1661s 1/1: $display$always_display.v:15$2_EN 1661s 1661s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1661s 1661s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1661s 1661s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1661s 1661s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:7$1'. 1661s Removing empty process `m.$proc$always_display.v:7$1'. 1661s Cleaned up 1 empty switch. 1661s 1661s 2.12. Executing OPT_EXPR pass (perform const folding). 1661s Optimizing module m. 1661s 1661s 3. Executing OPT_EXPR pass (perform const folding). 1661s Optimizing module m. 1661s 1661s Removed 0 unused cells and 3 unused wires. 1661s 1661s -- Writing to `yosys-always_display-clk_rst_en-1.v' using backend `verilog' -- 1661s 1661s 4. Executing Verilog backend. 1661s 1661s 4.1. Executing BMUXMAP pass. 1661s 1661s 4.2. Executing DEMUXMAP pass. 1661s Dumping module `\m'. 1661s 1661s End of script. Logfile hash: f9b4876f33, CPU: user 0.01s system 0.00s, MEM: 10.23 MB peak 1661s Yosys 0.33 (git sha1 2584903a060) 1661s Time spent: 40% 2x opt_expr (0 sec), 20% 1x clean (0 sec), ... 1661s 1661s /----------------------------------------------------------------------------\ 1661s | | 1661s | yosys -- Yosys Open SYnthesis Suite | 1661s | | 1661s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1661s | | 1661s | Permission to use, copy, modify, and/or distribute this software for any | 1661s | purpose with or without fee is hereby granted, provided that the above | 1661s | copyright notice and this permission notice appear in all copies. | 1661s | | 1661s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1661s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1661s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1661s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1661s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1661s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1661s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1661s | | 1661s \----------------------------------------------------------------------------/ 1661s 1661s Yosys 0.33 (git sha1 2584903a060) 1661s 1661s 1661s -- Running command `read_verilog yosys-always_display-clk_rst_en-1.v; proc; opt_expr -mux_bool; clean' -- 1661s 1661s 1. Executing Verilog-2005 frontend: yosys-always_display-clk_rst_en-1.v 1661s Parsing Verilog input from `yosys-always_display-clk_rst_en-1.v' to AST representation. 1661s Generating RTLIL representation for module `\m'. 1661s Successfully finished Verilog frontend. 1661s 1661s 2. Executing PROC pass (convert processes to netlists). 1661s 1661s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Cleaned up 0 empty switches. 1661s 1661s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1661s Removed a total of 0 dead cases. 1661s 1661s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1661s Removed 0 redundant assignments. 1661s Promoted 0 assignments to connections. 1661s 1661s 2.4. Executing PROC_INIT pass (extract init attributes). 1661s 1661s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1661s 1661s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1661s Converted 0 switches. 1661s 1661s 1661s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1661s Creating decoders for process `\m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'. 1661s 1/1: $write$yosys-always_display-clk_rst_en-1.v:20$2_EN 1661s 1661s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1661s 1661s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1661s 1661s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1661s 1661s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'. 1661s Removing empty process `m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'. 1661s Cleaned up 1 empty switch. 1661s 1661s 2.12. Executing OPT_EXPR pass (perform const folding). 1661s Optimizing module m. 1661s 1661s 3. Executing OPT_EXPR pass (perform const folding). 1661s Optimizing module m. 1661s 1661s Removed 0 unused cells and 3 unused wires. 1661s 1661s -- Writing to `yosys-always_display-clk_rst_en-2.v' using backend `verilog' -- 1661s 1661s 4. Executing Verilog backend. 1661s 1661s 4.1. Executing BMUXMAP pass. 1661s 1661s 4.2. Executing DEMUXMAP pass. 1661s Dumping module `\m'. 1661s 1661s End of script. Logfile hash: 0c4b4eaa9c, CPU: user 0.01s system 0.00s, MEM: 10.44 MB peak 1661s Yosys 0.33 (git sha1 2584903a060) 1661s Time spent: 36% 2x opt_expr (0 sec), 20% 1x clean (0 sec), ... 1661s 1661s /----------------------------------------------------------------------------\ 1661s | | 1661s | yosys -- Yosys Open SYnthesis Suite | 1661s | | 1661s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1661s | | 1661s | Permission to use, copy, modify, and/or distribute this software for any | 1661s | purpose with or without fee is hereby granted, provided that the above | 1661s | copyright notice and this permission notice appear in all copies. | 1661s | | 1661s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1661s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1661s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1661s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1661s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1661s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1661s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1661s | | 1661s \----------------------------------------------------------------------------/ 1661s 1661s Yosys 0.33 (git sha1 2584903a060) 1661s 1661s 1661s -- Running command `read_verilog -DEVENT_STAR -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -- 1661s 1661s 1. Executing Verilog-2005 frontend: always_display.v 1661s Parsing Verilog input from `always_display.v' to AST representation. 1661s Generating RTLIL representation for module `\m'. 1661s Successfully finished Verilog frontend. 1661s 1661s 2. Executing PROC pass (convert processes to netlists). 1661s 1661s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Cleaned up 0 empty switches. 1661s 1661s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1661s Removed a total of 0 dead cases. 1661s 1661s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1661s Removed 0 redundant assignments. 1661s Promoted 0 assignments to connections. 1661s 1661s 2.4. Executing PROC_INIT pass (extract init attributes). 1661s 1661s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1661s 1661s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1661s Converted 0 switches. 1661s 1661s 1661s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1661s Creating decoders for process `\m.$proc$always_display.v:10$1'. 1661s 1/1: $display$always_display.v:15$2_EN 1661s 1661s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1661s 1661s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1661s 1661s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1661s 1661s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:10$1'. 1661s Removing empty process `m.$proc$always_display.v:10$1'. 1661s Cleaned up 1 empty switch. 1661s 1661s 2.12. Executing OPT_EXPR pass (perform const folding). 1661s Optimizing module m. 1661s 1661s 3. Executing OPT_EXPR pass (perform const folding). 1661s Optimizing module m. 1661s 1661s Removed 0 unused cells and 3 unused wires. 1661s 1661s -- Writing to `yosys-always_display-star_en-1.v' using backend `verilog' -- 1661s 1661s 4. Executing Verilog backend. 1661s 1661s 4.1. Executing BMUXMAP pass. 1661s 1661s 4.2. Executing DEMUXMAP pass. 1661s Dumping module `\m'. 1661s 1661s End of script. Logfile hash: d6a7335726, CPU: user 0.01s system 0.00s, MEM: 10.26 MB peak 1661s Yosys 0.33 (git sha1 2584903a060) 1661s Time spent: 39% 2x opt_expr (0 sec), 20% 1x clean (0 sec), ... 1661s + diff yosys-always_display-star_en-1.v yosys-always_display-star_en-2.v 1661s 1661s /----------------------------------------------------------------------------\ 1661s | | 1661s | yosys -- Yosys Open SYnthesis Suite | 1661s | | 1661s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1661s | | 1661s | Permission to use, copy, modify, and/or distribute this software for any | 1661s | purpose with or without fee is hereby granted, provided that the above | 1661s | copyright notice and this permission notice appear in all copies. | 1661s | | 1661s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1661s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1661s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1661s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1661s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1661s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1661s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1661s | | 1661s \----------------------------------------------------------------------------/ 1661s 1661s Yosys 0.33 (git sha1 2584903a060) 1661s 1661s 1661s -- Running command `read_verilog yosys-always_display-star_en-1.v; proc; opt_expr -mux_bool; clean' -- 1661s 1661s 1. Executing Verilog-2005 frontend: yosys-always_display-star_en-1.v 1661s Parsing Verilog input from `yosys-always_display-star_en-1.v' to AST representation. 1661s Generating RTLIL representation for module `\m'. 1661s Successfully finished Verilog frontend. 1661s 1661s 2. Executing PROC pass (convert processes to netlists). 1661s 1661s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Cleaned up 0 empty switches. 1661s 1661s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1661s Removed a total of 0 dead cases. 1661s 1661s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1661s Removed 0 redundant assignments. 1661s Promoted 0 assignments to connections. 1661s 1661s 2.4. Executing PROC_INIT pass (extract init attributes). 1661s 1661s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1661s 1661s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1661s Converted 0 switches. 1661s 1661s 1661s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1661s Creating decoders for process `\m.$proc$yosys-always_display-star_en-1.v:18$1'. 1661s 1/1: $write$yosys-always_display-star_en-1.v:20$2_EN 1661s 1661s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1661s 1661s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1661s 1661s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1661s 1661s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-star_en-1.v:18$1'. 1661s Removing empty process `m.$proc$yosys-always_display-star_en-1.v:18$1'. 1661s Cleaned up 1 empty switch. 1661s 1661s 2.12. Executing OPT_EXPR pass (perform const folding). 1661s Optimizing module m. 1661s 1661s 3. Executing OPT_EXPR pass (perform const folding). 1661s Optimizing module m. 1661s 1661s Removed 0 unused cells and 3 unused wires. 1661s 1661s -- Writing to `yosys-always_display-star_en-2.v' using backend `verilog' -- 1661s 1661s 4. Executing Verilog backend. 1661s 1661s 4.1. Executing BMUXMAP pass. 1661s 1661s 4.2. Executing DEMUXMAP pass. 1661s Dumping module `\m'. 1661s 1661s End of script. Logfile hash: 18895a2046, CPU: user 0.01s system 0.00s, MEM: 10.30 MB peak 1661s Yosys 0.33 (git sha1 2584903a060) 1661s Time spent: 37% 2x opt_expr (0 sec), 20% 1x clean (0 sec), ... 1661s + test_roundtrip dec_unsigned -DBASE_DEC -DSIGN= 1661s + local subtest=dec_unsigned 1661s + shift 1661s + ../../yosys -p 'read_verilog -DBASE_DEC -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-dec_unsigned-1.v 1661s 1661s /----------------------------------------------------------------------------\ 1661s | | 1661s | yosys -- Yosys Open SYnthesis Suite | 1661s | | 1661s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1661s | | 1661s | Permission to use, copy, modify, and/or distribute this software for any | 1661s | purpose with or without fee is hereby granted, provided that the above | 1661s | copyright notice and this permission notice appear in all copies. | 1661s | | 1661s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1661s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1661s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1661s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1661s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1661s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1661s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1661s | | 1661s \----------------------------------------------------------------------------/ 1661s 1661s Yosys 0.33 (git sha1 2584903a060) 1661s 1661s 1661s -- Running command `read_verilog -DBASE_DEC -DSIGN= roundtrip.v; proc; clean' -- 1661s 1661s 1. Executing Verilog-2005 frontend: roundtrip.v 1661s Parsing Verilog input from `roundtrip.v' to AST representation. 1661s Generating RTLIL representation for module `\m'. 1661s Successfully finished Verilog frontend. 1661s 1661s 2. Executing PROC pass (convert processes to netlists). 1661s 1661s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Cleaned up 0 empty switches. 1661s 1661s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1661s Removed a total of 0 dead cases. 1661s 1661s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1661s Removed 1 redundant assignment. 1661s Promoted 1 assignment to connection. 1661s 1661s 2.4. Executing PROC_INIT pass (extract init attributes). 1661s 1661s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1661s 1661s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1661s Converted 0 switches. 1661s 1661s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1661s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 1661s 1661s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1661s 1661s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1661s 1661s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1661s 1661s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Removing empty process `m.$proc$roundtrip.v:3$1'. 1661s Cleaned up 0 empty switches. 1661s 1661s 2.12. Executing OPT_EXPR pass (perform const folding). 1661s Optimizing module m. 1661s Removed 0 unused cells and 1 unused wires. 1661s 1661s -- Writing to `yosys-roundtrip-dec_unsigned-1.v' using backend `verilog' -- 1661s 1661s 3. Executing Verilog backend. 1661s 1661s 3.1. Executing BMUXMAP pass. 1661s 1661s 3.2. Executing DEMUXMAP pass. 1661s Dumping module `\m'. 1661s 1661s End of script. Logfile hash: bfb187b86d, CPU: user 0.00s system 0.00s, MEM: 10.23 MB peak 1661s Yosys 0.33 (git sha1 2584903a060) 1661s Time spent: 26% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 1661s 1661s /----------------------------------------------------------------------------\ 1661s | | 1661s | yosys -- Yosys Open SYnthesis Suite | 1661s | | 1661s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1661s | | 1661s | Permission to use, copy, modify, and/or distribute this software for any | 1661s | purpose with or without fee is hereby granted, provided that the above | 1661s | copyright notice and this permission notice appear in all copies. | 1661s | | 1661s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1661s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1661s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1661s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1661s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1661s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1661s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1661s | | 1661s \----------------------------------------------------------------------------/ 1661s 1661s Yosys 0.33 (git sha1 2584903a060) 1661s 1661s 1661s -- Running command `read_verilog yosys-roundtrip-dec_unsigned-1.v; proc; clean' -- 1661s 1661s 1. Executing Verilog-2005 frontend: yosys-roundtrip-dec_unsigned-1.v 1661s Parsing Verilog input from `yosys-roundtrip-dec_unsigned-1.v' to AST representation. 1661s Generating RTLIL representation for module `\m'. 1661s Successfully finished Verilog frontend. 1661s 1661s 2. Executing PROC pass (convert processes to netlists). 1661s 1661s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'. 1661s Cleaned up 1 empty switch. 1661s 1661s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1661s Removed a total of 0 dead cases. 1661s 1661s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1661s Removed 1 redundant assignment. 1661s Promoted 1 assignment to connection. 1661s 1661s 2.4. Executing PROC_INIT pass (extract init attributes). 1661s 1661s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1661s 1661s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1661s Converted 0 switches. 1661s 1661s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1661s Creating decoders for process `\m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'. 1661s 1661s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1661s 1661s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1661s 1661s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1661s 1661s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Removing empty process `m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'. 1661s Cleaned up 0 empty switches. 1661s 1661s 2.12. Executing OPT_EXPR pass (perform const folding). 1661s Optimizing module m. 1661s Removed 0 unused cells and 1 unused wires. 1661s 1661s -- Writing to `yosys-roundtrip-dec_unsigned-2.v' using backend `verilog' -- 1661s 1661s 3. Executing Verilog backend. 1661s 1661s 3.1. Executing BMUXMAP pass. 1661s 1661s 3.2. Executing DEMUXMAP pass. 1661s Dumping module `\m'. 1661s 1661s End of script. Logfile hash: 4be9539e85, CPU: user 0.00s system 0.00s, MEM: 10.20 MB peak 1661s Yosys 0.33 (git sha1 2584903a060) 1661s Time spent: 28% 1x clean (0 sec), 19% 1x opt_expr (0 sec), ... 1661s + ../../yosys -p 'read_verilog yosys-roundtrip-dec_unsigned-1.v; proc; clean' -o yosys-roundtrip-dec_unsigned-2.v 1661s + diff yosys-roundtrip-dec_unsigned-1.v yosys-roundtrip-dec_unsigned-2.v 1661s + iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned roundtrip.v roundtrip_tb.v 1661s + ./iverilog-roundtrip-dec_unsigned 1661s + iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned-1 yosys-roundtrip-dec_unsigned-1.v roundtrip_tb.v 1661s + ./iverilog-roundtrip-dec_unsigned-1 1661s + iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned-2 yosys-roundtrip-dec_unsigned-2.v roundtrip_tb.v 1661s + ./iverilog-roundtrip-dec_unsigned-1 1661s + diff iverilog-roundtrip-dec_unsigned.log iverilog-roundtrip-dec_unsigned-1.log 1661s + diff iverilog-roundtrip-dec_unsigned-1.log iverilog-roundtrip-dec_unsigned-2.log 1661s + test_roundtrip dec_signed -DBASE_DEC -DSIGN=signed 1661s + local subtest=dec_signed 1661s + shift 1661s + ../../yosys -p 'read_verilog -DBASE_DEC -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-dec_signed-1.v 1661s 1661s /----------------------------------------------------------------------------\ 1661s | | 1661s | yosys -- Yosys Open SYnthesis Suite | 1661s | | 1661s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1661s | | 1661s | Permission to use, copy, modify, and/or distribute this software for any | 1661s | purpose with or without fee is hereby granted, provided that the above | 1661s | copyright notice and this permission notice appear in all copies. | 1661s | | 1661s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1661s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1661s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1661s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1661s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1661s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1661s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1661s | | 1661s \----------------------------------------------------------------------------/ 1661s 1661s Yosys 0.33 (git sha1 2584903a060) 1661s 1661s 1661s -- Running command `read_verilog -DBASE_DEC -DSIGN=signed roundtrip.v; proc; clean' -- 1661s 1661s 1. Executing Verilog-2005 frontend: roundtrip.v 1661s Parsing Verilog input from `roundtrip.v' to AST representation. 1661s Generating RTLIL representation for module `\m'. 1661s Successfully finished Verilog frontend. 1661s 1661s 2. Executing PROC pass (convert processes to netlists). 1661s 1661s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Cleaned up 0 empty switches. 1661s 1661s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1661s Removed a total of 0 dead cases. 1661s 1661s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1661s Removed 1 redundant assignment. 1661s Promoted 1 assignment to connection. 1661s 1661s 2.4. Executing PROC_INIT pass (extract init attributes). 1661s 1661s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1661s 1661s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1661s Converted 0 switches. 1661s 1661s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1661s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 1661s 1661s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1661s 1661s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1661s 1661s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1661s 1661s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Removing empty process `m.$proc$roundtrip.v:3$1'. 1661s Cleaned up 0 empty switches. 1661s 1661s 2.12. Executing OPT_EXPR pass (perform const folding). 1661s Optimizing module m. 1661s Removed 0 unused cells and 1 unused wires. 1661s 1661s -- Writing to `yosys-roundtrip-dec_signed-1.v' using backend `verilog' -- 1661s 1661s 3. Executing Verilog backend. 1661s 1661s 3.1. Executing BMUXMAP pass. 1661s 1661s 3.2. Executing DEMUXMAP pass. 1661s Dumping module `\m'. 1661s 1661s End of script. Logfile hash: bbdfa5ca92, CPU: user 0.00s system 0.00s, MEM: 10.27 MB peak 1661s Yosys 0.33 (git sha1 2584903a060) 1661s Time spent: 27% 1x clean (0 sec), 19% 1x opt_expr (0 sec), ... 1661s + ../../yosys -p 'read_verilog yosys-roundtrip-dec_signed-1.v; proc; clean' -o yosys-roundtrip-dec_signed-2.v 1661s 1661s /----------------------------------------------------------------------------\ 1661s | | 1661s | yosys -- Yosys Open SYnthesis Suite | 1661s | | 1661s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1661s | | 1661s | Permission to use, copy, modify, and/or distribute this software for any | 1661s | purpose with or without fee is hereby granted, provided that the above | 1661s | copyright notice and this permission notice appear in all copies. | 1661s | | 1661s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1661s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1661s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1661s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1661s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1661s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1661s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1661s | | 1661s \----------------------------------------------------------------------------/ 1661s 1661s Yosys 0.33 (git sha1 2584903a060) 1661s 1661s 1661s -- Running command `read_verilog yosys-roundtrip-dec_signed-1.v; proc; clean' -- 1661s 1661s 1. Executing Verilog-2005 frontend: yosys-roundtrip-dec_signed-1.v 1661s Parsing Verilog input from `yosys-roundtrip-dec_signed-1.v' to AST representation. 1661s Generating RTLIL representation for module `\m'. 1661s Successfully finished Verilog frontend. 1661s 1661s 2. Executing PROC pass (convert processes to netlists). 1661s 1661s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'. 1661s Cleaned up 1 empty switch. 1661s 1661s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1661s Removed a total of 0 dead cases. 1661s 1661s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1661s Removed 1 redundant assignment. 1661s Promoted 1 assignment to connection. 1661s 1661s 2.4. Executing PROC_INIT pass (extract init attributes). 1661s 1661s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1661s 1661s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1661s Converted 0 switches. 1661s 1661s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1661s Creating decoders for process `\m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'. 1661s 1661s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1661s 1661s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1661s 1661s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1661s 1661s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Removing empty process `m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'. 1661s Cleaned up 0 empty switches. 1661s 1661s 2.12. Executing OPT_EXPR pass (perform const folding). 1661s Optimizing module m. 1661s Removed 0 unused cells and 1 unused wires. 1661s 1661s -- Writing to `yosys-roundtrip-dec_signed-2.v' using backend `verilog' -- 1661s 1661s 3. Executing Verilog backend. 1661s 1661s 3.1. Executing BMUXMAP pass. 1661s 1661s 3.2. Executing DEMUXMAP pass. 1661s Dumping module `\m'. 1661s 1661s End of script. Logfile hash: b233de92a6, CPU: user 0.00s system 0.00s, MEM: 10.20 MB peak 1661s Yosys 0.33 (git sha1 2584903a060) 1661s Time spent: 25% 1x clean (0 sec), 22% 2x read_verilog (0 sec), ... 1661s + diff yosys-roundtrip-dec_signed-1.v yosys-roundtrip-dec_signed-2.v 1661s + iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed roundtrip.v roundtrip_tb.v 1661s + ./iverilog-roundtrip-dec_signed 1661s + iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed-1 yosys-roundtrip-dec_signed-1.v roundtrip_tb.v 1661s + ./iverilog-roundtrip-dec_signed-1 1661s + iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed-2 yosys-roundtrip-dec_signed-2.v roundtrip_tb.v 1661s + ./iverilog-roundtrip-dec_signed-1 1661s + diff iverilog-roundtrip-dec_signed.log iverilog-roundtrip-dec_signed-1.log 1661s + diff iverilog-roundtrip-dec_signed-1.log iverilog-roundtrip-dec_signed-2.log 1661s + test_roundtrip hex_unsigned -DBASE_HEX -DSIGN= 1661s + local subtest=hex_unsigned 1661s + shift 1661s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-hex_unsigned-1.v 1661s 1661s /----------------------------------------------------------------------------\ 1661s | | 1661s | yosys -- Yosys Open SYnthesis Suite | 1661s | | 1661s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1661s | | 1661s | Permission to use, copy, modify, and/or distribute this software for any | 1661s | purpose with or without fee is hereby granted, provided that the above | 1661s | copyright notice and this permission notice appear in all copies. | 1661s | | 1661s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1661s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1661s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1661s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1661s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1661s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1661s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1661s | | 1661s \----------------------------------------------------------------------------/ 1661s 1661s Yosys 0.33 (git sha1 2584903a060) 1661s 1661s 1661s -- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -- 1661s 1661s 1. Executing Verilog-2005 frontend: roundtrip.v 1661s Parsing Verilog input from `roundtrip.v' to AST representation. 1661s Generating RTLIL representation for module `\m'. 1661s Successfully finished Verilog frontend. 1661s 1661s 2. Executing PROC pass (convert processes to netlists). 1661s 1661s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Cleaned up 0 empty switches. 1661s 1661s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1661s Removed a total of 0 dead cases. 1661s 1661s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1661s Removed 1 redundant assignment. 1661s Promoted 1 assignment to connection. 1661s 1661s 2.4. Executing PROC_INIT pass (extract init attributes). 1661s 1661s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1661s 1661s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1661s Converted 0 switches. 1661s 1661s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1661s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 1661s 1661s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1661s 1661s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1661s 1661s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1661s 1661s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Removing empty process `m.$proc$roundtrip.v:3$1'. 1661s Cleaned up 0 empty switches. 1661s 1661s 2.12. Executing OPT_EXPR pass (perform const folding). 1661s Optimizing module m. 1661s Removed 0 unused cells and 1 unused wires. 1661s 1661s -- Writing to `yosys-roundtrip-hex_unsigned-1.v' using backend `verilog' -- 1661s 1661s 3. Executing Verilog backend. 1661s 1661s 3.1. Executing BMUXMAP pass. 1661s 1661s 3.2. Executing DEMUXMAP pass. 1661s Dumping module `\m'. 1661s 1661s End of script. Logfile hash: 2377f2e106, CPU: user 0.01s system 0.00s, MEM: 10.26 MB peak 1661s Yosys 0.33 (git sha1 2584903a060) 1661s Time spent: 27% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... 1661s 1661s /----------------------------------------------------------------------------\ 1661s | | 1661s | yosys -- Yosys Open SYnthesis Suite | 1661s | | 1661s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1661s | | 1661s | Permission to use, copy, modify, and/or distribute this software for any | 1661s | purpose with or without fee is hereby granted, provided that the above | 1661s | copyright notice and this permission notice appear in all copies. | 1661s | | 1661s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1661s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1661s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1661s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1661s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1661s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1661s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1661s | | 1661s \----------------------------------------------------------------------------/ 1661s 1661s Yosys 0.33 (git sha1 2584903a060) 1661s 1661s 1661s -- Running command `read_verilog yosys-roundtrip-hex_unsigned-1.v; proc; clean' -- 1661s 1661s 1. Executing Verilog-2005 frontend: yosys-roundtrip-hex_unsigned-1.v 1661s + ../../yosys -p 'read_verilog yosys-roundtrip-hex_unsigned-1.v; proc; clean' -o yosys-roundtrip-hex_unsigned-2.v 1661s Parsing Verilog input from `yosys-roundtrip-hex_unsigned-1.v' to AST representation. 1661s Generating RTLIL representation for module `\m'. 1661s Successfully finished Verilog frontend. 1661s 1661s 2. Executing PROC pass (convert processes to netlists). 1661s 1661s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'. 1661s Cleaned up 1 empty switch. 1661s 1661s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1661s Removed a total of 0 dead cases. 1661s 1661s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1661s Removed 1 redundant assignment. 1661s Promoted 1 assignment to connection. 1661s 1661s 2.4. Executing PROC_INIT pass (extract init attributes). 1661s 1661s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1661s 1661s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1661s Converted 0 switches. 1661s 1661s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1661s Creating decoders for process `\m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'. 1661s 1661s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1661s 1661s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1661s 1661s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1661s 1661s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Removing empty process `m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'. 1661s Cleaned up 0 empty switches. 1661s 1661s 2.12. Executing OPT_EXPR pass (perform const folding). 1661s Optimizing module m. 1661s Removed 0 unused cells and 1 unused wires. 1661s 1661s -- Writing to `yosys-roundtrip-hex_unsigned-2.v' using backend `verilog' -- 1661s 1661s 3. Executing Verilog backend. 1661s 1661s 3.1. Executing BMUXMAP pass. 1661s 1661s 3.2. Executing DEMUXMAP pass. 1661s Dumping module `\m'. 1661s 1661s End of script. Logfile hash: 06bfea69c8, CPU: user 0.00s system 0.00s, MEM: 10.39 MB peak 1661s Yosys 0.33 (git sha1 2584903a060) 1661s Time spent: 27% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 1661s + diff yosys-roundtrip-hex_unsigned-1.v yosys-roundtrip-hex_unsigned-2.v 1661s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned roundtrip.v roundtrip_tb.v 1661s + ./iverilog-roundtrip-hex_unsigned 1661s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned-1 yosys-roundtrip-hex_unsigned-1.v roundtrip_tb.v 1661s + ./iverilog-roundtrip-hex_unsigned-1 1661s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned-2 yosys-roundtrip-hex_unsigned-2.v roundtrip_tb.v 1661s + ./iverilog-roundtrip-hex_unsigned-1 1661s + diff iverilog-roundtrip-hex_unsigned.log iverilog-roundtrip-hex_unsigned-1.log 1661s + diff iverilog-roundtrip-hex_unsigned-1.log iverilog-roundtrip-hex_unsigned-2.log 1661s + test_roundtrip hex_signed -DBASE_HEX -DSIGN=signed 1661s + local subtest=hex_signed 1661s + shift 1661s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-hex_signed-1.v 1661s 1661s /----------------------------------------------------------------------------\ 1661s | | 1661s | yosys -- Yosys Open SYnthesis Suite | 1661s | | 1661s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1661s | | 1661s | Permission to use, copy, modify, and/or distribute this software for any | 1661s | purpose with or without fee is hereby granted, provided that the above | 1661s | copyright notice and this permission notice appear in all copies. | 1661s | | 1661s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1661s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1661s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1661s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1661s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1661s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1661s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1661s | | 1661s \----------------------------------------------------------------------------/ 1661s 1661s Yosys 0.33 (git sha1 2584903a060) 1661s 1661s 1661s -- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -- 1661s 1661s 1. Executing Verilog-2005 frontend: roundtrip.v 1661s Parsing Verilog input from `roundtrip.v' to AST representation. 1661s Generating RTLIL representation for module `\m'. 1661s Successfully finished Verilog frontend. 1661s 1661s 2. Executing PROC pass (convert processes to netlists). 1661s 1661s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Cleaned up 0 empty switches. 1661s 1661s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1661s Removed a total of 0 dead cases. 1661s 1661s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1661s Removed 1 redundant assignment. 1661s Promoted 1 assignment to connection. 1661s 1661s 2.4. Executing PROC_INIT pass (extract init attributes). 1661s 1661s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1661s 1661s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1661s Converted 0 switches. 1661s 1661s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1661s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 1661s 1661s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1661s 1661s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1661s 1661s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1661s 1661s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Removing empty process `m.$proc$roundtrip.v:3$1'. 1661s Cleaned up 0 empty switches. 1661s 1661s 2.12. Executing OPT_EXPR pass (perform const folding). 1661s Optimizing module m. 1661s Removed 0 unused cells and 1 unused wires. 1661s 1661s -- Writing to `yosys-roundtrip-hex_signed-1.v' using backend `verilog' -- 1661s 1661s 3. Executing Verilog backend. 1661s 1661s 3.1. Executing BMUXMAP pass. 1661s 1661s 3.2. Executing DEMUXMAP pass. 1661s Dumping module `\m'. 1661s 1661s End of script. Logfile hash: 824c3b1e65, CPU: user 0.00s system 0.00s, MEM: 10.38 MB peak 1661s Yosys 0.33 (git sha1 2584903a060) 1661s Time spent: 27% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 1661s + ../../yosys -p 'read_verilog yosys-roundtrip-hex_signed-1.v; proc; clean' -o yosys-roundtrip-hex_signed-2.v 1661s 1661s /----------------------------------------------------------------------------\ 1661s | | 1661s | yosys -- Yosys Open SYnthesis Suite | 1661s | | 1661s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1661s | | 1661s | Permission to use, copy, modify, and/or distribute this software for any | 1661s | purpose with or without fee is hereby granted, provided that the above | 1661s | copyright notice and this permission notice appear in all copies. | 1661s | | 1661s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1661s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1661s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1661s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1661s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1661s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1661s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1661s | | 1661s \----------------------------------------------------------------------------/ 1661s 1661s Yosys 0.33 (git sha1 2584903a060) 1661s 1661s 1661s -- Running command `read_verilog yosys-roundtrip-hex_signed-1.v; proc; clean' -- 1661s 1661s 1. Executing Verilog-2005 frontend: yosys-roundtrip-hex_signed-1.v 1661s Parsing Verilog input from `yosys-roundtrip-hex_signed-1.v' to AST representation. 1661s Generating RTLIL representation for module `\m'. 1661s Successfully finished Verilog frontend. 1661s 1661s 2. Executing PROC pass (convert processes to netlists). 1661s 1661s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'. 1661s Cleaned up 1 empty switch. 1661s 1661s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1661s Removed a total of 0 dead cases. 1661s 1661s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1661s Removed 1 redundant assignment. 1661s Promoted 1 assignment to connection. 1661s 1661s 2.4. Executing PROC_INIT pass (extract init attributes). 1661s 1661s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1661s 1661s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1661s Converted 0 switches. 1661s 1661s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1661s Creating decoders for process `\m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'. 1661s 1661s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1661s 1661s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1661s 1661s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1661s 1661s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Removing empty process `m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'. 1661s Cleaned up 0 empty switches. 1661s 1661s 2.12. Executing OPT_EXPR pass (perform const folding). 1661s Optimizing module m. 1661s Removed 0 unused cells and 1 unused wires. 1661s 1661s -- Writing to `yosys-roundtrip-hex_signed-2.v' using backend `verilog' -- 1661s 1661s 3. Executing Verilog backend. 1661s 1661s 3.1. Executing BMUXMAP pass. 1661s 1661s 3.2. Executing DEMUXMAP pass. 1661s Dumping module `\m'. 1661s 1661s End of script. Logfile hash: f18b3fa15b, CPU: user 0.01s system 0.00s, MEM: 10.23 MB peak 1661s Yosys 0.33 (git sha1 2584903a060) 1661s Time spent: 27% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 1661s + diff yosys-roundtrip-hex_signed-1.v yosys-roundtrip-hex_signed-2.v 1661s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed roundtrip.v roundtrip_tb.v 1661s + ./iverilog-roundtrip-hex_signed 1661s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed-1 yosys-roundtrip-hex_signed-1.v roundtrip_tb.v 1661s + ./iverilog-roundtrip-hex_signed-1 1661s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed-2 yosys-roundtrip-hex_signed-2.v roundtrip_tb.v 1661s + ./iverilog-roundtrip-hex_signed-1 1661s + diff iverilog-roundtrip-hex_signed.log iverilog-roundtrip-hex_signed-1.log 1661s 1661s /----------------------------------------------------------------------------\ 1661s | | 1661s | yosys -- Yosys Open SYnthesis Suite | 1661s | | 1661s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1661s | | 1661s | Permission to use, copy, modify, and/or distribute this software for any | 1661s | purpose with or without fee is hereby granted, provided that the above | 1661s | copyright notice and this permission notice appear in all copies. | 1661s | | 1661s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1661s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1661s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1661s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1661s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1661s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1661s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1661s | | 1661s \----------------------------------------------------------------------------/ 1661s 1661s Yosys 0.33 (git sha1 2584903a060) 1661s 1661s 1661s -- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -- 1661s 1661s 1. Executing Verilog-2005 frontend: roundtrip.v 1661s Parsing Verilog input from `roundtrip.v' to AST representation. 1661s Generating RTLIL representation for module `\m'. 1661s Successfully finished Verilog frontend. 1661s 1661s 2. Executing PROC pass (convert processes to netlists). 1661s 1661s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Cleaned up 0 empty switches. 1661s 1661s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1661s Removed a total of 0 dead cases. 1661s 1661s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1661s Removed 1 redundant assignment. 1661s Promoted 1 assignment to connection. 1661s 1661s 2.4. Executing PROC_INIT pass (extract init attributes). 1661s 1661s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1661s 1661s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1661s Converted 0 switches. 1661s 1661s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1661s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 1661s 1661s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1661s 1661s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1661s 1661s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1661s 1661s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Removing empty process `m.$proc$roundtrip.v:3$1'. 1661s Cleaned up 0 empty switches. 1661s 1661s 2.12. Executing OPT_EXPR pass (perform const folding). 1661s + diff iverilog-roundtrip-hex_signed-1.log iverilog-roundtrip-hex_signed-2.log 1661s + test_roundtrip oct_unsigned -DBASE_HEX -DSIGN= 1661s + local subtest=oct_unsigned 1661s + shift 1661s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-oct_unsigned-1.v 1661s Optimizing module m. 1661s Removed 0 unused cells and 1 unused wires. 1661s 1661s -- Writing to `yosys-roundtrip-oct_unsigned-1.v' using backend `verilog' -- 1661s 1661s 3. Executing Verilog backend. 1661s 1661s 3.1. Executing BMUXMAP pass. 1661s 1661s 3.2. Executing DEMUXMAP pass. 1661s Dumping module `\m'. 1661s 1661s End of script. Logfile hash: b768358a65, CPU: user 0.00s system 0.00s, MEM: 10.28 MB peak 1661s Yosys 0.33 (git sha1 2584903a060) 1661s Time spent: 28% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... 1661s + ../../yosys -p 'read_verilog yosys-roundtrip-oct_unsigned-1.v; proc; clean' -o yosys-roundtrip-oct_unsigned-2.v 1661s 1661s /----------------------------------------------------------------------------\ 1661s | | 1661s | yosys -- Yosys Open SYnthesis Suite | 1661s | | 1661s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1661s | | 1661s | Permission to use, copy, modify, and/or distribute this software for any | 1661s | purpose with or without fee is hereby granted, provided that the above | 1661s | copyright notice and this permission notice appear in all copies. | 1661s | | 1661s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1661s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1661s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1661s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1661s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1661s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1661s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1661s | | 1661s \----------------------------------------------------------------------------/ 1661s 1661s Yosys 0.33 (git sha1 2584903a060) 1661s 1661s 1661s -- Running command `read_verilog yosys-roundtrip-oct_unsigned-1.v; proc; clean' -- 1661s 1661s 1. Executing Verilog-2005 frontend: yosys-roundtrip-oct_unsigned-1.v 1661s Parsing Verilog input from `yosys-roundtrip-oct_unsigned-1.v' to AST representation. 1661s Generating RTLIL representation for module `\m'. 1661s Successfully finished Verilog frontend. 1661s 1661s 2. Executing PROC pass (convert processes to netlists). 1661s 1661s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'. 1661s Cleaned up 1 empty switch. 1661s 1661s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1661s Removed a total of 0 dead cases. 1661s 1661s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1661s Removed 1 redundant assignment. 1661s Promoted 1 assignment to connection. 1661s 1661s 2.4. Executing PROC_INIT pass (extract init attributes). 1661s 1661s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1661s 1661s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1661s Converted 0 switches. 1661s 1661s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1661s Creating decoders for process `\m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'. 1661s 1661s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1661s 1661s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1661s 1661s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1661s 1661s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Removing empty process `m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'. 1661s Cleaned up 0 empty switches. 1661s 1661s 2.12. Executing OPT_EXPR pass (perform const folding). 1661s Optimizing module m. 1661s Removed 0 unused cells and 1 unused wires. 1661s 1661s -- Writing to `yosys-roundtrip-oct_unsigned-2.v' using backend `verilog' -- 1661s 1661s 3. Executing Verilog backend. 1661s 1661s 3.1. Executing BMUXMAP pass. 1661s 1661s 3.2. Executing DEMUXMAP pass. 1661s Dumping module `\m'. 1661s 1661s End of script. Logfile hash: 762621cd95, CPU: user 0.01s system 0.00s, MEM: 10.29 MB peak 1661s Yosys 0.33 (git sha1 2584903a060) 1661s Time spent: 26% 1x clean (0 sec), 19% 1x opt_expr (0 sec), ... 1661s + diff yosys-roundtrip-oct_unsigned-1.v yosys-roundtrip-oct_unsigned-2.v 1661s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned roundtrip.v roundtrip_tb.v 1661s + ./iverilog-roundtrip-oct_unsigned 1661s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned-1 yosys-roundtrip-oct_unsigned-1.v roundtrip_tb.v 1661s + ./iverilog-roundtrip-oct_unsigned-1 1661s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned-2 yosys-roundtrip-oct_unsigned-2.v roundtrip_tb.v 1661s + ./iverilog-roundtrip-oct_unsigned-1 1661s + diff iverilog-roundtrip-oct_unsigned.log iverilog-roundtrip-oct_unsigned-1.log 1661s + diff iverilog-roundtrip-oct_unsigned-1.log iverilog-roundtrip-oct_unsigned-2.log 1661s + test_roundtrip oct_signed -DBASE_HEX -DSIGN=signed 1661s + local subtest=oct_signed 1661s + shift 1661s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-oct_signed-1.v 1661s 1661s /----------------------------------------------------------------------------\ 1661s | | 1661s | yosys -- Yosys Open SYnthesis Suite | 1661s | | 1661s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1661s | | 1661s | Permission to use, copy, modify, and/or distribute this software for any | 1661s | purpose with or without fee is hereby granted, provided that the above | 1661s | copyright notice and this permission notice appear in all copies. | 1661s | | 1661s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1661s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1661s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1661s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1661s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1661s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1661s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1661s | | 1661s \----------------------------------------------------------------------------/ 1661s 1661s Yosys 0.33 (git sha1 2584903a060) 1661s 1661s 1661s -- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -- 1661s 1661s 1. Executing Verilog-2005 frontend: roundtrip.v 1661s Parsing Verilog input from `roundtrip.v' to AST representation. 1661s Generating RTLIL representation for module `\m'. 1661s Successfully finished Verilog frontend. 1661s 1661s 2. Executing PROC pass (convert processes to netlists). 1661s 1661s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Cleaned up 0 empty switches. 1661s 1661s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1661s Removed a total of 0 dead cases. 1661s 1661s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1661s Removed 1 redundant assignment. 1661s Promoted 1 assignment to connection. 1661s 1661s 2.4. Executing PROC_INIT pass (extract init attributes). 1661s 1661s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1661s 1661s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1661s Converted 0 switches. 1661s 1661s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1661s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 1661s 1661s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1661s 1661s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1661s 1661s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1661s 1661s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Removing empty process `m.$proc$roundtrip.v:3$1'. 1661s Cleaned up 0 empty switches. 1661s 1661s 2.12. Executing OPT_EXPR pass (perform const folding). 1661s Optimizing module m. 1661s Removed 0 unused cells and 1 unused wires. 1661s 1661s -- Writing to `yosys-roundtrip-oct_signed-1.v' using backend `verilog' -- 1661s 1661s 3. Executing Verilog backend. 1661s 1661s 3.1. Executing BMUXMAP pass. 1661s 1661s 3.2. Executing DEMUXMAP pass. 1661s Dumping module `\m'. 1661s 1661s End of script. Logfile hash: 7ec82b15e3, CPU: user 0.00s system 0.00s, MEM: 10.41 MB peak 1661s Yosys 0.33 (git sha1 2584903a060) 1661s Time spent: 26% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... 1661s 1661s /----------------------------------------------------------------------------\ 1661s | | 1661s | yosys -- Yosys Open SYnthesis Suite | 1661s | | 1661s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1661s | | 1661s | Permission to use, copy, modify, and/or distribute this software for any | 1661s | purpose with or without fee is hereby granted, provided that the above | 1661s | copyright notice and this permission notice appear in all copies. | 1661s | | 1661s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1661s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1661s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1661s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1661s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1661s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1661s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1661s | | 1661s \----------------------------------------------------------------------------/ 1661s 1661s Yosys 0.33 (git sha1 2584903a060) 1661s 1661s 1661s -- Running command `read_verilog yosys-roundtrip-oct_signed-1.v; proc; clean' -- 1661s 1661s 1. Executing Verilog-2005 frontend: yosys-roundtrip-oct_signed-1.v 1661s Parsing Verilog input from `yosys-roundtrip-oct_signed-1.v' to AST representation. 1661s Generating RTLIL representation for module `\m'. 1661s Successfully finished Verilog frontend. 1661s 1661s 2. Executing PROC pass (convert processes to netlists). 1661s 1661s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'. 1661s Cleaned up 1 empty switch. 1661s 1661s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1661s Removed a total of 0 dead cases. 1661s 1661s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1661s Removed 1 redundant assignment. 1661s Promoted 1 assignment to connection. 1661s 1661s 2.4. Executing PROC_INIT pass (extract init attributes). 1661s 1661s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1661s 1661s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1661s Converted 0 switches. 1661s 1661s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1661s Creating decoders for process `\m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'. 1661s 1661s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1661s 1661s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1661s 1661s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1661s 1661s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Removing empty process `m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'. 1661s Cleaned up 0 empty switches. 1661s 1661s 2.12. Executing OPT_EXPR pass (perform const folding). 1661s Optimizing module m. 1661s Removed 0 unused cells and 1 unused wires. 1661s 1661s -- Writing to `yosys-roundtrip-oct_signed-2.v' using backend `verilog' -- 1661s 1661s 3. Executing Verilog backend. 1661s 1661s 3.1. Executing BMUXMAP pass. 1661s 1661s 3.2. Executing DEMUXMAP pass. 1661s Dumping module `\m'. 1661s 1661s End of script. Logfile hash: a747b9bd4f, CPU: user 0.00s system 0.00s, MEM: 10.42 MB peak 1661s Yosys 0.33 (git sha1 2584903a060) 1661s Time spent: 27% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 1661s + ../../yosys -p 'read_verilog yosys-roundtrip-oct_signed-1.v; proc; clean' -o yosys-roundtrip-oct_signed-2.v 1661s + diff yosys-roundtrip-oct_signed-1.v yosys-roundtrip-oct_signed-2.v 1661s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed roundtrip.v roundtrip_tb.v 1661s + ./iverilog-roundtrip-oct_signed 1661s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed-1 yosys-roundtrip-oct_signed-1.v roundtrip_tb.v 1661s + ./iverilog-roundtrip-oct_signed-1 1661s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed-2 yosys-roundtrip-oct_signed-2.v roundtrip_tb.v 1661s + ./iverilog-roundtrip-oct_signed-1 1661s + diff iverilog-roundtrip-oct_signed.log iverilog-roundtrip-oct_signed-1.log 1661s + diff iverilog-roundtrip-oct_signed-1.log iverilog-roundtrip-oct_signed-2.log 1661s + test_roundtrip bin_unsigned -DBASE_HEX -DSIGN= 1661s + local subtest=bin_unsigned 1661s + shift 1661s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-bin_unsigned-1.v 1661s 1661s /----------------------------------------------------------------------------\ 1661s | | 1661s | yosys -- Yosys Open SYnthesis Suite | 1661s | | 1661s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1661s | | 1661s | Permission to use, copy, modify, and/or distribute this software for any | 1661s | purpose with or without fee is hereby granted, provided that the above | 1661s | copyright notice and this permission notice appear in all copies. | 1661s | | 1661s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1661s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1661s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1661s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1661s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1661s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1661s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1661s | | 1661s \----------------------------------------------------------------------------/ 1661s 1661s Yosys 0.33 (git sha1 2584903a060) 1661s 1661s 1661s -- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -- 1661s 1661s 1. Executing Verilog-2005 frontend: roundtrip.v 1661s Parsing Verilog input from `roundtrip.v' to AST representation. 1661s Generating RTLIL representation for module `\m'. 1661s Successfully finished Verilog frontend. 1661s 1661s 2. Executing PROC pass (convert processes to netlists). 1661s 1661s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Cleaned up 0 empty switches. 1661s 1661s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1661s Removed a total of 0 dead cases. 1661s 1661s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1661s Removed 1 redundant assignment. 1661s Promoted 1 assignment to connection. 1661s 1661s 2.4. Executing PROC_INIT pass (extract init attributes). 1661s 1661s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1661s 1661s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1661s Converted 0 switches. 1661s 1661s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1661s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 1661s 1661s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1661s 1661s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1661s 1661s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1661s 1661s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Removing empty process `m.$proc$roundtrip.v:3$1'. 1661s Cleaned up 0 empty switches. 1661s 1661s 2.12. Executing OPT_EXPR pass (perform const folding). 1661s Optimizing module m. 1661s Removed 0 unused cells and 1 unused wires. 1661s 1661s -- Writing to `yosys-roundtrip-bin_unsigned-1.v' using backend `verilog' -- 1661s 1661s 3. Executing Verilog backend. 1661s 1661s 3.1. Executing BMUXMAP pass. 1661s 1661s 3.2. Executing DEMUXMAP pass. 1661s Dumping module `\m'. 1661s 1661s End of script. Logfile hash: 270b564880, CPU: user 0.01s system 0.00s, MEM: 10.27 MB peak 1661s Yosys 0.33 (git sha1 2584903a060) 1661s Time spent: 30% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 1661s + ../../yosys -p 'read_verilog yosys-roundtrip-bin_unsigned-1.v; proc; clean' -o yosys-roundtrip-bin_unsigned-2.v 1661s 1661s /----------------------------------------------------------------------------\ 1661s | | 1661s | yosys -- Yosys Open SYnthesis Suite | 1661s | | 1661s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1661s | | 1661s | Permission to use, copy, modify, and/or distribute this software for any | 1661s | purpose with or without fee is hereby granted, provided that the above | 1661s | copyright notice and this permission notice appear in all copies. | 1661s | | 1661s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1661s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1661s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1661s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1661s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1661s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1661s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1661s | | 1661s \----------------------------------------------------------------------------/ 1661s 1661s Yosys 0.33 (git sha1 2584903a060) 1661s 1661s 1661s -- Running command `read_verilog yosys-roundtrip-bin_unsigned-1.v; proc; clean' -- 1661s 1661s 1. Executing Verilog-2005 frontend: yosys-roundtrip-bin_unsigned-1.v 1661s Parsing Verilog input from `yosys-roundtrip-bin_unsigned-1.v' to AST representation. 1661s Generating RTLIL representation for module `\m'. 1661s Successfully finished Verilog frontend. 1661s 1661s 2. Executing PROC pass (convert processes to netlists). 1661s 1661s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'. 1661s Cleaned up 1 empty switch. 1661s 1661s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1661s Removed a total of 0 dead cases. 1661s 1661s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1661s Removed 1 redundant assignment. 1661s Promoted 1 assignment to connection. 1661s 1661s 2.4. Executing PROC_INIT pass (extract init attributes). 1661s 1661s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1661s 1661s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1661s Converted 0 switches. 1661s 1661s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1661s Creating decoders for process `\m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'. 1661s 1661s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1661s 1661s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1661s 1661s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1661s 1661s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Removing empty process `m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'. 1661s Cleaned up 0 empty switches. 1661s 1661s 2.12. Executing OPT_EXPR pass (perform const folding). 1661s Optimizing module m. 1661s Removed 0 unused cells and 1 unused wires. 1661s 1661s -- Writing to `yosys-roundtrip-bin_unsigned-2.v' using backend `verilog' -- 1661s 1661s 3. Executing Verilog backend. 1661s 1661s 3.1. Executing BMUXMAP pass. 1661s 1661s 3.2. Executing DEMUXMAP pass. 1661s Dumping module `\m'. 1661s 1661s End of script. Logfile hash: dc9f56cb10, CPU: user 0.01s system 0.00s, MEM: 10.29 MB peak 1661s Yosys 0.33 (git sha1 2584903a060) 1661s Time spent: 26% 1x clean (0 sec), 23% 1x opt_expr (0 sec), ... 1661s + diff yosys-roundtrip-bin_unsigned-1.v yosys-roundtrip-bin_unsigned-2.v 1661s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned roundtrip.v roundtrip_tb.v 1661s + ./iverilog-roundtrip-bin_unsigned 1661s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned-1 yosys-roundtrip-bin_unsigned-1.v roundtrip_tb.v 1661s + ./iverilog-roundtrip-bin_unsigned-1 1661s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned-2 yosys-roundtrip-bin_unsigned-2.v roundtrip_tb.v 1661s + ./iverilog-roundtrip-bin_unsigned-1 1661s + diff iverilog-roundtrip-bin_unsigned.log iverilog-roundtrip-bin_unsigned-1.log 1661s + diff iverilog-roundtrip-bin_unsigned-1.log iverilog-roundtrip-bin_unsigned-2.log 1661s + test_roundtrip bin_signed -DBASE_HEX -DSIGN=signed 1661s + local subtest=bin_signed 1661s + shift 1661s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-bin_signed-1.v 1661s 1661s /----------------------------------------------------------------------------\ 1661s | | 1661s | yosys -- Yosys Open SYnthesis Suite | 1661s | | 1661s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1661s | | 1661s | Permission to use, copy, modify, and/or distribute this software for any | 1661s | purpose with or without fee is hereby granted, provided that the above | 1661s | copyright notice and this permission notice appear in all copies. | 1661s | | 1661s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1661s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1661s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1661s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1661s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1661s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1661s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1661s | | 1661s \----------------------------------------------------------------------------/ 1661s 1661s Yosys 0.33 (git sha1 2584903a060) 1661s 1661s 1661s -- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -- 1661s 1661s 1. Executing Verilog-2005 frontend: roundtrip.v 1661s Parsing Verilog input from `roundtrip.v' to AST representation. 1661s Generating RTLIL representation for module `\m'. 1661s Successfully finished Verilog frontend. 1661s 1661s 2. Executing PROC pass (convert processes to netlists). 1661s 1661s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Cleaned up 0 empty switches. 1661s 1661s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1661s Removed a total of 0 dead cases. 1661s 1661s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1661s Removed 1 redundant assignment. 1661s Promoted 1 assignment to connection. 1661s 1661s 2.4. Executing PROC_INIT pass (extract init attributes). 1661s 1661s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1661s 1661s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1661s Converted 0 switches. 1661s 1661s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1661s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 1661s 1661s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1661s 1661s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1661s 1661s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1661s 1661s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Removing empty process `m.$proc$roundtrip.v:3$1'. 1661s Cleaned up 0 empty switches. 1661s 1661s 2.12. Executing OPT_EXPR pass (perform const folding). 1661s Optimizing module m. 1661s Removed 0 unused cells and 1 unused wires. 1661s 1661s -- Writing to `yosys-roundtrip-bin_signed-1.v' using backend `verilog' -- 1661s 1661s 3. Executing Verilog backend. 1661s 1661s 3.1. Executing BMUXMAP pass. 1661s 1661s 3.2. Executing DEMUXMAP pass. 1661s Dumping module `\m'. 1661s 1661s End of script. Logfile hash: 7709253822, CPU: user 0.01s system 0.00s, MEM: 10.36 MB peak 1661s Yosys 0.33 (git sha1 2584903a060) 1661s Time spent: 25% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ... 1661s + ../../yosys -p 'read_verilog yosys-roundtrip-bin_signed-1.v; proc; clean' -o yosys-roundtrip-bin_signed-2.v 1661s 1661s /----------------------------------------------------------------------------\ 1661s | | 1661s | yosys -- Yosys Open SYnthesis Suite | 1661s | | 1661s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1661s | | 1661s | Permission to use, copy, modify, and/or distribute this software for any | 1661s | purpose with or without fee is hereby granted, provided that the above | 1661s | copyright notice and this permission notice appear in all copies. | 1661s | | 1661s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1661s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1661s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1661s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1661s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1661s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1661s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1661s | | 1661s \----------------------------------------------------------------------------/ 1661s 1661s Yosys 0.33 (git sha1 2584903a060) 1661s 1661s 1661s -- Running command `read_verilog yosys-roundtrip-bin_signed-1.v; proc; clean' -- 1661s 1661s 1. Executing Verilog-2005 frontend: yosys-roundtrip-bin_signed-1.v 1661s Parsing Verilog input from `yosys-roundtrip-bin_signed-1.v' to AST representation. 1661s Generating RTLIL representation for module `\m'. 1661s Successfully finished Verilog frontend. 1661s 1661s 2. Executing PROC pass (convert processes to netlists). 1661s 1661s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'. 1661s Cleaned up 1 empty switch. 1661s 1661s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1661s Removed a total of 0 dead cases. 1661s 1661s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1661s Removed 1 redundant assignment. 1661s Promoted 1 assignment to connection. 1661s 1661s 2.4. Executing PROC_INIT pass (extract init attributes). 1661s 1661s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1661s 1661s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1661s Converted 0 switches. 1661s 1661s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1661s Creating decoders for process `\m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'. 1661s 1661s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1661s 1661s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1661s 1661s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1661s 1661s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Removing empty process `m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'. 1661s Cleaned up 0 empty switches. 1661s 1661s 2.12. Executing OPT_EXPR pass (perform const folding). 1661s Optimizing module m. 1661s Removed 0 unused cells and 1 unused wires. 1661s 1661s -- Writing to `yosys-roundtrip-bin_signed-2.v' using backend `verilog' -- 1661s 1661s 3. Executing Verilog backend. 1661s 1661s 3.1. Executing BMUXMAP pass. 1661s 1661s 3.2. Executing DEMUXMAP pass. 1661s Dumping module `\m'. 1661s 1661s End of script. Logfile hash: 7e2d8271c4, CPU: user 0.00s system 0.00s, MEM: 10.28 MB peak 1661s Yosys 0.33 (git sha1 2584903a060) 1661s Time spent: 25% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... 1661s 1661s /----------------------------------------------------------------------------\ 1661s | | 1661s | yosys -- Yosys Open SYnthesis Suite | 1661s | | 1661s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1661s | | 1661s | Permission to use, copy, modify, and/or distribute this software for any | 1661s | purpose with or without fee is hereby granted, provided that the above | 1661s | copyright notice and this permission notice appear in all copies. | 1661s | | 1661s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1661s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1661s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1661s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1661s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1661s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1661s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1661s | | 1661s \----------------------------------------------------------------------------/ 1661s 1661s Yosys 0.33 (git sha1 2584903a060) 1661s 1661s 1661s -- Running command `read_verilog always_full.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_full.cc' -- 1661s 1661s 1. Executing Verilog-2005 frontend: always_full.v 1661s Parsing Verilog input from `always_full.v' to AST representation. 1661s Generating RTLIL representation for module `\always_full'. 1661s Successfully finished Verilog frontend. 1661s 1661s 2. Executing PROC pass (convert processes to netlists). 1661s 1661s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Cleaned up 0 empty switches. 1661s 1661s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1661s Removed a total of 0 dead cases. 1661s 1661s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1661s + diff yosys-roundtrip-bin_signed-1.v yosys-roundtrip-bin_signed-2.v 1661s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed roundtrip.v roundtrip_tb.v 1661s + ./iverilog-roundtrip-bin_signed 1661s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed-1 yosys-roundtrip-bin_signed-1.v roundtrip_tb.v 1661s + ./iverilog-roundtrip-bin_signed-1 1661s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed-2 yosys-roundtrip-bin_signed-2.v roundtrip_tb.v 1661s + ./iverilog-roundtrip-bin_signed-1 1661s + diff iverilog-roundtrip-bin_signed.log iverilog-roundtrip-bin_signed-1.log 1661s + diff iverilog-roundtrip-bin_signed-1.log iverilog-roundtrip-bin_signed-2.log 1661s + test_cxxrtl always_full 1661s + local subtest=always_full 1661s + shift 1661s + ../../yosys -p 'read_verilog always_full.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_full.cc' 1661s Removed 207 redundant assignments. 1661s Promoted 207 assignments to connections. 1661s 1661s 2.4. Executing PROC_INIT pass (extract init attributes). 1661s 1661s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1661s 1661s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1661s Converted 0 switches. 1661s 1661s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1661s Creating decoders for process `\always_full.$proc$always_full.v:3$1'. 1661s 1661s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1661s 1661s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1661s 1661s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1661s 1661s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Removing empty process `always_full.$proc$always_full.v:3$1'. 1661s Cleaned up 0 empty switches. 1661s 1661s 2.12. Executing OPT_EXPR pass (perform const folding). 1661s Optimizing module always_full. 1661s Removed 0 unused cells and 207 unused wires. 1661s 1661s 3. Executing CXXRTL backend. 1661s 1661s 3.1. Executing HIERARCHY pass (managing design hierarchy). 1661s 1661s 3.1.1. Finding top of design hierarchy.. 1661s root of 0 design levels: always_full 1661s Automatically selected always_full as design top module. 1661s 1661s 3.1.2. Analyzing design hierarchy.. 1661s Top module: \always_full 1661s 1661s 3.1.3. Analyzing design hierarchy.. 1661s Top module: \always_full 1661s Removed 0 unused modules. 1661s 1661s 3.2. Executing FLATTEN pass (flatten design). 1661s 1661s 3.3. Executing PROC pass (convert processes to netlists). 1661s 1661s 3.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Cleaned up 0 empty switches. 1661s 1661s 3.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1661s Removed a total of 0 dead cases. 1661s 1661s 3.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1661s Removed 0 redundant assignments. 1661s Promoted 0 assignments to connections. 1661s 1661s 3.3.4. Executing PROC_INIT pass (extract init attributes). 1661s 1661s 3.3.5. Executing PROC_ARST pass (detect async resets in processes). 1661s 1661s 3.3.6. Executing PROC_ROM pass (convert switches to ROMs). 1661s Converted 0 switches. 1661s 1661s 3.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1661s 1661s 3.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1661s 1661s 3.3.9. Executing PROC_DFF pass (convert process syncs to FFs). 1661s 1661s 3.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1661s 1661s 3.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1661s Cleaned up 0 empty switches. 1661s 1661s 3.3.12. Executing OPT_EXPR pass (perform const folding). 1661s Optimizing module always_full. 1661s 1661s 1661s 1661s End of script. Logfile hash: 6abd135c0a, CPU: user 0.02s system 0.00s, MEM: 11.54 MB peak 1661s Yosys 0.33 (git sha1 2584903a060) 1661s Time spent: 28% 2x read_verilog (0 sec), 21% 2x opt_expr (0 sec), ... 1661s + gcc -std=c++11 -o yosys-always_full -I../.. always_full_tb.cc -lstdc++ 1662s + ./yosys-always_full 1662s + iverilog -o iverilog-always_full always_full.v always_full_tb.v 1662s + ./iverilog-always_full 1662s + grep -v '\$finish called' 1662s + diff iverilog-always_full.log yosys-always_full.log 1662s + test_cxxrtl always_comb 1662s + local subtest=always_comb 1662s + shift 1662s + ../../yosys -p 'read_verilog always_comb.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_comb.cc' 1662s 1662s /----------------------------------------------------------------------------\ 1662s | | 1662s | yosys -- Yosys Open SYnthesis Suite | 1662s | | 1662s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1662s | | 1662s | Permission to use, copy, modify, and/or distribute this software for any | 1662s | purpose with or without fee is hereby granted, provided that the above | 1662s | copyright notice and this permission notice appear in all copies. | 1662s | | 1662s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1662s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1662s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1662s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1662s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1662s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1662s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1662s | | 1662s \----------------------------------------------------------------------------/ 1662s 1662s Yosys 0.33 (git sha1 2584903a060) 1662s 1662s 1662s -- Running command `read_verilog always_comb.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_comb.cc' -- 1662s 1662s 1. Executing Verilog-2005 frontend: always_comb.v 1662s Parsing Verilog input from `always_comb.v' to AST representation. 1662s Generating RTLIL representation for module `\top'. 1662s Generating RTLIL representation for module `\sub'. 1662s Successfully finished Verilog frontend. 1662s 1662s 2. Executing PROC pass (convert processes to netlists). 1662s 1662s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1662s Cleaned up 0 empty switches. 1662s 1662s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1662s Removed a total of 0 dead cases. 1662s 1662s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1662s Removed 0 redundant assignments. 1662s Promoted 4 assignments to connections. 1662s 1662s 2.4. Executing PROC_INIT pass (extract init attributes). 1662s Found init rule in `\top.$proc$always_comb.v:3$13'. 1662s Set init value: \b = 1'0 1662s Found init rule in `\top.$proc$always_comb.v:2$12'. 1662s Set init value: \a = 1'0 1662s 1662s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1662s 1662s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1662s Converted 0 switches. 1662s 1662s 1662s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1662s Creating decoders for process `\sub.$proc$always_comb.v:23$15'. 1662s 1/1: $display$always_comb.v:23$19_EN 1662s Creating decoders for process `\top.$proc$always_comb.v:3$13'. 1662s Creating decoders for process `\top.$proc$always_comb.v:2$12'. 1662s Creating decoders for process `\top.$proc$always_comb.v:8$1'. 1662s 1662s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1662s 1662s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1662s Creating register for signal `\top.\a' using process `\top.$proc$always_comb.v:8$1'. 1662s created $dff cell `$procdff$22' with positive edge clock. 1662s Creating register for signal `\top.\b' using process `\top.$proc$always_comb.v:8$1'. 1662s created $dff cell `$procdff$23' with positive edge clock. 1662s 1662s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1662s 1662s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1662s Found and cleaned up 1 empty switch in `\sub.$proc$always_comb.v:23$15'. 1662s Removing empty process `sub.$proc$always_comb.v:23$15'. 1662s Removing empty process `top.$proc$always_comb.v:3$13'. 1662s Removing empty process `top.$proc$always_comb.v:2$12'. 1662s Removing empty process `top.$proc$always_comb.v:8$1'. 1662s Cleaned up 1 empty switch. 1662s 1662s 2.12. Executing OPT_EXPR pass (perform const folding). 1662s Optimizing module sub. 1662s Optimizing module top. 1662s Removed 0 unused cells and 7 unused wires. 1662s 1662s 3. Executing CXXRTL backend. 1662s 1662s 3.1. Executing HIERARCHY pass (managing design hierarchy). 1662s 1662s 3.1.1. Finding top of design hierarchy.. 1662s root of 0 design levels: sub 1662s root of 1 design levels: top 1662s Automatically selected top as design top module. 1662s 1662s 3.1.2. Analyzing design hierarchy.. 1662s Top module: \top 1662s Used module: \sub 1662s 1662s 3.1.3. Analyzing design hierarchy.. 1662s Top module: \top 1662s Used module: \sub 1662s Removed 0 unused modules. 1662s 1662s 3.2. Executing FLATTEN pass (flatten design). 1662s Deleting now unused module sub. 1662s 1662s 1662s 3.3. Executing PROC pass (convert processes to netlists). 1662s 1662s 3.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1662s Cleaned up 0 empty switches. 1662s 1662s 3.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1662s Removed a total of 0 dead cases. 1662s 1662s 3.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1662s Removed 0 redundant assignments. 1662s Promoted 0 assignments to connections. 1662s 1662s 3.3.4. Executing PROC_INIT pass (extract init attributes). 1662s 1662s 3.3.5. Executing PROC_ARST pass (detect async resets in processes). 1662s 1662s 3.3.6. Executing PROC_ROM pass (convert switches to ROMs). 1662s Converted 0 switches. 1662s 1662s 3.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1662s 1662s 3.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1662s 1662s 3.3.9. Executing PROC_DFF pass (convert process syncs to FFs). 1662s 1662s 3.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1662s 1662s 3.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1662s Cleaned up 0 empty switches. 1662s 1662s 3.3.12. Executing OPT_EXPR pass (perform const folding). 1662s Optimizing module top. 1662s + gcc -std=c++11 -o yosys-always_comb -I../.. always_comb_tb.cc -lstdc++ 1662s 1662s 1662s 1662s End of script. Logfile hash: 03fe26efda, CPU: user 0.01s system 0.00s, MEM: 10.55 MB peak 1662s Yosys 0.33 (git sha1 2584903a060) 1662s Time spent: 27% 2x opt_expr (0 sec), 18% 1x clean (0 sec), ... 1663s + ./yosys-always_comb 1663s + iverilog -o iverilog-always_comb always_comb.v always_comb_tb.v 1663s + ./iverilog-always_comb 1663s + grep -v '\$finish called' 1663s + diff iverilog-always_comb.log yosys-always_comb.log 1663s 1663s /----------------------------------------------------------------------------\ 1663s | | 1663s | yosys -- Yosys Open SYnthesis Suite | 1663s | | 1663s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1663s | | 1663s | Permission to use, copy, modify, and/or distribute this software for any | 1663s | purpose with or without fee is hereby granted, provided that the above | 1663s | copyright notice and this permission notice appear in all copies. | 1663s | | 1663s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1663s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1663s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1663s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1663s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1663s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1663s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1663s | | 1663s \----------------------------------------------------------------------------/ 1663s 1663s Yosys 0.33 (git sha1 2584903a060) 1663s 1663s 1663s -- Running command `read_verilog always_full.v; prep; clean' -- 1663s 1663s 1. Executing Verilog-2005 frontend: always_full.v 1663s + ../../yosys -p 'read_verilog always_full.v; prep; clean' -o yosys-always_full-1.v 1663s Parsing Verilog input from `always_full.v' to AST representation. 1663s Generating RTLIL representation for module `\always_full'. 1663s Successfully finished Verilog frontend. 1663s 1663s 2. Executing PREP pass. 1663s 1663s 2.1. Executing HIERARCHY pass (managing design hierarchy). 1663s 1663s 2.2. Executing PROC pass (convert processes to netlists). 1663s 1663s 2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1663s Cleaned up 0 empty switches. 1663s 1663s 2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1663s Removed a total of 0 dead cases. 1663s 1663s 2.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1663s Removed 207 redundant assignments. 1663s Promoted 207 assignments to connections. 1663s 1663s 2.2.4. Executing PROC_INIT pass (extract init attributes). 1663s 1663s 2.2.5. Executing PROC_ARST pass (detect async resets in processes). 1663s 1663s 2.2.6. Executing PROC_ROM pass (convert switches to ROMs). 1663s Converted 0 switches. 1663s 1663s 2.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1663s Creating decoders for process `\always_full.$proc$always_full.v:3$1'. 1663s 1663s 2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1663s 1663s 2.2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1663s 1663s 2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1663s 1663s 2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1663s Removing empty process `always_full.$proc$always_full.v:3$1'. 1663s Cleaned up 0 empty switches. 1663s 1663s 2.2.12. Executing OPT_EXPR pass (perform const folding). 1663s Optimizing module always_full. 1663s 1663s 2.3. Executing OPT_EXPR pass (perform const folding). 1663s Optimizing module always_full. 1663s 1663s 2.4. Executing OPT_CLEAN pass (remove unused cells and wires). 1663s Finding unused cells or wires in module \always_full.. 1663s Removed 0 unused cells and 207 unused wires. 1663s 1663s 1663s 2.5. Executing CHECK pass (checking for obvious problems). 1663s Checking module always_full... 1663s Found and reported 0 problems. 1663s 1663s 2.6. Executing OPT pass (performing simple optimizations). 1663s 1663s 2.6.1. Executing OPT_EXPR pass (perform const folding). 1663s Optimizing module always_full. 1663s 1663s 2.6.2. Executing OPT_MERGE pass (detect identical cells). 1663s Finding identical cells in module `\always_full'. 1663s Removed a total of 0 cells. 1663s 1663s 2.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 1663s Running muxtree optimizer on module \always_full.. 1663s Creating internal representation of mux trees. 1663s No muxes found in this module. 1663s Removed 0 multiplexer ports. 1663s 1663s 2.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 1663s Optimizing cells in module \always_full. 1663s Performed a total of 0 changes. 1663s 1663s 2.6.5. Executing OPT_MERGE pass (detect identical cells). 1663s Finding identical cells in module `\always_full'. 1663s Removed a total of 0 cells. 1663s 1663s 2.6.6. Executing OPT_CLEAN pass (remove unused cells and wires). 1663s Finding unused cells or wires in module \always_full.. 1663s 1663s 2.6.7. Executing OPT_EXPR pass (perform const folding). 1663s Optimizing module always_full. 1663s 1663s 2.6.8. Finished OPT passes. (There is nothing left to do.) 1663s 1663s 2.7. Executing WREDUCE pass (reducing word size of cells). 1663s 1663s 2.8. Executing OPT_CLEAN pass (remove unused cells and wires). 1663s Finding unused cells or wires in module \always_full.. 1663s 1663s 2.9. Executing MEMORY_COLLECT pass (generating $mem cells). 1663s 1663s 2.10. Executing OPT pass (performing simple optimizations). 1663s 1663s 2.10.1. Executing OPT_EXPR pass (perform const folding). 1663s Optimizing module always_full. 1663s 1663s 2.10.2. Executing OPT_MERGE pass (detect identical cells). 1663s Finding identical cells in module `\always_full'. 1663s Removed a total of 0 cells. 1663s 1663s 2.10.3. Executing OPT_CLEAN pass (remove unused cells and wires). 1663s Finding unused cells or wires in module \always_full.. 1663s 1663s 2.10.4. Finished fast OPT passes. 1663s 1663s 2.11. Printing statistics. 1663s 1663s === always_full === 1663s 1663s Number of wires: 1 1663s Number of wire bits: 1 1663s Number of public wires: 1 1663s Number of public wire bits: 1 1663s Number of memories: 0 1663s Number of memory bits: 0 1663s Number of processes: 0 1663s Number of cells: 207 1663s $print 207 1663s 1663s 2.12. Executing CHECK pass (checking for obvious problems). 1663s Checking module always_full... 1663s Found and reported 0 problems. 1663s 1663s -- Writing to `yosys-always_full-1.v' using backend `verilog' -- 1663s 1663s 3. Executing Verilog backend. 1663s 1663s 3.1. Executing BMUXMAP pass. 1663s 1663s 3.2. Executing DEMUXMAP pass. 1663s Dumping module `\always_full'. 1663s 1663s End of script. Logfile hash: cfd5b76053, CPU: user 0.05s system 0.01s, MEM: 11.77 MB peak 1663s Yosys 0.33 (git sha1 2584903a060) 1663s Time spent: 19% 5x opt_expr (0 sec), 19% 4x opt_clean (0 sec), ... 1663s + iverilog -o iverilog-always_full-1 yosys-always_full-1.v always_full_tb.v 1663s + ./iverilog-always_full-1 1663s + grep -v '\$finish called' 1663s + diff iverilog-always_full.log iverilog-always_full-1.log 1663s + ../../yosys -p 'read_verilog display_lm.v' 1663s + ../../yosys -p 'read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc' 1663s 1663s /----------------------------------------------------------------------------\ 1663s | | 1663s | yosys -- Yosys Open SYnthesis Suite | 1663s | | 1663s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1663s | | 1663s | Permission to use, copy, modify, and/or distribute this software for any | 1663s | purpose with or without fee is hereby granted, provided that the above | 1663s | copyright notice and this permission notice appear in all copies. | 1663s | | 1663s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1663s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1663s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1663s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1663s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1663s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1663s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1663s | | 1663s \----------------------------------------------------------------------------/ 1663s 1663s Yosys 0.33 (git sha1 2584903a060) 1663s 1663s 1663s -- Running command `read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc' -- 1663s 1663s 1. Executing Verilog-2005 frontend: display_lm.v 1663s Parsing Verilog input from `display_lm.v' to AST representation. 1663s Generating RTLIL representation for module `\top'. 1663s Generating RTLIL representation for module `\mid'. 1663s Generating RTLIL representation for module `\bot'. 1663s %l: \bot 1663s %m: \bot 1663s Successfully finished Verilog frontend. 1663s 1663s 2. Executing CXXRTL backend. 1663s 1663s 2.1. Executing HIERARCHY pass (managing design hierarchy). 1663s 1663s 2.1.1. Finding top of design hierarchy.. 1663s root of 0 design levels: bot 1663s root of 1 design levels: mid 1663s root of 2 design levels: top 1663s Automatically selected top as design top module. 1663s 1663s 2.1.2. Analyzing design hierarchy.. 1663s Top module: \top 1663s Used module: \mid 1663s Used module: \bot 1663s 1663s 2.1.3. Analyzing design hierarchy.. 1663s Top module: \top 1663s Used module: \mid 1663s Used module: \bot 1663s Removed 0 unused modules. 1663s 1663s 2.2. Executing FLATTEN pass (flatten design). 1663s Deleting now unused module bot. 1663s Deleting now unused module mid. 1663s 1663s 1663s 2.3. Executing PROC pass (convert processes to netlists). 1663s 1663s 2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1663s Removing empty process `top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:0$3'. 1663s Cleaned up 0 empty switches. 1663s 1663s 2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1663s Removed a total of 0 dead cases. 1663s 1663s 2.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1663s Removed 1 redundant assignment. 1663s Promoted 1 assignment to connection. 1663s 1663s 2.3.4. Executing PROC_INIT pass (extract init attributes). 1663s 1663s 2.3.5. Executing PROC_ARST pass (detect async resets in processes). 1663s 1663s 2.3.6. Executing PROC_ROM pass (convert switches to ROMs). 1663s Converted 0 switches. 1663s 1663s 2.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1663s Creating decoders for process `\top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:11$1'. 1663s 1663s 2.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1663s 1663s 2.3.9. Executing PROC_DFF pass (convert process syncs to FFs). 1663s 1663s 2.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1663s 1663s 2.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1663s Removing empty process `top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:11$1'. 1663s Cleaned up 0 empty switches. 1663s 1663s 2.3.12. Executing OPT_EXPR pass (perform const folding). 1663s Optimizing module top. 1663s 1663s 1663s 1663s End of script. Logfile hash: 1b689717a7, CPU: user 0.01s system 0.00s, MEM: 10.36 MB peak 1663s Yosys 0.33 (git sha1 2584903a060) 1663s Time spent: 33% 1x opt_expr (0 sec), 13% 2x read_verilog (0 sec), ... 1663s + gcc -std=c++11 -o yosys-display_lm_cc -I../.. display_lm_tb.cc -lstdc++ 1664s + ./yosys-display_lm_cc 1664s + for log in yosys-display_lm.log yosys-display_lm_cc.log 1664s + grep '^%l: \\bot$' yosys-display_lm.log 1664s %l: \bot 1664s + grep '^%m: \\bot$' yosys-display_lm.log 1664s + for log in yosys-display_lm.log yosys-display_lm_cc.log 1664s + grep '^%l: \\bot$' yosys-display_lm_cc.log 1664s + grep '^%m: \\bot$' yosys-display_lm_cc.log 1664s %m: \bot 1664s %l: \bot 1664s %m: \bot 1664s 1664s Passed "make test". 1664s 1664s autopkgtest [00:22:27]: test yosys-testsuite: -----------------------] 1665s yosys-testsuite PASS 1665s autopkgtest [00:22:28]: test yosys-testsuite: - - - - - - - - - - results - - - - - - - - - - 1665s autopkgtest [00:22:28]: test ice: preparing testbed 1728s autopkgtest [00:23:31]: testbed dpkg architecture: amd64 1729s autopkgtest [00:23:32]: testbed apt version: 2.9.31ubuntu1 1729s autopkgtest [00:23:32]: @@@@@@@@@@@@@@@@@@@@ test bed setup 1729s autopkgtest [00:23:32]: testbed release detected to be: plucky 1730s autopkgtest [00:23:33]: updating testbed package index (apt update) 1730s Get:1 http://ftpmaster.internal/ubuntu plucky-proposed InRelease [126 kB] 1731s Hit:2 http://ftpmaster.internal/ubuntu plucky InRelease 1731s Hit:3 http://ftpmaster.internal/ubuntu plucky-updates InRelease 1731s Hit:4 http://ftpmaster.internal/ubuntu plucky-security InRelease 1731s Get:5 http://ftpmaster.internal/ubuntu plucky-proposed/multiverse Sources [17.7 kB] 1731s Get:6 http://ftpmaster.internal/ubuntu plucky-proposed/universe Sources [365 kB] 1731s Get:7 http://ftpmaster.internal/ubuntu plucky-proposed/main Sources [41.4 kB] 1731s Get:8 http://ftpmaster.internal/ubuntu plucky-proposed/main amd64 Packages [84.0 kB] 1731s Get:9 http://ftpmaster.internal/ubuntu plucky-proposed/main i386 Packages [66.6 kB] 1731s Get:10 http://ftpmaster.internal/ubuntu plucky-proposed/main amd64 c-n-f Metadata [1844 B] 1731s Get:11 http://ftpmaster.internal/ubuntu plucky-proposed/restricted amd64 c-n-f Metadata [116 B] 1731s Get:12 http://ftpmaster.internal/ubuntu plucky-proposed/universe amd64 Packages [338 kB] 1731s Get:13 http://ftpmaster.internal/ubuntu plucky-proposed/universe i386 Packages [168 kB] 1731s Get:14 http://ftpmaster.internal/ubuntu plucky-proposed/universe amd64 c-n-f Metadata [14.9 kB] 1731s Get:15 http://ftpmaster.internal/ubuntu plucky-proposed/multiverse i386 Packages [9324 B] 1731s Get:16 http://ftpmaster.internal/ubuntu plucky-proposed/multiverse amd64 Packages [18.0 kB] 1731s Get:17 http://ftpmaster.internal/ubuntu plucky-proposed/multiverse amd64 c-n-f Metadata [628 B] 1731s Fetched 1252 kB in 1s (1412 kB/s) 1732s Reading package lists... 1733s Reading package lists... 1733s Building dependency tree... 1733s Reading state information... 1733s Calculating upgrade... 1733s Calculating upgrade... 1734s The following package was automatically installed and is no longer required: 1734s libnl-genl-3-200 1734s Use 'sudo apt autoremove' to remove it. 1734s The following NEW packages will be installed: 1734s bpftool libdebuginfod-common libdebuginfod1t64 linux-headers-6.14.0-10 1734s linux-headers-6.14.0-10-generic linux-image-6.14.0-10-generic 1734s linux-modules-6.14.0-10-generic linux-modules-extra-6.14.0-10-generic 1734s linux-perf linux-tools-6.14.0-10 linux-tools-6.14.0-10-generic pnp.ids 1734s The following packages will be upgraded: 1734s apparmor apt apt-utils binutils binutils-common binutils-x86-64-linux-gnu 1734s cloud-init cloud-init-base curl dosfstools exfatprogs fwupd gcc-15-base 1734s gir1.2-girepository-2.0 gir1.2-glib-2.0 htop hwdata initramfs-tools 1734s initramfs-tools-bin initramfs-tools-core libapparmor1 libapt-pkg7.0 1734s libassuan9 libatomic1 libaudit-common libaudit1 libbinutils libbrotli1 1734s libc-bin libc-dev-bin libc6 libc6-dev libcap-ng0 libctf-nobfd0 libctf0 1734s libcurl3t64-gnutls libcurl4t64 libestr0 libftdi1-2 libfwupd3 libgcc-s1 1734s libgirepository-1.0-1 libglib2.0-0t64 libglib2.0-data libgpgme11t64 1734s libgprofng0 libjemalloc2 liblz4-1 liblzma5 libmm-glib0 libncurses6 1734s libncursesw6 libnewt0.52 libnl-3-200 libnl-genl-3-200 libnl-route-3-200 1734s libnss-systemd libpam-systemd libparted2t64 libpci3 libpython3-stdlib 1734s libpython3.13 libpython3.13-minimal libpython3.13-stdlib libseccomp2 1734s libselinux1 libsemanage-common libsemanage2 libsframe1 libsqlite3-0 1734s libstdc++6 libsystemd-shared libsystemd0 libtinfo6 libudev1 libxml2 1734s linux-firmware linux-generic linux-headers-generic linux-headers-virtual 1734s linux-image-generic linux-image-virtual linux-libc-dev linux-tools-common 1734s linux-virtual locales media-types ncurses-base ncurses-bin ncurses-term 1734s parted pci.ids pciutils pinentry-curses python-apt-common python3 1734s python3-apt python3-bcrypt python3-cffi-backend python3-dbus python3-gi 1734s python3-jinja2 python3-lazr.uri python3-markupsafe python3-minimal 1734s python3-newt python3-rpds-py python3-systemd python3-yaml python3.13 1734s python3.13-gdbm python3.13-minimal rsync rsyslog strace systemd 1734s systemd-cryptsetup systemd-resolved systemd-sysv systemd-timesyncd 1734s ubuntu-kernel-accessories ubuntu-minimal ubuntu-standard udev whiptail 1734s xz-utils 1734s 126 upgraded, 12 newly installed, 0 to remove and 0 not upgraded. 1734s Need to get 829 MB of archives. 1734s After this operation, 325 MB of additional disk space will be used. 1734s Get:1 http://ftpmaster.internal/ubuntu plucky/main amd64 ncurses-bin amd64 6.5+20250216-2 [194 kB] 1734s Get:2 http://ftpmaster.internal/ubuntu plucky/main amd64 libc-dev-bin amd64 2.41-1ubuntu1 [24.7 kB] 1734s Get:3 http://ftpmaster.internal/ubuntu plucky/main amd64 libc6-dev amd64 2.41-1ubuntu1 [2182 kB] 1734s Get:4 http://ftpmaster.internal/ubuntu plucky/main amd64 locales all 2.41-1ubuntu1 [4246 kB] 1734s Get:5 http://ftpmaster.internal/ubuntu plucky/main amd64 libc6 amd64 2.41-1ubuntu1 [3327 kB] 1735s Get:6 http://ftpmaster.internal/ubuntu plucky/main amd64 libc-bin amd64 2.41-1ubuntu1 [701 kB] 1735s Get:7 http://ftpmaster.internal/ubuntu plucky/main amd64 linux-libc-dev amd64 6.14.0-10.10 [1723 kB] 1735s Get:8 http://ftpmaster.internal/ubuntu plucky/main amd64 libatomic1 amd64 15-20250222-0ubuntu1 [10.4 kB] 1735s Get:9 http://ftpmaster.internal/ubuntu plucky/main amd64 gcc-15-base amd64 15-20250222-0ubuntu1 [53.4 kB] 1735s Get:10 http://ftpmaster.internal/ubuntu plucky/main amd64 libgcc-s1 amd64 15-20250222-0ubuntu1 [77.8 kB] 1735s Get:11 http://ftpmaster.internal/ubuntu plucky/main amd64 libstdc++6 amd64 15-20250222-0ubuntu1 [798 kB] 1735s Get:12 http://ftpmaster.internal/ubuntu plucky/main amd64 ncurses-base all 6.5+20250216-2 [25.9 kB] 1735s Get:13 http://ftpmaster.internal/ubuntu plucky/main amd64 ncurses-term all 6.5+20250216-2 [276 kB] 1735s Get:14 http://ftpmaster.internal/ubuntu plucky/main amd64 liblz4-1 amd64 1.10.0-4 [66.4 kB] 1735s Get:15 http://ftpmaster.internal/ubuntu plucky/main amd64 liblzma5 amd64 5.6.4-1 [157 kB] 1735s Get:16 http://ftpmaster.internal/ubuntu plucky/main amd64 libsystemd0 amd64 257.3-1ubuntu3 [595 kB] 1735s Get:17 http://ftpmaster.internal/ubuntu plucky/main amd64 libnss-systemd amd64 257.3-1ubuntu3 [199 kB] 1735s Get:18 http://ftpmaster.internal/ubuntu plucky/main amd64 systemd-sysv amd64 257.3-1ubuntu3 [11.9 kB] 1735s Get:19 http://ftpmaster.internal/ubuntu plucky/main amd64 systemd-resolved amd64 257.3-1ubuntu3 [345 kB] 1735s Get:20 http://ftpmaster.internal/ubuntu plucky/main amd64 libpam-systemd amd64 257.3-1ubuntu3 [302 kB] 1735s Get:21 http://ftpmaster.internal/ubuntu plucky/main amd64 libsystemd-shared amd64 257.3-1ubuntu3 [2371 kB] 1735s Get:22 http://ftpmaster.internal/ubuntu plucky/main amd64 systemd amd64 257.3-1ubuntu3 [3052 kB] 1735s Get:23 http://ftpmaster.internal/ubuntu plucky/main amd64 systemd-timesyncd amd64 257.3-1ubuntu3 [42.1 kB] 1735s Get:24 http://ftpmaster.internal/ubuntu plucky/main amd64 systemd-cryptsetup amd64 257.3-1ubuntu3 [124 kB] 1735s Get:25 http://ftpmaster.internal/ubuntu plucky/main amd64 udev amd64 257.3-1ubuntu3 [1404 kB] 1735s Get:26 http://ftpmaster.internal/ubuntu plucky/main amd64 libudev1 amd64 257.3-1ubuntu3 [215 kB] 1735s Get:27 http://ftpmaster.internal/ubuntu plucky/main amd64 libaudit-common all 1:4.0.2-2ubuntu2 [6628 B] 1735s Get:28 http://ftpmaster.internal/ubuntu plucky/main amd64 libcap-ng0 amd64 0.8.5-4build1 [15.6 kB] 1735s Get:29 http://ftpmaster.internal/ubuntu plucky/main amd64 libaudit1 amd64 1:4.0.2-2ubuntu2 [54.0 kB] 1735s Get:30 http://ftpmaster.internal/ubuntu plucky/main amd64 libseccomp2 amd64 2.5.5-1ubuntu6 [53.5 kB] 1735s Get:31 http://ftpmaster.internal/ubuntu plucky/main amd64 libselinux1 amd64 3.7-3ubuntu3 [87.3 kB] 1735s Get:32 http://ftpmaster.internal/ubuntu plucky/main amd64 libapparmor1 amd64 4.1.0~beta5-0ubuntu8 [55.0 kB] 1735s Get:33 http://ftpmaster.internal/ubuntu plucky/main amd64 libapt-pkg7.0 amd64 2.9.33 [1138 kB] 1735s Get:34 http://ftpmaster.internal/ubuntu plucky/main amd64 apt amd64 2.9.33 [1439 kB] 1735s Get:35 http://ftpmaster.internal/ubuntu plucky/main amd64 apt-utils amd64 2.9.33 [222 kB] 1735s Get:36 http://ftpmaster.internal/ubuntu plucky/main amd64 python3-minimal amd64 3.13.2-2 [27.7 kB] 1735s Get:37 http://ftpmaster.internal/ubuntu plucky/main amd64 python3 amd64 3.13.2-2 [24.0 kB] 1735s Get:38 http://ftpmaster.internal/ubuntu plucky/main amd64 libpython3.13 amd64 3.13.2-2 [2341 kB] 1735s Get:39 http://ftpmaster.internal/ubuntu plucky/main amd64 media-types all 13.0.0 [29.9 kB] 1735s Get:40 http://ftpmaster.internal/ubuntu plucky/main amd64 libncurses6 amd64 6.5+20250216-2 [126 kB] 1735s Get:41 http://ftpmaster.internal/ubuntu plucky/main amd64 libncursesw6 amd64 6.5+20250216-2 [165 kB] 1735s Get:42 http://ftpmaster.internal/ubuntu plucky/main amd64 libtinfo6 amd64 6.5+20250216-2 [119 kB] 1735s Get:43 http://ftpmaster.internal/ubuntu plucky/main amd64 libsqlite3-0 amd64 3.46.1-2 [715 kB] 1735s Get:44 http://ftpmaster.internal/ubuntu plucky/main amd64 python3.13 amd64 3.13.2-2 [735 kB] 1735s Get:45 http://ftpmaster.internal/ubuntu plucky/main amd64 python3.13-minimal amd64 3.13.2-2 [2365 kB] 1735s Get:46 http://ftpmaster.internal/ubuntu plucky/main amd64 libpython3.13-minimal amd64 3.13.2-2 [883 kB] 1735s Get:47 http://ftpmaster.internal/ubuntu plucky/main amd64 libpython3.13-stdlib amd64 3.13.2-2 [2066 kB] 1735s Get:48 http://ftpmaster.internal/ubuntu plucky/main amd64 libpython3-stdlib amd64 3.13.2-2 [10.4 kB] 1735s Get:49 http://ftpmaster.internal/ubuntu plucky/main amd64 rsync amd64 3.4.1+ds1-3 [482 kB] 1736s Get:50 http://ftpmaster.internal/ubuntu plucky/main amd64 libdebuginfod-common all 0.192-4 [15.4 kB] 1736s Get:51 http://ftpmaster.internal/ubuntu plucky/main amd64 libsemanage-common all 3.7-2.1build1 [7268 B] 1736s Get:52 http://ftpmaster.internal/ubuntu plucky/main amd64 libsemanage2 amd64 3.7-2.1build1 [106 kB] 1736s Get:53 http://ftpmaster.internal/ubuntu plucky/main amd64 libassuan9 amd64 3.0.2-2 [43.1 kB] 1736s Get:54 http://ftpmaster.internal/ubuntu plucky/main amd64 gir1.2-girepository-2.0 amd64 1.83.4-1 [25.3 kB] 1736s Get:55 http://ftpmaster.internal/ubuntu plucky/main amd64 gir1.2-glib-2.0 amd64 2.84.0-1 [184 kB] 1736s Get:56 http://ftpmaster.internal/ubuntu plucky/main amd64 libglib2.0-0t64 amd64 2.84.0-1 [1669 kB] 1736s Get:57 http://ftpmaster.internal/ubuntu plucky/main amd64 libgirepository-1.0-1 amd64 1.83.4-1 [89.5 kB] 1736s Get:58 http://ftpmaster.internal/ubuntu plucky/main amd64 libestr0 amd64 0.1.11-2 [8340 B] 1736s Get:59 http://ftpmaster.internal/ubuntu plucky/main amd64 libglib2.0-data all 2.84.0-1 [53.0 kB] 1736s Get:60 http://ftpmaster.internal/ubuntu plucky/main amd64 python3-newt amd64 0.52.24-4ubuntu2 [21.1 kB] 1736s Get:61 http://ftpmaster.internal/ubuntu plucky/main amd64 libnewt0.52 amd64 0.52.24-4ubuntu2 [55.7 kB] 1736s Get:62 http://ftpmaster.internal/ubuntu plucky/main amd64 libxml2 amd64 2.12.7+dfsg+really2.9.14-0.2ubuntu5 [772 kB] 1736s Get:63 http://ftpmaster.internal/ubuntu plucky/main amd64 python-apt-common all 2.9.9build1 [21.3 kB] 1736s Get:64 http://ftpmaster.internal/ubuntu plucky/main amd64 python3-apt amd64 2.9.9build1 [172 kB] 1736s Get:65 http://ftpmaster.internal/ubuntu plucky/main amd64 python3-cffi-backend amd64 1.17.1-2build2 [96.6 kB] 1736s Get:66 http://ftpmaster.internal/ubuntu plucky/main amd64 python3-dbus amd64 1.3.2-5build5 [102 kB] 1736s Get:67 http://ftpmaster.internal/ubuntu plucky/main amd64 python3-gi amd64 3.50.0-4build1 [252 kB] 1736s Get:68 http://ftpmaster.internal/ubuntu plucky/main amd64 python3-yaml amd64 6.0.2-1build2 [144 kB] 1736s Get:69 http://ftpmaster.internal/ubuntu plucky/main amd64 rsyslog amd64 8.2412.0-2ubuntu2 [555 kB] 1736s Get:70 http://ftpmaster.internal/ubuntu plucky/main amd64 whiptail amd64 0.52.24-4ubuntu2 [19.1 kB] 1736s Get:71 http://ftpmaster.internal/ubuntu plucky/main amd64 ubuntu-minimal amd64 1.549 [11.5 kB] 1736s Get:72 http://ftpmaster.internal/ubuntu plucky/main amd64 apparmor amd64 4.1.0~beta5-0ubuntu8 [701 kB] 1736s Get:73 http://ftpmaster.internal/ubuntu plucky/main amd64 dosfstools amd64 4.2-1.2 [95.0 kB] 1736s Get:74 http://ftpmaster.internal/ubuntu plucky/main amd64 libnl-genl-3-200 amd64 3.7.0-1 [12.2 kB] 1736s Get:75 http://ftpmaster.internal/ubuntu plucky/main amd64 libnl-route-3-200 amd64 3.7.0-1 [191 kB] 1736s Get:76 http://ftpmaster.internal/ubuntu plucky/main amd64 libnl-3-200 amd64 3.7.0-1 [64.9 kB] 1736s Get:77 http://ftpmaster.internal/ubuntu plucky/main amd64 parted amd64 3.6-5 [53.9 kB] 1736s Get:78 http://ftpmaster.internal/ubuntu plucky/main amd64 libparted2t64 amd64 3.6-5 [158 kB] 1736s Get:79 http://ftpmaster.internal/ubuntu plucky/main amd64 pci.ids all 0.0~2025.03.09-1 [285 kB] 1736s Get:80 http://ftpmaster.internal/ubuntu plucky/main amd64 pciutils amd64 1:3.13.0-2 [110 kB] 1736s Get:81 http://ftpmaster.internal/ubuntu plucky/main amd64 libpci3 amd64 1:3.13.0-2 [39.8 kB] 1736s Get:82 http://ftpmaster.internal/ubuntu plucky/main amd64 strace amd64 6.13+ds-1ubuntu1 [622 kB] 1736s Get:83 http://ftpmaster.internal/ubuntu plucky/main amd64 xz-utils amd64 5.6.4-1 [278 kB] 1736s Get:84 http://ftpmaster.internal/ubuntu plucky/main amd64 ubuntu-standard amd64 1.549 [11.5 kB] 1736s Get:85 http://ftpmaster.internal/ubuntu plucky/main amd64 libgprofng0 amd64 2.44-3ubuntu1 [886 kB] 1736s Get:86 http://ftpmaster.internal/ubuntu plucky/main amd64 libctf0 amd64 2.44-3ubuntu1 [96.5 kB] 1736s Get:87 http://ftpmaster.internal/ubuntu plucky/main amd64 libctf-nobfd0 amd64 2.44-3ubuntu1 [98.9 kB] 1736s Get:88 http://ftpmaster.internal/ubuntu plucky/main amd64 binutils-x86-64-linux-gnu amd64 2.44-3ubuntu1 [1108 kB] 1736s Get:89 http://ftpmaster.internal/ubuntu plucky/main amd64 libbinutils amd64 2.44-3ubuntu1 [585 kB] 1736s Get:90 http://ftpmaster.internal/ubuntu plucky/main amd64 binutils amd64 2.44-3ubuntu1 [208 kB] 1736s Get:91 http://ftpmaster.internal/ubuntu plucky/main amd64 binutils-common amd64 2.44-3ubuntu1 [215 kB] 1736s Get:92 http://ftpmaster.internal/ubuntu plucky/main amd64 libsframe1 amd64 2.44-3ubuntu1 [14.8 kB] 1736s Get:93 http://ftpmaster.internal/ubuntu plucky/main amd64 hwdata all 0.393-3 [1562 B] 1736s Get:94 http://ftpmaster.internal/ubuntu plucky/main amd64 pnp.ids all 0.393-3 [29.5 kB] 1736s Get:95 http://ftpmaster.internal/ubuntu plucky/main amd64 linux-tools-common all 6.14.0-10.10 [295 kB] 1736s Get:96 http://ftpmaster.internal/ubuntu plucky/main amd64 bpftool amd64 7.6.0+6.14.0-10.10 [1147 kB] 1736s Get:97 http://ftpmaster.internal/ubuntu plucky/main amd64 python3-markupsafe amd64 2.1.5-1build4 [13.4 kB] 1736s Get:98 http://ftpmaster.internal/ubuntu plucky/main amd64 python3-jinja2 all 3.1.5-2ubuntu1 [109 kB] 1736s Get:99 http://ftpmaster.internal/ubuntu plucky/main amd64 cloud-init-base all 25.1-0ubuntu3 [616 kB] 1736s Get:100 http://ftpmaster.internal/ubuntu plucky/main amd64 libbrotli1 amd64 1.1.0-2build4 [365 kB] 1736s Get:101 http://ftpmaster.internal/ubuntu plucky/main amd64 curl amd64 8.12.1-3ubuntu1 [258 kB] 1736s Get:102 http://ftpmaster.internal/ubuntu plucky/main amd64 libcurl4t64 amd64 8.12.1-3ubuntu1 [437 kB] 1737s Get:103 http://ftpmaster.internal/ubuntu plucky/main amd64 exfatprogs amd64 1.2.8-1 [76.3 kB] 1737s Get:104 http://ftpmaster.internal/ubuntu plucky/main amd64 libcurl3t64-gnutls amd64 8.12.1-3ubuntu1 [432 kB] 1737s Get:105 http://ftpmaster.internal/ubuntu plucky/main amd64 fwupd amd64 2.0.6-4 [5408 kB] 1737s Get:106 http://ftpmaster.internal/ubuntu plucky/main amd64 libfwupd3 amd64 2.0.6-4 [136 kB] 1737s Get:107 http://ftpmaster.internal/ubuntu plucky/main amd64 libmm-glib0 amd64 1.23.4-0ubuntu3 [251 kB] 1737s Get:108 http://ftpmaster.internal/ubuntu plucky/main amd64 htop amd64 3.4.0-2 [195 kB] 1737s Get:109 http://ftpmaster.internal/ubuntu plucky/main amd64 linux-firmware amd64 20250310.git9e1370d3-0ubuntu1 [571 MB] 1755s Get:110 http://ftpmaster.internal/ubuntu plucky/main amd64 initramfs-tools all 0.146ubuntu1 [7920 B] 1755s Get:111 http://ftpmaster.internal/ubuntu plucky/main amd64 initramfs-tools-core all 0.146ubuntu1 [51.9 kB] 1755s Get:112 http://ftpmaster.internal/ubuntu plucky/main amd64 initramfs-tools-bin amd64 0.146ubuntu1 [26.2 kB] 1755s Get:113 http://ftpmaster.internal/ubuntu plucky/main amd64 libdebuginfod1t64 amd64 0.192-4 [21.0 kB] 1755s Get:114 http://ftpmaster.internal/ubuntu plucky/main amd64 libftdi1-2 amd64 1.5-8build1 [30.2 kB] 1755s Get:115 http://ftpmaster.internal/ubuntu plucky/main amd64 libgpgme11t64 amd64 1.24.2-1ubuntu2 [155 kB] 1755s Get:116 http://ftpmaster.internal/ubuntu plucky/main amd64 libjemalloc2 amd64 5.3.0-3 [277 kB] 1755s Get:117 http://ftpmaster.internal/ubuntu plucky/main amd64 linux-modules-6.14.0-10-generic amd64 6.14.0-10.10 [41.2 MB] 1757s Get:118 http://ftpmaster.internal/ubuntu plucky/main amd64 linux-image-6.14.0-10-generic amd64 6.14.0-10.10 [15.3 MB] 1758s Get:119 http://ftpmaster.internal/ubuntu plucky/main amd64 linux-modules-extra-6.14.0-10-generic amd64 6.14.0-10.10 [120 MB] 1763s Get:120 http://ftpmaster.internal/ubuntu plucky/main amd64 linux-generic amd64 6.14.0-10.10 [1730 B] 1763s Get:121 http://ftpmaster.internal/ubuntu plucky/main amd64 linux-image-generic amd64 6.14.0-10.10 [11.1 kB] 1763s Get:122 http://ftpmaster.internal/ubuntu plucky/main amd64 linux-virtual amd64 6.14.0-10.10 [1722 B] 1763s Get:123 http://ftpmaster.internal/ubuntu plucky/main amd64 linux-image-virtual amd64 6.14.0-10.10 [11.1 kB] 1763s Get:124 http://ftpmaster.internal/ubuntu plucky/main amd64 linux-headers-virtual amd64 6.14.0-10.10 [1642 B] 1763s Get:125 http://ftpmaster.internal/ubuntu plucky/main amd64 linux-headers-6.14.0-10 all 6.14.0-10.10 [14.2 MB] 1764s Get:126 http://ftpmaster.internal/ubuntu plucky/main amd64 linux-headers-6.14.0-10-generic amd64 6.14.0-10.10 [3915 kB] 1764s Get:127 http://ftpmaster.internal/ubuntu plucky/main amd64 linux-headers-generic amd64 6.14.0-10.10 [11.0 kB] 1764s Get:128 http://ftpmaster.internal/ubuntu plucky/main amd64 linux-perf amd64 6.14.0-10.10 [4122 kB] 1764s Get:129 http://ftpmaster.internal/ubuntu plucky/main amd64 linux-tools-6.14.0-10 amd64 6.14.0-10.10 [1394 kB] 1764s Get:130 http://ftpmaster.internal/ubuntu plucky/main amd64 linux-tools-6.14.0-10-generic amd64 6.14.0-10.10 [830 B] 1764s Get:131 http://ftpmaster.internal/ubuntu plucky/main amd64 pinentry-curses amd64 1.3.1-2ubuntu3 [42.3 kB] 1764s Get:132 http://ftpmaster.internal/ubuntu plucky/main amd64 python3-lazr.uri all 1.0.6-6 [13.7 kB] 1764s Get:133 http://ftpmaster.internal/ubuntu plucky/main amd64 python3-rpds-py amd64 0.21.0-2ubuntu2 [278 kB] 1764s Get:134 http://ftpmaster.internal/ubuntu plucky/main amd64 python3-systemd amd64 235-1build6 [43.9 kB] 1764s Get:135 http://ftpmaster.internal/ubuntu plucky/main amd64 python3.13-gdbm amd64 3.13.2-2 [31.9 kB] 1764s Get:136 http://ftpmaster.internal/ubuntu plucky/main amd64 ubuntu-kernel-accessories amd64 1.549 [11.2 kB] 1764s Get:137 http://ftpmaster.internal/ubuntu plucky/main amd64 cloud-init all 25.1-0ubuntu3 [2100 B] 1764s Get:138 http://ftpmaster.internal/ubuntu plucky/main amd64 python3-bcrypt amd64 4.2.0-2.1build1 [221 kB] 1765s Preconfiguring packages ... 1765s Fetched 829 MB in 30s (27.3 MB/s) 1765s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 109140 files and directories currently installed.) 1765s Preparing to unpack .../ncurses-bin_6.5+20250216-2_amd64.deb ... 1765s Unpacking ncurses-bin (6.5+20250216-2) over (6.5+20250216-1) ... 1765s Setting up ncurses-bin (6.5+20250216-2) ... 1765s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 109140 files and directories currently installed.) 1765s Preparing to unpack .../libc-dev-bin_2.41-1ubuntu1_amd64.deb ... 1765s Unpacking libc-dev-bin (2.41-1ubuntu1) over (2.40-4ubuntu1) ... 1765s Preparing to unpack .../libc6-dev_2.41-1ubuntu1_amd64.deb ... 1765s Unpacking libc6-dev:amd64 (2.41-1ubuntu1) over (2.40-4ubuntu1) ... 1765s Preparing to unpack .../locales_2.41-1ubuntu1_all.deb ... 1765s Unpacking locales (2.41-1ubuntu1) over (2.40-4ubuntu1) ... 1766s Preparing to unpack .../libc6_2.41-1ubuntu1_amd64.deb ... 1766s Checking for services that may need to be restarted... 1766s Checking init scripts... 1766s Checking for services that may need to be restarted... 1766s Checking init scripts... 1766s Stopping some services possibly affected by the upgrade (will be restarted later): 1766s cron: stopping...done. 1766s 1766s Unpacking libc6:amd64 (2.41-1ubuntu1) over (2.40-4ubuntu1) ... 1766s Setting up libc6:amd64 (2.41-1ubuntu1) ... 1766s Checking for services that may need to be restarted... 1766s Checking init scripts... 1766s Restarting services possibly affected by the upgrade: 1766s cron: restarting...done. 1766s 1766s Services restarted successfully. 1766s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 109141 files and directories currently installed.) 1766s Preparing to unpack .../libc-bin_2.41-1ubuntu1_amd64.deb ... 1766s Unpacking libc-bin (2.41-1ubuntu1) over (2.40-4ubuntu1) ... 1766s Setting up libc-bin (2.41-1ubuntu1) ... 1766s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 109141 files and directories currently installed.) 1766s Preparing to unpack .../linux-libc-dev_6.14.0-10.10_amd64.deb ... 1766s Unpacking linux-libc-dev:amd64 (6.14.0-10.10) over (6.12.0-16.16) ... 1767s Preparing to unpack .../libatomic1_15-20250222-0ubuntu1_amd64.deb ... 1767s Unpacking libatomic1:amd64 (15-20250222-0ubuntu1) over (15-20250213-1ubuntu1) ... 1767s Preparing to unpack .../gcc-15-base_15-20250222-0ubuntu1_amd64.deb ... 1767s Unpacking gcc-15-base:amd64 (15-20250222-0ubuntu1) over (15-20250213-1ubuntu1) ... 1767s Setting up gcc-15-base:amd64 (15-20250222-0ubuntu1) ... 1767s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 109146 files and directories currently installed.) 1767s Preparing to unpack .../libgcc-s1_15-20250222-0ubuntu1_amd64.deb ... 1767s Unpacking libgcc-s1:amd64 (15-20250222-0ubuntu1) over (15-20250213-1ubuntu1) ... 1767s Setting up libgcc-s1:amd64 (15-20250222-0ubuntu1) ... 1767s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 109146 files and directories currently installed.) 1767s Preparing to unpack .../libstdc++6_15-20250222-0ubuntu1_amd64.deb ... 1767s Unpacking libstdc++6:amd64 (15-20250222-0ubuntu1) over (15-20250213-1ubuntu1) ... 1767s Setting up libstdc++6:amd64 (15-20250222-0ubuntu1) ... 1767s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 109146 files and directories currently installed.) 1767s Preparing to unpack .../ncurses-base_6.5+20250216-2_all.deb ... 1767s Unpacking ncurses-base (6.5+20250216-2) over (6.5+20250216-1) ... 1767s Setting up ncurses-base (6.5+20250216-2) ... 1767s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 109146 files and directories currently installed.) 1767s Preparing to unpack .../ncurses-term_6.5+20250216-2_all.deb ... 1767s Unpacking ncurses-term (6.5+20250216-2) over (6.5+20250216-1) ... 1768s Preparing to unpack .../liblz4-1_1.10.0-4_amd64.deb ... 1768s Unpacking liblz4-1:amd64 (1.10.0-4) over (1.10.0-3) ... 1768s Setting up liblz4-1:amd64 (1.10.0-4) ... 1768s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 109146 files and directories currently installed.) 1768s Preparing to unpack .../liblzma5_5.6.4-1_amd64.deb ... 1768s Unpacking liblzma5:amd64 (5.6.4-1) over (5.6.3-1) ... 1768s Setting up liblzma5:amd64 (5.6.4-1) ... 1768s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 109146 files and directories currently installed.) 1768s Preparing to unpack .../libsystemd0_257.3-1ubuntu3_amd64.deb ... 1768s Unpacking libsystemd0:amd64 (257.3-1ubuntu3) over (257.2-3ubuntu1) ... 1768s Setting up libsystemd0:amd64 (257.3-1ubuntu3) ... 1768s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 109146 files and directories currently installed.) 1768s Preparing to unpack .../libnss-systemd_257.3-1ubuntu3_amd64.deb ... 1768s Unpacking libnss-systemd:amd64 (257.3-1ubuntu3) over (257.2-3ubuntu1) ... 1768s Preparing to unpack .../systemd-sysv_257.3-1ubuntu3_amd64.deb ... 1768s Unpacking systemd-sysv (257.3-1ubuntu3) over (257.2-3ubuntu1) ... 1768s Preparing to unpack .../systemd-resolved_257.3-1ubuntu3_amd64.deb ... 1768s Unpacking systemd-resolved (257.3-1ubuntu3) over (257.2-3ubuntu1) ... 1768s Preparing to unpack .../libpam-systemd_257.3-1ubuntu3_amd64.deb ... 1768s Unpacking libpam-systemd:amd64 (257.3-1ubuntu3) over (257.2-3ubuntu1) ... 1768s Preparing to unpack .../libsystemd-shared_257.3-1ubuntu3_amd64.deb ... 1768s Unpacking libsystemd-shared:amd64 (257.3-1ubuntu3) over (257.2-3ubuntu1) ... 1768s Setting up libsystemd-shared:amd64 (257.3-1ubuntu3) ... 1768s (Reading database ... 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(6.13+ds-1ubuntu1) over (6.11-0ubuntu1) ... 1774s Preparing to unpack .../29-xz-utils_5.6.4-1_amd64.deb ... 1774s Unpacking xz-utils (5.6.4-1) over (5.6.3-1) ... 1774s Preparing to unpack .../30-ubuntu-standard_1.549_amd64.deb ... 1774s Unpacking ubuntu-standard (1.549) over (1.548) ... 1774s Preparing to unpack .../31-libgprofng0_2.44-3ubuntu1_amd64.deb ... 1774s Unpacking libgprofng0:amd64 (2.44-3ubuntu1) over (2.44-2ubuntu1) ... 1774s Preparing to unpack .../32-libctf0_2.44-3ubuntu1_amd64.deb ... 1774s Unpacking libctf0:amd64 (2.44-3ubuntu1) over (2.44-2ubuntu1) ... 1774s Preparing to unpack .../33-libctf-nobfd0_2.44-3ubuntu1_amd64.deb ... 1774s Unpacking libctf-nobfd0:amd64 (2.44-3ubuntu1) over (2.44-2ubuntu1) ... 1774s Preparing to unpack .../34-binutils-x86-64-linux-gnu_2.44-3ubuntu1_amd64.deb ... 1774s Unpacking binutils-x86-64-linux-gnu (2.44-3ubuntu1) over (2.44-2ubuntu1) ... 1774s Preparing to unpack .../35-libbinutils_2.44-3ubuntu1_amd64.deb ... 1774s Unpacking libbinutils:amd64 (2.44-3ubuntu1) over (2.44-2ubuntu1) ... 1774s Preparing to unpack .../36-binutils_2.44-3ubuntu1_amd64.deb ... 1774s Unpacking binutils (2.44-3ubuntu1) over (2.44-2ubuntu1) ... 1774s Preparing to unpack .../37-binutils-common_2.44-3ubuntu1_amd64.deb ... 1774s Unpacking binutils-common:amd64 (2.44-3ubuntu1) over (2.44-2ubuntu1) ... 1774s Preparing to unpack .../38-libsframe1_2.44-3ubuntu1_amd64.deb ... 1774s Unpacking libsframe1:amd64 (2.44-3ubuntu1) over (2.44-2ubuntu1) ... 1774s Preparing to unpack .../39-hwdata_0.393-3_all.deb ... 1774s Unpacking hwdata (0.393-3) over (0.392-1) ... 1774s Selecting previously unselected package pnp.ids. 1774s Preparing to unpack .../40-pnp.ids_0.393-3_all.deb ... 1774s Unpacking pnp.ids (0.393-3) ... 1775s Preparing to unpack .../41-linux-tools-common_6.14.0-10.10_all.deb ... 1775s Unpacking linux-tools-common (6.14.0-10.10) over (6.12.0-16.16) ... 1775s Selecting previously unselected package bpftool. 1775s Preparing to unpack .../42-bpftool_7.6.0+6.14.0-10.10_amd64.deb ... 1775s Unpacking bpftool (7.6.0+6.14.0-10.10) ... 1775s Preparing to unpack .../43-python3-markupsafe_2.1.5-1build4_amd64.deb ... 1775s Unpacking python3-markupsafe (2.1.5-1build4) over (2.1.5-1build3) ... 1775s Preparing to unpack .../44-python3-jinja2_3.1.5-2ubuntu1_all.deb ... 1775s Unpacking python3-jinja2 (3.1.5-2ubuntu1) over (3.1.5-2) ... 1775s Preparing to unpack .../45-cloud-init-base_25.1-0ubuntu3_all.deb ... 1775s Unpacking cloud-init-base (25.1-0ubuntu3) over (25.1-0ubuntu2) ... 1775s Preparing to unpack .../46-libbrotli1_1.1.0-2build4_amd64.deb ... 1775s Unpacking libbrotli1:amd64 (1.1.0-2build4) over (1.1.0-2build3) ... 1775s Preparing to unpack .../47-curl_8.12.1-3ubuntu1_amd64.deb ... 1775s Unpacking curl (8.12.1-3ubuntu1) over (8.12.1-2ubuntu1) ... 1775s Preparing to unpack .../48-libcurl4t64_8.12.1-3ubuntu1_amd64.deb ... 1775s Unpacking libcurl4t64:amd64 (8.12.1-3ubuntu1) over (8.12.1-2ubuntu1) ... 1775s Preparing to unpack .../49-exfatprogs_1.2.8-1_amd64.deb ... 1775s Unpacking exfatprogs (1.2.8-1) over (1.2.7-3) ... 1775s Preparing to unpack .../50-libcurl3t64-gnutls_8.12.1-3ubuntu1_amd64.deb ... 1775s Unpacking libcurl3t64-gnutls:amd64 (8.12.1-3ubuntu1) over (8.12.1-2ubuntu1) ... 1775s Preparing to unpack .../51-fwupd_2.0.6-4_amd64.deb ... 1775s Unpacking fwupd (2.0.6-4) over (2.0.6-3) ... 1776s Preparing to unpack .../52-libfwupd3_2.0.6-4_amd64.deb ... 1776s Unpacking libfwupd3:amd64 (2.0.6-4) over (2.0.6-3) ... 1776s Preparing to unpack .../53-libmm-glib0_1.23.4-0ubuntu3_amd64.deb ... 1776s Unpacking libmm-glib0:amd64 (1.23.4-0ubuntu3) over (1.23.4-0ubuntu2) ... 1776s Preparing to unpack .../54-htop_3.4.0-2_amd64.deb ... 1776s Unpacking htop (3.4.0-2) over (3.3.0-5) ... 1776s Preparing to unpack .../55-linux-firmware_20250310.git9e1370d3-0ubuntu1_amd64.deb ... 1776s Unpacking linux-firmware (20250310.git9e1370d3-0ubuntu1) over (20250204.git0fd450ee-0ubuntu1) ... 1778s Preparing to unpack .../56-initramfs-tools_0.146ubuntu1_all.deb ... 1778s Unpacking initramfs-tools (0.146ubuntu1) over (0.145ubuntu3) ... 1778s Preparing to unpack .../57-initramfs-tools-core_0.146ubuntu1_all.deb ... 1778s Unpacking initramfs-tools-core (0.146ubuntu1) over (0.145ubuntu3) ... 1778s Preparing to unpack .../58-initramfs-tools-bin_0.146ubuntu1_amd64.deb ... 1778s Unpacking initramfs-tools-bin (0.146ubuntu1) over (0.145ubuntu3) ... 1778s Selecting previously unselected package libdebuginfod1t64:amd64. 1779s Preparing to unpack .../59-libdebuginfod1t64_0.192-4_amd64.deb ... 1779s Unpacking libdebuginfod1t64:amd64 (0.192-4) ... 1779s Preparing to unpack .../60-libftdi1-2_1.5-8build1_amd64.deb ... 1779s Unpacking libftdi1-2:amd64 (1.5-8build1) over (1.5-8) ... 1779s Preparing to unpack .../61-libgpgme11t64_1.24.2-1ubuntu2_amd64.deb ... 1779s Unpacking libgpgme11t64:amd64 (1.24.2-1ubuntu2) over (1.24.2-1ubuntu1) ... 1779s Preparing to unpack .../62-libjemalloc2_5.3.0-3_amd64.deb ... 1779s Unpacking libjemalloc2:amd64 (5.3.0-3) over (5.3.0-2build1) ... 1779s Selecting previously unselected package linux-modules-6.14.0-10-generic. 1779s Preparing to unpack .../63-linux-modules-6.14.0-10-generic_6.14.0-10.10_amd64.deb ... 1779s Unpacking linux-modules-6.14.0-10-generic (6.14.0-10.10) ... 1779s Selecting previously unselected package linux-image-6.14.0-10-generic. 1779s Preparing to unpack .../64-linux-image-6.14.0-10-generic_6.14.0-10.10_amd64.deb ... 1779s Unpacking linux-image-6.14.0-10-generic (6.14.0-10.10) ... 1779s Selecting previously unselected package linux-modules-extra-6.14.0-10-generic. 1779s Preparing to unpack .../65-linux-modules-extra-6.14.0-10-generic_6.14.0-10.10_amd64.deb ... 1779s Unpacking linux-modules-extra-6.14.0-10-generic (6.14.0-10.10) ... 1780s Preparing to unpack .../66-linux-generic_6.14.0-10.10_amd64.deb ... 1780s Unpacking linux-generic (6.14.0-10.10) over (6.12.0-16.16+2) ... 1780s Preparing to unpack .../67-linux-image-generic_6.14.0-10.10_amd64.deb ... 1780s Unpacking linux-image-generic (6.14.0-10.10) over (6.12.0-16.16+2) ... 1780s Preparing to unpack .../68-linux-virtual_6.14.0-10.10_amd64.deb ... 1780s Unpacking linux-virtual (6.14.0-10.10) over (6.12.0-16.16+2) ... 1780s Preparing to unpack .../69-linux-image-virtual_6.14.0-10.10_amd64.deb ... 1780s Unpacking linux-image-virtual (6.14.0-10.10) over (6.12.0-16.16+2) ... 1780s Preparing to unpack .../70-linux-headers-virtual_6.14.0-10.10_amd64.deb ... 1780s Unpacking linux-headers-virtual (6.14.0-10.10) over (6.12.0-16.16+2) ... 1780s Selecting previously unselected package linux-headers-6.14.0-10. 1780s Preparing to unpack .../71-linux-headers-6.14.0-10_6.14.0-10.10_all.deb ... 1780s Unpacking linux-headers-6.14.0-10 (6.14.0-10.10) ... 1783s Selecting previously unselected package linux-headers-6.14.0-10-generic. 1783s Preparing to unpack .../72-linux-headers-6.14.0-10-generic_6.14.0-10.10_amd64.deb ... 1783s Unpacking linux-headers-6.14.0-10-generic (6.14.0-10.10) ... 1784s Preparing to unpack .../73-linux-headers-generic_6.14.0-10.10_amd64.deb ... 1784s Unpacking linux-headers-generic (6.14.0-10.10) over (6.12.0-16.16+2) ... 1784s Selecting previously unselected package linux-perf. 1784s Preparing to unpack .../74-linux-perf_6.14.0-10.10_amd64.deb ... 1784s Unpacking linux-perf (6.14.0-10.10) ... 1784s Selecting previously unselected package linux-tools-6.14.0-10. 1784s Preparing to unpack .../75-linux-tools-6.14.0-10_6.14.0-10.10_amd64.deb ... 1784s Unpacking linux-tools-6.14.0-10 (6.14.0-10.10) ... 1784s Selecting previously unselected package linux-tools-6.14.0-10-generic. 1784s Preparing to unpack .../76-linux-tools-6.14.0-10-generic_6.14.0-10.10_amd64.deb ... 1784s Unpacking linux-tools-6.14.0-10-generic (6.14.0-10.10) ... 1784s Preparing to unpack .../77-pinentry-curses_1.3.1-2ubuntu3_amd64.deb ... 1784s Unpacking pinentry-curses (1.3.1-2ubuntu3) over (1.3.1-2ubuntu2) ... 1784s Preparing to unpack .../78-python3-lazr.uri_1.0.6-6_all.deb ... 1784s Unpacking python3-lazr.uri (1.0.6-6) over (1.0.6-5) ... 1784s Preparing to unpack .../79-python3-rpds-py_0.21.0-2ubuntu2_amd64.deb ... 1784s Unpacking python3-rpds-py (0.21.0-2ubuntu2) over (0.21.0-2ubuntu1) ... 1785s Preparing to unpack .../80-python3-systemd_235-1build6_amd64.deb ... 1785s Unpacking python3-systemd (235-1build6) over (235-1build5) ... 1785s Preparing to unpack .../81-python3.13-gdbm_3.13.2-2_amd64.deb ... 1785s Unpacking python3.13-gdbm (3.13.2-2) over (3.13.2-1) ... 1785s Preparing to unpack .../82-ubuntu-kernel-accessories_1.549_amd64.deb ... 1785s Unpacking ubuntu-kernel-accessories (1.549) over (1.548) ... 1785s Preparing to unpack .../83-cloud-init_25.1-0ubuntu3_all.deb ... 1785s Unpacking cloud-init (25.1-0ubuntu3) over (25.1-0ubuntu2) ... 1785s Preparing to unpack .../84-python3-bcrypt_4.2.0-2.1build1_amd64.deb ... 1785s Unpacking python3-bcrypt (4.2.0-2.1build1) over (4.2.0-2.1) ... 1785s Setting up linux-headers-6.14.0-10 (6.14.0-10.10) ... 1785s Setting up media-types (13.0.0) ... 1785s Installing new version of config file /etc/mime.types ... 1785s Setting up linux-headers-6.14.0-10-generic (6.14.0-10.10) ... 1785s Setting up ubuntu-kernel-accessories (1.549) ... 1785s Setting up libapparmor1:amd64 (4.1.0~beta5-0ubuntu8) ... 1785s Setting up pci.ids (0.0~2025.03.09-1) ... 1785s Setting up libnewt0.52:amd64 (0.52.24-4ubuntu2) ... 1785s Setting up apt-utils (2.9.33) ... 1785s Setting up libdebuginfod-common (0.192-4) ... 1785s Setting up exfatprogs (1.2.8-1) ... 1785s Setting up linux-firmware (20250310.git9e1370d3-0ubuntu1) ... 1785s Setting up bpftool (7.6.0+6.14.0-10.10) ... 1785s Setting up libestr0:amd64 (0.1.11-2) ... 1785s Setting up libbrotli1:amd64 (1.1.0-2build4) ... 1785s Setting up libsqlite3-0:amd64 (3.46.1-2) ... 1785s Setting up dosfstools (4.2-1.2) ... 1785s Setting up rsyslog (8.2412.0-2ubuntu2) ... 1785s info: The user `syslog' is already a member of `adm'. 1786s Setting up binutils-common:amd64 (2.44-3ubuntu1) ... 1786s Setting up libcurl3t64-gnutls:amd64 (8.12.1-3ubuntu1) ... 1786s Setting up linux-libc-dev:amd64 (6.14.0-10.10) ... 1786s Setting up libctf-nobfd0:amd64 (2.44-3ubuntu1) ... 1786s Setting up systemd (257.3-1ubuntu3) ... 1786s /usr/lib/tmpfiles.d/legacy.conf:14: Duplicate line for path "/run/lock", ignoring. 1786s Created symlink '/run/systemd/system/tmp.mount' → '/dev/null'. 1786s /usr/lib/tmpfiles.d/legacy.conf:14: Duplicate line for path "/run/lock", ignoring. 1787s Setting up libparted2t64:amd64 (3.6-5) ... 1787s Removing 'diversion of /lib/x86_64-linux-gnu/libparted.so.2 to /lib/x86_64-linux-gnu/libparted.so.2.usr-is-merged by libparted2t64' 1787s Removing 'diversion of /lib/x86_64-linux-gnu/libparted.so.2.0.5 to /lib/x86_64-linux-gnu/libparted.so.2.0.5.usr-is-merged by libparted2t64' 1787s Setting up linux-headers-generic (6.14.0-10.10) ... 1787s Setting up libjemalloc2:amd64 (5.3.0-3) ... 1787s Setting up locales (2.41-1ubuntu1) ... 1787s Installing new version of config file /etc/locale.alias ... 1788s Generating locales (this might take a while)... 1789s en_US.UTF-8... done 1789s Generation complete. 1789s Setting up libsframe1:amd64 (2.44-3ubuntu1) ... 1789s Setting up libpython3.13-minimal:amd64 (3.13.2-2) ... 1789s Setting up apparmor (4.1.0~beta5-0ubuntu8) ... 1789s Installing new version of config file /etc/apparmor.d/fusermount3 ... 1789s Installing new version of config file /etc/apparmor.d/lsusb ... 1789s Installing new version of config file /etc/apparmor.d/openvpn ... 1790s Reloading AppArmor profiles 1791s Setting up libftdi1-2:amd64 (1.5-8build1) ... 1791s Setting up libglib2.0-data (2.84.0-1) ... 1791s Setting up systemd-cryptsetup (257.3-1ubuntu3) ... 1791s Setting up libncurses6:amd64 (6.5+20250216-2) ... 1791s Setting up strace (6.13+ds-1ubuntu1) ... 1791s Setting up xz-utils (5.6.4-1) ... 1791s Setting up systemd-timesyncd (257.3-1ubuntu3) ... 1792s systemd-time-wait-sync.service is a disabled or a static unit not running, not starting it. 1792s Setting up libatomic1:amd64 (15-20250222-0ubuntu1) ... 1792s Setting up udev (257.3-1ubuntu3) ... 1793s Setting up linux-modules-6.14.0-10-generic (6.14.0-10.10) ... 1795s Setting up libncursesw6:amd64 (6.5+20250216-2) ... 1795s Setting up libpci3:amd64 (1:3.13.0-2) ... 1795s Setting up whiptail (0.52.24-4ubuntu2) ... 1795s Setting up python-apt-common (2.9.9build1) ... 1795s Setting up pnp.ids (0.393-3) ... 1795s Setting up libnl-3-200:amd64 (3.7.0-1) ... 1795s Setting up python3.13-minimal (3.13.2-2) ... 1795s Setting up libgpgme11t64:amd64 (1.24.2-1ubuntu2) ... 1795s Setting up libbinutils:amd64 (2.44-3ubuntu1) ... 1795s Setting up libc-dev-bin (2.41-1ubuntu1) ... 1795s Setting up libpython3.13-stdlib:amd64 (3.13.2-2) ... 1795s Setting up libxml2:amd64 (2.12.7+dfsg+really2.9.14-0.2ubuntu5) ... 1795s Setting up rsync (3.4.1+ds1-3) ... 1796s rsync.service is a disabled or a static unit not running, not starting it. 1796s Setting up python3.13-gdbm (3.13.2-2) ... 1796s Setting up libpython3-stdlib:amd64 (3.13.2-2) ... 1796s Setting up systemd-resolved (257.3-1ubuntu3) ... 1796s Setting up initramfs-tools-bin (0.146ubuntu1) ... 1796s Setting up ncurses-term (6.5+20250216-2) ... 1796s Setting up libctf0:amd64 (2.44-3ubuntu1) ... 1796s Setting up libpython3.13:amd64 (3.13.2-2) ... 1796s Setting up pinentry-curses (1.3.1-2ubuntu3) ... 1796s Setting up libdebuginfod1t64:amd64 (0.192-4) ... 1796s Setting up systemd-sysv (257.3-1ubuntu3) ... 1796s Setting up linux-headers-virtual (6.14.0-10.10) ... 1796s Setting up libcurl4t64:amd64 (8.12.1-3ubuntu1) ... 1796s Setting up python3.13 (3.13.2-2) ... 1797s Setting up htop (3.4.0-2) ... 1797s Setting up linux-image-6.14.0-10-generic (6.14.0-10.10) ... 1799s I: /boot/vmlinuz.old is now a symlink to vmlinuz-6.12.0-16-generic 1799s I: /boot/initrd.img.old is now a symlink to initrd.img-6.12.0-16-generic 1799s I: /boot/vmlinuz is now a symlink to vmlinuz-6.14.0-10-generic 1799s I: /boot/initrd.img is now a symlink to initrd.img-6.14.0-10-generic 1799s Setting up parted (3.6-5) ... 1799s Setting up libnss-systemd:amd64 (257.3-1ubuntu3) ... 1799s Setting up python3 (3.13.2-2) ... 1799s Setting up python3-newt:amd64 (0.52.24-4ubuntu2) ... 1800s Setting up python3-markupsafe (2.1.5-1build4) ... 1800s Setting up linux-modules-extra-6.14.0-10-generic (6.14.0-10.10) ... 1802s Setting up libnl-route-3-200:amd64 (3.7.0-1) ... 1802s Setting up hwdata (0.393-3) ... 1802s Setting up python3-jinja2 (3.1.5-2ubuntu1) ... 1802s Setting up libglib2.0-0t64:amd64 (2.84.0-1) ... 1802s No schema files found: doing nothing. 1802s Setting up libgprofng0:amd64 (2.44-3ubuntu1) ... 1802s Setting up linux-perf (6.14.0-10.10) ... 1802s Setting up gir1.2-glib-2.0:amd64 (2.84.0-1) ... 1802s Setting up pciutils (1:3.13.0-2) ... 1802s Setting up python3-rpds-py (0.21.0-2ubuntu2) ... 1802s Setting up libmm-glib0:amd64 (1.23.4-0ubuntu3) ... 1802s Setting up libnl-genl-3-200:amd64 (3.7.0-1) ... 1802s Setting up libpam-systemd:amd64 (257.3-1ubuntu3) ... 1802s Setting up libc6-dev:amd64 (2.41-1ubuntu1) ... 1802s Setting up libgirepository-1.0-1:amd64 (1.83.4-1) ... 1802s Setting up curl (8.12.1-3ubuntu1) ... 1802s Setting up linux-image-virtual (6.14.0-10.10) ... 1802s Setting up initramfs-tools-core (0.146ubuntu1) ... 1802s Setting up linux-tools-common (6.14.0-10.10) ... 1802s Setting up python3-systemd (235-1build6) ... 1802s Setting up python3-cffi-backend:amd64 (1.17.1-2build2) ... 1802s Setting up binutils-x86-64-linux-gnu (2.44-3ubuntu1) ... 1802s Setting up linux-image-generic (6.14.0-10.10) ... 1802s Setting up python3-dbus (1.3.2-5build5) ... 1802s Setting up linux-tools-6.14.0-10 (6.14.0-10.10) ... 1802s Setting up initramfs-tools (0.146ubuntu1) ... 1802s Installing new version of config file /etc/kernel/postinst.d/initramfs-tools ... 1802s Installing new version of config file /etc/kernel/postrm.d/initramfs-tools ... 1802s update-initramfs: deferring update (trigger activated) 1802s Setting up linux-generic (6.14.0-10.10) ... 1802s Setting up ubuntu-minimal (1.549) ... 1802s Setting up python3-apt (2.9.9build1) ... 1802s Setting up python3-bcrypt (4.2.0-2.1build1) ... 1802s Setting up python3-yaml (6.0.2-1build2) ... 1803s Setting up libfwupd3:amd64 (2.0.6-4) ... 1803s Setting up python3-lazr.uri (1.0.6-6) ... 1803s Setting up binutils (2.44-3ubuntu1) ... 1803s Setting up ubuntu-standard (1.549) ... 1803s Setting up cloud-init-base (25.1-0ubuntu3) ... 1804s Setting up linux-virtual (6.14.0-10.10) ... 1804s Setting up gir1.2-girepository-2.0:amd64 (1.83.4-1) ... 1804s Setting up python3-gi (3.50.0-4build1) ... 1804s Setting up linux-tools-6.14.0-10-generic (6.14.0-10.10) ... 1804s Setting up fwupd (2.0.6-4) ... 1805s fwupd-refresh.service is a disabled or a static unit not running, not starting it. 1805s fwupd.service is a disabled or a static unit not running, not starting it. 1805s Setting up cloud-init (25.1-0ubuntu3) ... 1805s Processing triggers for man-db (2.13.0-1) ... 1806s Processing triggers for dbus (1.16.2-1ubuntu1) ... 1806s Processing triggers for shared-mime-info (2.4-5) ... 1806s Warning: program compiled against libxml 212 using older 209 1807s Processing triggers for libc-bin (2.41-1ubuntu1) ... 1807s Processing triggers for linux-image-6.14.0-10-generic (6.14.0-10.10) ... 1807s /etc/kernel/postinst.d/initramfs-tools: 1807s update-initramfs: Generating /boot/initrd.img-6.14.0-10-generic 1807s W: No lz4 in /usr/bin:/sbin:/bin, using gzip 1816s /etc/kernel/postinst.d/zz-update-grub: 1816s Sourcing file `/etc/default/grub' 1816s Sourcing file `/etc/default/grub.d/50-cloudimg-settings.cfg' 1816s Sourcing file `/etc/default/grub.d/90-autopkgtest.cfg' 1816s Generating grub configuration file ... 1816s Found linux image: /boot/vmlinuz-6.14.0-10-generic 1816s Found initrd image: /boot/initrd.img-6.14.0-10-generic 1816s Found linux image: /boot/vmlinuz-6.12.0-16-generic 1816s Found initrd image: /boot/initrd.img-6.12.0-16-generic 1817s Found linux image: /boot/vmlinuz-6.11.0-8-generic 1817s Found initrd image: /boot/initrd.img-6.11.0-8-generic 1817s Warning: os-prober will not be executed to detect other bootable partitions. 1817s Systems on them will not be added to the GRUB boot configuration. 1817s Check GRUB_DISABLE_OS_PROBER documentation entry. 1817s Adding boot menu entry for UEFI Firmware Settings ... 1817s done 1817s Processing triggers for initramfs-tools (0.146ubuntu1) ... 1817s update-initramfs: Generating /boot/initrd.img-6.14.0-10-generic 1817s W: No lz4 in /usr/bin:/sbin:/bin, using gzip 1827s Reading package lists... 1828s Building dependency tree... 1828s Reading state information... 1828s Solving dependencies... 1828s The following packages will be REMOVED: 1828s libnl-genl-3-200* libnsl2* libpython3.12-minimal* libpython3.12-stdlib* 1828s libpython3.12t64* linux-headers-6.11.0-8* linux-headers-6.11.0-8-generic* 1828s linux-headers-6.12.0-16* linux-headers-6.12.0-16-generic* 1828s linux-image-6.11.0-8-generic* linux-image-6.12.0-16-generic* 1828s linux-modules-6.11.0-8-generic* linux-modules-6.12.0-16-generic* 1828s linux-modules-extra-6.12.0-16-generic* linux-tools-6.11.0-8* 1828s linux-tools-6.11.0-8-generic* linux-tools-6.12.0-16* 1828s linux-tools-6.12.0-16-generic* 1828s 0 upgraded, 0 newly installed, 18 to remove and 5 not upgraded. 1828s After this operation, 545 MB disk space will be freed. 1828s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 148643 files and directories currently installed.) 1828s Removing libnl-genl-3-200:amd64 (3.7.0-1) ... 1828s Removing linux-tools-6.11.0-8-generic (6.11.0-8.8) ... 1828s Removing linux-tools-6.11.0-8 (6.11.0-8.8) ... 1828s Removing libpython3.12t64:amd64 (3.12.9-1) ... 1828s Removing libpython3.12-stdlib:amd64 (3.12.9-1) ... 1828s Removing libnsl2:amd64 (1.3.0-3build3) ... 1828s Removing libpython3.12-minimal:amd64 (3.12.9-1) ... 1828s Removing linux-headers-6.11.0-8-generic (6.11.0-8.8) ... 1829s Removing linux-headers-6.11.0-8 (6.11.0-8.8) ... 1831s Removing linux-headers-6.12.0-16-generic (6.12.0-16.16) ... 1831s Removing linux-headers-6.12.0-16 (6.12.0-16.16) ... 1833s Removing linux-image-6.11.0-8-generic (6.11.0-8.8) ... 1833s /etc/kernel/postrm.d/initramfs-tools: 1833s update-initramfs: Deleting /boot/initrd.img-6.11.0-8-generic 1833s /etc/kernel/postrm.d/zz-update-grub: 1833s Sourcing file `/etc/default/grub' 1833s Sourcing file `/etc/default/grub.d/50-cloudimg-settings.cfg' 1833s Sourcing file `/etc/default/grub.d/90-autopkgtest.cfg' 1833s Generating grub configuration file ... 1834s Found linux image: /boot/vmlinuz-6.14.0-10-generic 1834s Found initrd image: /boot/initrd.img-6.14.0-10-generic 1834s Found linux image: /boot/vmlinuz-6.12.0-16-generic 1834s Found initrd image: /boot/initrd.img-6.12.0-16-generic 1834s Warning: os-prober will not be executed to detect other bootable partitions. 1834s Systems on them will not be added to the GRUB boot configuration. 1834s Check GRUB_DISABLE_OS_PROBER documentation entry. 1834s Adding boot menu entry for UEFI Firmware Settings ... 1834s done 1834s Removing linux-image-6.12.0-16-generic (6.12.0-16.16) ... 1834s W: Removing the running kernel 1834s I: /boot/vmlinuz.old is now a symlink to vmlinuz-6.14.0-10-generic 1834s I: /boot/initrd.img.old is now a symlink to initrd.img-6.14.0-10-generic 1834s /etc/kernel/postrm.d/initramfs-tools: 1834s update-initramfs: Deleting /boot/initrd.img-6.12.0-16-generic 1834s /etc/kernel/postrm.d/zz-update-grub: 1834s Sourcing file `/etc/default/grub' 1834s Sourcing file `/etc/default/grub.d/50-cloudimg-settings.cfg' 1834s Sourcing file `/etc/default/grub.d/90-autopkgtest.cfg' 1834s Generating grub configuration file ... 1834s Found linux image: /boot/vmlinuz-6.14.0-10-generic 1834s Found initrd image: /boot/initrd.img-6.14.0-10-generic 1835s Warning: os-prober will not be executed to detect other bootable partitions. 1835s Systems on them will not be added to the GRUB boot configuration. 1835s Check GRUB_DISABLE_OS_PROBER documentation entry. 1835s Adding boot menu entry for UEFI Firmware Settings ... 1835s done 1835s Removing linux-modules-6.11.0-8-generic (6.11.0-8.8) ... 1835s Removing linux-modules-extra-6.12.0-16-generic (6.12.0-16.16) ... 1836s Removing linux-modules-6.12.0-16-generic (6.12.0-16.16) ... 1836s Removing linux-tools-6.12.0-16-generic (6.12.0-16.16) ... 1836s Removing linux-tools-6.12.0-16 (6.12.0-16.16) ... 1836s Processing triggers for libc-bin (2.41-1ubuntu1) ... 1836s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 76972 files and directories currently installed.) 1836s Purging configuration files for linux-image-6.11.0-8-generic (6.11.0-8.8) ... 1836s Purging configuration files for libpython3.12-minimal:amd64 (3.12.9-1) ... 1836s Purging configuration files for linux-modules-extra-6.12.0-16-generic (6.12.0-16.16) ... 1836s Purging configuration files for linux-modules-6.12.0-16-generic (6.12.0-16.16) ... 1836s dpkg: warning: while removing linux-modules-6.12.0-16-generic, directory '/lib/modules/6.12.0-16-generic' not empty so not removed 1836s Purging configuration files for linux-modules-6.11.0-8-generic (6.11.0-8.8) ... 1836s Purging configuration files for linux-image-6.12.0-16-generic (6.12.0-16.16) ... 1837s rmdir: failed to remove '/lib/modules/6.12.0-16-generic': Directory not empty 1837s autopkgtest [00:25:20]: upgrading testbed (apt dist-upgrade and autopurge) 1837s Reading package lists... 1837s Building dependency tree... 1837s Reading state information... 1837s Calculating upgrade...Starting pkgProblemResolver with broken count: 0 1838s Starting 2 pkgProblemResolver with broken count: 0 1838s Done 1838s Entering ResolveByKeep 1838s 1838s Calculating upgrade... 1838s The following packages will be upgraded: 1838s libc-bin libc-dev-bin libc6 libc6-dev locales 1839s 5 upgraded, 0 newly installed, 0 to remove and 0 not upgraded. 1839s Need to get 10.5 MB of archives. 1839s After this operation, 1024 B of additional disk space will be used. 1839s Get:1 http://ftpmaster.internal/ubuntu plucky-proposed/main amd64 libc6-dev amd64 2.41-1ubuntu2 [2183 kB] 1839s Get:2 http://ftpmaster.internal/ubuntu plucky-proposed/main amd64 libc-dev-bin amd64 2.41-1ubuntu2 [24.7 kB] 1839s Get:3 http://ftpmaster.internal/ubuntu plucky-proposed/main amd64 libc6 amd64 2.41-1ubuntu2 [3327 kB] 1839s Get:4 http://ftpmaster.internal/ubuntu plucky-proposed/main amd64 libc-bin amd64 2.41-1ubuntu2 [700 kB] 1839s Get:5 http://ftpmaster.internal/ubuntu plucky-proposed/main amd64 locales all 2.41-1ubuntu2 [4246 kB] 1840s Preconfiguring packages ... 1840s Fetched 10.5 MB in 1s (9809 kB/s) 1840s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 76968 files and directories currently installed.) 1840s Preparing to unpack .../libc6-dev_2.41-1ubuntu2_amd64.deb ... 1840s Unpacking libc6-dev:amd64 (2.41-1ubuntu2) over (2.41-1ubuntu1) ... 1840s Preparing to unpack .../libc-dev-bin_2.41-1ubuntu2_amd64.deb ... 1840s Unpacking libc-dev-bin (2.41-1ubuntu2) over (2.41-1ubuntu1) ... 1840s Preparing to unpack .../libc6_2.41-1ubuntu2_amd64.deb ... 1840s Unpacking libc6:amd64 (2.41-1ubuntu2) over (2.41-1ubuntu1) ... 1840s Setting up libc6:amd64 (2.41-1ubuntu2) ... 1841s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 76968 files and directories currently installed.) 1841s Preparing to unpack .../libc-bin_2.41-1ubuntu2_amd64.deb ... 1841s Unpacking libc-bin (2.41-1ubuntu2) over (2.41-1ubuntu1) ... 1841s Setting up libc-bin (2.41-1ubuntu2) ... 1841s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 76968 files and directories currently installed.) 1841s Preparing to unpack .../locales_2.41-1ubuntu2_all.deb ... 1841s Unpacking locales (2.41-1ubuntu2) over (2.41-1ubuntu1) ... 1841s Setting up locales (2.41-1ubuntu2) ... 1842s Generating locales (this might take a while)... 1843s en_US.UTF-8... done 1843s Generation complete. 1843s Setting up libc-dev-bin (2.41-1ubuntu2) ... 1843s Setting up libc6-dev:amd64 (2.41-1ubuntu2) ... 1843s Processing triggers for man-db (2.13.0-1) ... 1844s Processing triggers for systemd (257.3-1ubuntu3) ... 1844s Reading package lists... 1845s Building dependency tree... 1845s Reading state information... 1845s Starting pkgProblemResolver with broken count: 0 1845s Starting 2 pkgProblemResolver with broken count: 0 1845s Done 1845s Solving dependencies... 1845s 0 upgraded, 0 newly installed, 0 to remove and 0 not upgraded. 1846s autopkgtest [00:25:29]: rebooting testbed after setup commands that affected boot 1872s Reading package lists... 1872s Building dependency tree... 1872s Reading state information... 1872s Starting pkgProblemResolver with broken count: 0 1872s Starting 2 pkgProblemResolver with broken count: 0 1872s Done 1873s The following NEW packages will be installed: 1873s libtcl8.6 python3-click yosys yosys-abc 1873s 0 upgraded, 4 newly installed, 0 to remove and 0 not upgraded. 1873s Need to get 10.2 MB of archives. 1873s After this operation, 32.5 MB of additional disk space will be used. 1873s Get:1 http://ftpmaster.internal/ubuntu plucky/main amd64 libtcl8.6 amd64 8.6.16+dfsg-1 [1086 kB] 1873s Get:2 http://ftpmaster.internal/ubuntu plucky/main amd64 python3-click all 8.2.0+0.really.8.1.8-1 [80.0 kB] 1873s Get:3 http://ftpmaster.internal/ubuntu plucky/universe amd64 yosys-abc amd64 0.33-5build2 [5829 kB] 1874s Get:4 http://ftpmaster.internal/ubuntu plucky/universe amd64 yosys amd64 0.33-5build2 [3222 kB] 1874s Fetched 10.2 MB in 1s (9750 kB/s) 1874s Selecting previously unselected package libtcl8.6:amd64. 1874s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 76968 files and directories currently installed.) 1874s Preparing to unpack .../libtcl8.6_8.6.16+dfsg-1_amd64.deb ... 1874s Unpacking libtcl8.6:amd64 (8.6.16+dfsg-1) ... 1874s Selecting previously unselected package python3-click. 1874s Preparing to unpack .../python3-click_8.2.0+0.really.8.1.8-1_all.deb ... 1874s Unpacking python3-click (8.2.0+0.really.8.1.8-1) ... 1874s Selecting previously unselected package yosys-abc. 1874s Preparing to unpack .../yosys-abc_0.33-5build2_amd64.deb ... 1874s Unpacking yosys-abc (0.33-5build2) ... 1875s Selecting previously unselected package yosys. 1875s Preparing to unpack .../yosys_0.33-5build2_amd64.deb ... 1875s Unpacking yosys (0.33-5build2) ... 1875s Setting up yosys-abc (0.33-5build2) ... 1875s Setting up python3-click (8.2.0+0.really.8.1.8-1) ... 1875s Setting up libtcl8.6:amd64 (8.6.16+dfsg-1) ... 1875s Setting up yosys (0.33-5build2) ... 1875s Processing triggers for libc-bin (2.41-1ubuntu2) ... 1875s Processing triggers for man-db (2.13.0-1) ... 1898s autopkgtest [00:26:21]: test ice: [----------------------- 1898s 1898s /----------------------------------------------------------------------------\ 1898s | | 1898s | yosys -- Yosys Open SYnthesis Suite | 1898s | | 1898s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1898s | | 1898s | Permission to use, copy, modify, and/or distribute this software for any | 1898s | purpose with or without fee is hereby granted, provided that the above | 1898s | copyright notice and this permission notice appear in all copies. | 1898s | | 1898s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1898s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1898s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1898s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1898s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1898s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1898s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1898s | | 1898s \----------------------------------------------------------------------------/ 1898s 1898s Yosys 0.33 (git sha1 2584903a060) 1898s 1898s 1898s -- Running command `read_verilog debian/tests/design_ice.v; synth_ice40 -blif /tmp/autopkgtest.dZoNHp/autopkgtest_tmp/design_ice.blif' -- 1898s 1898s 1. Executing Verilog-2005 frontend: debian/tests/design_ice.v 1898s Parsing Verilog input from `debian/tests/design_ice.v' to AST representation. 1898s Generating RTLIL representation for module `\design_ice'. 1898s Successfully finished Verilog frontend. 1898s 1898s 2. Executing SYNTH_ICE40 pass. 1898s 1898s 2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v 1898s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation. 1898s Generating RTLIL representation for module `\SB_IO'. 1898s Generating RTLIL representation for module `\SB_GB_IO'. 1898s Generating RTLIL representation for module `\SB_GB'. 1898s Generating RTLIL representation for module `\SB_LUT4'. 1898s Generating RTLIL representation for module `\SB_CARRY'. 1898s Generating RTLIL representation for module `\SB_DFF'. 1898s Generating RTLIL representation for module `\SB_DFFE'. 1898s Generating RTLIL representation for module `\SB_DFFSR'. 1898s Generating RTLIL representation for module `\SB_DFFR'. 1898s Generating RTLIL representation for module `\SB_DFFSS'. 1898s Generating RTLIL representation for module `\SB_DFFS'. 1898s Generating RTLIL representation for module `\SB_DFFESR'. 1898s Generating RTLIL representation for module `\SB_DFFER'. 1898s Generating RTLIL representation for module `\SB_DFFESS'. 1898s Generating RTLIL representation for module `\SB_DFFES'. 1898s Generating RTLIL representation for module `\SB_DFFN'. 1898s Generating RTLIL representation for module `\SB_DFFNE'. 1898s Generating RTLIL representation for module `\SB_DFFNSR'. 1898s Generating RTLIL representation for module `\SB_DFFNR'. 1898s Generating RTLIL representation for module `\SB_DFFNSS'. 1898s Generating RTLIL representation for module `\SB_DFFNS'. 1898s Generating RTLIL representation for module `\SB_DFFNESR'. 1898s Generating RTLIL representation for module `\SB_DFFNER'. 1898s Generating RTLIL representation for module `\SB_DFFNESS'. 1898s Generating RTLIL representation for module `\SB_DFFNES'. 1898s Generating RTLIL representation for module `\SB_RAM40_4K'. 1898s Generating RTLIL representation for module `\SB_RAM40_4KNR'. 1898s Generating RTLIL representation for module `\SB_RAM40_4KNW'. 1898s Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. 1898s Generating RTLIL representation for module `\ICESTORM_LC'. 1898s Generating RTLIL representation for module `\SB_PLL40_CORE'. 1898s Generating RTLIL representation for module `\SB_PLL40_PAD'. 1898s Generating RTLIL representation for module `\SB_PLL40_2_PAD'. 1898s Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. 1898s Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. 1898s Generating RTLIL representation for module `\SB_WARMBOOT'. 1898s Generating RTLIL representation for module `\SB_SPRAM256KA'. 1898s Generating RTLIL representation for module `\SB_HFOSC'. 1898s Generating RTLIL representation for module `\SB_LFOSC'. 1898s Generating RTLIL representation for module `\SB_RGBA_DRV'. 1898s Generating RTLIL representation for module `\SB_LED_DRV_CUR'. 1898s Generating RTLIL representation for module `\SB_RGB_DRV'. 1898s Generating RTLIL representation for module `\SB_I2C'. 1898s Generating RTLIL representation for module `\SB_SPI'. 1898s Generating RTLIL representation for module `\SB_LEDDA_IP'. 1898s Generating RTLIL representation for module `\SB_FILTER_50NS'. 1898s Generating RTLIL representation for module `\SB_IO_I3C'. 1898s Generating RTLIL representation for module `\SB_IO_OD'. 1898s Generating RTLIL representation for module `\SB_MAC16'. 1898s Generating RTLIL representation for module `\ICESTORM_RAM'. 1898s Successfully finished Verilog frontend. 1898s 1898s 2.2. Executing HIERARCHY pass (managing design hierarchy). 1898s 1898s 2.2.1. Finding top of design hierarchy.. 1898s root of 0 design levels: design_ice 1898s Automatically selected design_ice as design top module. 1898s 1898s 2.2.2. Analyzing design hierarchy.. 1898s Top module: \design_ice 1898s 1898s 2.2.3. Analyzing design hierarchy.. 1898s Top module: \design_ice 1898s Removed 0 unused modules. 1898s 1898s 2.3. Executing PROC pass (convert processes to netlists). 1898s 1898s 2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1898s Cleaned up 0 empty switches. 1898s 1898s 2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1898s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243 in module SB_DFFNES. 1898s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236 in module SB_DFFNESS. 1898s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232 in module SB_DFFNER. 1898s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225 in module SB_DFFNESR. 1898s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222 in module SB_DFFNS. 1898s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219 in module SB_DFFNSS. 1898s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216 in module SB_DFFNR. 1898s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213 in module SB_DFFNSR. 1898s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205 in module SB_DFFES. 1898s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198 in module SB_DFFESS. 1898s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194 in module SB_DFFER. 1898s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187 in module SB_DFFESR. 1898s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184 in module SB_DFFS. 1898s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181 in module SB_DFFSS. 1898s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178 in module SB_DFFR. 1898s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175 in module SB_DFFSR. 1898s Marked 1 switch rules as full_case in process $proc$debian/tests/design_ice.v:6$1 in module design_ice. 1898s Removed a total of 0 dead cases. 1898s 1898s 2.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1898s Removed 8 redundant assignments. 1898s Promoted 23 assignments to connections. 1898s 1898s 2.3.4. Executing PROC_INIT pass (extract init attributes). 1898s Found init rule in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$246'. 1898s Set init value: \Q = 1'0 1898s Found init rule in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$242'. 1898s Set init value: \Q = 1'0 1898s Found init rule in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$235'. 1898s Set init value: \Q = 1'0 1898s Found init rule in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$231'. 1898s Set init value: \Q = 1'0 1898s Found init rule in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$224'. 1898s Set init value: \Q = 1'0 1898s Found init rule in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$221'. 1898s Set init value: \Q = 1'0 1898s Found init rule in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$218'. 1898s Set init value: \Q = 1'0 1898s Found init rule in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$215'. 1898s Set init value: \Q = 1'0 1898s Found init rule in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$212'. 1898s Set init value: \Q = 1'0 1898s Found init rule in `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 1898s Set init value: \Q = 1'0 1898s Found init rule in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 1898s Set init value: \Q = 1'0 1898s Found init rule in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$204'. 1898s Set init value: \Q = 1'0 1898s Found init rule in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$197'. 1898s Set init value: \Q = 1'0 1898s Found init rule in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$193'. 1898s Set init value: \Q = 1'0 1898s Found init rule in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$186'. 1898s Set init value: \Q = 1'0 1898s Found init rule in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$183'. 1898s Set init value: \Q = 1'0 1898s Found init rule in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$180'. 1898s Set init value: \Q = 1'0 1898s Found init rule in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$177'. 1898s Set init value: \Q = 1'0 1898s Found init rule in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$174'. 1898s Set init value: \Q = 1'0 1898s Found init rule in `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 1898s Set init value: \Q = 1'0 1898s Found init rule in `\design_ice.$proc$debian/tests/design_ice.v:3$2'. 1898s Set init value: \ready = 1'0 1898s 1898s 2.3.5. Executing PROC_ARST pass (detect async resets in processes). 1898s Found async reset \S in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'. 1898s Found async reset \R in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'. 1898s Found async reset \S in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222'. 1898s Found async reset \R in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216'. 1898s Found async reset \S in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'. 1898s Found async reset \R in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'. 1898s Found async reset \S in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184'. 1898s Found async reset \R in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178'. 1898s 1898s 2.3.6. Executing PROC_ROM pass (convert switches to ROMs). 1898s Converted 0 switches. 1898s 1898s 1898s 2.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1898s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$246'. 1898s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'. 1898s 1/1: $0\Q[0:0] 1898s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$242'. 1898s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236'. 1898s 1/1: $0\Q[0:0] 1898s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$235'. 1898s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'. 1898s 1/1: $0\Q[0:0] 1898s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$231'. 1898s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225'. 1898s 1/1: $0\Q[0:0] 1898s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$224'. 1898s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222'. 1898s 1/1: $0\Q[0:0] 1898s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$221'. 1898s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219'. 1898s 1/1: $0\Q[0:0] 1898s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$218'. 1898s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216'. 1898s 1/1: $0\Q[0:0] 1898s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$215'. 1898s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213'. 1898s 1/1: $0\Q[0:0] 1898s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$212'. 1898s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$211'. 1898s 1/1: $0\Q[0:0] 1898s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 1898s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$209'. 1898s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 1898s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'. 1898s 1/1: $0\Q[0:0] 1898s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$204'. 1898s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198'. 1898s 1/1: $0\Q[0:0] 1898s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$197'. 1898s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'. 1898s 1/1: $0\Q[0:0] 1898s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$193'. 1898s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187'. 1898s 1/1: $0\Q[0:0] 1898s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$186'. 1898s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184'. 1898s 1/1: $0\Q[0:0] 1898s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$183'. 1898s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181'. 1898s 1/1: $0\Q[0:0] 1898s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$180'. 1898s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178'. 1898s 1/1: $0\Q[0:0] 1898s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$177'. 1898s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175'. 1898s 1/1: $0\Q[0:0] 1898s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$174'. 1898s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$173'. 1898s 1/1: $0\Q[0:0] 1898s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 1898s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$171'. 1898s Creating decoders for process `\design_ice.$proc$debian/tests/design_ice.v:3$2'. 1898s Creating decoders for process `\design_ice.$proc$debian/tests/design_ice.v:6$1'. 1898s 1/2: $0\value[0:0] 1898s 2/2: $0\ready[0:0] 1898s 1898s 2.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1898s 1898s 2.3.9. Executing PROC_DFF pass (convert process syncs to FFs). 1898s Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'. 1898s created $adff cell `$procdff$433' with negative edge clock and positive level reset. 1898s Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236'. 1898s created $dff cell `$procdff$434' with negative edge clock. 1898s Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'. 1898s created $adff cell `$procdff$435' with negative edge clock and positive level reset. 1898s Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225'. 1898s created $dff cell `$procdff$436' with negative edge clock. 1898s Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222'. 1898s created $adff cell `$procdff$437' with negative edge clock and positive level reset. 1898s Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219'. 1898s created $dff cell `$procdff$438' with negative edge clock. 1898s Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216'. 1898s created $adff cell `$procdff$439' with negative edge clock and positive level reset. 1898s Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213'. 1898s created $dff cell `$procdff$440' with negative edge clock. 1898s Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$211'. 1898s created $dff cell `$procdff$441' with negative edge clock. 1898s Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$209'. 1898s created $dff cell `$procdff$442' with negative edge clock. 1898s Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'. 1898s created $adff cell `$procdff$443' with positive edge clock and positive level reset. 1898s Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198'. 1898s created $dff cell `$procdff$444' with positive edge clock. 1898s Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'. 1898s created $adff cell `$procdff$445' with positive edge clock and positive level reset. 1898s Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187'. 1898s created $dff cell `$procdff$446' with positive edge clock. 1898s Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184'. 1898s created $adff cell `$procdff$447' with positive edge clock and positive level reset. 1898s Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181'. 1898s created $dff cell `$procdff$448' with positive edge clock. 1898s Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178'. 1898s created $adff cell `$procdff$449' with positive edge clock and positive level reset. 1898s Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175'. 1898s created $dff cell `$procdff$450' with positive edge clock. 1898s Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$173'. 1898s created $dff cell `$procdff$451' with positive edge clock. 1898s Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$171'. 1898s created $dff cell `$procdff$452' with positive edge clock. 1898s Creating register for signal `\design_ice.\ready' using process `\design_ice.$proc$debian/tests/design_ice.v:6$1'. 1898s created $dff cell `$procdff$453' with positive edge clock. 1898s Creating register for signal `\design_ice.\value' using process `\design_ice.$proc$debian/tests/design_ice.v:6$1'. 1898s created $dff cell `$procdff$454' with positive edge clock. 1898s 1898s 2.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1898s 1898s 2.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1898s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$246'. 1898s Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'. 1898s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'. 1898s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$242'. 1898s Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236'. 1898s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236'. 1898s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$235'. 1898s Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'. 1898s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'. 1898s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$231'. 1898s Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225'. 1898s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225'. 1898s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$224'. 1898s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222'. 1898s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$221'. 1898s Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219'. 1898s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219'. 1898s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$218'. 1898s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216'. 1898s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$215'. 1898s Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213'. 1898s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213'. 1898s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$212'. 1898s Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$211'. 1898s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$211'. 1898s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 1898s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$209'. 1898s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 1898s Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'. 1898s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'. 1898s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$204'. 1898s Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198'. 1898s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198'. 1898s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$197'. 1898s Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'. 1898s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'. 1898s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$193'. 1898s Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187'. 1898s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187'. 1898s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$186'. 1898s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184'. 1898s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$183'. 1898s Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181'. 1898s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181'. 1898s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$180'. 1898s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178'. 1898s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$177'. 1898s Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175'. 1898s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175'. 1898s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$174'. 1898s Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$173'. 1898s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$173'. 1898s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 1898s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$171'. 1898s Removing empty process `design_ice.$proc$debian/tests/design_ice.v:3$2'. 1898s Found and cleaned up 1 empty switch in `\design_ice.$proc$debian/tests/design_ice.v:6$1'. 1898s Removing empty process `design_ice.$proc$debian/tests/design_ice.v:6$1'. 1898s Cleaned up 19 empty switches. 1898s 1898s 2.3.12. Executing OPT_EXPR pass (perform const folding). 1898s Optimizing module design_ice. 1898s 1898s 2.4. Executing FLATTEN pass (flatten design). 1898s 1898s 2.5. Executing TRIBUF pass. 1898s 1898s 2.6. Executing DEMINOUT pass (demote inout ports to input or output). 1898s 1898s 2.7. Executing OPT_EXPR pass (perform const folding). 1898s Optimizing module design_ice. 1898s 1898s 2.8. Executing OPT_CLEAN pass (remove unused cells and wires). 1898s Finding unused cells or wires in module \design_ice.. 1898s Removed 0 unused cells and 5 unused wires. 1898s 1898s 1898s 2.9. Executing CHECK pass (checking for obvious problems). 1898s Checking module design_ice... 1898s Found and reported 0 problems. 1898s 1898s 2.10. Executing OPT pass (performing simple optimizations). 1898s 1898s 2.10.1. Executing OPT_EXPR pass (perform const folding). 1898s Optimizing module design_ice. 1898s 1898s 2.10.2. Executing OPT_MERGE pass (detect identical cells). 1898s Finding identical cells in module `\design_ice'. 1898s Removed a total of 0 cells. 1898s 1898s 2.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 1898s Running muxtree optimizer on module \design_ice.. 1898s Creating internal representation of mux trees. 1898s Evaluating internal representation of mux trees. 1898s Replacing known input bits on port B of cell $procmux$431: \ready -> 1'1 1898s Analyzing evaluation results. 1898s Removed 0 multiplexer ports. 1898s 1898s 1898s 2.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 1898s Optimizing cells in module \design_ice. 1898s Optimizing cells in module \design_ice. 1898s Performed a total of 1 changes. 1898s 1898s 2.10.5. Executing OPT_MERGE pass (detect identical cells). 1898s Finding identical cells in module `\design_ice'. 1898s Removed a total of 0 cells. 1898s 1898s 2.10.6. Executing OPT_DFF pass (perform DFF optimizations). 1898s 1898s 2.10.7. Executing OPT_CLEAN pass (remove unused cells and wires). 1898s Finding unused cells or wires in module \design_ice.. 1898s Removed 0 unused cells and 1 unused wires. 1898s 1898s 1898s 2.10.8. Executing OPT_EXPR pass (perform const folding). 1898s Optimizing module design_ice. 1898s 1898s 2.10.9. Rerunning OPT passes. (Maybe there is more to do..) 1898s 1898s 2.10.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 1898s Running muxtree optimizer on module \design_ice.. 1898s Creating internal representation of mux trees. 1898s Evaluating internal representation of mux trees. 1898s Analyzing evaluation results. 1898s Removed 0 multiplexer ports. 1898s 1898s 1898s 2.10.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 1898s Optimizing cells in module \design_ice. 1898s Performed a total of 0 changes. 1898s 1898s 2.10.12. Executing OPT_MERGE pass (detect identical cells). 1898s Finding identical cells in module `\design_ice'. 1898s Removed a total of 0 cells. 1898s 1898s 2.10.13. Executing OPT_DFF pass (perform DFF optimizations). 1898s 1898s 2.10.14. Executing OPT_CLEAN pass (remove unused cells and wires). 1898s Finding unused cells or wires in module \design_ice.. 1898s 1898s 2.10.15. Executing OPT_EXPR pass (perform const folding). 1898s Optimizing module design_ice. 1898s 1898s 2.10.16. Finished OPT passes. (There is nothing left to do.) 1898s 1898s 2.11. Executing FSM pass (extract and optimize FSM). 1898s 1898s 2.11.1. Executing FSM_DETECT pass (finding FSMs in design). 1898s 1898s 2.11.2. Executing FSM_EXTRACT pass (extracting FSM from design). 1898s 1898s 2.11.3. Executing FSM_OPT pass (simple optimizations of FSMs). 1898s 1898s 2.11.4. Executing OPT_CLEAN pass (remove unused cells and wires). 1898s Finding unused cells or wires in module \design_ice.. 1898s 1898s 2.11.5. Executing FSM_OPT pass (simple optimizations of FSMs). 1898s 1898s 2.11.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 1898s 1898s 2.11.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 1898s 1898s 2.11.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 1898s 1898s 2.12. Executing OPT pass (performing simple optimizations). 1898s 1898s 2.12.1. Executing OPT_EXPR pass (perform const folding). 1898s Optimizing module design_ice. 1898s 1898s 2.12.2. Executing OPT_MERGE pass (detect identical cells). 1898s Finding identical cells in module `\design_ice'. 1898s Removed a total of 0 cells. 1898s 1898s 2.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 1898s Running muxtree optimizer on module \design_ice.. 1898s Creating internal representation of mux trees. 1898s Evaluating internal representation of mux trees. 1898s Analyzing evaluation results. 1898s Removed 0 multiplexer ports. 1898s 1898s 1898s 2.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 1898s Optimizing cells in module \design_ice. 1898s Performed a total of 0 changes. 1898s 1898s 2.12.5. Executing OPT_MERGE pass (detect identical cells). 1898s Finding identical cells in module `\design_ice'. 1898s Removed a total of 0 cells. 1898s 1898s 2.12.6. Executing OPT_DFF pass (perform DFF optimizations). 1898s Adding EN signal on $procdff$454 ($dff) from module design_ice (D = \I1, Q = \value). 1898s 1898s 2.12.7. Executing OPT_CLEAN pass (remove unused cells and wires). 1898s Finding unused cells or wires in module \design_ice.. 1898s Removed 1 unused cells and 1 unused wires. 1898s 1898s 1898s 2.12.8. Executing OPT_EXPR pass (perform const folding). 1898s Optimizing module design_ice. 1898s 1898s 2.12.9. Rerunning OPT passes. (Maybe there is more to do..) 1898s 1898s 2.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 1898s Running muxtree optimizer on module \design_ice.. 1898s Creating internal representation of mux trees. 1898s No muxes found in this module. 1898s Removed 0 multiplexer ports. 1898s 1898s 2.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 1898s Optimizing cells in module \design_ice. 1898s Performed a total of 0 changes. 1898s 1898s 2.12.12. Executing OPT_MERGE pass (detect identical cells). 1898s Finding identical cells in module `\design_ice'. 1898s Removed a total of 0 cells. 1898s 1898s 2.12.13. Executing OPT_DFF pass (perform DFF optimizations). 1898s 1898s 2.12.14. Executing OPT_CLEAN pass (remove unused cells and wires). 1898s Finding unused cells or wires in module \design_ice.. 1898s 1898s 2.12.15. Executing OPT_EXPR pass (perform const folding). 1898s Optimizing module design_ice. 1898s 1898s 2.12.16. Finished OPT passes. (There is nothing left to do.) 1898s 1898s 2.13. Executing WREDUCE pass (reducing word size of cells). 1898s 1898s 2.14. Executing PEEPOPT pass (run peephole optimizers). 1898s 1898s 2.15. Executing OPT_CLEAN pass (remove unused cells and wires). 1898s Finding unused cells or wires in module \design_ice.. 1898s 1898s 2.16. Executing SHARE pass (SAT-based resource sharing). 1898s 1898s 2.17. Executing TECHMAP pass (map to technology primitives). 1898s 1898s 2.17.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v 1898s Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation. 1898s Generating RTLIL representation for module `\_90_lut_cmp_'. 1898s Successfully finished Verilog frontend. 1898s 1898s 2.17.2. Continuing TECHMAP pass. 1898s No more expansions possible. 1898s 1898s 1898s 2.18. Executing OPT_EXPR pass (perform const folding). 1898s Optimizing module design_ice. 1898s 1898s 2.19. Executing OPT_CLEAN pass (remove unused cells and wires). 1898s Finding unused cells or wires in module \design_ice.. 1898s 1898s 2.20. Executing ALUMACC pass (create $alu and $macc cells). 1898s Extracting $alu and $macc cells in module design_ice: 1898s created 0 $alu and 0 $macc cells. 1898s 1898s 2.21. Executing OPT pass (performing simple optimizations). 1898s 1898s 2.21.1. Executing OPT_EXPR pass (perform const folding). 1898s Optimizing module design_ice. 1898s 1898s 2.21.2. Executing OPT_MERGE pass (detect identical cells). 1898s Finding identical cells in module `\design_ice'. 1898s Removed a total of 0 cells. 1898s 1898s 2.21.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 1898s Running muxtree optimizer on module \design_ice.. 1898s Creating internal representation of mux trees. 1898s No muxes found in this module. 1898s Removed 0 multiplexer ports. 1898s 1898s 2.21.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 1898s Optimizing cells in module \design_ice. 1898s Performed a total of 0 changes. 1898s 1898s 2.21.5. Executing OPT_MERGE pass (detect identical cells). 1898s Finding identical cells in module `\design_ice'. 1898s Removed a total of 0 cells. 1898s 1898s 2.21.6. Executing OPT_DFF pass (perform DFF optimizations). 1898s 1898s 2.21.7. Executing OPT_CLEAN pass (remove unused cells and wires). 1898s Finding unused cells or wires in module \design_ice.. 1898s 1898s 2.21.8. Executing OPT_EXPR pass (perform const folding). 1898s Optimizing module design_ice. 1898s 1898s 2.21.9. Finished OPT passes. (There is nothing left to do.) 1898s 1898s 2.22. Executing MEMORY pass. 1898s 1898s 2.22.1. Executing OPT_MEM pass (optimize memories). 1898s Performed a total of 0 transformations. 1898s 1898s 2.22.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). 1898s Performed a total of 0 transformations. 1898s 1898s 2.22.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 1898s 1898s 2.22.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 1898s 1898s 2.22.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 1898s 1898s 2.22.6. Executing OPT_CLEAN pass (remove unused cells and wires). 1898s Finding unused cells or wires in module \design_ice.. 1898s 1898s 2.22.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 1898s 1898s 2.22.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). 1898s Performed a total of 0 transformations. 1898s 1898s 2.22.9. Executing OPT_CLEAN pass (remove unused cells and wires). 1898s Finding unused cells or wires in module \design_ice.. 1898s 1898s 2.22.10. Executing MEMORY_COLLECT pass (generating $mem cells). 1898s 1898s 2.23. Executing OPT_CLEAN pass (remove unused cells and wires). 1898s Finding unused cells or wires in module \design_ice.. 1898s 1898s 2.24. Executing MEMORY_LIBMAP pass (mapping memories to cells). 1898s 1898s 2.25. Executing TECHMAP pass (map to technology primitives). 1898s 1898s 2.25.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v 1899s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation. 1899s Generating RTLIL representation for module `\$__ICE40_RAM4K_'. 1899s Successfully finished Verilog frontend. 1899s 1899s 2.25.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/spram_map.v 1899s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/spram_map.v' to AST representation. 1899s Generating RTLIL representation for module `\$__ICE40_SPRAM_'. 1899s Successfully finished Verilog frontend. 1899s 1899s 2.25.3. Continuing TECHMAP pass. 1899s No more expansions possible. 1899s 1899s 1899s 2.26. Executing ICE40_BRAMINIT pass. 1899s 1899s 2.27. Executing OPT pass (performing simple optimizations). 1899s 1899s 2.27.1. Executing OPT_EXPR pass (perform const folding). 1899s Optimizing module design_ice. 1899s 1899s 2.27.2. Executing OPT_MERGE pass (detect identical cells). 1899s Finding identical cells in module `\design_ice'. 1899s Removed a total of 0 cells. 1899s 1899s 2.27.3. Executing OPT_DFF pass (perform DFF optimizations). 1899s 1899s 2.27.4. Executing OPT_CLEAN pass (remove unused cells and wires). 1899s Finding unused cells or wires in module \design_ice.. 1899s 1899s 2.27.5. Finished fast OPT passes. 1899s 1899s 2.28. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 1899s 1899s 2.29. Executing OPT pass (performing simple optimizations). 1899s 1899s 2.29.1. Executing OPT_EXPR pass (perform const folding). 1899s Optimizing module design_ice. 1899s 1899s 2.29.2. Executing OPT_MERGE pass (detect identical cells). 1899s Finding identical cells in module `\design_ice'. 1899s Removed a total of 0 cells. 1899s 1899s 2.29.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 1899s Running muxtree optimizer on module \design_ice.. 1899s Creating internal representation of mux trees. 1899s No muxes found in this module. 1899s Removed 0 multiplexer ports. 1899s 1899s 2.29.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 1899s Optimizing cells in module \design_ice. 1899s Performed a total of 0 changes. 1899s 1899s 2.29.5. Executing OPT_MERGE pass (detect identical cells). 1899s Finding identical cells in module `\design_ice'. 1899s Removed a total of 0 cells. 1899s 1899s 2.29.6. Executing OPT_DFF pass (perform DFF optimizations). 1899s 1899s 2.29.7. Executing OPT_CLEAN pass (remove unused cells and wires). 1899s Finding unused cells or wires in module \design_ice.. 1899s 1899s 2.29.8. Executing OPT_EXPR pass (perform const folding). 1899s Optimizing module design_ice. 1899s 1899s 2.29.9. Finished OPT passes. (There is nothing left to do.) 1899s 1899s 2.30. Executing ICE40_WRAPCARRY pass (wrap carries). 1899s 1899s 2.31. Executing TECHMAP pass (map to technology primitives). 1899s 1899s 2.31.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v 1899s Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation. 1899s Generating RTLIL representation for module `\_90_simplemap_bool_ops'. 1899s Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. 1899s Generating RTLIL representation for module `\_90_simplemap_logic_ops'. 1899s Generating RTLIL representation for module `\_90_simplemap_compare_ops'. 1899s Generating RTLIL representation for module `\_90_simplemap_various'. 1899s Generating RTLIL representation for module `\_90_simplemap_registers'. 1899s Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. 1899s Generating RTLIL representation for module `\_90_shift_shiftx'. 1899s Generating RTLIL representation for module `\_90_fa'. 1899s Generating RTLIL representation for module `\_90_lcu'. 1899s Generating RTLIL representation for module `\_90_alu'. 1899s Generating RTLIL representation for module `\_90_macc'. 1899s Generating RTLIL representation for module `\_90_alumacc'. 1899s Generating RTLIL representation for module `\$__div_mod_u'. 1899s Generating RTLIL representation for module `\$__div_mod_trunc'. 1899s Generating RTLIL representation for module `\_90_div'. 1899s Generating RTLIL representation for module `\_90_mod'. 1899s Generating RTLIL representation for module `\$__div_mod_floor'. 1899s Generating RTLIL representation for module `\_90_divfloor'. 1899s Generating RTLIL representation for module `\_90_modfloor'. 1899s Generating RTLIL representation for module `\_90_pow'. 1899s Generating RTLIL representation for module `\_90_pmux'. 1899s Generating RTLIL representation for module `\_90_demux'. 1899s Generating RTLIL representation for module `\_90_lut'. 1899s Successfully finished Verilog frontend. 1899s 1899s 2.31.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v 1899s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation. 1899s Generating RTLIL representation for module `\_80_ice40_alu'. 1899s Successfully finished Verilog frontend. 1899s 1899s 2.31.3. Continuing TECHMAP pass. 1899s Using extmapper simplemap for cells of type $dffe. 1899s Using extmapper simplemap for cells of type $dff. 1899s No more expansions possible. 1899s 1899s 1899s 2.32. Executing OPT pass (performing simple optimizations). 1899s 1899s 2.32.1. Executing OPT_EXPR pass (perform const folding). 1899s Optimizing module design_ice. 1899s 1899s 2.32.2. Executing OPT_MERGE pass (detect identical cells). 1899s Finding identical cells in module `\design_ice'. 1899s Removed a total of 0 cells. 1899s 1899s 2.32.3. Executing OPT_DFF pass (perform DFF optimizations). 1899s 1899s 2.32.4. Executing OPT_CLEAN pass (remove unused cells and wires). 1899s Finding unused cells or wires in module \design_ice.. 1899s 1899s 2.32.5. Finished fast OPT passes. 1899s 1899s 2.33. Executing ICE40_OPT pass (performing simple optimizations). 1899s 1899s 2.33.1. Running ICE40 specific optimizations. 1899s 1899s 2.33.2. Executing OPT_EXPR pass (perform const folding). 1899s Optimizing module design_ice. 1899s 1899s 2.33.3. Executing OPT_MERGE pass (detect identical cells). 1899s Finding identical cells in module `\design_ice'. 1899s Removed a total of 0 cells. 1899s 1899s 2.33.4. Executing OPT_DFF pass (perform DFF optimizations). 1899s 1899s 2.33.5. Executing OPT_CLEAN pass (remove unused cells and wires). 1899s Finding unused cells or wires in module \design_ice.. 1899s 1899s 2.33.6. Finished OPT passes. (There is nothing left to do.) 1899s 1899s 2.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 1899s 1899s 2.35. Executing TECHMAP pass (map to technology primitives). 1899s 1899s 2.35.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 1899s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 1899s Generating RTLIL representation for module `\$_DFF_N_'. 1899s Generating RTLIL representation for module `\$_DFF_P_'. 1899s Generating RTLIL representation for module `\$_DFFE_NP_'. 1899s Generating RTLIL representation for module `\$_DFFE_PP_'. 1899s Generating RTLIL representation for module `\$_DFF_NP0_'. 1899s Generating RTLIL representation for module `\$_DFF_NP1_'. 1899s Generating RTLIL representation for module `\$_DFF_PP0_'. 1899s Generating RTLIL representation for module `\$_DFF_PP1_'. 1899s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 1899s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 1899s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 1899s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 1899s Generating RTLIL representation for module `\$_SDFF_NP0_'. 1899s Generating RTLIL representation for module `\$_SDFF_NP1_'. 1899s Generating RTLIL representation for module `\$_SDFF_PP0_'. 1899s Generating RTLIL representation for module `\$_SDFF_PP1_'. 1899s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 1899s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 1899s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 1899s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 1899s Successfully finished Verilog frontend. 1899s 1899s 2.35.2. Continuing TECHMAP pass. 1899s Using template \$_DFF_P_ for cells of type $_DFF_P_. 1899s Using template \$_DFFE_PP_ for cells of type $_DFFE_PP_. 1899s No more expansions possible. 1899s 1899s 1899s 2.36. Executing OPT_EXPR pass (perform const folding). 1899s Optimizing module design_ice. 1899s 1899s 2.37. Executing SIMPLEMAP pass (map simple cells to gate primitives). 1899s 1899s 2.38. Executing ICE40_OPT pass (performing simple optimizations). 1899s 1899s 2.38.1. Running ICE40 specific optimizations. 1899s 1899s 2.38.2. Executing OPT_EXPR pass (perform const folding). 1899s Optimizing module design_ice. 1899s 1899s 2.38.3. Executing OPT_MERGE pass (detect identical cells). 1899s Finding identical cells in module `\design_ice'. 1899s Removed a total of 0 cells. 1899s 1899s 2.38.4. Executing OPT_DFF pass (perform DFF optimizations). 1899s 1899s 2.38.5. Executing OPT_CLEAN pass (remove unused cells and wires). 1899s Finding unused cells or wires in module \design_ice.. 1899s Removed 0 unused cells and 9 unused wires. 1899s 1899s 1899s 2.38.6. Rerunning OPT passes. (Removed registers in this run.) 1899s 1899s 2.38.7. Running ICE40 specific optimizations. 1899s 1899s 2.38.8. Executing OPT_EXPR pass (perform const folding). 1899s Optimizing module design_ice. 1899s 1899s 2.38.9. Executing OPT_MERGE pass (detect identical cells). 1899s Finding identical cells in module `\design_ice'. 1899s Removed a total of 0 cells. 1899s 1899s 2.38.10. Executing OPT_DFF pass (perform DFF optimizations). 1899s 1899s 2.38.11. Executing OPT_CLEAN pass (remove unused cells and wires). 1899s Finding unused cells or wires in module \design_ice.. 1899s 1899s 2.38.12. Finished OPT passes. (There is nothing left to do.) 1899s 1899s 2.39. Executing TECHMAP pass (map to technology primitives). 1899s 1899s 2.39.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v 1899s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation. 1899s Generating RTLIL representation for module `\$_DLATCH_N_'. 1899s Generating RTLIL representation for module `\$_DLATCH_P_'. 1899s Successfully finished Verilog frontend. 1899s 1899s 2.39.2. Continuing TECHMAP pass. 1899s No more expansions possible. 1899s 1899s 1899s 2.40. Executing ABC pass (technology mapping using ABC). 1899s 1899s 2.40.1. Extracting gate netlist of module `\design_ice' to `/input.blif'.. 1899s Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs. 1899s Don't call ABC as there is nothing to map. 1899s Removing temp directory. 1899s 1899s 2.41. Executing ICE40_WRAPCARRY pass (wrap carries). 1899s 1899s 2.42. Executing TECHMAP pass (map to technology primitives). 1899s 1899s 2.42.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 1899s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 1899s Generating RTLIL representation for module `\$_DFF_N_'. 1899s Generating RTLIL representation for module `\$_DFF_P_'. 1899s Generating RTLIL representation for module `\$_DFFE_NP_'. 1899s Generating RTLIL representation for module `\$_DFFE_PP_'. 1899s Generating RTLIL representation for module `\$_DFF_NP0_'. 1899s Generating RTLIL representation for module `\$_DFF_NP1_'. 1899s Generating RTLIL representation for module `\$_DFF_PP0_'. 1899s Generating RTLIL representation for module `\$_DFF_PP1_'. 1899s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 1899s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 1899s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 1899s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 1899s Generating RTLIL representation for module `\$_SDFF_NP0_'. 1899s Generating RTLIL representation for module `\$_SDFF_NP1_'. 1899s Generating RTLIL representation for module `\$_SDFF_PP0_'. 1899s Generating RTLIL representation for module `\$_SDFF_PP1_'. 1899s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 1899s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 1899s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 1899s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 1899s Successfully finished Verilog frontend. 1899s 1899s 2.42.2. Continuing TECHMAP pass. 1899s No more expansions possible. 1899s 1899s 1899s 2.43. Executing OPT_LUT pass (optimize LUTs). 1899s Discovering LUTs. 1899s Number of LUTs: 0 1899s with \SB_CARRY (#0) 0 1899s with \SB_CARRY (#1) 0 1899s 1899s Eliminating LUTs. 1899s Number of LUTs: 0 1899s with \SB_CARRY (#0) 0 1899s with \SB_CARRY (#1) 0 1899s 1899s Combining LUTs. 1899s Number of LUTs: 0 1899s with \SB_CARRY (#0) 0 1899s with \SB_CARRY (#1) 0 1899s 1899s Eliminated 0 LUTs. 1899s Combined 0 LUTs. 1899s 1899s 2.44. Executing TECHMAP pass (map to technology primitives). 1899s 1899s 2.44.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v 1899s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation. 1899s Generating RTLIL representation for module `\$lut'. 1899s Successfully finished Verilog frontend. 1899s 1899s 2.44.2. Continuing TECHMAP pass. 1899s No more expansions possible. 1899s 1899s 1899s 2.45. Executing AUTONAME pass. 1899s Renamed 2 objects in module design_ice (2 iterations). 1899s 1899s 1899s 2.46. Executing HIERARCHY pass (managing design hierarchy). 1899s 1899s 2.46.1. Analyzing design hierarchy.. 1899s Top module: \design_ice 1899s 1899s 2.46.2. Analyzing design hierarchy.. 1899s Top module: \design_ice 1899s Removed 0 unused modules. 1899s 1899s 2.47. Printing statistics. 1899s 1899s === design_ice === 1899s 1899s Number of wires: 5 1899s Number of wire bits: 5 1899s Number of public wires: 5 1899s Number of public wire bits: 5 1899s Number of memories: 0 1899s Number of memory bits: 0 1899s Number of processes: 0 1899s Number of cells: 2 1899s SB_DFF 1 1899s SB_DFFE 1 1899s 1899s 2.48. Executing CHECK pass (checking for obvious problems). 1899s Checking module design_ice... 1899s Found and reported 0 problems. 1899s 1899s 2.49. Executing BLIF backend. 1899s 1899s End of script. Logfile hash: aa87fc59fc, CPU: user 0.55s system 0.01s, MEM: 19.90 MB peak 1899s Yosys 0.33 (git sha1 2584903a060) 1899s Time spent: 72% 13x read_verilog (0 sec), 7% 1x synth_ice40 (0 sec), ... 1899s autopkgtest [00:26:22]: test ice: -----------------------] 1900s autopkgtest [00:26:23]: test ice: - - - - - - - - - - results - - - - - - - - - - 1900s ice PASS 1900s autopkgtest [00:26:23]: test smtbc: preparing testbed 1901s Reading package lists... 1901s Building dependency tree... 1901s Reading state information... 1901s Starting pkgProblemResolver with broken count: 0 1901s Starting 2 pkgProblemResolver with broken count: 0 1901s Done 1902s 0 upgraded, 0 newly installed, 0 to remove and 0 not upgraded. 1902s autopkgtest [00:26:25]: test smtbc: [----------------------- 1903s autopkgtest [00:26:26]: test smtbc: -----------------------] 1903s autopkgtest [00:26:26]: test smtbc: - - - - - - - - - - results - - - - - - - - - - 1903s smtbc PASS 1904s autopkgtest [00:26:27]: @@@@@@@@@@@@@@@@@@@@ summary 1904s yosys-testsuite PASS 1904s ice PASS 1904s smtbc PASS 1922s nova [W] Skipping flock for amd64 1922s Creating nova instance adt-plucky-amd64-yosys-20250315-235443-juju-7f2275-prod-proposed-migration-environment-2-6475d2f7-471d-4373-ae33-3e58b1c59995 from image adt/ubuntu-plucky-amd64-server-20250304.img (UUID 9c7d4da5-d95f-4c85-ac1f-51eb37e75c4c)... 1922s nova [W] Timed out waiting for a0c03ba0-7be5-4632-876c-3479cdaf792b to get deleted. 1922s nova [W] Skipping flock for amd64 1922s Creating nova instance adt-plucky-amd64-yosys-20250315-235443-juju-7f2275-prod-proposed-migration-environment-2-6475d2f7-471d-4373-ae33-3e58b1c59995 from image adt/ubuntu-plucky-amd64-server-20250304.img (UUID 9c7d4da5-d95f-4c85-ac1f-51eb37e75c4c)... 1922s nova [W] Timed out waiting for b8ee969e-9d1a-445b-90d2-aa19215b15f7 to get deleted.