0s autopkgtest [21:07:27]: starting date and time: 2024-03-19 21:07:27+0000 0s autopkgtest [21:07:27]: git checkout: 4a1cd702 l/adt_testbed: don't blame the testbed for unsolvable build deps 0s autopkgtest [21:07:27]: host juju-7f2275-prod-proposed-migration-environment-2; command line: /home/ubuntu/autopkgtest/runner/autopkgtest --output-dir /tmp/autopkgtest-work.kr49u2ra/out --timeout-copy=6000 --setup-commands /home/ubuntu/autopkgtest-cloud/worker-config-production/setup-canonical.sh --apt-pocket=proposed=src:yosys,src:readline,src:yosys-plugin-ghdl --apt-upgrade yosys --timeout-short=300 --timeout-copy=20000 --timeout-build=20000 '--env=ADT_TEST_TRIGGERS=yosys/0.33-5build1 readline/8.2-3.1 yosys-plugin-ghdl/0.0~git20230419.5b64ccf-1' -- ssh -s /home/ubuntu/autopkgtest/ssh-setup/nova -- --flavor autopkgtest --security-groups autopkgtest-juju-7f2275-prod-proposed-migration-environment-2@bos02-ppc64el-12.secgroup --name adt-noble-ppc64el-yosys-20240319-210727-juju-7f2275-prod-proposed-migration-environment-2 --image adt/ubuntu-noble-ppc64el-server --keyname testbed-juju-7f2275-prod-proposed-migration-environment-2 --net-id=net_prod-proposed-migration -e TERM=linux -e ''"'"'http_proxy=http://squid.internal:3128'"'"'' -e ''"'"'https_proxy=http://squid.internal:3128'"'"'' -e ''"'"'no_proxy=127.0.0.1,127.0.1.1,login.ubuntu.com,localhost,localdomain,novalocal,internal,archive.ubuntu.com,ports.ubuntu.com,security.ubuntu.com,ddebs.ubuntu.com,changelogs.ubuntu.com,launchpadlibrarian.net,launchpadcontent.net,launchpad.net,10.24.0.0/24,keystone.ps5.canonical.com,objectstorage.prodstack5.canonical.com'"'"'' --mirror=http://ftpmaster.internal/ubuntu/ 99s autopkgtest [21:09:06]: testbed dpkg architecture: ppc64el 99s autopkgtest [21:09:06]: testbed apt version: 2.7.12 99s autopkgtest [21:09:06]: @@@@@@@@@@@@@@@@@@@@ test bed setup 100s Get:1 http://ftpmaster.internal/ubuntu noble-proposed InRelease [117 kB] 101s Get:2 http://ftpmaster.internal/ubuntu noble-proposed/main Sources [493 kB] 101s Get:3 http://ftpmaster.internal/ubuntu noble-proposed/multiverse Sources [52.7 kB] 101s Get:4 http://ftpmaster.internal/ubuntu noble-proposed/restricted Sources [6540 B] 101s Get:5 http://ftpmaster.internal/ubuntu noble-proposed/universe Sources [3757 kB] 102s Get:6 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el Packages [649 kB] 102s Get:7 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el c-n-f Metadata [3116 B] 102s Get:8 http://ftpmaster.internal/ubuntu noble-proposed/restricted ppc64el Packages [1372 B] 102s Get:9 http://ftpmaster.internal/ubuntu noble-proposed/restricted ppc64el c-n-f Metadata [116 B] 102s Get:10 http://ftpmaster.internal/ubuntu noble-proposed/universe ppc64el Packages [4110 kB] 102s Get:11 http://ftpmaster.internal/ubuntu noble-proposed/universe ppc64el c-n-f Metadata [8652 B] 102s Get:12 http://ftpmaster.internal/ubuntu noble-proposed/multiverse ppc64el Packages [47.7 kB] 102s Get:13 http://ftpmaster.internal/ubuntu noble-proposed/multiverse ppc64el c-n-f Metadata [116 B] 105s Fetched 9246 kB in 3s (2922 kB/s) 105s Reading package lists... 108s Reading package lists... 108s Building dependency tree... 108s Reading state information... 108s Calculating upgrade... 109s The following packages will be upgraded: 109s readline-common ubuntu-minimal ubuntu-standard 109s 3 upgraded, 0 newly installed, 0 to remove and 0 not upgraded. 109s Need to get 77.9 kB of archives. 109s After this operation, 0 B of additional disk space will be used. 109s Get:1 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el readline-common all 8.2-3.1 [56.4 kB] 109s Get:2 http://ftpmaster.internal/ubuntu noble/main ppc64el ubuntu-minimal ppc64el 1.536build1 [10.7 kB] 109s Get:3 http://ftpmaster.internal/ubuntu noble/main ppc64el ubuntu-standard ppc64el 1.536build1 [10.7 kB] 109s Fetched 77.9 kB in 0s (192 kB/s) 109s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 70095 files and directories currently installed.) 109s Preparing to unpack .../readline-common_8.2-3.1_all.deb ... 109s Unpacking readline-common (8.2-3.1) over (8.2-3) ... 109s Preparing to unpack .../ubuntu-minimal_1.536build1_ppc64el.deb ... 109s Unpacking ubuntu-minimal (1.536build1) over (1.536) ... 109s Preparing to unpack .../ubuntu-standard_1.536build1_ppc64el.deb ... 109s Unpacking ubuntu-standard (1.536build1) over (1.536) ... 109s Setting up ubuntu-minimal (1.536build1) ... 109s Setting up ubuntu-standard (1.536build1) ... 109s Setting up readline-common (8.2-3.1) ... 109s Processing triggers for install-info (7.1-3) ... 109s Processing triggers for man-db (2.12.0-3) ... 110s Reading package lists... 110s Building dependency tree... 110s Reading state information... 110s 0 upgraded, 0 newly installed, 0 to remove and 0 not upgraded. 110s Hit:1 http://ftpmaster.internal/ubuntu noble-proposed InRelease 111s Hit:2 http://ftpmaster.internal/ubuntu noble InRelease 111s Hit:3 http://ftpmaster.internal/ubuntu noble-updates InRelease 111s Hit:4 http://ftpmaster.internal/ubuntu noble-security InRelease 112s Reading package lists... 112s Reading package lists... 112s Building dependency tree... 112s Reading state information... 112s Calculating upgrade... 112s 0 upgraded, 0 newly installed, 0 to remove and 0 not upgraded. 112s Reading package lists... 113s Building dependency tree... 113s Reading state information... 113s 0 upgraded, 0 newly installed, 0 to remove and 0 not upgraded. 116s autopkgtest [21:09:23]: testbed running kernel: Linux 6.8.0-11-generic #11-Ubuntu SMP Wed Feb 14 00:33:03 UTC 2024 116s autopkgtest [21:09:23]: @@@@@@@@@@@@@@@@@@@@ apt-source yosys 123s Get:1 http://ftpmaster.internal/ubuntu noble-proposed/universe yosys 0.33-5build1 (dsc) [2990 B] 123s Get:2 http://ftpmaster.internal/ubuntu noble-proposed/universe yosys 0.33-5build1 (tar) [6161 kB] 123s Get:3 http://ftpmaster.internal/ubuntu noble-proposed/universe yosys 0.33-5build1 (tar) [2586 kB] 123s Get:4 http://ftpmaster.internal/ubuntu noble-proposed/universe yosys 0.33-5build1 (diff) [30.2 kB] 123s gpgv: Signature made Fri Mar 15 18:03:30 2024 UTC 123s gpgv: using RSA key 568BF22A66337CBFC9A6B9B72C83DBC8E9BD0E37 123s gpgv: Can't check signature: No public key 123s dpkg-source: warning: cannot verify inline signature for ./yosys_0.33-5build1.dsc: no acceptable signature found 124s autopkgtest [21:09:31]: testing package yosys version 0.33-5build1 124s autopkgtest [21:09:31]: build not needed 149s autopkgtest [21:09:56]: test yosys-testsuite: preparing testbed 151s Reading package lists... 151s Building dependency tree... 151s Reading state information... 151s Starting pkgProblemResolver with broken count: 0 151s Starting 2 pkgProblemResolver with broken count: 0 151s Done 151s The following additional packages will be installed: 151s cpp cpp-13 cpp-13-powerpc64le-linux-gnu cpp-powerpc64le-linux-gnu g++ g++-13 151s g++-13-powerpc64le-linux-gnu g++-powerpc64le-linux-gnu gcc gcc-13 151s gcc-13-powerpc64le-linux-gnu gcc-powerpc64le-linux-gnu iverilog libasan8 151s libatomic1 libc-dev-bin libc6-dev libcc1-0 libcrypt-dev libffi-dev 151s libgcc-13-dev libgomp1 libisl23 libitm1 liblsan0 libmpc3 libncurses-dev 151s libnsl-dev libpkgconf3 libquadmath0 libreadline-dev libreadline8t64 151s libstdc++-13-dev libtcl8.6 libtirpc-dev libtsan2 libubsan1 linux-libc-dev 151s pkg-config pkgconf pkgconf-bin python3-click python3-colorama rpcsvc-proto 151s tcl tcl-dev tcl8.6 tcl8.6-dev yosys yosys-abc yosys-dev zlib1g-dev 151s Suggested packages: 151s cpp-doc gcc-13-locales cpp-13-doc gcc-13-doc gcc-multilib manpages-dev 151s autoconf automake libtool flex bison gdb gcc-doc gdb-powerpc64le-linux-gnu 151s gtkwave glibc-doc ncurses-doc readline-doc libstdc++-13-doc tcl-doc 151s tcl-tclreadline tcl8.6-doc 151s Recommended packages: 151s manpages manpages-dev libc-devtools xdot 152s The following packages will be REMOVED: 152s libreadline8 152s The following NEW packages will be installed: 152s autopkgtest-satdep cpp cpp-13 cpp-13-powerpc64le-linux-gnu 152s cpp-powerpc64le-linux-gnu g++ g++-13 g++-13-powerpc64le-linux-gnu 152s g++-powerpc64le-linux-gnu gcc gcc-13 gcc-13-powerpc64le-linux-gnu 152s gcc-powerpc64le-linux-gnu iverilog libasan8 libatomic1 libc-dev-bin 152s libc6-dev libcc1-0 libcrypt-dev libffi-dev libgcc-13-dev libgomp1 libisl23 152s libitm1 liblsan0 libmpc3 libncurses-dev libnsl-dev libpkgconf3 libquadmath0 152s libreadline-dev libreadline8t64 libstdc++-13-dev libtcl8.6 libtirpc-dev 152s libtsan2 libubsan1 linux-libc-dev pkg-config pkgconf pkgconf-bin 152s python3-click python3-colorama rpcsvc-proto tcl tcl-dev tcl8.6 tcl8.6-dev 152s yosys yosys-abc yosys-dev zlib1g-dev 152s 0 upgraded, 53 newly installed, 1 to remove and 0 not upgraded. 152s Need to get 79.8 MB/79.8 MB of archives. 152s After this operation, 304 MB of additional disk space will be used. 152s Get:1 /tmp/autopkgtest.l2kRn3/1-autopkgtest-satdep.deb autopkgtest-satdep ppc64el 0 [740 B] 152s Get:2 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libreadline8t64 ppc64el 8.2-3.1 [182 kB] 152s Get:3 http://ftpmaster.internal/ubuntu noble/main ppc64el libisl23 ppc64el 0.26-3 [864 kB] 152s Get:4 http://ftpmaster.internal/ubuntu noble/main ppc64el libmpc3 ppc64el 1.3.1-1 [61.2 kB] 153s Get:5 http://ftpmaster.internal/ubuntu noble/main ppc64el cpp-13-powerpc64le-linux-gnu ppc64el 13.2.0-17ubuntu2 [10.7 MB] 155s Get:6 http://ftpmaster.internal/ubuntu noble/main ppc64el cpp-13 ppc64el 13.2.0-17ubuntu2 [1038 B] 155s Get:7 http://ftpmaster.internal/ubuntu noble/main ppc64el cpp-powerpc64le-linux-gnu ppc64el 4:13.2.0-7ubuntu1 [5330 B] 155s Get:8 http://ftpmaster.internal/ubuntu noble/main ppc64el cpp ppc64el 4:13.2.0-7ubuntu1 [22.5 kB] 155s Get:9 http://ftpmaster.internal/ubuntu noble/main ppc64el libcc1-0 ppc64el 14-20240303-1ubuntu1 [48.1 kB] 155s Get:10 http://ftpmaster.internal/ubuntu noble/main ppc64el libgomp1 ppc64el 14-20240303-1ubuntu1 [161 kB] 155s Get:11 http://ftpmaster.internal/ubuntu noble/main ppc64el libitm1 ppc64el 14-20240303-1ubuntu1 [32.4 kB] 155s Get:12 http://ftpmaster.internal/ubuntu noble/main ppc64el libatomic1 ppc64el 14-20240303-1ubuntu1 [10.7 kB] 155s Get:13 http://ftpmaster.internal/ubuntu noble/main ppc64el libasan8 ppc64el 14-20240303-1ubuntu1 [2973 kB] 156s Get:14 http://ftpmaster.internal/ubuntu noble/main ppc64el liblsan0 ppc64el 14-20240303-1ubuntu1 [1325 kB] 156s Get:15 http://ftpmaster.internal/ubuntu noble/main ppc64el libtsan2 ppc64el 14-20240303-1ubuntu1 [2734 kB] 156s Get:16 http://ftpmaster.internal/ubuntu noble/main ppc64el libubsan1 ppc64el 14-20240303-1ubuntu1 [1194 kB] 157s Get:17 http://ftpmaster.internal/ubuntu noble/main ppc64el libquadmath0 ppc64el 14-20240303-1ubuntu1 [158 kB] 157s Get:18 http://ftpmaster.internal/ubuntu noble/main ppc64el libgcc-13-dev ppc64el 13.2.0-17ubuntu2 [1581 kB] 157s Get:19 http://ftpmaster.internal/ubuntu noble/main ppc64el gcc-13-powerpc64le-linux-gnu ppc64el 13.2.0-17ubuntu2 [20.6 MB] 161s Get:20 http://ftpmaster.internal/ubuntu noble/main ppc64el gcc-13 ppc64el 13.2.0-17ubuntu2 [477 kB] 161s Get:21 http://ftpmaster.internal/ubuntu noble/main ppc64el gcc-powerpc64le-linux-gnu ppc64el 4:13.2.0-7ubuntu1 [1224 B] 161s Get:22 http://ftpmaster.internal/ubuntu noble/main ppc64el gcc ppc64el 4:13.2.0-7ubuntu1 [5022 B] 161s Get:23 http://ftpmaster.internal/ubuntu noble/main ppc64el libc-dev-bin ppc64el 2.39-0ubuntu2 [21.3 kB] 161s Get:24 http://ftpmaster.internal/ubuntu noble/main ppc64el linux-libc-dev ppc64el 6.8.0-11.11 [1585 kB] 161s Get:25 http://ftpmaster.internal/ubuntu noble/main ppc64el libcrypt-dev ppc64el 1:4.4.36-4 [167 kB] 161s Get:26 http://ftpmaster.internal/ubuntu noble/main ppc64el libtirpc-dev ppc64el 1.3.4+ds-1build1 [262 kB] 161s Get:27 http://ftpmaster.internal/ubuntu noble/main ppc64el libnsl-dev ppc64el 1.3.0-3 [79.2 kB] 161s Get:28 http://ftpmaster.internal/ubuntu noble/main ppc64el rpcsvc-proto ppc64el 1.4.2-0ubuntu6 [82.3 kB] 161s Get:29 http://ftpmaster.internal/ubuntu noble/main ppc64el libc6-dev ppc64el 2.39-0ubuntu2 [2102 kB] 162s Get:30 http://ftpmaster.internal/ubuntu noble/main ppc64el libstdc++-13-dev ppc64el 13.2.0-17ubuntu2 [2445 kB] 162s Get:31 http://ftpmaster.internal/ubuntu noble/main ppc64el g++-13-powerpc64le-linux-gnu ppc64el 13.2.0-17ubuntu2 [12.2 MB] 166s Get:32 http://ftpmaster.internal/ubuntu noble/main ppc64el g++-13 ppc64el 13.2.0-17ubuntu2 [14.5 kB] 166s Get:33 http://ftpmaster.internal/ubuntu noble/main ppc64el g++-powerpc64le-linux-gnu ppc64el 4:13.2.0-7ubuntu1 [968 B] 166s Get:34 http://ftpmaster.internal/ubuntu noble/main ppc64el g++ ppc64el 4:13.2.0-7ubuntu1 [1086 B] 166s Get:35 http://ftpmaster.internal/ubuntu noble/universe ppc64el iverilog ppc64el 12.0-2 [2378 kB] 167s Get:36 http://ftpmaster.internal/ubuntu noble/main ppc64el libncurses-dev ppc64el 6.4+20240113-1ubuntu1 [485 kB] 167s Get:37 http://ftpmaster.internal/ubuntu noble/main ppc64el libpkgconf3 ppc64el 1.8.1-2 [36.9 kB] 167s Get:38 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libreadline-dev ppc64el 8.2-3.1 [230 kB] 167s Get:39 http://ftpmaster.internal/ubuntu noble/main ppc64el libtcl8.6 ppc64el 8.6.13+dfsg-2 [1179 kB] 168s Get:40 http://ftpmaster.internal/ubuntu noble/main ppc64el pkgconf-bin ppc64el 1.8.1-2 [22.0 kB] 168s Get:41 http://ftpmaster.internal/ubuntu noble/main ppc64el pkgconf ppc64el 1.8.1-2 [16.7 kB] 168s Get:42 http://ftpmaster.internal/ubuntu noble/main ppc64el pkg-config ppc64el 1.8.1-2 [7170 B] 168s Get:43 http://ftpmaster.internal/ubuntu noble/main ppc64el python3-colorama all 0.4.6-4 [32.1 kB] 168s Get:44 http://ftpmaster.internal/ubuntu noble/main ppc64el python3-click all 8.1.6-1 [79.0 kB] 168s Get:45 http://ftpmaster.internal/ubuntu noble/main ppc64el tcl8.6 ppc64el 8.6.13+dfsg-2 [14.8 kB] 168s Get:46 http://ftpmaster.internal/ubuntu noble/main ppc64el tcl ppc64el 8.6.13 [3994 B] 168s Get:47 http://ftpmaster.internal/ubuntu noble/main ppc64el zlib1g-dev ppc64el 1:1.3.dfsg-3ubuntu1 [902 kB] 168s Get:48 http://ftpmaster.internal/ubuntu noble/main ppc64el tcl8.6-dev ppc64el 8.6.13+dfsg-2 [1202 kB] 168s Get:49 http://ftpmaster.internal/ubuntu noble/main ppc64el tcl-dev ppc64el 8.6.13 [5750 B] 168s Get:50 http://ftpmaster.internal/ubuntu noble-proposed/universe ppc64el yosys-abc ppc64el 0.33-5build1 [7747 kB] 171s Get:51 http://ftpmaster.internal/ubuntu noble-proposed/universe ppc64el yosys ppc64el 0.33-5build1 [3184 kB] 173s Get:52 http://ftpmaster.internal/ubuntu noble/main ppc64el libffi-dev ppc64el 3.4.6-1 [67.4 kB] 173s Get:53 http://ftpmaster.internal/ubuntu noble-proposed/universe ppc64el yosys-dev ppc64el 0.33-5build1 [88.3 kB] 173s Fetched 79.8 MB in 21s (3791 kB/s) 173s dpkg: libreadline8:ppc64el: dependency problems, but removing anyway as you requested: 173s parted depends on libreadline8 (>= 6.0). 173s libpython3.12-stdlib:ppc64el depends on libreadline8 (>= 7.0~beta). 173s libpython3.11-stdlib:ppc64el depends on libreadline8 (>= 7.0~beta). 173s gpgsm depends on libreadline8 (>= 6.0). 173s gpgconf depends on libreadline8 (>= 6.0). 173s gpg depends on libreadline8 (>= 6.0). 173s gawk depends on libreadline8 (>= 6.0). 173s fdisk depends on libreadline8 (>= 6.0). 173s bc depends on libreadline8 (>= 6.0). 173s 173s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 70095 files and directories currently installed.) 173s Removing libreadline8:ppc64el (8.2-3) ... 173s Selecting previously unselected package libreadline8t64:ppc64el. 173s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 70083 files and directories currently installed.) 173s Preparing to unpack .../00-libreadline8t64_8.2-3.1_ppc64el.deb ... 173s Adding 'diversion of /lib/powerpc64le-linux-gnu/libhistory.so.8 to /lib/powerpc64le-linux-gnu/libhistory.so.8.usr-is-merged by libreadline8t64' 173s Adding 'diversion of /lib/powerpc64le-linux-gnu/libhistory.so.8.2 to /lib/powerpc64le-linux-gnu/libhistory.so.8.2.usr-is-merged by libreadline8t64' 173s Adding 'diversion of /lib/powerpc64le-linux-gnu/libreadline.so.8 to /lib/powerpc64le-linux-gnu/libreadline.so.8.usr-is-merged by libreadline8t64' 173s Adding 'diversion of /lib/powerpc64le-linux-gnu/libreadline.so.8.2 to /lib/powerpc64le-linux-gnu/libreadline.so.8.2.usr-is-merged by libreadline8t64' 173s Unpacking libreadline8t64:ppc64el (8.2-3.1) ... 173s Selecting previously unselected package libisl23:ppc64el. 173s Preparing to unpack .../01-libisl23_0.26-3_ppc64el.deb ... 173s Unpacking libisl23:ppc64el (0.26-3) ... 173s Selecting previously unselected package libmpc3:ppc64el. 173s Preparing to unpack .../02-libmpc3_1.3.1-1_ppc64el.deb ... 173s Unpacking libmpc3:ppc64el (1.3.1-1) ... 173s Selecting previously unselected package cpp-13-powerpc64le-linux-gnu. 173s Preparing to unpack .../03-cpp-13-powerpc64le-linux-gnu_13.2.0-17ubuntu2_ppc64el.deb ... 173s Unpacking cpp-13-powerpc64le-linux-gnu (13.2.0-17ubuntu2) ... 173s Selecting previously unselected package cpp-13. 173s Preparing to unpack .../04-cpp-13_13.2.0-17ubuntu2_ppc64el.deb ... 173s Unpacking cpp-13 (13.2.0-17ubuntu2) ... 173s Selecting previously unselected package cpp-powerpc64le-linux-gnu. 173s Preparing to unpack .../05-cpp-powerpc64le-linux-gnu_4%3a13.2.0-7ubuntu1_ppc64el.deb ... 173s Unpacking cpp-powerpc64le-linux-gnu (4:13.2.0-7ubuntu1) ... 173s Selecting previously unselected package cpp. 173s Preparing to unpack .../06-cpp_4%3a13.2.0-7ubuntu1_ppc64el.deb ... 173s Unpacking cpp (4:13.2.0-7ubuntu1) ... 173s Selecting previously unselected package libcc1-0:ppc64el. 173s Preparing to unpack .../07-libcc1-0_14-20240303-1ubuntu1_ppc64el.deb ... 173s Unpacking libcc1-0:ppc64el (14-20240303-1ubuntu1) ... 173s Selecting previously unselected package libgomp1:ppc64el. 173s Preparing to unpack .../08-libgomp1_14-20240303-1ubuntu1_ppc64el.deb ... 173s Unpacking libgomp1:ppc64el (14-20240303-1ubuntu1) ... 173s Selecting previously unselected package libitm1:ppc64el. 173s Preparing to unpack .../09-libitm1_14-20240303-1ubuntu1_ppc64el.deb ... 173s Unpacking libitm1:ppc64el (14-20240303-1ubuntu1) ... 173s Selecting previously unselected package libatomic1:ppc64el. 173s Preparing to unpack .../10-libatomic1_14-20240303-1ubuntu1_ppc64el.deb ... 173s Unpacking libatomic1:ppc64el (14-20240303-1ubuntu1) ... 173s Selecting previously unselected package libasan8:ppc64el. 173s Preparing to unpack .../11-libasan8_14-20240303-1ubuntu1_ppc64el.deb ... 173s Unpacking libasan8:ppc64el (14-20240303-1ubuntu1) ... 173s Selecting previously unselected package liblsan0:ppc64el. 173s Preparing to unpack .../12-liblsan0_14-20240303-1ubuntu1_ppc64el.deb ... 173s Unpacking liblsan0:ppc64el (14-20240303-1ubuntu1) ... 174s Selecting previously unselected package libtsan2:ppc64el. 174s Preparing to unpack .../13-libtsan2_14-20240303-1ubuntu1_ppc64el.deb ... 174s Unpacking libtsan2:ppc64el (14-20240303-1ubuntu1) ... 174s Selecting previously unselected package libubsan1:ppc64el. 174s Preparing to unpack .../14-libubsan1_14-20240303-1ubuntu1_ppc64el.deb ... 174s Unpacking libubsan1:ppc64el (14-20240303-1ubuntu1) ... 174s Selecting previously unselected package libquadmath0:ppc64el. 174s Preparing to unpack .../15-libquadmath0_14-20240303-1ubuntu1_ppc64el.deb ... 174s Unpacking libquadmath0:ppc64el (14-20240303-1ubuntu1) ... 174s Selecting previously unselected package libgcc-13-dev:ppc64el. 174s Preparing to unpack .../16-libgcc-13-dev_13.2.0-17ubuntu2_ppc64el.deb ... 174s Unpacking libgcc-13-dev:ppc64el (13.2.0-17ubuntu2) ... 174s Selecting previously unselected package gcc-13-powerpc64le-linux-gnu. 174s Preparing to unpack .../17-gcc-13-powerpc64le-linux-gnu_13.2.0-17ubuntu2_ppc64el.deb ... 174s Unpacking gcc-13-powerpc64le-linux-gnu (13.2.0-17ubuntu2) ... 174s Selecting previously unselected package gcc-13. 174s Preparing to unpack .../18-gcc-13_13.2.0-17ubuntu2_ppc64el.deb ... 174s Unpacking gcc-13 (13.2.0-17ubuntu2) ... 174s Selecting previously unselected package gcc-powerpc64le-linux-gnu. 174s Preparing to unpack .../19-gcc-powerpc64le-linux-gnu_4%3a13.2.0-7ubuntu1_ppc64el.deb ... 174s Unpacking gcc-powerpc64le-linux-gnu (4:13.2.0-7ubuntu1) ... 174s Selecting previously unselected package gcc. 174s Preparing to unpack .../20-gcc_4%3a13.2.0-7ubuntu1_ppc64el.deb ... 174s Unpacking gcc (4:13.2.0-7ubuntu1) ... 174s Selecting previously unselected package libc-dev-bin. 174s Preparing to unpack .../21-libc-dev-bin_2.39-0ubuntu2_ppc64el.deb ... 174s Unpacking libc-dev-bin (2.39-0ubuntu2) ... 174s Selecting previously unselected package linux-libc-dev:ppc64el. 174s Preparing to unpack .../22-linux-libc-dev_6.8.0-11.11_ppc64el.deb ... 174s Unpacking linux-libc-dev:ppc64el (6.8.0-11.11) ... 174s Selecting previously unselected package libcrypt-dev:ppc64el. 174s Preparing to unpack .../23-libcrypt-dev_1%3a4.4.36-4_ppc64el.deb ... 174s Unpacking libcrypt-dev:ppc64el (1:4.4.36-4) ... 175s Selecting previously unselected package libtirpc-dev:ppc64el. 175s Preparing to unpack .../24-libtirpc-dev_1.3.4+ds-1build1_ppc64el.deb ... 175s Unpacking libtirpc-dev:ppc64el (1.3.4+ds-1build1) ... 175s Selecting previously unselected package libnsl-dev:ppc64el. 175s Preparing to unpack .../25-libnsl-dev_1.3.0-3_ppc64el.deb ... 175s Unpacking libnsl-dev:ppc64el (1.3.0-3) ... 175s Selecting previously unselected package rpcsvc-proto. 175s Preparing to unpack .../26-rpcsvc-proto_1.4.2-0ubuntu6_ppc64el.deb ... 175s Unpacking rpcsvc-proto (1.4.2-0ubuntu6) ... 175s Selecting previously unselected package libc6-dev:ppc64el. 175s Preparing to unpack .../27-libc6-dev_2.39-0ubuntu2_ppc64el.deb ... 175s Unpacking libc6-dev:ppc64el (2.39-0ubuntu2) ... 175s Selecting previously unselected package libstdc++-13-dev:ppc64el. 175s Preparing to unpack .../28-libstdc++-13-dev_13.2.0-17ubuntu2_ppc64el.deb ... 175s Unpacking libstdc++-13-dev:ppc64el (13.2.0-17ubuntu2) ... 175s Selecting previously unselected package g++-13-powerpc64le-linux-gnu. 175s Preparing to unpack .../29-g++-13-powerpc64le-linux-gnu_13.2.0-17ubuntu2_ppc64el.deb ... 175s Unpacking g++-13-powerpc64le-linux-gnu (13.2.0-17ubuntu2) ... 175s Selecting previously unselected package g++-13. 175s Preparing to unpack .../30-g++-13_13.2.0-17ubuntu2_ppc64el.deb ... 175s Unpacking g++-13 (13.2.0-17ubuntu2) ... 175s Selecting previously unselected package g++-powerpc64le-linux-gnu. 175s Preparing to unpack .../31-g++-powerpc64le-linux-gnu_4%3a13.2.0-7ubuntu1_ppc64el.deb ... 175s Unpacking g++-powerpc64le-linux-gnu (4:13.2.0-7ubuntu1) ... 175s Selecting previously unselected package g++. 175s Preparing to unpack .../32-g++_4%3a13.2.0-7ubuntu1_ppc64el.deb ... 175s Unpacking g++ (4:13.2.0-7ubuntu1) ... 175s Selecting previously unselected package iverilog. 175s Preparing to unpack .../33-iverilog_12.0-2_ppc64el.deb ... 175s Unpacking iverilog (12.0-2) ... 175s Selecting previously unselected package libncurses-dev:ppc64el. 175s Preparing to unpack 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pkgconf:ppc64el (1.8.1-2) ... 176s Selecting previously unselected package pkg-config:ppc64el. 176s Preparing to unpack .../40-pkg-config_1.8.1-2_ppc64el.deb ... 176s Unpacking pkg-config:ppc64el (1.8.1-2) ... 176s Selecting previously unselected package python3-colorama. 176s Preparing to unpack .../41-python3-colorama_0.4.6-4_all.deb ... 176s Unpacking python3-colorama (0.4.6-4) ... 176s Selecting previously unselected package python3-click. 176s Preparing to unpack .../42-python3-click_8.1.6-1_all.deb ... 176s Unpacking python3-click (8.1.6-1) ... 176s Selecting previously unselected package tcl8.6. 176s Preparing to unpack .../43-tcl8.6_8.6.13+dfsg-2_ppc64el.deb ... 176s Unpacking tcl8.6 (8.6.13+dfsg-2) ... 176s Selecting previously unselected package tcl. 176s Preparing to unpack .../44-tcl_8.6.13_ppc64el.deb ... 176s Unpacking tcl (8.6.13) ... 176s Selecting previously unselected package zlib1g-dev:ppc64el. 176s Preparing to unpack .../45-zlib1g-dev_1%3a1.3.dfsg-3ubuntu1_ppc64el.deb ... 176s Unpacking zlib1g-dev:ppc64el (1:1.3.dfsg-3ubuntu1) ... 176s Selecting previously unselected package tcl8.6-dev:ppc64el. 176s Preparing to unpack .../46-tcl8.6-dev_8.6.13+dfsg-2_ppc64el.deb ... 176s Unpacking tcl8.6-dev:ppc64el (8.6.13+dfsg-2) ... 176s Selecting previously unselected package tcl-dev:ppc64el. 176s Preparing to unpack .../47-tcl-dev_8.6.13_ppc64el.deb ... 176s Unpacking tcl-dev:ppc64el (8.6.13) ... 176s Selecting previously unselected package yosys-abc. 176s Preparing to unpack .../48-yosys-abc_0.33-5build1_ppc64el.deb ... 176s Unpacking yosys-abc (0.33-5build1) ... 176s Selecting previously unselected package yosys. 176s Preparing to unpack .../49-yosys_0.33-5build1_ppc64el.deb ... 176s Unpacking yosys (0.33-5build1) ... 176s Selecting previously unselected package libffi-dev:ppc64el. 176s Preparing to unpack .../50-libffi-dev_3.4.6-1_ppc64el.deb ... 176s Unpacking libffi-dev:ppc64el (3.4.6-1) ... 176s Selecting previously unselected package yosys-dev. 176s Preparing to unpack .../51-yosys-dev_0.33-5build1_ppc64el.deb ... 176s Unpacking yosys-dev (0.33-5build1) ... 176s Selecting previously unselected package autopkgtest-satdep. 176s Preparing to unpack .../52-1-autopkgtest-satdep.deb ... 176s Unpacking autopkgtest-satdep (0) ... 176s Setting up python3-colorama (0.4.6-4) ... 176s Setting up linux-libc-dev:ppc64el (6.8.0-11.11) ... 176s Setting up libgomp1:ppc64el (14-20240303-1ubuntu1) ... 176s Setting up python3-click (8.1.6-1) ... 176s Setting up libffi-dev:ppc64el (3.4.6-1) ... 176s Setting up libtirpc-dev:ppc64el (1.3.4+ds-1build1) ... 176s Setting up libpkgconf3:ppc64el (1.8.1-2) ... 176s Setting up rpcsvc-proto (1.4.2-0ubuntu6) ... 176s Setting up libquadmath0:ppc64el (14-20240303-1ubuntu1) ... 176s Setting up libmpc3:ppc64el (1.3.1-1) ... 176s Setting up libatomic1:ppc64el (14-20240303-1ubuntu1) ... 176s Setting up libtcl8.6:ppc64el (8.6.13+dfsg-2) ... 176s Setting up pkgconf-bin (1.8.1-2) ... 176s Setting up libreadline8t64:ppc64el (8.2-3.1) ... 176s Setting up libubsan1:ppc64el (14-20240303-1ubuntu1) ... 176s Setting up libnsl-dev:ppc64el (1.3.0-3) ... 176s Setting up libcrypt-dev:ppc64el (1:4.4.36-4) ... 176s Setting up libasan8:ppc64el (14-20240303-1ubuntu1) ... 176s Setting up libtsan2:ppc64el (14-20240303-1ubuntu1) ... 176s Setting up libisl23:ppc64el (0.26-3) ... 176s Setting up libc-dev-bin (2.39-0ubuntu2) ... 176s Setting up cpp-13-powerpc64le-linux-gnu (13.2.0-17ubuntu2) ... 176s Setting up libcc1-0:ppc64el (14-20240303-1ubuntu1) ... 176s Setting up liblsan0:ppc64el (14-20240303-1ubuntu1) ... 176s Setting up libitm1:ppc64el (14-20240303-1ubuntu1) ... 177s Setting up cpp-powerpc64le-linux-gnu (4:13.2.0-7ubuntu1) ... 177s Setting up tcl8.6 (8.6.13+dfsg-2) ... 177s Setting up cpp-13 (13.2.0-17ubuntu2) ... 177s Setting up yosys-abc (0.33-5build1) ... 177s Setting up pkgconf:ppc64el (1.8.1-2) ... 177s Setting up iverilog (12.0-2) ... 177s Setting up pkg-config:ppc64el (1.8.1-2) ... 177s Setting up libgcc-13-dev:ppc64el (13.2.0-17ubuntu2) ... 177s Setting up cpp (4:13.2.0-7ubuntu1) ... 177s Setting up tcl (8.6.13) ... 177s Setting up libc6-dev:ppc64el (2.39-0ubuntu2) ... 177s Setting up libstdc++-13-dev:ppc64el (13.2.0-17ubuntu2) ... 177s Setting up libncurses-dev:ppc64el (6.4+20240113-1ubuntu1) ... 177s Setting up yosys (0.33-5build1) ... 177s Setting up libreadline-dev:ppc64el (8.2-3.1) ... 177s Setting up gcc-13-powerpc64le-linux-gnu (13.2.0-17ubuntu2) ... 177s Setting up gcc-13 (13.2.0-17ubuntu2) ... 177s Setting up zlib1g-dev:ppc64el (1:1.3.dfsg-3ubuntu1) ... 177s Setting up tcl8.6-dev:ppc64el (8.6.13+dfsg-2) ... 177s Setting up g++-13-powerpc64le-linux-gnu (13.2.0-17ubuntu2) ... 177s Setting up gcc-powerpc64le-linux-gnu (4:13.2.0-7ubuntu1) ... 177s Setting up tcl-dev:ppc64el (8.6.13) ... 177s Setting up yosys-dev (0.33-5build1) ... 177s Setting up g++-powerpc64le-linux-gnu (4:13.2.0-7ubuntu1) ... 177s Setting up g++-13 (13.2.0-17ubuntu2) ... 177s Setting up gcc (4:13.2.0-7ubuntu1) ... 177s Setting up g++ (4:13.2.0-7ubuntu1) ... 177s update-alternatives: using /usr/bin/g++ to provide /usr/bin/c++ (c++) in auto mode 177s Setting up autopkgtest-satdep (0) ... 177s Processing triggers for man-db (2.12.0-3) ... 178s Processing triggers for install-info (7.1-3) ... 178s Processing triggers for libc-bin (2.39-0ubuntu2) ... 181s (Reading database ... 73967 files and directories currently installed.) 181s Removing autopkgtest-satdep (0) ... 182s autopkgtest [21:10:29]: test yosys-testsuite: [----------------------- 182s + [ 1 -ge 1 ] 182s + testdir=. 182s + shift 182s + mkdir -p . 182s + cd . 182s + ln -sf /usr/bin/yosys . 182s + ln -sf /usr/bin/yosys-abc . 182s + ln -sf /usr/bin/yosys-config . 182s + sed -i s/^test:.*/test: $(EXTRA_TARGETS)/ Makefile 182s + make test CONFIG=gcc ABCPULL=0 182s mkdir -p share/include/kernel/ 182s cp "./"/kernel/yosys.h share/include/kernel/yosys.h 182s mkdir -p share/include/kernel/ 182s cp "./"/kernel/hashlib.h share/include/kernel/hashlib.h 182s mkdir -p share/include/kernel/ 182s cp "./"/kernel/log.h share/include/kernel/log.h 182s mkdir -p share/include/kernel/ 182s cp "./"/kernel/rtlil.h share/include/kernel/rtlil.h 182s mkdir -p share/include/kernel/ 182s cp "./"/kernel/binding.h share/include/kernel/binding.h 182s mkdir -p share/include/kernel/ 182s cp "./"/kernel/register.h share/include/kernel/register.h 182s mkdir -p share/include/kernel/ 182s cp "./"/kernel/cellaigs.h share/include/kernel/cellaigs.h 182s mkdir -p share/include/kernel/ 182s cp "./"/kernel/celltypes.h share/include/kernel/celltypes.h 182s mkdir -p share/include/kernel/ 182s cp "./"/kernel/celledges.h share/include/kernel/celledges.h 182s mkdir -p share/include/kernel/ 182s cp "./"/kernel/consteval.h share/include/kernel/consteval.h 182s mkdir -p share/include/kernel/ 182s cp "./"/kernel/constids.inc share/include/kernel/constids.inc 182s mkdir -p share/include/kernel/ 182s cp "./"/kernel/sigtools.h share/include/kernel/sigtools.h 182s mkdir -p share/include/kernel/ 182s cp "./"/kernel/modtools.h share/include/kernel/modtools.h 182s mkdir -p share/include/kernel/ 182s cp "./"/kernel/macc.h share/include/kernel/macc.h 182s mkdir -p share/include/kernel/ 182s cp "./"/kernel/utils.h share/include/kernel/utils.h 182s mkdir -p share/include/kernel/ 182s cp "./"/kernel/satgen.h share/include/kernel/satgen.h 182s mkdir -p share/include/kernel/ 182s cp "./"/kernel/qcsat.h share/include/kernel/qcsat.h 182s mkdir -p share/include/kernel/ 182s cp "./"/kernel/ff.h share/include/kernel/ff.h 182s mkdir -p share/include/kernel/ 182s cp "./"/kernel/ffinit.h share/include/kernel/ffinit.h 182s mkdir -p share/include/kernel/ 182s cp "./"/kernel/fstdata.h share/include/kernel/fstdata.h 182s mkdir -p share/include/kernel/ 182s cp "./"/kernel/mem.h share/include/kernel/mem.h 182s mkdir -p share/include/kernel/ 182s cp "./"/kernel/yw.h share/include/kernel/yw.h 182s mkdir -p share/include/kernel/ 182s cp "./"/kernel/json.h share/include/kernel/json.h 182s mkdir -p share/include/libs/ezsat/ 182s cp "./"/libs/ezsat/ezsat.h share/include/libs/ezsat/ezsat.h 182s mkdir -p share/include/libs/ezsat/ 182s cp "./"/libs/ezsat/ezminisat.h share/include/libs/ezsat/ezminisat.h 182s mkdir -p share/include/libs/fst/ 182s cp "./"/libs/fst/fstapi.h share/include/libs/fst/fstapi.h 182s mkdir -p share/include/libs/sha1/ 182s cp "./"/libs/sha1/sha1.h share/include/libs/sha1/sha1.h 182s mkdir -p share/include/libs/json11/ 182s cp "./"/libs/json11/json11.hpp share/include/libs/json11/json11.hpp 182s mkdir -p share/include/passes/fsm/ 182s cp "./"/passes/fsm/fsmdata.h share/include/passes/fsm/fsmdata.h 182s mkdir -p share/include/frontends/ast/ 182s cp "./"/frontends/ast/ast.h share/include/frontends/ast/ast.h 182s mkdir -p share/include/frontends/ast/ 182s cp "./"/frontends/ast/ast_binding.h share/include/frontends/ast/ast_binding.h 182s mkdir -p share/include/frontends/blif/ 182s cp "./"/frontends/blif/blifparse.h share/include/frontends/blif/blifparse.h 182s mkdir -p share/include/backends/rtlil/ 182s cp "./"/backends/rtlil/rtlil_backend.h share/include/backends/rtlil/rtlil_backend.h 182s mkdir -p share/include/backends/cxxrtl/ 182s cp "./"/backends/cxxrtl/cxxrtl.h share/include/backends/cxxrtl/cxxrtl.h 182s mkdir -p share/include/backends/cxxrtl/ 182s cp "./"/backends/cxxrtl/cxxrtl_vcd.h share/include/backends/cxxrtl/cxxrtl_vcd.h 182s mkdir -p share/include/backends/cxxrtl/ 182s cp "./"/backends/cxxrtl/cxxrtl_capi.cc share/include/backends/cxxrtl/cxxrtl_capi.cc 182s mkdir -p share/include/backends/cxxrtl/ 182s cp "./"/backends/cxxrtl/cxxrtl_capi.h share/include/backends/cxxrtl/cxxrtl_capi.h 182s mkdir -p share/include/backends/cxxrtl/ 182s cp "./"/backends/cxxrtl/cxxrtl_vcd_capi.cc share/include/backends/cxxrtl/cxxrtl_vcd_capi.cc 182s mkdir -p share/include/backends/cxxrtl/ 182s cp "./"/backends/cxxrtl/cxxrtl_vcd_capi.h share/include/backends/cxxrtl/cxxrtl_vcd_capi.h 182s mkdir -p share/python3 182s cp "./"/backends/smt2/smtio.py share/python3/smtio.py 182s mkdir -p share/python3 182s cp "./"/backends/smt2/ywio.py share/python3/ywio.py 182s mkdir -p share/achronix/speedster22i/ 182s cp "./"/techlibs/achronix/speedster22i/cells_sim.v share/achronix/speedster22i/cells_sim.v 182s mkdir -p share/achronix/speedster22i/ 182s cp "./"/techlibs/achronix/speedster22i/cells_map.v share/achronix/speedster22i/cells_map.v 182s mkdir -p share/anlogic 182s cp "./"/techlibs/anlogic/cells_map.v share/anlogic/cells_map.v 182s mkdir -p share/anlogic 182s cp "./"/techlibs/anlogic/arith_map.v share/anlogic/arith_map.v 182s mkdir -p share/anlogic 182s cp "./"/techlibs/anlogic/cells_sim.v share/anlogic/cells_sim.v 182s mkdir -p share/anlogic 182s cp "./"/techlibs/anlogic/eagle_bb.v share/anlogic/eagle_bb.v 182s mkdir -p share/anlogic 182s cp "./"/techlibs/anlogic/lutrams.txt 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mkdir -p share 182s cp "./"/techlibs/common/cells.lib share/cells.lib 182s mkdir -p share 182s cp "./"/techlibs/common/mul2dsp.v share/mul2dsp.v 182s mkdir -p share 182s cp "./"/techlibs/common/abc9_model.v share/abc9_model.v 182s mkdir -p share 182s cp "./"/techlibs/common/abc9_map.v share/abc9_map.v 182s mkdir -p share 182s cp "./"/techlibs/common/abc9_unmap.v share/abc9_unmap.v 182s mkdir -p share 182s cp "./"/techlibs/common/cmp2lcu.v share/cmp2lcu.v 182s mkdir -p share/coolrunner2 182s cp "./"/techlibs/coolrunner2/cells_latch.v share/coolrunner2/cells_latch.v 182s mkdir -p share/coolrunner2 182s cp "./"/techlibs/coolrunner2/cells_sim.v share/coolrunner2/cells_sim.v 182s mkdir -p share/coolrunner2 182s cp "./"/techlibs/coolrunner2/cells_counter_map.v share/coolrunner2/cells_counter_map.v 182s mkdir -p share/coolrunner2 182s cp "./"/techlibs/coolrunner2/tff_extract.v share/coolrunner2/tff_extract.v 182s mkdir -p share/coolrunner2 182s cp "./"/techlibs/coolrunner2/xc2_dff.lib share/coolrunner2/xc2_dff.lib 182s mkdir -p share/ecp5 182s cp "./"/techlibs/ecp5/cells_ff.vh share/ecp5/cells_ff.vh 182s mkdir -p share/ecp5 182s cp "./"/techlibs/ecp5/cells_io.vh share/ecp5/cells_io.vh 182s mkdir -p share/ecp5 182s cp "./"/techlibs/ecp5/cells_map.v share/ecp5/cells_map.v 182s mkdir -p share/ecp5 182s cp "./"/techlibs/ecp5/cells_sim.v share/ecp5/cells_sim.v 182s mkdir -p share/ecp5 182s cp "./"/techlibs/ecp5/cells_bb.v share/ecp5/cells_bb.v 182s mkdir -p share/ecp5 182s cp "./"/techlibs/ecp5/lutrams_map.v share/ecp5/lutrams_map.v 182s mkdir -p share/ecp5 182s cp "./"/techlibs/ecp5/lutrams.txt share/ecp5/lutrams.txt 182s mkdir -p share/ecp5 182s cp "./"/techlibs/ecp5/brams_map.v share/ecp5/brams_map.v 182s mkdir -p share/ecp5 182s cp "./"/techlibs/ecp5/brams.txt share/ecp5/brams.txt 182s mkdir -p share/ecp5 182s cp "./"/techlibs/ecp5/arith_map.v share/ecp5/arith_map.v 182s mkdir -p share/ecp5 182s cp "./"/techlibs/ecp5/latches_map.v share/ecp5/latches_map.v 182s mkdir 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share/fabulous/ff_map.v 182s mkdir -p share/fabulous 182s cp "./"/techlibs/fabulous/ram_regfile.txt share/fabulous/ram_regfile.txt 182s mkdir -p share/fabulous 182s cp "./"/techlibs/fabulous/regfile_map.v share/fabulous/regfile_map.v 182s mkdir -p share/fabulous 182s cp "./"/techlibs/fabulous/io_map.v share/fabulous/io_map.v 182s mkdir -p share/fabulous 182s cp "./"/techlibs/fabulous/arith_map.v share/fabulous/arith_map.v 182s mkdir -p share/gatemate 182s cp "./"/techlibs/gatemate/reg_map.v share/gatemate/reg_map.v 182s mkdir -p share/gatemate 182s cp "./"/techlibs/gatemate/mux_map.v share/gatemate/mux_map.v 182s mkdir -p share/gatemate 182s cp "./"/techlibs/gatemate/lut_map.v share/gatemate/lut_map.v 182s mkdir -p share/gatemate 182s cp "./"/techlibs/gatemate/mul_map.v share/gatemate/mul_map.v 182s mkdir -p share/gatemate 182s cp "./"/techlibs/gatemate/arith_map.v share/gatemate/arith_map.v 182s mkdir -p share/gatemate 182s cp "./"/techlibs/gatemate/cells_sim.v share/gatemate/cells_sim.v 182s mkdir -p share/gatemate 182s cp "./"/techlibs/gatemate/cells_bb.v share/gatemate/cells_bb.v 182s mkdir -p share/gatemate 182s cp "./"/techlibs/gatemate/brams_map.v share/gatemate/brams_map.v 182s mkdir -p share/gatemate 182s cp "./"/techlibs/gatemate/brams.txt share/gatemate/brams.txt 182s mkdir -p share/gatemate 182s cp "./"/techlibs/gatemate/brams_init_20.vh share/gatemate/brams_init_20.vh 182s mkdir -p share/gatemate 182s cp "./"/techlibs/gatemate/brams_init_40.vh share/gatemate/brams_init_40.vh 182s mkdir -p share/gatemate 182s cp "./"/techlibs/gatemate/inv_map.v share/gatemate/inv_map.v 182s mkdir -p techlibs/gatemate 182s python3 techlibs/gatemate/make_lut_tree_lib.py 182s touch techlibs/gatemate/lut_tree_lib.mk 182s mkdir -p share/gatemate 182s cp techlibs/gatemate/lut_tree_cells.genlib share/gatemate/lut_tree_cells.genlib 182s mkdir -p share/gatemate 182s cp techlibs/gatemate/lut_tree_map.v share/gatemate/lut_tree_map.v 182s mkdir -p share/gowin 182s cp "./"/techlibs/gowin/cells_map.v share/gowin/cells_map.v 182s mkdir -p share/gowin 182s cp "./"/techlibs/gowin/cells_sim.v share/gowin/cells_sim.v 182s mkdir -p share/gowin 182s cp "./"/techlibs/gowin/cells_xtra.v share/gowin/cells_xtra.v 182s mkdir -p share/gowin 182s cp "./"/techlibs/gowin/arith_map.v share/gowin/arith_map.v 182s mkdir -p share/gowin 182s cp "./"/techlibs/gowin/brams_map.v share/gowin/brams_map.v 182s mkdir -p share/gowin 182s cp "./"/techlibs/gowin/brams.txt share/gowin/brams.txt 182s mkdir -p share/gowin 182s cp "./"/techlibs/gowin/lutrams_map.v share/gowin/lutrams_map.v 182s mkdir -p share/gowin 182s cp "./"/techlibs/gowin/lutrams.txt share/gowin/lutrams.txt 182s mkdir -p share/greenpak4 182s cp "./"/techlibs/greenpak4/cells_blackbox.v share/greenpak4/cells_blackbox.v 182s mkdir -p share/greenpak4 182s cp "./"/techlibs/greenpak4/cells_latch.v share/greenpak4/cells_latch.v 182s mkdir -p share/greenpak4 182s cp "./"/techlibs/greenpak4/cells_map.v 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share/xilinx 183s cp "./"/techlibs/xilinx/brams_xc3sda.txt share/xilinx/brams_xc3sda.txt 183s mkdir -p share/xilinx 183s cp "./"/techlibs/xilinx/brams_xc3sda_map.v share/xilinx/brams_xc3sda_map.v 183s mkdir -p share/xilinx 183s cp "./"/techlibs/xilinx/brams_xc4v.txt share/xilinx/brams_xc4v.txt 183s mkdir -p share/xilinx 183s cp "./"/techlibs/xilinx/brams_xc4v_map.v share/xilinx/brams_xc4v_map.v 183s mkdir -p share/xilinx 183s cp "./"/techlibs/xilinx/brams_xc5v_map.v share/xilinx/brams_xc5v_map.v 183s mkdir -p share/xilinx 183s cp "./"/techlibs/xilinx/brams_xc6v_map.v share/xilinx/brams_xc6v_map.v 183s mkdir -p share/xilinx 183s cp "./"/techlibs/xilinx/brams_xcu_map.v share/xilinx/brams_xcu_map.v 183s mkdir -p share/xilinx 183s cp "./"/techlibs/xilinx/urams.txt share/xilinx/urams.txt 183s mkdir -p share/xilinx 183s cp "./"/techlibs/xilinx/urams_map.v share/xilinx/urams_map.v 183s mkdir -p share/xilinx 183s cp "./"/techlibs/xilinx/arith_map.v share/xilinx/arith_map.v 183s mkdir -p share/xilinx 183s cp "./"/techlibs/xilinx/ff_map.v share/xilinx/ff_map.v 183s mkdir -p share/xilinx 183s cp "./"/techlibs/xilinx/lut_map.v share/xilinx/lut_map.v 183s mkdir -p share/xilinx 183s cp "./"/techlibs/xilinx/mux_map.v share/xilinx/mux_map.v 183s mkdir -p share/xilinx 183s cp "./"/techlibs/xilinx/xc3s_mult_map.v share/xilinx/xc3s_mult_map.v 183s mkdir -p share/xilinx 183s cp "./"/techlibs/xilinx/xc3sda_dsp_map.v share/xilinx/xc3sda_dsp_map.v 183s mkdir -p share/xilinx 183s cp "./"/techlibs/xilinx/xc6s_dsp_map.v share/xilinx/xc6s_dsp_map.v 183s mkdir -p share/xilinx 183s cp "./"/techlibs/xilinx/xc4v_dsp_map.v share/xilinx/xc4v_dsp_map.v 183s mkdir -p share/xilinx 183s cp "./"/techlibs/xilinx/xc5v_dsp_map.v share/xilinx/xc5v_dsp_map.v 183s mkdir -p share/xilinx 183s cp "./"/techlibs/xilinx/xc7_dsp_map.v share/xilinx/xc7_dsp_map.v 183s mkdir -p share/xilinx 183s cp "./"/techlibs/xilinx/xcu_dsp_map.v share/xilinx/xcu_dsp_map.v 183s mkdir -p share/xilinx 183s cp "./"/techlibs/xilinx/abc9_model.v share/xilinx/abc9_model.v 183s cd tests/simple && bash run-test.sh "" 183s make[1]: Entering directory '/tmp/autopkgtest.l2kRn3/build.e8a/src/tests/simple' 183s + gcc -Wall -o /tmp/autopkgtest.l2kRn3/build.e8a/src/tests/tools/cmp_tbdata /tmp/autopkgtest.l2kRn3/build.e8a/src/tests/tools/cmp_tbdata.c 183s Test: arrays02 -> ok 186s Test: asgn_binop -> ok 186s Test: case_expr_extend -> ok 186s Test: case_expr_query -> ok 187s Test: defvalue -> ok 187s Test: implicit_ports -> ok 187s Test: lesser_size_cast -> ok 188s Test: local_loop_var -> ok 188s Test: macro_arg_spaces -> ok 189s Test: matching_end_labels -> ok 189s Test: memwr_port_connection -> ok 189s Test: unnamed_block_decl -> ok 189s Test: aes_kexp128 -> ok 190s Test: always01 -> ok 190s Test: always02 -> ok 191s Test: always03 -> ok 191s Test: arraycells -> ok 191s Test: arrays01 -> ok 192s Test: attrib01_module -> ok 192s Test: attrib02_port_decl -> ok 193s Test: attrib03_parameter -> ok 193s Test: attrib04_net_var -> ok 194s Test: attrib06_operator_suffix -> ok 194s Test: attrib08_mod_inst -> ok 195s Test: attrib09_case -> ok 195s Test: carryadd -> ok 195s Test: case_expr_const -> ok 196s Test: case_expr_non_const -> ok 206s Test: case_large -> ok 206s Test: const_branch_finish -> ok 207s Test: const_fold_func -> ok 208s Test: const_func_shadow -> ok 210s Test: constmuldivmod -> ok 211s Test: constpower -> ok 212s Test: dff_different_styles -> ok 213s Test: dff_init -> ok 215s Test: dynslice -> ok 216s Test: fiedler-cooley -> ok 216s Test: forgen01 -> ok 217s Test: forgen02 -> ok 217s Test: forloops -> ok 218s Test: fsm -> ok 219s Test: func_block -> ok 219s Test: func_recurse -> ok 220s Test: func_width_scope -> ok 220s Test: genblk_collide -> ok 220s Test: genblk_dive -> ok 220s Test: genblk_order -> ok 220s Test: genblk_port_shadow -> ok 224s Test: generate -> ok 224s Test: graphtest -> ok 224s Test: hierarchy -> ok 225s Test: hierdefparam -> ok 226s Test: i2c_master_tests -> ok 226s Test: ifdef_1 -> ok 226s Test: ifdef_2 -> ok 226s Test: localparam_attr -> ok 227s Test: loop_prefix_case -> ok 227s Test: loop_var_shadow -> ok 228s Test: loops -> ok 228s Test: macro_arg_surrounding_spaces -> ok 228s Test: macros -> ok 230s Test: mem2reg -> ok 230s Test: mem2reg_bounds_tern -> ok 232s Test: mem_arst -> ok 240s Test: memory -> ok 241s Test: module_scope -> ok 241s Test: module_scope_case -> ok 241s Test: module_scope_func -> ok 242s Test: multiplier -> ok 243s Test: muxtree -> ok 243s Test: named_genblk -> ok 244s Test: nested_genblk_resolve -> ok 244s Test: omsp_dbg_uart -> ok 250s Test: operators -> ok 250s Test: param_attr -> ok 251s Test: paramods -> ok 256s Test: partsel -> ok 257s Test: process -> ok 258s Test: realexpr -> ok 259s Test: repwhile -> ok 259s Test: retime -> ok 265s Test: rotate -> ok 266s Test: scopes -> ok 266s Test: signed_full_slice -> ok 267s Test: signedexpr -> ok 269s Test: sincos -> ok 269s Test: specify -> ok 269s Test: string_format -> ok 270s Test: subbytes -> ok 271s Test: task_func -> ok 271s Test: undef_eqx_nex -> ok 272s Test: usb_phy_tests -> ok 272s Test: values -> ok 273s Test: verilog_primitives -> ok 274s Test: vloghammer -> ok 275s Test: wandwor -> ok 276s Test: wreduce -> ok 276s make[1]: Leaving directory '/tmp/autopkgtest.l2kRn3/build.e8a/src/tests/simple' 276s cd tests/simple_abc9 && bash run-test.sh "" 276s ls: cannot access '*.sv': No such file or directory 276s make[1]: Entering directory '/tmp/autopkgtest.l2kRn3/build.e8a/src/tests/simple_abc9' 279s Test: abc9 -> ok 279s Test: aes_kexp128 -> ok 279s Test: always01 -> ok 279s Test: always02 -> ok 280s Test: always03 -> ok 280s Test: arraycells -> ok 280s Test: arrays01 -> ok 280s Test: attrib01_module -> ok 281s Test: attrib02_port_decl -> ok 281s Test: attrib03_parameter -> ok 281s Test: attrib04_net_var -> ok 282s Test: attrib06_operator_suffix -> ok 282s Test: attrib08_mod_inst -> ok 282s Test: attrib09_case -> ok 283s Test: carryadd -> ok 283s Test: case_expr_const -> ok 283s Test: case_expr_non_const -> ok 300s Test: case_large -> ok 300s Test: const_branch_finish -> ok 300s Test: const_fold_func -> ok 301s Test: const_func_shadow -> ok 304s Test: constmuldivmod -> ok 304s Test: constpower -> ok 305s Test: dff_different_styles -> ok 305s Test: dff_init -> ok 313s Test: dynslice -> ok 313s Test: fiedler-cooley -> ok 314s Test: forgen01 -> ok 314s Test: forgen02 -> ok 314s Test: forloops -> ok 315s Test: fsm -> ok 315s Test: func_block -> ok 315s Test: func_recurse -> ok 316s Test: func_width_scope -> ok 316s Test: genblk_collide -> ok 316s Test: genblk_dive -> ok 316s Test: genblk_order -> ok 316s Test: genblk_port_shadow -> ok 319s Test: generate -> ok 319s Test: graphtest -> ok 319s Test: hierarchy -> ok 320s Test: hierdefparam -> ok 320s Test: i2c_master_tests -> ok 320s Test: ifdef_1 -> ok 321s Test: ifdef_2 -> ok 321s Test: localparam_attr -> ok 321s Test: loop_prefix_case -> ok 321s Test: loop_var_shadow -> ok 322s Test: loops -> ok 322s Test: macro_arg_surrounding_spaces -> ok 322s Test: macros -> ok 323s Test: mem2reg -> ok 324s Test: mem2reg_bounds_tern -> ok 324s Test: mem_arst -> ok 328s Test: memory -> ok 329s Test: module_scope -> ok 329s Test: module_scope_case -> ok 329s Test: module_scope_func -> ok 330s Test: multiplier -> ok 330s Test: muxtree -> ok 331s Test: named_genblk -> ok 331s Test: nested_genblk_resolve -> ok 331s Test: omsp_dbg_uart -> ok 337s Test: operators -> ok 338s Test: param_attr -> ok 338s Test: paramods -> ok 344s Test: partsel -> ok 345s Test: process -> ok 345s Test: realexpr -> ok 346s Test: repwhile -> ok 346s Test: retime -> ok 348s Test: rotate -> ok 349s Test: scopes -> ok 349s Test: signed_full_slice -> ok 349s Test: signedexpr -> ok 352s Test: sincos -> ok 352s Test: string_format -> ok 353s Test: subbytes -> ok 354s Test: task_func -> ok 354s Test: undef_eqx_nex -> ok 354s Test: usb_phy_tests -> ok 354s Test: values -> ok 355s Test: verilog_primitives -> ok 355s Test: vloghammer -> ok 356s Test: wandwor -> ok 357s Test: wreduce -> ok 358s Test: arrays02 -> ok 359s Test: asgn_binop -> ok 360s Test: case_expr_extend -> ok 360s Test: case_expr_query -> ok 360s Test: defvalue -> ok 361s Test: implicit_ports -> ok 361s Test: lesser_size_cast -> ok 361s Test: local_loop_var -> ok 362s Test: macro_arg_spaces -> ok 362s Test: matching_end_labels -> ok 363s Test: memwr_port_connection -> ok 363s Test: unnamed_block_decl -> ok 363s make[1]: Leaving directory '/tmp/autopkgtest.l2kRn3/build.e8a/src/tests/simple_abc9' 363s cd tests/hana && bash run-test.sh "" 363s make[1]: Entering directory '/tmp/autopkgtest.l2kRn3/build.e8a/src/tests/hana' 367s Test: test_intermout -> ok 368s Test: test_parse2synthtrans -> ok 369s Test: test_parser -> ok 370s Test: test_simulation_always -> ok 371s Test: test_simulation_and -> ok 371s Test: test_simulation_buffer -> ok 372s Test: test_simulation_decoder -> ok 373s Test: test_simulation_inc -> ok 374s Test: test_simulation_mux -> ok 375s Test: test_simulation_nand -> ok 375s Test: test_simulation_nor -> ok 376s Test: test_simulation_or -> ok 376s Test: test_simulation_seq -> ok 379s Test: test_simulation_shifter -> ok 380s Test: test_simulation_sop -> ok 382s Test: test_simulation_techmap -> ok 384s Test: test_simulation_techmap_tech -> ok 385s Test: test_simulation_vlib -> ok 385s Test: test_simulation_xnor -> ok 386s Test: test_simulation_xor -> ok 386s make[1]: Leaving directory '/tmp/autopkgtest.l2kRn3/build.e8a/src/tests/hana' 386s cd tests/asicworld && bash run-test.sh "" 386s make[1]: Entering directory '/tmp/autopkgtest.l2kRn3/build.e8a/src/tests/asicworld' 386s Test: code_hdl_models_GrayCounter -> ok 386s Test: code_hdl_models_arbiter -> ok 397s Test: code_hdl_models_cam -> ok 397s Test: code_hdl_models_clk_div -> ok 397s Test: code_hdl_models_clk_div_45 -> ok 398s Test: code_hdl_models_d_ff_gates -> ok 398s Test: code_hdl_models_d_latch_gates -> ok 398s Test: code_hdl_models_decoder_2to4_gates -> ok 399s Test: code_hdl_models_decoder_using_assign -> ok 399s Test: code_hdl_models_decoder_using_case -> ok 399s Test: code_hdl_models_dff_async_reset -> ok 399s Test: code_hdl_models_dff_sync_reset -> ok 400s Test: code_hdl_models_encoder_4to2_gates -> ok 400s Test: code_hdl_models_encoder_using_case -> ok 401s Test: code_hdl_models_encoder_using_if -> ok 401s Test: code_hdl_models_full_adder_gates -> ok 401s Test: code_hdl_models_full_subtracter_gates -> ok 402s Test: code_hdl_models_gray_counter -> ok 402s Test: code_hdl_models_half_adder_gates -> ok 402s Test: code_hdl_models_lfsr -> ok 403s Test: code_hdl_models_lfsr_updown -> ok 403s Test: code_hdl_models_mux_2to1_gates -> ok 403s Test: code_hdl_models_mux_using_assign -> ok 404s Test: code_hdl_models_mux_using_case -> ok 404s Test: code_hdl_models_mux_using_if -> ok 404s Test: code_hdl_models_one_hot_cnt -> ok 405s Test: code_hdl_models_parallel_crc -> ok 405s Test: code_hdl_models_parity_using_assign -> ok 405s Test: code_hdl_models_parity_using_bitwise -> ok 405s Test: code_hdl_models_parity_using_function -> ok 406s Test: code_hdl_models_pri_encoder_using_assign -> ok 406s Test: code_hdl_models_rom_using_case -> ok 407s Test: code_hdl_models_serial_crc -> ok 407s Test: code_hdl_models_tff_async_reset -> ok 407s Test: code_hdl_models_tff_sync_reset -> ok 409s Test: code_hdl_models_uart -> ok 409s Test: code_hdl_models_up_counter -> ok 410s Test: code_hdl_models_up_counter_load -> ok 410s Test: code_hdl_models_up_down_counter -> ok 411s Test: code_specman_switch_fabric -> ok 411s Test: code_tidbits_asyn_reset -> ok 411s Test: code_tidbits_blocking -> ok 412s Test: code_tidbits_fsm_using_always -> ok 412s Test: code_tidbits_fsm_using_function -> ok 413s Test: code_tidbits_fsm_using_single_always -> ok 413s Test: code_tidbits_nonblocking -> ok 413s Test: code_tidbits_reg_combo_example -> ok 414s Test: code_tidbits_reg_seq_example -> ok 414s Test: code_tidbits_syn_reset -> ok 414s Test: code_tidbits_wire_example -> ok 414s Test: code_verilog_tutorial_addbit -> ok 415s Test: code_verilog_tutorial_always_example -> ok 415s Test: code_verilog_tutorial_bus_con -> ok 415s Test: code_verilog_tutorial_comment -> ok 415s Test: code_verilog_tutorial_counter -> ok 416s Test: code_verilog_tutorial_d_ff -> ok 416s Test: code_verilog_tutorial_decoder -> ok 416s Test: code_verilog_tutorial_decoder_always -> ok 417s Test: code_verilog_tutorial_escape_id -> ok 417s Test: code_verilog_tutorial_explicit -> ok 417s Test: code_verilog_tutorial_first_counter -> ok 417s Test: code_verilog_tutorial_flip_flop -> ok 418s Test: code_verilog_tutorial_fsm_full -> ok 418s Test: code_verilog_tutorial_good_code -> ok 418s Test: code_verilog_tutorial_if_else -> ok 419s Test: code_verilog_tutorial_multiply -> ok 419s Test: code_verilog_tutorial_mux_21 -> ok 419s Test: code_verilog_tutorial_n_out_primitive -> ok 419s Test: code_verilog_tutorial_parallel_if -> ok 420s Test: code_verilog_tutorial_parity -> ok 420s Test: code_verilog_tutorial_simple_function -> ok 420s Test: code_verilog_tutorial_simple_if -> ok 420s Test: code_verilog_tutorial_task_global -> ok 421s Test: code_verilog_tutorial_tri_buf -> ok 421s Test: code_verilog_tutorial_v2k_reg -> ok 421s Test: code_verilog_tutorial_which_clock -> ok 421s make[1]: Leaving directory '/tmp/autopkgtest.l2kRn3/build.e8a/src/tests/asicworld' 421s # +cd tests/realmath && bash run-test.sh "" 421s cd tests/share && bash run-test.sh "" 421s generating tests.. 421s running tests.. 424s [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41][42][43][44][45][46][47][48][49][50][51][52][53][54][55][56][57][58][59][60][61][62][63][64][65][66][67][68][69][70][71][72][73][74][75][76][77][78][79][80][81][82][83][84][85][86][87][88][89][90][91][92][93][94][95][96][97][98][99] 424s cd tests/opt_share && bash run-test.sh "" 424s generating tests.. 424s running tests.. 424s make[1]: Entering directory '/tmp/autopkgtest.l2kRn3/build.e8a/src/tests/opt_share' 600s [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41][42][43][44][45][46][47][48][49][50][51][52][53][54][55][56][57][58][59][60][61][62][63][64][65][66][67][68][69][70][71][72][73][74][75][76][77][78][79][80][81][82][83][84][85][86][87][88][89][90][91][92][93][94][95][96][97][98][99]make[1]: Leaving directory '/tmp/autopkgtest.l2kRn3/build.e8a/src/tests/opt_share' 600s 600s cd tests/fsm && bash run-test.sh "" 600s generating tests.. 600s PRNG seed: 8151564043759631542 600s running tests.. 600s make[1]: Entering directory '/tmp/autopkgtest.l2kRn3/build.e8a/src/tests/fsm' 600s [0]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 600s Users of state reg look like FSM recoding might result in larger circuit. 600s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 601s K[1]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 601s Users of state reg look like FSM recoding might result in larger circuit. 601s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 607s K[2]K[3]K[4]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 607s Users of state reg look like FSM recoding might result in larger circuit. 607s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 608s K[5]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 608s Users of state reg look like FSM recoding might result in larger circuit. 608s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 614s K[6]K[7]K[8]K[9]K[10]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 614s Users of state reg look like FSM recoding might result in larger circuit. 614s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 616s K[11]K[12]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 616s Users of state reg look like FSM recoding might result in larger circuit. 616s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 617s K[13]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 617s Users of state reg look like FSM recoding might result in larger circuit. 617s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 620s K[14]K[15]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 620s Users of state reg look like FSM recoding might result in larger circuit. 620s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 622s K[16]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 622s Users of state reg look like FSM recoding might result in larger circuit. 622s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 624s K[17]K[18]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 624s Users of state reg look like FSM recoding might result in larger circuit. 624s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 626s K[19]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 626s Users of state reg look like FSM recoding might result in larger circuit. 626s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 630s K[20]K[21]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 630s Users of state reg look like FSM recoding might result in larger circuit. 630s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 636s K[22]K[23]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 636s Users of state reg look like FSM recoding might result in larger circuit. 636s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 638s K[24]K[25]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 638s Users of state reg look like FSM recoding might result in larger circuit. 638s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 641s K[26]K[27]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 641s Users of state reg look like FSM recoding might result in larger circuit. 641s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 642s K[28]K[29]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 642s Users of state reg look like FSM recoding might result in larger circuit. 642s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 643s K[30]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 643s Users of state reg look like FSM recoding might result in larger circuit. 643s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 643s K[31]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 643s Users of state reg look like FSM recoding might result in larger circuit. 643s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 645s K[32]K[33]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 645s Users of state reg look like FSM recoding might result in larger circuit. 645s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 659s K[34]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 659s Users of state reg look like FSM recoding might result in larger circuit. 659s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 666s K[35]K[36]K[37]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 666s Users of state reg look like FSM recoding might result in larger circuit. 666s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 668s K[38]K[39]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 668s Users of state reg look like FSM recoding might result in larger circuit. 668s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 679s K[40]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 679s Users of state reg look like FSM recoding might result in larger circuit. 679s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 680s K[41]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 680s Users of state reg look like FSM recoding might result in larger circuit. 680s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 680s K[42]K[43]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 680s Users of state reg look like FSM recoding might result in larger circuit. 680s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 683s K[44]K[45]K[46]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 683s Users of state reg look like FSM recoding might result in larger circuit. 683s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 691s K[47]K[48]K[49]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 692s Users of state reg look like FSM recoding might result in larger circuit. 692s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 692s K 692s make[1]: Leaving directory '/tmp/autopkgtest.l2kRn3/build.e8a/src/tests/fsm' 692s cd tests/techmap && bash run-test.sh 692s make[1]: Entering directory '/tmp/autopkgtest.l2kRn3/build.e8a/src/tests/techmap' 694s Passed abc9.ys 694s Passed adff2dff.ys 694s Warning: wire '\Q' is assigned in a block at < ok 707s Test: firrtl_938 -> ok 708s Test: implicit_en -> ok 711s Test: issue00335 -> ok 712s Test: issue00710 -> ok 713s Test: no_implicit_en -> ok 714s Test: read_arst -> ok 715s Test: read_two_mux -> ok 716s Test: shared_ports -> ok 717s Test: simple_sram_byte_en -> ok 718s Test: trans_addr_enable -> ok 719s Test: trans_sdp -> ok 720s Test: trans_sp -> ok 721s Test: wide_all -> ok 722s Test: wide_read_async -> ok 724s Test: wide_read_mixed -> ok 725s Test: wide_read_sync -> ok 726s Test: wide_read_trans -> ok 727s Test: wide_thru_priority -> ok 728s Test: wide_write -> ok 728s make[1]: Leaving directory '/tmp/autopkgtest.l2kRn3/build.e8a/src/tests/memories' 728s Testing expectations for amber23_sram_byte_en.v .. ok. 729s Testing expectations for implicit_en.v .. ok. 729s Testing expectations for issue00335.v .. ok. 729s Testing expectations for issue00710.v .. ok. 729s Testing expectations for no_implicit_en.v .. ok. 729s Testing expectations for read_arst.v .. ok. 729s Testing expectations for read_two_mux.v .. ok. 729s Testing expectations for shared_ports.v .. ok. 729s Testing expectations for simple_sram_byte_en.v .. ok. 729s Testing expectations for trans_addr_enable.v .. ok. 729s Testing expectations for trans_sdp.v .. ok. 729s Testing expectations for trans_sp.v .. ok. 729s Testing expectations for wide_all.v .. ok. 729s Testing expectations for wide_read_async.v .. ok. 729s Testing expectations for wide_read_mixed.v .. ok. 729s Testing expectations for wide_read_sync.v .. ok. 729s Testing expectations for wide_read_trans.v .. ok. 729s Testing expectations for wide_thru_priority.v .. ok. 729s Testing expectations for wide_write.v .. ok. 729s cd tests/memlib && bash run-test.sh "" 730s make[1]: Entering directory '/tmp/autopkgtest.l2kRn3/build.e8a/src/tests/memlib' 731s Test: t_async_big -> ok 734s Test: t_async_big_block -> ok 734s Test: t_async_small -> ok 734s Test: t_async_small_block -> ok 735s Test: t_sync_big -> ok 735s Test: t_sync_big_sdp -> ok 736s Test: t_sync_big_lut -> ok 736s Test: t_sync_small -> ok 737s Test: t_sync_small_block -> ok 737s Test: t_sync_small_block_attr -> ok 737s Test: t_init_lut_zeros_zero -> ok 737s Test: t_init_lut_zeros_any -> ok 737s Test: t_init_lut_val_zero -> ok 737s Test: t_init_lut_val_any -> ok 738s Test: t_init_lut_val_no_undef -> ok 738s Test: t_init_lut_val2_any -> ok 738s Test: t_init_lut_val2_no_undef -> ok 738s Test: t_init_lut_x_none -> ok 739s Test: t_init_lut_x_zero -> ok 739s Test: t_init_lut_x_any -> ok 739s Test: t_init_lut_x_no_undef -> ok 739s Test: t_ram_18b2B -> ok 739s Test: t_ram_9b1B -> ok 739s Test: t_ram_4b1B -> ok 740s Test: t_ram_2b1B -> ok 740s Test: t_ram_1b1B -> ok 740s Test: t_init_9b1B_zeros_zero -> ok 740s Test: t_init_9b1B_zeros_any -> ok 740s Test: t_init_9b1B_val_zero -> ok 741s Test: t_init_9b1B_val_any -> ok 741s Test: t_init_9b1B_val_no_undef -> ok 741s Test: t_init_13b2B_val_any -> ok 741s Test: t_init_18b2B_val_any -> ok 741s Test: t_init_18b2B_val_no_undef -> ok 742s Test: t_init_4b1B_x_none -> ok 742s Test: t_init_4b1B_x_zero -> ok 742s Test: t_init_4b1B_x_any -> ok 742s Test: t_init_4b1B_x_no_undef -> ok 742s Test: t_clock_a4_wANYrANYsFalse -> ok 742s Test: t_clock_a4_wANYrNEGsFalse -> ok 743s Test: t_clock_a4_wANYrPOSsFalse -> ok 743s Test: t_clock_a4_wNEGrANYsFalse -> ok 743s Test: t_clock_a4_wNEGrPOSsFalse -> ok 743s Test: t_clock_a4_wNEGrNEGsFalse -> ok 743s Test: t_clock_a4_wPOSrANYsFalse -> ok 744s Test: t_clock_a4_wPOSrNEGsFalse -> ok 744s Test: t_clock_a4_wPOSrPOSsFalse -> ok 744s Test: t_clock_a4_wANYrANYsTrue -> ok 744s Test: t_clock_a4_wNEGrPOSsTrue -> ok 744s Test: t_clock_a4_wNEGrNEGsTrue -> ok 744s Test: t_clock_a4_wPOSrNEGsTrue -> ok 745s Test: t_clock_a4_wPOSrPOSsTrue -> ok 745s Test: t_unmixed -> ok 745s Test: t_mixed_9_18 -> ok 745s Test: t_mixed_18_9 -> ok 745s Test: t_mixed_36_9 -> ok 746s Test: t_mixed_4_2 -> ok 746s Test: t_tdp -> ok 746s Test: t_sync_2clk -> ok 746s Test: t_sync_shared -> ok 746s Test: t_sync_2clk_shared -> ok 746s Test: t_sync_trans_old_old -> ok 747s Test: t_sync_trans_old_new -> ok 747s Test: t_sync_trans_old_none -> ok 747s Test: t_sync_trans_new_old -> ok 747s Test: t_sync_trans_new_new -> ok 747s Test: t_sync_trans_new_none -> ok 748s Test: t_sp_nc_none -> ok 748s Test: t_sp_new_none -> ok 748s Test: t_sp_old_none -> ok 748s Test: t_sp_nc_nc -> ok 748s Test: t_sp_new_nc -> ok 748s Test: t_sp_old_nc -> ok 749s Test: t_sp_nc_new -> ok 749s Test: t_sp_new_new -> ok 749s Test: t_sp_old_new -> ok 749s Test: t_sp_nc_old -> ok 749s Test: t_sp_new_old -> ok 749s Test: t_sp_old_old -> ok 750s Test: t_sp_nc_new_only -> ok 750s Test: t_sp_new_new_only -> ok 750s Test: t_sp_old_new_only -> ok 750s Test: t_sp_nc_new_only_be -> ok 750s Test: t_sp_new_new_only_be -> ok 750s Test: t_sp_old_new_only_be -> ok 751s Test: t_sp_nc_new_be -> ok 751s Test: t_sp_new_new_be -> ok 751s Test: t_sp_old_new_be -> ok 751s Test: t_sp_nc_old_be -> ok 751s Test: t_sp_new_old_be -> ok 752s Test: t_sp_old_old_be -> ok 752s Test: t_sp_nc_nc_be -> ok 752s Test: t_sp_new_nc_be -> ok 752s Test: t_sp_old_nc_be -> ok 752s Test: t_sp_nc_auto -> ok 753s Test: t_sp_new_auto -> ok 753s Test: t_sp_old_auto -> ok 753s Test: t_sp_nc_auto_be -> ok 753s Test: t_sp_new_auto_be -> ok 753s Test: t_sp_old_auto_be -> ok 753s Test: t_sp_init_x_x -> ok 754s Test: t_sp_init_x_x_re -> ok 754s Test: t_sp_init_x_x_ce -> ok 754s Test: t_sp_init_0_x -> ok 754s Test: t_sp_init_0_x_re -> ok 754s Test: t_sp_init_0_0 -> ok 754s Test: t_sp_init_0_0_re -> ok 755s Test: t_sp_init_0_any -> ok 755s Test: t_sp_init_0_any_re -> ok 755s Test: t_sp_init_v_x -> ok 755s Test: t_sp_init_v_x_re -> ok 755s Test: t_sp_init_v_0 -> ok 756s Test: t_sp_init_v_0_re -> ok 756s Test: t_sp_init_v_any -> ok 756s Test: t_sp_init_v_any_re -> ok 756s Test: t_sp_arst_x_x -> ok 756s Test: t_sp_arst_x_x_re -> ok 756s Test: t_sp_arst_0_x -> ok 757s Test: t_sp_arst_0_x_re -> ok 757s Test: t_sp_arst_0_0 -> ok 757s Test: t_sp_arst_0_0_re -> ok 757s Test: t_sp_arst_0_any -> ok 757s Test: t_sp_arst_0_any_re -> ok 757s Test: t_sp_arst_0_init -> ok 758s Test: t_sp_arst_0_init_re -> ok 758s Test: t_sp_arst_v_x -> ok 758s Test: t_sp_arst_v_x_re -> ok 758s Test: t_sp_arst_v_0 -> ok 758s Test: t_sp_arst_v_0_re -> ok 758s Test: t_sp_arst_v_any -> ok 759s Test: t_sp_arst_v_any_re -> ok 759s Test: t_sp_arst_v_init -> ok 759s Test: t_sp_arst_v_init_re -> ok 759s Test: t_sp_arst_e_x -> ok 759s Test: t_sp_arst_e_x_re -> ok 760s Test: t_sp_arst_e_0 -> ok 760s Test: t_sp_arst_e_0_re -> ok 760s Test: t_sp_arst_e_any -> ok 760s Test: t_sp_arst_e_any_re -> ok 760s Test: t_sp_arst_e_init -> ok 760s Test: t_sp_arst_e_init_re -> ok 761s Test: t_sp_arst_n_x -> ok 761s Test: t_sp_arst_n_x_re -> ok 761s Test: t_sp_arst_n_0 -> ok 761s Test: t_sp_arst_n_0_re -> ok 761s Test: t_sp_arst_n_any -> ok 762s Test: t_sp_arst_n_any_re -> ok 762s Test: t_sp_arst_n_init -> ok 762s Test: t_sp_arst_n_init_re -> ok 762s Test: t_sp_srst_x_x -> ok 762s Test: t_sp_srst_x_x_re -> ok 762s Test: t_sp_srst_0_x -> ok 763s Test: t_sp_srst_0_x_re -> ok 763s Test: t_sp_srst_0_0 -> ok 763s Test: t_sp_srst_0_0_re -> ok 763s Test: t_sp_srst_0_any -> ok 763s Test: t_sp_srst_0_any_re -> ok 764s Test: t_sp_srst_0_init -> ok 764s Test: t_sp_srst_0_init_re -> ok 764s Test: t_sp_srst_v_x -> ok 764s Test: t_sp_srst_v_x_re -> ok 764s Test: t_sp_srst_v_0 -> ok 764s Test: t_sp_srst_v_0_re -> ok 765s Test: t_sp_srst_v_any -> ok 765s Test: t_sp_srst_v_any_re -> ok 765s Test: t_sp_srst_v_any_re_gated -> ok 765s Test: t_sp_srst_v_any_ce -> ok 765s Test: t_sp_srst_v_any_ce_gated -> ok 766s Test: t_sp_srst_v_init -> ok 766s Test: t_sp_srst_v_init_re -> ok 766s Test: t_sp_srst_e_x -> ok 766s Test: t_sp_srst_e_x_re -> ok 766s Test: t_sp_srst_e_0 -> ok 766s Test: t_sp_srst_e_0_re -> ok 767s Test: t_sp_srst_e_any -> ok 767s Test: t_sp_srst_e_any_re -> ok 767s Test: t_sp_srst_e_init -> ok 767s Test: t_sp_srst_e_init_re -> ok 767s Test: t_sp_srst_n_x -> ok 768s Test: t_sp_srst_n_x_re -> ok 768s Test: t_sp_srst_n_0 -> ok 768s Test: t_sp_srst_n_0_re -> ok 768s Test: t_sp_srst_n_any -> ok 768s Test: t_sp_srst_n_any_re -> ok 769s Test: t_sp_srst_n_init -> ok 769s Test: t_sp_srst_n_init_re -> ok 769s Test: t_sp_srst_gv_x -> ok 769s Test: t_sp_srst_gv_x_re -> ok 769s Test: t_sp_srst_gv_0 -> ok 769s Test: t_sp_srst_gv_0_re -> ok 770s Test: t_sp_srst_gv_any -> ok 770s Test: t_sp_srst_gv_any_re -> ok 770s Test: t_sp_srst_gv_any_re_gated -> ok 770s Test: t_sp_srst_gv_any_ce -> ok 770s Test: t_sp_srst_gv_any_ce_gated -> ok 771s Test: t_sp_srst_gv_init -> ok 771s Test: t_sp_srst_gv_init_re -> ok 771s Test: t_wren_a4d4_NO_BYTE -> ok 771s Test: t_wren_a5d4_NO_BYTE -> ok 771s Test: t_wren_a6d4_NO_BYTE -> ok 771s Test: t_wren_a3d8_NO_BYTE -> ok 772s Test: t_wren_a4d8_NO_BYTE -> ok 772s Test: t_wren_a4d4_W4_B4 -> ok 772s Test: t_wren_a4d8_W4_B4_separate -> ok 772s Test: t_wren_a4d8_W8_B4 -> ok 772s Test: t_wren_a4d8_W8_B4_separate -> ok 772s Test: t_wren_a4d8_W8_B8 -> ok 773s Test: t_wren_a4d8_W8_B8_separate -> ok 773s Test: t_wren_a4d2w8_W16_B4 -> ok 773s Test: t_wren_a4d2w8_W16_B4_separate -> ok 773s Test: t_wren_a4d4w4_W16_B4 -> ok 773s Test: t_wren_a4d4w4_W16_B4_separate -> ok 774s Test: t_wren_a5d4w2_W16_B4 -> ok 774s Test: t_wren_a5d4w2_W16_B4_separate -> ok 774s Test: t_wren_a5d4w4_W16_B4 -> ok 774s Test: t_wren_a5d4w4_W16_B4_separate -> ok 774s Test: t_wren_a4d8w2_W16_B4 -> ok 775s Test: t_wren_a4d8w2_W16_B4_separate -> ok 775s Test: t_wren_a5d8w1_W16_B4 -> ok 775s Test: t_wren_a5d8w1_W16_B4_separate -> ok 775s Test: t_wren_a5d8w2_W16_B4 -> ok 775s Test: t_wren_a5d8w2_W16_B4_separate -> ok 776s Test: t_wren_a4d16w1_W16_B4 -> ok 776s Test: t_wren_a4d16w1_W16_B4_separate -> ok 776s Test: t_wren_a4d4w2_W8_B8 -> ok 776s Test: t_wren_a4d4w2_W8_B8_separate -> ok 776s Test: t_wren_a4d4w1_W8_B8 -> ok 777s Test: t_wren_a4d4w1_W8_B8_separate -> ok 777s Test: t_wren_a4d8w2_W8_B8 -> ok 777s Test: t_wren_a4d8w2_W8_B8_separate -> ok 777s Test: t_wren_a3d8w2_W8_B8 -> ok 777s Test: t_wren_a3d8w2_W8_B8_separate -> ok 777s Test: t_wren_a4d4w2_W8_B4 -> ok 778s Test: t_wren_a4d4w2_W8_B4_separate -> ok 778s Test: t_wren_a4d2w4_W8_B4 -> ok 778s Test: t_wren_a4d2w4_W8_B4_separate -> ok 778s Test: t_wren_a4d4w4_W8_B4 -> ok 778s Test: t_wren_a4d4w4_W8_B4_separate -> ok 779s Test: t_wren_a4d4w4_W4_B4 -> ok 779s Test: t_wren_a4d4w4_W4_B4_separate -> ok 779s Test: t_wren_a4d4w5_W4_B4 -> ok 779s Test: t_wren_a4d4w5_W4_B4_separate -> ok 779s Test: t_geom_a4d64_wren -> ok 780s Test: t_geom_a5d32_wren -> ok 780s Test: t_geom_a5d64_wren -> ok 780s Test: t_geom_a6d16_wren -> ok 780s Test: t_geom_a6d30_wren -> ok 780s Test: t_geom_a6d64_wren -> ok 781s Test: t_geom_a7d4_wren -> ok 781s Test: t_geom_a7d6_wren -> ok 781s Test: t_geom_a7d8_wren -> ok 781s Test: t_geom_a7d17_wren -> ok 781s Test: t_geom_a8d4_wren -> ok 781s Test: t_geom_a8d6_wren -> ok 782s Test: t_geom_a9d4_wren -> ok 782s Test: t_geom_a9d8_wren -> ok 782s Test: t_geom_a9d5_wren -> ok 782s Test: t_geom_a9d6_wren -> ok 782s Test: t_geom_a3d18_9b1B -> ok 783s Test: t_geom_a4d4_9b1B -> ok 783s Test: t_geom_a4d18_9b1B -> ok 783s Test: t_geom_a5d32_9b1B -> ok 783s Test: t_geom_a6d4_9b1B -> ok 783s Test: t_geom_a7d11_9b1B -> ok 784s Test: t_geom_a7d18_9b1B -> ok 784s Test: t_geom_a11d1_9b1B -> ok 784s Test: t_wide_sdp_a6r1w1b1x1 -> ok 784s Test: t_wide_sdp_a7r1w1b1x1 -> ok 784s Test: t_wide_sdp_a8r1w1b1x1 -> ok 785s Test: t_wide_sdp_a6r0w0b0x0 -> ok 785s Test: t_wide_sdp_a6r1w0b0x0 -> ok 785s Test: t_wide_sdp_a6r2w0b0x0 -> ok 786s Test: t_wide_sdp_a6r3w0b0x0 -> ok 786s Test: t_wide_sdp_a6r4w0b0x0 -> ok 786s Test: t_wide_sdp_a6r5w0b0x0 -> ok 786s Test: t_wide_sdp_a6r0w1b0x0 -> ok 786s Test: t_wide_sdp_a6r0w1b1x0 -> ok 786s Test: t_wide_sdp_a6r0w2b0x0 -> ok 787s Test: t_wide_sdp_a6r0w2b2x0 -> ok 787s Test: t_wide_sdp_a6r0w3b2x0 -> ok 787s Test: t_wide_sdp_a6r0w4b2x0 -> ok 788s Test: t_wide_sdp_a6r0w5b2x0 -> ok 788s Test: t_wide_sdp_a7r0w0b0x0 -> ok 788s Test: t_wide_sdp_a7r1w0b0x0 -> ok 788s Test: t_wide_sdp_a7r2w0b0x0 -> ok 788s Test: t_wide_sdp_a7r3w0b0x0 -> ok 789s Test: t_wide_sdp_a7r4w0b0x0 -> ok 789s Test: t_wide_sdp_a7r5w0b0x0 -> ok 789s Test: t_wide_sdp_a7r0w1b0x0 -> ok 789s Test: t_wide_sdp_a7r0w1b1x0 -> ok 790s Test: t_wide_sdp_a7r0w2b0x0 -> ok 790s Test: t_wide_sdp_a7r0w2b2x0 -> ok 790s Test: t_wide_sdp_a7r0w3b2x0 -> ok 790s Test: t_wide_sdp_a7r0w4b2x0 -> ok 791s Test: t_wide_sdp_a7r0w5b2x0 -> ok 791s Test: t_wide_sp_mix_a6r1w1b1 -> ok 791s Test: t_wide_sp_mix_a7r1w1b1 -> ok 791s Test: t_wide_sp_mix_a8r1w1b1 -> ok 792s Test: t_wide_sp_mix_a6r0w0b0 -> ok 792s Test: t_wide_sp_mix_a6r1w0b0 -> ok 792s Test: t_wide_sp_mix_a6r2w0b0 -> ok 792s Test: t_wide_sp_mix_a6r3w0b0 -> ok 792s Test: t_wide_sp_mix_a6r4w0b0 -> ok 793s Test: t_wide_sp_mix_a6r5w0b0 -> ok 793s Test: t_wide_sp_mix_a6r0w1b0 -> ok 793s Test: t_wide_sp_mix_a6r0w1b1 -> ok 793s Test: t_wide_sp_mix_a6r0w2b0 -> ok 793s Test: t_wide_sp_mix_a6r0w2b2 -> ok 794s Test: t_wide_sp_mix_a6r0w3b2 -> ok 794s Test: t_wide_sp_mix_a6r0w4b2 -> ok 794s Test: t_wide_sp_mix_a6r0w5b2 -> ok 795s Test: t_wide_sp_mix_a7r0w0b0 -> ok 795s Test: t_wide_sp_mix_a7r1w0b0 -> ok 795s Test: t_wide_sp_mix_a7r2w0b0 -> ok 795s Test: t_wide_sp_mix_a7r3w0b0 -> ok 795s Test: t_wide_sp_mix_a7r4w0b0 -> ok 796s Test: t_wide_sp_mix_a7r5w0b0 -> ok 796s Test: t_wide_sp_mix_a7r0w1b0 -> ok 796s Test: t_wide_sp_mix_a7r0w1b1 -> ok 796s Test: t_wide_sp_mix_a7r0w2b0 -> ok 797s Test: t_wide_sp_mix_a7r0w2b2 -> ok 797s Test: t_wide_sp_mix_a7r0w3b2 -> ok 797s Test: t_wide_sp_mix_a7r0w4b2 -> ok 798s Test: t_wide_sp_mix_a7r0w5b2 -> ok 798s Test: t_wide_sp_tied_a6r1w1b1 -> ok 798s Test: t_wide_sp_tied_a7r1w1b1 -> ok 798s Test: t_wide_sp_tied_a8r1w1b1 -> ok 798s Test: t_wide_sp_tied_a6r0w0b0 -> ok 798s Test: t_wide_sp_tied_a6r1w0b0 -> ok 799s Test: t_wide_sp_tied_a6r2w0b0 -> ok 799s Test: t_wide_sp_tied_a6r3w0b0 -> ok 799s Test: t_wide_sp_tied_a6r4w0b0 -> ok 799s Test: t_wide_sp_tied_a6r5w0b0 -> ok 800s Test: t_wide_sp_tied_a6r0w1b0 -> ok 800s Test: t_wide_sp_tied_a6r0w1b1 -> ok 800s Test: t_wide_sp_tied_a6r0w2b0 -> ok 800s Test: t_wide_sp_tied_a6r0w2b2 -> ok 801s Test: t_wide_sp_tied_a6r0w3b2 -> ok 801s Test: t_wide_sp_tied_a6r0w4b2 -> ok 801s Test: t_wide_sp_tied_a6r0w5b2 -> ok 801s Test: t_wide_sp_tied_a7r0w0b0 -> ok 802s Test: t_wide_sp_tied_a7r1w0b0 -> ok 802s Test: t_wide_sp_tied_a7r2w0b0 -> ok 802s Test: t_wide_sp_tied_a7r3w0b0 -> ok 802s Test: t_wide_sp_tied_a7r4w0b0 -> ok 803s Test: t_wide_sp_tied_a7r5w0b0 -> ok 803s Test: t_wide_sp_tied_a7r0w1b0 -> ok 803s Test: t_wide_sp_tied_a7r0w1b1 -> ok 803s Test: t_wide_sp_tied_a7r0w2b0 -> ok 803s Test: t_wide_sp_tied_a7r0w2b2 -> ok 804s Test: t_wide_sp_tied_a7r0w3b2 -> ok 804s Test: t_wide_sp_tied_a7r0w4b2 -> ok 804s Test: t_wide_sp_tied_a7r0w5b2 -> ok 805s Test: t_wide_read_a6r1w1b1 -> ok 805s Test: t_wide_write_a6r1w1b1 -> ok 805s Test: t_wide_read_a7r1w1b1 -> ok 805s Test: t_wide_write_a7r1w1b1 -> ok 805s Test: t_wide_read_a8r1w1b1 -> ok 806s Test: t_wide_write_a8r1w1b1 -> ok 806s Test: t_wide_read_a6r0w0b0 -> ok 806s Test: t_wide_write_a6r0w0b0 -> ok 806s Test: t_wide_read_a6r1w0b0 -> ok 806s Test: t_wide_write_a6r1w0b0 -> ok 806s Test: t_wide_read_a6r2w0b0 -> ok 807s Test: t_wide_write_a6r2w0b0 -> ok 807s Test: t_wide_read_a6r3w0b0 -> ok 807s Test: t_wide_write_a6r3w0b0 -> ok 807s Test: t_wide_read_a6r4w0b0 -> ok 808s Test: t_wide_write_a6r4w0b0 -> ok 808s Test: t_wide_read_a6r5w0b0 -> ok 808s Test: t_wide_write_a6r5w0b0 -> ok 808s Test: t_wide_read_a6r0w1b0 -> ok 809s Test: t_wide_write_a6r0w1b0 -> ok 809s Test: t_wide_read_a6r0w1b1 -> ok 809s Test: t_wide_write_a6r0w1b1 -> ok 809s Test: t_wide_read_a6r0w2b0 -> ok 809s Test: t_wide_write_a6r0w2b0 -> ok 810s Test: t_wide_read_a6r0w2b2 -> ok 810s Test: t_wide_write_a6r0w2b2 -> ok 810s Test: t_wide_read_a6r0w3b2 -> ok 810s Test: t_wide_write_a6r0w3b2 -> ok 811s Test: t_wide_read_a6r0w4b2 -> ok 811s Test: t_wide_write_a6r0w4b2 -> ok 811s Test: t_wide_read_a6r0w5b2 -> ok 812s Test: t_wide_write_a6r0w5b2 -> ok 812s Test: t_wide_read_a7r0w0b0 -> ok 812s Test: t_wide_write_a7r0w0b0 -> ok 812s Test: t_wide_read_a7r1w0b0 -> ok 813s Test: t_wide_write_a7r1w0b0 -> ok 813s Test: t_wide_read_a7r2w0b0 -> ok 813s Test: t_wide_write_a7r2w0b0 -> ok 813s Test: t_wide_read_a7r3w0b0 -> ok 813s Test: t_wide_write_a7r3w0b0 -> ok 814s Test: t_wide_read_a7r4w0b0 -> ok 814s Test: t_wide_write_a7r4w0b0 -> ok 814s Test: t_wide_read_a7r5w0b0 -> ok 814s Test: t_wide_write_a7r5w0b0 -> ok 815s Test: t_wide_read_a7r0w1b0 -> ok 815s Test: t_wide_write_a7r0w1b0 -> ok 815s Test: t_wide_read_a7r0w1b1 -> ok 815s Test: t_wide_write_a7r0w1b1 -> ok 815s Test: t_wide_read_a7r0w2b0 -> ok 816s Test: t_wide_write_a7r0w2b0 -> ok 816s Test: t_wide_read_a7r0w2b2 -> ok 816s Test: t_wide_write_a7r0w2b2 -> ok 816s Test: t_wide_read_a7r0w3b2 -> ok 817s Test: t_wide_write_a7r0w3b2 -> ok 817s Test: t_wide_read_a7r0w4b2 -> ok 817s Test: t_wide_write_a7r0w4b2 -> ok 818s Test: t_wide_read_a7r0w5b2 -> ok 818s Test: t_wide_write_a7r0w5b2 -> ok 818s Test: t_quad_port_a2d2 -> ok 818s Test: t_quad_port_a4d2 -> ok 819s Test: t_quad_port_a5d2 -> ok 819s Test: t_quad_port_a4d4 -> ok 819s Test: t_quad_port_a6d2 -> ok 819s Test: t_quad_port_a4d8 -> ok 819s Test: t_wide_quad_a4w2r1 -> ok 819s Test: t_wide_oct_a4w2r1 -> ok 820s Test: t_wide_quad_a4w2r2 -> ok 820s Test: t_wide_oct_a4w2r2 -> ok 820s Test: t_wide_quad_a4w2r3 -> ok 820s Test: t_wide_oct_a4w2r3 -> ok 820s Test: t_wide_quad_a4w2r4 -> ok 820s Test: t_wide_oct_a4w2r4 -> ok 821s Test: t_wide_quad_a4w2r5 -> ok 821s Test: t_wide_oct_a4w2r5 -> ok 821s Test: t_wide_quad_a4w2r6 -> ok 821s Test: t_wide_oct_a4w2r6 -> ok 821s Test: t_wide_quad_a4w2r7 -> ok 822s Test: t_wide_oct_a4w2r7 -> ok 822s Test: t_wide_quad_a4w2r8 -> ok 822s Test: t_wide_oct_a4w2r8 -> ok 822s Test: t_wide_quad_a4w2r9 -> ok 822s Test: t_wide_oct_a4w2r9 -> ok 823s Test: t_wide_quad_a4w4r1 -> ok 823s Test: t_wide_oct_a4w4r1 -> ok 823s Test: t_wide_quad_a4w4r4 -> ok 823s Test: t_wide_oct_a4w4r4 -> ok 823s Test: t_wide_quad_a4w4r6 -> ok 824s Test: t_wide_oct_a4w4r6 -> ok 824s Test: t_wide_quad_a4w4r9 -> ok 824s Test: t_wide_oct_a4w4r9 -> ok 824s Test: t_wide_quad_a5w2r1 -> ok 824s Test: t_wide_oct_a5w2r1 -> ok 825s Test: t_wide_quad_a5w2r4 -> ok 825s Test: t_wide_oct_a5w2r4 -> ok 825s Test: t_wide_quad_a5w2r9 -> ok 825s Test: t_wide_oct_a5w2r9 -> ok 825s Test: t_no_reset -> ok 826s Test: t_gclken -> ok 826s Test: t_ungated -> ok 826s Test: t_gclken_ce -> ok 826s Test: t_grden -> ok 827s Test: t_grden_ce -> ok 827s Test: t_exclwr -> ok 827s Test: t_excl_rst -> ok 827s Test: t_transwr -> ok 827s Test: t_trans_rst -> ok 828s Test: t_wr_byte -> ok 828s Test: t_trans_byte -> ok 828s Test: t_wr_rst_byte -> ok 828s Test: t_rst_wr_byte -> ok 828s Test: t_rdenrst_wr_byte -> ok 828s make[1]: Leaving directory '/tmp/autopkgtest.l2kRn3/build.e8a/src/tests/memlib' 828s cd tests/bram && bash run-test.sh "" 828s generating tests.. 829s PRNG seed: 965508 829s running tests.. 829s make[1]: Entering directory '/tmp/autopkgtest.l2kRn3/build.e8a/src/tests/bram' 830s Passed memory_bram test 00_01. 830s Passed memory_bram test 00_02. 831s Passed memory_bram test 00_03. 833s Passed memory_bram test 00_04. 834s Passed memory_bram test 01_00. 834s Passed memory_bram test 01_02. 837s Passed memory_bram test 01_03. 839s Passed memory_bram test 01_04. 840s Passed memory_bram test 02_00. 840s Passed memory_bram test 02_01. 842s Passed memory_bram test 02_03. 843s Passed memory_bram test 02_04. 845s Passed memory_bram test 03_00. 846s Passed memory_bram test 03_01. 847s Passed memory_bram test 03_02. 848s Passed memory_bram test 03_04. 848s Passed memory_bram test 04_00. 849s Passed memory_bram test 04_01. 850s Passed memory_bram test 04_02. 852s Passed memory_bram test 04_03. 852s make[1]: Leaving directory '/tmp/autopkgtest.l2kRn3/build.e8a/src/tests/bram' 852s cd tests/various && bash run-test.sh 852s make[1]: Entering directory '/tmp/autopkgtest.l2kRn3/build.e8a/src/tests/various' 852s Warning: Wire abc9_test027.$abc$91$o is used but has no driver. 852s Passed abc9.ys 852s Passed aiger_dff.ys 852s Passed attrib05_port_conn.ys 852s Passed attrib07_func_call.ys 852s Passed autoname.ys 852s Passed blackbox_wb.ys 852s Passed bug1496.ys 852s Passed bug1531.ys 852s Passed bug1614.ys 852s Passed bug1710.ys 852s Warning: Yosys has only limited support for tri-state logic at the moment. (< svinterface1_tb.v:50: $finish called at 420000 (10ps) 917s svinterface1_tb.v:50: $finish called at 420000 (10ps) 917s ok 918s Test: svinterface_at_top -> svinterface_at_top_tb.v:61: $finish called at 420000 (10ps) 918s svinterface_at_top_tb_wrapper.v:61: $finish called at 420000 (10ps) 918s ERROR! 918s Test: load_and_derive ->ok 918s Test: resolve_types ->ok 918s cd tests/svtypes && bash run-test.sh "" 918s make[1]: Entering directory '/tmp/autopkgtest.l2kRn3/build.e8a/src/tests/svtypes' 918s Passed enum_simple.ys 918s Passed logic_rom.ys 918s < ok 933s Test ../../techlibs/anlogic/cells_sim.v -> ok 933s Test ../../techlibs/coolrunner2/cells_sim.v -> ok 933s Test ../../techlibs/ecp5/cells_sim.v -> ok 933s Test ../../techlibs/efinix/cells_sim.v -> ok 933s Test ../../techlibs/gatemate/cells_sim.v -> ok 933s Test ../../techlibs/gowin/cells_sim.v -> ok 933s Test ../../techlibs/greenpak4/cells_sim.v -> ok 933s Test ../../techlibs/ice40/cells_sim.v -DICE40_HX ->../../techlibs/ice40/cells_sim.v:2231: warning: Choosing typ expression. 933s ../../techlibs/ice40/cells_sim.v:2231: warning: Choosing typ expression. 933s ../../techlibs/ice40/cells_sim.v:2233: warning: Choosing typ expression. 933s ../../techlibs/ice40/cells_sim.v:2233: warning: Choosing typ expression. 933s ../../techlibs/ice40/cells_sim.v:2235: warning: Choosing typ expression. 933s ../../techlibs/ice40/cells_sim.v:2235: warning: Choosing typ expression. 933s ../../techlibs/ice40/cells_sim.v:2237: warning: Choosing typ expression. 933s ../../techlibs/ice40/cells_sim.v:2237: warning: Choosing typ expression. 933s ../../techlibs/ice40/cells_sim.v:2239: warning: Choosing typ expression. 933s ../../techlibs/ice40/cells_sim.v:2239: warning: Choosing typ expression. 933s ok 933s Test ../../techlibs/ice40/cells_sim.v -DICE40_LP ->../../techlibs/ice40/cells_sim.v:2295: warning: Choosing typ expression. 933s ../../techlibs/ice40/cells_sim.v:2295: warning: Choosing typ expression. 933s ../../techlibs/ice40/cells_sim.v:2297: warning: Choosing typ expression. 933s ../../techlibs/ice40/cells_sim.v:2297: warning: Choosing typ expression. 933s ../../techlibs/ice40/cells_sim.v:2299: warning: Choosing typ expression. 933s ../../techlibs/ice40/cells_sim.v:2299: warning: Choosing typ expression. 933s ../../techlibs/ice40/cells_sim.v:2301: warning: Choosing typ expression. 933s ../../techlibs/ice40/cells_sim.v:2301: warning: Choosing typ expression. 933s ../../techlibs/ice40/cells_sim.v:2303: warning: Choosing typ expression. 933s ../../techlibs/ice40/cells_sim.v:2303: warning: Choosing typ expression. 933s ok 933s Test ../../techlibs/ice40/cells_sim.v -DICE40_U ->../../techlibs/ice40/cells_sim.v:2359: warning: Choosing typ expression. 933s ../../techlibs/ice40/cells_sim.v:2359: warning: Choosing typ expression. 933s ../../techlibs/ice40/cells_sim.v:2361: warning: Choosing typ expression. 933s ../../techlibs/ice40/cells_sim.v:2361: warning: Choosing typ expression. 933s ../../techlibs/ice40/cells_sim.v:2363: warning: Choosing typ expression. 933s ../../techlibs/ice40/cells_sim.v:2363: warning: Choosing typ expression. 933s ../../techlibs/ice40/cells_sim.v:2365: warning: Choosing typ expression. 933s ../../techlibs/ice40/cells_sim.v:2365: warning: Choosing typ expression. 933s ../../techlibs/ice40/cells_sim.v:2367: warning: Choosing typ expression. 933s ../../techlibs/ice40/cells_sim.v:2367: warning: Choosing typ expression. 933s ok 933s Test ../../techlibs/intel/cyclone10lp/cells_sim.v -> ok 933s Test ../../techlibs/intel/cycloneiv/cells_sim.v -> ok 933s Test ../../techlibs/intel/cycloneive/cells_sim.v -> ok 933s Test ../../techlibs/intel/max10/cells_sim.v -> ok 934s Test ../../techlibs/intel_alm/cyclonev/cells_sim.v -> ok 934s Test ../../techlibs/nexus/cells_sim.v -> ok 934s Test ../../techlibs/quicklogic/cells_sim.v -> ok 934s Test ../../techlibs/sf2/cells_sim.v -> ok 934s Test ../../techlibs/xilinx/cells_sim.v -> ok 934s Test ../../techlibs/common/simcells.v -> ok 934s Test ../../techlibs/common/simlib.v -> ok 934s cd tests/arch/ice40 && bash run-test.sh "" 934s make[1]: Entering directory '/tmp/autopkgtest.l2kRn3/build.e8a/src/tests/arch/ice40' 935s Passed add_sub.ys 939s Passed adffs.ys 939s Warning: Resizing cell port SSCounter6o.l0.I3 from 32 bits to 1 bits. 939s Warning: Resizing cell port SSCounter6o.c0.CI from 32 bits to 1 bits. 939s Warning: Resizing cell port SSCounter6o.lien.I0 from 32 bits to 1 bits. 939s Warning: Resizing cell port SSCounter6o.lien.I1 from 32 bits to 1 bits. 940s Passed bug1597.ys 941s Passed bug1598.ys 942s Passed bug1626.ys 963s Passed bug1644.ys 964s Passed bug2061.ys 965s Passed counter.ys 967s Passed dffs.ys 977s Passed dpram.ys 978s Passed fsm.ys 978s Passed ice40_dsp.ys 979s Passed ice40_opt.ys 979s Passed ice40_wrapcarry.ys 982s Passed latches.ys 983s Passed logic.ys 989s Passed macc.ys 1056s Passed memories.ys 1057s Passed mul.ys 1063s Passed mux.ys 1063s Warning: wire '\data' is assigned in a block at rom.v:10.5-10.15. 1063s Warning: wire '\data' is assigned in a block at rom.v:11.5-11.15. 1063s Warning: wire '\data' is assigned in a block at rom.v:12.5-12.15. 1063s Warning: wire '\data' is assigned in a block at rom.v:13.6-13.16. 1063s Warning: wire '\data' is assigned in a block at rom.v:14.6-14.16. 1063s Warning: wire '\data' is assigned in a block at rom.v:15.6-15.16. 1063s Warning: wire '\data' is assigned in a block at rom.v:16.11-16.21. 1063s Passed rom.ys 1064s Passed shifter.ys 1064s Warning: wire '\read_data' is assigned in a block at spram.v:19.3-19.25. 1066s Passed spram.ys 1067s Passed tribuf.ys 1067s make[1]: Leaving directory '/tmp/autopkgtest.l2kRn3/build.e8a/src/tests/arch/ice40' 1067s cd tests/arch/xilinx && bash run-test.sh "" 1067s make[1]: Entering directory '/tmp/autopkgtest.l2kRn3/build.e8a/src/tests/arch/xilinx' 1086s Warning: Whitebox '$paramod\FDRE\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. 1086s Warning: Whitebox 'FDSE' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. 1086s Warning: Whitebox '$paramod\FDRE_1\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. 1086s Warning: Whitebox '$paramod\FDSE_1\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. 1115s Passed abc9_dff.ys 1120s Warning: Shift register inference not yet supported for family xc3s. 1124s Passed add_sub.ys 1146s Passed adffs.ys 1151s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DIADI from 64 bits to 16 bits. 1151s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOADO from 64 bits to 16 bits. 1151s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOBDO from 64 bits to 16 bits. 1151s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOPADOP from 8 bits to 2 bits. 1151s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOPBDOP from 8 bits to 2 bits. 1151s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.WEA from 4 bits to 2 bits. 1163s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.WEBWE from 1 bits to 4 bits. 1168s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DIADI from 64 bits to 16 bits. 1168s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOADO from 64 bits to 16 bits. 1168s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOBDO from 64 bits to 16 bits. 1168s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOPADOP from 8 bits to 2 bits. 1168s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOPBDOP from 8 bits to 2 bits. 1168s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.WEA from 4 bits to 2 bits. 1169s Warning: Selection "asym_ram_sdp_read_wider" did not match any module. 1185s Passed asym_ram_sdp.ys 1190s Warning: Resizing cell port block_ram.memory.0.0.DIADI from 64 bits to 16 bits. 1190s Warning: Resizing cell port block_ram.memory.0.0.DOADO from 64 bits to 16 bits. 1190s Warning: Resizing cell port block_ram.memory.0.0.DOBDO from 64 bits to 16 bits. 1190s Warning: Resizing cell port block_ram.memory.0.0.DOPADOP from 8 bits to 2 bits. 1190s Warning: Resizing cell port block_ram.memory.0.0.DOPBDOP from 8 bits to 2 bits. 1190s Warning: Resizing cell port block_ram.memory.0.0.WEA from 4 bits to 2 bits. 1219s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DIADI from 64 bits to 16 bits. 1219s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOADO from 64 bits to 16 bits. 1219s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOBDO from 64 bits to 16 bits. 1219s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOPADOP from 8 bits to 2 bits. 1219s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOPBDOP from 8 bits to 2 bits. 1219s Warning: Resizing cell port distributed_ram_manual.memory.0.0.WEA from 4 bits to 2 bits. 1219s Passed attributes_test.ys 1224s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIADI from 64 bits to 16 bits. 1224s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOADO from 64 bits to 16 bits. 1224s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOBDO from 64 bits to 16 bits. 1224s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPADOP from 8 bits to 2 bits. 1224s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPBDOP from 8 bits to 2 bits. 1224s Warning: Resizing cell port sync_ram_sdp.memory.0.0.WEA from 4 bits to 2 bits. 1230s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIPADIP from 8 bits to 2 bits. 1252s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIADI from 64 bits to 32 bits. 1252s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIPADIP from 8 bits to 4 bits. 1252s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOADO from 64 bits to 32 bits. 1252s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOBDO from 64 bits to 32 bits. 1252s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPADOP from 8 bits to 4 bits. 1252s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPBDOP from 8 bits to 4 bits. 1285s Passed blockram.ys 1290s Passed bug1460.ys 1295s Passed bug1462.ys 1300s Passed bug1480.ys 1306s Passed bug1598.ys 1308s Warning: Wire top.\t is used but has no driver. 1308s Warning: Wire top.\in is used but has no driver. 1311s Passed bug1605.ys 1312s Passed bug3670.ys 1318s Passed counter.ys 1342s Passed dffs.ys 1360s Passed dsp_abc9.ys 1373s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef. 1373s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef. 1427s Passed dsp_cascade.ys 1432s Passed dsp_fastfir.ys 1439s Passed dsp_simd.ys 1446s Warning: Shift register inference not yet supported for family xc3se. 1449s Passed fsm.ys 1466s Passed latches.ys 1471s Passed logic.ys 1518s Warning: Shift register inference not yet supported for family xc3s. 1522s Passed lutram.ys 1535s Passed macc.ys 1544s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef. 1544s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef. 1546s Passed mul.ys 1546s Warning: Replacing memory \M with list of registers. See mul_unsigned.v:25 1559s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef. 1559s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef. 1564s Passed mul_unsigned.ys 1587s Passed mux.ys 1587s Warning: Shift register inference not yet supported for family xc3se. 1601s Passed mux_lut4.ys 1612s Passed nosrl.ys 1613s Passed opt_lut_ins.ys 1628s Passed pmgen_xilinx_srl.ys 1635s Warning: Resizing cell port priority_memory.mem.0.0.ADDRARDADDR from 16 bits to 15 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.0.ADDRBWRADDR from 16 bits to 15 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.0.DINADIN from 64 bits to 32 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.0.DINBDIN from 64 bits to 32 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.0.DINPADINP from 8 bits to 4 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.0.DINPBDINP from 8 bits to 4 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.0.DOUTADOUT from 64 bits to 32 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.0.DOUTBDOUT from 64 bits to 32 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.0.DOUTPADOUTP from 8 bits to 4 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.0.DOUTPBDOUTP from 8 bits to 4 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.0.WEBWE from 4 bits to 8 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.1.ADDRARDADDR from 16 bits to 15 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.1.ADDRBWRADDR from 16 bits to 15 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.1.DINADIN from 64 bits to 32 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.1.DINBDIN from 64 bits to 32 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.1.DINPADINP from 8 bits to 4 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.1.DINPBDINP from 8 bits to 4 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.1.DOUTADOUT from 64 bits to 32 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.1.DOUTBDOUT from 64 bits to 32 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.1.DOUTPADOUTP from 8 bits to 4 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.1.DOUTPBDOUTP from 8 bits to 4 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.1.WEBWE from 4 bits to 8 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.2.ADDRARDADDR from 16 bits to 15 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.2.ADDRBWRADDR from 16 bits to 15 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.2.DINADIN from 64 bits to 32 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.2.DINBDIN from 64 bits to 32 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.2.DINPADINP from 8 bits to 4 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.2.DINPBDINP from 8 bits to 4 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.2.DOUTADOUT from 64 bits to 32 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.2.DOUTBDOUT from 64 bits to 32 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.2.DOUTPADOUTP from 8 bits to 4 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.2.DOUTPBDOUTP from 8 bits to 4 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.2.WEBWE from 4 bits to 8 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.3.ADDRARDADDR from 16 bits to 15 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.3.ADDRBWRADDR from 16 bits to 15 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.3.DINADIN from 64 bits to 32 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.3.DINBDIN from 64 bits to 32 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.3.DINPADINP from 8 bits to 4 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.3.DINPBDINP from 8 bits to 4 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.3.DOUTADOUT from 64 bits to 32 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.3.DOUTBDOUT from 64 bits to 32 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.3.DOUTPADOUTP from 8 bits to 4 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.3.DOUTPBDOUTP from 8 bits to 4 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.3.WEBWE from 4 bits to 8 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.4.ADDRARDADDR from 16 bits to 15 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.4.ADDRBWRADDR from 16 bits to 15 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.4.DINADIN from 64 bits to 32 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.4.DINBDIN from 64 bits to 32 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.4.DINPADINP from 8 bits to 4 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.4.DINPBDINP from 8 bits to 4 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.4.DOUTADOUT from 64 bits to 32 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.4.DOUTBDOUT from 64 bits to 32 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.4.DOUTPADOUTP from 8 bits to 4 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.4.DOUTPBDOUTP from 8 bits to 4 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.4.WEBWE from 4 bits to 8 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.5.ADDRARDADDR from 16 bits to 15 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.5.ADDRBWRADDR from 16 bits to 15 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.5.DINADIN from 64 bits to 32 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.5.DINBDIN from 64 bits to 32 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.5.DINPADINP from 8 bits to 4 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.5.DINPBDINP from 8 bits to 4 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.5.DOUTADOUT from 64 bits to 32 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.5.DOUTBDOUT from 64 bits to 32 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.5.DOUTPADOUTP from 8 bits to 4 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.5.DOUTPBDOUTP from 8 bits to 4 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.5.WEBWE from 4 bits to 8 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.6.ADDRARDADDR from 16 bits to 15 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.6.ADDRBWRADDR from 16 bits to 15 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.6.DINADIN from 64 bits to 32 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.6.DINBDIN from 64 bits to 32 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.6.DINPADINP from 8 bits to 4 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.6.DINPBDINP from 8 bits to 4 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.6.DOUTADOUT from 64 bits to 32 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.6.DOUTBDOUT from 64 bits to 32 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.6.DOUTPADOUTP from 8 bits to 4 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.6.DOUTPBDOUTP from 8 bits to 4 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.6.WEBWE from 4 bits to 8 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.7.ADDRARDADDR from 16 bits to 15 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.7.ADDRBWRADDR from 16 bits to 15 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.7.DINADIN from 64 bits to 32 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.7.DINBDIN from 64 bits to 32 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.7.DINPADINP from 8 bits to 4 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.7.DINPBDINP from 8 bits to 4 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.7.DOUTADOUT from 64 bits to 32 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.7.DOUTBDOUT from 64 bits to 32 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.7.DOUTPADOUTP from 8 bits to 4 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.7.DOUTPBDOUTP from 8 bits to 4 bits. 1635s Warning: Resizing cell port priority_memory.mem.0.7.WEBWE from 4 bits to 8 bits. 1640s Warning: Resizing cell port priority_memory.mem.0.0.BWE_A from 8 bits to 9 bits. 1640s Warning: Resizing cell port priority_memory.mem.0.0.BWE_B from 8 bits to 9 bits. 1656s Warning: Resizing cell port sp_write_first.mem.0.0.BWE_A from 8 bits to 9 bits. 1661s Warning: Resizing cell port sp_read_first.mem.0.0.BWE_B from 8 bits to 9 bits. 1661s Passed priority_memory.ys 1667s Passed shifter.ys 1672s Passed tribuf.ys 1677s Passed xilinx_dffopt.ys 1677s Passed xilinx_dsp.ys 1677s Passed xilinx_srl.ys 1688s Passed macc.sh 1698s Passed tribuf.sh 1698s make[1]: Leaving directory '/tmp/autopkgtest.l2kRn3/build.e8a/src/tests/arch/xilinx' 1698s cd tests/arch/ecp5 && bash run-test.sh "" 1698s make[1]: Entering directory '/tmp/autopkgtest.l2kRn3/build.e8a/src/tests/arch/ecp5' 1699s Passed add_sub.ys 1702s Passed adffs.ys 1703s Passed bug1459.ys 1704s Passed bug1598.ys 1704s Passed bug1630.ys 1704s Warning: Literal has a width of 16 bit, but value requires 184 bit. (<>>/,/<<>>/ {print $0}' 2245s + iverilog -o iverilog-initial_display initial_display.v 2245s + ./iverilog-initial_display 2245s + diff yosys-initial_display.log iverilog-initial_display.log 2245s + test_always_display clk -DEVENT_CLK 2245s + local subtest=clk 2245s + shift 2245s + ../../yosys -p 'read_verilog -DEVENT_CLK always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk-1.v 2245s + ../../yosys -p 'read_verilog yosys-always_display-clk-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk-2.v 2245s + diff yosys-always_display-clk-1.v yosys-always_display-clk-2.v 2245s + test_always_display clk_rst -DEVENT_CLK_RST 2245s + local subtest=clk_rst 2245s + shift 2245s + ../../yosys -p 'read_verilog -DEVENT_CLK_RST always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst-1.v 2245s + ../../yosys -p 'read_verilog yosys-always_display-clk_rst-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst-2.v 2245s + diff yosys-always_display-clk_rst-1.v yosys-always_display-clk_rst-2.v 2245s + test_always_display star -DEVENT_STAR 2245s + local subtest=star 2245s + shift 2245s + ../../yosys -p 'read_verilog -DEVENT_STAR always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star-1.v 2245s + ../../yosys -p 'read_verilog yosys-always_display-star-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star-2.v 2245s + diff yosys-always_display-star-1.v yosys-always_display-star-2.v 2245s + test_always_display clk_en -DEVENT_CLK -DCOND_EN 2245s + local subtest=clk_en 2245s + shift 2245s + ../../yosys -p 'read_verilog -DEVENT_CLK -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_en-1.v 2245s + ../../yosys -p 'read_verilog yosys-always_display-clk_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_en-2.v 2245s + diff yosys-always_display-clk_en-1.v yosys-always_display-clk_en-2.v 2245s + test_always_display clk_rst_en -DEVENT_CLK_RST -DCOND_EN 2245s + local subtest=clk_rst_en 2245s + shift 2245s + ../../yosys -p 'read_verilog -DEVENT_CLK_RST -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst_en-1.v 2245s + ../../yosys -p 'read_verilog yosys-always_display-clk_rst_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst_en-2.v 2245s + diff yosys-always_display-clk_rst_en-1.v yosys-always_display-clk_rst_en-2.v 2245s + test_always_display star_en -DEVENT_STAR -DCOND_EN 2245s + local subtest=star_en 2245s + shift 2245s + ../../yosys -p 'read_verilog -DEVENT_STAR -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star_en-1.v 2245s + ../../yosys -p 'read_verilog yosys-always_display-star_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star_en-2.v 2245s + diff yosys-always_display-star_en-1.v yosys-always_display-star_en-2.v 2245s + test_roundtrip dec_unsigned -DBASE_DEC -DSIGN= 2245s + local subtest=dec_unsigned 2245s + shift 2245s + ../../yosys -p 'read_verilog -DBASE_DEC -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-dec_unsigned-1.v 2245s + ../../yosys -p 'read_verilog yosys-roundtrip-dec_unsigned-1.v; proc; clean' -o yosys-roundtrip-dec_unsigned-2.v 2245s + diff yosys-roundtrip-dec_unsigned-1.v yosys-roundtrip-dec_unsigned-2.v 2245s + iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned roundtrip.v roundtrip_tb.v 2245s + ./iverilog-roundtrip-dec_unsigned 2245s + iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned-1 yosys-roundtrip-dec_unsigned-1.v roundtrip_tb.v 2245s + ./iverilog-roundtrip-dec_unsigned-1 2245s + iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned-2 yosys-roundtrip-dec_unsigned-2.v roundtrip_tb.v 2245s + ./iverilog-roundtrip-dec_unsigned-1 2245s + diff iverilog-roundtrip-dec_unsigned.log iverilog-roundtrip-dec_unsigned-1.log 2245s + diff iverilog-roundtrip-dec_unsigned-1.log iverilog-roundtrip-dec_unsigned-2.log 2245s + test_roundtrip dec_signed -DBASE_DEC -DSIGN=signed 2245s + local subtest=dec_signed 2245s + shift 2245s + ../../yosys -p 'read_verilog -DBASE_DEC -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-dec_signed-1.v 2245s + ../../yosys -p 'read_verilog yosys-roundtrip-dec_signed-1.v; proc; clean' -o yosys-roundtrip-dec_signed-2.v 2245s + diff yosys-roundtrip-dec_signed-1.v yosys-roundtrip-dec_signed-2.v 2245s + iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed roundtrip.v roundtrip_tb.v 2245s + ./iverilog-roundtrip-dec_signed 2245s + iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed-1 yosys-roundtrip-dec_signed-1.v roundtrip_tb.v 2245s + ./iverilog-roundtrip-dec_signed-1 2245s + iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed-2 yosys-roundtrip-dec_signed-2.v roundtrip_tb.v 2245s + ./iverilog-roundtrip-dec_signed-1 2245s + diff iverilog-roundtrip-dec_signed.log iverilog-roundtrip-dec_signed-1.log 2245s + diff iverilog-roundtrip-dec_signed-1.log iverilog-roundtrip-dec_signed-2.log 2245s + test_roundtrip hex_unsigned -DBASE_HEX -DSIGN= 2245s + local subtest=hex_unsigned 2245s + shift 2245s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-hex_unsigned-1.v 2245s + ../../yosys -p 'read_verilog yosys-roundtrip-hex_unsigned-1.v; proc; clean' -o yosys-roundtrip-hex_unsigned-2.v 2245s xprop_dffe_3npd: ok 2245s xprop_dffe_3npd: ok 2245s done 2245s make[1]: Leaving directory '/tmp/autopkgtest.l2kRn3/build.e8a/src/tests/xprop' 2245s cd tests/fmt && bash run-test.sh 2245s 2245s /----------------------------------------------------------------------------\ 2245s | | 2245s | yosys -- Yosys Open SYnthesis Suite | 2245s | | 2245s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2245s | | 2245s | Permission to use, copy, modify, and/or distribute this software for any | 2245s | purpose with or without fee is hereby granted, provided that the above | 2245s | copyright notice and this permission notice appear in all copies. | 2245s | | 2245s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2245s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2245s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2245s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2245s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2245s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2245s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2245s | | 2245s \----------------------------------------------------------------------------/ 2245s 2245s Yosys 0.33 (git sha1 2584903a060) 2245s 2245s 2245s -- Running command `read_verilog -DEVENT_CLK always_display.v; proc; opt_expr -mux_bool; clean' -- 2245s 2245s 1. Executing Verilog-2005 frontend: always_display.v 2245s Parsing Verilog input from `always_display.v' to AST representation. 2245s Generating RTLIL representation for module `\m'. 2245s Successfully finished Verilog frontend. 2245s 2245s 2. Executing PROC pass (convert processes to netlists). 2245s 2245s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Cleaned up 0 empty switches. 2245s 2245s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2245s Removed a total of 0 dead cases. 2245s 2245s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2245s Removed 1 redundant assignment. 2245s Promoted 1 assignment to connection. 2245s 2245s 2.4. Executing PROC_INIT pass (extract init attributes). 2245s 2245s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2245s 2245s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2245s Converted 0 switches. 2245s 2245s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2245s Creating decoders for process `\m.$proc$always_display.v:4$1'. 2245s 2245s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2245s 2245s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2245s 2245s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2245s 2245s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Removing empty process `m.$proc$always_display.v:4$1'. 2245s Cleaned up 0 empty switches. 2245s 2245s 2.12. Executing OPT_EXPR pass (perform const folding). 2245s Optimizing module m. 2245s 2245s 3. Executing OPT_EXPR pass (perform const folding). 2245s Optimizing module m. 2245s Removed 0 unused cells and 1 unused wires. 2245s 2245s -- Writing to `yosys-always_display-clk-1.v' using backend `verilog' -- 2245s 2245s 4. Executing Verilog backend. 2245s 2245s 4.1. Executing BMUXMAP pass. 2245s 2245s 4.2. Executing DEMUXMAP pass. 2245s Dumping module `\m'. 2245s 2245s End of script. Logfile hash: 0de35d2746, CPU: user 0.01s system 0.00s, MEM: 10.00 MB peak 2245s Yosys 0.33 (git sha1 2584903a060) 2245s Time spent: 37% 2x opt_expr (0 sec), 25% 1x clean (0 sec), ... 2245s 2245s /----------------------------------------------------------------------------\ 2245s | | 2245s | yosys -- Yosys Open SYnthesis Suite | 2245s | | 2245s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2245s | | 2245s | Permission to use, copy, modify, and/or distribute this software for any | 2245s | purpose with or without fee is hereby granted, provided that the above | 2245s | copyright notice and this permission notice appear in all copies. | 2245s | | 2245s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2245s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2245s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2245s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2245s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2245s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2245s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2245s | | 2245s \----------------------------------------------------------------------------/ 2245s 2245s Yosys 0.33 (git sha1 2584903a060) 2245s 2245s 2245s -- Running command `read_verilog yosys-always_display-clk-1.v; proc; opt_expr -mux_bool; clean' -- 2245s 2245s 1. Executing Verilog-2005 frontend: yosys-always_display-clk-1.v 2245s Parsing Verilog input from `yosys-always_display-clk-1.v' to AST representation. 2245s Generating RTLIL representation for module `\m'. 2245s Successfully finished Verilog frontend. 2245s 2245s 2. Executing PROC pass (convert processes to netlists). 2245s 2245s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk-1.v:18$1'. 2245s Cleaned up 1 empty switch. 2245s 2245s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2245s Removed a total of 0 dead cases. 2245s 2245s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2245s Removed 1 redundant assignment. 2245s Promoted 1 assignment to connection. 2245s 2245s 2.4. Executing PROC_INIT pass (extract init attributes). 2245s 2245s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2245s 2245s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2245s Converted 0 switches. 2245s 2245s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2245s Creating decoders for process `\m.$proc$yosys-always_display-clk-1.v:18$1'. 2245s 2245s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2245s 2245s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2245s 2245s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2245s 2245s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Removing empty process `m.$proc$yosys-always_display-clk-1.v:18$1'. 2245s Cleaned up 0 empty switches. 2245s 2245s 2.12. Executing OPT_EXPR pass (perform const folding). 2245s Optimizing module m. 2245s 2245s 3. Executing OPT_EXPR pass (perform const folding). 2245s Optimizing module m. 2245s Removed 0 unused cells and 1 unused wires. 2245s 2245s -- Writing to `yosys-always_display-clk-2.v' using backend `verilog' -- 2245s 2245s 4. Executing Verilog backend. 2245s 2245s 4.1. Executing BMUXMAP pass. 2245s 2245s 4.2. Executing DEMUXMAP pass. 2245s Dumping module `\m'. 2245s 2245s End of script. Logfile hash: e35e8bb689, CPU: user 0.01s system 0.00s, MEM: 10.00 MB peak 2245s Yosys 0.33 (git sha1 2584903a060) 2245s Time spent: 37% 2x opt_expr (0 sec), 25% 1x clean (0 sec), ... 2245s 2245s /----------------------------------------------------------------------------\ 2245s | | 2245s | yosys -- Yosys Open SYnthesis Suite | 2245s | | 2245s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2245s | | 2245s | Permission to use, copy, modify, and/or distribute this software for any | 2245s | purpose with or without fee is hereby granted, provided that the above | 2245s | copyright notice and this permission notice appear in all copies. | 2245s | | 2245s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2245s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2245s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2245s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2245s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2245s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2245s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2245s | | 2245s \----------------------------------------------------------------------------/ 2245s 2245s Yosys 0.33 (git sha1 2584903a060) 2245s 2245s 2245s -- Running command `read_verilog -DEVENT_CLK_RST always_display.v; proc; opt_expr -mux_bool; clean' -- 2245s 2245s 1. Executing Verilog-2005 frontend: always_display.v 2245s Parsing Verilog input from `always_display.v' to AST representation. 2245s Generating RTLIL representation for module `\m'. 2245s Successfully finished Verilog frontend. 2245s 2245s 2. Executing PROC pass (convert processes to netlists). 2245s 2245s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Cleaned up 0 empty switches. 2245s 2245s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2245s Removed a total of 0 dead cases. 2245s 2245s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2245s Removed 1 redundant assignment. 2245s Promoted 1 assignment to connection. 2245s 2245s 2.4. Executing PROC_INIT pass (extract init attributes). 2245s 2245s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2245s 2245s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2245s Converted 0 switches. 2245s 2245s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2245s Creating decoders for process `\m.$proc$always_display.v:7$1'. 2245s 2245s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2245s 2245s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2245s 2245s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2245s 2245s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Removing empty process `m.$proc$always_display.v:7$1'. 2245s Cleaned up 0 empty switches. 2245s 2245s 2.12. Executing OPT_EXPR pass (perform const folding). 2245s Optimizing module m. 2245s 2245s 3. Executing OPT_EXPR pass (perform const folding). 2245s Optimizing module m. 2245s Removed 0 unused cells and 1 unused wires. 2245s 2245s -- Writing to `yosys-always_display-clk_rst-1.v' using backend `verilog' -- 2245s 2245s 4. Executing Verilog backend. 2245s 2245s 4.1. Executing BMUXMAP pass. 2245s 2245s 4.2. Executing DEMUXMAP pass. 2245s Dumping module `\m'. 2245s 2245s End of script. Logfile hash: c95608ddf0, CPU: user 0.01s system 0.00s, MEM: 10.00 MB peak 2245s Yosys 0.33 (git sha1 2584903a060) 2245s Time spent: 39% 2x opt_expr (0 sec), 25% 1x clean (0 sec), ... 2245s 2245s /----------------------------------------------------------------------------\ 2245s | | 2245s | yosys -- Yosys Open SYnthesis Suite | 2245s | | 2245s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2245s | | 2245s | Permission to use, copy, modify, and/or distribute this software for any | 2245s | purpose with or without fee is hereby granted, provided that the above | 2245s | copyright notice and this permission notice appear in all copies. | 2245s | | 2245s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2245s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2245s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2245s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2245s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2245s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2245s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2245s | | 2245s \----------------------------------------------------------------------------/ 2245s 2245s Yosys 0.33 (git sha1 2584903a060) 2245s 2245s 2245s -- Running command `read_verilog yosys-always_display-clk_rst-1.v; proc; opt_expr -mux_bool; clean' -- 2245s 2245s 1. Executing Verilog-2005 frontend: yosys-always_display-clk_rst-1.v 2245s Parsing Verilog input from `yosys-always_display-clk_rst-1.v' to AST representation. 2245s Generating RTLIL representation for module `\m'. 2245s Successfully finished Verilog frontend. 2245s 2245s 2. Executing PROC pass (convert processes to netlists). 2245s 2245s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_rst-1.v:18$1'. 2245s Cleaned up 1 empty switch. 2245s 2245s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2245s Removed a total of 0 dead cases. 2245s 2245s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2245s Removed 1 redundant assignment. 2245s Promoted 1 assignment to connection. 2245s 2245s 2.4. Executing PROC_INIT pass (extract init attributes). 2245s 2245s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2245s 2245s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2245s Converted 0 switches. 2245s 2245s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2245s Creating decoders for process `\m.$proc$yosys-always_display-clk_rst-1.v:18$1'. 2245s 2245s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2245s 2245s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2245s 2245s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2245s 2245s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Removing empty process `m.$proc$yosys-always_display-clk_rst-1.v:18$1'. 2245s Cleaned up 0 empty switches. 2245s 2245s 2.12. Executing OPT_EXPR pass (perform const folding). 2245s Optimizing module m. 2245s 2245s 3. Executing OPT_EXPR pass (perform const folding). 2245s Optimizing module m. 2245s Removed 0 unused cells and 1 unused wires. 2245s 2245s -- Writing to `yosys-always_display-clk_rst-2.v' using backend `verilog' -- 2245s 2245s 4. Executing Verilog backend. 2245s 2245s 4.1. Executing BMUXMAP pass. 2245s 2245s 4.2. Executing DEMUXMAP pass. 2245s Dumping module `\m'. 2245s 2245s End of script. Logfile hash: faf50513c3, CPU: user 0.01s system 0.00s, MEM: 10.00 MB peak 2245s Yosys 0.33 (git sha1 2584903a060) 2245s Time spent: 36% 2x opt_expr (0 sec), 25% 1x clean (0 sec), ... 2245s 2245s /----------------------------------------------------------------------------\ 2245s | | 2245s | yosys -- Yosys Open SYnthesis Suite | 2245s | | 2245s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2245s | | 2245s | Permission to use, copy, modify, and/or distribute this software for any | 2245s | purpose with or without fee is hereby granted, provided that the above | 2245s | copyright notice and this permission notice appear in all copies. | 2245s | | 2245s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2245s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2245s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2245s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2245s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2245s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2245s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2245s | | 2245s \----------------------------------------------------------------------------/ 2245s 2245s Yosys 0.33 (git sha1 2584903a060) 2245s 2245s 2245s -- Running command `read_verilog -DEVENT_STAR always_display.v; proc; opt_expr -mux_bool; clean' -- 2245s 2245s 1. Executing Verilog-2005 frontend: always_display.v 2245s Parsing Verilog input from `always_display.v' to AST representation. 2245s Generating RTLIL representation for module `\m'. 2245s Successfully finished Verilog frontend. 2245s 2245s 2. Executing PROC pass (convert processes to netlists). 2245s 2245s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Cleaned up 0 empty switches. 2245s 2245s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2245s Removed a total of 0 dead cases. 2245s 2245s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2245s Removed 1 redundant assignment. 2245s Promoted 1 assignment to connection. 2245s 2245s 2.4. Executing PROC_INIT pass (extract init attributes). 2245s 2245s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2245s 2245s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2245s Converted 0 switches. 2245s 2245s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2245s Creating decoders for process `\m.$proc$always_display.v:10$1'. 2245s 2245s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2245s 2245s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2245s 2245s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2245s 2245s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Removing empty process `m.$proc$always_display.v:10$1'. 2245s Cleaned up 0 empty switches. 2245s 2245s 2.12. Executing OPT_EXPR pass (perform const folding). 2245s Optimizing module m. 2245s 2245s 3. Executing OPT_EXPR pass (perform const folding). 2245s Optimizing module m. 2245s Removed 0 unused cells and 1 unused wires. 2245s 2245s -- Writing to `yosys-always_display-star-1.v' using backend `verilog' -- 2245s 2245s 4. Executing Verilog backend. 2245s 2245s 4.1. Executing BMUXMAP pass. 2245s 2245s 4.2. Executing DEMUXMAP pass. 2245s Dumping module `\m'. 2245s 2245s End of script. Logfile hash: 7b2c5274a5, CPU: user 0.01s system 0.00s, MEM: 10.00 MB peak 2245s Yosys 0.33 (git sha1 2584903a060) 2245s Time spent: 38% 2x opt_expr (0 sec), 25% 1x clean (0 sec), ... 2245s 2245s /----------------------------------------------------------------------------\ 2245s | | 2245s | yosys -- Yosys Open SYnthesis Suite | 2245s | | 2245s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2245s | | 2245s | Permission to use, copy, modify, and/or distribute this software for any | 2245s | purpose with or without fee is hereby granted, provided that the above | 2245s | copyright notice and this permission notice appear in all copies. | 2245s | | 2245s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2245s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2245s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2245s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2245s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2245s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2245s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2245s | | 2245s \----------------------------------------------------------------------------/ 2245s 2245s Yosys 0.33 (git sha1 2584903a060) 2245s 2245s 2245s -- Running command `read_verilog yosys-always_display-star-1.v; proc; opt_expr -mux_bool; clean' -- 2245s 2245s 1. Executing Verilog-2005 frontend: yosys-always_display-star-1.v 2245s Parsing Verilog input from `yosys-always_display-star-1.v' to AST representation. 2245s Generating RTLIL representation for module `\m'. 2245s Successfully finished Verilog frontend. 2245s 2245s 2. Executing PROC pass (convert processes to netlists). 2245s 2245s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-star-1.v:18$1'. 2245s Cleaned up 1 empty switch. 2245s 2245s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2245s Removed a total of 0 dead cases. 2245s 2245s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2245s Removed 1 redundant assignment. 2245s Promoted 1 assignment to connection. 2245s 2245s 2.4. Executing PROC_INIT pass (extract init attributes). 2245s 2245s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2245s 2245s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2245s Converted 0 switches. 2245s 2245s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2245s Creating decoders for process `\m.$proc$yosys-always_display-star-1.v:18$1'. 2245s 2245s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2245s 2245s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2245s 2245s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2245s 2245s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Removing empty process `m.$proc$yosys-always_display-star-1.v:18$1'. 2245s Cleaned up 0 empty switches. 2245s 2245s 2.12. Executing OPT_EXPR pass (perform const folding). 2245s Optimizing module m. 2245s 2245s 3. Executing OPT_EXPR pass (perform const folding). 2245s Optimizing module m. 2245s Removed 0 unused cells and 1 unused wires. 2245s 2245s -- Writing to `yosys-always_display-star-2.v' using backend `verilog' -- 2245s 2245s 4. Executing Verilog backend. 2245s 2245s 4.1. Executing BMUXMAP pass. 2245s 2245s 4.2. Executing DEMUXMAP pass. 2245s Dumping module `\m'. 2245s 2245s End of script. Logfile hash: 8979c5de0b, CPU: user 0.00s system 0.00s, MEM: 10.00 MB peak 2245s Yosys 0.33 (git sha1 2584903a060) 2245s Time spent: 38% 2x opt_expr (0 sec), 24% 1x clean (0 sec), ... 2245s 2245s /----------------------------------------------------------------------------\ 2245s | | 2245s | yosys -- Yosys Open SYnthesis Suite | 2245s | | 2245s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2245s | | 2245s | Permission to use, copy, modify, and/or distribute this software for any | 2245s | purpose with or without fee is hereby granted, provided that the above | 2245s | copyright notice and this permission notice appear in all copies. | 2245s | | 2245s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2245s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2245s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2245s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2245s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2245s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2245s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2245s | | 2245s \----------------------------------------------------------------------------/ 2245s 2245s Yosys 0.33 (git sha1 2584903a060) 2245s 2245s 2245s -- Running command `read_verilog -DEVENT_CLK -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -- 2245s 2245s 1. Executing Verilog-2005 frontend: always_display.v 2245s Parsing Verilog input from `always_display.v' to AST representation. 2245s Generating RTLIL representation for module `\m'. 2245s Successfully finished Verilog frontend. 2245s 2245s 2. Executing PROC pass (convert processes to netlists). 2245s 2245s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Cleaned up 0 empty switches. 2245s 2245s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2245s Removed a total of 0 dead cases. 2245s 2245s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2245s Removed 0 redundant assignments. 2245s Promoted 0 assignments to connections. 2245s 2245s 2.4. Executing PROC_INIT pass (extract init attributes). 2245s 2245s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2245s 2245s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2245s Converted 0 switches. 2245s 2245s 2245s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2245s Creating decoders for process `\m.$proc$always_display.v:4$1'. 2245s 1/1: $display$always_display.v:15$2_EN 2245s 2245s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2245s 2245s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2245s 2245s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2245s 2245s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:4$1'. 2245s Removing empty process `m.$proc$always_display.v:4$1'. 2245s Cleaned up 1 empty switch. 2245s 2245s 2.12. Executing OPT_EXPR pass (perform const folding). 2245s Optimizing module m. 2245s 2245s 3. Executing OPT_EXPR pass (perform const folding). 2245s Optimizing module m. 2245s 2245s Removed 0 unused cells and 3 unused wires. 2245s 2245s -- Writing to `yosys-always_display-clk_en-1.v' using backend `verilog' -- 2245s 2245s 4. Executing Verilog backend. 2245s 2245s 4.1. Executing BMUXMAP pass. 2245s 2245s 4.2. Executing DEMUXMAP pass. 2245s Dumping module `\m'. 2245s 2245s End of script. Logfile hash: 4f8a3b339c, CPU: user 0.01s system 0.00s, MEM: 12.00 MB peak 2245s Yosys 0.33 (git sha1 2584903a060) 2245s Time spent: 41% 2x opt_expr (0 sec), 24% 1x clean (0 sec), ... 2245s 2245s /----------------------------------------------------------------------------\ 2245s | | 2245s | yosys -- Yosys Open SYnthesis Suite | 2245s | | 2245s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2245s | | 2245s | Permission to use, copy, modify, and/or distribute this software for any | 2245s | purpose with or without fee is hereby granted, provided that the above | 2245s | copyright notice and this permission notice appear in all copies. | 2245s | | 2245s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2245s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2245s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2245s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2245s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2245s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2245s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2245s | | 2245s \----------------------------------------------------------------------------/ 2245s 2245s Yosys 0.33 (git sha1 2584903a060) 2245s 2245s 2245s -- Running command `read_verilog yosys-always_display-clk_en-1.v; proc; opt_expr -mux_bool; clean' -- 2245s 2245s 1. Executing Verilog-2005 frontend: yosys-always_display-clk_en-1.v 2245s Parsing Verilog input from `yosys-always_display-clk_en-1.v' to AST representation. 2245s Generating RTLIL representation for module `\m'. 2245s Successfully finished Verilog frontend. 2245s 2245s 2. Executing PROC pass (convert processes to netlists). 2245s 2245s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Cleaned up 0 empty switches. 2245s 2245s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2245s Removed a total of 0 dead cases. 2245s 2245s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2245s Removed 0 redundant assignments. 2245s Promoted 0 assignments to connections. 2245s 2245s 2.4. Executing PROC_INIT pass (extract init attributes). 2245s 2245s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2245s 2245s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2245s Converted 0 switches. 2245s 2245s 2245s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2245s Creating decoders for process `\m.$proc$yosys-always_display-clk_en-1.v:18$1'. 2245s 1/1: $write$yosys-always_display-clk_en-1.v:20$2_EN 2245s 2245s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2245s 2245s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2245s 2245s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2245s 2245s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_en-1.v:18$1'. 2245s Removing empty process `m.$proc$yosys-always_display-clk_en-1.v:18$1'. 2245s Cleaned up 1 empty switch. 2245s 2245s 2.12. Executing OPT_EXPR pass (perform const folding). 2245s Optimizing module m. 2245s 2245s 3. Executing OPT_EXPR pass (perform const folding). 2245s Optimizing module m. 2245s 2245s Removed 0 unused cells and 3 unused wires. 2245s 2245s -- Writing to `yosys-always_display-clk_en-2.v' using backend `verilog' -- 2245s 2245s 4. Executing Verilog backend. 2245s 2245s 4.1. Executing BMUXMAP pass. 2245s 2245s 4.2. Executing DEMUXMAP pass. 2245s Dumping module `\m'. 2245s 2245s End of script. Logfile hash: 51e7fa3902, CPU: user 0.01s system 0.00s, MEM: 12.00 MB peak 2245s Yosys 0.33 (git sha1 2584903a060) 2245s Time spent: 40% 2x opt_expr (0 sec), 23% 1x clean (0 sec), ... 2245s 2245s /----------------------------------------------------------------------------\ 2245s | | 2245s | yosys -- Yosys Open SYnthesis Suite | 2245s | | 2245s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2245s | | 2245s | Permission to use, copy, modify, and/or distribute this software for any | 2245s | purpose with or without fee is hereby granted, provided that the above | 2245s | copyright notice and this permission notice appear in all copies. | 2245s | | 2245s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2245s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2245s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2245s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2245s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2245s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2245s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2245s | | 2245s \----------------------------------------------------------------------------/ 2245s 2245s Yosys 0.33 (git sha1 2584903a060) 2245s 2245s 2245s -- Running command `read_verilog -DEVENT_CLK_RST -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -- 2245s 2245s 1. Executing Verilog-2005 frontend: always_display.v 2245s Parsing Verilog input from `always_display.v' to AST representation. 2245s Generating RTLIL representation for module `\m'. 2245s Successfully finished Verilog frontend. 2245s 2245s 2. Executing PROC pass (convert processes to netlists). 2245s 2245s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Cleaned up 0 empty switches. 2245s 2245s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2245s Removed a total of 0 dead cases. 2245s 2245s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2245s Removed 0 redundant assignments. 2245s Promoted 0 assignments to connections. 2245s 2245s 2.4. Executing PROC_INIT pass (extract init attributes). 2245s 2245s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2245s 2245s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2245s Converted 0 switches. 2245s 2245s 2245s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2245s Creating decoders for process `\m.$proc$always_display.v:7$1'. 2245s 1/1: $display$always_display.v:15$2_EN 2245s 2245s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2245s 2245s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2245s 2245s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2245s 2245s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:7$1'. 2245s Removing empty process `m.$proc$always_display.v:7$1'. 2245s Cleaned up 1 empty switch. 2245s 2245s 2.12. Executing OPT_EXPR pass (perform const folding). 2245s Optimizing module m. 2245s 2245s 3. Executing OPT_EXPR pass (perform const folding). 2245s Optimizing module m. 2245s 2245s Removed 0 unused cells and 3 unused wires. 2245s 2245s -- Writing to `yosys-always_display-clk_rst_en-1.v' using backend `verilog' -- 2245s 2245s 4. Executing Verilog backend. 2245s 2245s 4.1. Executing BMUXMAP pass. 2245s 2245s 4.2. Executing DEMUXMAP pass. 2245s Dumping module `\m'. 2245s 2245s End of script. Logfile hash: f9b4876f33, CPU: user 0.01s system 0.00s, MEM: 12.00 MB peak 2245s Yosys 0.33 (git sha1 2584903a060) 2245s Time spent: 41% 2x opt_expr (0 sec), 24% 1x clean (0 sec), ... 2245s 2245s /----------------------------------------------------------------------------\ 2245s | | 2245s | yosys -- Yosys Open SYnthesis Suite | 2245s | | 2245s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2245s | | 2245s | Permission to use, copy, modify, and/or distribute this software for any | 2245s | purpose with or without fee is hereby granted, provided that the above | 2245s | copyright notice and this permission notice appear in all copies. | 2245s | | 2245s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2245s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2245s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2245s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2245s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2245s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2245s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2245s | | 2245s \----------------------------------------------------------------------------/ 2245s 2245s Yosys 0.33 (git sha1 2584903a060) 2245s 2245s 2245s -- Running command `read_verilog yosys-always_display-clk_rst_en-1.v; proc; opt_expr -mux_bool; clean' -- 2245s 2245s 1. Executing Verilog-2005 frontend: yosys-always_display-clk_rst_en-1.v 2245s Parsing Verilog input from `yosys-always_display-clk_rst_en-1.v' to AST representation. 2245s Generating RTLIL representation for module `\m'. 2245s Successfully finished Verilog frontend. 2245s 2245s 2. Executing PROC pass (convert processes to netlists). 2245s 2245s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Cleaned up 0 empty switches. 2245s 2245s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2245s Removed a total of 0 dead cases. 2245s 2245s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2245s Removed 0 redundant assignments. 2245s Promoted 0 assignments to connections. 2245s 2245s 2.4. Executing PROC_INIT pass (extract init attributes). 2245s 2245s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2245s 2245s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2245s Converted 0 switches. 2245s 2245s 2245s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2245s Creating decoders for process `\m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'. 2245s 1/1: $write$yosys-always_display-clk_rst_en-1.v:20$2_EN 2245s 2245s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2245s 2245s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2245s 2245s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2245s 2245s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'. 2245s Removing empty process `m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'. 2245s Cleaned up 1 empty switch. 2245s 2245s 2.12. Executing OPT_EXPR pass (perform const folding). 2245s Optimizing module m. 2245s 2245s 3. Executing OPT_EXPR pass (perform const folding). 2245s Optimizing module m. 2245s 2245s Removed 0 unused cells and 3 unused wires. 2245s 2245s -- Writing to `yosys-always_display-clk_rst_en-2.v' using backend `verilog' -- 2245s 2245s 4. Executing Verilog backend. 2245s 2245s 4.1. Executing BMUXMAP pass. 2245s 2245s 4.2. Executing DEMUXMAP pass. 2245s Dumping module `\m'. 2245s 2245s End of script. Logfile hash: 0c4b4eaa9c, CPU: user 0.00s system 0.00s, MEM: 12.00 MB peak 2245s Yosys 0.33 (git sha1 2584903a060) 2245s Time spent: 39% 2x opt_expr (0 sec), 23% 1x clean (0 sec), ... 2245s 2245s /----------------------------------------------------------------------------\ 2245s | | 2245s | yosys -- Yosys Open SYnthesis Suite | 2245s | | 2245s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2245s | | 2245s | Permission to use, copy, modify, and/or distribute this software for any | 2245s | purpose with or without fee is hereby granted, provided that the above | 2245s | copyright notice and this permission notice appear in all copies. | 2245s | | 2245s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2245s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2245s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2245s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2245s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2245s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2245s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2245s | | 2245s \----------------------------------------------------------------------------/ 2245s 2245s Yosys 0.33 (git sha1 2584903a060) 2245s 2245s 2245s -- Running command `read_verilog -DEVENT_STAR -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -- 2245s 2245s 1. Executing Verilog-2005 frontend: always_display.v 2245s Parsing Verilog input from `always_display.v' to AST representation. 2245s Generating RTLIL representation for module `\m'. 2245s Successfully finished Verilog frontend. 2245s 2245s 2. Executing PROC pass (convert processes to netlists). 2245s 2245s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Cleaned up 0 empty switches. 2245s 2245s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2245s Removed a total of 0 dead cases. 2245s 2245s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2245s Removed 0 redundant assignments. 2245s Promoted 0 assignments to connections. 2245s 2245s 2.4. Executing PROC_INIT pass (extract init attributes). 2245s 2245s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2245s 2245s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2245s Converted 0 switches. 2245s 2245s 2245s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2245s Creating decoders for process `\m.$proc$always_display.v:10$1'. 2245s 1/1: $display$always_display.v:15$2_EN 2245s 2245s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2245s 2245s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2245s 2245s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2245s 2245s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:10$1'. 2245s Removing empty process `m.$proc$always_display.v:10$1'. 2245s Cleaned up 1 empty switch. 2245s 2245s 2.12. Executing OPT_EXPR pass (perform const folding). 2245s Optimizing module m. 2245s 2245s 3. Executing OPT_EXPR pass (perform const folding). 2245s Optimizing module m. 2245s 2245s Removed 0 unused cells and 3 unused wires. 2245s 2245s -- Writing to `yosys-always_display-star_en-1.v' using backend `verilog' -- 2245s 2245s 4. Executing Verilog backend. 2245s 2245s 4.1. Executing BMUXMAP pass. 2245s 2245s 4.2. Executing DEMUXMAP pass. 2245s Dumping module `\m'. 2245s 2245s End of script. Logfile hash: d6a7335726, CPU: user 0.00s system 0.00s, MEM: 10.00 MB peak 2245s Yosys 0.33 (git sha1 2584903a060) 2245s Time spent: 42% 2x opt_expr (0 sec), 24% 1x clean (0 sec), ... 2245s 2245s /----------------------------------------------------------------------------\ 2245s | | 2245s | yosys -- Yosys Open SYnthesis Suite | 2245s | | 2245s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2245s | | 2245s | Permission to use, copy, modify, and/or distribute this software for any | 2245s | purpose with or without fee is hereby granted, provided that the above | 2245s | copyright notice and this permission notice appear in all copies. | 2245s | | 2245s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2245s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2245s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2245s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2245s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2245s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2245s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2245s | | 2245s \----------------------------------------------------------------------------/ 2245s 2245s Yosys 0.33 (git sha1 2584903a060) 2245s 2245s 2245s -- Running command `read_verilog yosys-always_display-star_en-1.v; proc; opt_expr -mux_bool; clean' -- 2245s 2245s 1. Executing Verilog-2005 frontend: yosys-always_display-star_en-1.v 2245s Parsing Verilog input from `yosys-always_display-star_en-1.v' to AST representation. 2245s Generating RTLIL representation for module `\m'. 2245s Successfully finished Verilog frontend. 2245s 2245s 2. Executing PROC pass (convert processes to netlists). 2245s 2245s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Cleaned up 0 empty switches. 2245s 2245s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2245s Removed a total of 0 dead cases. 2245s 2245s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2245s Removed 0 redundant assignments. 2245s Promoted 0 assignments to connections. 2245s 2245s 2.4. Executing PROC_INIT pass (extract init attributes). 2245s 2245s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2245s 2245s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2245s Converted 0 switches. 2245s 2245s 2245s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2245s Creating decoders for process `\m.$proc$yosys-always_display-star_en-1.v:18$1'. 2245s 1/1: $write$yosys-always_display-star_en-1.v:20$2_EN 2245s 2245s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2245s 2245s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2245s 2245s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2245s 2245s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-star_en-1.v:18$1'. 2245s Removing empty process `m.$proc$yosys-always_display-star_en-1.v:18$1'. 2245s Cleaned up 1 empty switch. 2245s 2245s 2.12. Executing OPT_EXPR pass (perform const folding). 2245s Optimizing module m. 2245s 2245s 3. Executing OPT_EXPR pass (perform const folding). 2245s Optimizing module m. 2245s 2245s Removed 0 unused cells and 3 unused wires. 2245s 2245s -- Writing to `yosys-always_display-star_en-2.v' using backend `verilog' -- 2245s 2245s 4. Executing Verilog backend. 2245s 2245s 4.1. Executing BMUXMAP pass. 2245s 2245s 4.2. Executing DEMUXMAP pass. 2245s Dumping module `\m'. 2245s 2245s End of script. Logfile hash: 18895a2046, CPU: user 0.00s system 0.00s, MEM: 10.00 MB peak 2245s Yosys 0.33 (git sha1 2584903a060) 2245s Time spent: 40% 2x opt_expr (0 sec), 23% 1x clean (0 sec), ... 2245s 2245s /----------------------------------------------------------------------------\ 2245s | | 2245s | yosys -- Yosys Open SYnthesis Suite | 2245s | | 2245s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2245s | | 2245s | Permission to use, copy, modify, and/or distribute this software for any | 2245s | purpose with or without fee is hereby granted, provided that the above | 2245s | copyright notice and this permission notice appear in all copies. | 2245s | | 2245s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2245s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2245s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2245s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2245s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2245s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2245s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2245s | | 2245s \----------------------------------------------------------------------------/ 2245s 2245s Yosys 0.33 (git sha1 2584903a060) 2245s 2245s 2245s -- Running command `read_verilog -DBASE_DEC -DSIGN= roundtrip.v; proc; clean' -- 2245s 2245s 1. Executing Verilog-2005 frontend: roundtrip.v 2245s Parsing Verilog input from `roundtrip.v' to AST representation. 2245s Generating RTLIL representation for module `\m'. 2245s Successfully finished Verilog frontend. 2245s 2245s 2. Executing PROC pass (convert processes to netlists). 2245s 2245s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Cleaned up 0 empty switches. 2245s 2245s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2245s Removed a total of 0 dead cases. 2245s 2245s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2245s Removed 1 redundant assignment. 2245s Promoted 1 assignment to connection. 2245s 2245s 2.4. Executing PROC_INIT pass (extract init attributes). 2245s 2245s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2245s 2245s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2245s Converted 0 switches. 2245s 2245s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2245s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2245s 2245s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2245s 2245s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2245s 2245s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2245s 2245s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Removing empty process `m.$proc$roundtrip.v:3$1'. 2245s Cleaned up 0 empty switches. 2245s 2245s 2.12. Executing OPT_EXPR pass (perform const folding). 2245s Optimizing module m. 2245s Removed 0 unused cells and 1 unused wires. 2245s 2245s -- Writing to `yosys-roundtrip-dec_unsigned-1.v' using backend `verilog' -- 2245s 2245s 3. Executing Verilog backend. 2245s 2245s 3.1. Executing BMUXMAP pass. 2245s 2245s 3.2. Executing DEMUXMAP pass. 2245s Dumping module `\m'. 2245s 2245s End of script. Logfile hash: bfb187b86d, CPU: user 0.01s system 0.00s, MEM: 10.00 MB peak 2245s Yosys 0.33 (git sha1 2584903a060) 2245s Time spent: 31% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 2245s 2245s /----------------------------------------------------------------------------\ 2245s | | 2245s | yosys -- Yosys Open SYnthesis Suite | 2245s | | 2245s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2245s | | 2245s | Permission to use, copy, modify, and/or distribute this software for any | 2245s | purpose with or without fee is hereby granted, provided that the above | 2245s | copyright notice and this permission notice appear in all copies. | 2245s | | 2245s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2245s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2245s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2245s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2245s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2245s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2245s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2245s | | 2245s \----------------------------------------------------------------------------/ 2245s 2245s Yosys 0.33 (git sha1 2584903a060) 2245s 2245s 2245s -- Running command `read_verilog yosys-roundtrip-dec_unsigned-1.v; proc; clean' -- 2245s 2245s 1. Executing Verilog-2005 frontend: yosys-roundtrip-dec_unsigned-1.v 2245s Parsing Verilog input from `yosys-roundtrip-dec_unsigned-1.v' to AST representation. 2245s Generating RTLIL representation for module `\m'. 2245s Successfully finished Verilog frontend. 2245s 2245s 2. Executing PROC pass (convert processes to netlists). 2245s 2245s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'. 2245s Cleaned up 1 empty switch. 2245s 2245s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2245s Removed a total of 0 dead cases. 2245s 2245s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2245s Removed 1 redundant assignment. 2245s Promoted 1 assignment to connection. 2245s 2245s 2.4. Executing PROC_INIT pass (extract init attributes). 2245s 2245s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2245s 2245s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2245s Converted 0 switches. 2245s 2245s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2245s Creating decoders for process `\m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'. 2245s 2245s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2245s 2245s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2245s 2245s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2245s 2245s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Removing empty process `m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'. 2245s Cleaned up 0 empty switches. 2245s 2245s 2.12. Executing OPT_EXPR pass (perform const folding). 2245s Optimizing module m. 2245s Removed 0 unused cells and 1 unused wires. 2245s 2245s -- Writing to `yosys-roundtrip-dec_unsigned-2.v' using backend `verilog' -- 2245s 2245s 3. Executing Verilog backend. 2245s 2245s 3.1. Executing BMUXMAP pass. 2245s 2245s 3.2. Executing DEMUXMAP pass. 2245s Dumping module `\m'. 2245s 2245s End of script. Logfile hash: 4be9539e85, CPU: user 0.00s system 0.00s, MEM: 10.00 MB peak 2245s Yosys 0.33 (git sha1 2584903a060) 2245s Time spent: 32% 1x clean (0 sec), 19% 1x opt_expr (0 sec), ... 2245s 2245s /----------------------------------------------------------------------------\ 2245s | | 2245s | yosys -- Yosys Open SYnthesis Suite | 2245s | | 2245s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2245s | | 2245s | Permission to use, copy, modify, and/or distribute this software for any | 2245s | purpose with or without fee is hereby granted, provided that the above | 2245s | copyright notice and this permission notice appear in all copies. | 2245s | | 2245s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2245s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2245s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2245s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2245s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2245s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2245s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2245s | | 2245s \----------------------------------------------------------------------------/ 2245s 2245s Yosys 0.33 (git sha1 2584903a060) 2245s 2245s 2245s -- Running command `read_verilog -DBASE_DEC -DSIGN=signed roundtrip.v; proc; clean' -- 2245s 2245s 1. Executing Verilog-2005 frontend: roundtrip.v 2245s Parsing Verilog input from `roundtrip.v' to AST representation. 2245s Generating RTLIL representation for module `\m'. 2245s Successfully finished Verilog frontend. 2245s 2245s 2. Executing PROC pass (convert processes to netlists). 2245s 2245s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Cleaned up 0 empty switches. 2245s 2245s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2245s Removed a total of 0 dead cases. 2245s 2245s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2245s Removed 1 redundant assignment. 2245s Promoted 1 assignment to connection. 2245s 2245s 2.4. Executing PROC_INIT pass (extract init attributes). 2245s 2245s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2245s 2245s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2245s Converted 0 switches. 2245s 2245s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2245s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2245s 2245s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2245s 2245s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2245s 2245s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2245s 2245s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Removing empty process `m.$proc$roundtrip.v:3$1'. 2245s Cleaned up 0 empty switches. 2245s 2245s 2.12. Executing OPT_EXPR pass (perform const folding). 2245s Optimizing module m. 2245s Removed 0 unused cells and 1 unused wires. 2245s 2245s -- Writing to `yosys-roundtrip-dec_signed-1.v' using backend `verilog' -- 2245s 2245s 3. Executing Verilog backend. 2245s 2245s 3.1. Executing BMUXMAP pass. 2245s 2245s 3.2. Executing DEMUXMAP pass. 2245s Dumping module `\m'. 2245s 2245s End of script. Logfile hash: bbdfa5ca92, CPU: user 0.01s system 0.00s, MEM: 10.00 MB peak 2245s Yosys 0.33 (git sha1 2584903a060) 2245s Time spent: 32% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 2245s 2245s /----------------------------------------------------------------------------\ 2245s | | 2245s | yosys -- Yosys Open SYnthesis Suite | 2245s | | 2245s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2245s | | 2245s | Permission to use, copy, modify, and/or distribute this software for any | 2245s | purpose with or without fee is hereby granted, provided that the above | 2245s | copyright notice and this permission notice appear in all copies. | 2245s | | 2245s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2245s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2245s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2245s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2245s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2245s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2245s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2245s | | 2245s \----------------------------------------------------------------------------/ 2245s 2245s Yosys 0.33 (git sha1 2584903a060) 2245s 2245s 2245s -- Running command `read_verilog yosys-roundtrip-dec_signed-1.v; proc; clean' -- 2245s 2245s 1. Executing Verilog-2005 frontend: yosys-roundtrip-dec_signed-1.v 2245s Parsing Verilog input from `yosys-roundtrip-dec_signed-1.v' to AST representation. 2245s Generating RTLIL representation for module `\m'. 2245s Successfully finished Verilog frontend. 2245s 2245s 2. Executing PROC pass (convert processes to netlists). 2245s 2245s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'. 2245s Cleaned up 1 empty switch. 2245s 2245s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2245s Removed a total of 0 dead cases. 2245s 2245s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2245s Removed 1 redundant assignment. 2245s Promoted 1 assignment to connection. 2245s 2245s 2.4. Executing PROC_INIT pass (extract init attributes). 2245s 2245s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2245s 2245s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2245s Converted 0 switches. 2245s 2245s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2245s Creating decoders for process `\m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'. 2245s 2245s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2245s 2245s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2245s 2245s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2245s 2245s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Removing empty process `m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'. 2245s Cleaned up 0 empty switches. 2245s 2245s 2.12. Executing OPT_EXPR pass (perform const folding). 2245s Optimizing module m. 2245s Removed 0 unused cells and 1 unused wires. 2245s 2245s -- Writing to `yosys-roundtrip-dec_signed-2.v' using backend `verilog' -- 2245s 2245s 3. Executing Verilog backend. 2245s 2245s 3.1. Executing BMUXMAP pass. 2245s 2245s 3.2. Executing DEMUXMAP pass. 2245s Dumping module `\m'. 2245s 2245s End of script. Logfile hash: b233de92a6, CPU: user 0.01s system 0.00s, MEM: 10.00 MB peak 2245s Yosys 0.33 (git sha1 2584903a060) 2245s Time spent: 31% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 2245s 2245s /----------------------------------------------------------------------------\ 2245s | | 2245s | yosys -- Yosys Open SYnthesis Suite | 2245s | | 2245s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2245s | | 2245s | Permission to use, copy, modify, and/or distribute this software for any | 2245s | purpose with or without fee is hereby granted, provided that the above | 2245s | copyright notice and this permission notice appear in all copies. | 2245s | | 2245s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2245s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2245s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2245s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2245s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2245s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2245s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2245s | | 2245s \----------------------------------------------------------------------------/ 2245s 2245s Yosys 0.33 (git sha1 2584903a060) 2245s 2245s 2245s -- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -- 2245s 2245s 1. Executing Verilog-2005 frontend: roundtrip.v 2245s Parsing Verilog input from `roundtrip.v' to AST representation. 2245s Generating RTLIL representation for module `\m'. 2245s Successfully finished Verilog frontend. 2245s 2245s 2. Executing PROC pass (convert processes to netlists). 2245s 2245s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Cleaned up 0 empty switches. 2245s 2245s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2245s Removed a total of 0 dead cases. 2245s 2245s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2245s Removed 1 redundant assignment. 2245s Promoted 1 assignment to connection. 2245s 2245s 2.4. Executing PROC_INIT pass (extract init attributes). 2245s 2245s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2245s 2245s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2245s Converted 0 switches. 2245s 2245s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2245s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2245s 2245s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2245s 2245s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2245s 2245s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2245s 2245s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Removing empty process `m.$proc$roundtrip.v:3$1'. 2245s Cleaned up 0 empty switches. 2245s 2245s 2.12. Executing OPT_EXPR pass (perform const folding). 2245s Optimizing module m. 2245s Removed 0 unused cells and 1 unused wires. 2245s 2245s -- Writing to `yosys-roundtrip-hex_unsigned-1.v' using backend `verilog' -- 2245s 2245s 3. Executing Verilog backend. 2245s 2245s 3.1. Executing BMUXMAP pass. 2245s 2245s 3.2. Executing DEMUXMAP pass. 2245s Dumping module `\m'. 2245s 2245s End of script. Logfile hash: 2377f2e106, CPU: user 0.01s system 0.00s, MEM: 10.00 MB peak 2245s Yosys 0.33 (git sha1 2584903a060) 2245s Time spent: 32% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... 2245s 2245s /----------------------------------------------------------------------------\ 2245s | | 2245s | yosys -- Yosys Open SYnthesis Suite | 2245s | | 2245s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2245s | | 2245s | Permission to use, copy, modify, and/or distribute this software for any | 2245s | purpose with or without fee is hereby granted, provided that the above | 2245s | copyright notice and this permission notice appear in all copies. | 2245s | | 2245s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2245s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2245s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2245s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2245s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2245s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2245s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2245s | | 2245s \----------------------------------------------------------------------------/ 2245s 2245s Yosys 0.33 (git sha1 2584903a060) 2245s 2245s 2245s -- Running command `read_verilog yosys-roundtrip-hex_unsigned-1.v; proc; clean' -- 2245s 2245s 1. Executing Verilog-2005 frontend: yosys-roundtrip-hex_unsigned-1.v 2245s Parsing Verilog input from `yosys-roundtrip-hex_unsigned-1.v' to AST representation. 2245s Generating RTLIL representation for module `\m'. 2245s Successfully finished Verilog frontend. 2245s 2245s 2. Executing PROC pass (convert processes to netlists). 2245s 2245s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'. 2245s Cleaned up 1 empty switch. 2245s 2245s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2245s Removed a total of 0 dead cases. 2245s 2245s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2245s Removed 1 redundant assignment. 2245s Promoted 1 assignment to connection. 2245s 2245s 2.4. Executing PROC_INIT pass (extract init attributes). 2245s + diff yosys-roundtrip-hex_unsigned-1.v yosys-roundtrip-hex_unsigned-2.v 2245s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned roundtrip.v roundtrip_tb.v 2245s + ./iverilog-roundtrip-hex_unsigned 2245s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned-1 yosys-roundtrip-hex_unsigned-1.v roundtrip_tb.v 2245s + ./iverilog-roundtrip-hex_unsigned-1 2245s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned-2 yosys-roundtrip-hex_unsigned-2.v roundtrip_tb.v 2245s + ./iverilog-roundtrip-hex_unsigned-1 2245s + diff iverilog-roundtrip-hex_unsigned.log iverilog-roundtrip-hex_unsigned-1.log 2245s + diff iverilog-roundtrip-hex_unsigned-1.log iverilog-roundtrip-hex_unsigned-2.log 2245s + test_roundtrip hex_signed -DBASE_HEX -DSIGN=signed 2245s + local subtest=hex_signed 2245s + shift 2245s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-hex_signed-1.v 2245s + ../../yosys -p 'read_verilog yosys-roundtrip-hex_signed-1.v; proc; clean' -o yosys-roundtrip-hex_signed-2.v 2245s 2245s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2245s 2245s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2245s Converted 0 switches. 2245s 2245s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2245s Creating decoders for process `\m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'. 2245s 2245s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2245s 2245s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2245s 2245s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2245s 2245s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Removing empty process `m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'. 2245s Cleaned up 0 empty switches. 2245s 2245s 2.12. Executing OPT_EXPR pass (perform const folding). 2245s Optimizing module m. 2245s Removed 0 unused cells and 1 unused wires. 2245s 2245s -- Writing to `yosys-roundtrip-hex_unsigned-2.v' using backend `verilog' -- 2245s 2245s 3. Executing Verilog backend. 2245s 2245s 3.1. Executing BMUXMAP pass. 2245s 2245s 3.2. Executing DEMUXMAP pass. 2245s Dumping module `\m'. 2245s 2245s End of script. Logfile hash: 06bfea69c8, CPU: user 0.01s system 0.00s, MEM: 10.00 MB peak 2245s Yosys 0.33 (git sha1 2584903a060) 2245s Time spent: 34% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 2245s 2245s /----------------------------------------------------------------------------\ 2245s | | 2245s | yosys -- Yosys Open SYnthesis Suite | 2245s | | 2245s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2245s | | 2245s | Permission to use, copy, modify, and/or distribute this software for any | 2245s | purpose with or without fee is hereby granted, provided that the above | 2245s | copyright notice and this permission notice appear in all copies. | 2245s | | 2245s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2245s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2245s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2245s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2245s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2245s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2245s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2245s | | 2245s \----------------------------------------------------------------------------/ 2245s 2245s Yosys 0.33 (git sha1 2584903a060) 2245s 2245s 2245s -- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -- 2245s 2245s 1. Executing Verilog-2005 frontend: roundtrip.v 2245s Parsing Verilog input from `roundtrip.v' to AST representation. 2245s Generating RTLIL representation for module `\m'. 2245s Successfully finished Verilog frontend. 2245s 2245s 2. Executing PROC pass (convert processes to netlists). 2245s 2245s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Cleaned up 0 empty switches. 2245s 2245s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2245s Removed a total of 0 dead cases. 2245s 2245s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2245s Removed 1 redundant assignment. 2245s Promoted 1 assignment to connection. 2245s 2245s 2.4. Executing PROC_INIT pass (extract init attributes). 2245s 2245s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2245s 2245s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2245s Converted 0 switches. 2245s 2245s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2245s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2245s 2245s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2245s 2245s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2245s 2245s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2245s 2245s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Removing empty process `m.$proc$roundtrip.v:3$1'. 2245s Cleaned up 0 empty switches. 2245s 2245s 2.12. Executing OPT_EXPR pass (perform const folding). 2245s Optimizing module m. 2245s Removed 0 unused cells and 1 unused wires. 2245s 2245s -- Writing to `yosys-roundtrip-hex_signed-1.v' using backend `verilog' -- 2245s 2245s 3. Executing Verilog backend. 2245s 2245s 3.1. Executing BMUXMAP pass. 2245s 2245s 3.2. Executing DEMUXMAP pass. 2245s Dumping module `\m'. 2245s 2245s End of script. Logfile hash: 824c3b1e65, CPU: user 0.01s system 0.00s, MEM: 10.00 MB peak 2245s Yosys 0.33 (git sha1 2584903a060) 2245s Time spent: 32% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ... 2245s 2245s /----------------------------------------------------------------------------\ 2245s | | 2245s | yosys -- Yosys Open SYnthesis Suite | 2245s | | 2245s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2245s | | 2245s | Permission to use, copy, modify, and/or distribute this software for any | 2245s | purpose with or without fee is hereby granted, provided that the above | 2245s | copyright notice and this permission notice appear in all copies. | 2245s | | 2245s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2245s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2245s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2245s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2245s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2245s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2245s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2245s | | 2245s \----------------------------------------------------------------------------/ 2245s 2245s Yosys 0.33 (git sha1 2584903a060) 2245s 2245s 2245s -- Running command `read_verilog yosys-roundtrip-hex_signed-1.v; proc; clean' -- 2245s 2245s 1. Executing Verilog-2005 frontend: yosys-roundtrip-hex_signed-1.v 2245s Parsing Verilog input from `yosys-roundtrip-hex_signed-1.v' to AST representation. 2245s Generating RTLIL representation for module `\m'. 2245s Successfully finished Verilog frontend. 2245s 2245s 2. Executing PROC pass (convert processes to netlists). 2245s 2245s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'. 2245s Cleaned up 1 empty switch. 2245s 2245s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2245s Removed a total of 0 dead cases. 2245s 2245s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2245s Removed 1 redundant assignment. 2245s Promoted 1 assignment to connection. 2245s 2245s 2.4. Executing PROC_INIT pass (extract init attributes). 2245s 2245s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2245s 2245s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2245s Converted 0 switches. 2245s 2245s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2245s Creating decoders for process `\m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'. 2245s 2245s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2245s 2245s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2245s 2245s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2245s 2245s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Removing empty process `m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'. 2245s Cleaned up 0 empty switches. 2245s 2245s 2.12. Executing OPT_EXPR pass (perform const folding). 2245s Optimizing module m. 2245s Removed 0 unused cells and 1 unused wires. 2245s 2245s -- Writing to `yosys-roundtrip-hex_signed-2.v' using backend `verilog' -- 2245s 2245s 3. Executing Verilog backend. 2245s 2245s 3.1. Executing BMUXMAP pass. 2245s 2245s 3.2. Executing DEMUXMAP pass. 2245s Dumping module `\m'. 2245s 2245s End of script. Logfile hash: f18b3fa15b, CPU: user 0.00s system 0.00s, MEM: 10.00 MB peak 2245s Yosys 0.33 (git sha1 2584903a060) 2245s Time spent: 31% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... 2245s + diff yosys-roundtrip-hex_signed-1.v yosys-roundtrip-hex_signed-2.v 2245s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed roundtrip.v roundtrip_tb.v 2245s + ./iverilog-roundtrip-hex_signed 2245s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed-1 yosys-roundtrip-hex_signed-1.v roundtrip_tb.v 2245s + ./iverilog-roundtrip-hex_signed-1 2245s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed-2 yosys-roundtrip-hex_signed-2.v roundtrip_tb.v 2245s + ./iverilog-roundtrip-hex_signed-1 2245s + diff iverilog-roundtrip-hex_signed.log iverilog-roundtrip-hex_signed-1.log 2245s + diff iverilog-roundtrip-hex_signed-1.log iverilog-roundtrip-hex_signed-2.log 2245s + test_roundtrip oct_unsigned -DBASE_HEX -DSIGN= 2245s + local subtest=oct_unsigned 2245s + shift 2245s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-oct_unsigned-1.v 2245s 2245s /----------------------------------------------------------------------------\ 2245s | | 2245s | yosys -- Yosys Open SYnthesis Suite | 2245s | | 2245s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2245s | | 2245s | Permission to use, copy, modify, and/or distribute this software for any | 2245s | purpose with or without fee is hereby granted, provided that the above | 2245s | copyright notice and this permission notice appear in all copies. | 2245s | | 2245s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2245s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2245s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2245s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2245s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2245s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2245s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2245s | | 2245s \----------------------------------------------------------------------------/ 2245s 2245s Yosys 0.33 (git sha1 2584903a060) 2245s 2245s 2245s -- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -- 2245s 2245s 1. Executing Verilog-2005 frontend: roundtrip.v 2245s Parsing Verilog input from `roundtrip.v' to AST representation. 2245s Generating RTLIL representation for module `\m'. 2245s Successfully finished Verilog frontend. 2245s 2245s 2. Executing PROC pass (convert processes to netlists). 2245s 2245s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Cleaned up 0 empty switches. 2245s 2245s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2245s Removed a total of 0 dead cases. 2245s 2245s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2245s Removed 1 redundant assignment. 2245s Promoted 1 assignment to connection. 2245s 2245s 2.4. Executing PROC_INIT pass (extract init attributes). 2245s 2245s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2245s 2245s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2245s Converted 0 switches. 2245s 2245s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2245s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2245s 2245s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2245s + ../../yosys -p 'read_verilog yosys-roundtrip-oct_unsigned-1.v; proc; clean' -o yosys-roundtrip-oct_unsigned-2.v 2245s + diff yosys-roundtrip-oct_unsigned-1.v yosys-roundtrip-oct_unsigned-2.v 2245s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned roundtrip.v roundtrip_tb.v 2245s + ./iverilog-roundtrip-oct_unsigned 2245s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned-1 yosys-roundtrip-oct_unsigned-1.v roundtrip_tb.v 2245s + ./iverilog-roundtrip-oct_unsigned-1 2245s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned-2 yosys-roundtrip-oct_unsigned-2.v roundtrip_tb.v 2245s + ./iverilog-roundtrip-oct_unsigned-1 2245s + diff iverilog-roundtrip-oct_unsigned.log iverilog-roundtrip-oct_unsigned-1.log 2245s + diff iverilog-roundtrip-oct_unsigned-1.log iverilog-roundtrip-oct_unsigned-2.log 2245s + test_roundtrip oct_signed -DBASE_HEX -DSIGN=signed 2245s + local subtest=oct_signed 2245s + shift 2245s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-oct_signed-1.v 2245s + ../../yosys -p 'read_verilog yosys-roundtrip-oct_signed-1.v; proc; clean' -o yosys-roundtrip-oct_signed-2.v 2245s 2245s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2245s 2245s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2245s 2245s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Removing empty process `m.$proc$roundtrip.v:3$1'. 2245s Cleaned up 0 empty switches. 2245s 2245s 2.12. Executing OPT_EXPR pass (perform const folding). 2245s Optimizing module m. 2245s Removed 0 unused cells and 1 unused wires. 2245s 2245s -- Writing to `yosys-roundtrip-oct_unsigned-1.v' using backend `verilog' -- 2245s 2245s 3. Executing Verilog backend. 2245s 2245s 3.1. Executing BMUXMAP pass. 2245s 2245s 3.2. Executing DEMUXMAP pass. 2245s Dumping module `\m'. 2245s 2245s End of script. Logfile hash: b768358a65, CPU: user 0.01s system 0.00s, MEM: 10.00 MB peak 2245s Yosys 0.33 (git sha1 2584903a060) 2245s Time spent: 31% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ... 2245s 2245s /----------------------------------------------------------------------------\ 2245s | | 2245s | yosys -- Yosys Open SYnthesis Suite | 2245s | | 2245s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2245s | | 2245s | Permission to use, copy, modify, and/or distribute this software for any | 2245s | purpose with or without fee is hereby granted, provided that the above | 2245s | copyright notice and this permission notice appear in all copies. | 2245s | | 2245s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2245s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2245s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2245s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2245s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2245s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2245s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2245s | | 2245s \----------------------------------------------------------------------------/ 2245s 2245s Yosys 0.33 (git sha1 2584903a060) 2245s 2245s 2245s -- Running command `read_verilog yosys-roundtrip-oct_unsigned-1.v; proc; clean' -- 2245s 2245s 1. Executing Verilog-2005 frontend: yosys-roundtrip-oct_unsigned-1.v 2245s Parsing Verilog input from `yosys-roundtrip-oct_unsigned-1.v' to AST representation. 2245s Generating RTLIL representation for module `\m'. 2245s Successfully finished Verilog frontend. 2245s 2245s 2. Executing PROC pass (convert processes to netlists). 2245s 2245s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'. 2245s Cleaned up 1 empty switch. 2245s 2245s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2245s Removed a total of 0 dead cases. 2245s 2245s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2245s Removed 1 redundant assignment. 2245s Promoted 1 assignment to connection. 2245s 2245s 2.4. Executing PROC_INIT pass (extract init attributes). 2245s 2245s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2245s 2245s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2245s Converted 0 switches. 2245s 2245s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2245s Creating decoders for process `\m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'. 2245s 2245s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2245s 2245s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2245s 2245s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2245s 2245s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Removing empty process `m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'. 2245s Cleaned up 0 empty switches. 2245s 2245s 2.12. Executing OPT_EXPR pass (perform const folding). 2245s Optimizing module m. 2245s Removed 0 unused cells and 1 unused wires. 2245s 2245s -- Writing to `yosys-roundtrip-oct_unsigned-2.v' using backend `verilog' -- 2245s 2245s 3. Executing Verilog backend. 2245s 2245s 3.1. Executing BMUXMAP pass. 2245s 2245s 3.2. Executing DEMUXMAP pass. 2245s Dumping module `\m'. 2245s 2245s End of script. Logfile hash: 762621cd95, CPU: user 0.00s system 0.00s, MEM: 10.00 MB peak 2245s Yosys 0.33 (git sha1 2584903a060) 2245s Time spent: 30% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 2245s 2245s /----------------------------------------------------------------------------\ 2245s | | 2245s | yosys -- Yosys Open SYnthesis Suite | 2245s | | 2245s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2245s | | 2245s | Permission to use, copy, modify, and/or distribute this software for any | 2245s | purpose with or without fee is hereby granted, provided that the above | 2245s | copyright notice and this permission notice appear in all copies. | 2245s | | 2245s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2245s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2245s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2245s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2245s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2245s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2245s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2245s | | 2245s \----------------------------------------------------------------------------/ 2245s 2245s Yosys 0.33 (git sha1 2584903a060) 2245s 2245s 2245s -- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -- 2245s 2245s 1. Executing Verilog-2005 frontend: roundtrip.v 2245s Parsing Verilog input from `roundtrip.v' to AST representation. 2245s Generating RTLIL representation for module `\m'. 2245s Successfully finished Verilog frontend. 2245s 2245s 2. Executing PROC pass (convert processes to netlists). 2245s 2245s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Cleaned up 0 empty switches. 2245s 2245s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2245s Removed a total of 0 dead cases. 2245s 2245s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2245s Removed 1 redundant assignment. 2245s Promoted 1 assignment to connection. 2245s 2245s 2.4. Executing PROC_INIT pass (extract init attributes). 2245s 2245s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2245s 2245s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2245s Converted 0 switches. 2245s 2245s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2245s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2245s 2245s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2245s 2245s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2245s 2245s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2245s 2245s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Removing empty process `m.$proc$roundtrip.v:3$1'. 2245s Cleaned up 0 empty switches. 2245s 2245s 2.12. Executing OPT_EXPR pass (perform const folding). 2245s Optimizing module m. 2245s Removed 0 unused cells and 1 unused wires. 2245s 2245s -- Writing to `yosys-roundtrip-oct_signed-1.v' using backend `verilog' -- 2245s 2245s 3. Executing Verilog backend. 2245s 2245s 3.1. Executing BMUXMAP pass. 2245s 2245s 3.2. Executing DEMUXMAP pass. 2245s Dumping module `\m'. 2245s 2245s End of script. Logfile hash: 7ec82b15e3, CPU: user 0.00s system 0.00s, MEM: 10.00 MB peak 2245s Yosys 0.33 (git sha1 2584903a060) 2245s Time spent: 32% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... 2245s 2245s /----------------------------------------------------------------------------\ 2245s | | 2245s | yosys -- Yosys Open SYnthesis Suite | 2245s | | 2245s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2245s | | 2245s | Permission to use, copy, modify, and/or distribute this software for any | 2245s | purpose with or without fee is hereby granted, provided that the above | 2245s | copyright notice and this permission notice appear in all copies. | 2245s | | 2245s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2245s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2245s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2245s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2245s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2245s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2245s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2245s | | 2245s \----------------------------------------------------------------------------/ 2245s 2245s Yosys 0.33 (git sha1 2584903a060) 2245s 2245s 2245s -- Running command `read_verilog yosys-roundtrip-oct_signed-1.v; proc; clean' -- 2245s 2245s 1. Executing Verilog-2005 frontend: yosys-roundtrip-oct_signed-1.v 2245s Parsing Verilog input from `yosys-roundtrip-oct_signed-1.v' to AST representation. 2245s Generating RTLIL representation for module `\m'. 2245s Successfully finished Verilog frontend. 2245s 2245s 2. Executing PROC pass (convert processes to netlists). 2245s 2245s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'. 2245s Cleaned up 1 empty switch. 2245s 2245s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2245s Removed a total of 0 dead cases. 2245s 2245s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2245s Removed 1 redundant assignment. 2245s Promoted 1 assignment to connection. 2245s 2245s 2.4. Executing PROC_INIT pass (extract init attributes). 2245s + diff yosys-roundtrip-oct_signed-1.v yosys-roundtrip-oct_signed-2.v 2245s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed roundtrip.v roundtrip_tb.v 2245s + ./iverilog-roundtrip-oct_signed 2245s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed-1 yosys-roundtrip-oct_signed-1.v roundtrip_tb.v 2245s + ./iverilog-roundtrip-oct_signed-1 2245s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed-2 yosys-roundtrip-oct_signed-2.v roundtrip_tb.v 2245s + ./iverilog-roundtrip-oct_signed-1 2245s + diff iverilog-roundtrip-oct_signed.log iverilog-roundtrip-oct_signed-1.log 2245s + diff iverilog-roundtrip-oct_signed-1.log iverilog-roundtrip-oct_signed-2.log 2245s + test_roundtrip bin_unsigned -DBASE_HEX -DSIGN= 2245s + local subtest=bin_unsigned 2245s + shift 2245s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-bin_unsigned-1.v 2245s + ../../yosys -p 'read_verilog yosys-roundtrip-bin_unsigned-1.v; proc; clean' -o yosys-roundtrip-bin_unsigned-2.v 2245s 2245s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2245s 2245s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2245s Converted 0 switches. 2245s 2245s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2245s Creating decoders for process `\m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'. 2245s 2245s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2245s 2245s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2245s 2245s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2245s 2245s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Removing empty process `m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'. 2245s Cleaned up 0 empty switches. 2245s 2245s 2.12. Executing OPT_EXPR pass (perform const folding). 2245s Optimizing module m. 2245s Removed 0 unused cells and 1 unused wires. 2245s 2245s -- Writing to `yosys-roundtrip-oct_signed-2.v' using backend `verilog' -- 2245s 2245s 3. Executing Verilog backend. 2245s 2245s 3.1. Executing BMUXMAP pass. 2245s 2245s 3.2. Executing DEMUXMAP pass. 2245s Dumping module `\m'. 2245s 2245s End of script. Logfile hash: a747b9bd4f, CPU: user 0.01s system 0.00s, MEM: 10.00 MB peak 2245s Yosys 0.33 (git sha1 2584903a060) 2245s Time spent: 31% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 2245s 2245s /----------------------------------------------------------------------------\ 2245s | | 2245s | yosys -- Yosys Open SYnthesis Suite | 2245s | | 2245s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2245s | | 2245s | Permission to use, copy, modify, and/or distribute this software for any | 2245s | purpose with or without fee is hereby granted, provided that the above | 2245s | copyright notice and this permission notice appear in all copies. | 2245s | | 2245s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2245s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2245s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2245s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2245s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2245s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2245s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2245s | | 2245s \----------------------------------------------------------------------------/ 2245s 2245s Yosys 0.33 (git sha1 2584903a060) 2245s 2245s 2245s -- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -- 2245s 2245s 1. Executing Verilog-2005 frontend: roundtrip.v 2245s Parsing Verilog input from `roundtrip.v' to AST representation. 2245s Generating RTLIL representation for module `\m'. 2245s Successfully finished Verilog frontend. 2245s 2245s 2. Executing PROC pass (convert processes to netlists). 2245s 2245s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Cleaned up 0 empty switches. 2245s 2245s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2245s Removed a total of 0 dead cases. 2245s 2245s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2245s Removed 1 redundant assignment. 2245s Promoted 1 assignment to connection. 2245s 2245s 2.4. Executing PROC_INIT pass (extract init attributes). 2245s 2245s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2245s 2245s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2245s Converted 0 switches. 2245s 2245s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2245s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2245s 2245s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2245s 2245s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2245s 2245s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2245s 2245s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Removing empty process `m.$proc$roundtrip.v:3$1'. 2245s Cleaned up 0 empty switches. 2245s 2245s 2.12. Executing OPT_EXPR pass (perform const folding). 2245s Optimizing module m. 2245s Removed 0 unused cells and 1 unused wires. 2245s 2245s -- Writing to `yosys-roundtrip-bin_unsigned-1.v' using backend `verilog' -- 2245s 2245s 3. Executing Verilog backend. 2245s 2245s 3.1. Executing BMUXMAP pass. 2245s 2245s 3.2. Executing DEMUXMAP pass. 2245s Dumping module `\m'. 2245s 2245s End of script. Logfile hash: 270b564880, CPU: user 0.01s system 0.00s, MEM: 10.00 MB peak 2245s Yosys 0.33 (git sha1 2584903a060) 2245s Time spent: 32% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... 2245s 2245s /----------------------------------------------------------------------------\ 2245s | | 2245s | yosys -- Yosys Open SYnthesis Suite | 2245s | | 2245s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2245s | | 2245s | Permission to use, copy, modify, and/or distribute this software for any | 2245s | purpose with or without fee is hereby granted, provided that the above | 2245s | copyright notice and this permission notice appear in all copies. | 2245s | | 2245s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2245s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2245s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2245s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2245s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2245s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2245s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2245s | | 2245s \----------------------------------------------------------------------------/ 2245s 2245s Yosys 0.33 (git sha1 2584903a060) 2245s 2245s 2245s -- Running command `read_verilog yosys-roundtrip-bin_unsigned-1.v; proc; clean' -- 2245s 2245s 1. Executing Verilog-2005 frontend: yosys-roundtrip-bin_unsigned-1.v 2245s Parsing Verilog input from `yosys-roundtrip-bin_unsigned-1.v' to AST representation. 2245s Generating RTLIL representation for module `\m'. 2245s Successfully finished Verilog frontend. 2245s 2245s 2. Executing PROC pass (convert processes to netlists). 2245s 2245s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'. 2245s Cleaned up 1 empty switch. 2245s 2245s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2245s + diff yosys-roundtrip-bin_unsigned-1.v yosys-roundtrip-bin_unsigned-2.v 2245s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned roundtrip.v roundtrip_tb.v 2245s + ./iverilog-roundtrip-bin_unsigned 2245s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned-1 yosys-roundtrip-bin_unsigned-1.v roundtrip_tb.v 2245s + ./iverilog-roundtrip-bin_unsigned-1 2245s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned-2 yosys-roundtrip-bin_unsigned-2.v roundtrip_tb.v 2245s + ./iverilog-roundtrip-bin_unsigned-1 2245s + diff iverilog-roundtrip-bin_unsigned.log iverilog-roundtrip-bin_unsigned-1.log 2245s + diff iverilog-roundtrip-bin_unsigned-1.log iverilog-roundtrip-bin_unsigned-2.log 2245s + test_roundtrip bin_signed -DBASE_HEX -DSIGN=signed 2245s + local subtest=bin_signed 2245s + shift 2245s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-bin_signed-1.v 2245s Removed a total of 0 dead cases. 2245s 2245s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2245s Removed 1 redundant assignment. 2245s Promoted 1 assignment to connection. 2245s 2245s 2.4. Executing PROC_INIT pass (extract init attributes). 2245s 2245s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2245s 2245s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2245s Converted 0 switches. 2245s 2245s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2245s Creating decoders for process `\m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'. 2245s 2245s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2245s 2245s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2245s 2245s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2245s 2245s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Removing empty process `m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'. 2245s Cleaned up 0 empty switches. 2245s 2245s 2.12. Executing OPT_EXPR pass (perform const folding). 2245s Optimizing module m. 2245s Removed 0 unused cells and 1 unused wires. 2245s 2245s -- Writing to `yosys-roundtrip-bin_unsigned-2.v' using backend `verilog' -- 2245s 2245s 3. Executing Verilog backend. 2245s 2245s 3.1. Executing BMUXMAP pass. 2245s 2245s 3.2. Executing DEMUXMAP pass. 2245s Dumping module `\m'. 2245s 2245s End of script. Logfile hash: dc9f56cb10, CPU: user 0.01s system 0.00s, MEM: 10.00 MB peak 2245s Yosys 0.33 (git sha1 2584903a060) 2245s Time spent: 31% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... 2245s 2245s /----------------------------------------------------------------------------\ 2245s | | 2245s | yosys -- Yosys Open SYnthesis Suite | 2245s | | 2245s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2245s | | 2245s | Permission to use, copy, modify, and/or distribute this software for any | 2245s | purpose with or without fee is hereby granted, provided that the above | 2245s | copyright notice and this permission notice appear in all copies. | 2245s | | 2245s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2245s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2245s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2245s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2245s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2245s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2245s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2245s | | 2245s \----------------------------------------------------------------------------/ 2245s 2245s Yosys 0.33 (git sha1 2584903a060) 2245s 2245s 2245s -- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -- 2245s 2245s 1. Executing Verilog-2005 frontend: roundtrip.v 2245s Parsing Verilog input from `roundtrip.v' to AST representation. 2245s Generating RTLIL representation for module `\m'. 2245s Successfully finished Verilog frontend. 2245s 2245s 2. Executing PROC pass (convert processes to netlists). 2245s 2245s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Cleaned up 0 empty switches. 2245s 2245s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2245s Removed a total of 0 dead cases. 2245s 2245s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2245s Removed 1 redundant assignment. 2245s Promoted 1 assignment to connection. 2245s 2245s 2.4. Executing PROC_INIT pass (extract init attributes). 2245s 2245s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2245s 2245s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2245s Converted 0 switches. 2245s 2245s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2245s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 2245s 2245s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2245s 2245s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2245s 2245s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2245s 2245s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Removing empty process `m.$proc$roundtrip.v:3$1'. 2245s Cleaned up 0 empty switches. 2245s 2245s 2.12. Executing OPT_EXPR pass (perform const folding). 2245s Optimizing module m. 2245s Removed 0 unused cells and 1 unused wires. 2245s 2245s -- Writing to `yosys-roundtrip-bin_signed-1.v' using backend `verilog' -- 2245s 2245s 3. Executing Verilog backend. 2245s 2245s 3.1. Executing BMUXMAP pass. 2245s 2245s 3.2. Executing DEMUXMAP pass. 2245s Dumping module `\m'. 2245s 2245s End of script. Logfile hash: 7709253822, CPU: user 0.01s system 0.00s, MEM: 10.00 MB peak 2245s Yosys 0.33 (git sha1 2584903a060) 2245s Time spent: 32% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... 2245s 2245s /----------------------------------------------------------------------------\ 2245s | | 2245s | yosys -- Yosys Open SYnthesis Suite | 2245s | | 2245s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2245s | | 2245s | Permission to use, copy, modify, and/or distribute this software for any | 2245s | purpose with or without fee is hereby granted, provided that the above | 2245s | copyright notice and this permission notice appear in all copies. | 2245s | | 2245s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2245s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2245s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2245s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2245s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2245s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2245s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2245s | | 2245s \----------------------------------------------------------------------------/ 2245s 2245s Yosys 0.33 (git sha1 2584903a060) 2245s 2245s 2245s -- Running command `read_verilog yosys-roundtrip-bin_signed-1.v; proc; clean' -- 2245s 2245s 1. Executing Verilog-2005 frontend: yosys-roundtrip-bin_signed-1.v 2245s Parsing Verilog input from `yosys-roundtrip-bin_signed-1.v' to AST representation. 2245s Generating RTLIL representation for module `\m'. 2245s Successfully finished Verilog frontend. 2245s 2245s 2. Executing PROC pass (convert processes to netlists). 2245s 2245s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'. 2245s Cleaned up 1 empty switch. 2245s 2245s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2245s Removed a total of 0 dead cases. 2245s 2245s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2245s Removed 1 redundant assignment. 2245s Promoted 1 assignment to connection. 2245s 2245s 2.4. Executing PROC_INIT pass (extract init attributes). 2245s 2245s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2245s 2245s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2245s Converted 0 switches. 2245s 2245s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2245s Creating decoders for process `\m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'. 2245s 2245s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2245s 2245s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2245s 2245s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2245s 2245s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Removing empty process `m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'. 2245s Cleaned up 0 empty switches. 2245s 2245s 2.12. Executing OPT_EXPR pass (perform const folding). 2245s Optimizing module m. 2245s Removed 0 unused cells and 1 unused wires. 2245s 2245s -- Writing to `yosys-roundtrip-bin_signed-2.v' using backend `verilog' -- 2245s 2245s 3. Executing Verilog backend. 2245s 2245s 3.1. Executing BMUXMAP pass. 2245s 2245s 3.2. Executing DEMUXMAP pass. 2245s Dumping module `\m'. 2245s 2245s End of script. Logfile hash: 7e2d8271c4, CPU: user 0.00s system 0.00s, MEM: 10.00 MB peak 2245s Yosys 0.33 (git sha1 2584903a060) 2245s Time spent: 31% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... 2245s + ../../yosys -p 'read_verilog yosys-roundtrip-bin_signed-1.v; proc; clean' -o yosys-roundtrip-bin_signed-2.v 2245s + diff yosys-roundtrip-bin_signed-1.v yosys-roundtrip-bin_signed-2.v 2245s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed roundtrip.v roundtrip_tb.v 2245s + ./iverilog-roundtrip-bin_signed 2245s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed-1 yosys-roundtrip-bin_signed-1.v roundtrip_tb.v 2245s + ./iverilog-roundtrip-bin_signed-1 2245s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed-2 yosys-roundtrip-bin_signed-2.v roundtrip_tb.v 2245s + ./iverilog-roundtrip-bin_signed-1 2245s + diff iverilog-roundtrip-bin_signed.log iverilog-roundtrip-bin_signed-1.log 2245s + diff iverilog-roundtrip-bin_signed-1.log iverilog-roundtrip-bin_signed-2.log 2245s + test_cxxrtl always_full 2245s + local subtest=always_full 2245s + shift 2245s + ../../yosys -p 'read_verilog always_full.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_full.cc' 2245s 2245s /----------------------------------------------------------------------------\ 2245s | | 2245s | yosys -- Yosys Open SYnthesis Suite | 2245s | | 2245s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2245s | | 2245s | Permission to use, copy, modify, and/or distribute this software for any | 2245s | purpose with or without fee is hereby granted, provided that the above | 2245s | copyright notice and this permission notice appear in all copies. | 2245s | | 2245s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2245s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2245s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2245s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2245s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2245s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2245s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2245s | | 2245s \----------------------------------------------------------------------------/ 2245s 2245s Yosys 0.33 (git sha1 2584903a060) 2245s 2245s 2245s -- Running command `read_verilog always_full.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_full.cc' -- 2245s 2245s 1. Executing Verilog-2005 frontend: always_full.v 2245s Parsing Verilog input from `always_full.v' to AST representation. 2245s Generating RTLIL representation for module `\always_full'. 2245s Successfully finished Verilog frontend. 2245s 2245s 2. Executing PROC pass (convert processes to netlists). 2245s 2245s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Cleaned up 0 empty switches. 2245s 2245s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2245s Removed a total of 0 dead cases. 2245s 2245s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2245s Removed 207 redundant assignments. 2245s Promoted 207 assignments to connections. 2245s 2245s 2.4. Executing PROC_INIT pass (extract init attributes). 2245s 2245s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2245s 2245s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2245s Converted 0 switches. 2245s 2245s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2245s Creating decoders for process `\always_full.$proc$always_full.v:3$1'. 2245s 2245s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2245s 2245s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2245s 2245s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2245s 2245s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Removing empty process `always_full.$proc$always_full.v:3$1'. 2245s Cleaned up 0 empty switches. 2245s 2245s 2.12. Executing OPT_EXPR pass (perform const folding). 2245s Optimizing module always_full. 2245s Removed 0 unused cells and 207 unused wires. 2245s 2245s 3. Executing CXXRTL backend. 2245s 2245s 3.1. Executing HIERARCHY pass (managing design hierarchy). 2245s 2245s 3.1.1. Finding top of design hierarchy.. 2245s root of 0 design levels: always_full 2245s Automatically selected always_full as design top module. 2245s 2245s 3.1.2. Analyzing design hierarchy.. 2245s Top module: \always_full 2245s 2245s 3.1.3. Analyzing design hierarchy.. 2245s Top module: \always_full 2245s Removed 0 unused modules. 2245s 2245s 3.2. Executing FLATTEN pass (flatten design). 2245s 2245s 3.3. Executing PROC pass (convert processes to netlists). 2245s 2245s 3.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Cleaned up 0 empty switches. 2245s 2245s 3.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2245s Removed a total of 0 dead cases. 2245s 2245s 3.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2245s Removed 0 redundant assignments. 2245s Promoted 0 assignments to connections. 2245s 2245s 3.3.4. Executing PROC_INIT pass (extract init attributes). 2245s 2245s 3.3.5. Executing PROC_ARST pass (detect async resets in processes). 2245s 2245s 3.3.6. Executing PROC_ROM pass (convert switches to ROMs). 2245s Converted 0 switches. 2245s 2245s 3.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2245s 2245s 3.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2245s 2245s 3.3.9. Executing PROC_DFF pass (convert process syncs to FFs). 2245s 2245s 3.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2245s 2245s 3.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2245s Cleaned up 0 empty switches. 2245s 2245s 3.3.12. Executing OPT_EXPR pass (perform const folding). 2245s Optimizing module always_full. 2245s 2245s 2245s 2245s End of script. Logfile hash: 6abd135c0a, CPU: user 0.03s system 0.00s, MEM: 12.00 MB peak 2245s Yosys 0.33 (git sha1 2584903a060) 2245s Time spent: 26% 2x read_verilog (0 sec), 23% 2x opt_expr (0 sec), ... 2245s + gcc -std=c++11 -o yosys-always_full -I../.. always_full_tb.cc -lstdc++ 2246s + ./yosys-always_full 2246s + iverilog -o iverilog-always_full always_full.v always_full_tb.v 2246s + ./iverilog-always_full 2246s + grep -v '\$finish called' 2246s + diff iverilog-always_full.log yosys-always_full.log 2246s + test_cxxrtl always_comb 2246s + local subtest=always_comb 2246s + shift 2246s + ../../yosys -p 'read_verilog always_comb.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_comb.cc' 2246s 2246s /----------------------------------------------------------------------------\ 2246s | | 2246s | yosys -- Yosys Open SYnthesis Suite | 2246s | | 2246s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2246s | | 2246s | Permission to use, copy, modify, and/or distribute this software for any | 2246s | purpose with or without fee is hereby granted, provided that the above | 2246s | copyright notice and this permission notice appear in all copies. | 2246s | | 2246s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2246s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2246s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2246s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2246s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2246s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2246s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2246s | | 2246s \----------------------------------------------------------------------------/ 2246s 2246s Yosys 0.33 (git sha1 2584903a060) 2246s 2246s 2246s -- Running command `read_verilog always_comb.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_comb.cc' -- 2246s 2246s 1. Executing Verilog-2005 frontend: always_comb.v 2246s Parsing Verilog input from `always_comb.v' to AST representation. 2246s Generating RTLIL representation for module `\top'. 2246s Generating RTLIL representation for module `\sub'. 2246s Successfully finished Verilog frontend. 2246s 2246s 2. Executing PROC pass (convert processes to netlists). 2246s 2246s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2246s Cleaned up 0 empty switches. 2246s 2246s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2246s Removed a total of 0 dead cases. 2246s 2246s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2246s Removed 0 redundant assignments. 2246s Promoted 4 assignments to connections. 2246s 2246s 2.4. Executing PROC_INIT pass (extract init attributes). 2246s Found init rule in `\top.$proc$always_comb.v:3$13'. 2246s Set init value: \b = 1'0 2246s Found init rule in `\top.$proc$always_comb.v:2$12'. 2246s Set init value: \a = 1'0 2246s 2246s 2.5. Executing PROC_ARST pass (detect async resets in processes). 2246s 2246s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 2246s Converted 0 switches. 2246s 2246s 2246s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2246s Creating decoders for process `\sub.$proc$always_comb.v:23$15'. 2246s 1/1: $display$always_comb.v:23$19_EN 2246s Creating decoders for process `\top.$proc$always_comb.v:3$13'. 2246s Creating decoders for process `\top.$proc$always_comb.v:2$12'. 2246s Creating decoders for process `\top.$proc$always_comb.v:8$1'. 2246s 2246s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2246s 2246s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2246s Creating register for signal `\top.\a' using process `\top.$proc$always_comb.v:8$1'. 2246s created $dff cell `$procdff$22' with positive edge clock. 2246s Creating register for signal `\top.\b' using process `\top.$proc$always_comb.v:8$1'. 2246s created $dff cell `$procdff$23' with positive edge clock. 2246s 2246s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2246s 2246s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2246s Found and cleaned up 1 empty switch in `\sub.$proc$always_comb.v:23$15'. 2246s Removing empty process `sub.$proc$always_comb.v:23$15'. 2246s Removing empty process `top.$proc$always_comb.v:3$13'. 2246s Removing empty process `top.$proc$always_comb.v:2$12'. 2246s Removing empty process `top.$proc$always_comb.v:8$1'. 2246s Cleaned up 1 empty switch. 2246s 2246s 2.12. Executing OPT_EXPR pass (perform const folding). 2246s Optimizing module sub. 2246s Optimizing module top. 2246s Removed 0 unused cells and 7 unused wires. 2246s 2246s 3. Executing CXXRTL backend. 2246s 2246s 3.1. Executing HIERARCHY pass (managing design hierarchy). 2246s 2246s 3.1.1. Finding top of design hierarchy.. 2246s root of 0 design levels: sub 2246s root of 1 design levels: top 2246s Automatically selected top as design top module. 2246s 2246s 3.1.2. Analyzing design hierarchy.. 2246s Top module: \top 2246s Used module: \sub 2246s 2246s 3.1.3. Analyzing design hierarchy.. 2246s Top module: \top 2246s Used module: \sub 2246s Removed 0 unused modules. 2246s 2246s 3.2. Executing FLATTEN pass (flatten design). 2246s Deleting now unused module sub. 2246s 2246s 2246s 3.3. Executing PROC pass (convert processes to netlists). 2246s 2246s 3.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2246s Cleaned up 0 empty switches. 2246s 2246s 3.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2246s Removed a total of 0 dead cases. 2246s 2246s 3.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2246s Removed 0 redundant assignments. 2246s Promoted 0 assignments to connections. 2246s 2246s 3.3.4. Executing PROC_INIT pass (extract init attributes). 2246s 2246s 3.3.5. Executing PROC_ARST pass (detect async resets in processes). 2246s 2246s 3.3.6. Executing PROC_ROM pass (convert switches to ROMs). 2246s Converted 0 switches. 2246s 2246s 3.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2246s 2246s 3.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2246s 2246s 3.3.9. Executing PROC_DFF pass (convert process syncs to FFs). 2246s 2246s 3.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2246s 2246s 3.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2246s Cleaned up 0 empty switches. 2246s 2246s 3.3.12. Executing OPT_EXPR pass (perform const folding). 2246s Optimizing module top. 2246s 2246s 2246s 2246s End of script. Logfile hash: 03fe26efda, CPU: user 0.01s system 0.00s, MEM: 12.00 MB peak 2246s Yosys 0.33 (git sha1 2584903a060) 2246s Time spent: 30% 2x opt_expr (0 sec), 20% 1x clean (0 sec), ... 2246s + gcc -std=c++11 -o yosys-always_comb -I../.. always_comb_tb.cc -lstdc++ 2248s + ./yosys-always_comb 2248s 2248s /----------------------------------------------------------------------------\ 2248s | | 2248s | yosys -- Yosys Open SYnthesis Suite | 2248s | | 2248s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2248s | | 2248s | Permission to use, copy, modify, and/or distribute this software for any | 2248s | purpose with or without fee is hereby granted, provided that the above | 2248s | copyright notice and this permission notice appear in all copies. | 2248s | | 2248s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2248s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2248s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2248s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2248s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2248s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2248s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2248s | | 2248s \----------------------------------------------------------------------------/ 2248s 2248s Yosys 0.33 (git sha1 2584903a060) 2248s 2248s 2248s -- Running command `read_verilog always_full.v; prep; clean' -- 2248s 2248s 1. Executing Verilog-2005 frontend: always_full.v 2248s Parsing Verilog input from `always_full.v' to AST representation. 2248s Generating RTLIL representation for module `\always_full'. 2248s Successfully finished Verilog frontend. 2248s 2248s 2. Executing PREP pass. 2248s 2248s 2.1. Executing HIERARCHY pass (managing design hierarchy). 2248s 2248s 2.2. Executing PROC pass (convert processes to netlists). 2248s 2248s 2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2248s Cleaned up 0 empty switches. 2248s 2248s 2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2248s Removed a total of 0 dead cases. 2248s 2248s 2.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2248s Removed 207 redundant assignments. 2248s Promoted 207 assignments to connections. 2248s 2248s 2.2.4. Executing PROC_INIT pass (extract init attributes). 2248s 2248s 2.2.5. Executing PROC_ARST pass (detect async resets in processes). 2248s 2248s 2.2.6. Executing PROC_ROM pass (convert switches to ROMs). 2248s Converted 0 switches. 2248s 2248s 2.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2248s Creating decoders for process `\always_full.$proc$always_full.v:3$1'. 2248s 2248s 2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2248s 2248s 2.2.9. Executing PROC_DFF pass (convert process syncs to FFs). 2248s 2248s 2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2248s 2248s 2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2248s Removing empty process `always_full.$proc$always_full.v:3$1'. 2248s Cleaned up 0 empty switches. 2248s 2248s 2.2.12. Executing OPT_EXPR pass (perform const folding). 2248s Optimizing module always_full. 2248s 2248s 2.3. Executing OPT_EXPR pass (perform const folding). 2248s Optimizing module always_full. 2248s 2248s 2.4. Executing OPT_CLEAN pass (remove unused cells and wires). 2248s Finding unused cells or wires in module \always_full.. 2248s Removed 0 unused cells and 207 unused wires. 2248s 2248s 2248s 2.5. Executing CHECK pass (checking for obvious problems). 2248s Checking module always_full... 2248s Found and reported 0 problems. 2248s 2248s 2.6. Executing OPT pass (performing simple optimizations). 2248s 2248s 2.6.1. Executing OPT_EXPR pass (perform const folding). 2248s Optimizing module always_full. 2248s 2248s 2.6.2. Executing OPT_MERGE pass (detect identical cells). 2248s Finding identical cells in module `\always_full'. 2248s Removed a total of 0 cells. 2248s 2248s 2.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 2248s Running muxtree optimizer on module \always_full.. 2248s Creating internal representation of mux trees. 2248s No muxes found in this module. 2248s Removed 0 multiplexer ports. 2248s 2248s 2.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 2248s Optimizing cells in module \always_full. 2248s Performed a total of 0 changes. 2248s 2248s 2.6.5. Executing OPT_MERGE pass (detect identical cells). 2248s Finding identical cells in module `\always_full'. 2248s Removed a total of 0 cells. 2248s 2248s 2.6.6. Executing OPT_CLEAN pass (remove unused cells and wires). 2248s Finding unused cells or wires in module \always_full.. 2248s 2248s 2.6.7. Executing OPT_EXPR pass (perform const folding). 2248s Optimizing module always_full. 2248s 2248s 2.6.8. Finished OPT passes. (There is nothing left to do.) 2248s 2248s 2.7. Executing WREDUCE pass (reducing word size of cells). 2248s 2248s 2.8. Executing OPT_CLEAN pass (remove unused cells and wires). 2248s Finding unused cells or wires in module \always_full.. 2248s 2248s 2.9. Executing MEMORY_COLLECT pass (generating $mem cells). 2248s 2248s 2.10. Executing OPT pass (performing simple optimizations). 2248s 2248s 2.10.1. Executing OPT_EXPR pass (perform const folding). 2248s Optimizing module always_full. 2248s 2248s 2.10.2. Executing OPT_MERGE pass (detect identical cells). 2248s Finding identical cells in module `\always_full'. 2248s Removed a total of 0 cells. 2248s 2248s 2.10.3. Executing OPT_CLEAN pass (remove unused cells and wires). 2248s Finding unused cells or wires in module \always_full.. 2248s 2248s 2.10.4. Finished fast OPT passes. 2248s 2248s 2.11. Printing statistics. 2248s 2248s === always_full === 2248s 2248s Number of wires: 1 2248s Number of wire bits: 1 2248s Number of public wires: 1 2248s Number of public wire bits: 1 2248s Number of memories: 0 2248s Number of memory bits: 0 2248s Number of processes: 0 2248s Number of cells: 207 2248s $print 207 2248s 2248s 2.12. Executing CHECK pass (checking for obvious problems). 2248s Checking module always_full... 2248s Found and reported 0 problems. 2248s 2248s -- Writing to `yosys-always_full-1.v' using backend `verilog' -- 2248s 2248s 3. Executing Verilog backend. 2248s 2248s 3.1. Executing BMUXMAP pass. 2248s 2248s 3.2. Executing DEMUXMAP pass. 2248s Dumping module `\always_full'. 2248s 2248s End of script. Logfile hash: cfd5b76053, CPU: user 0.07s system 0.01s, MEM: 12.00 MB peak 2248s Yosys 0.33 (git sha1 2584903a060) 2248s Time spent: 21% 5x opt_expr (0 sec), 20% 4x opt_clean (0 sec), ... 2248s 2248s /----------------------------------------------------------------------------\ 2248s | | 2248s | yosys -- Yosys Open SYnthesis Suite | 2248s | | 2248s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2248s | | 2248s | Permission to use, copy, modify, and/or distribute this software for any | 2248s | purpose with or without fee is hereby granted, provided that the above | 2248s | copyright notice and this permission notice appear in all copies. | 2248s | | 2248s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2248s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2248s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2248s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2248s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2248s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2248s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2248s | | 2248s \----------------------------------------------------------------------------/ 2248s 2248s Yosys 0.33 (git sha1 2584903a060) 2248s 2248s 2248s -- Running command `read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc' -- 2248s 2248s 1. Executing Verilog-2005 frontend: display_lm.v 2248s Parsing Verilog input from `display_lm.v' to AST representation. 2248s Generating RTLIL representation for module `\top'. 2248s Generating RTLIL representation for module `\mid'. 2248s Generating RTLIL representation for module `\bot'. 2248s %l: \bot 2248s %m: \bot 2248s Successfully finished Verilog frontend. 2248s 2248s 2. Executing CXXRTL backend. 2248s 2248s 2.1. Executing HIERARCHY pass (managing design hierarchy). 2248s 2248s 2.1.1. Finding top of design hierarchy.. 2248s root of 0 design levels: bot 2248s root of 1 design levels: mid 2248s root of 2 design levels: top 2248s Automatically selected top as design top module. 2248s 2248s 2.1.2. Analyzing design hierarchy.. 2248s Top module: \top 2248s Used module: \mid 2248s Used module: \bot 2248s 2248s 2.1.3. Analyzing design hierarchy.. 2248s Top module: \top 2248s Used module: \mid 2248s Used module: \bot 2248s Removed 0 unused modules. 2248s 2248s 2.2. Executing FLATTEN pass (flatten design). 2248s Deleting now unused module bot. 2248s Deleting now unused module mid. 2248s 2248s 2248s 2.3. Executing PROC pass (convert processes to netlists). 2248s 2248s 2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2248s Removing empty process `top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:0$3'. 2248s Cleaned up 0 empty switches. 2248s 2248s 2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2248s Removed a total of 0 dead cases. 2248s 2248s 2.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2248s Removed 1 redundant assignment. 2248s Promoted 1 assignment to connection. 2248s 2248s 2.3.4. Executing PROC_INIT pass (extract init attributes). 2248s 2248s 2.3.5. Executing PROC_ARST pass (detect async resets in processes). 2248s 2248s 2.3.6. Executing PROC_ROM pass (convert switches to ROMs). 2248s Converted 0 switches. 2248s 2248s 2.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2248s Creating decoders for process `\top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:11$1'. 2248s 2248s 2.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2248s 2248s 2.3.9. Executing PROC_DFF pass (convert process syncs to FFs). 2248s 2248s 2.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2248s 2248s 2.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2248s Removing empty process `top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:11$1'. 2248s Cleaned up 0 empty switches. 2248s 2248s 2.3.12. Executing OPT_EXPR pass (perform const folding). 2248s Optimizing module top. 2248s 2248s 2248s 2248s End of script. Logfile hash: 1b689717a7, CPU: user 0.01s system 0.00s, MEM: 12.00 MB peak 2248s Yosys 0.33 (git sha1 2584903a060) 2248s Time spent: 40% 1x opt_expr (0 sec), 12% 2x read_verilog (0 sec), ... 2248s %l: \bot 2248s %m: \bot 2248s %l: \bot 2248s %m: \bot 2248s 2248s Passed "make test". 2248s 2248s + iverilog -o iverilog-always_comb always_comb.v always_comb_tb.v 2248s + ./iverilog-always_comb 2248s + grep -v '\$finish called' 2248s + diff iverilog-always_comb.log yosys-always_comb.log 2248s + ../../yosys -p 'read_verilog always_full.v; prep; clean' -o yosys-always_full-1.v 2248s + iverilog -o iverilog-always_full-1 yosys-always_full-1.v always_full_tb.v 2248s + ./iverilog-always_full-1 2248s + grep -v '\$finish called' 2248s + diff iverilog-always_full.log iverilog-always_full-1.log 2248s + ../../yosys -p 'read_verilog display_lm.v' 2248s + ../../yosys -p 'read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc' 2248s + gcc -std=c++11 -o yosys-display_lm_cc -I../.. display_lm_tb.cc -lstdc++ 2248s + ./yosys-display_lm_cc 2248s + for log in yosys-display_lm.log yosys-display_lm_cc.log 2248s + grep '^%l: \\bot$' yosys-display_lm.log 2248s + grep '^%m: \\bot$' yosys-display_lm.log 2248s + for log in yosys-display_lm.log yosys-display_lm_cc.log 2248s + grep '^%l: \\bot$' yosys-display_lm_cc.log 2248s + grep '^%m: \\bot$' yosys-display_lm_cc.log 2248s autopkgtest [21:44:55]: test yosys-testsuite: -----------------------] 2249s yosys-testsuite PASS 2249s autopkgtest [21:44:56]: test yosys-testsuite: - - - - - - - - - - results - - - - - - - - - - 2250s autopkgtest [21:44:57]: test ice: preparing testbed 2354s autopkgtest [21:46:41]: testbed dpkg architecture: ppc64el 2354s autopkgtest [21:46:41]: testbed apt version: 2.7.12 2354s autopkgtest [21:46:41]: @@@@@@@@@@@@@@@@@@@@ test bed setup 2355s Get:1 http://ftpmaster.internal/ubuntu noble-proposed InRelease [117 kB] 2355s Get:2 http://ftpmaster.internal/ubuntu noble-proposed/main Sources [493 kB] 2355s Get:3 http://ftpmaster.internal/ubuntu noble-proposed/multiverse Sources [52.7 kB] 2355s Get:4 http://ftpmaster.internal/ubuntu noble-proposed/universe Sources [3757 kB] 2355s Get:5 http://ftpmaster.internal/ubuntu noble-proposed/restricted Sources [6540 B] 2355s Get:6 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el Packages [654 kB] 2355s Get:7 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el c-n-f Metadata [3116 B] 2355s Get:8 http://ftpmaster.internal/ubuntu noble-proposed/restricted ppc64el Packages [1372 B] 2355s Get:9 http://ftpmaster.internal/ubuntu noble-proposed/restricted ppc64el c-n-f Metadata [116 B] 2355s Get:10 http://ftpmaster.internal/ubuntu noble-proposed/universe ppc64el Packages [4081 kB] 2356s Get:11 http://ftpmaster.internal/ubuntu noble-proposed/universe ppc64el c-n-f Metadata [8652 B] 2356s Get:12 http://ftpmaster.internal/ubuntu noble-proposed/multiverse ppc64el Packages [47.7 kB] 2356s Get:13 http://ftpmaster.internal/ubuntu noble-proposed/multiverse ppc64el c-n-f Metadata [116 B] 2359s Fetched 9222 kB in 2s (4164 kB/s) 2359s Reading package lists... 2361s Reading package lists... 2362s Building dependency tree... 2362s Reading state information... 2362s Calculating upgrade... 2362s The following packages will be upgraded: 2362s readline-common ubuntu-minimal ubuntu-standard 2362s 3 upgraded, 0 newly installed, 0 to remove and 0 not upgraded. 2362s Need to get 77.9 kB of archives. 2362s After this operation, 0 B of additional disk space will be used. 2362s Get:1 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el readline-common all 8.2-3.1 [56.4 kB] 2362s Get:2 http://ftpmaster.internal/ubuntu noble/main ppc64el ubuntu-minimal ppc64el 1.536build1 [10.7 kB] 2362s Get:3 http://ftpmaster.internal/ubuntu noble/main ppc64el ubuntu-standard ppc64el 1.536build1 [10.7 kB] 2363s Fetched 77.9 kB in 1s (148 kB/s) 2363s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 70095 files and directories currently installed.) 2363s Preparing to unpack .../readline-common_8.2-3.1_all.deb ... 2363s Unpacking readline-common (8.2-3.1) over (8.2-3) ... 2363s Preparing to unpack .../ubuntu-minimal_1.536build1_ppc64el.deb ... 2363s Unpacking ubuntu-minimal (1.536build1) over (1.536) ... 2363s Preparing to unpack .../ubuntu-standard_1.536build1_ppc64el.deb ... 2363s Unpacking ubuntu-standard (1.536build1) over (1.536) ... 2363s Setting up ubuntu-minimal (1.536build1) ... 2363s Setting up ubuntu-standard (1.536build1) ... 2363s Setting up readline-common (8.2-3.1) ... 2363s Processing triggers for install-info (7.1-3) ... 2363s Processing triggers for man-db (2.12.0-3) ... 2363s Reading package lists... 2363s Building dependency tree... 2363s Reading state information... 2363s 0 upgraded, 0 newly installed, 0 to remove and 0 not upgraded. 2364s Hit:1 http://ftpmaster.internal/ubuntu noble-proposed InRelease 2364s Hit:2 http://ftpmaster.internal/ubuntu noble InRelease 2364s Hit:3 http://ftpmaster.internal/ubuntu noble-updates InRelease 2364s Hit:4 http://ftpmaster.internal/ubuntu noble-security InRelease 2365s Reading package lists... 2365s Reading package lists... 2366s Building dependency tree... 2366s Reading state information... 2366s Calculating upgrade... 2366s 0 upgraded, 0 newly installed, 0 to remove and 0 not upgraded. 2366s Reading package lists... 2366s Building dependency tree... 2366s Reading state information... 2366s 0 upgraded, 0 newly installed, 0 to remove and 0 not upgraded. 2372s Reading package lists... 2372s Building dependency tree... 2372s Reading state information... 2372s Starting pkgProblemResolver with broken count: 0 2372s Starting 2 pkgProblemResolver with broken count: 0 2372s Done 2373s The following additional packages will be installed: 2373s libreadline8t64 libtcl8.6 python3-click python3-colorama yosys yosys-abc 2373s Suggested packages: 2373s tcl8.6 2373s Recommended packages: 2373s xdot 2373s The following packages will be REMOVED: 2373s libreadline8 2373s The following NEW packages will be installed: 2373s autopkgtest-satdep libreadline8t64 libtcl8.6 python3-click python3-colorama 2373s yosys yosys-abc 2373s 0 upgraded, 7 newly installed, 1 to remove and 0 not upgraded. 2373s Need to get 12.4 MB/12.4 MB of archives. 2373s After this operation, 42.0 MB of additional disk space will be used. 2373s Get:1 /tmp/autopkgtest.l2kRn3/2-autopkgtest-satdep.deb autopkgtest-satdep ppc64el 0 [708 B] 2373s Get:2 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libreadline8t64 ppc64el 8.2-3.1 [182 kB] 2373s Get:3 http://ftpmaster.internal/ubuntu noble/main ppc64el libtcl8.6 ppc64el 8.6.13+dfsg-2 [1179 kB] 2374s Get:4 http://ftpmaster.internal/ubuntu noble/main ppc64el python3-colorama all 0.4.6-4 [32.1 kB] 2374s Get:5 http://ftpmaster.internal/ubuntu noble/main ppc64el python3-click all 8.1.6-1 [79.0 kB] 2374s Get:6 http://ftpmaster.internal/ubuntu noble-proposed/universe ppc64el yosys-abc ppc64el 0.33-5build1 [7747 kB] 2381s Get:7 http://ftpmaster.internal/ubuntu noble-proposed/universe ppc64el yosys ppc64el 0.33-5build1 [3184 kB] 2383s Fetched 12.4 MB in 10s (1195 kB/s) 2383s dpkg: libreadline8:ppc64el: dependency problems, but removing anyway as you requested: 2383s parted depends on libreadline8 (>= 6.0). 2383s libpython3.12-stdlib:ppc64el depends on libreadline8 (>= 7.0~beta). 2383s libpython3.11-stdlib:ppc64el depends on libreadline8 (>= 7.0~beta). 2383s gpgsm depends on libreadline8 (>= 6.0). 2383s gpgconf depends on libreadline8 (>= 6.0). 2383s gpg depends on libreadline8 (>= 6.0). 2383s gawk depends on libreadline8 (>= 6.0). 2383s fdisk depends on libreadline8 (>= 6.0). 2383s bc depends on libreadline8 (>= 6.0). 2383s 2383s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 70095 files and directories currently installed.) 2383s Removing libreadline8:ppc64el (8.2-3) ... 2383s Selecting previously unselected package libreadline8t64:ppc64el. 2383s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 70083 files and directories currently installed.) 2383s Preparing to unpack .../0-libreadline8t64_8.2-3.1_ppc64el.deb ... 2383s Adding 'diversion of /lib/powerpc64le-linux-gnu/libhistory.so.8 to /lib/powerpc64le-linux-gnu/libhistory.so.8.usr-is-merged by libreadline8t64' 2383s Adding 'diversion of /lib/powerpc64le-linux-gnu/libhistory.so.8.2 to /lib/powerpc64le-linux-gnu/libhistory.so.8.2.usr-is-merged by libreadline8t64' 2383s Adding 'diversion of /lib/powerpc64le-linux-gnu/libreadline.so.8 to /lib/powerpc64le-linux-gnu/libreadline.so.8.usr-is-merged by libreadline8t64' 2383s Adding 'diversion of /lib/powerpc64le-linux-gnu/libreadline.so.8.2 to /lib/powerpc64le-linux-gnu/libreadline.so.8.2.usr-is-merged by libreadline8t64' 2383s Unpacking libreadline8t64:ppc64el (8.2-3.1) ... 2383s Selecting previously unselected package libtcl8.6:ppc64el. 2383s Preparing to unpack .../1-libtcl8.6_8.6.13+dfsg-2_ppc64el.deb ... 2383s Unpacking libtcl8.6:ppc64el (8.6.13+dfsg-2) ... 2383s Selecting previously unselected package python3-colorama. 2383s Preparing to unpack .../2-python3-colorama_0.4.6-4_all.deb ... 2383s Unpacking python3-colorama (0.4.6-4) ... 2383s Selecting previously unselected package python3-click. 2383s Preparing to unpack .../3-python3-click_8.1.6-1_all.deb ... 2384s Unpacking python3-click (8.1.6-1) ... 2384s Selecting previously unselected package yosys-abc. 2384s Preparing to unpack .../4-yosys-abc_0.33-5build1_ppc64el.deb ... 2384s Unpacking yosys-abc (0.33-5build1) ... 2384s Selecting previously unselected package yosys. 2384s Preparing to unpack .../5-yosys_0.33-5build1_ppc64el.deb ... 2384s Unpacking yosys (0.33-5build1) ... 2384s Selecting previously unselected package autopkgtest-satdep. 2384s Preparing to unpack .../6-2-autopkgtest-satdep.deb ... 2384s Unpacking autopkgtest-satdep (0) ... 2384s Setting up python3-colorama (0.4.6-4) ... 2384s Setting up python3-click (8.1.6-1) ... 2384s Setting up libtcl8.6:ppc64el (8.6.13+dfsg-2) ... 2384s Setting up libreadline8t64:ppc64el (8.2-3.1) ... 2384s Setting up yosys-abc (0.33-5build1) ... 2384s Setting up yosys (0.33-5build1) ... 2384s Setting up autopkgtest-satdep (0) ... 2384s Processing triggers for man-db (2.12.0-3) ... 2385s Processing triggers for libc-bin (2.39-0ubuntu2) ... 2387s (Reading database ... 70667 files and directories currently installed.) 2387s Removing autopkgtest-satdep (0) ... 2399s autopkgtest [21:47:26]: test ice: [----------------------- 2399s 2399s /----------------------------------------------------------------------------\ 2399s | | 2399s | yosys -- Yosys Open SYnthesis Suite | 2399s | | 2399s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2399s | | 2399s | Permission to use, copy, modify, and/or distribute this software for any | 2399s | purpose with or without fee is hereby granted, provided that the above | 2399s | copyright notice and this permission notice appear in all copies. | 2399s | | 2399s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2399s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2399s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2399s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2399s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2399s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2399s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2399s | | 2399s \----------------------------------------------------------------------------/ 2399s 2399s Yosys 0.33 (git sha1 2584903a060) 2399s 2399s 2399s -- Running command `read_verilog debian/tests/design_ice.v; synth_ice40 -blif /tmp/autopkgtest.l2kRn3/autopkgtest_tmp/design_ice.blif' -- 2399s 2399s 1. Executing Verilog-2005 frontend: debian/tests/design_ice.v 2399s Parsing Verilog input from `debian/tests/design_ice.v' to AST representation. 2399s Generating RTLIL representation for module `\design_ice'. 2399s Successfully finished Verilog frontend. 2399s 2399s 2. Executing SYNTH_ICE40 pass. 2399s 2399s 2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v 2400s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation. 2400s Generating RTLIL representation for module `\SB_IO'. 2400s Generating RTLIL representation for module `\SB_GB_IO'. 2400s Generating RTLIL representation for module `\SB_GB'. 2400s Generating RTLIL representation for module `\SB_LUT4'. 2400s Generating RTLIL representation for module `\SB_CARRY'. 2400s Generating RTLIL representation for module `\SB_DFF'. 2400s Generating RTLIL representation for module `\SB_DFFE'. 2400s Generating RTLIL representation for module `\SB_DFFSR'. 2400s Generating RTLIL representation for module `\SB_DFFR'. 2400s Generating RTLIL representation for module `\SB_DFFSS'. 2400s Generating RTLIL representation for module `\SB_DFFS'. 2400s Generating RTLIL representation for module `\SB_DFFESR'. 2400s Generating RTLIL representation for module `\SB_DFFER'. 2400s Generating RTLIL representation for module `\SB_DFFESS'. 2400s Generating RTLIL representation for module `\SB_DFFES'. 2400s Generating RTLIL representation for module `\SB_DFFN'. 2400s Generating RTLIL representation for module `\SB_DFFNE'. 2400s Generating RTLIL representation for module `\SB_DFFNSR'. 2400s Generating RTLIL representation for module `\SB_DFFNR'. 2400s Generating RTLIL representation for module `\SB_DFFNSS'. 2400s Generating RTLIL representation for module `\SB_DFFNS'. 2400s Generating RTLIL representation for module `\SB_DFFNESR'. 2400s Generating RTLIL representation for module `\SB_DFFNER'. 2400s Generating RTLIL representation for module `\SB_DFFNESS'. 2400s Generating RTLIL representation for module `\SB_DFFNES'. 2400s Generating RTLIL representation for module `\SB_RAM40_4K'. 2400s Generating RTLIL representation for module `\SB_RAM40_4KNR'. 2400s Generating RTLIL representation for module `\SB_RAM40_4KNW'. 2400s Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. 2400s Generating RTLIL representation for module `\ICESTORM_LC'. 2400s Generating RTLIL representation for module `\SB_PLL40_CORE'. 2400s Generating RTLIL representation for module `\SB_PLL40_PAD'. 2400s Generating RTLIL representation for module `\SB_PLL40_2_PAD'. 2400s Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. 2400s Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. 2400s Generating RTLIL representation for module `\SB_WARMBOOT'. 2400s Generating RTLIL representation for module `\SB_SPRAM256KA'. 2400s Generating RTLIL representation for module `\SB_HFOSC'. 2400s Generating RTLIL representation for module `\SB_LFOSC'. 2400s Generating RTLIL representation for module `\SB_RGBA_DRV'. 2400s Generating RTLIL representation for module `\SB_LED_DRV_CUR'. 2400s Generating RTLIL representation for module `\SB_RGB_DRV'. 2400s Generating RTLIL representation for module `\SB_I2C'. 2400s Generating RTLIL representation for module `\SB_SPI'. 2400s Generating RTLIL representation for module `\SB_LEDDA_IP'. 2400s Generating RTLIL representation for module `\SB_FILTER_50NS'. 2400s Generating RTLIL representation for module `\SB_IO_I3C'. 2400s Generating RTLIL representation for module `\SB_IO_OD'. 2400s Generating RTLIL representation for module `\SB_MAC16'. 2400s Generating RTLIL representation for module `\ICESTORM_RAM'. 2400s Successfully finished Verilog frontend. 2400s 2400s 2.2. Executing HIERARCHY pass (managing design hierarchy). 2400s 2400s 2.2.1. Finding top of design hierarchy.. 2400s root of 0 design levels: design_ice 2400s Automatically selected design_ice as design top module. 2400s 2400s 2.2.2. Analyzing design hierarchy.. 2400s Top module: \design_ice 2400s 2400s 2.2.3. Analyzing design hierarchy.. 2400s Top module: \design_ice 2400s Removed 0 unused modules. 2400s 2400s 2.3. Executing PROC pass (convert processes to netlists). 2400s 2400s 2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2400s Cleaned up 0 empty switches. 2400s 2400s 2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2400s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243 in module SB_DFFNES. 2400s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236 in module SB_DFFNESS. 2400s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232 in module SB_DFFNER. 2400s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225 in module SB_DFFNESR. 2400s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222 in module SB_DFFNS. 2400s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219 in module SB_DFFNSS. 2400s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216 in module SB_DFFNR. 2400s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213 in module SB_DFFNSR. 2400s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205 in module SB_DFFES. 2400s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198 in module SB_DFFESS. 2400s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194 in module SB_DFFER. 2400s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187 in module SB_DFFESR. 2400s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184 in module SB_DFFS. 2400s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181 in module SB_DFFSS. 2400s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178 in module SB_DFFR. 2400s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175 in module SB_DFFSR. 2400s Marked 1 switch rules as full_case in process $proc$debian/tests/design_ice.v:6$1 in module design_ice. 2400s Removed a total of 0 dead cases. 2400s 2400s 2.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2400s Removed 8 redundant assignments. 2400s Promoted 23 assignments to connections. 2400s 2400s 2.3.4. Executing PROC_INIT pass (extract init attributes). 2400s Found init rule in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$246'. 2400s Set init value: \Q = 1'0 2400s Found init rule in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$242'. 2400s Set init value: \Q = 1'0 2400s Found init rule in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$235'. 2400s Set init value: \Q = 1'0 2400s Found init rule in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$231'. 2400s Set init value: \Q = 1'0 2400s Found init rule in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$224'. 2400s Set init value: \Q = 1'0 2400s Found init rule in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$221'. 2400s Set init value: \Q = 1'0 2400s Found init rule in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$218'. 2400s Set init value: \Q = 1'0 2400s Found init rule in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$215'. 2400s Set init value: \Q = 1'0 2400s Found init rule in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$212'. 2400s Set init value: \Q = 1'0 2400s Found init rule in `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 2400s Set init value: \Q = 1'0 2400s Found init rule in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 2400s Set init value: \Q = 1'0 2400s Found init rule in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$204'. 2400s Set init value: \Q = 1'0 2400s Found init rule in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$197'. 2400s Set init value: \Q = 1'0 2400s Found init rule in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$193'. 2400s Set init value: \Q = 1'0 2400s Found init rule in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$186'. 2400s Set init value: \Q = 1'0 2400s Found init rule in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$183'. 2400s Set init value: \Q = 1'0 2400s Found init rule in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$180'. 2400s Set init value: \Q = 1'0 2400s Found init rule in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$177'. 2400s Set init value: \Q = 1'0 2400s Found init rule in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$174'. 2400s Set init value: \Q = 1'0 2400s Found init rule in `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 2400s Set init value: \Q = 1'0 2400s Found init rule in `\design_ice.$proc$debian/tests/design_ice.v:3$2'. 2400s Set init value: \ready = 1'0 2400s 2400s 2.3.5. Executing PROC_ARST pass (detect async resets in processes). 2400s Found async reset \S in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'. 2400s Found async reset \R in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'. 2400s Found async reset \S in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222'. 2400s Found async reset \R in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216'. 2400s Found async reset \S in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'. 2400s Found async reset \R in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'. 2400s Found async reset \S in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184'. 2400s Found async reset \R in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178'. 2400s 2400s 2.3.6. Executing PROC_ROM pass (convert switches to ROMs). 2400s Converted 0 switches. 2400s 2400s 2400s 2.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2400s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$246'. 2400s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'. 2400s 1/1: $0\Q[0:0] 2400s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$242'. 2400s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236'. 2400s 1/1: $0\Q[0:0] 2400s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$235'. 2400s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'. 2400s 1/1: $0\Q[0:0] 2400s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$231'. 2400s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225'. 2400s 1/1: $0\Q[0:0] 2400s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$224'. 2400s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222'. 2400s 1/1: $0\Q[0:0] 2400s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$221'. 2400s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219'. 2400s 1/1: $0\Q[0:0] 2400s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$218'. 2400s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216'. 2400s 1/1: $0\Q[0:0] 2400s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$215'. 2400s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213'. 2400s 1/1: $0\Q[0:0] 2400s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$212'. 2400s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$211'. 2400s 1/1: $0\Q[0:0] 2400s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 2400s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$209'. 2400s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 2400s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'. 2400s 1/1: $0\Q[0:0] 2400s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$204'. 2400s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198'. 2400s 1/1: $0\Q[0:0] 2400s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$197'. 2400s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'. 2400s 1/1: $0\Q[0:0] 2400s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$193'. 2400s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187'. 2400s 1/1: $0\Q[0:0] 2400s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$186'. 2400s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184'. 2400s 1/1: $0\Q[0:0] 2400s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$183'. 2400s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181'. 2400s 1/1: $0\Q[0:0] 2400s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$180'. 2400s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178'. 2400s 1/1: $0\Q[0:0] 2400s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$177'. 2400s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175'. 2400s 1/1: $0\Q[0:0] 2400s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$174'. 2400s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$173'. 2400s 1/1: $0\Q[0:0] 2400s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 2400s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$171'. 2400s Creating decoders for process `\design_ice.$proc$debian/tests/design_ice.v:3$2'. 2400s Creating decoders for process `\design_ice.$proc$debian/tests/design_ice.v:6$1'. 2400s 1/2: $0\value[0:0] 2400s 2/2: $0\ready[0:0] 2400s 2400s 2.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2400s 2400s 2.3.9. Executing PROC_DFF pass (convert process syncs to FFs). 2400s Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'. 2400s created $adff cell `$procdff$433' with negative edge clock and positive level reset. 2400s Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236'. 2400s created $dff cell `$procdff$434' with negative edge clock. 2400s Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'. 2400s created $adff cell `$procdff$435' with negative edge clock and positive level reset. 2400s Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225'. 2400s created $dff cell `$procdff$436' with negative edge clock. 2400s Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222'. 2400s created $adff cell `$procdff$437' with negative edge clock and positive level reset. 2400s Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219'. 2400s created $dff cell `$procdff$438' with negative edge clock. 2400s Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216'. 2400s created $adff cell `$procdff$439' with negative edge clock and positive level reset. 2400s Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213'. 2400s created $dff cell `$procdff$440' with negative edge clock. 2400s Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$211'. 2400s created $dff cell `$procdff$441' with negative edge clock. 2400s Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$209'. 2400s created $dff cell `$procdff$442' with negative edge clock. 2400s Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'. 2400s created $adff cell `$procdff$443' with positive edge clock and positive level reset. 2400s Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198'. 2400s created $dff cell `$procdff$444' with positive edge clock. 2400s Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'. 2400s created $adff cell `$procdff$445' with positive edge clock and positive level reset. 2400s Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187'. 2400s created $dff cell `$procdff$446' with positive edge clock. 2400s Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184'. 2400s created $adff cell `$procdff$447' with positive edge clock and positive level reset. 2400s Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181'. 2400s created $dff cell `$procdff$448' with positive edge clock. 2400s Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178'. 2400s created $adff cell `$procdff$449' with positive edge clock and positive level reset. 2400s Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175'. 2400s created $dff cell `$procdff$450' with positive edge clock. 2400s Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$173'. 2400s created $dff cell `$procdff$451' with positive edge clock. 2400s Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$171'. 2400s created $dff cell `$procdff$452' with positive edge clock. 2400s Creating register for signal `\design_ice.\ready' using process `\design_ice.$proc$debian/tests/design_ice.v:6$1'. 2400s created $dff cell `$procdff$453' with positive edge clock. 2400s Creating register for signal `\design_ice.\value' using process `\design_ice.$proc$debian/tests/design_ice.v:6$1'. 2400s created $dff cell `$procdff$454' with positive edge clock. 2400s 2400s 2.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2400s 2400s 2.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2400s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$246'. 2400s Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'. 2400s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'. 2400s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$242'. 2400s Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236'. 2400s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236'. 2400s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$235'. 2400s Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'. 2400s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'. 2400s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$231'. 2400s Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225'. 2400s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225'. 2400s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$224'. 2400s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222'. 2400s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$221'. 2400s Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219'. 2400s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219'. 2400s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$218'. 2400s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216'. 2400s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$215'. 2400s Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213'. 2400s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213'. 2400s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$212'. 2400s Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$211'. 2400s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$211'. 2400s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 2400s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$209'. 2400s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 2400s Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'. 2400s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'. 2400s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$204'. 2400s Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198'. 2400s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198'. 2400s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$197'. 2400s Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'. 2400s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'. 2400s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$193'. 2400s Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187'. 2400s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187'. 2400s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$186'. 2400s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184'. 2400s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$183'. 2400s Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181'. 2400s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181'. 2400s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$180'. 2400s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178'. 2400s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$177'. 2400s Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175'. 2400s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175'. 2400s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$174'. 2400s Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$173'. 2400s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$173'. 2400s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 2400s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$171'. 2400s Removing empty process `design_ice.$proc$debian/tests/design_ice.v:3$2'. 2400s Found and cleaned up 1 empty switch in `\design_ice.$proc$debian/tests/design_ice.v:6$1'. 2400s Removing empty process `design_ice.$proc$debian/tests/design_ice.v:6$1'. 2400s Cleaned up 19 empty switches. 2400s 2400s 2.3.12. Executing OPT_EXPR pass (perform const folding). 2400s Optimizing module design_ice. 2400s 2400s 2.4. Executing FLATTEN pass (flatten design). 2400s 2400s 2.5. Executing TRIBUF pass. 2400s 2400s 2.6. Executing DEMINOUT pass (demote inout ports to input or output). 2400s 2400s 2.7. Executing OPT_EXPR pass (perform const folding). 2400s Optimizing module design_ice. 2400s 2400s 2.8. Executing OPT_CLEAN pass (remove unused cells and wires). 2400s Finding unused cells or wires in module \design_ice.. 2400s Removed 0 unused cells and 5 unused wires. 2400s 2400s 2400s 2.9. Executing CHECK pass (checking for obvious problems). 2400s Checking module design_ice... 2400s Found and reported 0 problems. 2400s 2400s 2.10. Executing OPT pass (performing simple optimizations). 2400s 2400s 2.10.1. Executing OPT_EXPR pass (perform const folding). 2400s Optimizing module design_ice. 2400s 2400s 2.10.2. Executing OPT_MERGE pass (detect identical cells). 2400s Finding identical cells in module `\design_ice'. 2400s Removed a total of 0 cells. 2400s 2400s 2.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 2400s Running muxtree optimizer on module \design_ice.. 2400s Creating internal representation of mux trees. 2400s Evaluating internal representation of mux trees. 2400s Replacing known input bits on port B of cell $procmux$431: \ready -> 1'1 2400s Analyzing evaluation results. 2400s Removed 0 multiplexer ports. 2400s 2400s 2400s 2.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 2400s Optimizing cells in module \design_ice. 2400s Optimizing cells in module \design_ice. 2400s Performed a total of 1 changes. 2400s 2400s 2.10.5. Executing OPT_MERGE pass (detect identical cells). 2400s Finding identical cells in module `\design_ice'. 2400s Removed a total of 0 cells. 2400s 2400s 2.10.6. Executing OPT_DFF pass (perform DFF optimizations). 2400s 2400s 2.10.7. Executing OPT_CLEAN pass (remove unused cells and wires). 2400s Finding unused cells or wires in module \design_ice.. 2400s Removed 0 unused cells and 1 unused wires. 2400s 2400s 2400s 2.10.8. Executing OPT_EXPR pass (perform const folding). 2400s Optimizing module design_ice. 2400s 2400s 2.10.9. Rerunning OPT passes. (Maybe there is more to do..) 2400s 2400s 2.10.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 2400s Running muxtree optimizer on module \design_ice.. 2400s Creating internal representation of mux trees. 2400s Evaluating internal representation of mux trees. 2400s Analyzing evaluation results. 2400s Removed 0 multiplexer ports. 2400s 2400s 2400s 2.10.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 2400s Optimizing cells in module \design_ice. 2400s Performed a total of 0 changes. 2400s 2400s 2.10.12. Executing OPT_MERGE pass (detect identical cells). 2400s Finding identical cells in module `\design_ice'. 2400s Removed a total of 0 cells. 2400s 2400s 2.10.13. Executing OPT_DFF pass (perform DFF optimizations). 2400s 2400s 2.10.14. Executing OPT_CLEAN pass (remove unused cells and wires). 2400s Finding unused cells or wires in module \design_ice.. 2400s 2400s 2.10.15. Executing OPT_EXPR pass (perform const folding). 2400s Optimizing module design_ice. 2400s 2400s 2.10.16. Finished OPT passes. (There is nothing left to do.) 2400s 2400s 2.11. Executing FSM pass (extract and optimize FSM). 2400s 2400s 2.11.1. Executing FSM_DETECT pass (finding FSMs in design). 2400s 2400s 2.11.2. Executing FSM_EXTRACT pass (extracting FSM from design). 2400s 2400s 2.11.3. Executing FSM_OPT pass (simple optimizations of FSMs). 2400s 2400s 2.11.4. Executing OPT_CLEAN pass (remove unused cells and wires). 2400s Finding unused cells or wires in module \design_ice.. 2400s 2400s 2.11.5. Executing FSM_OPT pass (simple optimizations of FSMs). 2400s 2400s 2.11.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 2400s 2400s 2.11.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 2400s 2400s 2.11.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 2400s 2400s 2.12. Executing OPT pass (performing simple optimizations). 2400s 2400s 2.12.1. Executing OPT_EXPR pass (perform const folding). 2400s Optimizing module design_ice. 2400s 2400s 2.12.2. Executing OPT_MERGE pass (detect identical cells). 2400s Finding identical cells in module `\design_ice'. 2400s Removed a total of 0 cells. 2400s 2400s 2.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 2400s Running muxtree optimizer on module \design_ice.. 2400s Creating internal representation of mux trees. 2400s Evaluating internal representation of mux trees. 2400s Analyzing evaluation results. 2400s Removed 0 multiplexer ports. 2400s 2400s 2400s 2.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 2400s Optimizing cells in module \design_ice. 2400s Performed a total of 0 changes. 2400s 2400s 2.12.5. Executing OPT_MERGE pass (detect identical cells). 2400s Finding identical cells in module `\design_ice'. 2400s Removed a total of 0 cells. 2400s 2400s 2.12.6. Executing OPT_DFF pass (perform DFF optimizations). 2400s Adding EN signal on $procdff$454 ($dff) from module design_ice (D = \I1, Q = \value). 2400s 2400s 2.12.7. Executing OPT_CLEAN pass (remove unused cells and wires). 2400s Finding unused cells or wires in module \design_ice.. 2400s Removed 1 unused cells and 1 unused wires. 2400s 2400s 2400s 2.12.8. Executing OPT_EXPR pass (perform const folding). 2400s Optimizing module design_ice. 2400s 2400s 2.12.9. Rerunning OPT passes. (Maybe there is more to do..) 2400s 2400s 2.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 2400s Running muxtree optimizer on module \design_ice.. 2400s Creating internal representation of mux trees. 2400s No muxes found in this module. 2400s Removed 0 multiplexer ports. 2400s 2400s 2.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 2400s Optimizing cells in module \design_ice. 2400s Performed a total of 0 changes. 2400s 2400s 2.12.12. Executing OPT_MERGE pass (detect identical cells). 2400s Finding identical cells in module `\design_ice'. 2400s Removed a total of 0 cells. 2400s 2400s 2.12.13. Executing OPT_DFF pass (perform DFF optimizations). 2400s 2400s 2.12.14. Executing OPT_CLEAN pass (remove unused cells and wires). 2400s Finding unused cells or wires in module \design_ice.. 2400s 2400s 2.12.15. Executing OPT_EXPR pass (perform const folding). 2400s Optimizing module design_ice. 2400s 2400s 2.12.16. Finished OPT passes. (There is nothing left to do.) 2400s 2400s 2.13. Executing WREDUCE pass (reducing word size of cells). 2400s 2400s 2.14. Executing PEEPOPT pass (run peephole optimizers). 2400s 2400s 2.15. Executing OPT_CLEAN pass (remove unused cells and wires). 2400s Finding unused cells or wires in module \design_ice.. 2400s 2400s 2.16. Executing SHARE pass (SAT-based resource sharing). 2400s 2400s 2.17. Executing TECHMAP pass (map to technology primitives). 2400s 2400s 2.17.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v 2400s Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation. 2400s Generating RTLIL representation for module `\_90_lut_cmp_'. 2400s Successfully finished Verilog frontend. 2400s 2400s 2.17.2. Continuing TECHMAP pass. 2400s No more expansions possible. 2400s 2400s 2400s 2.18. Executing OPT_EXPR pass (perform const folding). 2400s Optimizing module design_ice. 2400s 2400s 2.19. Executing OPT_CLEAN pass (remove unused cells and wires). 2400s Finding unused cells or wires in module \design_ice.. 2400s 2400s 2.20. Executing ALUMACC pass (create $alu and $macc cells). 2400s Extracting $alu and $macc cells in module design_ice: 2400s created 0 $alu and 0 $macc cells. 2400s 2400s 2.21. Executing OPT pass (performing simple optimizations). 2400s 2400s 2.21.1. Executing OPT_EXPR pass (perform const folding). 2400s Optimizing module design_ice. 2400s 2400s 2.21.2. Executing OPT_MERGE pass (detect identical cells). 2400s Finding identical cells in module `\design_ice'. 2400s Removed a total of 0 cells. 2400s 2400s 2.21.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 2400s Running muxtree optimizer on module \design_ice.. 2400s Creating internal representation of mux trees. 2400s No muxes found in this module. 2400s Removed 0 multiplexer ports. 2400s 2400s 2.21.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 2400s Optimizing cells in module \design_ice. 2400s Performed a total of 0 changes. 2400s 2400s 2.21.5. Executing OPT_MERGE pass (detect identical cells). 2400s Finding identical cells in module `\design_ice'. 2400s Removed a total of 0 cells. 2400s 2400s 2.21.6. Executing OPT_DFF pass (perform DFF optimizations). 2400s 2400s 2.21.7. Executing OPT_CLEAN pass (remove unused cells and wires). 2400s Finding unused cells or wires in module \design_ice.. 2400s 2400s 2.21.8. Executing OPT_EXPR pass (perform const folding). 2400s Optimizing module design_ice. 2400s 2400s 2.21.9. Finished OPT passes. (There is nothing left to do.) 2400s 2400s 2.22. Executing MEMORY pass. 2400s 2400s 2.22.1. Executing OPT_MEM pass (optimize memories). 2400s Performed a total of 0 transformations. 2400s 2400s 2.22.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). 2400s Performed a total of 0 transformations. 2400s 2400s 2.22.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 2400s 2400s 2.22.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 2400s 2400s 2.22.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 2400s 2400s 2.22.6. Executing OPT_CLEAN pass (remove unused cells and wires). 2400s Finding unused cells or wires in module \design_ice.. 2400s 2400s 2.22.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 2400s 2400s 2.22.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). 2400s Performed a total of 0 transformations. 2400s 2400s 2.22.9. Executing OPT_CLEAN pass (remove unused cells and wires). 2400s Finding unused cells or wires in module \design_ice.. 2400s 2400s 2.22.10. Executing MEMORY_COLLECT pass (generating $mem cells). 2400s 2400s 2.23. Executing OPT_CLEAN pass (remove unused cells and wires). 2400s Finding unused cells or wires in module \design_ice.. 2400s 2400s 2.24. Executing MEMORY_LIBMAP pass (mapping memories to cells). 2400s 2400s 2.25. Executing TECHMAP pass (map to technology primitives). 2400s 2400s 2.25.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v 2400s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation. 2400s Generating RTLIL representation for module `\$__ICE40_RAM4K_'. 2400s Successfully finished Verilog frontend. 2400s 2400s 2.25.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/spram_map.v 2400s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/spram_map.v' to AST representation. 2400s Generating RTLIL representation for module `\$__ICE40_SPRAM_'. 2400s Successfully finished Verilog frontend. 2400s 2400s 2.25.3. Continuing TECHMAP pass. 2400s No more expansions possible. 2400s 2400s 2400s 2.26. Executing ICE40_BRAMINIT pass. 2400s 2400s 2.27. Executing OPT pass (performing simple optimizations). 2400s 2400s 2.27.1. Executing OPT_EXPR pass (perform const folding). 2400s Optimizing module design_ice. 2400s 2400s 2.27.2. Executing OPT_MERGE pass (detect identical cells). 2400s Finding identical cells in module `\design_ice'. 2400s Removed a total of 0 cells. 2400s 2400s 2.27.3. Executing OPT_DFF pass (perform DFF optimizations). 2400s 2400s 2.27.4. Executing OPT_CLEAN pass (remove unused cells and wires). 2400s Finding unused cells or wires in module \design_ice.. 2400s 2400s 2.27.5. Finished fast OPT passes. 2400s 2400s 2.28. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 2400s 2400s 2.29. Executing OPT pass (performing simple optimizations). 2400s 2400s 2.29.1. Executing OPT_EXPR pass (perform const folding). 2400s Optimizing module design_ice. 2400s 2400s 2.29.2. Executing OPT_MERGE pass (detect identical cells). 2400s Finding identical cells in module `\design_ice'. 2400s Removed a total of 0 cells. 2400s 2400s 2.29.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 2400s Running muxtree optimizer on module \design_ice.. 2400s Creating internal representation of mux trees. 2400s No muxes found in this module. 2400s Removed 0 multiplexer ports. 2400s 2400s 2.29.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 2400s Optimizing cells in module \design_ice. 2400s Performed a total of 0 changes. 2400s 2400s 2.29.5. Executing OPT_MERGE pass (detect identical cells). 2400s Finding identical cells in module `\design_ice'. 2400s Removed a total of 0 cells. 2400s 2400s 2.29.6. Executing OPT_DFF pass (perform DFF optimizations). 2400s 2400s 2.29.7. Executing OPT_CLEAN pass (remove unused cells and wires). 2400s Finding unused cells or wires in module \design_ice.. 2400s 2400s 2.29.8. Executing OPT_EXPR pass (perform const folding). 2400s Optimizing module design_ice. 2400s 2400s 2.29.9. Finished OPT passes. (There is nothing left to do.) 2400s 2400s 2.30. Executing ICE40_WRAPCARRY pass (wrap carries). 2400s 2400s 2.31. Executing TECHMAP pass (map to technology primitives). 2400s 2400s 2.31.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v 2400s Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation. 2400s Generating RTLIL representation for module `\_90_simplemap_bool_ops'. 2400s Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. 2400s Generating RTLIL representation for module `\_90_simplemap_logic_ops'. 2400s Generating RTLIL representation for module `\_90_simplemap_compare_ops'. 2400s Generating RTLIL representation for module `\_90_simplemap_various'. 2400s Generating RTLIL representation for module `\_90_simplemap_registers'. 2400s Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. 2400s Generating RTLIL representation for module `\_90_shift_shiftx'. 2400s Generating RTLIL representation for module `\_90_fa'. 2400s Generating RTLIL representation for module `\_90_lcu'. 2400s Generating RTLIL representation for module `\_90_alu'. 2400s Generating RTLIL representation for module `\_90_macc'. 2400s Generating RTLIL representation for module `\_90_alumacc'. 2400s Generating RTLIL representation for module `\$__div_mod_u'. 2400s Generating RTLIL representation for module `\$__div_mod_trunc'. 2400s Generating RTLIL representation for module `\_90_div'. 2400s Generating RTLIL representation for module `\_90_mod'. 2400s Generating RTLIL representation for module `\$__div_mod_floor'. 2400s Generating RTLIL representation for module `\_90_divfloor'. 2400s Generating RTLIL representation for module `\_90_modfloor'. 2400s Generating RTLIL representation for module `\_90_pow'. 2400s Generating RTLIL representation for module `\_90_pmux'. 2400s Generating RTLIL representation for module `\_90_demux'. 2400s Generating RTLIL representation for module `\_90_lut'. 2400s Successfully finished Verilog frontend. 2400s 2400s 2.31.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v 2400s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation. 2400s Generating RTLIL representation for module `\_80_ice40_alu'. 2400s Successfully finished Verilog frontend. 2400s 2400s 2.31.3. Continuing TECHMAP pass. 2400s Using extmapper simplemap for cells of type $dffe. 2400s Using extmapper simplemap for cells of type $dff. 2400s No more expansions possible. 2400s 2400s 2400s 2.32. Executing OPT pass (performing simple optimizations). 2400s 2400s 2.32.1. Executing OPT_EXPR pass (perform const folding). 2400s Optimizing module design_ice. 2400s 2400s 2.32.2. Executing OPT_MERGE pass (detect identical cells). 2400s Finding identical cells in module `\design_ice'. 2400s Removed a total of 0 cells. 2400s 2400s 2.32.3. Executing OPT_DFF pass (perform DFF optimizations). 2400s 2400s 2.32.4. Executing OPT_CLEAN pass (remove unused cells and wires). 2400s Finding unused cells or wires in module \design_ice.. 2400s 2400s 2.32.5. Finished fast OPT passes. 2400s 2400s 2.33. Executing ICE40_OPT pass (performing simple optimizations). 2400s 2400s 2.33.1. Running ICE40 specific optimizations. 2400s 2400s 2.33.2. Executing OPT_EXPR pass (perform const folding). 2400s Optimizing module design_ice. 2400s 2400s 2.33.3. Executing OPT_MERGE pass (detect identical cells). 2400s Finding identical cells in module `\design_ice'. 2400s Removed a total of 0 cells. 2400s 2400s 2.33.4. Executing OPT_DFF pass (perform DFF optimizations). 2400s 2400s 2.33.5. Executing OPT_CLEAN pass (remove unused cells and wires). 2400s Finding unused cells or wires in module \design_ice.. 2400s 2400s 2.33.6. Finished OPT passes. (There is nothing left to do.) 2400s 2400s 2.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 2400s 2400s 2.35. Executing TECHMAP pass (map to technology primitives). 2400s 2400s 2.35.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 2400s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 2400s Generating RTLIL representation for module `\$_DFF_N_'. 2400s Generating RTLIL representation for module `\$_DFF_P_'. 2400s Generating RTLIL representation for module `\$_DFFE_NP_'. 2400s Generating RTLIL representation for module `\$_DFFE_PP_'. 2400s Generating RTLIL representation for module `\$_DFF_NP0_'. 2400s Generating RTLIL representation for module `\$_DFF_NP1_'. 2400s Generating RTLIL representation for module `\$_DFF_PP0_'. 2400s Generating RTLIL representation for module `\$_DFF_PP1_'. 2400s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 2400s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 2400s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 2400s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 2400s Generating RTLIL representation for module `\$_SDFF_NP0_'. 2400s Generating RTLIL representation for module `\$_SDFF_NP1_'. 2400s Generating RTLIL representation for module `\$_SDFF_PP0_'. 2400s Generating RTLIL representation for module `\$_SDFF_PP1_'. 2400s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 2400s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 2400s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 2400s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 2400s Successfully finished Verilog frontend. 2400s 2400s 2.35.2. Continuing TECHMAP pass. 2400s Using template \$_DFF_P_ for cells of type $_DFF_P_. 2400s Using template \$_DFFE_PP_ for cells of type $_DFFE_PP_. 2400s No more expansions possible. 2400s 2400s 2400s 2.36. Executing OPT_EXPR pass (perform const folding). 2400s Optimizing module design_ice. 2400s 2400s 2.37. Executing SIMPLEMAP pass (map simple cells to gate primitives). 2400s 2400s 2.38. Executing ICE40_OPT pass (performing simple optimizations). 2400s 2400s 2.38.1. Running ICE40 specific optimizations. 2400s 2400s 2.38.2. Executing OPT_EXPR pass (perform const folding). 2400s Optimizing module design_ice. 2400s 2400s 2.38.3. Executing OPT_MERGE pass (detect identical cells). 2400s Finding identical cells in module `\design_ice'. 2400s Removed a total of 0 cells. 2400s 2400s 2.38.4. Executing OPT_DFF pass (perform DFF optimizations). 2400s 2400s 2.38.5. Executing OPT_CLEAN pass (remove unused cells and wires). 2400s Finding unused cells or wires in module \design_ice.. 2400s Removed 0 unused cells and 9 unused wires. 2400s 2400s 2400s 2.38.6. Rerunning OPT passes. (Removed registers in this run.) 2400s 2400s 2.38.7. Running ICE40 specific optimizations. 2400s 2400s 2.38.8. Executing OPT_EXPR pass (perform const folding). 2400s Optimizing module design_ice. 2400s 2400s 2.38.9. Executing OPT_MERGE pass (detect identical cells). 2400s Finding identical cells in module `\design_ice'. 2400s Removed a total of 0 cells. 2400s 2400s 2.38.10. Executing OPT_DFF pass (perform DFF optimizations). 2400s 2400s 2.38.11. Executing OPT_CLEAN pass (remove unused cells and wires). 2400s Finding unused cells or wires in module \design_ice.. 2400s 2400s 2.38.12. Finished OPT passes. (There is nothing left to do.) 2400s 2400s 2.39. Executing TECHMAP pass (map to technology primitives). 2400s 2400s 2.39.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v 2400s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation. 2400s Generating RTLIL representation for module `\$_DLATCH_N_'. 2400s Generating RTLIL representation for module `\$_DLATCH_P_'. 2400s Successfully finished Verilog frontend. 2400s 2400s 2.39.2. Continuing TECHMAP pass. 2400s No more expansions possible. 2400s 2400s 2400s 2.40. Executing ABC pass (technology mapping using ABC). 2400s 2400s 2.40.1. Extracting gate netlist of module `\design_ice' to `/input.blif'.. 2400s Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs. 2400s Don't call ABC as there is nothing to map. 2400s Removing temp directory. 2400s 2400s 2.41. Executing ICE40_WRAPCARRY pass (wrap carries). 2400s 2400s 2.42. Executing TECHMAP pass (map to technology primitives). 2400s 2400s 2.42.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 2400s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 2400s Generating RTLIL representation for module `\$_DFF_N_'. 2400s Generating RTLIL representation for module `\$_DFF_P_'. 2400s Generating RTLIL representation for module `\$_DFFE_NP_'. 2400s Generating RTLIL representation for module `\$_DFFE_PP_'. 2400s Generating RTLIL representation for module `\$_DFF_NP0_'. 2400s Generating RTLIL representation for module `\$_DFF_NP1_'. 2400s Generating RTLIL representation for module `\$_DFF_PP0_'. 2400s Generating RTLIL representation for module `\$_DFF_PP1_'. 2400s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 2400s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 2400s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 2400s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 2400s Generating RTLIL representation for module `\$_SDFF_NP0_'. 2400s Generating RTLIL representation for module `\$_SDFF_NP1_'. 2400s Generating RTLIL representation for module `\$_SDFF_PP0_'. 2400s Generating RTLIL representation for module `\$_SDFF_PP1_'. 2400s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 2400s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 2400s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 2400s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 2400s Successfully finished Verilog frontend. 2400s 2400s 2.42.2. Continuing TECHMAP pass. 2400s No more expansions possible. 2400s 2400s 2400s 2.43. Executing OPT_LUT pass (optimize LUTs). 2400s Discovering LUTs. 2400s Number of LUTs: 0 2400s with \SB_CARRY (#0) 0 2400s with \SB_CARRY (#1) 0 2400s 2400s Eliminating LUTs. 2400s Number of LUTs: 0 2400s with \SB_CARRY (#0) 0 2400s with \SB_CARRY (#1) 0 2400s 2400s Combining LUTs. 2400s Number of LUTs: 0 2400s with \SB_CARRY (#0) 0 2400s with \SB_CARRY (#1) 0 2400s 2400s Eliminated 0 LUTs. 2400s Combined 0 LUTs. 2400s 2400s 2.44. Executing TECHMAP pass (map to technology primitives). 2400s 2400s 2.44.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v 2400s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation. 2400s Generating RTLIL representation for module `\$lut'. 2400s Successfully finished Verilog frontend. 2400s 2400s 2.44.2. Continuing TECHMAP pass. 2400s No more expansions possible. 2400s 2400s 2400s 2.45. Executing AUTONAME pass. 2400s Renamed 2 objects in module design_ice (2 iterations). 2400s 2400s 2400s 2.46. Executing HIERARCHY pass (managing design hierarchy). 2400s 2400s 2.46.1. Analyzing design hierarchy.. 2400s Top module: \design_ice 2400s 2400s 2.46.2. Analyzing design hierarchy.. 2400s Top module: \design_ice 2400s Removed 0 unused modules. 2400s 2400s 2.47. Printing statistics. 2400s 2400s === design_ice === 2400s 2400s Number of wires: 5 2400s Number of wire bits: 5 2400s Number of public wires: 5 2400s Number of public wire bits: 5 2400s Number of memories: 0 2400s Number of memory bits: 0 2400s Number of processes: 0 2400s Number of cells: 2 2400s SB_DFF 1 2400s SB_DFFE 1 2400s 2400s 2.48. Executing CHECK pass (checking for obvious problems). 2400s Checking module design_ice... 2400s Found and reported 0 problems. 2400s 2400s 2.49. Executing BLIF backend. 2400s 2400s End of script. Logfile hash: 7ac01acf69, CPU: user 0.90s system 0.00s, MEM: 20.00 MB peak 2400s Yosys 0.33 (git sha1 2584903a060) 2400s Time spent: 73% 13x read_verilog (0 sec), 7% 1x synth_ice40 (0 sec), ... 2401s autopkgtest [21:47:28]: test ice: -----------------------] 2401s ice PASS 2401s autopkgtest [21:47:28]: test ice: - - - - - - - - - - results - - - - - - - - - - 2402s autopkgtest [21:47:29]: test smtbc: preparing testbed 2403s Reading package lists... 2404s Building dependency tree... 2404s Reading state information... 2404s Starting pkgProblemResolver with broken count: 0 2404s Starting 2 pkgProblemResolver with broken count: 0 2404s Done 2404s The following NEW packages will be installed: 2404s autopkgtest-satdep 2404s 0 upgraded, 1 newly installed, 0 to remove and 0 not upgraded. 2404s Need to get 0 B/708 B of archives. 2404s After this operation, 0 B of additional disk space will be used. 2404s Get:1 /tmp/autopkgtest.l2kRn3/3-autopkgtest-satdep.deb autopkgtest-satdep ppc64el 0 [708 B] 2404s Selecting previously unselected package autopkgtest-satdep. 2404s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 70667 files and directories currently installed.) 2404s Preparing to unpack .../3-autopkgtest-satdep.deb ... 2404s Unpacking autopkgtest-satdep (0) ... 2404s Setting up autopkgtest-satdep (0) ... 2406s (Reading database ... 70667 files and directories currently installed.) 2406s Removing autopkgtest-satdep (0) ... 2407s autopkgtest [21:47:34]: test smtbc: [----------------------- 2407s autopkgtest [21:47:34]: test smtbc: -----------------------] 2408s smtbc PASS 2408s autopkgtest [21:47:35]: test smtbc: - - - - - - - - - - results - - - - - - - - - - 2408s autopkgtest [21:47:35]: @@@@@@@@@@@@@@@@@@@@ summary 2408s yosys-testsuite PASS 2408s ice PASS 2408s smtbc PASS 2420s Creating nova instance adt-noble-ppc64el-yosys-20240319-210727-juju-7f2275-prod-proposed-migration-environment-2 from image adt/ubuntu-noble-ppc64el-server-20240319.img (UUID 6e7a6c13-d651-45a1-a24f-48d9d59effd9)... 2420s Creating nova instance adt-noble-ppc64el-yosys-20240319-210727-juju-7f2275-prod-proposed-migration-environment-2 from image adt/ubuntu-noble-ppc64el-server-20240319.img (UUID 6e7a6c13-d651-45a1-a24f-48d9d59effd9)...