  0s autopkgtest [08:02:36]: starting date and time: 2024-03-27 08:02:36+0000
  0s autopkgtest [08:02:36]: git checkout: 4a1cd702 l/adt_testbed: don't blame the testbed for unsolvable build deps
  0s autopkgtest [08:02:36]: host juju-7f2275-prod-proposed-migration-environment-3; command line: /home/ubuntu/autopkgtest/runner/autopkgtest --output-dir /tmp/autopkgtest-work.szfp17wr/out --timeout-copy=6000 --setup-commands /home/ubuntu/autopkgtest-cloud/worker-config-production/setup-canonical.sh --apt-pocket=proposed --apt-upgrade fpga-icestorm --timeout-short=300 --timeout-copy=20000 --timeout-build=20000 --env=ADT_TEST_TRIGGERS=python3-defaults/3.12.2-0ubuntu1 -- ssh -s /home/ubuntu/autopkgtest/ssh-setup/nova -- --flavor autopkgtest --security-groups autopkgtest-juju-7f2275-prod-proposed-migration-environment-3@bos02-ppc64el-7.secgroup --name adt-noble-ppc64el-fpga-icestorm-20240327-080236-juju-7f2275-prod-proposed-migration-environment-3-77f572f6-6365-49d3-aa4f-a43bea3f2994 --image adt/ubuntu-noble-ppc64el-server --keyname testbed-juju-7f2275-prod-proposed-migration-environment-3 --net-id=net_prod-proposed-migration -e TERM=linux -e ''"'"'http_proxy=http://squid.internal:3128'"'"'' -e ''"'"'https_proxy=http://squid.internal:3128'"'"'' -e ''"'"'no_proxy=127.0.0.1,127.0.1.1,login.ubuntu.com,localhost,localdomain,novalocal,internal,archive.ubuntu.com,ports.ubuntu.com,security.ubuntu.com,ddebs.ubuntu.com,changelogs.ubuntu.com,launchpadlibrarian.net,launchpadcontent.net,launchpad.net,10.24.0.0/24,keystone.ps5.canonical.com,objectstorage.prodstack5.canonical.com'"'"'' --mirror=http://ftpmaster.internal/ubuntu/
104s autopkgtest [08:04:20]: testbed dpkg architecture: ppc64el
104s autopkgtest [08:04:20]: testbed apt version: 2.7.12
104s autopkgtest [08:04:20]: @@@@@@@@@@@@@@@@@@@@ test bed setup
105s Get:1 http://ftpmaster.internal/ubuntu noble-proposed InRelease [117 kB]
106s Get:2 http://ftpmaster.internal/ubuntu noble-proposed/multiverse Sources [55.4 kB]
106s Get:3 http://ftpmaster.internal/ubuntu noble-proposed/universe Sources [3964 kB]
107s Get:4 http://ftpmaster.internal/ubuntu noble-proposed/restricted Sources [8504 B]
107s Get:5 http://ftpmaster.internal/ubuntu noble-proposed/main Sources [497 kB]
107s Get:6 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el Packages [702 kB]
107s Get:7 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el c-n-f Metadata [3116 B]
107s Get:8 http://ftpmaster.internal/ubuntu noble-proposed/restricted ppc64el Packages [1372 B]
107s Get:9 http://ftpmaster.internal/ubuntu noble-proposed/restricted ppc64el c-n-f Metadata [116 B]
107s Get:10 http://ftpmaster.internal/ubuntu noble-proposed/universe ppc64el Packages [4217 kB]
108s Get:11 http://ftpmaster.internal/ubuntu noble-proposed/universe ppc64el c-n-f Metadata [8652 B]
108s Get:12 http://ftpmaster.internal/ubuntu noble-proposed/multiverse ppc64el Packages [62.2 kB]
109s Get:13 http://ftpmaster.internal/ubuntu noble-proposed/multiverse ppc64el c-n-f Metadata [116 B]
111s Fetched 9637 kB in 4s (2343 kB/s)
111s Reading package lists...
113s Reading package lists...
113s Building dependency tree...
113s Reading state information...
115s Calculating upgrade...Hit:1 http://ftpmaster.internal/ubuntu noble-proposed InRelease
115s Hit:2 http://ftpmaster.internal/ubuntu noble InRelease
115s Hit:3 http://ftpmaster.internal/ubuntu noble-updates InRelease
115s Hit:4 http://ftpmaster.internal/ubuntu noble-security InRelease
115s Reading package lists...
115s 0 upgraded, 0 newly installed, 0 to remove and 0 not upgraded.
115s Reading package lists...
115s Building dependency tree...
115s Reading state information...
115s 0 upgraded, 0 newly installed, 0 to remove and 248 not upgraded.
116s 
116s Reading package lists...
116s Building dependency tree...
116s Reading state information...
116s Calculating upgrade...
116s The following packages were automatically installed and are no longer required:
116s   libaio1 libnetplan0 python3-distutils python3-lib2to3
116s Use 'sudo apt autoremove' to remove them.
116s The following packages will be REMOVED:
116s   libapt-pkg6.0 libarchive13 libatm1 libcurl3-gnutls libcurl4 libdb5.3 libelf1
116s   libext2fs2 libgdbm-compat4 libgdbm6 libglib2.0-0 libgnutls30 libgpgme11
116s   libhogweed6 libmagic1 libnettle8 libnpth0 libnvme1 libparted2 libperl5.38
116s   libpng16-16 libpsl5 libreadline8 libreiserfscore0 libssl3 libtirpc3 liburcu8
116s   libuv1
116s The following NEW packages will be installed:
116s   bpfcc-tools bpftrace fontconfig-config fonts-dejavu-core fonts-dejavu-mono
116s   ieee-data libaio1t64 libapt-pkg6.0t64 libarchive13t64 libatm1t64 libbpfcc
116s   libc-dev-bin libc-devtools libc6-dev libclang-cpp18 libclang1-18
116s   libcrypt-dev libcurl3t64-gnutls libcurl4t64 libdb5.3t64 libdeflate0
116s   libdw1t64 libelf1t64 libext2fs2t64 libfontconfig1 libgd3 libgdbm-compat4t64
116s   libgdbm6t64 libglib2.0-0t64 libgnutls30t64 libgpgme11t64 libhogweed6t64
116s   libjbig0 libjpeg-turbo8 libjpeg8 liblerc4 libllvm18 libmagic1t64 libnetplan1
116s   libnettle8t64 libnpth0t64 libnvme1t64 libparted2t64 libperl5.38t64
116s   libpng16-16t64 libpsl5t64 libreadline8t64 libreiserfscore0t64 libsharpyuv0
116s   libssl3t64 libtiff6 libtirpc3t64 libunwind8 liburcu8t64 libuv1t64 libwebp7
116s   libxpm4 linux-headers-6.8.0-20 linux-headers-6.8.0-20-generic
116s   linux-image-6.8.0-20-generic linux-libc-dev linux-modules-6.8.0-20-generic
116s   linux-modules-extra-6.8.0-20-generic linux-tools-6.8.0-20
116s   linux-tools-6.8.0-20-generic linux-tools-common manpages manpages-dev
116s   python3-bpfcc python3-netaddr rpcsvc-proto ubuntu-kernel-accessories
116s   xdg-user-dirs
116s The following packages will be upgraded:
116s   apparmor apt apt-utils base-files bash bc bind9-dnsutils bind9-host
116s   bind9-libs binutils binutils-common binutils-powerpc64le-linux-gnu bolt
116s   bsdextrautils bsdutils btrfs-progs coreutils cryptsetup-bin curl dbus
117s   dbus-bin dbus-daemon dbus-session-bus-common dbus-system-bus-common
117s   dbus-user-session dhcpcd-base dirmngr dmsetup dpkg dpkg-dev e2fsprogs
117s   e2fsprogs-l10n eject fdisk file ftp fwupd gawk gcc-13-base gcc-14-base
117s   gir1.2-girepository-2.0 gir1.2-glib-2.0 gnupg gnupg-l10n gnupg-utils gpg
117s   gpg-agent gpg-wks-client gpgconf gpgsm gpgv groff-base grub-common
117s   grub-ieee1275 grub-ieee1275-bin grub2-common ibverbs-providers
117s   inetutils-telnet info initramfs-tools initramfs-tools-bin
117s   initramfs-tools-core install-info iproute2 jq keyboxd kmod kpartx
117s   krb5-locales libapparmor1 libaudit-common libaudit1 libbinutils libblkid1
117s   libblockdev-crypto3 libblockdev-fs3 libblockdev-loop3 libblockdev-mdraid3
117s   libblockdev-nvme3 libblockdev-part3 libblockdev-swap3 libblockdev-utils3
117s   libblockdev3 libbpf1 libbrotli1 libcap-ng0 libcom-err2 libcryptsetup12
117s   libctf-nobfd0 libctf0 libdbus-1-3 libdebconfclient0 libdevmapper1.02.1
117s   libdpkg-perl libevent-core-2.1-7 libexpat1 libfdisk1 libfido2-1 libfreetype6
117s   libftdi1-2 libfwupd2 libgcc-s1 libgirepository-1.0-1 libglib2.0-data
117s   libgssapi-krb5-2 libgudev-1.0-0 libgusb2 libibverbs1 libjcat1 libjq1
117s   libjson-glib-1.0-0 libjson-glib-1.0-common libk5crypto3 libkmod2 libkrb5-3
117s   libkrb5support0 libldap-common libldap2 liblocale-gettext-perl liblzma5
117s   libmagic-mgc libmbim-glib4 libmbim-proxy libmm-glib0 libmount1 libnghttp2-14
117s   libnsl2 libnss-systemd libpam-modules libpam-modules-bin libpam-runtime
117s   libpam-systemd libpam0g libplymouth5 libpolkit-agent-1-0
117s   libpolkit-gobject-1-0 libproc2-0 libprotobuf-c1 libpython3-stdlib
117s   libpython3.11-minimal libpython3.11-stdlib libpython3.12-minimal
117s   libpython3.12-stdlib libqmi-glib5 libqmi-proxy libqrtr-glib0 librtmp1
117s   libsasl2-2 libsasl2-modules libsasl2-modules-db libseccomp2 libselinux1
117s   libsemanage-common libsemanage2 libsframe1 libslang2 libsmartcols1
117s   libsqlite3-0 libss2 libssh-4 libstdc++6 libsystemd-shared libsystemd0
117s   libtext-charwidth-perl libtext-iconv-perl libtirpc-common libudev1
117s   libudisks2-0 libusb-1.0-0 libuuid1 libvolume-key1 libxml2 libxmlb2 libxmuu1
117s   linux-generic linux-headers-generic linux-headers-virtual
117s   linux-image-generic linux-image-virtual linux-virtual logsave lshw lsof
117s   man-db motd-news-config mount mtr-tiny multipath-tools netplan-generator
117s   netplan.io openssh-client openssh-server openssh-sftp-server openssl parted
117s   perl perl-base perl-modules-5.38 pinentry-curses plymouth
117s   plymouth-theme-ubuntu-text procps python-apt-common python3 python3-apt
117s   python3-cryptography python3-dbus python3-distutils python3-gdbm python3-gi
117s   python3-lib2to3 python3-minimal python3-netplan python3-pkg-resources
117s   python3-pyrsistent python3-setuptools python3-typing-extensions python3-yaml
117s   python3.11 python3.11-minimal python3.12 python3.12-minimal readline-common
117s   rsync rsyslog shared-mime-info sudo systemd systemd-dev systemd-resolved
117s   systemd-sysv systemd-timesyncd tcpdump telnet tnftp ubuntu-pro-client
117s   ubuntu-pro-client-l10n udev udisks2 usb.ids util-linux uuid-runtime
117s   vim-common vim-tiny wget xxd xz-utils zlib1g
117s 248 upgraded, 73 newly installed, 28 to remove and 0 not upgraded.
117s Need to get 390 MB of archives.
117s After this operation, 640 MB of additional disk space will be used.
117s Get:1 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el motd-news-config all 13ubuntu8 [5098 B]
117s Get:2 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el base-files ppc64el 13ubuntu8 [74.5 kB]
117s Get:3 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el bash ppc64el 5.2.21-2ubuntu3 [977 kB]
118s Get:4 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el bsdutils ppc64el 1:2.39.3-9ubuntu2 [98.3 kB]
118s Get:5 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el coreutils ppc64el 9.4-3ubuntu3 [1523 kB]
118s Get:6 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libudisks2-0 ppc64el 2.10.1-6 [182 kB]
118s Get:7 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el udisks2 ppc64el 2.10.1-6 [344 kB]
118s Get:8 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el shared-mime-info ppc64el 2.4-1build1 [481 kB]
119s Get:9 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el gir1.2-girepository-2.0 ppc64el 1.79.1-1ubuntu6 [24.8 kB]
119s Get:10 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el gir1.2-glib-2.0 ppc64el 2.79.3-3ubuntu5 [182 kB]
119s Get:11 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libgirepository-1.0-1 ppc64el 1.79.1-1ubuntu6 [93.8 kB]
119s Get:12 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el python3-gi ppc64el 3.47.0-3build1 [261 kB]
119s Get:13 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el python3-dbus ppc64el 1.3.2-5build2 [107 kB]
119s Get:14 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libnetplan1 ppc64el 1.0-1 [136 kB]
119s Get:15 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el python3-netplan ppc64el 1.0-1 [21.8 kB]
119s Get:16 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el netplan-generator ppc64el 1.0-1 [59.2 kB]
119s Get:17 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el initramfs-tools-bin ppc64el 0.142ubuntu23 [21.0 kB]
119s Get:18 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el initramfs-tools-core all 0.142ubuntu23 [50.1 kB]
119s Get:19 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el initramfs-tools all 0.142ubuntu23 [9058 B]
119s Get:20 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el netplan.io ppc64el 1.0-1 [66.2 kB]
119s Get:21 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libxmlb2 ppc64el 0.3.15-1build1 [82.6 kB]
119s Get:22 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libgpgme11t64 ppc64el 1.18.0-4.1ubuntu3 [173 kB]
119s Get:23 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libvolume-key1 ppc64el 0.3.12-7build1 [47.9 kB]
119s Get:24 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libqrtr-glib0 ppc64el 1.2.2-1ubuntu3 [18.3 kB]
119s Get:25 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libqmi-glib5 ppc64el 1.35.2-0ubuntu1 [966 kB]
119s Get:26 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libqmi-proxy ppc64el 1.35.2-0ubuntu1 [6208 B]
119s Get:27 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libpolkit-agent-1-0 ppc64el 124-1ubuntu1 [18.8 kB]
119s Get:28 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libpolkit-gobject-1-0 ppc64el 124-1ubuntu1 [52.7 kB]
119s Get:29 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libmm-glib0 ppc64el 1.23.4-0ubuntu1 [282 kB]
119s Get:30 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libmbim-glib4 ppc64el 1.31.2-0ubuntu2 [253 kB]
119s Get:31 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libmbim-proxy ppc64el 1.31.2-0ubuntu2 [6274 B]
119s Get:32 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libjson-glib-1.0-common all 1.8.0-2build1 [4210 B]
119s Get:33 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libjson-glib-1.0-0 ppc64el 1.8.0-2build1 [73.6 kB]
120s Get:34 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libgusb2 ppc64el 0.4.8-1build1 [43.0 kB]
120s Get:35 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libgudev-1.0-0 ppc64el 1:238-3ubuntu2 [15.8 kB]
120s Get:36 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el tnftp ppc64el 20230507-2build1 [116 kB]
120s Get:37 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el tcpdump ppc64el 4.99.4-3ubuntu2 [543 kB]
120s Get:38 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libsystemd0 ppc64el 255.4-1ubuntu5 [526 kB]
120s Get:39 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el systemd-dev all 255.4-1ubuntu5 [103 kB]
120s Get:40 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libnss-systemd ppc64el 255.4-1ubuntu5 [208 kB]
120s Get:41 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libudev1 ppc64el 255.4-1ubuntu5 [200 kB]
120s Get:42 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libssl3t64 ppc64el 3.0.13-0ubuntu2 [2125 kB]
120s Get:43 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el systemd ppc64el 255.4-1ubuntu5 [3771 kB]
121s Get:44 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el udev ppc64el 255.4-1ubuntu5 [2038 kB]
122s Get:45 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el systemd-sysv ppc64el 255.4-1ubuntu5 [11.9 kB]
122s Get:46 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libpam-systemd ppc64el 255.4-1ubuntu5 [304 kB]
122s Get:47 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el systemd-timesyncd ppc64el 255.4-1ubuntu5 [37.9 kB]
122s Get:48 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libsystemd-shared ppc64el 255.4-1ubuntu5 [2351 kB]
123s Get:49 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el systemd-resolved ppc64el 255.4-1ubuntu5 [346 kB]
123s Get:50 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el sudo ppc64el 1.9.15p5-3ubuntu3 [1005 kB]
123s Get:51 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el rsync ppc64el 3.2.7-1build1 [487 kB]
124s Get:52 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el python3-cryptography ppc64el 41.0.7-4build2 [860 kB]
124s Get:53 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el openssl ppc64el 3.0.13-0ubuntu2 [1026 kB]
125s Get:54 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el openssh-sftp-server ppc64el 1:9.6p1-3ubuntu11 [43.7 kB]
125s Get:55 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el openssh-client ppc64el 1:9.6p1-3ubuntu11 [1112 kB]
125s Get:56 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el openssh-server ppc64el 1:9.6p1-3ubuntu11 [627 kB]
126s Get:57 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libssh-4 ppc64el 0.10.6-2build1 [234 kB]
126s Get:58 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libsasl2-modules ppc64el 2.1.28+dfsg1-5ubuntu1 [83.1 kB]
126s Get:59 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el python3.12 ppc64el 3.12.2-4build3 [645 kB]
126s Get:60 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el python3.12-minimal ppc64el 3.12.2-4build3 [2447 kB]
128s Get:61 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libpython3.12-minimal ppc64el 3.12.2-4build3 [836 kB]
129s Get:62 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el grub-ieee1275 ppc64el 2.12-1ubuntu5 [63.1 kB]
129s Get:63 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el grub2-common ppc64el 2.12-1ubuntu5 [752 kB]
129s Get:64 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el grub-common ppc64el 2.12-1ubuntu5 [2356 kB]
131s Get:65 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el grub-ieee1275-bin ppc64el 2.12-1ubuntu5 [687 kB]
131s Get:66 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libparted2t64 ppc64el 3.6-3.1build2 [184 kB]
131s Get:67 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el parted ppc64el 3.6-3.1build2 [58.9 kB]
131s Get:68 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el python3.11 ppc64el 3.11.8-1build4 [589 kB]
132s Get:69 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el python3.11-minimal ppc64el 3.11.8-1build4 [2292 kB]
133s Get:70 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libpython3.11-minimal ppc64el 3.11.8-1build4 [846 kB]
133s Get:71 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libpython3.11-stdlib ppc64el 3.11.8-1build4 [1977 kB]
134s Get:72 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el gnupg-utils ppc64el 2.4.4-2ubuntu15 [123 kB]
134s Get:73 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el gpg-agent ppc64el 2.4.4-2ubuntu15 [275 kB]
135s Get:74 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el gpg-wks-client ppc64el 2.4.4-2ubuntu15 [85.0 kB]
135s Get:75 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el gpg ppc64el 2.4.4-2ubuntu15 [706 kB]
135s Get:76 http://ftpmaster.internal/ubuntu noble/main ppc64el libnpth0t64 ppc64el 1.6-3.1 [8864 B]
135s Get:77 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el gpgv ppc64el 2.4.4-2ubuntu15 [198 kB]
135s Get:78 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el dirmngr ppc64el 2.4.4-2ubuntu15 [391 kB]
135s Get:79 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el gnupg all 2.4.4-2ubuntu15 [359 kB]
135s Get:80 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el keyboxd ppc64el 2.4.4-2ubuntu15 [94.3 kB]
136s Get:81 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el gpgconf ppc64el 2.4.4-2ubuntu15 [115 kB]
136s Get:82 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el gpgsm ppc64el 2.4.4-2ubuntu15 [292 kB]
136s Get:83 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libreadline8t64 ppc64el 8.2-4 [182 kB]
136s Get:84 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el gawk ppc64el 1:5.2.1-2build2 [528 kB]
136s Get:85 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el fdisk ppc64el 2.39.3-9ubuntu2 [132 kB]
136s Get:86 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el bc ppc64el 1.07.1-3ubuntu2 [93.2 kB]
136s Get:87 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libpython3.12-stdlib ppc64el 3.12.2-4build3 [2082 kB]
137s Get:88 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el perl-base ppc64el 5.38.2-3.2 [1916 kB]
138s Get:89 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el perl-modules-5.38 all 5.38.2-3.2 [3110 kB]
140s Get:90 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el python3-gdbm ppc64el 3.12.2-3ubuntu1.1 [19.8 kB]
140s Get:91 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el man-db ppc64el 2.12.0-3build4 [1274 kB]
141s Get:92 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libgdbm6t64 ppc64el 1.23-5.1 [41.9 kB]
141s Get:93 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libgdbm-compat4t64 ppc64el 1.23-5.1 [6972 B]
141s Get:94 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libperl5.38t64 ppc64el 5.38.2-3.2 [4957 kB]
143s Get:95 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el perl ppc64el 5.38.2-3.2 [231 kB]
143s Get:96 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libdb5.3t64 ppc64el 5.3.28+dfsg2-6 [875 kB]
143s Get:97 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libsasl2-modules-db ppc64el 2.1.28+dfsg1-5ubuntu1 [23.4 kB]
143s Get:98 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libsasl2-2 ppc64el 2.1.28+dfsg1-5ubuntu1 [68.0 kB]
143s Get:99 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libnvme1t64 ppc64el 1.8-3 [98.2 kB]
143s Get:100 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el wget ppc64el 1.21.4-1ubuntu2 [382 kB]
144s Get:101 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libcurl4t64 ppc64el 8.5.0-2ubuntu8 [428 kB]
144s Get:102 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el curl ppc64el 8.5.0-2ubuntu8 [234 kB]
144s Get:103 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libpsl5t64 ppc64el 0.21.2-1.1 [59.0 kB]
144s Get:104 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libarchive13t64 ppc64el 3.7.2-1.1ubuntu2 [518 kB]
145s Get:105 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el fwupd ppc64el 1.9.15-2 [4634 kB]
146s Get:106 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libcurl3t64-gnutls ppc64el 8.5.0-2ubuntu8 [419 kB]
147s Get:107 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libfwupd2 ppc64el 1.9.15-2 [136 kB]
147s Get:108 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libblockdev3 ppc64el 3.1.0-1build1 [55.2 kB]
147s Get:109 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libblockdev-utils3 ppc64el 3.1.0-1build1 [20.3 kB]
147s Get:110 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libblockdev-swap3 ppc64el 3.1.0-1build1 [8616 B]
147s Get:111 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libblockdev-part3 ppc64el 3.1.0-1build1 [17.5 kB]
147s Get:112 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libblockdev-nvme3 ppc64el 3.1.0-1build1 [20.1 kB]
147s Get:113 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libblockdev-mdraid3 ppc64el 3.1.0-1build1 [14.3 kB]
147s Get:114 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libblockdev-loop3 ppc64el 3.1.0-1build1 [7742 B]
147s Get:115 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el e2fsprogs-l10n all 1.47.0-2.4~exp1ubuntu2 [5996 B]
147s Get:116 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el logsave ppc64el 1.47.0-2.4~exp1ubuntu2 [22.9 kB]
147s Get:117 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libext2fs2t64 ppc64el 1.47.0-2.4~exp1ubuntu2 [270 kB]
147s Get:118 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el e2fsprogs ppc64el 1.47.0-2.4~exp1ubuntu2 [663 kB]
147s Get:119 http://ftpmaster.internal/ubuntu noble/main ppc64el libreiserfscore0t64 ppc64el 1:3.6.27-7.1 [92.7 kB]
147s Get:120 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el btrfs-progs ppc64el 6.6.3-1.1build1 [1352 kB]
147s Get:121 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libblockdev-fs3 ppc64el 3.1.0-1build1 [41.2 kB]
147s Get:122 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libblockdev-crypto3 ppc64el 3.1.0-1build1 [22.5 kB]
147s Get:123 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el bolt ppc64el 0.9.6-2build1 [171 kB]
147s Get:124 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libglib2.0-0t64 ppc64el 2.79.3-3ubuntu5 [1773 kB]
148s Get:125 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libjcat1 ppc64el 0.2.0-2build2 [40.0 kB]
148s Get:126 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libldap2 ppc64el 2.6.7+dfsg-1~exp1ubuntu6 [233 kB]
148s Get:127 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el ubuntu-pro-client-l10n ppc64el 31.2.2 [19.4 kB]
148s Get:128 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el ubuntu-pro-client ppc64el 31.2.2 [215 kB]
148s Get:129 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el python3-apt ppc64el 2.7.7 [181 kB]
148s Get:130 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el apt-utils ppc64el 2.7.14 [226 kB]
148s Get:131 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libapt-pkg6.0t64 ppc64el 2.7.14 [1063 kB]
148s Get:132 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libnettle8t64 ppc64el 3.9.1-2.2 [226 kB]
148s Get:133 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libhogweed6t64 ppc64el 3.9.1-2.2 [208 kB]
148s Get:134 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libgnutls30t64 ppc64el 3.8.3-1.1ubuntu2 [1154 kB]
148s Get:135 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el apt ppc64el 2.7.14 [1401 kB]
148s Get:136 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el librtmp1 ppc64el 2.4+20151223.gitfa8646d.1-2build6 [64.4 kB]
148s Get:137 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el liblzma5 ppc64el 5.6.0-0.2 [156 kB]
148s Get:138 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libblkid1 ppc64el 2.39.3-9ubuntu2 [155 kB]
148s Get:139 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el kmod ppc64el 31+20240202-2ubuntu4 [122 kB]
148s Get:140 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libkmod2 ppc64el 31+20240202-2ubuntu4 [64.4 kB]
148s Get:141 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libselinux1 ppc64el 3.5-2ubuntu1 [101 kB]
148s Get:142 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libaudit-common all 1:3.1.2-2.1 [5674 B]
148s Get:143 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libcap-ng0 ppc64el 0.8.4-2build1 [16.2 kB]
148s Get:144 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libaudit1 ppc64el 1:3.1.2-2.1 [52.8 kB]
148s Get:145 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libpam0g ppc64el 1.5.3-5ubuntu3 [75.7 kB]
148s Get:146 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libpam-modules-bin ppc64el 1.5.3-5ubuntu3 [57.9 kB]
148s Get:147 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libpam-modules ppc64el 1.5.3-5ubuntu3 [320 kB]
148s Get:148 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libpam-runtime all 1.5.3-5ubuntu3 [40.8 kB]
148s Get:149 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el dbus-session-bus-common all 1.14.10-4ubuntu2 [80.3 kB]
148s Get:150 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el dbus-user-session ppc64el 1.14.10-4ubuntu2 [9960 B]
148s Get:151 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libapparmor1 ppc64el 4.0.0-beta3-0ubuntu2 [55.0 kB]
148s Get:152 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libexpat1 ppc64el 2.6.1-2 [101 kB]
148s Get:153 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el dbus-system-bus-common all 1.14.10-4ubuntu2 [81.5 kB]
148s Get:154 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el dbus-bin ppc64el 1.14.10-4ubuntu2 [48.1 kB]
148s Get:155 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el dbus ppc64el 1.14.10-4ubuntu2 [26.9 kB]
148s Get:156 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el dbus-daemon ppc64el 1.14.10-4ubuntu2 [136 kB]
148s Get:157 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libdbus-1-3 ppc64el 1.14.10-4ubuntu2 [244 kB]
148s Get:158 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libdevmapper1.02.1 ppc64el 2:1.02.185-3ubuntu2 [182 kB]
148s Get:159 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libuuid1 ppc64el 2.39.3-9ubuntu2 [39.3 kB]
148s Get:160 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libcryptsetup12 ppc64el 2:2.7.0-1ubuntu2 [376 kB]
148s Get:161 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libfdisk1 ppc64el 2.39.3-9ubuntu2 [171 kB]
148s Get:162 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libseccomp2 ppc64el 2.5.5-1ubuntu2 [62.5 kB]
148s Get:163 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el mount ppc64el 2.39.3-9ubuntu2 [125 kB]
148s Get:164 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libmount1 ppc64el 2.39.3-9ubuntu2 [169 kB]
148s Get:165 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el zlib1g ppc64el 1:1.3.dfsg-3.1ubuntu1 [72.8 kB]
148s Get:166 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el python3-minimal ppc64el 3.12.2-0ubuntu1 [27.1 kB]
148s Get:167 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el python3 ppc64el 3.12.2-0ubuntu1 [24.1 kB]
148s Get:168 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libplymouth5 ppc64el 24.004.60-1ubuntu6 [166 kB]
149s Get:169 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libpng16-16t64 ppc64el 1.6.43-3 [242 kB]
149s Get:170 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libbrotli1 ppc64el 1.1.0-2build1 [410 kB]
149s Get:171 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libfreetype6 ppc64el 2.13.2+dfsg-1build2 [545 kB]
149s Get:172 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libsqlite3-0 ppc64el 3.45.1-1ubuntu1 [804 kB]
149s Get:173 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el pinentry-curses ppc64el 1.2.1-3ubuntu4 [38.7 kB]
149s Get:174 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el gcc-14-base ppc64el 14-20240315-1ubuntu1 [47.0 kB]
149s Get:175 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libgcc-s1 ppc64el 14-20240315-1ubuntu1 [39.2 kB]
149s Get:176 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libstdc++6 ppc64el 14-20240315-1ubuntu1 [897 kB]
149s Get:177 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el python-apt-common all 2.7.7 [19.8 kB]
149s Get:178 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libsmartcols1 ppc64el 2.39.3-9ubuntu2 [79.0 kB]
149s Get:179 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el readline-common all 8.2-4 [56.4 kB]
149s Get:180 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el bsdextrautils ppc64el 2.39.3-9ubuntu2 [78.6 kB]
149s Get:181 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el groff-base ppc64el 1.23.0-3build1 [1112 kB]
149s Get:182 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libpython3-stdlib ppc64el 3.12.2-0ubuntu1 [9798 B]
149s Get:183 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libfido2-1 ppc64el 1.14.0-1build1 [111 kB]
149s Get:184 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libgssapi-krb5-2 ppc64el 1.20.1-6ubuntu1 [185 kB]
149s Get:185 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libkrb5-3 ppc64el 1.20.1-6ubuntu1 [432 kB]
149s Get:186 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libkrb5support0 ppc64el 1.20.1-6ubuntu1 [38.5 kB]
149s Get:187 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libk5crypto3 ppc64el 1.20.1-6ubuntu1 [108 kB]
149s Get:188 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libcom-err2 ppc64el 1.47.0-2.4~exp1ubuntu2 [22.9 kB]
149s Get:189 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libproc2-0 ppc64el 2:4.0.4-4ubuntu2 [68.8 kB]
149s Get:190 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el procps ppc64el 2:4.0.4-4ubuntu2 [736 kB]
149s Get:191 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libnghttp2-14 ppc64el 1.59.0-1build1 [89.0 kB]
149s Get:192 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el dpkg ppc64el 1.22.6ubuntu5 [1343 kB]
149s Get:193 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el util-linux ppc64el 2.39.3-9ubuntu2 [1195 kB]
149s Get:194 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libxml2 ppc64el 2.9.14+dfsg-1.3ubuntu2 [840 kB]
149s Get:195 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libbpf1 ppc64el 1:1.3.0-2build1 [216 kB]
149s Get:196 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el iproute2 ppc64el 6.1.0-1ubuntu5 [1384 kB]
149s Get:197 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libelf1t64 ppc64el 0.190-1.1build2 [69.3 kB]
149s Get:198 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el dhcpcd-base ppc64el 1:10.0.6-1ubuntu2 [276 kB]
149s Get:199 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el file ppc64el 1:5.45-3 [22.7 kB]
149s Get:200 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libmagic-mgc ppc64el 1:5.45-3 [307 kB]
149s Get:201 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libmagic1t64 ppc64el 1:5.45-3 [106 kB]
149s Get:202 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libtirpc-common all 1.3.4+ds-1.1 [8018 B]
149s Get:203 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el lsof ppc64el 4.95.0-1build2 [256 kB]
150s Get:204 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libnsl2 ppc64el 1.3.0-3build2 [48.9 kB]
150s Get:205 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libtirpc3t64 ppc64el 1.3.4+ds-1.1 [102 kB]
150s Get:206 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el multipath-tools ppc64el 0.9.4-5ubuntu6 [341 kB]
150s Get:207 http://ftpmaster.internal/ubuntu noble/main ppc64el liburcu8t64 ppc64el 0.14.0-3.1 [73.6 kB]
150s Get:208 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el bind9-host ppc64el 1:9.18.24-0ubuntu3 [54.5 kB]
150s Get:209 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el bind9-dnsutils ppc64el 1:9.18.24-0ubuntu3 [167 kB]
150s Get:210 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el bind9-libs ppc64el 1:9.18.24-0ubuntu3 [1436 kB]
150s Get:211 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libuv1t64 ppc64el 1.48.0-1.1 [117 kB]
150s Get:212 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el liblocale-gettext-perl ppc64el 1.07-6ubuntu4 [16.1 kB]
150s Get:213 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el uuid-runtime ppc64el 2.39.3-9ubuntu2 [33.8 kB]
150s Get:214 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libdebconfclient0 ppc64el 0.271ubuntu2 [11.2 kB]
150s Get:215 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libsemanage-common all 3.5-1build4 [10.1 kB]
150s Get:216 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libsemanage2 ppc64el 3.5-1build4 [115 kB]
150s Get:217 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el install-info ppc64el 7.1-3build1 [64.5 kB]
150s Get:218 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el gcc-13-base ppc64el 13.2.0-21ubuntu1 [48.3 kB]
150s Get:219 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libss2 ppc64el 1.47.0-2.4~exp1ubuntu2 [18.0 kB]
150s Get:220 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el dmsetup ppc64el 2:1.02.185-3ubuntu2 [91.8 kB]
150s Get:221 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el eject ppc64el 2.39.3-9ubuntu2 [28.2 kB]
150s Get:222 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el krb5-locales all 1.20.1-6ubuntu1 [13.8 kB]
150s Get:223 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libglib2.0-data all 2.79.3-3ubuntu5 [46.6 kB]
150s Get:224 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libslang2 ppc64el 2.3.3-3build1 [501 kB]
151s Get:225 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libtext-charwidth-perl ppc64el 0.04-11build2 [9506 B]
151s Get:226 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libtext-iconv-perl ppc64el 1.7-8build2 [13.7 kB]
151s Get:227 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el python3-yaml ppc64el 6.0.1-2build1 [123 kB]
151s Get:228 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el python3-setuptools all 68.1.2-2ubuntu1 [396 kB]
151s Get:229 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el python3-pkg-resources all 68.1.2-2ubuntu1 [168 kB]
151s Get:230 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el rsyslog ppc64el 8.2312.0-3ubuntu7 [629 kB]
151s Get:231 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el vim-tiny ppc64el 2:9.1.0016-1ubuntu6 [1042 kB]
151s Get:232 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el vim-common all 2:9.1.0016-1ubuntu6 [385 kB]
151s Get:233 http://ftpmaster.internal/ubuntu noble/main ppc64el xdg-user-dirs ppc64el 0.18-1 [20.0 kB]
151s Get:234 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el xxd ppc64el 2:9.1.0016-1ubuntu6 [63.7 kB]
151s Get:235 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el apparmor ppc64el 4.0.0-beta3-0ubuntu2 [747 kB]
151s Get:236 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el ftp all 20230507-2build1 [4724 B]
151s Get:237 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el inetutils-telnet ppc64el 2:2.5-3ubuntu3 [115 kB]
151s Get:238 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el info ppc64el 7.1-3build1 [188 kB]
151s Get:239 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libusb-1.0-0 ppc64el 2:1.0.27-1 [64.0 kB]
151s Get:240 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libxmuu1 ppc64el 2:1.1.3-3build1 [9488 B]
151s Get:241 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el lshw ppc64el 02.19.git.2021.06.19.996aaad9c7-2build2 [334 kB]
151s Get:242 http://ftpmaster.internal/ubuntu noble/main ppc64el manpages all 6.05.01-1 [1340 kB]
151s Get:243 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el mtr-tiny ppc64el 0.95-1.1build1 [62.8 kB]
151s Get:244 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el plymouth-theme-ubuntu-text ppc64el 24.004.60-1ubuntu6 [11.1 kB]
151s Get:245 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el plymouth ppc64el 24.004.60-1ubuntu6 [155 kB]
151s Get:246 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el telnet all 0.17+2.5-3ubuntu3 [3682 B]
151s Get:247 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el usb.ids all 2024.03.18-1 [223 kB]
151s Get:248 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el xz-utils ppc64el 5.6.0-0.2 [281 kB]
151s Get:249 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libctf0 ppc64el 2.42-4ubuntu1 [112 kB]
151s Get:250 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libctf-nobfd0 ppc64el 2.42-4ubuntu1 [112 kB]
151s Get:251 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el binutils-powerpc64le-linux-gnu ppc64el 2.42-4ubuntu1 [2473 kB]
152s Get:252 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libbinutils ppc64el 2.42-4ubuntu1 [699 kB]
152s Get:253 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el binutils ppc64el 2.42-4ubuntu1 [3078 B]
152s Get:254 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el binutils-common ppc64el 2.42-4ubuntu1 [217 kB]
152s Get:255 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libsframe1 ppc64el 2.42-4ubuntu1 [16.0 kB]
152s Get:256 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libllvm18 ppc64el 1:18.1.2-1ubuntu2 [28.9 MB]
155s Get:257 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libclang-cpp18 ppc64el 1:18.1.2-1ubuntu2 [14.6 MB]
156s Get:258 http://ftpmaster.internal/ubuntu noble-proposed/universe ppc64el libbpfcc ppc64el 0.29.1+ds-1ubuntu4 [707 kB]
156s Get:259 http://ftpmaster.internal/ubuntu noble-proposed/universe ppc64el python3-bpfcc all 0.29.1+ds-1ubuntu4 [40.2 kB]
156s Get:260 http://ftpmaster.internal/ubuntu noble/main ppc64el ieee-data all 20220827.1 [2113 kB]
157s Get:261 http://ftpmaster.internal/ubuntu noble/main ppc64el python3-netaddr all 0.8.0-2ubuntu1 [319 kB]
157s Get:262 http://ftpmaster.internal/ubuntu noble-proposed/universe ppc64el bpfcc-tools all 0.29.1+ds-1ubuntu4 [687 kB]
157s Get:263 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libclang1-18 ppc64el 1:18.1.2-1ubuntu2 [8725 kB]
157s Get:264 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libdw1t64 ppc64el 0.190-1.1build2 [301 kB]
158s Get:265 http://ftpmaster.internal/ubuntu noble-proposed/universe ppc64el bpftrace ppc64el 0.20.2-1ubuntu1 [1058 kB]
158s Get:266 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el cryptsetup-bin ppc64el 2:2.7.0-1ubuntu2 [227 kB]
158s Get:267 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el dpkg-dev all 1.22.6ubuntu5 [1074 kB]
158s Get:268 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libdpkg-perl all 1.22.6ubuntu5 [269 kB]
158s Get:269 http://ftpmaster.internal/ubuntu noble/main ppc64el fonts-dejavu-mono all 2.37-8 [502 kB]
158s Get:270 http://ftpmaster.internal/ubuntu noble/main ppc64el fonts-dejavu-core all 2.37-8 [835 kB]
158s Get:271 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el fontconfig-config ppc64el 2.15.0-1.1ubuntu1 [37.4 kB]
158s Get:272 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libprotobuf-c1 ppc64el 1.4.1-1ubuntu3 [25.9 kB]
158s Get:273 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el gnupg-l10n all 2.4.4-2ubuntu15 [65.8 kB]
158s Get:274 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libibverbs1 ppc64el 50.0-2build1 [74.4 kB]
158s Get:275 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el ibverbs-providers ppc64el 50.0-2build1 [420 kB]
158s Get:276 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el jq ppc64el 1.7.1-3 [66.1 kB]
158s Get:277 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libjq1 ppc64el 1.7.1-3 [173 kB]
158s Get:278 http://ftpmaster.internal/ubuntu noble/main ppc64el libaio1t64 ppc64el 0.3.113-6 [8188 B]
158s Get:279 http://ftpmaster.internal/ubuntu noble/main ppc64el libatm1t64 ppc64el 1:2.5.1-5.1 [26.9 kB]
158s Get:280 http://ftpmaster.internal/ubuntu noble/main ppc64el libc-dev-bin ppc64el 2.39-0ubuntu6 [21.3 kB]
158s Get:281 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libfontconfig1 ppc64el 2.15.0-1.1ubuntu1 [190 kB]
158s Get:282 http://ftpmaster.internal/ubuntu noble/main ppc64el libjpeg-turbo8 ppc64el 2.1.5-2ubuntu1 [212 kB]
158s Get:283 http://ftpmaster.internal/ubuntu noble/main ppc64el libjpeg8 ppc64el 8c-2ubuntu11 [2148 B]
158s Get:284 http://ftpmaster.internal/ubuntu noble/main ppc64el libdeflate0 ppc64el 1.19-1 [61.9 kB]
158s Get:285 http://ftpmaster.internal/ubuntu noble/main ppc64el libjbig0 ppc64el 2.1-6.1ubuntu1 [34.7 kB]
158s Get:286 http://ftpmaster.internal/ubuntu noble/main ppc64el liblerc4 ppc64el 4.0.0+ds-4ubuntu1 [266 kB]
158s Get:287 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libsharpyuv0 ppc64el 1.3.2-0.4build2 [28.8 kB]
158s Get:288 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libwebp7 ppc64el 1.3.2-0.4build2 [312 kB]
158s Get:289 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libtiff6 ppc64el 4.5.1+git230720-4ubuntu1 [274 kB]
158s Get:290 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libxpm4 ppc64el 1:3.5.17-1build1 [50.2 kB]
158s Get:291 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libgd3 ppc64el 2.3.3-9ubuntu3 [162 kB]
158s Get:292 http://ftpmaster.internal/ubuntu noble/main ppc64el libc-devtools ppc64el 2.39-0ubuntu6 [29.6 kB]
158s Get:293 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el linux-libc-dev ppc64el 6.8.0-20.20 [1586 kB]
158s Get:294 http://ftpmaster.internal/ubuntu noble/main ppc64el libcrypt-dev ppc64el 1:4.4.36-4 [167 kB]
158s Get:295 http://ftpmaster.internal/ubuntu noble/main ppc64el rpcsvc-proto ppc64el 1.4.2-0ubuntu6 [82.3 kB]
158s Get:296 http://ftpmaster.internal/ubuntu noble/main ppc64el libc6-dev ppc64el 2.39-0ubuntu6 [2102 kB]
159s Get:297 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libevent-core-2.1-7 ppc64el 2.1.12-stable-9build1 [110 kB]
159s Get:298 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libftdi1-2 ppc64el 1.5-6build4 [32.5 kB]
159s Get:299 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libldap-common all 2.6.7+dfsg-1~exp1ubuntu6 [31.3 kB]
159s Get:300 http://ftpmaster.internal/ubuntu noble/main ppc64el libunwind8 ppc64el 1.6.2-3 [59.9 kB]
159s Get:301 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el linux-modules-6.8.0-20-generic ppc64el 6.8.0-20.20 [31.3 MB]
162s Get:302 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el linux-image-6.8.0-20-generic ppc64el 6.8.0-20.20 [63.9 MB]
175s Get:303 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el linux-modules-extra-6.8.0-20-generic ppc64el 6.8.0-20.20 [103 MB]
235s Get:304 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el linux-generic ppc64el 6.8.0-20.20+1 [1734 B]
235s Get:305 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el linux-image-generic ppc64el 6.8.0-20.20+1 [9698 B]
235s Get:306 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el linux-virtual ppc64el 6.8.0-20.20+1 [1686 B]
235s Get:307 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el linux-image-virtual ppc64el 6.8.0-20.20+1 [9702 B]
235s Get:308 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el linux-headers-virtual ppc64el 6.8.0-20.20+1 [1648 B]
235s Get:309 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el linux-headers-6.8.0-20 all 6.8.0-20.20 [13.6 MB]
239s Get:310 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el linux-headers-6.8.0-20-generic ppc64el 6.8.0-20.20 [3728 kB]
239s Get:311 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el linux-headers-generic ppc64el 6.8.0-20.20+1 [9612 B]
239s Get:312 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el linux-tools-common all 6.8.0-20.20 [437 kB]
239s Get:313 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el linux-tools-6.8.0-20 ppc64el 6.8.0-20.20 [2924 kB]
240s Get:314 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el linux-tools-6.8.0-20-generic ppc64el 6.8.0-20.20 [1730 B]
240s Get:315 http://ftpmaster.internal/ubuntu noble/main ppc64el manpages-dev all 6.05.01-1 [2018 kB]
240s Get:316 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el python3-distutils all 3.12.2-3ubuntu1.1 [133 kB]
240s Get:317 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el python3-lib2to3 all 3.12.2-3ubuntu1.1 [79.1 kB]
240s Get:318 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el python3-pyrsistent ppc64el 0.20.0-1build1 [60.4 kB]
240s Get:319 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el python3-typing-extensions all 4.10.0-1 [60.7 kB]
240s Get:320 http://ftpmaster.internal/ubuntu noble/main ppc64el ubuntu-kernel-accessories ppc64el 1.536build1 [10.5 kB]
240s Get:321 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el kpartx ppc64el 0.9.4-5ubuntu6 [34.4 kB]
241s Preconfiguring packages ...
241s Fetched 390 MB in 2min 3s (3159 kB/s)
241s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70153 files and directories currently installed.)
241s Preparing to unpack .../motd-news-config_13ubuntu8_all.deb ...
241s Unpacking motd-news-config (13ubuntu8) over (13ubuntu7) ...
241s Preparing to unpack .../base-files_13ubuntu8_ppc64el.deb ...
241s Unpacking base-files (13ubuntu8) over (13ubuntu7) ...
241s Setting up base-files (13ubuntu8) ...
242s motd-news.service is a disabled or a static unit not running, not starting it.
242s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70153 files and directories currently installed.)
242s Preparing to unpack .../bash_5.2.21-2ubuntu3_ppc64el.deb ...
242s Unpacking bash (5.2.21-2ubuntu3) over (5.2.21-2ubuntu2) ...
242s Setting up bash (5.2.21-2ubuntu3) ...
242s update-alternatives: using /usr/share/man/man7/bash-builtins.7.gz to provide /usr/share/man/man7/builtins.7.gz (builtins.7.gz) in auto mode
242s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70153 files and directories currently installed.)
242s Preparing to unpack .../bsdutils_1%3a2.39.3-9ubuntu2_ppc64el.deb ...
242s Unpacking bsdutils (1:2.39.3-9ubuntu2) over (1:2.39.3-6ubuntu2) ...
242s Setting up bsdutils (1:2.39.3-9ubuntu2) ...
242s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70153 files and directories currently installed.)
242s Preparing to unpack .../coreutils_9.4-3ubuntu3_ppc64el.deb ...
242s Unpacking coreutils (9.4-3ubuntu3) over (9.4-2ubuntu4) ...
242s Setting up coreutils (9.4-3ubuntu3) ...
242s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70153 files and directories currently installed.)
242s Preparing to unpack .../00-libudisks2-0_2.10.1-6_ppc64el.deb ...
242s Unpacking libudisks2-0:ppc64el (2.10.1-6) over (2.10.1-1ubuntu2) ...
242s Preparing to unpack .../01-udisks2_2.10.1-6_ppc64el.deb ...
242s Unpacking udisks2 (2.10.1-6) over (2.10.1-1ubuntu2) ...
242s Preparing to unpack .../02-shared-mime-info_2.4-1build1_ppc64el.deb ...
242s Unpacking shared-mime-info (2.4-1build1) over (2.4-1) ...
242s Preparing to unpack .../03-gir1.2-girepository-2.0_1.79.1-1ubuntu6_ppc64el.deb ...
242s Unpacking gir1.2-girepository-2.0:ppc64el (1.79.1-1ubuntu6) over (1.79.1-1) ...
242s Preparing to unpack .../04-gir1.2-glib-2.0_2.79.3-3ubuntu5_ppc64el.deb ...
242s Unpacking gir1.2-glib-2.0:ppc64el (2.79.3-3ubuntu5) over (2.79.2-1~ubuntu1) ...
242s Preparing to unpack .../05-libgirepository-1.0-1_1.79.1-1ubuntu6_ppc64el.deb ...
242s Unpacking libgirepository-1.0-1:ppc64el (1.79.1-1ubuntu6) over (1.79.1-1) ...
242s Preparing to unpack .../06-python3-gi_3.47.0-3build1_ppc64el.deb ...
242s Unpacking python3-gi (3.47.0-3build1) over (3.47.0-3) ...
242s Preparing to unpack .../07-python3-dbus_1.3.2-5build2_ppc64el.deb ...
243s Unpacking python3-dbus (1.3.2-5build2) over (1.3.2-5build1) ...
243s Selecting previously unselected package libnetplan1:ppc64el.
243s Preparing to unpack .../08-libnetplan1_1.0-1_ppc64el.deb ...
243s Unpacking libnetplan1:ppc64el (1.0-1) ...
243s Preparing to unpack .../09-python3-netplan_1.0-1_ppc64el.deb ...
243s Unpacking python3-netplan (1.0-1) over (0.107.1-3) ...
243s Preparing to unpack .../10-netplan-generator_1.0-1_ppc64el.deb ...
243s Adding 'diversion of /lib/systemd/system-generators/netplan to /lib/systemd/system-generators/netplan.usr-is-merged by netplan-generator'
243s Unpacking netplan-generator (1.0-1) over (0.107.1-3) ...
243s Preparing to unpack .../11-initramfs-tools-bin_0.142ubuntu23_ppc64el.deb ...
243s Unpacking initramfs-tools-bin (0.142ubuntu23) over (0.142ubuntu20) ...
243s Preparing to unpack .../12-initramfs-tools-core_0.142ubuntu23_all.deb ...
243s Unpacking initramfs-tools-core (0.142ubuntu23) over (0.142ubuntu20) ...
243s Preparing to unpack .../13-initramfs-tools_0.142ubuntu23_all.deb ...
243s Unpacking initramfs-tools (0.142ubuntu23) over (0.142ubuntu20) ...
243s Preparing to unpack .../14-netplan.io_1.0-1_ppc64el.deb ...
243s Unpacking netplan.io (1.0-1) over (0.107.1-3) ...
243s Preparing to unpack .../15-libxmlb2_0.3.15-1build1_ppc64el.deb ...
243s Unpacking libxmlb2:ppc64el (0.3.15-1build1) over (0.3.15-1) ...
243s dpkg: libgpgme11:ppc64el: dependency problems, but removing anyway as you requested:
243s  libvolume-key1:ppc64el depends on libgpgme11 (>= 1.4.1).
243s  libjcat1:ppc64el depends on libgpgme11 (>= 1.2.0).
243s 
243s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70157 files and directories currently installed.)
243s Removing libgpgme11:ppc64el (1.18.0-4ubuntu1) ...
243s Selecting previously unselected package libgpgme11t64:ppc64el.
243s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70151 files and directories currently installed.)
243s Preparing to unpack .../00-libgpgme11t64_1.18.0-4.1ubuntu3_ppc64el.deb ...
243s Unpacking libgpgme11t64:ppc64el (1.18.0-4.1ubuntu3) ...
243s Preparing to unpack .../01-libvolume-key1_0.3.12-7build1_ppc64el.deb ...
243s Unpacking libvolume-key1:ppc64el (0.3.12-7build1) over (0.3.12-5build2) ...
243s Preparing to unpack .../02-libqrtr-glib0_1.2.2-1ubuntu3_ppc64el.deb ...
243s Unpacking libqrtr-glib0:ppc64el (1.2.2-1ubuntu3) over (1.2.2-1ubuntu2) ...
243s Preparing to unpack .../03-libqmi-glib5_1.35.2-0ubuntu1_ppc64el.deb ...
243s Unpacking libqmi-glib5:ppc64el (1.35.2-0ubuntu1) over (1.34.0-2) ...
243s Preparing to unpack .../04-libqmi-proxy_1.35.2-0ubuntu1_ppc64el.deb ...
243s Unpacking libqmi-proxy (1.35.2-0ubuntu1) over (1.34.0-2) ...
243s Preparing to unpack .../05-libpolkit-agent-1-0_124-1ubuntu1_ppc64el.deb ...
243s Unpacking libpolkit-agent-1-0:ppc64el (124-1ubuntu1) over (124-1) ...
243s Preparing to unpack .../06-libpolkit-gobject-1-0_124-1ubuntu1_ppc64el.deb ...
243s Unpacking libpolkit-gobject-1-0:ppc64el (124-1ubuntu1) over (124-1) ...
243s Preparing to unpack .../07-libmm-glib0_1.23.4-0ubuntu1_ppc64el.deb ...
243s Unpacking libmm-glib0:ppc64el (1.23.4-0ubuntu1) over (1.22.0-3) ...
243s Preparing to unpack .../08-libmbim-glib4_1.31.2-0ubuntu2_ppc64el.deb ...
243s Unpacking libmbim-glib4:ppc64el (1.31.2-0ubuntu2) over (1.30.0-1) ...
243s Preparing to unpack .../09-libmbim-proxy_1.31.2-0ubuntu2_ppc64el.deb ...
243s Unpacking libmbim-proxy (1.31.2-0ubuntu2) over (1.30.0-1) ...
243s Preparing to unpack .../10-libjson-glib-1.0-common_1.8.0-2build1_all.deb ...
243s Unpacking libjson-glib-1.0-common (1.8.0-2build1) over (1.8.0-2) ...
243s Preparing to unpack .../11-libjson-glib-1.0-0_1.8.0-2build1_ppc64el.deb ...
243s Unpacking libjson-glib-1.0-0:ppc64el (1.8.0-2build1) over (1.8.0-2) ...
243s Preparing to unpack .../12-libgusb2_0.4.8-1build1_ppc64el.deb ...
243s Unpacking libgusb2:ppc64el (0.4.8-1build1) over (0.4.8-1) ...
243s Preparing to unpack .../13-libgudev-1.0-0_1%3a238-3ubuntu2_ppc64el.deb ...
243s Unpacking libgudev-1.0-0:ppc64el (1:238-3ubuntu2) over (1:238-3) ...
243s Preparing to unpack .../14-tnftp_20230507-2build1_ppc64el.deb ...
243s Unpacking tnftp (20230507-2build1) over (20230507-2) ...
243s Preparing to unpack .../15-tcpdump_4.99.4-3ubuntu2_ppc64el.deb ...
243s Unpacking tcpdump (4.99.4-3ubuntu2) over (4.99.4-3ubuntu1) ...
243s Preparing to unpack .../16-libsystemd0_255.4-1ubuntu5_ppc64el.deb ...
243s Unpacking libsystemd0:ppc64el (255.4-1ubuntu5) over (255.2-3ubuntu2) ...
243s Setting up libsystemd0:ppc64el (255.4-1ubuntu5) ...
243s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70158 files and directories currently installed.)
243s Preparing to unpack .../systemd-dev_255.4-1ubuntu5_all.deb ...
243s Unpacking systemd-dev (255.4-1ubuntu5) over (255.2-3ubuntu2) ...
243s Preparing to unpack .../libnss-systemd_255.4-1ubuntu5_ppc64el.deb ...
243s Unpacking libnss-systemd:ppc64el (255.4-1ubuntu5) over (255.2-3ubuntu2) ...
243s Preparing to unpack .../libudev1_255.4-1ubuntu5_ppc64el.deb ...
243s Unpacking libudev1:ppc64el (255.4-1ubuntu5) over (255.2-3ubuntu2) ...
243s Setting up libudev1:ppc64el (255.4-1ubuntu5) ...
243s dpkg: libssl3:ppc64el: dependency problems, but removing anyway as you requested:
243s  wget depends on libssl3 (>= 3.0.0).
243s  systemd-resolved depends on libssl3 (>= 3.0.0).
243s  systemd depends on libssl3 (>= 3.0.0).
243s  sudo depends on libssl3 (>= 3.0.0).
243s  rsync depends on libssl3 (>= 3.0.0).
243s  python3-cryptography depends on libssl3 (>= 3.0.0).
243s  openssl depends on libssl3 (>= 3.0.9).
243s  openssh-server depends on libssl3 (>= 3.0.10).
243s  openssh-client depends on libssl3 (>= 3.0.10).
243s  linux-headers-6.8.0-11-generic depends on libssl3 (>= 3.0.0).
243s  libsystemd-shared:ppc64el depends on libssl3 (>= 3.0.0).
243s  libssh-4:ppc64el depends on libssl3 (>= 3.0.0).
243s  libsasl2-modules:ppc64el depends on libssl3 (>= 3.0.0).
243s  libsasl2-2:ppc64el depends on libssl3 (>= 3.0.0).
243s  libpython3.12-minimal:ppc64el depends on libssl3 (>= 3.0.0).
243s  libpython3.11-minimal:ppc64el depends on libssl3 (>= 3.0.0).
243s  libnvme1 depends on libssl3 (>= 3.0.0).
243s  libkrb5-3:ppc64el depends on libssl3 (>= 3.0.0).
243s  libkmod2:ppc64el depends on libssl3 (>= 3.0.0).
243s  libfido2-1:ppc64el depends on libssl3 (>= 3.0.0).
243s  libcurl4:ppc64el depends on libssl3 (>= 3.0.0).
243s  libcryptsetup12:ppc64el depends on libssl3 (>= 3.0.0).
243s  kmod depends on libssl3 (>= 3.0.0).
243s  dhcpcd-base depends on libssl3 (>= 3.0.0).
243s  coreutils depends on libssl3 (>= 3.0.0).
243s  bind9-libs:ppc64el depends on libssl3 (>= 3.0.0).
243s 
243s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70158 files and directories currently installed.)
243s Removing libssl3:ppc64el (3.0.10-1ubuntu4) ...
243s Selecting previously unselected package libssl3t64:ppc64el.
243s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70147 files and directories currently installed.)
243s Preparing to unpack .../libssl3t64_3.0.13-0ubuntu2_ppc64el.deb ...
243s Unpacking libssl3t64:ppc64el (3.0.13-0ubuntu2) ...
244s Setting up libssl3t64:ppc64el (3.0.13-0ubuntu2) ...
244s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70160 files and directories currently installed.)
244s Preparing to unpack .../systemd_255.4-1ubuntu5_ppc64el.deb ...
244s Unpacking systemd (255.4-1ubuntu5) over (255.2-3ubuntu2) ...
244s Preparing to unpack .../udev_255.4-1ubuntu5_ppc64el.deb ...
244s Unpacking udev (255.4-1ubuntu5) over (255.2-3ubuntu2) ...
244s Preparing to unpack .../libsystemd-shared_255.4-1ubuntu5_ppc64el.deb ...
244s Unpacking libsystemd-shared:ppc64el (255.4-1ubuntu5) over (255.2-3ubuntu2) ...
244s Setting up libsystemd-shared:ppc64el (255.4-1ubuntu5) ...
244s Setting up systemd-dev (255.4-1ubuntu5) ...
244s Setting up systemd (255.4-1ubuntu5) ...
245s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70160 files and directories currently installed.)
245s Preparing to unpack .../00-systemd-sysv_255.4-1ubuntu5_ppc64el.deb ...
245s Unpacking systemd-sysv (255.4-1ubuntu5) over (255.2-3ubuntu2) ...
245s Preparing to unpack .../01-libpam-systemd_255.4-1ubuntu5_ppc64el.deb ...
245s Unpacking libpam-systemd:ppc64el (255.4-1ubuntu5) over (255.2-3ubuntu2) ...
245s Preparing to unpack .../02-systemd-timesyncd_255.4-1ubuntu5_ppc64el.deb ...
245s Unpacking systemd-timesyncd (255.4-1ubuntu5) over (255.2-3ubuntu2) ...
245s Preparing to unpack .../03-systemd-resolved_255.4-1ubuntu5_ppc64el.deb ...
245s Unpacking systemd-resolved (255.4-1ubuntu5) over (255.2-3ubuntu2) ...
245s Preparing to unpack .../04-sudo_1.9.15p5-3ubuntu3_ppc64el.deb ...
245s Unpacking sudo (1.9.15p5-3ubuntu3) over (1.9.15p5-3ubuntu1) ...
245s Preparing to unpack .../05-rsync_3.2.7-1build1_ppc64el.deb ...
245s Unpacking rsync (3.2.7-1build1) over (3.2.7-1) ...
245s Preparing to unpack .../06-python3-cryptography_41.0.7-4build2_ppc64el.deb ...
245s Unpacking python3-cryptography (41.0.7-4build2) over (41.0.7-3) ...
245s Preparing to unpack .../07-openssl_3.0.13-0ubuntu2_ppc64el.deb ...
245s Unpacking openssl (3.0.13-0ubuntu2) over (3.0.10-1ubuntu4) ...
245s Preparing to unpack .../08-openssh-sftp-server_1%3a9.6p1-3ubuntu11_ppc64el.deb ...
245s Unpacking openssh-sftp-server (1:9.6p1-3ubuntu11) over (1:9.6p1-3ubuntu2) ...
245s Preparing to unpack .../09-openssh-client_1%3a9.6p1-3ubuntu11_ppc64el.deb ...
245s Unpacking openssh-client (1:9.6p1-3ubuntu11) over (1:9.6p1-3ubuntu2) ...
245s Preparing to unpack .../10-openssh-server_1%3a9.6p1-3ubuntu11_ppc64el.deb ...
245s Unpacking openssh-server (1:9.6p1-3ubuntu11) over (1:9.6p1-3ubuntu2) ...
245s Preparing to unpack .../11-libssh-4_0.10.6-2build1_ppc64el.deb ...
245s Unpacking libssh-4:ppc64el (0.10.6-2build1) over (0.10.6-2) ...
246s Preparing to unpack .../12-libsasl2-modules_2.1.28+dfsg1-5ubuntu1_ppc64el.deb ...
246s Unpacking libsasl2-modules:ppc64el (2.1.28+dfsg1-5ubuntu1) over (2.1.28+dfsg1-4) ...
246s Preparing to unpack .../13-python3.12_3.12.2-4build3_ppc64el.deb ...
246s Unpacking python3.12 (3.12.2-4build3) over (3.12.2-1) ...
246s Preparing to unpack .../14-python3.12-minimal_3.12.2-4build3_ppc64el.deb ...
246s Unpacking python3.12-minimal (3.12.2-4build3) over (3.12.2-1) ...
246s Preparing to unpack .../15-libpython3.12-minimal_3.12.2-4build3_ppc64el.deb ...
246s Unpacking libpython3.12-minimal:ppc64el (3.12.2-4build3) over (3.12.2-1) ...
246s Preparing to unpack .../16-grub-ieee1275_2.12-1ubuntu5_ppc64el.deb ...
246s Unpacking grub-ieee1275 (2.12-1ubuntu5) over (2.12-1ubuntu4) ...
246s Preparing to unpack .../17-grub2-common_2.12-1ubuntu5_ppc64el.deb ...
246s Unpacking grub2-common (2.12-1ubuntu5) over (2.12-1ubuntu4) ...
246s Preparing to unpack .../18-grub-common_2.12-1ubuntu5_ppc64el.deb ...
246s Unpacking grub-common (2.12-1ubuntu5) over (2.12-1ubuntu4) ...
246s Preparing to unpack .../19-grub-ieee1275-bin_2.12-1ubuntu5_ppc64el.deb ...
246s Unpacking grub-ieee1275-bin (2.12-1ubuntu5) over (2.12-1ubuntu4) ...
246s dpkg: libparted2:ppc64el: dependency problems, but removing anyway as you requested:
246s  parted depends on libparted2 (= 3.6-3).
246s 
246s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70160 files and directories currently installed.)
246s Removing libparted2:ppc64el (3.6-3) ...
246s Selecting previously unselected package libparted2t64:ppc64el.
246s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70154 files and directories currently installed.)
246s Preparing to unpack .../0-libparted2t64_3.6-3.1build2_ppc64el.deb ...
246s Unpacking libparted2t64:ppc64el (3.6-3.1build2) ...
246s Preparing to unpack .../1-parted_3.6-3.1build2_ppc64el.deb ...
246s Unpacking parted (3.6-3.1build2) over (3.6-3) ...
246s Preparing to unpack .../2-python3.11_3.11.8-1build4_ppc64el.deb ...
246s Unpacking python3.11 (3.11.8-1build4) over (3.11.8-1) ...
246s Preparing to unpack .../3-python3.11-minimal_3.11.8-1build4_ppc64el.deb ...
246s Unpacking python3.11-minimal (3.11.8-1build4) over (3.11.8-1) ...
246s Preparing to unpack .../4-libpython3.11-minimal_3.11.8-1build4_ppc64el.deb ...
247s Unpacking libpython3.11-minimal:ppc64el (3.11.8-1build4) over (3.11.8-1) ...
247s Preparing to unpack .../5-libpython3.11-stdlib_3.11.8-1build4_ppc64el.deb ...
247s Unpacking libpython3.11-stdlib:ppc64el (3.11.8-1build4) over (3.11.8-1) ...
247s Preparing to unpack .../6-gnupg-utils_2.4.4-2ubuntu15_ppc64el.deb ...
247s Unpacking gnupg-utils (2.4.4-2ubuntu15) over (2.4.4-2ubuntu7) ...
247s Preparing to unpack .../7-gpg-agent_2.4.4-2ubuntu15_ppc64el.deb ...
247s Unpacking gpg-agent (2.4.4-2ubuntu15) over (2.4.4-2ubuntu7) ...
247s Preparing to unpack .../8-gpg-wks-client_2.4.4-2ubuntu15_ppc64el.deb ...
247s Unpacking gpg-wks-client (2.4.4-2ubuntu15) over (2.4.4-2ubuntu7) ...
247s Preparing to unpack .../9-gpg_2.4.4-2ubuntu15_ppc64el.deb ...
247s Unpacking gpg (2.4.4-2ubuntu15) over (2.4.4-2ubuntu7) ...
247s dpkg: libnpth0:ppc64el: dependency problems, but removing anyway as you requested:
247s  keyboxd depends on libnpth0 (>= 0.90).
247s  gpgv depends on libnpth0 (>= 0.90).
247s  gpgsm depends on libnpth0 (>= 0.90).
247s  dirmngr depends on libnpth0 (>= 0.90).
247s 
247s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70159 files and directories currently installed.)
247s Removing libnpth0:ppc64el (1.6-3build2) ...
247s Selecting previously unselected package libnpth0t64:ppc64el.
247s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70154 files and directories currently installed.)
247s Preparing to unpack .../libnpth0t64_1.6-3.1_ppc64el.deb ...
247s Unpacking libnpth0t64:ppc64el (1.6-3.1) ...
247s Setting up libnpth0t64:ppc64el (1.6-3.1) ...
247s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70160 files and directories currently installed.)
247s Preparing to unpack .../gpgv_2.4.4-2ubuntu15_ppc64el.deb ...
247s Unpacking gpgv (2.4.4-2ubuntu15) over (2.4.4-2ubuntu7) ...
247s Setting up gpgv (2.4.4-2ubuntu15) ...
247s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70160 files and directories currently installed.)
247s Preparing to unpack .../dirmngr_2.4.4-2ubuntu15_ppc64el.deb ...
247s Unpacking dirmngr (2.4.4-2ubuntu15) over (2.4.4-2ubuntu7) ...
247s Preparing to unpack .../gnupg_2.4.4-2ubuntu15_all.deb ...
247s Unpacking gnupg (2.4.4-2ubuntu15) over (2.4.4-2ubuntu7) ...
247s Preparing to unpack .../keyboxd_2.4.4-2ubuntu15_ppc64el.deb ...
247s Unpacking keyboxd (2.4.4-2ubuntu15) over (2.4.4-2ubuntu7) ...
247s Preparing to unpack .../gpgconf_2.4.4-2ubuntu15_ppc64el.deb ...
247s Unpacking gpgconf (2.4.4-2ubuntu15) over (2.4.4-2ubuntu7) ...
247s Preparing to unpack .../gpgsm_2.4.4-2ubuntu15_ppc64el.deb ...
247s Unpacking gpgsm (2.4.4-2ubuntu15) over (2.4.4-2ubuntu7) ...
247s dpkg: libreadline8:ppc64el: dependency problems, but removing anyway as you requested:
247s  libpython3.12-stdlib:ppc64el depends on libreadline8 (>= 7.0~beta).
247s  gawk depends on libreadline8 (>= 6.0).
247s  fdisk depends on libreadline8 (>= 6.0).
247s  bc depends on libreadline8 (>= 6.0).
247s 
247s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70160 files and directories currently installed.)
247s Removing libreadline8:ppc64el (8.2-3) ...
247s Selecting previously unselected package libreadline8t64:ppc64el.
247s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70148 files and directories currently installed.)
247s Preparing to unpack .../libreadline8t64_8.2-4_ppc64el.deb ...
247s Adding 'diversion of /lib/powerpc64le-linux-gnu/libhistory.so.8 to /lib/powerpc64le-linux-gnu/libhistory.so.8.usr-is-merged by libreadline8t64'
247s Adding 'diversion of /lib/powerpc64le-linux-gnu/libhistory.so.8.2 to /lib/powerpc64le-linux-gnu/libhistory.so.8.2.usr-is-merged by libreadline8t64'
247s Adding 'diversion of /lib/powerpc64le-linux-gnu/libreadline.so.8 to /lib/powerpc64le-linux-gnu/libreadline.so.8.usr-is-merged by libreadline8t64'
247s Adding 'diversion of /lib/powerpc64le-linux-gnu/libreadline.so.8.2 to /lib/powerpc64le-linux-gnu/libreadline.so.8.2.usr-is-merged by libreadline8t64'
247s Unpacking libreadline8t64:ppc64el (8.2-4) ...
247s Setting up libreadline8t64:ppc64el (8.2-4) ...
247s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70168 files and directories currently installed.)
247s Preparing to unpack .../gawk_1%3a5.2.1-2build2_ppc64el.deb ...
247s Unpacking gawk (1:5.2.1-2build2) over (1:5.2.1-2) ...
247s Preparing to unpack .../fdisk_2.39.3-9ubuntu2_ppc64el.deb ...
247s Unpacking fdisk (2.39.3-9ubuntu2) over (2.39.3-6ubuntu2) ...
247s Preparing to unpack .../bc_1.07.1-3ubuntu2_ppc64el.deb ...
247s Unpacking bc (1.07.1-3ubuntu2) over (1.07.1-3build1) ...
247s Preparing to unpack .../libpython3.12-stdlib_3.12.2-4build3_ppc64el.deb ...
248s Unpacking libpython3.12-stdlib:ppc64el (3.12.2-4build3) over (3.12.2-1) ...
248s Preparing to unpack .../perl-base_5.38.2-3.2_ppc64el.deb ...
248s Unpacking perl-base (5.38.2-3.2) over (5.38.2-3) ...
248s Setting up perl-base (5.38.2-3.2) ...
248s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70166 files and directories currently installed.)
248s Preparing to unpack .../perl-modules-5.38_5.38.2-3.2_all.deb ...
248s Unpacking perl-modules-5.38 (5.38.2-3.2) over (5.38.2-3) ...
248s Preparing to unpack .../python3-gdbm_3.12.2-3ubuntu1.1_ppc64el.deb ...
248s Unpacking python3-gdbm:ppc64el (3.12.2-3ubuntu1.1) over (3.11.5-1) ...
248s Preparing to unpack .../man-db_2.12.0-3build4_ppc64el.deb ...
248s Unpacking man-db (2.12.0-3build4) over (2.12.0-3) ...
248s dpkg: libgdbm-compat4:ppc64el: dependency problems, but removing anyway as you requested:
248s  libperl5.38:ppc64el depends on libgdbm-compat4 (>= 1.18-3).
248s 
249s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70166 files and directories currently installed.)
249s Removing libgdbm-compat4:ppc64el (1.23-5) ...
249s dpkg: libgdbm6:ppc64el: dependency problems, but removing anyway as you requested:
249s  libperl5.38:ppc64el depends on libgdbm6 (>= 1.21).
249s 
249s Removing libgdbm6:ppc64el (1.23-5) ...
249s Selecting previously unselected package libgdbm6t64:ppc64el.
249s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70156 files and directories currently installed.)
249s Preparing to unpack .../libgdbm6t64_1.23-5.1_ppc64el.deb ...
249s Unpacking libgdbm6t64:ppc64el (1.23-5.1) ...
249s Selecting previously unselected package libgdbm-compat4t64:ppc64el.
249s Preparing to unpack .../libgdbm-compat4t64_1.23-5.1_ppc64el.deb ...
249s Unpacking libgdbm-compat4t64:ppc64el (1.23-5.1) ...
249s dpkg: libperl5.38:ppc64el: dependency problems, but removing anyway as you requested:
249s  perl depends on libperl5.38 (= 5.38.2-3).
249s 
249s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70168 files and directories currently installed.)
249s Removing libperl5.38:ppc64el (5.38.2-3) ...
249s Selecting previously unselected package libperl5.38t64:ppc64el.
249s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 69645 files and directories currently installed.)
249s Preparing to unpack .../libperl5.38t64_5.38.2-3.2_ppc64el.deb ...
249s Unpacking libperl5.38t64:ppc64el (5.38.2-3.2) ...
249s Preparing to unpack .../perl_5.38.2-3.2_ppc64el.deb ...
249s Unpacking perl (5.38.2-3.2) over (5.38.2-3) ...
249s dpkg: libdb5.3:ppc64el: dependency problems, but removing anyway as you requested:
249s  libsasl2-modules-db:ppc64el depends on libdb5.3.
249s  libpam-modules:ppc64el depends on libdb5.3.
249s  iproute2 depends on libdb5.3.
249s  apt-utils depends on libdb5.3.
249s 
249s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70168 files and directories currently installed.)
249s Removing libdb5.3:ppc64el (5.3.28+dfsg2-4) ...
249s Selecting previously unselected package libdb5.3t64:ppc64el.
249s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70162 files and directories currently installed.)
249s Preparing to unpack .../libdb5.3t64_5.3.28+dfsg2-6_ppc64el.deb ...
249s Unpacking libdb5.3t64:ppc64el (5.3.28+dfsg2-6) ...
249s Preparing to unpack .../libsasl2-modules-db_2.1.28+dfsg1-5ubuntu1_ppc64el.deb ...
249s Unpacking libsasl2-modules-db:ppc64el (2.1.28+dfsg1-5ubuntu1) over (2.1.28+dfsg1-4) ...
249s Preparing to unpack .../libsasl2-2_2.1.28+dfsg1-5ubuntu1_ppc64el.deb ...
249s Unpacking libsasl2-2:ppc64el (2.1.28+dfsg1-5ubuntu1) over (2.1.28+dfsg1-4) ...
249s dpkg: libnvme1: dependency problems, but removing anyway as you requested:
249s  libblockdev-nvme3:ppc64el depends on libnvme1 (>= 1.7.1).
249s 
249s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70168 files and directories currently installed.)
249s Removing libnvme1 (1.8-2) ...
249s Selecting previously unselected package libnvme1t64.
249s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70161 files and directories currently installed.)
249s Preparing to unpack .../libnvme1t64_1.8-3_ppc64el.deb ...
249s Unpacking libnvme1t64 (1.8-3) ...
249s Preparing to unpack .../wget_1.21.4-1ubuntu2_ppc64el.deb ...
249s Unpacking wget (1.21.4-1ubuntu2) over (1.21.4-1ubuntu1) ...
249s dpkg: libcurl4:ppc64el: dependency problems, but removing anyway as you requested:
249s  curl depends on libcurl4 (= 8.5.0-2ubuntu2).
249s 
249s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70169 files and directories currently installed.)
249s Removing libcurl4:ppc64el (8.5.0-2ubuntu2) ...
249s Selecting previously unselected package libcurl4t64:ppc64el.
249s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70164 files and directories currently installed.)
249s Preparing to unpack .../libcurl4t64_8.5.0-2ubuntu8_ppc64el.deb ...
249s Unpacking libcurl4t64:ppc64el (8.5.0-2ubuntu8) ...
249s Preparing to unpack .../curl_8.5.0-2ubuntu8_ppc64el.deb ...
249s Unpacking curl (8.5.0-2ubuntu8) over (8.5.0-2ubuntu2) ...
249s dpkg: libpsl5:ppc64el: dependency problems, but removing anyway as you requested:
249s  libcurl3-gnutls:ppc64el depends on libpsl5 (>= 0.16.0).
249s 
249s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70170 files and directories currently installed.)
249s Removing libpsl5:ppc64el (0.21.2-1build1) ...
249s Selecting previously unselected package libpsl5t64:ppc64el.
249s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70165 files and directories currently installed.)
249s Preparing to unpack .../libpsl5t64_0.21.2-1.1_ppc64el.deb ...
249s Unpacking libpsl5t64:ppc64el (0.21.2-1.1) ...
249s dpkg: libarchive13:ppc64el: dependency problems, but removing anyway as you requested:
249s  fwupd depends on libarchive13 (>= 3.2.1).
249s 
250s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70171 files and directories currently installed.)
250s Removing libarchive13:ppc64el (3.7.2-1ubuntu2) ...
250s Selecting previously unselected package libarchive13t64:ppc64el.
250s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70165 files and directories currently installed.)
250s Preparing to unpack .../libarchive13t64_3.7.2-1.1ubuntu2_ppc64el.deb ...
250s Unpacking libarchive13t64:ppc64el (3.7.2-1.1ubuntu2) ...
250s Preparing to unpack .../fwupd_1.9.15-2_ppc64el.deb ...
250s Unpacking fwupd (1.9.15-2) over (1.9.14-1) ...
250s dpkg: libcurl3-gnutls:ppc64el: dependency problems, but removing anyway as you requested:
250s  libfwupd2:ppc64el depends on libcurl3-gnutls (>= 7.63.0).
250s 
250s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70172 files and directories currently installed.)
250s Removing libcurl3-gnutls:ppc64el (8.5.0-2ubuntu2) ...
250s Selecting previously unselected package libcurl3t64-gnutls:ppc64el.
250s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70165 files and directories currently installed.)
250s Preparing to unpack .../00-libcurl3t64-gnutls_8.5.0-2ubuntu8_ppc64el.deb ...
250s Unpacking libcurl3t64-gnutls:ppc64el (8.5.0-2ubuntu8) ...
250s Preparing to unpack .../01-libfwupd2_1.9.15-2_ppc64el.deb ...
250s Unpacking libfwupd2:ppc64el (1.9.15-2) over (1.9.14-1) ...
250s Preparing to unpack .../02-libblockdev3_3.1.0-1build1_ppc64el.deb ...
250s Unpacking libblockdev3:ppc64el (3.1.0-1build1) over (3.1.0-1) ...
250s Preparing to unpack .../03-libblockdev-utils3_3.1.0-1build1_ppc64el.deb ...
250s Unpacking libblockdev-utils3:ppc64el (3.1.0-1build1) over (3.1.0-1) ...
250s Preparing to unpack .../04-libblockdev-swap3_3.1.0-1build1_ppc64el.deb ...
250s Unpacking libblockdev-swap3:ppc64el (3.1.0-1build1) over (3.1.0-1) ...
250s Preparing to unpack .../05-libblockdev-part3_3.1.0-1build1_ppc64el.deb ...
250s Unpacking libblockdev-part3:ppc64el (3.1.0-1build1) over (3.1.0-1) ...
250s Preparing to unpack .../06-libblockdev-nvme3_3.1.0-1build1_ppc64el.deb ...
250s Unpacking libblockdev-nvme3:ppc64el (3.1.0-1build1) over (3.1.0-1) ...
250s Preparing to unpack .../07-libblockdev-mdraid3_3.1.0-1build1_ppc64el.deb ...
250s Unpacking libblockdev-mdraid3:ppc64el (3.1.0-1build1) over (3.1.0-1) ...
250s Preparing to unpack .../08-libblockdev-loop3_3.1.0-1build1_ppc64el.deb ...
250s Unpacking libblockdev-loop3:ppc64el (3.1.0-1build1) over (3.1.0-1) ...
250s Preparing to unpack .../09-e2fsprogs-l10n_1.47.0-2.4~exp1ubuntu2_all.deb ...
250s Unpacking e2fsprogs-l10n (1.47.0-2.4~exp1ubuntu2) over (1.47.0-2ubuntu1) ...
250s Preparing to unpack .../10-logsave_1.47.0-2.4~exp1ubuntu2_ppc64el.deb ...
250s Unpacking logsave (1.47.0-2.4~exp1ubuntu2) over (1.47.0-2ubuntu1) ...
250s dpkg: libext2fs2:ppc64el: dependency problems, but removing anyway as you requested:
250s  libblockdev-fs3:ppc64el depends on libext2fs2 (>= 1.42.11).
250s  e2fsprogs depends on libext2fs2 (= 1.47.0-2ubuntu1).
250s  btrfs-progs depends on libext2fs2 (>= 1.42).
250s 
250s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70172 files and directories currently installed.)
250s Removing libext2fs2:ppc64el (1.47.0-2ubuntu1) ...
250s Selecting previously unselected package libext2fs2t64:ppc64el.
250s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70165 files and directories currently installed.)
250s Preparing to unpack .../libext2fs2t64_1.47.0-2.4~exp1ubuntu2_ppc64el.deb ...
250s Adding 'diversion of /lib/powerpc64le-linux-gnu/libe2p.so.2 to /lib/powerpc64le-linux-gnu/libe2p.so.2.usr-is-merged by libext2fs2t64'
250s Adding 'diversion of /lib/powerpc64le-linux-gnu/libe2p.so.2.3 to /lib/powerpc64le-linux-gnu/libe2p.so.2.3.usr-is-merged by libext2fs2t64'
250s Adding 'diversion of /lib/powerpc64le-linux-gnu/libext2fs.so.2 to /lib/powerpc64le-linux-gnu/libext2fs.so.2.usr-is-merged by libext2fs2t64'
250s Adding 'diversion of /lib/powerpc64le-linux-gnu/libext2fs.so.2.4 to /lib/powerpc64le-linux-gnu/libext2fs.so.2.4.usr-is-merged by libext2fs2t64'
250s Unpacking libext2fs2t64:ppc64el (1.47.0-2.4~exp1ubuntu2) ...
250s Setting up libext2fs2t64:ppc64el (1.47.0-2.4~exp1ubuntu2) ...
250s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70181 files and directories currently installed.)
250s Preparing to unpack .../e2fsprogs_1.47.0-2.4~exp1ubuntu2_ppc64el.deb ...
250s Unpacking e2fsprogs (1.47.0-2.4~exp1ubuntu2) over (1.47.0-2ubuntu1) ...
250s dpkg: libreiserfscore0: dependency problems, but removing anyway as you requested:
250s  btrfs-progs depends on libreiserfscore0 (>= 1:3.6.27).
250s 
250s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70181 files and directories currently installed.)
250s Removing libreiserfscore0 (1:3.6.27-7) ...
250s Selecting previously unselected package libreiserfscore0t64.
250s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70176 files and directories currently installed.)
250s Preparing to unpack .../libreiserfscore0t64_1%3a3.6.27-7.1_ppc64el.deb ...
250s Unpacking libreiserfscore0t64 (1:3.6.27-7.1) ...
250s Preparing to unpack .../btrfs-progs_6.6.3-1.1build1_ppc64el.deb ...
250s Unpacking btrfs-progs (6.6.3-1.1build1) over (6.6.3-1.1) ...
250s Preparing to unpack .../libblockdev-fs3_3.1.0-1build1_ppc64el.deb ...
250s Unpacking libblockdev-fs3:ppc64el (3.1.0-1build1) over (3.1.0-1) ...
251s Preparing to unpack .../libblockdev-crypto3_3.1.0-1build1_ppc64el.deb ...
251s Unpacking libblockdev-crypto3:ppc64el (3.1.0-1build1) over (3.1.0-1) ...
251s Preparing to unpack .../bolt_0.9.6-2build1_ppc64el.deb ...
251s Unpacking bolt (0.9.6-2build1) over (0.9.6-2) ...
251s dpkg: libglib2.0-0:ppc64el: dependency problems, but removing anyway as you requested:
251s  libnetplan0:ppc64el depends on libglib2.0-0 (>= 2.75.3).
251s  libjcat1:ppc64el depends on libglib2.0-0 (>= 2.75.3).
251s 
251s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70182 files and directories currently installed.)
251s Removing libglib2.0-0:ppc64el (2.79.2-1~ubuntu1) ...
251s Selecting previously unselected package libglib2.0-0t64:ppc64el.
251s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70157 files and directories currently installed.)
251s Preparing to unpack .../0-libglib2.0-0t64_2.79.3-3ubuntu5_ppc64el.deb ...
251s libglib2.0-0t64.preinst: Removing /var/lib/dpkg/info/libglib2.0-0:ppc64el.postrm to avoid loss of /usr/share/glib-2.0/schemas/gschemas.compiled...
251s removed '/var/lib/dpkg/info/libglib2.0-0:ppc64el.postrm'
251s Unpacking libglib2.0-0t64:ppc64el (2.79.3-3ubuntu5) ...
251s Preparing to unpack .../1-libjcat1_0.2.0-2build2_ppc64el.deb ...
251s Unpacking libjcat1:ppc64el (0.2.0-2build2) over (0.2.0-2) ...
251s Preparing to unpack .../2-libldap2_2.6.7+dfsg-1~exp1ubuntu6_ppc64el.deb ...
251s Unpacking libldap2:ppc64el (2.6.7+dfsg-1~exp1ubuntu6) over (2.6.7+dfsg-1~exp1ubuntu1) ...
251s Preparing to unpack .../3-ubuntu-pro-client-l10n_31.2.2_ppc64el.deb ...
251s Unpacking ubuntu-pro-client-l10n (31.2.2) over (31.1) ...
251s Preparing to unpack .../4-ubuntu-pro-client_31.2.2_ppc64el.deb ...
251s Unpacking ubuntu-pro-client (31.2.2) over (31.1) ...
251s Preparing to unpack .../5-python3-apt_2.7.7_ppc64el.deb ...
251s Unpacking python3-apt (2.7.7) over (2.7.6) ...
251s Preparing to unpack .../6-apt-utils_2.7.14_ppc64el.deb ...
251s Unpacking apt-utils (2.7.14) over (2.7.12) ...
251s dpkg: libapt-pkg6.0:ppc64el: dependency problems, but removing anyway as you requested:
251s  apt depends on libapt-pkg6.0 (>= 2.7.12).
251s 
251s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70180 files and directories currently installed.)
251s Removing libapt-pkg6.0:ppc64el (2.7.12) ...
251s dpkg: libnettle8:ppc64el: dependency problems, but removing anyway as you requested:
251s  librtmp1:ppc64el depends on libnettle8.
251s  libhogweed6:ppc64el depends on libnettle8.
251s  libgnutls30:ppc64el depends on libnettle8 (>= 3.9~).
251s 
251s Removing libnettle8:ppc64el (3.9.1-2) ...
251s Selecting previously unselected package libapt-pkg6.0t64:ppc64el.
251s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70124 files and directories currently installed.)
251s Preparing to unpack .../libapt-pkg6.0t64_2.7.14_ppc64el.deb ...
251s Unpacking libapt-pkg6.0t64:ppc64el (2.7.14) ...
251s Setting up libapt-pkg6.0t64:ppc64el (2.7.14) ...
252s Selecting previously unselected package libnettle8t64:ppc64el.
252s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70174 files and directories currently installed.)
252s Preparing to unpack .../libnettle8t64_3.9.1-2.2_ppc64el.deb ...
252s Unpacking libnettle8t64:ppc64el (3.9.1-2.2) ...
252s Setting up libnettle8t64:ppc64el (3.9.1-2.2) ...
252s dpkg: libhogweed6:ppc64el: dependency problems, but removing anyway as you requested:
252s  librtmp1:ppc64el depends on libhogweed6.
252s  libgnutls30:ppc64el depends on libhogweed6 (>= 3.6).
252s 
252s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70182 files and directories currently installed.)
252s Removing libhogweed6:ppc64el (3.9.1-2) ...
252s Selecting previously unselected package libhogweed6t64:ppc64el.
252s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70177 files and directories currently installed.)
252s Preparing to unpack .../libhogweed6t64_3.9.1-2.2_ppc64el.deb ...
252s Unpacking libhogweed6t64:ppc64el (3.9.1-2.2) ...
252s Setting up libhogweed6t64:ppc64el (3.9.1-2.2) ...
252s dpkg: libgnutls30:ppc64el: dependency problems, but removing anyway as you requested:
252s  librtmp1:ppc64el depends on libgnutls30 (>= 3.7.2).
252s  apt depends on libgnutls30 (>= 3.8.1).
252s 
252s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70183 files and directories currently installed.)
252s Removing libgnutls30:ppc64el (3.8.3-1ubuntu1) ...
252s Selecting previously unselected package libgnutls30t64:ppc64el.
252s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70174 files and directories currently installed.)
252s Preparing to unpack .../libgnutls30t64_3.8.3-1.1ubuntu2_ppc64el.deb ...
252s Unpacking libgnutls30t64:ppc64el (3.8.3-1.1ubuntu2) ...
252s Setting up libgnutls30t64:ppc64el (3.8.3-1.1ubuntu2) ...
252s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70202 files and directories currently installed.)
252s Preparing to unpack .../apt_2.7.14_ppc64el.deb ...
252s Unpacking apt (2.7.14) over (2.7.12) ...
252s Setting up apt (2.7.14) ...
253s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70202 files and directories currently installed.)
253s Preparing to unpack .../librtmp1_2.4+20151223.gitfa8646d.1-2build6_ppc64el.deb ...
253s Unpacking librtmp1:ppc64el (2.4+20151223.gitfa8646d.1-2build6) over (2.4+20151223.gitfa8646d.1-2build4) ...
253s Preparing to unpack .../liblzma5_5.6.0-0.2_ppc64el.deb ...
253s Unpacking liblzma5:ppc64el (5.6.0-0.2) over (5.4.5-0.3) ...
253s Setting up liblzma5:ppc64el (5.6.0-0.2) ...
253s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70202 files and directories currently installed.)
253s Preparing to unpack .../libblkid1_2.39.3-9ubuntu2_ppc64el.deb ...
253s Unpacking libblkid1:ppc64el (2.39.3-9ubuntu2) over (2.39.3-6ubuntu2) ...
253s Setting up libblkid1:ppc64el (2.39.3-9ubuntu2) ...
253s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70202 files and directories currently installed.)
253s Preparing to unpack .../kmod_31+20240202-2ubuntu4_ppc64el.deb ...
253s Unpacking kmod (31+20240202-2ubuntu4) over (30+20230601-2ubuntu1) ...
253s Preparing to unpack .../libkmod2_31+20240202-2ubuntu4_ppc64el.deb ...
253s Unpacking libkmod2:ppc64el (31+20240202-2ubuntu4) over (30+20230601-2ubuntu1) ...
253s Preparing to unpack .../libselinux1_3.5-2ubuntu1_ppc64el.deb ...
253s Unpacking libselinux1:ppc64el (3.5-2ubuntu1) over (3.5-2build1) ...
253s Setting up libselinux1:ppc64el (3.5-2ubuntu1) ...
253s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70202 files and directories currently installed.)
253s Preparing to unpack .../libaudit-common_1%3a3.1.2-2.1_all.deb ...
253s Unpacking libaudit-common (1:3.1.2-2.1) over (1:3.1.2-2) ...
253s Setting up libaudit-common (1:3.1.2-2.1) ...
253s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70202 files and directories currently installed.)
253s Preparing to unpack .../libcap-ng0_0.8.4-2build1_ppc64el.deb ...
253s Unpacking libcap-ng0:ppc64el (0.8.4-2build1) over (0.8.4-2) ...
253s Setting up libcap-ng0:ppc64el (0.8.4-2build1) ...
253s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70202 files and directories currently installed.)
253s Preparing to unpack .../libaudit1_1%3a3.1.2-2.1_ppc64el.deb ...
253s Unpacking libaudit1:ppc64el (1:3.1.2-2.1) over (1:3.1.2-2) ...
253s Setting up libaudit1:ppc64el (1:3.1.2-2.1) ...
253s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70202 files and directories currently installed.)
253s Preparing to unpack .../libpam0g_1.5.3-5ubuntu3_ppc64el.deb ...
253s Unpacking libpam0g:ppc64el (1.5.3-5ubuntu3) over (1.5.2-9.1ubuntu3) ...
253s Setting up libpam0g:ppc64el (1.5.3-5ubuntu3) ...
253s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70202 files and directories currently installed.)
253s Preparing to unpack .../libpam-modules-bin_1.5.3-5ubuntu3_ppc64el.deb ...
253s Unpacking libpam-modules-bin (1.5.3-5ubuntu3) over (1.5.2-9.1ubuntu3) ...
253s Setting up libpam-modules-bin (1.5.3-5ubuntu3) ...
254s pam_namespace.service is a disabled or a static unit not running, not starting it.
254s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70202 files and directories currently installed.)
254s Preparing to unpack .../libpam-modules_1.5.3-5ubuntu3_ppc64el.deb ...
254s Unpacking libpam-modules:ppc64el (1.5.3-5ubuntu3) over (1.5.2-9.1ubuntu3) ...
254s Setting up libpam-modules:ppc64el (1.5.3-5ubuntu3) ...
254s Installing new version of config file /etc/security/namespace.init ...
254s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70200 files and directories currently installed.)
254s Preparing to unpack .../libpam-runtime_1.5.3-5ubuntu3_all.deb ...
254s Unpacking libpam-runtime (1.5.3-5ubuntu3) over (1.5.2-9.1ubuntu3) ...
254s Setting up libpam-runtime (1.5.3-5ubuntu3) ...
254s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70200 files and directories currently installed.)
254s Preparing to unpack .../00-dbus-session-bus-common_1.14.10-4ubuntu2_all.deb ...
254s Unpacking dbus-session-bus-common (1.14.10-4ubuntu2) over (1.14.10-4ubuntu1) ...
254s Preparing to unpack .../01-dbus-user-session_1.14.10-4ubuntu2_ppc64el.deb ...
254s Unpacking dbus-user-session (1.14.10-4ubuntu2) over (1.14.10-4ubuntu1) ...
254s Preparing to unpack .../02-libapparmor1_4.0.0-beta3-0ubuntu2_ppc64el.deb ...
254s Unpacking libapparmor1:ppc64el (4.0.0-beta3-0ubuntu2) over (4.0.0~alpha4-0ubuntu1) ...
254s Preparing to unpack .../03-libexpat1_2.6.1-2_ppc64el.deb ...
254s Unpacking libexpat1:ppc64el (2.6.1-2) over (2.6.0-1) ...
254s Preparing to unpack .../04-dbus-system-bus-common_1.14.10-4ubuntu2_all.deb ...
254s Unpacking dbus-system-bus-common (1.14.10-4ubuntu2) over (1.14.10-4ubuntu1) ...
254s Preparing to unpack .../05-dbus-bin_1.14.10-4ubuntu2_ppc64el.deb ...
254s Unpacking dbus-bin (1.14.10-4ubuntu2) over (1.14.10-4ubuntu1) ...
254s Preparing to unpack .../06-dbus_1.14.10-4ubuntu2_ppc64el.deb ...
254s Unpacking dbus (1.14.10-4ubuntu2) over (1.14.10-4ubuntu1) ...
254s Preparing to unpack .../07-dbus-daemon_1.14.10-4ubuntu2_ppc64el.deb ...
254s Unpacking dbus-daemon (1.14.10-4ubuntu2) over (1.14.10-4ubuntu1) ...
254s Preparing to unpack .../08-libdbus-1-3_1.14.10-4ubuntu2_ppc64el.deb ...
254s Unpacking libdbus-1-3:ppc64el (1.14.10-4ubuntu2) over (1.14.10-4ubuntu1) ...
254s Preparing to unpack .../09-libdevmapper1.02.1_2%3a1.02.185-3ubuntu2_ppc64el.deb ...
254s Unpacking libdevmapper1.02.1:ppc64el (2:1.02.185-3ubuntu2) over (2:1.02.185-3ubuntu1) ...
254s Preparing to unpack .../10-libuuid1_2.39.3-9ubuntu2_ppc64el.deb ...
254s Unpacking libuuid1:ppc64el (2.39.3-9ubuntu2) over (2.39.3-6ubuntu2) ...
254s Setting up libuuid1:ppc64el (2.39.3-9ubuntu2) ...
254s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70200 files and directories currently installed.)
254s Preparing to unpack .../libcryptsetup12_2%3a2.7.0-1ubuntu2_ppc64el.deb ...
254s Unpacking libcryptsetup12:ppc64el (2:2.7.0-1ubuntu2) over (2:2.7.0-1ubuntu1) ...
255s Preparing to unpack .../libfdisk1_2.39.3-9ubuntu2_ppc64el.deb ...
255s Unpacking libfdisk1:ppc64el (2.39.3-9ubuntu2) over (2.39.3-6ubuntu2) ...
255s Preparing to unpack .../libseccomp2_2.5.5-1ubuntu2_ppc64el.deb ...
255s Unpacking libseccomp2:ppc64el (2.5.5-1ubuntu2) over (2.5.5-1ubuntu1) ...
255s Setting up libseccomp2:ppc64el (2.5.5-1ubuntu2) ...
255s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70200 files and directories currently installed.)
255s Preparing to unpack .../mount_2.39.3-9ubuntu2_ppc64el.deb ...
255s Unpacking mount (2.39.3-9ubuntu2) over (2.39.3-6ubuntu2) ...
255s Preparing to unpack .../libmount1_2.39.3-9ubuntu2_ppc64el.deb ...
255s Unpacking libmount1:ppc64el (2.39.3-9ubuntu2) over (2.39.3-6ubuntu2) ...
255s Setting up libmount1:ppc64el (2.39.3-9ubuntu2) ...
255s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70200 files and directories currently installed.)
255s Preparing to unpack .../zlib1g_1%3a1.3.dfsg-3.1ubuntu1_ppc64el.deb ...
255s Unpacking zlib1g:ppc64el (1:1.3.dfsg-3.1ubuntu1) over (1:1.3.dfsg-3ubuntu1) ...
255s Setting up zlib1g:ppc64el (1:1.3.dfsg-3.1ubuntu1) ...
255s Setting up libpython3.12-minimal:ppc64el (3.12.2-4build3) ...
255s Setting up libexpat1:ppc64el (2.6.1-2) ...
255s Setting up python3.12-minimal (3.12.2-4build3) ...
256s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70200 files and directories currently installed.)
256s Preparing to unpack .../python3-minimal_3.12.2-0ubuntu1_ppc64el.deb ...
256s Unpacking python3-minimal (3.12.2-0ubuntu1) over (3.12.1-0ubuntu2) ...
256s Setting up python3-minimal (3.12.2-0ubuntu1) ...
256s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70200 files and directories currently installed.)
256s Preparing to unpack .../python3_3.12.2-0ubuntu1_ppc64el.deb ...
256s Unpacking python3 (3.12.2-0ubuntu1) over (3.12.1-0ubuntu2) ...
256s Preparing to unpack .../libplymouth5_24.004.60-1ubuntu6_ppc64el.deb ...
256s Unpacking libplymouth5:ppc64el (24.004.60-1ubuntu6) over (24.004.60-1ubuntu3) ...
256s dpkg: libpng16-16:ppc64el: dependency problems, but removing anyway as you requested:
256s  libfreetype6:ppc64el depends on libpng16-16 (>= 1.6.2-1).
256s 
256s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70200 files and directories currently installed.)
256s Removing libpng16-16:ppc64el (1.6.43-1) ...
256s Selecting previously unselected package libpng16-16t64:ppc64el.
256s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70190 files and directories currently installed.)
256s Preparing to unpack .../0-libpng16-16t64_1.6.43-3_ppc64el.deb ...
256s Unpacking libpng16-16t64:ppc64el (1.6.43-3) ...
256s Preparing to unpack .../1-libbrotli1_1.1.0-2build1_ppc64el.deb ...
256s Unpacking libbrotli1:ppc64el (1.1.0-2build1) over (1.1.0-2) ...
256s Preparing to unpack .../2-libfreetype6_2.13.2+dfsg-1build2_ppc64el.deb ...
256s Unpacking libfreetype6:ppc64el (2.13.2+dfsg-1build2) over (2.13.2+dfsg-1) ...
256s Preparing to unpack .../3-libsqlite3-0_3.45.1-1ubuntu1_ppc64el.deb ...
256s Unpacking libsqlite3-0:ppc64el (3.45.1-1ubuntu1) over (3.45.1-1) ...
256s Preparing to unpack .../4-pinentry-curses_1.2.1-3ubuntu4_ppc64el.deb ...
256s Unpacking pinentry-curses (1.2.1-3ubuntu4) over (1.2.1-3ubuntu1) ...
256s Preparing to unpack .../5-gcc-14-base_14-20240315-1ubuntu1_ppc64el.deb ...
256s Unpacking gcc-14-base:ppc64el (14-20240315-1ubuntu1) over (14-20240303-1ubuntu1) ...
256s Setting up gcc-14-base:ppc64el (14-20240315-1ubuntu1) ...
256s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70201 files and directories currently installed.)
256s Preparing to unpack .../libgcc-s1_14-20240315-1ubuntu1_ppc64el.deb ...
256s Unpacking libgcc-s1:ppc64el (14-20240315-1ubuntu1) over (14-20240303-1ubuntu1) ...
256s Setting up libgcc-s1:ppc64el (14-20240315-1ubuntu1) ...
256s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70201 files and directories currently installed.)
256s Preparing to unpack .../libstdc++6_14-20240315-1ubuntu1_ppc64el.deb ...
256s Unpacking libstdc++6:ppc64el (14-20240315-1ubuntu1) over (14-20240303-1ubuntu1) ...
257s Setting up libstdc++6:ppc64el (14-20240315-1ubuntu1) ...
257s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70201 files and directories currently installed.)
257s Preparing to unpack .../python-apt-common_2.7.7_all.deb ...
257s Unpacking python-apt-common (2.7.7) over (2.7.6) ...
257s Preparing to unpack .../libsmartcols1_2.39.3-9ubuntu2_ppc64el.deb ...
257s Unpacking libsmartcols1:ppc64el (2.39.3-9ubuntu2) over (2.39.3-6ubuntu2) ...
257s Setting up libsmartcols1:ppc64el (2.39.3-9ubuntu2) ...
257s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70201 files and directories currently installed.)
257s Preparing to unpack .../00-readline-common_8.2-4_all.deb ...
257s Unpacking readline-common (8.2-4) over (8.2-3) ...
257s Preparing to unpack .../01-bsdextrautils_2.39.3-9ubuntu2_ppc64el.deb ...
257s Unpacking bsdextrautils (2.39.3-9ubuntu2) over (2.39.3-6ubuntu2) ...
257s Preparing to unpack .../02-groff-base_1.23.0-3build1_ppc64el.deb ...
257s Unpacking groff-base (1.23.0-3build1) over (1.23.0-3) ...
257s Preparing to unpack .../03-libpython3-stdlib_3.12.2-0ubuntu1_ppc64el.deb ...
257s Unpacking libpython3-stdlib:ppc64el (3.12.2-0ubuntu1) over (3.12.1-0ubuntu2) ...
257s Preparing to unpack .../04-libfido2-1_1.14.0-1build1_ppc64el.deb ...
257s Unpacking libfido2-1:ppc64el (1.14.0-1build1) over (1.14.0-1) ...
257s Preparing to unpack .../05-libgssapi-krb5-2_1.20.1-6ubuntu1_ppc64el.deb ...
257s Unpacking libgssapi-krb5-2:ppc64el (1.20.1-6ubuntu1) over (1.20.1-5build1) ...
257s Preparing to unpack .../06-libkrb5-3_1.20.1-6ubuntu1_ppc64el.deb ...
257s Unpacking libkrb5-3:ppc64el (1.20.1-6ubuntu1) over (1.20.1-5build1) ...
257s Preparing to unpack .../07-libkrb5support0_1.20.1-6ubuntu1_ppc64el.deb ...
257s Unpacking libkrb5support0:ppc64el (1.20.1-6ubuntu1) over (1.20.1-5build1) ...
257s Preparing to unpack .../08-libk5crypto3_1.20.1-6ubuntu1_ppc64el.deb ...
257s Unpacking libk5crypto3:ppc64el (1.20.1-6ubuntu1) over (1.20.1-5build1) ...
257s Preparing to unpack .../09-libcom-err2_1.47.0-2.4~exp1ubuntu2_ppc64el.deb ...
257s Unpacking libcom-err2:ppc64el (1.47.0-2.4~exp1ubuntu2) over (1.47.0-2ubuntu1) ...
257s Preparing to unpack .../10-libproc2-0_2%3a4.0.4-4ubuntu2_ppc64el.deb ...
257s Unpacking libproc2-0:ppc64el (2:4.0.4-4ubuntu2) over (2:4.0.4-4ubuntu1) ...
257s Preparing to unpack .../11-procps_2%3a4.0.4-4ubuntu2_ppc64el.deb ...
257s Unpacking procps (2:4.0.4-4ubuntu2) over (2:4.0.4-4ubuntu1) ...
257s Preparing to unpack .../12-libnghttp2-14_1.59.0-1build1_ppc64el.deb ...
257s Unpacking libnghttp2-14:ppc64el (1.59.0-1build1) over (1.59.0-1) ...
257s Preparing to unpack .../13-dpkg_1.22.6ubuntu5_ppc64el.deb ...
257s Unpacking dpkg (1.22.6ubuntu5) over (1.22.4ubuntu5) ...
257s Setting up dpkg (1.22.6ubuntu5) ...
258s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70202 files and directories currently installed.)
258s Preparing to unpack .../util-linux_2.39.3-9ubuntu2_ppc64el.deb ...
258s Unpacking util-linux (2.39.3-9ubuntu2) over (2.39.3-6ubuntu2) ...
258s Setting up util-linux (2.39.3-9ubuntu2) ...
259s fstrim.service is a disabled or a static unit not running, not starting it.
259s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70202 files and directories currently installed.)
259s Preparing to unpack .../libxml2_2.9.14+dfsg-1.3ubuntu2_ppc64el.deb ...
259s Unpacking libxml2:ppc64el (2.9.14+dfsg-1.3ubuntu2) over (2.9.14+dfsg-1.3ubuntu1) ...
259s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70202 files and directories currently installed.)
259s Removing libatm1:ppc64el (1:2.5.1-5) ...
259s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70197 files and directories currently installed.)
259s Preparing to unpack .../libbpf1_1%3a1.3.0-2build1_ppc64el.deb ...
259s Unpacking libbpf1:ppc64el (1:1.3.0-2build1) over (1:1.3.0-2) ...
259s Preparing to unpack .../iproute2_6.1.0-1ubuntu5_ppc64el.deb ...
259s Unpacking iproute2 (6.1.0-1ubuntu5) over (6.1.0-1ubuntu2) ...
259s dpkg: libelf1:ppc64el: dependency problems, but removing anyway as you requested:
259s  linux-headers-6.8.0-11-generic depends on libelf1 (>= 0.144).
259s 
259s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70197 files and directories currently installed.)
259s Removing libelf1:ppc64el (0.190-1) ...
259s Selecting previously unselected package libelf1t64:ppc64el.
259s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70192 files and directories currently installed.)
259s Preparing to unpack .../libelf1t64_0.190-1.1build2_ppc64el.deb ...
259s Unpacking libelf1t64:ppc64el (0.190-1.1build2) ...
259s Preparing to unpack .../dhcpcd-base_1%3a10.0.6-1ubuntu2_ppc64el.deb ...
259s Unpacking dhcpcd-base (1:10.0.6-1ubuntu2) over (1:10.0.6-1ubuntu1) ...
259s Preparing to unpack .../file_1%3a5.45-3_ppc64el.deb ...
259s Unpacking file (1:5.45-3) over (1:5.45-2) ...
259s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70197 files and directories currently installed.)
259s Removing libmagic1:ppc64el (1:5.45-2) ...
259s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70187 files and directories currently installed.)
259s Preparing to unpack .../libmagic-mgc_1%3a5.45-3_ppc64el.deb ...
259s Unpacking libmagic-mgc (1:5.45-3) over (1:5.45-2) ...
259s Selecting previously unselected package libmagic1t64:ppc64el.
259s Preparing to unpack .../libmagic1t64_1%3a5.45-3_ppc64el.deb ...
259s Unpacking libmagic1t64:ppc64el (1:5.45-3) ...
259s Preparing to unpack .../libtirpc-common_1.3.4+ds-1.1_all.deb ...
259s Unpacking libtirpc-common (1.3.4+ds-1.1) over (1.3.4+ds-1build1) ...
259s Preparing to unpack .../lsof_4.95.0-1build2_ppc64el.deb ...
259s Unpacking lsof (4.95.0-1build2) over (4.95.0-1build1) ...
259s Preparing to unpack .../libnsl2_1.3.0-3build2_ppc64el.deb ...
259s Unpacking libnsl2:ppc64el (1.3.0-3build2) over (1.3.0-3) ...
259s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70198 files and directories currently installed.)
259s Removing libtirpc3:ppc64el (1.3.4+ds-1build1) ...
259s Selecting previously unselected package libtirpc3t64:ppc64el.
259s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70192 files and directories currently installed.)
259s Preparing to unpack .../libtirpc3t64_1.3.4+ds-1.1_ppc64el.deb ...
259s Adding 'diversion of /lib/powerpc64le-linux-gnu/libtirpc.so.3 to /lib/powerpc64le-linux-gnu/libtirpc.so.3.usr-is-merged by libtirpc3t64'
259s Adding 'diversion of /lib/powerpc64le-linux-gnu/libtirpc.so.3.0.0 to /lib/powerpc64le-linux-gnu/libtirpc.so.3.0.0.usr-is-merged by libtirpc3t64'
259s Unpacking libtirpc3t64:ppc64el (1.3.4+ds-1.1) ...
259s Preparing to unpack .../multipath-tools_0.9.4-5ubuntu6_ppc64el.deb ...
259s Unpacking multipath-tools (0.9.4-5ubuntu6) over (0.9.4-5ubuntu3) ...
260s dpkg: liburcu8:ppc64el: dependency problems, but removing anyway as you requested:
260s  xfsprogs depends on liburcu8 (>= 0.13.0).
260s 
260s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70202 files and directories currently installed.)
260s Removing liburcu8:ppc64el (0.14.0-3) ...
260s Selecting previously unselected package liburcu8t64:ppc64el.
260s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70183 files and directories currently installed.)
260s Preparing to unpack .../liburcu8t64_0.14.0-3.1_ppc64el.deb ...
260s Unpacking liburcu8t64:ppc64el (0.14.0-3.1) ...
260s Preparing to unpack .../bind9-host_1%3a9.18.24-0ubuntu3_ppc64el.deb ...
260s Unpacking bind9-host (1:9.18.24-0ubuntu3) over (1:9.18.21-0ubuntu1) ...
260s Preparing to unpack .../bind9-dnsutils_1%3a9.18.24-0ubuntu3_ppc64el.deb ...
260s Unpacking bind9-dnsutils (1:9.18.24-0ubuntu3) over (1:9.18.21-0ubuntu1) ...
260s Preparing to unpack .../bind9-libs_1%3a9.18.24-0ubuntu3_ppc64el.deb ...
260s Unpacking bind9-libs:ppc64el (1:9.18.24-0ubuntu3) over (1:9.18.21-0ubuntu1) ...
260s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70203 files and directories currently installed.)
260s Removing libuv1:ppc64el (1.48.0-1) ...
260s Selecting previously unselected package libuv1t64:ppc64el.
260s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70198 files and directories currently installed.)
260s Preparing to unpack .../libuv1t64_1.48.0-1.1_ppc64el.deb ...
260s Unpacking libuv1t64:ppc64el (1.48.0-1.1) ...
260s Preparing to unpack .../liblocale-gettext-perl_1.07-6ubuntu4_ppc64el.deb ...
260s Unpacking liblocale-gettext-perl (1.07-6ubuntu4) over (1.07-6build1) ...
260s Preparing to unpack .../uuid-runtime_2.39.3-9ubuntu2_ppc64el.deb ...
260s Unpacking uuid-runtime (2.39.3-9ubuntu2) over (2.39.3-6ubuntu2) ...
260s Preparing to unpack .../libdebconfclient0_0.271ubuntu2_ppc64el.deb ...
260s Unpacking libdebconfclient0:ppc64el (0.271ubuntu2) over (0.271ubuntu1) ...
260s Setting up libdebconfclient0:ppc64el (0.271ubuntu2) ...
260s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70204 files and directories currently installed.)
260s Preparing to unpack .../libsemanage-common_3.5-1build4_all.deb ...
260s Unpacking libsemanage-common (3.5-1build4) over (3.5-1build2) ...
260s Setting up libsemanage-common (3.5-1build4) ...
260s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70204 files and directories currently installed.)
260s Preparing to unpack .../libsemanage2_3.5-1build4_ppc64el.deb ...
260s Unpacking libsemanage2:ppc64el (3.5-1build4) over (3.5-1build2) ...
260s Setting up libsemanage2:ppc64el (3.5-1build4) ...
260s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70204 files and directories currently installed.)
260s Preparing to unpack .../install-info_7.1-3build1_ppc64el.deb ...
260s Unpacking install-info (7.1-3build1) over (7.1-3) ...
260s Setting up install-info (7.1-3build1) ...
260s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 70204 files and directories currently installed.)
260s Preparing to unpack .../000-gcc-13-base_13.2.0-21ubuntu1_ppc64el.deb ...
260s Unpacking gcc-13-base:ppc64el (13.2.0-21ubuntu1) over (13.2.0-17ubuntu2) ...
260s Preparing to unpack .../001-libss2_1.47.0-2.4~exp1ubuntu2_ppc64el.deb ...
260s Unpacking libss2:ppc64el (1.47.0-2.4~exp1ubuntu2) over (1.47.0-2ubuntu1) ...
260s Preparing to unpack .../002-dmsetup_2%3a1.02.185-3ubuntu2_ppc64el.deb ...
260s Unpacking dmsetup (2:1.02.185-3ubuntu2) over (2:1.02.185-3ubuntu1) ...
260s Preparing to unpack .../003-eject_2.39.3-9ubuntu2_ppc64el.deb ...
260s Unpacking eject (2.39.3-9ubuntu2) over (2.39.3-6ubuntu2) ...
260s Preparing to unpack .../004-krb5-locales_1.20.1-6ubuntu1_all.deb ...
260s Unpacking krb5-locales (1.20.1-6ubuntu1) over (1.20.1-5build1) ...
260s Preparing to unpack .../005-libglib2.0-data_2.79.3-3ubuntu5_all.deb ...
260s Unpacking libglib2.0-data (2.79.3-3ubuntu5) over (2.79.2-1~ubuntu1) ...
260s Preparing to unpack .../006-libslang2_2.3.3-3build1_ppc64el.deb ...
260s Unpacking libslang2:ppc64el (2.3.3-3build1) over (2.3.3-3) ...
260s Preparing to unpack .../007-libtext-charwidth-perl_0.04-11build2_ppc64el.deb ...
260s Unpacking libtext-charwidth-perl:ppc64el (0.04-11build2) over (0.04-11build1) ...
260s Preparing to unpack .../008-libtext-iconv-perl_1.7-8build2_ppc64el.deb ...
260s Unpacking libtext-iconv-perl:ppc64el (1.7-8build2) over (1.7-8build1) ...
260s Preparing to unpack .../009-python3-yaml_6.0.1-2build1_ppc64el.deb ...
260s Unpacking python3-yaml (6.0.1-2build1) over (6.0.1-2) ...
260s Preparing to unpack .../010-python3-setuptools_68.1.2-2ubuntu1_all.deb ...
261s Unpacking python3-setuptools (68.1.2-2ubuntu1) over (68.1.2-2) ...
261s Preparing to unpack .../011-python3-pkg-resources_68.1.2-2ubuntu1_all.deb ...
261s Unpacking python3-pkg-resources (68.1.2-2ubuntu1) over (68.1.2-2) ...
261s Preparing to unpack .../012-rsyslog_8.2312.0-3ubuntu7_ppc64el.deb ...
261s Unpacking rsyslog (8.2312.0-3ubuntu7) over (8.2312.0-3ubuntu3) ...
261s Preparing to unpack .../013-vim-tiny_2%3a9.1.0016-1ubuntu6_ppc64el.deb ...
261s Unpacking vim-tiny (2:9.1.0016-1ubuntu6) over (2:9.1.0016-1ubuntu2) ...
261s Preparing to unpack .../014-vim-common_2%3a9.1.0016-1ubuntu6_all.deb ...
261s Unpacking vim-common (2:9.1.0016-1ubuntu6) over (2:9.1.0016-1ubuntu2) ...
261s Selecting previously unselected package xdg-user-dirs.
261s Preparing to unpack .../015-xdg-user-dirs_0.18-1_ppc64el.deb ...
261s Unpacking xdg-user-dirs (0.18-1) ...
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261s Unpacking xxd (2:9.1.0016-1ubuntu6) over (2:9.1.0016-1ubuntu2) ...
261s Preparing to unpack .../017-apparmor_4.0.0-beta3-0ubuntu2_ppc64el.deb ...
261s Unpacking apparmor (4.0.0-beta3-0ubuntu2) over (4.0.0~alpha4-0ubuntu1) ...
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262s Preparing to unpack .../019-inetutils-telnet_2%3a2.5-3ubuntu3_ppc64el.deb ...
262s Unpacking inetutils-telnet (2:2.5-3ubuntu3) over (2:2.5-3ubuntu1) ...
262s Preparing to unpack .../020-info_7.1-3build1_ppc64el.deb ...
262s Unpacking info (7.1-3build1) over (7.1-3) ...
262s Preparing to unpack .../021-libusb-1.0-0_2%3a1.0.27-1_ppc64el.deb ...
262s Unpacking libusb-1.0-0:ppc64el (2:1.0.27-1) over (2:1.0.26-1) ...
262s Preparing to unpack .../022-libxmuu1_2%3a1.1.3-3build1_ppc64el.deb ...
262s Unpacking libxmuu1:ppc64el (2:1.1.3-3build1) over (2:1.1.3-3) ...
262s Preparing to unpack .../023-lshw_02.19.git.2021.06.19.996aaad9c7-2build2_ppc64el.deb ...
262s Unpacking lshw (02.19.git.2021.06.19.996aaad9c7-2build2) over (02.19.git.2021.06.19.996aaad9c7-2build1) ...
262s Selecting previously unselected package manpages.
262s Preparing to unpack .../024-manpages_6.05.01-1_all.deb ...
262s Unpacking manpages (6.05.01-1) ...
262s Preparing to unpack .../025-mtr-tiny_0.95-1.1build1_ppc64el.deb ...
262s Unpacking mtr-tiny (0.95-1.1build1) over (0.95-1.1) ...
262s Preparing to unpack .../026-plymouth-theme-ubuntu-text_24.004.60-1ubuntu6_ppc64el.deb ...
262s Unpacking plymouth-theme-ubuntu-text (24.004.60-1ubuntu6) over (24.004.60-1ubuntu3) ...
262s Preparing to unpack .../027-plymouth_24.004.60-1ubuntu6_ppc64el.deb ...
262s Unpacking plymouth (24.004.60-1ubuntu6) over (24.004.60-1ubuntu3) ...
262s Preparing to unpack .../028-telnet_0.17+2.5-3ubuntu3_all.deb ...
262s Unpacking telnet (0.17+2.5-3ubuntu3) over (0.17+2.5-3ubuntu1) ...
262s Preparing to unpack .../029-usb.ids_2024.03.18-1_all.deb ...
262s Unpacking usb.ids (2024.03.18-1) over (2024.01.30-1) ...
262s Preparing to unpack .../030-xz-utils_5.6.0-0.2_ppc64el.deb ...
262s Unpacking xz-utils (5.6.0-0.2) over (5.4.5-0.3) ...
262s Preparing to unpack .../031-libctf0_2.42-4ubuntu1_ppc64el.deb ...
262s Unpacking libctf0:ppc64el (2.42-4ubuntu1) over (2.42-3ubuntu1) ...
262s Preparing to unpack .../032-libctf-nobfd0_2.42-4ubuntu1_ppc64el.deb ...
262s Unpacking libctf-nobfd0:ppc64el (2.42-4ubuntu1) over (2.42-3ubuntu1) ...
262s Preparing to unpack .../033-binutils-powerpc64le-linux-gnu_2.42-4ubuntu1_ppc64el.deb ...
262s Unpacking binutils-powerpc64le-linux-gnu (2.42-4ubuntu1) over (2.42-3ubuntu1) ...
262s Preparing to unpack .../034-libbinutils_2.42-4ubuntu1_ppc64el.deb ...
262s Unpacking libbinutils:ppc64el (2.42-4ubuntu1) over (2.42-3ubuntu1) ...
262s Preparing to unpack .../035-binutils_2.42-4ubuntu1_ppc64el.deb ...
262s Unpacking binutils (2.42-4ubuntu1) over (2.42-3ubuntu1) ...
262s Preparing to unpack .../036-binutils-common_2.42-4ubuntu1_ppc64el.deb ...
262s Unpacking binutils-common:ppc64el (2.42-4ubuntu1) over (2.42-3ubuntu1) ...
262s Preparing to unpack .../037-libsframe1_2.42-4ubuntu1_ppc64el.deb ...
262s Unpacking libsframe1:ppc64el (2.42-4ubuntu1) over (2.42-3ubuntu1) ...
262s Selecting previously unselected package libllvm18:ppc64el.
262s Preparing to unpack .../038-libllvm18_1%3a18.1.2-1ubuntu2_ppc64el.deb ...
262s Unpacking libllvm18:ppc64el (1:18.1.2-1ubuntu2) ...
263s Selecting previously unselected package libclang-cpp18.
263s Preparing to unpack .../039-libclang-cpp18_1%3a18.1.2-1ubuntu2_ppc64el.deb ...
263s Unpacking libclang-cpp18 (1:18.1.2-1ubuntu2) ...
264s Selecting previously unselected package libbpfcc:ppc64el.
264s Preparing to unpack .../040-libbpfcc_0.29.1+ds-1ubuntu4_ppc64el.deb ...
264s Unpacking libbpfcc:ppc64el (0.29.1+ds-1ubuntu4) ...
264s Selecting previously unselected package python3-bpfcc.
264s Preparing to unpack .../041-python3-bpfcc_0.29.1+ds-1ubuntu4_all.deb ...
264s Unpacking python3-bpfcc (0.29.1+ds-1ubuntu4) ...
264s Selecting previously unselected package ieee-data.
264s Preparing to unpack .../042-ieee-data_20220827.1_all.deb ...
264s Unpacking ieee-data (20220827.1) ...
264s Selecting previously unselected package python3-netaddr.
264s Preparing to unpack .../043-python3-netaddr_0.8.0-2ubuntu1_all.deb ...
264s Unpacking python3-netaddr (0.8.0-2ubuntu1) ...
264s Selecting previously unselected package bpfcc-tools.
264s Preparing to unpack .../044-bpfcc-tools_0.29.1+ds-1ubuntu4_all.deb ...
264s Unpacking bpfcc-tools (0.29.1+ds-1ubuntu4) ...
264s Selecting previously unselected package libclang1-18.
264s Preparing to unpack .../045-libclang1-18_1%3a18.1.2-1ubuntu2_ppc64el.deb ...
264s Unpacking libclang1-18 (1:18.1.2-1ubuntu2) ...
264s Selecting previously unselected package libdw1t64:ppc64el.
264s Preparing to unpack .../046-libdw1t64_0.190-1.1build2_ppc64el.deb ...
264s Unpacking libdw1t64:ppc64el (0.190-1.1build2) ...
264s Selecting previously unselected package bpftrace.
264s Preparing to unpack .../047-bpftrace_0.20.2-1ubuntu1_ppc64el.deb ...
264s Unpacking bpftrace (0.20.2-1ubuntu1) ...
264s Preparing to unpack .../048-cryptsetup-bin_2%3a2.7.0-1ubuntu2_ppc64el.deb ...
264s Unpacking cryptsetup-bin (2:2.7.0-1ubuntu2) over (2:2.7.0-1ubuntu1) ...
264s Preparing to unpack .../049-dpkg-dev_1.22.6ubuntu5_all.deb ...
264s Unpacking dpkg-dev (1.22.6ubuntu5) over (1.22.4ubuntu5) ...
264s Preparing to unpack .../050-libdpkg-perl_1.22.6ubuntu5_all.deb ...
264s Unpacking libdpkg-perl (1.22.6ubuntu5) over (1.22.4ubuntu5) ...
264s Selecting previously unselected package fonts-dejavu-mono.
264s Preparing to unpack .../051-fonts-dejavu-mono_2.37-8_all.deb ...
264s Unpacking fonts-dejavu-mono (2.37-8) ...
265s Selecting previously unselected package fonts-dejavu-core.
265s Preparing to unpack .../052-fonts-dejavu-core_2.37-8_all.deb ...
265s Unpacking fonts-dejavu-core (2.37-8) ...
265s Selecting previously unselected package fontconfig-config.
265s Preparing to unpack .../053-fontconfig-config_2.15.0-1.1ubuntu1_ppc64el.deb ...
265s Unpacking fontconfig-config (2.15.0-1.1ubuntu1) ...
265s Preparing to unpack .../054-libprotobuf-c1_1.4.1-1ubuntu3_ppc64el.deb ...
265s Unpacking libprotobuf-c1:ppc64el (1.4.1-1ubuntu3) over (1.4.1-1ubuntu2) ...
265s Preparing to unpack .../055-gnupg-l10n_2.4.4-2ubuntu15_all.deb ...
265s Unpacking gnupg-l10n (2.4.4-2ubuntu15) over (2.4.4-2ubuntu7) ...
265s Preparing to unpack .../056-libibverbs1_50.0-2build1_ppc64el.deb ...
265s Unpacking libibverbs1:ppc64el (50.0-2build1) over (50.0-2) ...
265s Preparing to unpack .../057-ibverbs-providers_50.0-2build1_ppc64el.deb ...
265s Unpacking ibverbs-providers:ppc64el (50.0-2build1) over (50.0-2) ...
265s Preparing to unpack .../058-jq_1.7.1-3_ppc64el.deb ...
265s Unpacking jq (1.7.1-3) over (1.7.1-2) ...
265s Preparing to unpack .../059-libjq1_1.7.1-3_ppc64el.deb ...
265s Unpacking libjq1:ppc64el (1.7.1-3) over (1.7.1-2) ...
265s Selecting previously unselected package libaio1t64:ppc64el.
265s Preparing to unpack .../060-libaio1t64_0.3.113-6_ppc64el.deb ...
265s Unpacking libaio1t64:ppc64el (0.3.113-6) ...
265s Selecting previously unselected package libatm1t64:ppc64el.
265s Preparing to unpack .../061-libatm1t64_1%3a2.5.1-5.1_ppc64el.deb ...
265s Unpacking libatm1t64:ppc64el (1:2.5.1-5.1) ...
265s Selecting previously unselected package libc-dev-bin.
265s Preparing to unpack .../062-libc-dev-bin_2.39-0ubuntu6_ppc64el.deb ...
265s Unpacking libc-dev-bin (2.39-0ubuntu6) ...
265s Selecting previously unselected package libfontconfig1:ppc64el.
265s Preparing to unpack .../063-libfontconfig1_2.15.0-1.1ubuntu1_ppc64el.deb ...
265s Unpacking libfontconfig1:ppc64el (2.15.0-1.1ubuntu1) ...
265s Selecting previously unselected package libjpeg-turbo8:ppc64el.
265s Preparing to unpack .../064-libjpeg-turbo8_2.1.5-2ubuntu1_ppc64el.deb ...
265s Unpacking libjpeg-turbo8:ppc64el (2.1.5-2ubuntu1) ...
265s Selecting previously unselected package libjpeg8:ppc64el.
265s Preparing to unpack .../065-libjpeg8_8c-2ubuntu11_ppc64el.deb ...
265s Unpacking libjpeg8:ppc64el (8c-2ubuntu11) ...
265s Selecting previously unselected package libdeflate0:ppc64el.
265s Preparing to unpack .../066-libdeflate0_1.19-1_ppc64el.deb ...
265s Unpacking libdeflate0:ppc64el (1.19-1) ...
265s Selecting previously unselected package libjbig0:ppc64el.
265s Preparing to unpack .../067-libjbig0_2.1-6.1ubuntu1_ppc64el.deb ...
265s Unpacking libjbig0:ppc64el (2.1-6.1ubuntu1) ...
265s Selecting previously unselected package liblerc4:ppc64el.
265s Preparing to unpack .../068-liblerc4_4.0.0+ds-4ubuntu1_ppc64el.deb ...
265s Unpacking liblerc4:ppc64el (4.0.0+ds-4ubuntu1) ...
265s Selecting previously unselected package libsharpyuv0:ppc64el.
265s Preparing to unpack .../069-libsharpyuv0_1.3.2-0.4build2_ppc64el.deb ...
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265s Selecting previously unselected package libwebp7:ppc64el.
265s Preparing to unpack .../070-libwebp7_1.3.2-0.4build2_ppc64el.deb ...
265s Unpacking libwebp7:ppc64el (1.3.2-0.4build2) ...
265s Selecting previously unselected package libtiff6:ppc64el.
265s Preparing to unpack .../071-libtiff6_4.5.1+git230720-4ubuntu1_ppc64el.deb ...
265s Unpacking libtiff6:ppc64el (4.5.1+git230720-4ubuntu1) ...
265s Selecting previously unselected package libxpm4:ppc64el.
265s Preparing to unpack .../072-libxpm4_1%3a3.5.17-1build1_ppc64el.deb ...
265s Unpacking libxpm4:ppc64el (1:3.5.17-1build1) ...
265s Selecting previously unselected package libgd3:ppc64el.
265s Preparing to unpack .../073-libgd3_2.3.3-9ubuntu3_ppc64el.deb ...
265s Unpacking libgd3:ppc64el (2.3.3-9ubuntu3) ...
265s Selecting previously unselected package libc-devtools.
265s Preparing to unpack .../074-libc-devtools_2.39-0ubuntu6_ppc64el.deb ...
265s Unpacking libc-devtools (2.39-0ubuntu6) ...
265s Selecting previously unselected package linux-libc-dev:ppc64el.
265s Preparing to unpack .../075-linux-libc-dev_6.8.0-20.20_ppc64el.deb ...
265s Unpacking linux-libc-dev:ppc64el (6.8.0-20.20) ...
265s Selecting previously unselected package libcrypt-dev:ppc64el.
265s Preparing to unpack .../076-libcrypt-dev_1%3a4.4.36-4_ppc64el.deb ...
265s Unpacking libcrypt-dev:ppc64el (1:4.4.36-4) ...
265s Selecting previously unselected package rpcsvc-proto.
265s Preparing to unpack .../077-rpcsvc-proto_1.4.2-0ubuntu6_ppc64el.deb ...
265s Unpacking rpcsvc-proto (1.4.2-0ubuntu6) ...
265s Selecting previously unselected package libc6-dev:ppc64el.
265s Preparing to unpack .../078-libc6-dev_2.39-0ubuntu6_ppc64el.deb ...
265s Unpacking libc6-dev:ppc64el (2.39-0ubuntu6) ...
265s Preparing to unpack .../079-libevent-core-2.1-7_2.1.12-stable-9build1_ppc64el.deb ...
265s Unpacking libevent-core-2.1-7:ppc64el (2.1.12-stable-9build1) over (2.1.12-stable-9) ...
266s Preparing to unpack .../080-libftdi1-2_1.5-6build4_ppc64el.deb ...
266s Unpacking libftdi1-2:ppc64el (1.5-6build4) over (1.5-6build3) ...
266s Preparing to unpack .../081-libldap-common_2.6.7+dfsg-1~exp1ubuntu6_all.deb ...
266s Unpacking libldap-common (2.6.7+dfsg-1~exp1ubuntu6) over (2.6.7+dfsg-1~exp1ubuntu1) ...
266s Selecting previously unselected package libunwind8:ppc64el.
266s Preparing to unpack .../082-libunwind8_1.6.2-3_ppc64el.deb ...
266s Unpacking libunwind8:ppc64el (1.6.2-3) ...
266s Selecting previously unselected package linux-modules-6.8.0-20-generic.
266s Preparing to unpack .../083-linux-modules-6.8.0-20-generic_6.8.0-20.20_ppc64el.deb ...
266s Unpacking linux-modules-6.8.0-20-generic (6.8.0-20.20) ...
266s Selecting previously unselected package linux-image-6.8.0-20-generic.
266s Preparing to unpack .../084-linux-image-6.8.0-20-generic_6.8.0-20.20_ppc64el.deb ...
266s Unpacking linux-image-6.8.0-20-generic (6.8.0-20.20) ...
266s Selecting previously unselected package linux-modules-extra-6.8.0-20-generic.
266s Preparing to unpack .../085-linux-modules-extra-6.8.0-20-generic_6.8.0-20.20_ppc64el.deb ...
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268s Unpacking linux-generic (6.8.0-20.20+1) over (6.8.0-11.11+1) ...
268s Preparing to unpack .../087-linux-image-generic_6.8.0-20.20+1_ppc64el.deb ...
268s Unpacking linux-image-generic (6.8.0-20.20+1) over (6.8.0-11.11+1) ...
268s Preparing to unpack .../088-linux-virtual_6.8.0-20.20+1_ppc64el.deb ...
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268s Preparing to unpack .../090-linux-headers-virtual_6.8.0-20.20+1_ppc64el.deb ...
268s Unpacking linux-headers-virtual (6.8.0-20.20+1) over (6.8.0-11.11+1) ...
268s Selecting previously unselected package linux-headers-6.8.0-20.
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272s Unpacking linux-tools-6.8.0-20-generic (6.8.0-20.20) ...
272s Selecting previously unselected package manpages-dev.
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273s Unpacking kpartx (0.9.4-5ubuntu6) over (0.9.4-5ubuntu3) ...
273s Setting up pinentry-curses (1.2.1-3ubuntu4) ...
273s Setting up motd-news-config (13ubuntu8) ...
273s Setting up libtext-iconv-perl:ppc64el (1.7-8build2) ...
273s Setting up libtext-charwidth-perl:ppc64el (0.04-11build2) ...
273s Setting up libsharpyuv0:ppc64el (1.3.2-0.4build2) ...
273s Setting up liburcu8t64:ppc64el (0.14.0-3.1) ...
273s Setting up tcpdump (4.99.4-3ubuntu2) ...
273s Setting up libibverbs1:ppc64el (50.0-2build1) ...
273s Setting up systemd-sysv (255.4-1ubuntu5) ...
273s Setting up ubuntu-kernel-accessories (1.536build1) ...
273s Setting up libapparmor1:ppc64el (4.0.0-beta3-0ubuntu2) ...
273s Setting up libatm1t64:ppc64el (1:2.5.1-5.1) ...
273s Setting up liblerc4:ppc64el (4.0.0+ds-4ubuntu1) ...
273s Setting up libgdbm6t64:ppc64el (1.23-5.1) ...
273s Setting up bsdextrautils (2.39.3-9ubuntu2) ...
273s Setting up libxpm4:ppc64el (1:3.5.17-1build1) ...
273s Setting up libgdbm-compat4t64:ppc64el (1.23-5.1) ...
273s Setting up xdg-user-dirs (0.18-1) ...
273s Setting up ibverbs-providers:ppc64el (50.0-2build1) ...
273s Setting up linux-headers-6.8.0-20 (6.8.0-20.20) ...
273s Setting up libmagic-mgc (1:5.45-3) ...
273s Setting up gawk (1:5.2.1-2build2) ...
273s Setting up libjq1:ppc64el (1.7.1-3) ...
273s Setting up manpages (6.05.01-1) ...
273s Setting up libtirpc-common (1.3.4+ds-1.1) ...
273s Setting up libbrotli1:ppc64el (1.1.0-2build1) ...
273s Setting up libsqlite3-0:ppc64el (3.45.1-1ubuntu1) ...
273s Setting up libsasl2-modules:ppc64el (2.1.28+dfsg1-5ubuntu1) ...
273s Setting up libuv1t64:ppc64el (1.48.0-1.1) ...
273s Setting up libmagic1t64:ppc64el (1:5.45-3) ...
273s Setting up rsyslog (8.2312.0-3ubuntu7) ...
273s info: The user `syslog' is already a member of `adm'.
274s Setting up binutils-common:ppc64el (2.42-4ubuntu1) ...
274s Setting up libpsl5t64:ppc64el (0.21.2-1.1) ...
274s Setting up libnghttp2-14:ppc64el (1.59.0-1build1) ...
274s Setting up libdeflate0:ppc64el (1.19-1) ...
274s Setting up linux-libc-dev:ppc64el (6.8.0-20.20) ...
274s Setting up bc (1.07.1-3ubuntu2) ...
274s Setting up libctf-nobfd0:ppc64el (2.42-4ubuntu1) ...
274s Setting up libnss-systemd:ppc64el (255.4-1ubuntu5) ...
274s Setting up krb5-locales (1.20.1-6ubuntu1) ...
274s Setting up libcom-err2:ppc64el (1.47.0-2.4~exp1ubuntu2) ...
274s Setting up file (1:5.45-3) ...
274s Setting up lshw (02.19.git.2021.06.19.996aaad9c7-2build2) ...
274s Setting up libldap-common (2.6.7+dfsg-1~exp1ubuntu6) ...
274s Setting up libunwind8:ppc64el (1.6.2-3) ...
274s Setting up libprotobuf-c1:ppc64el (1.4.1-1ubuntu3) ...
274s Setting up libjbig0:ppc64el (2.1-6.1ubuntu1) ...
274s Setting up xxd (2:9.1.0016-1ubuntu6) ...
274s Setting up libsframe1:ppc64el (2.42-4ubuntu1) ...
274s Setting up libelf1t64:ppc64el (0.190-1.1build2) ...
274s Setting up libkrb5support0:ppc64el (1.20.1-6ubuntu1) ...
274s Setting up libdw1t64:ppc64el (0.190-1.1build2) ...
274s Setting up linux-headers-6.8.0-20-generic (6.8.0-20.20) ...
274s Setting up eject (2.39.3-9ubuntu2) ...
274s Setting up apparmor (4.0.0-beta3-0ubuntu2) ...
274s Installing new version of config file /etc/apparmor.d/abstractions/authentication ...
274s Installing new version of config file /etc/apparmor.d/abstractions/crypto ...
274s Installing new version of config file /etc/apparmor.d/abstractions/kde-open5 ...
274s Installing new version of config file /etc/apparmor.d/abstractions/openssl ...
274s Installing new version of config file /etc/apparmor.d/code ...
274s Installing new version of config file /etc/apparmor.d/firefox ...
275s Reloading AppArmor profiles 
276s Setting up libglib2.0-0t64:ppc64el (2.79.3-3ubuntu5) ...
276s No schema files found: doing nothing.
276s Setting up libglib2.0-data (2.79.3-3ubuntu5) ...
276s Setting up rpcsvc-proto (1.4.2-0ubuntu6) ...
276s Setting up vim-common (2:9.1.0016-1ubuntu6) ...
276s Setting up gcc-13-base:ppc64el (13.2.0-21ubuntu1) ...
276s Setting up libqrtr-glib0:ppc64el (1.2.2-1ubuntu3) ...
276s Setting up libslang2:ppc64el (2.3.3-3build1) ...
276s Setting up libnvme1t64 (1.8-3) ...
276s Setting up mtr-tiny (0.95-1.1build1) ...
276s Setting up gnupg-l10n (2.4.4-2ubuntu15) ...
276s Setting up librtmp1:ppc64el (2.4+20151223.gitfa8646d.1-2build6) ...
276s Setting up libdbus-1-3:ppc64el (1.14.10-4ubuntu2) ...
276s Setting up xz-utils (5.6.0-0.2) ...
276s Setting up perl-modules-5.38 (5.38.2-3.2) ...
276s Setting up libproc2-0:ppc64el (2:4.0.4-4ubuntu2) ...
276s Setting up fonts-dejavu-mono (2.37-8) ...
276s Setting up libpng16-16t64:ppc64el (1.6.43-3) ...
276s Setting up systemd-timesyncd (255.4-1ubuntu5) ...
276s Setting up libevent-core-2.1-7:ppc64el (2.1.12-stable-9build1) ...
276s Setting up libss2:ppc64el (1.47.0-2.4~exp1ubuntu2) ...
276s Setting up usb.ids (2024.03.18-1) ...
276s Setting up sudo (1.9.15p5-3ubuntu3) ...
276s Setting up fonts-dejavu-core (2.37-8) ...
276s Setting up dhcpcd-base (1:10.0.6-1ubuntu2) ...
276s Setting up gir1.2-glib-2.0:ppc64el (2.79.3-3ubuntu5) ...
276s Setting up libk5crypto3:ppc64el (1.20.1-6ubuntu1) ...
276s Setting up libjpeg-turbo8:ppc64el (2.1.5-2ubuntu1) ...
276s Setting up logsave (1.47.0-2.4~exp1ubuntu2) ...
276s Setting up libwebp7:ppc64el (1.3.2-0.4build2) ...
276s Setting up libfdisk1:ppc64el (2.39.3-9ubuntu2) ...
276s Setting up libdb5.3t64:ppc64el (5.3.28+dfsg2-6) ...
276s Setting up libdevmapper1.02.1:ppc64el (2:1.02.185-3ubuntu2) ...
276s Setting up libaio1t64:ppc64el (0.3.113-6) ...
276s Setting up python-apt-common (2.7.7) ...
276s Setting up mount (2.39.3-9ubuntu2) ...
276s Setting up dmsetup (2:1.02.185-3ubuntu2) ...
276s Setting up uuid-runtime (2.39.3-9ubuntu2) ...
277s uuidd.service is a disabled or a static unit not running, not starting it.
277s Setting up libmm-glib0:ppc64el (1.23.4-0ubuntu1) ...
277s Setting up groff-base (1.23.0-3build1) ...
277s Setting up libcrypt-dev:ppc64el (1:4.4.36-4) ...
277s Setting up libplymouth5:ppc64el (24.004.60-1ubuntu6) ...
277s Setting up dbus-session-bus-common (1.14.10-4ubuntu2) ...
277s Setting up jq (1.7.1-3) ...
277s Setting up procps (2:4.0.4-4ubuntu2) ...
278s Setting up gpgconf (2.4.4-2ubuntu15) ...
278s Setting up libcryptsetup12:ppc64el (2:2.7.0-1ubuntu2) ...
278s Setting up libgirepository-1.0-1:ppc64el (1.79.1-1ubuntu6) ...
278s Setting up libjson-glib-1.0-common (1.8.0-2build1) ...
278s Setting up libkrb5-3:ppc64el (1.20.1-6ubuntu1) ...
278s Setting up libpython3.11-minimal:ppc64el (3.11.8-1build4) ...
278s Setting up libusb-1.0-0:ppc64el (2:1.0.27-1) ...
278s Setting up libperl5.38t64:ppc64el (5.38.2-3.2) ...
278s Setting up tnftp (20230507-2build1) ...
278s Setting up libbinutils:ppc64el (2.42-4ubuntu1) ...
278s Setting up dbus-system-bus-common (1.14.10-4ubuntu2) ...
278s Setting up libfido2-1:ppc64el (1.14.0-1build1) ...
278s Setting up libc-dev-bin (2.39-0ubuntu6) ...
278s Setting up openssl (3.0.13-0ubuntu2) ...
278s Setting up linux-modules-6.8.0-20-generic (6.8.0-20.20) ...
281s Setting up linux-tools-common (6.8.0-20.20) ...
281s Setting up readline-common (8.2-4) ...
281s Setting up libxml2:ppc64el (2.9.14+dfsg-1.3ubuntu2) ...
281s Setting up libxmuu1:ppc64el (2:1.1.3-3build1) ...
281s Setting up dbus-bin (1.14.10-4ubuntu2) ...
281s Setting up info (7.1-3build1) ...
281s Setting up liblocale-gettext-perl (1.07-6ubuntu4) ...
281s Setting up gpg (2.4.4-2ubuntu15) ...
281s Setting up libgudev-1.0-0:ppc64el (1:238-3ubuntu2) ...
281s Setting up libpolkit-gobject-1-0:ppc64el (124-1ubuntu1) ...
281s Setting up libbpf1:ppc64el (1:1.3.0-2build1) ...
281s Setting up libmbim-glib4:ppc64el (1.31.2-0ubuntu2) ...
281s Setting up rsync (3.2.7-1build1) ...
282s rsync.service is a disabled or a static unit not running, not starting it.
282s Setting up libudisks2-0:ppc64el (2.10.1-6) ...
282s Setting up libkmod2:ppc64el (31+20240202-2ubuntu4) ...
282s Setting up bolt (0.9.6-2build1) ...
282s bolt.service is a disabled or a static unit not running, not starting it.
282s Setting up libllvm18:ppc64el (1:18.1.2-1ubuntu2) ...
282s Setting up gnupg-utils (2.4.4-2ubuntu15) ...
282s Setting up initramfs-tools-bin (0.142ubuntu23) ...
282s Setting up libctf0:ppc64el (2.42-4ubuntu1) ...
282s Setting up libjpeg8:ppc64el (8c-2ubuntu11) ...
282s Setting up cryptsetup-bin (2:2.7.0-1ubuntu2) ...
282s Setting up python3.11-minimal (3.11.8-1build4) ...
283s Setting up libclang1-18 (1:18.1.2-1ubuntu2) ...
283s Setting up manpages-dev (6.05.01-1) ...
283s Setting up linux-modules-extra-6.8.0-20-generic (6.8.0-20.20) ...
285s Setting up apt-utils (2.7.14) ...
285s Setting up gpg-agent (2.4.4-2ubuntu15) ...
285s Setting up libpython3.12-stdlib:ppc64el (3.12.2-4build3) ...
285s Setting up wget (1.21.4-1ubuntu2) ...
285s Setting up fontconfig-config (2.15.0-1.1ubuntu1) ...
286s Setting up libxmlb2:ppc64el (0.3.15-1build1) ...
286s Setting up libpython3.11-stdlib:ppc64el (3.11.8-1build4) ...
286s Setting up python3.12 (3.12.2-4build3) ...
287s Setting up gpgsm (2.4.4-2ubuntu15) ...
287s Setting up inetutils-telnet (2:2.5-3ubuntu3) ...
287s Setting up libreiserfscore0t64 (1:3.6.27-7.1) ...
287s Setting up e2fsprogs (1.47.0-2.4~exp1ubuntu2) ...
287s update-initramfs: deferring update (trigger activated)
288s e2scrub_all.service is a disabled or a static unit not running, not starting it.
288s Setting up linux-tools-6.8.0-20 (6.8.0-20.20) ...
288s Setting up libparted2t64:ppc64el (3.6-3.1build2) ...
288s Setting up linux-headers-generic (6.8.0-20.20+1) ...
288s Setting up dbus-daemon (1.14.10-4ubuntu2) ...
288s Setting up libmbim-proxy (1.31.2-0ubuntu2) ...
288s Setting up vim-tiny (2:9.1.0016-1ubuntu6) ...
288s Setting up kmod (31+20240202-2ubuntu4) ...
288s Setting up libnetplan1:ppc64el (1.0-1) ...
288s Setting up man-db (2.12.0-3build4) ...
289s Updating database of manual pages ...
292s man-db.service is a disabled or a static unit not running, not starting it.
292s Setting up fdisk (2.39.3-9ubuntu2) ...
292s Setting up libjson-glib-1.0-0:ppc64el (1.8.0-2build1) ...
292s Setting up libsasl2-modules-db:ppc64el (2.1.28+dfsg1-5ubuntu1) ...
292s Setting up libftdi1-2:ppc64el (1.5-6build4) ...
292s Setting up perl (5.38.2-3.2) ...
292s Setting up libfreetype6:ppc64el (2.13.2+dfsg-1build2) ...
292s Setting up linux-tools-6.8.0-20-generic (6.8.0-20.20) ...
292s Setting up gir1.2-girepository-2.0:ppc64el (1.79.1-1ubuntu6) ...
292s Setting up dbus (1.14.10-4ubuntu2) ...
292s A reboot is required to replace the running dbus-daemon.
292s Please reboot the system when convenient.
293s Setting up shared-mime-info (2.4-1build1) ...
293s Setting up libblockdev-utils3:ppc64el (3.1.0-1build1) ...
293s Setting up libgssapi-krb5-2:ppc64el (1.20.1-6ubuntu1) ...
293s Setting up udev (255.4-1ubuntu5) ...
294s Setting up ftp (20230507-2build1) ...
294s Setting up keyboxd (2.4.4-2ubuntu15) ...
294s Setting up libdpkg-perl (1.22.6ubuntu5) ...
294s Setting up libsasl2-2:ppc64el (2.1.28+dfsg1-5ubuntu1) ...
294s Setting up libssh-4:ppc64el (0.10.6-2build1) ...
294s Setting up libblockdev-nvme3:ppc64el (3.1.0-1build1) ...
294s Setting up libblockdev-fs3:ppc64el (3.1.0-1build1) ...
294s Setting up ieee-data (20220827.1) ...
294s Setting up libtiff6:ppc64el (4.5.1+git230720-4ubuntu1) ...
294s Setting up kpartx (0.9.4-5ubuntu6) ...
294s Setting up libpam-systemd:ppc64el (255.4-1ubuntu5) ...
294s Setting up libpolkit-agent-1-0:ppc64el (124-1ubuntu1) ...
294s Setting up libc6-dev:ppc64el (2.39-0ubuntu6) ...
294s Setting up libgpgme11t64:ppc64el (1.18.0-4.1ubuntu3) ...
294s Setting up libfontconfig1:ppc64el (2.15.0-1.1ubuntu1) ...
294s Setting up binutils-powerpc64le-linux-gnu (2.42-4ubuntu1) ...
294s Setting up netplan-generator (1.0-1) ...
294s Removing 'diversion of /lib/systemd/system-generators/netplan to /lib/systemd/system-generators/netplan.usr-is-merged by netplan-generator'
294s Setting up initramfs-tools-core (0.142ubuntu23) ...
294s Setting up libclang-cpp18 (1:18.1.2-1ubuntu2) ...
294s Setting up libbpfcc:ppc64el (0.29.1+ds-1ubuntu4) ...
294s Setting up libarchive13t64:ppc64el (3.7.2-1.1ubuntu2) ...
294s Setting up libldap2:ppc64el (2.6.7+dfsg-1~exp1ubuntu6) ...
294s Setting up libpython3-stdlib:ppc64el (3.12.2-0ubuntu1) ...
294s Setting up systemd-resolved (255.4-1ubuntu5) ...
295s Setting up python3.11 (3.11.8-1build4) ...
296s Setting up telnet (0.17+2.5-3ubuntu3) ...
296s Setting up initramfs-tools (0.142ubuntu23) ...
296s update-initramfs: deferring update (trigger activated)
296s Setting up libblockdev-mdraid3:ppc64el (3.1.0-1build1) ...
296s Setting up linux-headers-virtual (6.8.0-20.20+1) ...
296s Setting up libcurl4t64:ppc64el (8.5.0-2ubuntu8) ...
296s Setting up bpftrace (0.20.2-1ubuntu1) ...
296s Setting up bind9-libs:ppc64el (1:9.18.24-0ubuntu3) ...
296s Setting up linux-image-6.8.0-20-generic (6.8.0-20.20) ...
298s I: /boot/vmlinux is now a symlink to vmlinux-6.8.0-20-generic
298s I: /boot/initrd.img is now a symlink to initrd.img-6.8.0-20-generic
298s Setting up libtirpc3t64:ppc64el (1.3.4+ds-1.1) ...
298s Setting up e2fsprogs-l10n (1.47.0-2.4~exp1ubuntu2) ...
298s Setting up libblockdev-swap3:ppc64el (3.1.0-1build1) ...
298s Setting up plymouth (24.004.60-1ubuntu6) ...
298s update-initramfs: Generating /boot/initrd.img-6.8.0-11-generic
298s W: No lz4 in /usr/bin:/sbin:/bin, using gzip
304s update-rc.d: warning: start and stop actions are no longer supported; falling back to defaults
305s update-rc.d: warning: start and stop actions are no longer supported; falling back to defaults
305s Setting up iproute2 (6.1.0-1ubuntu5) ...
305s Setting up openssh-client (1:9.6p1-3ubuntu11) ...
305s Setting up libgusb2:ppc64el (0.4.8-1build1) ...
305s Setting up btrfs-progs (6.6.3-1.1build1) ...
305s Setting up libblockdev-loop3:ppc64el (3.1.0-1build1) ...
305s Setting up libcurl3t64-gnutls:ppc64el (8.5.0-2ubuntu8) ...
305s Setting up parted (3.6-3.1build2) ...
305s Setting up libqmi-glib5:ppc64el (1.35.2-0ubuntu1) ...
305s Setting up python3 (3.12.2-0ubuntu1) ...
306s Setting up binutils (2.42-4ubuntu1) ...
306s Setting up libblockdev3:ppc64el (3.1.0-1build1) ...
306s Setting up libjcat1:ppc64el (0.2.0-2build2) ...
306s Setting up multipath-tools (0.9.4-5ubuntu6) ...
306s Setting up dpkg-dev (1.22.6ubuntu5) ...
306s Setting up libblockdev-part3:ppc64el (3.1.0-1build1) ...
306s Setting up dirmngr (2.4.4-2ubuntu15) ...
306s Setting up dbus-user-session (1.14.10-4ubuntu2) ...
306s Setting up plymouth-theme-ubuntu-text (24.004.60-1ubuntu6) ...
306s update-initramfs: deferring update (trigger activated)
306s Setting up python3-cryptography (41.0.7-4build2) ...
307s Setting up python3-gi (3.47.0-3build1) ...
307s Setting up libgd3:ppc64el (2.3.3-9ubuntu3) ...
307s Setting up python3-typing-extensions (4.10.0-1) ...
307s Setting up lsof (4.95.0-1build2) ...
307s Setting up python3-pyrsistent:ppc64el (0.20.0-1build1) ...
307s Setting up python3-netaddr (0.8.0-2ubuntu1) ...
308s Setting up libnsl2:ppc64el (1.3.0-3build2) ...
308s Setting up gnupg (2.4.4-2ubuntu15) ...
308s Setting up python3-netplan (1.0-1) ...
308s Setting up curl (8.5.0-2ubuntu8) ...
308s Setting up libvolume-key1:ppc64el (0.3.12-7build1) ...
308s Setting up linux-image-virtual (6.8.0-20.20+1) ...
308s Setting up bind9-host (1:9.18.24-0ubuntu3) ...
308s Setting up python3-lib2to3 (3.12.2-3ubuntu1.1) ...
308s Setting up python3-bpfcc (0.29.1+ds-1ubuntu4) ...
308s Setting up libc-devtools (2.39-0ubuntu6) ...
308s Setting up python3-pkg-resources (68.1.2-2ubuntu1) ...
308s Setting up python3-distutils (3.12.2-3ubuntu1.1) ...
309s python3.12: can't get files for byte-compilation
309s Setting up openssh-sftp-server (1:9.6p1-3ubuntu11) ...
309s Setting up linux-image-generic (6.8.0-20.20+1) ...
309s Setting up python3-dbus (1.3.2-5build2) ...
309s Setting up python3-setuptools (68.1.2-2ubuntu1) ...
309s Setting up gpg-wks-client (2.4.4-2ubuntu15) ...
309s Setting up openssh-server (1:9.6p1-3ubuntu11) ...
310s Replacing config file /etc/ssh/sshd_config with new version
311s Created symlink /etc/systemd/system/ssh.service.requires/ssh.socket → /usr/lib/systemd/system/ssh.socket.
313s Setting up linux-generic (6.8.0-20.20+1) ...
313s Setting up libblockdev-crypto3:ppc64el (3.1.0-1build1) ...
313s Setting up python3-gdbm:ppc64el (3.12.2-3ubuntu1.1) ...
313s Setting up python3-apt (2.7.7) ...
313s Setting up libfwupd2:ppc64el (1.9.15-2) ...
313s Setting up python3-yaml (6.0.1-2build1) ...
313s Setting up libqmi-proxy (1.35.2-0ubuntu1) ...
313s Setting up netplan.io (1.0-1) ...
313s Setting up linux-virtual (6.8.0-20.20+1) ...
313s Setting up grub-common (2.12-1ubuntu5) ...
314s Setting up bpfcc-tools (0.29.1+ds-1ubuntu4) ...
314s Setting up bind9-dnsutils (1:9.18.24-0ubuntu3) ...
314s Setting up ubuntu-pro-client (31.2.2) ...
316s Setting up fwupd (1.9.15-2) ...
316s fwupd-offline-update.service is a disabled or a static unit not running, not starting it.
316s fwupd-refresh.service is a disabled or a static unit not running, not starting it.
316s fwupd.service is a disabled or a static unit not running, not starting it.
316s Setting up ubuntu-pro-client-l10n (31.2.2) ...
316s Setting up udisks2 (2.10.1-6) ...
317s Setting up grub2-common (2.12-1ubuntu5) ...
317s Setting up grub-ieee1275-bin (2.12-1ubuntu5) ...
317s Setting up grub-ieee1275 (2.12-1ubuntu5) ...
317s Installing for powerpc-ieee1275 platform.
317s Installation finished. No error reported.
317s Sourcing file `/etc/default/grub'
317s Sourcing file `/etc/default/grub.d/50-cloudimg-settings.cfg'
317s Generating grub configuration file ...
317s Found linux image: /boot/vmlinux-6.8.0-20-generic
318s Found linux image: /boot/vmlinux-6.8.0-11-generic
318s Found initrd image: /boot/initrd.img-6.8.0-11-generic
318s Warning: os-prober will not be executed to detect other bootable partitions.
318s Systems on them will not be added to the GRUB boot configuration.
318s Check GRUB_DISABLE_OS_PROBER documentation entry.
318s Adding boot menu entry for UEFI Firmware Settings ...
318s done
318s Processing triggers for ufw (0.36.2-5) ...
318s Processing triggers for systemd (255.4-1ubuntu5) ...
318s Processing triggers for debianutils (5.17) ...
318s Processing triggers for install-info (7.1-3build1) ...
318s Processing triggers for libc-bin (2.39-0ubuntu6) ...
318s Processing triggers for initramfs-tools (0.142ubuntu23) ...
318s update-initramfs: Generating /boot/initrd.img-6.8.0-11-generic
318s W: No lz4 in /usr/bin:/sbin:/bin, using gzip
325s Processing triggers for linux-image-6.8.0-20-generic (6.8.0-20.20) ...
325s /etc/kernel/postinst.d/initramfs-tools:
325s update-initramfs: Generating /boot/initrd.img-6.8.0-20-generic
325s W: No lz4 in /usr/bin:/sbin:/bin, using gzip
330s /etc/kernel/postinst.d/zz-update-grub:
330s Sourcing file `/etc/default/grub'
330s Sourcing file `/etc/default/grub.d/50-cloudimg-settings.cfg'
330s Generating grub configuration file ...
330s Found linux image: /boot/vmlinux-6.8.0-20-generic
330s Found initrd image: /boot/initrd.img-6.8.0-20-generic
330s Found linux image: /boot/vmlinux-6.8.0-11-generic
330s Found initrd image: /boot/initrd.img-6.8.0-11-generic
330s Warning: os-prober will not be executed to detect other bootable partitions.
330s Systems on them will not be added to the GRUB boot configuration.
330s Check GRUB_DISABLE_OS_PROBER documentation entry.
330s Adding boot menu entry for UEFI Firmware Settings ...
330s done
332s Reading package lists...
332s Building dependency tree...
332s Reading state information...
332s The following packages will be REMOVED:
332s   libaio1* libnetplan0* python3-distutils* python3-lib2to3*
332s 0 upgraded, 0 newly installed, 4 to remove and 0 not upgraded.
332s After this operation, 1613 kB disk space will be freed.
332s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 112169 files and directories currently installed.)
332s Removing libaio1:ppc64el (0.3.113-5) ...
332s Removing libnetplan0:ppc64el (0.107.1-3) ...
332s Removing python3-distutils (3.12.2-3ubuntu1.1) ...
332s Removing python3-lib2to3 (3.12.2-3ubuntu1.1) ...
332s Processing triggers for libc-bin (2.39-0ubuntu6) ...
333s autopkgtest [08:08:09]: rebooting testbed after setup commands that affected boot
371s autopkgtest-virt-ssh: WARNING: ssh connection failed. Retrying in 3 seconds...
380s autopkgtest [08:08:56]: testbed running kernel: Linux 6.8.0-20-generic #20-Ubuntu SMP Mon Mar 18 11:46:05 UTC 2024
383s autopkgtest [08:08:59]: @@@@@@@@@@@@@@@@@@@@ apt-source fpga-icestorm
385s Get:1 http://ftpmaster.internal/ubuntu noble/universe fpga-icestorm 0~20230218gitd20a5e9-1 (dsc) [2329 B]
385s Get:2 http://ftpmaster.internal/ubuntu noble/universe fpga-icestorm 0~20230218gitd20a5e9-1 (tar) [432 kB]
385s Get:3 http://ftpmaster.internal/ubuntu noble/universe fpga-icestorm 0~20230218gitd20a5e9-1 (diff) [10.3 kB]
386s gpgv: Signature made Wed Jun 14 23:39:20 2023 UTC
386s gpgv:                using RSA key 57A1BF15B4F6F99B89EDB29FD39481AE1E79ACF7
386s gpgv: Can't check signature: No public key
386s dpkg-source: warning: cannot verify inline signature for ./fpga-icestorm_0~20230218gitd20a5e9-1.dsc: no acceptable signature found
386s autopkgtest [08:09:02]: testing package fpga-icestorm version 0~20230218gitd20a5e9-1
386s autopkgtest [08:09:02]: build not needed
388s autopkgtest [08:09:04]: test can-show-help: preparing testbed
391s Reading package lists...
391s Building dependency tree...
391s Reading state information...
391s Starting pkgProblemResolver with broken count: 0
391s Starting 2 pkgProblemResolver with broken count: 0
391s Done
392s The following additional packages will be installed:
392s   fpga-icestorm fpga-icestorm-chipdb libftdi1 libusb-0.1-4
392s Suggested packages:
392s   nextpnr-ice40 | nextpnr-ice40-qt
392s Recommended packages:
392s   yosys
392s The following NEW packages will be installed:
392s   autopkgtest-satdep fpga-icestorm fpga-icestorm-chipdb libftdi1 libusb-0.1-4
392s 0 upgraded, 5 newly installed, 0 to remove and 0 not upgraded.
392s Need to get 10.8 MB/10.8 MB of archives.
392s After this operation, 116 MB of additional disk space will be used.
392s Get:1 /tmp/autopkgtest.eGJMaA/1-autopkgtest-satdep.deb autopkgtest-satdep ppc64el 0 [716 B]
392s Get:2 http://ftpmaster.internal/ubuntu noble/main ppc64el libusb-0.1-4 ppc64el 2:0.1.12-35 [22.0 kB]
392s Get:3 http://ftpmaster.internal/ubuntu noble/universe ppc64el libftdi1 ppc64el 0.20-4ubuntu2 [18.8 kB]
392s Get:4 http://ftpmaster.internal/ubuntu noble/universe ppc64el fpga-icestorm ppc64el 0~20230218gitd20a5e9-1 [439 kB]
392s Get:5 http://ftpmaster.internal/ubuntu noble/universe ppc64el fpga-icestorm-chipdb all 0~20230218gitd20a5e9-1 [10.3 MB]
395s Fetched 10.8 MB in 3s (3313 kB/s)
395s Selecting previously unselected package libusb-0.1-4:ppc64el.
395s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 111945 files and directories currently installed.)
395s Preparing to unpack .../libusb-0.1-4_2%3a0.1.12-35_ppc64el.deb ...
395s Unpacking libusb-0.1-4:ppc64el (2:0.1.12-35) ...
395s Selecting previously unselected package libftdi1:ppc64el.
395s Preparing to unpack .../libftdi1_0.20-4ubuntu2_ppc64el.deb ...
395s Unpacking libftdi1:ppc64el (0.20-4ubuntu2) ...
395s Selecting previously unselected package fpga-icestorm.
395s Preparing to unpack .../fpga-icestorm_0~20230218gitd20a5e9-1_ppc64el.deb ...
395s Unpacking fpga-icestorm (0~20230218gitd20a5e9-1) ...
395s Selecting previously unselected package fpga-icestorm-chipdb.
395s Preparing to unpack .../fpga-icestorm-chipdb_0~20230218gitd20a5e9-1_all.deb ...
395s Unpacking fpga-icestorm-chipdb (0~20230218gitd20a5e9-1) ...
396s Selecting previously unselected package autopkgtest-satdep.
396s Preparing to unpack .../1-autopkgtest-satdep.deb ...
396s Unpacking autopkgtest-satdep (0) ...
396s Setting up libusb-0.1-4:ppc64el (2:0.1.12-35) ...
396s Setting up fpga-icestorm-chipdb (0~20230218gitd20a5e9-1) ...
396s Setting up libftdi1:ppc64el (0.20-4ubuntu2) ...
396s Setting up fpga-icestorm (0~20230218gitd20a5e9-1) ...
396s Setting up autopkgtest-satdep (0) ...
396s Processing triggers for man-db (2.12.0-3build4) ...
397s Processing triggers for libc-bin (2.39-0ubuntu6) ...
399s (Reading database ... 112036 files and directories currently installed.)
399s Removing autopkgtest-satdep (0) ...
400s autopkgtest [08:09:16]: test can-show-help: [-----------------------
400s Simple programming tool for FTDI-based Lattice iCE programmers.
400s Usage: iceprog [-b|-n|-c] <input file>
400s        iceprog -r|-R<bytes> <output file>
400s        iceprog -S <input file>
400s        iceprog -t
400s 
400s General options:
400s   -d <device string>    use the specified USB device [default: i:0x0403:0x6010 or i:0x0403:0x6014]
400s                           d:<devicenode>               (e.g. d:002/005)
400s                           i:<vendor>:<product>         (e.g. i:0x0403:0x6010)
400s                           i:<vendor>:<product>:<index> (e.g. i:0x0403:0x6010:0)
400s                           s:<vendor>:<product>:<serial-string>
400s   -I [ABCD]             connect to the specified interface on the FTDI chip
400s                           [default: A]
400s   -o <offset in bytes>  start address for read/write [default: 0]
400s                           (append 'k' to the argument for size in kilobytes,
400s                           or 'M' for size in megabytes)
400s   -s                    slow SPI (50 kHz instead of 6 MHz)
400s   -k                    keep flash in powered up state (i.e. skip power down command)
400s   -v                    verbose output
400s   -i [4,32,64]          select erase block size [default: 64k]
400s 
400s Mode of operation:
400s   [default]             write file contents to flash, then verify
400s   -X                    write file contents to flash only
400s   -r                    read first 256 kB from flash and write to file
400s   -R <size in bytes>    read the specified number of bytes from flash
400s                           (append 'k' to the argument for size in kilobytes,
400s                           or 'M' for size in megabytes)
400s   -c                    do not write flash, only verify (`check')
400s   -S                    perform SRAM programming
400s   -t                    just read the flash ID sequence
400s   -Q                    just set the flash QE=1 bit
400s 
400s Erase mode (only meaningful in default mode):
400s   [default]             erase aligned chunks of 64kB in write mode
400s                           This means that some data after the written data (or
400s                           even before when -o is used) may be erased as well.
400s   -b                    bulk erase entire flash before writing
400s   -e <size in bytes>    erase flash as if we were writing that number of bytes
400s   -n                    do not erase flash before writing
400s   -p                    disable write protection before erasing or writing
400s                           This can be useful if flash memory appears to be
400s                           bricked and won't respond to erasing or programming.
400s 
400s Miscellaneous options:
400s       --help            display this help and exit
400s   --                    treat all remaining arguments as filenames
400s 
400s Exit status:
400s   0 on success,
400s   1 if a non-hardware error occurred (e.g., failure to read from or
400s     write to a file, or invoked with invalid options),
400s   2 if communication with the hardware failed (e.g., cannot find the
400s     iCE FTDI USB device),
400s   3 if verification of the data failed.
400s 
400s Notes for iCEstick (iCE40HX-1k devel board):
400s   An unmodified iCEstick can only be programmed via the serial flash.
400s   Direct programming of the SRAM is not supported. For direct SRAM
400s   programming the flash chip and one zero ohm resistor must be desoldered
400s   and the FT2232H SI pin must be connected to the iCE SPI_SI pin, as shown
400s   in this picture:
400s   http://www.clifford.at/gallery/2014-elektronik/IMG_20141115_183838
400s 
400s Notes for the iCE40-HX8K Breakout Board:
400s   Make sure that the jumper settings on the board match the selected
400s   mode (SRAM or FLASH). See the iCE40-HX8K user manual for details.
400s 
400s If you have a bug report, please file an issue on github:
400s   https://github.com/cliffordwolf/icestorm/issues
400s autopkgtest [08:09:16]: test can-show-help: -----------------------]
401s can-show-help        PASS (superficial)
401s autopkgtest [08:09:17]: test can-show-help:  - - - - - - - - - - results - - - - - - - - - -
401s autopkgtest [08:09:17]: test examples-compile: preparing testbed
404s Reading package lists...
404s Building dependency tree...
404s Reading state information...
405s Starting pkgProblemResolver with broken count: 0
405s Starting 2 pkgProblemResolver with broken count: 0
405s Done
405s The following additional packages will be installed:
405s   libboost-filesystem1.83.0 libboost-iostreams1.83.0
405s   libboost-program-options1.83.0 libboost-thread1.83.0 libpython3.12t64
405s   libtcl8.6 nextpnr-ice40 nextpnr-ice40-chipdb python3-click python3-colorama
405s   yosys yosys-abc
405s Suggested packages:
405s   tcl8.6
405s Recommended packages:
405s   xdot
405s The following NEW packages will be installed:
405s   autopkgtest-satdep libboost-filesystem1.83.0 libboost-iostreams1.83.0
405s   libboost-program-options1.83.0 libboost-thread1.83.0 libpython3.12t64
405s   libtcl8.6 nextpnr-ice40 nextpnr-ice40-chipdb python3-click python3-colorama
405s   yosys yosys-abc
405s 0 upgraded, 13 newly installed, 0 to remove and 0 not upgraded.
405s Need to get 64.5 MB/64.5 MB of archives.
405s After this operation, 296 MB of additional disk space will be used.
405s Get:1 /tmp/autopkgtest.eGJMaA/2-autopkgtest-satdep.deb autopkgtest-satdep ppc64el 0 [732 B]
405s Get:2 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libboost-filesystem1.83.0 ppc64el 1.83.0-2.1ubuntu2 [288 kB]
406s Get:3 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libboost-iostreams1.83.0 ppc64el 1.83.0-2.1ubuntu2 [259 kB]
406s Get:4 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libboost-program-options1.83.0 ppc64el 1.83.0-2.1ubuntu2 [328 kB]
406s Get:5 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libboost-thread1.83.0 ppc64el 1.83.0-2.1ubuntu2 [280 kB]
406s Get:6 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libpython3.12t64 ppc64el 3.12.2-4build3 [2551 kB]
406s Get:7 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libtcl8.6 ppc64el 8.6.14+dfsg-1 [1204 kB]
407s Get:8 http://ftpmaster.internal/ubuntu noble-proposed/universe ppc64el nextpnr-ice40-chipdb ppc64el 0.6-3build4 [47.6 MB]
415s Get:9 http://ftpmaster.internal/ubuntu noble-proposed/universe ppc64el nextpnr-ice40 ppc64el 0.6-3build4 [891 kB]
415s Get:10 http://ftpmaster.internal/ubuntu noble/main ppc64el python3-colorama all 0.4.6-4 [32.1 kB]
415s Get:11 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el python3-click all 8.1.6-2 [79.0 kB]
415s Get:12 http://ftpmaster.internal/ubuntu noble-proposed/universe ppc64el yosys-abc ppc64el 0.33-5build1 [7747 kB]
416s Get:13 http://ftpmaster.internal/ubuntu noble-proposed/universe ppc64el yosys ppc64el 0.33-5build1 [3184 kB]
417s Fetched 64.5 MB in 12s (5462 kB/s)
417s Selecting previously unselected package libboost-filesystem1.83.0:ppc64el.
417s (Reading database ... (Reading database ... 5%(Reading database ... 10%(Reading database ... 15%(Reading database ... 20%(Reading database ... 25%(Reading database ... 30%(Reading database ... 35%(Reading database ... 40%(Reading database ... 45%(Reading database ... 50%(Reading database ... 55%(Reading database ... 60%(Reading database ... 65%(Reading database ... 70%(Reading database ... 75%(Reading database ... 80%(Reading database ... 85%(Reading database ... 90%(Reading database ... 95%(Reading database ... 100%(Reading database ... 112036 files and directories currently installed.)
417s Preparing to unpack .../00-libboost-filesystem1.83.0_1.83.0-2.1ubuntu2_ppc64el.deb ...
417s Unpacking libboost-filesystem1.83.0:ppc64el (1.83.0-2.1ubuntu2) ...
417s Selecting previously unselected package libboost-iostreams1.83.0:ppc64el.
417s Preparing to unpack .../01-libboost-iostreams1.83.0_1.83.0-2.1ubuntu2_ppc64el.deb ...
417s Unpacking libboost-iostreams1.83.0:ppc64el (1.83.0-2.1ubuntu2) ...
417s Selecting previously unselected package libboost-program-options1.83.0:ppc64el.
417s Preparing to unpack .../02-libboost-program-options1.83.0_1.83.0-2.1ubuntu2_ppc64el.deb ...
417s Unpacking libboost-program-options1.83.0:ppc64el (1.83.0-2.1ubuntu2) ...
417s Selecting previously unselected package libboost-thread1.83.0:ppc64el.
417s Preparing to unpack .../03-libboost-thread1.83.0_1.83.0-2.1ubuntu2_ppc64el.deb ...
417s Unpacking libboost-thread1.83.0:ppc64el (1.83.0-2.1ubuntu2) ...
417s Selecting previously unselected package libpython3.12t64:ppc64el.
417s Preparing to unpack .../04-libpython3.12t64_3.12.2-4build3_ppc64el.deb ...
417s Unpacking libpython3.12t64:ppc64el (3.12.2-4build3) ...
417s Selecting previously unselected package libtcl8.6:ppc64el.
417s Preparing to unpack .../05-libtcl8.6_8.6.14+dfsg-1_ppc64el.deb ...
417s Unpacking libtcl8.6:ppc64el (8.6.14+dfsg-1) ...
417s Selecting previously unselected package nextpnr-ice40-chipdb.
417s Preparing to unpack .../06-nextpnr-ice40-chipdb_0.6-3build4_ppc64el.deb ...
417s Unpacking nextpnr-ice40-chipdb (0.6-3build4) ...
419s Selecting previously unselected package nextpnr-ice40.
419s Preparing to unpack .../07-nextpnr-ice40_0.6-3build4_ppc64el.deb ...
419s Unpacking nextpnr-ice40 (0.6-3build4) ...
419s Selecting previously unselected package python3-colorama.
419s Preparing to unpack .../08-python3-colorama_0.4.6-4_all.deb ...
419s Unpacking python3-colorama (0.4.6-4) ...
419s Selecting previously unselected package python3-click.
419s Preparing to unpack .../09-python3-click_8.1.6-2_all.deb ...
419s Unpacking python3-click (8.1.6-2) ...
419s Selecting previously unselected package yosys-abc.
419s Preparing to unpack .../10-yosys-abc_0.33-5build1_ppc64el.deb ...
419s Unpacking yosys-abc (0.33-5build1) ...
419s Selecting previously unselected package yosys.
419s Preparing to unpack .../11-yosys_0.33-5build1_ppc64el.deb ...
419s Unpacking yosys (0.33-5build1) ...
419s Selecting previously unselected package autopkgtest-satdep.
419s Preparing to unpack .../12-2-autopkgtest-satdep.deb ...
419s Unpacking autopkgtest-satdep (0) ...
419s Setting up libboost-program-options1.83.0:ppc64el (1.83.0-2.1ubuntu2) ...
419s Setting up python3-colorama (0.4.6-4) ...
419s Setting up nextpnr-ice40-chipdb (0.6-3build4) ...
419s Setting up libboost-thread1.83.0:ppc64el (1.83.0-2.1ubuntu2) ...
420s Setting up yosys-abc (0.33-5build1) ...
420s Setting up libboost-filesystem1.83.0:ppc64el (1.83.0-2.1ubuntu2) ...
420s Setting up python3-click (8.1.6-2) ...
420s Setting up libpython3.12t64:ppc64el (3.12.2-4build3) ...
420s Setting up libboost-iostreams1.83.0:ppc64el (1.83.0-2.1ubuntu2) ...
420s Setting up libtcl8.6:ppc64el (8.6.14+dfsg-1) ...
420s Setting up nextpnr-ice40 (0.6-3build4) ...
420s Setting up yosys (0.33-5build1) ...
420s Setting up autopkgtest-satdep (0) ...
420s Processing triggers for man-db (2.12.0-3build4) ...
420s Processing triggers for libc-bin (2.39-0ubuntu6) ...
422s (Reading database ... 112654 files and directories currently installed.)
422s Removing autopkgtest-satdep (0) ...
424s autopkgtest [08:09:40]: test examples-compile: [-----------------------
424s make: Entering directory '/tmp/autopkgtest.eGJMaA/build.OQp/src/examples/hx8kboard'
424s yosys -p 'synth_ice40 -top top -json example.json' example.v
424s 
424s  /----------------------------------------------------------------------------\
424s  |                                                                            |
424s  |  yosys -- Yosys Open SYnthesis Suite                                       |
424s  |                                                                            |
424s  |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
424s  |                                                                            |
424s  |  Permission to use, copy, modify, and/or distribute this software for any  |
424s  |  purpose with or without fee is hereby granted, provided that the above    |
424s  |  copyright notice and this permission notice appear in all copies.         |
424s  |                                                                            |
424s  |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
424s  |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
424s  |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
424s  |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
424s  |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
424s  |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
424s  |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
424s  |                                                                            |
424s  \----------------------------------------------------------------------------/
424s 
424s  Yosys 0.33 (git sha1 2584903a060)
424s 
424s 
424s -- Parsing `example.v' using frontend ` -vlog2k' --
424s 
424s 1. Executing Verilog-2005 frontend: example.v
424s Parsing Verilog input from `example.v' to AST representation.
424s Storing AST representation for module `$abstract\top'.
424s Successfully finished Verilog frontend.
424s 
424s -- Running command `synth_ice40 -top top -json example.json' --
424s 
424s 2. Executing SYNTH_ICE40 pass.
424s 
424s 2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v
424s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation.
424s Generating RTLIL representation for module `\SB_IO'.
424s Generating RTLIL representation for module `\SB_GB_IO'.
424s Generating RTLIL representation for module `\SB_GB'.
424s Generating RTLIL representation for module `\SB_LUT4'.
424s Generating RTLIL representation for module `\SB_CARRY'.
424s Generating RTLIL representation for module `\SB_DFF'.
424s Generating RTLIL representation for module `\SB_DFFE'.
424s Generating RTLIL representation for module `\SB_DFFSR'.
424s Generating RTLIL representation for module `\SB_DFFR'.
424s Generating RTLIL representation for module `\SB_DFFSS'.
424s Generating RTLIL representation for module `\SB_DFFS'.
424s Generating RTLIL representation for module `\SB_DFFESR'.
424s Generating RTLIL representation for module `\SB_DFFER'.
424s Generating RTLIL representation for module `\SB_DFFESS'.
424s Generating RTLIL representation for module `\SB_DFFES'.
424s Generating RTLIL representation for module `\SB_DFFN'.
424s Generating RTLIL representation for module `\SB_DFFNE'.
424s Generating RTLIL representation for module `\SB_DFFNSR'.
424s Generating RTLIL representation for module `\SB_DFFNR'.
424s Generating RTLIL representation for module `\SB_DFFNSS'.
424s Generating RTLIL representation for module `\SB_DFFNS'.
424s Generating RTLIL representation for module `\SB_DFFNESR'.
424s Generating RTLIL representation for module `\SB_DFFNER'.
424s Generating RTLIL representation for module `\SB_DFFNESS'.
424s Generating RTLIL representation for module `\SB_DFFNES'.
424s Generating RTLIL representation for module `\SB_RAM40_4K'.
424s Generating RTLIL representation for module `\SB_RAM40_4KNR'.
424s Generating RTLIL representation for module `\SB_RAM40_4KNW'.
424s Generating RTLIL representation for module `\SB_RAM40_4KNRNW'.
424s Generating RTLIL representation for module `\ICESTORM_LC'.
424s Generating RTLIL representation for module `\SB_PLL40_CORE'.
424s Generating RTLIL representation for module `\SB_PLL40_PAD'.
424s Generating RTLIL representation for module `\SB_PLL40_2_PAD'.
424s Generating RTLIL representation for module `\SB_PLL40_2F_CORE'.
424s Generating RTLIL representation for module `\SB_PLL40_2F_PAD'.
424s Generating RTLIL representation for module `\SB_WARMBOOT'.
424s Generating RTLIL representation for module `\SB_SPRAM256KA'.
424s Generating RTLIL representation for module `\SB_HFOSC'.
424s Generating RTLIL representation for module `\SB_LFOSC'.
424s Generating RTLIL representation for module `\SB_RGBA_DRV'.
424s Generating RTLIL representation for module `\SB_LED_DRV_CUR'.
424s Generating RTLIL representation for module `\SB_RGB_DRV'.
424s Generating RTLIL representation for module `\SB_I2C'.
424s Generating RTLIL representation for module `\SB_SPI'.
424s Generating RTLIL representation for module `\SB_LEDDA_IP'.
424s Generating RTLIL representation for module `\SB_FILTER_50NS'.
424s Generating RTLIL representation for module `\SB_IO_I3C'.
424s Generating RTLIL representation for module `\SB_IO_OD'.
424s Generating RTLIL representation for module `\SB_MAC16'.
424s Generating RTLIL representation for module `\ICESTORM_RAM'.
424s Successfully finished Verilog frontend.
424s 
424s 2.2. Executing HIERARCHY pass (managing design hierarchy).
424s 
424s 2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\top'.
424s Generating RTLIL representation for module `\top'.
424s 
424s 2.3.1. Analyzing design hierarchy..
424s Top module:  \top
424s 
424s 2.3.2. Analyzing design hierarchy..
424s Top module:  \top
424s Removing unused module `$abstract\top'.
424s Removed 1 unused modules.
424s 
424s 2.4. Executing PROC pass (convert processes to netlists).
424s 
424s 2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
424s Cleaned up 0 empty switches.
424s 
424s 2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
424s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241 in module SB_DFFNES.
424s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234 in module SB_DFFNESS.
424s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230 in module SB_DFFNER.
424s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223 in module SB_DFFNESR.
424s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220 in module SB_DFFNS.
424s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217 in module SB_DFFNSS.
424s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214 in module SB_DFFNR.
424s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211 in module SB_DFFNSR.
424s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203 in module SB_DFFES.
424s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196 in module SB_DFFESS.
424s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192 in module SB_DFFER.
424s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185 in module SB_DFFESR.
424s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182 in module SB_DFFS.
424s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179 in module SB_DFFSS.
424s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176 in module SB_DFFR.
424s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173 in module SB_DFFSR.
424s Removed a total of 0 dead cases.
424s 
424s 2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
424s Removed 8 redundant assignments.
424s Promoted 25 assignments to connections.
424s 
424s 2.4.4. Executing PROC_INIT pass (extract init attributes).
424s Found init rule in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'.
424s   Set init value: \Q = 1'0
424s Found init rule in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'.
424s   Set init value: \Q = 1'0
424s Found init rule in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'.
424s   Set init value: \Q = 1'0
424s Found init rule in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'.
424s   Set init value: \Q = 1'0
424s Found init rule in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'.
424s   Set init value: \Q = 1'0
424s Found init rule in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'.
424s   Set init value: \Q = 1'0
424s Found init rule in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'.
424s   Set init value: \Q = 1'0
424s Found init rule in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'.
424s   Set init value: \Q = 1'0
424s Found init rule in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'.
424s   Set init value: \Q = 1'0
424s Found init rule in `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'.
424s   Set init value: \Q = 1'0
424s Found init rule in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'.
424s   Set init value: \Q = 1'0
424s Found init rule in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'.
424s   Set init value: \Q = 1'0
424s Found init rule in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'.
424s   Set init value: \Q = 1'0
424s Found init rule in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'.
424s   Set init value: \Q = 1'0
424s Found init rule in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'.
424s   Set init value: \Q = 1'0
424s Found init rule in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'.
424s   Set init value: \Q = 1'0
424s Found init rule in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'.
424s   Set init value: \Q = 1'0
424s Found init rule in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'.
424s   Set init value: \Q = 1'0
424s Found init rule in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'.
424s   Set init value: \Q = 1'0
424s Found init rule in `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'.
424s   Set init value: \Q = 1'0
424s Found init rule in `\top.$proc$example.v:16$386'.
424s   Set init value: \counter = 30'000000000000000000000000000000
424s 
424s 2.4.5. Executing PROC_ARST pass (detect async resets in processes).
424s Found async reset \S in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
424s Found async reset \R in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
424s Found async reset \S in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
424s Found async reset \R in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
424s Found async reset \S in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
424s Found async reset \R in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
424s Found async reset \S in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'.
424s Found async reset \R in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'.
424s 
424s 2.4.6. Executing PROC_ROM pass (convert switches to ROMs).
424s Converted 0 switches.
424s <suppressed ~18 debug messages>
424s 
424s 2.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
424s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'.
424s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
424s      1/1: $0\Q[0:0]
424s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'.
424s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
424s      1/1: $0\Q[0:0]
424s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'.
424s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
424s      1/1: $0\Q[0:0]
424s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'.
424s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
424s      1/1: $0\Q[0:0]
424s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'.
424s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
424s      1/1: $0\Q[0:0]
424s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'.
424s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
424s      1/1: $0\Q[0:0]
424s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'.
424s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
424s      1/1: $0\Q[0:0]
424s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'.
424s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'.
424s      1/1: $0\Q[0:0]
424s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'.
424s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'.
424s      1/1: $0\Q[0:0]
424s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'.
424s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'.
424s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'.
424s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
424s      1/1: $0\Q[0:0]
424s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'.
424s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'.
424s      1/1: $0\Q[0:0]
424s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'.
424s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
424s      1/1: $0\Q[0:0]
424s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'.
424s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'.
424s      1/1: $0\Q[0:0]
424s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'.
424s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'.
424s      1/1: $0\Q[0:0]
424s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'.
424s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'.
424s      1/1: $0\Q[0:0]
424s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'.
424s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'.
424s      1/1: $0\Q[0:0]
424s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'.
424s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'.
424s      1/1: $0\Q[0:0]
424s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'.
424s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'.
424s      1/1: $0\Q[0:0]
424s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'.
424s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'.
424s Creating decoders for process `\top.$proc$example.v:16$386'.
424s Creating decoders for process `\top.$proc$example.v:19$381'.
424s 
424s 2.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
424s 
424s 2.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
424s Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
424s   created $adff cell `$procdff$431' with negative edge clock and positive level reset.
424s Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
424s   created $dff cell `$procdff$432' with negative edge clock.
424s Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
424s   created $adff cell `$procdff$433' with negative edge clock and positive level reset.
424s Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
424s   created $dff cell `$procdff$434' with negative edge clock.
424s Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
424s   created $adff cell `$procdff$435' with negative edge clock and positive level reset.
424s Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
424s   created $dff cell `$procdff$436' with negative edge clock.
424s Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
424s   created $adff cell `$procdff$437' with negative edge clock and positive level reset.
424s Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'.
424s   created $dff cell `$procdff$438' with negative edge clock.
424s Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'.
424s   created $dff cell `$procdff$439' with negative edge clock.
424s Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'.
424s   created $dff cell `$procdff$440' with negative edge clock.
424s Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
424s   created $adff cell `$procdff$441' with positive edge clock and positive level reset.
424s Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'.
424s   created $dff cell `$procdff$442' with positive edge clock.
424s Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
424s   created $adff cell `$procdff$443' with positive edge clock and positive level reset.
424s Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'.
424s   created $dff cell `$procdff$444' with positive edge clock.
424s Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'.
424s   created $adff cell `$procdff$445' with positive edge clock and positive level reset.
424s Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'.
424s   created $dff cell `$procdff$446' with positive edge clock.
424s Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'.
424s   created $adff cell `$procdff$447' with positive edge clock and positive level reset.
424s Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'.
424s   created $dff cell `$procdff$448' with positive edge clock.
424s Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'.
424s   created $dff cell `$procdff$449' with positive edge clock.
424s Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'.
424s   created $dff cell `$procdff$450' with positive edge clock.
424s Creating register for signal `\top.\counter' using process `\top.$proc$example.v:19$381'.
424s   created $dff cell `$procdff$451' with positive edge clock.
424s Creating register for signal `\top.\outcnt' using process `\top.$proc$example.v:19$381'.
424s   created $dff cell `$procdff$452' with positive edge clock.
424s 
424s 2.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
424s 
424s 2.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
424s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'.
424s Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
424s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
424s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'.
424s Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
424s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
424s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'.
424s Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
424s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
424s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'.
424s Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
424s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
424s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'.
424s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
424s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'.
424s Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
424s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
424s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'.
424s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
424s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'.
424s Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'.
424s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'.
424s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'.
424s Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'.
424s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'.
424s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'.
424s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'.
424s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'.
424s Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
424s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
424s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'.
424s Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'.
424s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'.
424s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'.
424s Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
424s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
424s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'.
424s Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'.
424s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'.
424s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'.
424s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'.
424s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'.
425s Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'.
425s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'.
425s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'.
425s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'.
425s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'.
425s Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'.
425s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'.
425s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'.
425s Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'.
425s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'.
425s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'.
425s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'.
425s Removing empty process `top.$proc$example.v:16$386'.
425s Removing empty process `top.$proc$example.v:19$381'.
425s Cleaned up 18 empty switches.
425s 
425s 2.4.12. Executing OPT_EXPR pass (perform const folding).
425s Optimizing module top.
425s <suppressed ~2 debug messages>
425s 
425s 2.5. Executing FLATTEN pass (flatten design).
425s 
425s 2.6. Executing TRIBUF pass.
425s 
425s 2.7. Executing DEMINOUT pass (demote inout ports to input or output).
425s 
425s 2.8. Executing OPT_EXPR pass (perform const folding).
425s Optimizing module top.
425s 
425s 2.9. Executing OPT_CLEAN pass (remove unused cells and wires).
425s Finding unused cells or wires in module \top..
425s Removed 0 unused cells and 5 unused wires.
425s <suppressed ~1 debug messages>
425s 
425s 2.10. Executing CHECK pass (checking for obvious problems).
425s Checking module top...
425s Found and reported 0 problems.
425s 
425s 2.11. Executing OPT pass (performing simple optimizations).
425s 
425s 2.11.1. Executing OPT_EXPR pass (perform const folding).
425s Optimizing module top.
425s 
425s 2.11.2. Executing OPT_MERGE pass (detect identical cells).
425s Finding identical cells in module `\top'.
425s Removed a total of 0 cells.
425s 
425s 2.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
425s Running muxtree optimizer on module \top..
425s   Creating internal representation of mux trees.
425s   No muxes found in this module.
425s Removed 0 multiplexer ports.
425s 
425s 2.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
425s   Optimizing cells in module \top.
425s Performed a total of 0 changes.
425s 
425s 2.11.5. Executing OPT_MERGE pass (detect identical cells).
425s Finding identical cells in module `\top'.
425s Removed a total of 0 cells.
425s 
425s 2.11.6. Executing OPT_DFF pass (perform DFF optimizations).
425s 
425s 2.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
425s Finding unused cells or wires in module \top..
425s 
425s 2.11.8. Executing OPT_EXPR pass (perform const folding).
425s Optimizing module top.
425s 
425s 2.11.9. Finished OPT passes. (There is nothing left to do.)
425s 
425s 2.12. Executing FSM pass (extract and optimize FSM).
425s 
425s 2.12.1. Executing FSM_DETECT pass (finding FSMs in design).
425s 
425s 2.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).
425s 
425s 2.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).
425s 
425s 2.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
425s Finding unused cells or wires in module \top..
425s 
425s 2.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).
425s 
425s 2.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
425s 
425s 2.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
425s 
425s 2.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
425s 
425s 2.13. Executing OPT pass (performing simple optimizations).
425s 
425s 2.13.1. Executing OPT_EXPR pass (perform const folding).
425s Optimizing module top.
425s 
425s 2.13.2. Executing OPT_MERGE pass (detect identical cells).
425s Finding identical cells in module `\top'.
425s Removed a total of 0 cells.
425s 
425s 2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
425s Running muxtree optimizer on module \top..
425s   Creating internal representation of mux trees.
425s   No muxes found in this module.
425s Removed 0 multiplexer ports.
425s 
425s 2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
425s   Optimizing cells in module \top.
425s Performed a total of 0 changes.
425s 
425s 2.13.5. Executing OPT_MERGE pass (detect identical cells).
425s Finding identical cells in module `\top'.
425s Removed a total of 0 cells.
425s 
425s 2.13.6. Executing OPT_DFF pass (perform DFF optimizations).
425s 
425s 2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
425s Finding unused cells or wires in module \top..
425s 
425s 2.13.8. Executing OPT_EXPR pass (perform const folding).
425s Optimizing module top.
425s 
425s 2.13.9. Finished OPT passes. (There is nothing left to do.)
425s 
425s 2.14. Executing WREDUCE pass (reducing word size of cells).
425s Removed top 31 bits (of 32) from port B of cell top.$add$example.v:20$382 ($add).
425s Removed top 2 bits (of 32) from port Y of cell top.$add$example.v:20$382 ($add).
425s Removed top 1 bits (of 8) from port B of cell top.$xor$example.v:24$385 ($xor).
425s 
425s 2.15. Executing PEEPOPT pass (run peephole optimizers).
425s 
425s 2.16. Executing OPT_CLEAN pass (remove unused cells and wires).
425s Finding unused cells or wires in module \top..
425s Removed 0 unused cells and 1 unused wires.
425s <suppressed ~1 debug messages>
425s 
425s 2.17. Executing SHARE pass (SAT-based resource sharing).
425s 
425s 2.18. Executing TECHMAP pass (map to technology primitives).
425s 
425s 2.18.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v
425s Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation.
425s Generating RTLIL representation for module `\_90_lut_cmp_'.
425s Successfully finished Verilog frontend.
425s 
425s 2.18.2. Continuing TECHMAP pass.
425s No more expansions possible.
425s <suppressed ~6 debug messages>
425s 
425s 2.19. Executing OPT_EXPR pass (perform const folding).
425s Optimizing module top.
425s 
425s 2.20. Executing OPT_CLEAN pass (remove unused cells and wires).
425s Finding unused cells or wires in module \top..
425s 
425s 2.21. Executing ALUMACC pass (create $alu and $macc cells).
425s Extracting $alu and $macc cells in module top:
425s   creating $macc model for $add$example.v:20$382 ($add).
425s   creating $alu model for $macc $add$example.v:20$382.
425s   creating $alu cell for $add$example.v:20$382: $auto$alumacc.cc:485:replace_alu$454
425s   created 1 $alu and 0 $macc cells.
425s 
425s 2.22. Executing OPT pass (performing simple optimizations).
425s 
425s 2.22.1. Executing OPT_EXPR pass (perform const folding).
425s Optimizing module top.
425s 
425s 2.22.2. Executing OPT_MERGE pass (detect identical cells).
425s Finding identical cells in module `\top'.
425s Removed a total of 0 cells.
425s 
425s 2.22.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
425s Running muxtree optimizer on module \top..
425s   Creating internal representation of mux trees.
425s   No muxes found in this module.
425s Removed 0 multiplexer ports.
425s 
425s 2.22.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
425s   Optimizing cells in module \top.
425s Performed a total of 0 changes.
425s 
425s 2.22.5. Executing OPT_MERGE pass (detect identical cells).
425s Finding identical cells in module `\top'.
425s Removed a total of 0 cells.
425s 
425s 2.22.6. Executing OPT_DFF pass (perform DFF optimizations).
425s 
425s 2.22.7. Executing OPT_CLEAN pass (remove unused cells and wires).
425s Finding unused cells or wires in module \top..
425s 
425s 2.22.8. Executing OPT_EXPR pass (perform const folding).
425s Optimizing module top.
425s 
425s 2.22.9. Finished OPT passes. (There is nothing left to do.)
425s 
425s 2.23. Executing MEMORY pass.
425s 
425s 2.23.1. Executing OPT_MEM pass (optimize memories).
425s Performed a total of 0 transformations.
425s 
425s 2.23.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
425s Performed a total of 0 transformations.
425s 
425s 2.23.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
425s 
425s 2.23.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
425s 
425s 2.23.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
425s 
425s 2.23.6. Executing OPT_CLEAN pass (remove unused cells and wires).
425s Finding unused cells or wires in module \top..
425s 
425s 2.23.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
425s 
425s 2.23.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
425s Performed a total of 0 transformations.
425s 
425s 2.23.9. Executing OPT_CLEAN pass (remove unused cells and wires).
425s Finding unused cells or wires in module \top..
425s 
425s 2.23.10. Executing MEMORY_COLLECT pass (generating $mem cells).
425s 
425s 2.24. Executing OPT_CLEAN pass (remove unused cells and wires).
425s Finding unused cells or wires in module \top..
425s 
425s 2.25. Executing MEMORY_LIBMAP pass (mapping memories to cells).
425s 
425s 2.26. Executing TECHMAP pass (map to technology primitives).
425s 
425s 2.26.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v
425s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation.
425s Generating RTLIL representation for module `\$__ICE40_RAM4K_'.
425s Successfully finished Verilog frontend.
425s 
425s 2.26.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/spram_map.v
425s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/spram_map.v' to AST representation.
425s Generating RTLIL representation for module `\$__ICE40_SPRAM_'.
425s Successfully finished Verilog frontend.
425s 
425s 2.26.3. Continuing TECHMAP pass.
425s No more expansions possible.
425s <suppressed ~4 debug messages>
425s 
425s 2.27. Executing ICE40_BRAMINIT pass.
425s 
425s 2.28. Executing OPT pass (performing simple optimizations).
425s 
425s 2.28.1. Executing OPT_EXPR pass (perform const folding).
425s Optimizing module top.
425s <suppressed ~5 debug messages>
425s 
425s 2.28.2. Executing OPT_MERGE pass (detect identical cells).
425s Finding identical cells in module `\top'.
425s Removed a total of 0 cells.
425s 
425s 2.28.3. Executing OPT_DFF pass (perform DFF optimizations).
425s 
425s 2.28.4. Executing OPT_CLEAN pass (remove unused cells and wires).
425s Finding unused cells or wires in module \top..
425s Removed 0 unused cells and 2 unused wires.
425s <suppressed ~1 debug messages>
425s 
425s 2.28.5. Finished fast OPT passes.
425s 
425s 2.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
425s 
425s 2.30. Executing OPT pass (performing simple optimizations).
425s 
425s 2.30.1. Executing OPT_EXPR pass (perform const folding).
425s Optimizing module top.
425s 
425s 2.30.2. Executing OPT_MERGE pass (detect identical cells).
425s Finding identical cells in module `\top'.
425s Removed a total of 0 cells.
425s 
425s 2.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
425s Running muxtree optimizer on module \top..
425s   Creating internal representation of mux trees.
425s   No muxes found in this module.
425s Removed 0 multiplexer ports.
425s 
425s 2.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
425s   Optimizing cells in module \top.
425s Performed a total of 0 changes.
425s 
425s 2.30.5. Executing OPT_MERGE pass (detect identical cells).
425s Finding identical cells in module `\top'.
425s Removed a total of 0 cells.
425s 
425s 2.30.6. Executing OPT_DFF pass (perform DFF optimizations).
425s 
425s 2.30.7. Executing OPT_CLEAN pass (remove unused cells and wires).
425s Finding unused cells or wires in module \top..
425s 
425s 2.30.8. Executing OPT_EXPR pass (perform const folding).
425s Optimizing module top.
425s 
425s 2.30.9. Finished OPT passes. (There is nothing left to do.)
425s 
425s 2.31. Executing ICE40_WRAPCARRY pass (wrap carries).
425s 
425s 2.32. Executing TECHMAP pass (map to technology primitives).
425s 
425s 2.32.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v
425s Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation.
425s Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
425s Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
425s Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
425s Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
425s Generating RTLIL representation for module `\_90_simplemap_various'.
425s Generating RTLIL representation for module `\_90_simplemap_registers'.
425s Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
425s Generating RTLIL representation for module `\_90_shift_shiftx'.
425s Generating RTLIL representation for module `\_90_fa'.
425s Generating RTLIL representation for module `\_90_lcu'.
425s Generating RTLIL representation for module `\_90_alu'.
425s Generating RTLIL representation for module `\_90_macc'.
425s Generating RTLIL representation for module `\_90_alumacc'.
425s Generating RTLIL representation for module `\$__div_mod_u'.
425s Generating RTLIL representation for module `\$__div_mod_trunc'.
425s Generating RTLIL representation for module `\_90_div'.
425s Generating RTLIL representation for module `\_90_mod'.
425s Generating RTLIL representation for module `\$__div_mod_floor'.
425s Generating RTLIL representation for module `\_90_divfloor'.
425s Generating RTLIL representation for module `\_90_modfloor'.
425s Generating RTLIL representation for module `\_90_pow'.
425s Generating RTLIL representation for module `\_90_pmux'.
425s Generating RTLIL representation for module `\_90_demux'.
425s Generating RTLIL representation for module `\_90_lut'.
425s Successfully finished Verilog frontend.
425s 
425s 2.32.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v
425s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation.
425s Generating RTLIL representation for module `\_80_ice40_alu'.
425s Successfully finished Verilog frontend.
425s 
425s 2.32.3. Continuing TECHMAP pass.
425s Using template $paramod$44a13d10af618e7fbe7b9aad2f6151ffcee1e2fa\_80_ice40_alu for cells of type $alu.
425s Using extmapper simplemap for cells of type $xor.
425s Using extmapper simplemap for cells of type $dff.
425s Using extmapper simplemap for cells of type $mux.
425s Using extmapper simplemap for cells of type $not.
425s Using extmapper simplemap for cells of type $pos.
425s No more expansions possible.
425s <suppressed ~101 debug messages>
425s 
425s 2.33. Executing OPT pass (performing simple optimizations).
425s 
425s 2.33.1. Executing OPT_EXPR pass (perform const folding).
425s Optimizing module top.
425s <suppressed ~60 debug messages>
425s 
425s 2.33.2. Executing OPT_MERGE pass (detect identical cells).
425s Finding identical cells in module `\top'.
425s <suppressed ~3 debug messages>
425s Removed a total of 1 cells.
425s 
425s 2.33.3. Executing OPT_DFF pass (perform DFF optimizations).
425s 
425s 2.33.4. Executing OPT_CLEAN pass (remove unused cells and wires).
425s Finding unused cells or wires in module \top..
425s Removed 30 unused cells and 17 unused wires.
425s <suppressed ~31 debug messages>
425s 
425s 2.33.5. Finished fast OPT passes.
425s 
425s 2.34. Executing ICE40_OPT pass (performing simple optimizations).
425s 
425s 2.34.1. Running ICE40 specific optimizations.
425s Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$454.slice[0].carry: CO=\counter [0]
425s 
425s 2.34.2. Executing OPT_EXPR pass (perform const folding).
425s Optimizing module top.
425s 
425s 2.34.3. Executing OPT_MERGE pass (detect identical cells).
425s Finding identical cells in module `\top'.
425s Removed a total of 0 cells.
425s 
425s 2.34.4. Executing OPT_DFF pass (perform DFF optimizations).
425s 
425s 2.34.5. Executing OPT_CLEAN pass (remove unused cells and wires).
425s Finding unused cells or wires in module \top..
425s 
425s 2.34.6. Rerunning OPT passes. (Removed registers in this run.)
425s 
425s 2.34.7. Running ICE40 specific optimizations.
425s 
425s 2.34.8. Executing OPT_EXPR pass (perform const folding).
425s Optimizing module top.
425s 
425s 2.34.9. Executing OPT_MERGE pass (detect identical cells).
425s Finding identical cells in module `\top'.
425s Removed a total of 0 cells.
425s 
425s 2.34.10. Executing OPT_DFF pass (perform DFF optimizations).
425s 
425s 2.34.11. Executing OPT_CLEAN pass (remove unused cells and wires).
425s Finding unused cells or wires in module \top..
425s 
425s 2.34.12. Finished OPT passes. (There is nothing left to do.)
425s 
425s 2.35. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
425s 
425s 2.36. Executing TECHMAP pass (map to technology primitives).
425s 
425s 2.36.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v
425s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation.
425s Generating RTLIL representation for module `\$_DFF_N_'.
425s Generating RTLIL representation for module `\$_DFF_P_'.
425s Generating RTLIL representation for module `\$_DFFE_NP_'.
425s Generating RTLIL representation for module `\$_DFFE_PP_'.
425s Generating RTLIL representation for module `\$_DFF_NP0_'.
425s Generating RTLIL representation for module `\$_DFF_NP1_'.
425s Generating RTLIL representation for module `\$_DFF_PP0_'.
425s Generating RTLIL representation for module `\$_DFF_PP1_'.
425s Generating RTLIL representation for module `\$_DFFE_NP0P_'.
425s Generating RTLIL representation for module `\$_DFFE_NP1P_'.
425s Generating RTLIL representation for module `\$_DFFE_PP0P_'.
425s Generating RTLIL representation for module `\$_DFFE_PP1P_'.
425s Generating RTLIL representation for module `\$_SDFF_NP0_'.
425s Generating RTLIL representation for module `\$_SDFF_NP1_'.
425s Generating RTLIL representation for module `\$_SDFF_PP0_'.
425s Generating RTLIL representation for module `\$_SDFF_PP1_'.
425s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
425s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
425s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
425s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
425s Successfully finished Verilog frontend.
425s 
425s 2.36.2. Continuing TECHMAP pass.
425s Using template \$_DFF_P_ for cells of type $_DFF_P_.
425s No more expansions possible.
425s <suppressed ~60 debug messages>
425s 
425s 2.37. Executing OPT_EXPR pass (perform const folding).
425s Optimizing module top.
425s 
425s 2.38. Executing SIMPLEMAP pass (map simple cells to gate primitives).
425s Mapping top.$auto$alumacc.cc:485:replace_alu$454.slice[0].carry ($lut).
425s 
425s 2.39. Executing ICE40_OPT pass (performing simple optimizations).
425s 
425s 2.39.1. Running ICE40 specific optimizations.
425s 
425s 2.39.2. Executing OPT_EXPR pass (perform const folding).
425s Optimizing module top.
425s <suppressed ~14 debug messages>
425s 
425s 2.39.3. Executing OPT_MERGE pass (detect identical cells).
425s Finding identical cells in module `\top'.
425s Removed a total of 0 cells.
425s 
425s 2.39.4. Executing OPT_DFF pass (perform DFF optimizations).
425s 
425s 2.39.5. Executing OPT_CLEAN pass (remove unused cells and wires).
425s Finding unused cells or wires in module \top..
425s Removed 0 unused cells and 156 unused wires.
425s <suppressed ~1 debug messages>
425s 
425s 2.39.6. Rerunning OPT passes. (Removed registers in this run.)
425s 
425s 2.39.7. Running ICE40 specific optimizations.
425s 
425s 2.39.8. Executing OPT_EXPR pass (perform const folding).
425s Optimizing module top.
425s 
425s 2.39.9. Executing OPT_MERGE pass (detect identical cells).
425s Finding identical cells in module `\top'.
425s Removed a total of 0 cells.
425s 
425s 2.39.10. Executing OPT_DFF pass (perform DFF optimizations).
425s 
425s 2.39.11. Executing OPT_CLEAN pass (remove unused cells and wires).
425s Finding unused cells or wires in module \top..
425s 
425s 2.39.12. Finished OPT passes. (There is nothing left to do.)
425s 
425s 2.40. Executing TECHMAP pass (map to technology primitives).
425s 
425s 2.40.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v
425s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation.
425s Generating RTLIL representation for module `\$_DLATCH_N_'.
425s Generating RTLIL representation for module `\$_DLATCH_P_'.
425s Successfully finished Verilog frontend.
425s 
425s 2.40.2. Continuing TECHMAP pass.
425s No more expansions possible.
425s <suppressed ~4 debug messages>
425s 
425s 2.41. Executing ABC pass (technology mapping using ABC).
425s 
425s 2.41.1. Extracting gate netlist of module `\top' to `<abc-temp-dir>/input.blif'..
425s Extracted 8 gates and 17 wires to a netlist network with 9 inputs and 8 outputs.
425s 
425s 2.41.1.1. Executing ABC.
425s Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
425s ABC: ABC command line: "source <abc-temp-dir>/abc.script".
425s ABC: 
425s ABC: + read_blif <abc-temp-dir>/input.blif 
425s ABC: + read_lut <abc-temp-dir>/lutdefs.txt 
425s ABC: + strash 
425s ABC: + &get -n 
425s ABC: + &fraig -x 
425s ABC: + &put 
425s ABC: + scorr 
425s ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
425s ABC: + dc2 
425s ABC: + dretime 
425s ABC: + strash 
425s ABC: + dch -f 
425s ABC: + if 
425s ABC: + mfs2 
425s ABC: + lutpack -S 1 
425s ABC: + dress <abc-temp-dir>/input.blif 
425s ABC: Total number of equiv classes                =       9.
425s ABC: Participating nodes from both networks       =      16.
425s ABC: Participating nodes from the first network   =       8. (  88.89 % of nodes)
425s ABC: Participating nodes from the second network  =       8. (  88.89 % of nodes)
425s ABC: Node pairs (any polarity)                    =       8. (  88.89 % of names can be moved)
425s ABC: Node pairs (same polarity)                   =       8. (  88.89 % of names can be moved)
425s ABC: Total runtime =     0.00 sec
425s ABC: + write_blif <abc-temp-dir>/output.blif 
425s 
425s 2.41.1.2. Re-integrating ABC results.
425s ABC RESULTS:              $lut cells:        8
425s ABC RESULTS:        internal signals:        0
425s ABC RESULTS:           input signals:        9
425s ABC RESULTS:          output signals:        8
425s Removing temp directory.
425s 
425s 2.42. Executing ICE40_WRAPCARRY pass (wrap carries).
425s 
425s 2.43. Executing TECHMAP pass (map to technology primitives).
425s 
425s 2.43.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v
425s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation.
425s Generating RTLIL representation for module `\$_DFF_N_'.
425s Generating RTLIL representation for module `\$_DFF_P_'.
425s Generating RTLIL representation for module `\$_DFFE_NP_'.
425s Generating RTLIL representation for module `\$_DFFE_PP_'.
425s Generating RTLIL representation for module `\$_DFF_NP0_'.
425s Generating RTLIL representation for module `\$_DFF_NP1_'.
425s Generating RTLIL representation for module `\$_DFF_PP0_'.
425s Generating RTLIL representation for module `\$_DFF_PP1_'.
425s Generating RTLIL representation for module `\$_DFFE_NP0P_'.
425s Generating RTLIL representation for module `\$_DFFE_NP1P_'.
425s Generating RTLIL representation for module `\$_DFFE_PP0P_'.
425s Generating RTLIL representation for module `\$_DFFE_PP1P_'.
425s Generating RTLIL representation for module `\$_SDFF_NP0_'.
425s Generating RTLIL representation for module `\$_SDFF_NP1_'.
425s Generating RTLIL representation for module `\$_SDFF_PP0_'.
425s Generating RTLIL representation for module `\$_SDFF_PP1_'.
425s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
425s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
425s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
425s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
425s Successfully finished Verilog frontend.
425s 
425s 2.43.2. Continuing TECHMAP pass.
425s No more expansions possible.
425s <suppressed ~22 debug messages>
425s Removed 1 unused cells and 18 unused wires.
425s 
425s 2.44. Executing OPT_LUT pass (optimize LUTs).
425s Discovering LUTs.
425s Number of LUTs:       37
425s   1-LUT                1
425s   2-LUT                8
425s   3-LUT               28
425s   with \SB_CARRY    (#0)   28
425s   with \SB_CARRY    (#1)   28
425s 
425s Eliminating LUTs.
425s Number of LUTs:       37
425s   1-LUT                1
425s   2-LUT                8
425s   3-LUT               28
425s   with \SB_CARRY    (#0)   28
425s   with \SB_CARRY    (#1)   28
425s 
425s Combining LUTs.
425s Number of LUTs:       37
425s   1-LUT                1
425s   2-LUT                8
425s   3-LUT               28
425s   with \SB_CARRY    (#0)   28
425s   with \SB_CARRY    (#1)   28
425s 
425s Eliminated 0 LUTs.
425s Combined 0 LUTs.
425s <suppressed ~130 debug messages>
425s 
425s 2.45. Executing TECHMAP pass (map to technology primitives).
425s 
425s 2.45.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v
425s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation.
425s Generating RTLIL representation for module `\$lut'.
425s Successfully finished Verilog frontend.
425s 
425s 2.45.2. Continuing TECHMAP pass.
425s Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut.
425s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
425s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
425s No more expansions possible.
425s <suppressed ~79 debug messages>
425s Removed 0 unused cells and 74 unused wires.
425s 
425s 2.46. Executing AUTONAME pass.
425s Renamed 163 objects in module top (4 iterations).
425s <suppressed ~105 debug messages>
425s 
425s 2.47. Executing HIERARCHY pass (managing design hierarchy).
425s 
425s 2.47.1. Analyzing design hierarchy..
425s Top module:  \top
425s 
425s 2.47.2. Analyzing design hierarchy..
425s Top module:  \top
425s Removed 0 unused modules.
425s 
425s 2.48. Printing statistics.
425s 
425s === top ===
425s 
425s    Number of wires:                 13
425s    Number of wire bits:            107
425s    Number of public wires:          13
425s    Number of public wire bits:     107
425s    Number of memories:               0
425s    Number of memory bits:            0
425s    Number of processes:              0
425s    Number of cells:                103
425s      SB_CARRY                       28
425s      SB_DFF                         38
425s      SB_LUT4                        37
425s 
425s 2.49. Executing CHECK pass (checking for obvious problems).
425s Checking module top...
425s Found and reported 0 problems.
425s 
425s 2.50. Executing JSON backend.
425s 
425s End of script. Logfile hash: fe179aca88, CPU: user 0.96s system 0.01s, MEM: 20.00 MB peak
425s Yosys 0.33 (git sha1 2584903a060)
425s Time spent: 65% 13x read_verilog (0 sec), 7% 1x synth_ice40 (0 sec), ...
425s nextpnr-ice40 --hx8k --package ct256 --asc example.asc --pcf hx8kboard.pcf --json example.json
425s Info: constrained 'LED0' to bel 'X7/Y33/io1'
425s Info: constrained 'LED1' to bel 'X6/Y33/io1'
425s Info: constrained 'LED2' to bel 'X5/Y33/io1'
425s Info: constrained 'LED3' to bel 'X4/Y33/io1'
425s Info: constrained 'LED4' to bel 'X4/Y33/io0'
425s Info: constrained 'LED5' to bel 'X3/Y33/io1'
425s Info: constrained 'LED6' to bel 'X3/Y33/io0'
425s Info: constrained 'LED7' to bel 'X1/Y33/io0'
425s Info: constrained 'clk' to bel 'X0/Y16/io1'
425s 
425s Info: Packing constants..
425s Info: Packing IOs..
425s Info: Packing LUT-FFs..
425s Info:        7 LCs used as LUT4 only
425s Info:       30 LCs used as LUT4 and DFF
425s Info: Packing non-LUT FFs..
425s Info:        8 LCs used as DFF only
425s Info: Packing carries..
425s Info:        0 LCs used as CARRY only
425s Info: Packing indirect carry+LUT pairs...
425s Info:        0 LUTs merged into carry LCs
425s Info: Packing RAMs..
425s Info: Placing PLLs..
425s Info: Packing special functions..
425s Info: Packing PLLs..
425s Info: Promoting globals..
425s Info: promoting clk$SB_IO_IN (fanout 38)
425s Info: Constraining chains...
425s Info:        1 LCs used to legalise carry chains.
425s Info: Checksum: 0x74fa9ee4
425s 
425s Info: Annotating ports with timing budgets for target frequency 12.00 MHz
425s Info: Checksum: 0x4df74e96
425s 
425s Info: Device utilisation:
425s Info: 	         ICESTORM_LC:    48/ 7680     0%
425s Info: 	        ICESTORM_RAM:     0/   32     0%
425s Info: 	               SB_IO:     9/  256     3%
425s Info: 	               SB_GB:     1/    8    12%
425s Info: 	        ICESTORM_PLL:     0/    2     0%
425s Info: 	         SB_WARMBOOT:     0/    1     0%
425s 
425s Info: Placed 9 cells based on constraints.
425s Info: Creating initial analytic placement for 18 cells, random placement wirelen = 571.
425s Info:     at initial placer iter 0, wirelen = 26
425s Info:     at initial placer iter 1, wirelen = 21
425s Info:     at initial placer iter 2, wirelen = 20
425s Info:     at initial placer iter 3, wirelen = 21
425s Info: Running main analytical placer, max placement attempts per cell = 10000.
425s Info:     at iteration #1, type ICESTORM_LC: wirelen solved = 20, spread = 50, legal = 50; time = 0.00s
425s Info:     at iteration #1, type SB_GB: wirelen solved = 50, spread = 50, legal = 50; time = 0.00s
425s Info:     at iteration #1, type ALL: wirelen solved = 20, spread = 45, legal = 49; time = 0.00s
425s Info:     at iteration #2, type ICESTORM_LC: wirelen solved = 32, spread = 47, legal = 51; time = 0.00s
425s Info:     at iteration #2, type SB_GB: wirelen solved = 51, spread = 51, legal = 51; time = 0.00s
425s Info:     at iteration #2, type ALL: wirelen solved = 31, spread = 44, legal = 48; time = 0.00s
425s Info:     at iteration #3, type ICESTORM_LC: wirelen solved = 29, spread = 58, legal = 62; time = 0.00s
425s Info:     at iteration #3, type SB_GB: wirelen solved = 62, spread = 62, legal = 62; time = 0.00s
425s Info:     at iteration #3, type ALL: wirelen solved = 27, spread = 60, legal = 62; time = 0.00s
425s Info:     at iteration #4, type ICESTORM_LC: wirelen solved = 29, spread = 52, legal = 64; time = 0.00s
425s Info:     at iteration #4, type SB_GB: wirelen solved = 64, spread = 64, legal = 64; time = 0.00s
425s Info:     at iteration #4, type ALL: wirelen solved = 29, spread = 52, legal = 62; time = 0.00s
425s Info:     at iteration #5, type ICESTORM_LC: wirelen solved = 30, spread = 53, legal = 60; time = 0.00s
425s Info:     at iteration #5, type SB_GB: wirelen solved = 60, spread = 60, legal = 60; time = 0.00s
425s Info:     at iteration #5, type ALL: wirelen solved = 30, spread = 53, legal = 57; time = 0.00s
425s Info:     at iteration #6, type ICESTORM_LC: wirelen solved = 34, spread = 44, legal = 57; time = 0.00s
425s Info:     at iteration #6, type SB_GB: wirelen solved = 57, spread = 57, legal = 57; time = 0.00s
425s Info:     at iteration #6, type ALL: wirelen solved = 34, spread = 44, legal = 61; time = 0.00s
425s Info:     at iteration #7, type ICESTORM_LC: wirelen solved = 34, spread = 44, legal = 59; time = 0.00s
425s Info:     at iteration #7, type SB_GB: wirelen solved = 59, spread = 59, legal = 59; time = 0.00s
425s Info:     at iteration #7, type ALL: wirelen solved = 34, spread = 44, legal = 57; time = 0.00s
425s Info: HeAP Placer Time: 0.02s
425s Info:   of which solving equations: 0.01s
425s Info:   of which spreading cells: 0.00s
425s Info:   of which strict legalisation: 0.00s
425s 
425s Info: Running simulated annealing placer for refinement.
425s Info:   at iteration #1: temp = 0.000000, timing cost = 3, wirelen = 48
425s Info:   at iteration #5: temp = 0.000000, timing cost = 4, wirelen = 33
425s Info:   at iteration #10: temp = 0.000000, timing cost = 4, wirelen = 32
425s Info:   at iteration #11: temp = 0.000000, timing cost = 4, wirelen = 32 
425s Info: SA placement time 0.01s
425s 
425s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 159.74 MHz (PASS at 12.00 MHz)
425s 
425s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> <async>: 2.72 ns
425s 
425s Info: Slack histogram:
425s Info:  legend: * represents 1 endpoint(s)
425s Info:          + represents [1,1) endpoint(s)
425s Info: [ 77073,  77313) |** 
425s Info: [ 77313,  77553) |** 
425s Info: [ 77553,  77793) |** 
425s Info: [ 77793,  78033) | 
425s Info: [ 78033,  78273) |** 
425s Info: [ 78273,  78513) |** 
425s Info: [ 78513,  78753) |** 
425s Info: [ 78753,  78993) |** 
425s Info: [ 78993,  79233) | 
425s Info: [ 79233,  79473) |** 
425s Info: [ 79473,  79713) |* 
425s Info: [ 79713,  79953) |** 
425s Info: [ 79953,  80193) |*** 
425s Info: [ 80193,  80433) | 
425s Info: [ 80433,  80673) |** 
425s Info: [ 80673,  80913) |*** 
425s Info: [ 80913,  81153) |** 
425s Info: [ 81153,  81393) |****** 
425s Info: [ 81393,  81633) |* 
425s Info: [ 81633,  81873) |*************************************** 
425s Info: Checksum: 0xa7a876a4
425s 
425s Info: Routing..
425s Info: Setting up routing queue.
425s Info: Routing 126 arcs.
425s Info:            |   (re-)routed arcs  |   delta    | remaining|       time spent     |
425s Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|
425s Info:        126 |        0        101 |    0   101 |         0|       0.01       0.01|
425s Info: Routing complete.
425s Info: Router1 time 0.01s
425s Info: Checksum: 0x3ab1ef41
425s 
425s Info: Critical path report for clock 'clk$SB_IO_IN_$glb_clk' (posedge -> posedge):
425s Info: curr total
425s Info:  0.5  0.5  Source counter_SB_LUT4_I3_LC.O
425s Info:  0.6  1.1    Net counter[0] budget 78.411003 ns (2,29) -> (3,29)
425s Info:                Sink $nextpnr_ICESTORM_LC_0.I1
425s Info:                Defined in:
425s Info:                  example.v:20.14-20.25
425s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
425s Info:  0.3  1.4  Source $nextpnr_ICESTORM_LC_0.COUT
425s Info:  0.0  1.4    Net $nextpnr_ICESTORM_LC_0$O budget 0.000000 ns (3,29) -> (3,29)
425s Info:                Sink counter_SB_LUT4_I2_26_LC.CIN
425s Info:  0.1  1.5  Source counter_SB_LUT4_I2_26_LC.COUT
425s Info:  0.0  1.5    Net counter_SB_CARRY_CI_CO[2] budget 0.000000 ns (3,29) -> (3,29)
425s Info:                Sink counter_SB_LUT4_I2_15_LC.CIN
425s Info:                Defined in:
425s Info:                  example.v:20.14-20.25
425s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
425s Info:  0.1  1.6  Source counter_SB_LUT4_I2_15_LC.COUT
425s Info:  0.0  1.6    Net counter_SB_CARRY_CI_CO[3] budget 0.000000 ns (3,29) -> (3,29)
425s Info:                Sink counter_SB_LUT4_I2_14_LC.CIN
425s Info:                Defined in:
425s Info:                  example.v:20.14-20.25
425s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
425s Info:  0.1  1.8  Source counter_SB_LUT4_I2_14_LC.COUT
425s Info:  0.0  1.8    Net counter_SB_CARRY_CI_CO[4] budget 0.000000 ns (3,29) -> (3,29)
425s Info:                Sink counter_SB_LUT4_I2_13_LC.CIN
425s Info:                Defined in:
425s Info:                  example.v:20.14-20.25
425s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
425s Info:  0.1  1.9  Source counter_SB_LUT4_I2_13_LC.COUT
425s Info:  0.0  1.9    Net counter_SB_CARRY_CI_CO[5] budget 0.000000 ns (3,29) -> (3,29)
425s Info:                Sink counter_SB_LUT4_I2_12_LC.CIN
425s Info:                Defined in:
425s Info:                  example.v:20.14-20.25
425s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
425s Info:  0.1  2.0  Source counter_SB_LUT4_I2_12_LC.COUT
425s Info:  0.0  2.0    Net counter_SB_CARRY_CI_CO[6] budget 0.000000 ns (3,29) -> (3,29)
425s Info:                Sink counter_SB_LUT4_I2_11_LC.CIN
425s Info:                Defined in:
425s Info:                  example.v:20.14-20.25
425s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
425s Info:  0.1  2.1  Source counter_SB_LUT4_I2_11_LC.COUT
425s Info:  0.0  2.1    Net counter_SB_CARRY_CI_CO[7] budget 0.000000 ns (3,29) -> (3,29)
425s Info:                Sink counter_SB_LUT4_I2_10_LC.CIN
425s Info:                Defined in:
425s Info:                  example.v:20.14-20.25
425s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
425s Info:  0.1  2.3  Source counter_SB_LUT4_I2_10_LC.COUT
425s Info:  0.2  2.5    Net counter_SB_CARRY_CI_CO[8] budget 0.190000 ns (3,29) -> (3,30)
425s Info:                Sink counter_SB_LUT4_I2_9_LC.CIN
425s Info:                Defined in:
425s Info:                  example.v:20.14-20.25
425s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
425s Info:  0.1  2.6  Source counter_SB_LUT4_I2_9_LC.COUT
425s Info:  0.0  2.6    Net counter_SB_CARRY_CI_CO[9] budget 0.000000 ns (3,30) -> (3,30)
425s Info:                Sink counter_SB_LUT4_I2_8_LC.CIN
425s Info:                Defined in:
425s Info:                  example.v:20.14-20.25
425s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
425s Info:  0.1  2.7  Source counter_SB_LUT4_I2_8_LC.COUT
425s Info:  0.0  2.7    Net counter_SB_CARRY_CI_CO[10] budget 0.000000 ns (3,30) -> (3,30)
425s Info:                Sink counter_SB_LUT4_I2_7_LC.CIN
425s Info:                Defined in:
425s Info:                  example.v:20.14-20.25
425s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
425s Info:  0.1  2.8  Source counter_SB_LUT4_I2_7_LC.COUT
425s Info:  0.0  2.8    Net counter_SB_CARRY_CI_CO[11] budget 0.000000 ns (3,30) -> (3,30)
425s Info:                Sink counter_SB_LUT4_I2_6_LC.CIN
425s Info:                Defined in:
425s Info:                  example.v:20.14-20.25
425s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
425s Info:  0.1  3.0  Source counter_SB_LUT4_I2_6_LC.COUT
425s Info:  0.0  3.0    Net counter_SB_CARRY_CI_CO[12] budget 0.000000 ns (3,30) -> (3,30)
425s Info:                Sink counter_SB_LUT4_I2_5_LC.CIN
425s Info:                Defined in:
425s Info:                  example.v:20.14-20.25
425s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
425s Info:  0.1  3.1  Source counter_SB_LUT4_I2_5_LC.COUT
425s Info:  0.0  3.1    Net counter_SB_CARRY_CI_CO[13] budget 0.000000 ns (3,30) -> (3,30)
425s Info:                Sink counter_SB_LUT4_I2_4_LC.CIN
425s Info:                Defined in:
425s Info:                  example.v:20.14-20.25
425s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
425s Info:  0.1  3.2  Source counter_SB_LUT4_I2_4_LC.COUT
425s Info:  0.0  3.2    Net counter_SB_CARRY_CI_CO[14] budget 0.000000 ns (3,30) -> (3,30)
425s Info:                Sink counter_SB_LUT4_I2_3_LC.CIN
425s Info:                Defined in:
425s Info:                  example.v:20.14-20.25
425s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
425s Info:  0.1  3.3  Source counter_SB_LUT4_I2_3_LC.COUT
425s Info:  0.0  3.3    Net counter_SB_CARRY_CI_CO[15] budget 0.000000 ns (3,30) -> (3,30)
425s Info:                Sink counter_SB_LUT4_I2_2_LC.CIN
425s Info:                Defined in:
425s Info:                  example.v:20.14-20.25
425s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
425s Info:  0.1  3.5  Source counter_SB_LUT4_I2_2_LC.COUT
425s Info:  0.2  3.7    Net counter_SB_CARRY_CI_CO[16] budget 0.190000 ns (3,30) -> (3,31)
425s Info:                Sink counter_SB_LUT4_I2_1_LC.CIN
425s Info:                Defined in:
425s Info:                  example.v:20.14-20.25
425s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
425s Info:  0.1  3.8  Source counter_SB_LUT4_I2_1_LC.COUT
425s Info:  0.0  3.8    Net counter_SB_CARRY_CI_CO[17] budget 0.000000 ns (3,31) -> (3,31)
425s Info:                Sink counter_SB_LUT4_I2_LC.CIN
425s Info:                Defined in:
425s Info:                  example.v:20.14-20.25
425s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
425s Info:  0.1  3.9  Source counter_SB_LUT4_I2_LC.COUT
425s Info:  0.0  3.9    Net counter_SB_CARRY_CI_CO[18] budget 0.000000 ns (3,31) -> (3,31)
425s Info:                Sink counter_SB_LUT4_I2_28_LC.CIN
425s Info:                Defined in:
425s Info:                  example.v:20.14-20.25
425s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
425s Info:  0.1  4.0  Source counter_SB_LUT4_I2_28_LC.COUT
425s Info:  0.0  4.0    Net counter_SB_CARRY_CI_CO[19] budget 0.000000 ns (3,31) -> (3,31)
425s Info:                Sink counter_SB_LUT4_I2_27_LC.CIN
425s Info:                Defined in:
425s Info:                  example.v:20.14-20.25
425s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
425s Info:  0.1  4.2  Source counter_SB_LUT4_I2_27_LC.COUT
425s Info:  0.0  4.2    Net counter_SB_CARRY_CI_CO[20] budget 0.000000 ns (3,31) -> (3,31)
425s Info:                Sink counter_SB_LUT4_I2_25_LC.CIN
425s Info:                Defined in:
425s Info:                  example.v:20.14-20.25
425s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
425s Info:  0.1  4.3  Source counter_SB_LUT4_I2_25_LC.COUT
425s Info:  0.0  4.3    Net counter_SB_CARRY_CI_CO[21] budget 0.000000 ns (3,31) -> (3,31)
425s Info:                Sink counter_SB_LUT4_I2_24_LC.CIN
425s Info:                Defined in:
425s Info:                  example.v:20.14-20.25
425s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
425s Info:  0.1  4.4  Source counter_SB_LUT4_I2_24_LC.COUT
425s Info:  0.0  4.4    Net counter_SB_CARRY_CI_CO[22] budget 0.000000 ns (3,31) -> (3,31)
425s Info:                Sink counter_SB_LUT4_I2_23_LC.CIN
425s Info:                Defined in:
425s Info:                  example.v:20.14-20.25
425s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
425s Info:  0.1  4.6  Source counter_SB_LUT4_I2_23_LC.COUT
425s Info:  0.0  4.6    Net counter_SB_CARRY_CI_CO[23] budget 0.000000 ns (3,31) -> (3,31)
425s Info:                Sink counter_SB_LUT4_I2_22_LC.CIN
425s Info:                Defined in:
425s Info:                  example.v:20.14-20.25
425s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
425s Info:  0.1  4.7  Source counter_SB_LUT4_I2_22_LC.COUT
425s Info:  0.2  4.9    Net counter_SB_CARRY_CI_CO[24] budget 0.190000 ns (3,31) -> (3,32)
425s Info:                Sink counter_SB_LUT4_I2_21_LC.CIN
425s Info:                Defined in:
425s Info:                  example.v:20.14-20.25
425s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
425s Info:  0.1  5.0  Source counter_SB_LUT4_I2_21_LC.COUT
425s Info:  0.0  5.0    Net counter_SB_CARRY_CI_CO[25] budget 0.000000 ns (3,32) -> (3,32)
425s Info:                Sink counter_SB_LUT4_I2_20_LC.CIN
425s Info:                Defined in:
425s Info:                  example.v:20.14-20.25
425s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
425s Info:  0.1  5.1  Source counter_SB_LUT4_I2_20_LC.COUT
425s Info:  0.0  5.1    Net counter_SB_CARRY_CI_CO[26] budget 0.000000 ns (3,32) -> (3,32)
425s Info:                Sink counter_SB_LUT4_I2_19_LC.CIN
425s Info:                Defined in:
425s Info:                  example.v:20.14-20.25
425s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
425s Info:  0.1  5.3  Source counter_SB_LUT4_I2_19_LC.COUT
425s Info:  0.0  5.3    Net counter_SB_CARRY_CI_CO[27] budget 0.000000 ns (3,32) -> (3,32)
425s Info:                Sink counter_SB_LUT4_I2_18_LC.CIN
425s Info:                Defined in:
425s Info:                  example.v:20.14-20.25
425s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
425s Info:  0.1  5.4  Source counter_SB_LUT4_I2_18_LC.COUT
425s Info:  0.0  5.4    Net counter_SB_CARRY_CI_CO[28] budget 0.000000 ns (3,32) -> (3,32)
425s Info:                Sink counter_SB_LUT4_I2_17_LC.CIN
425s Info:                Defined in:
425s Info:                  example.v:20.14-20.25
425s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
425s Info:  0.1  5.5  Source counter_SB_LUT4_I2_17_LC.COUT
425s Info:  0.3  5.8    Net counter_SB_CARRY_CI_CO[29] budget 0.260000 ns (3,32) -> (3,32)
425s Info:                Sink counter_SB_LUT4_I2_16_LC.I3
425s Info:                Defined in:
425s Info:                  example.v:20.14-20.25
425s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
425s Info:  0.3  6.1  Setup counter_SB_LUT4_I2_16_LC.I3
425s Info: 4.7 ns logic, 1.4 ns routing
425s 
425s Info: Critical path report for cross-domain path 'posedge clk$SB_IO_IN_$glb_clk' -> '<async>':
425s Info: curr total
425s Info:  0.5  0.5  Source outcnt_SB_DFF_Q_DFFLC.O
425s Info:  1.2  1.8    Net outcnt[6] budget 41.208000 ns (3,32) -> (6,32)
425s Info:                Sink LED1_SB_LUT4_O_LC.I2
425s Info:                Defined in:
425s Info:                  example.v:17.17-17.23
425s Info:  0.4  2.1  Source LED1_SB_LUT4_O_LC.O
425s Info:  0.6  2.7    Net LED1$SB_IO_OUT budget 41.207001 ns (6,32) -> (6,33)
425s Info:                Sink LED1$sb_io.D_OUT_0
425s Info:                Defined in:
425s Info:                  example.v:4.9-4.13
425s Info: 0.9 ns logic, 1.8 ns routing
425s 
425s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 163.99 MHz (PASS at 12.00 MHz)
425s 
425s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> <async>: 2.72 ns
425s 
425s Info: Slack histogram:
425s Info:  legend: * represents 1 endpoint(s)
425s Info:          + represents [1,1) endpoint(s)
425s Info: [ 77235,  77467) |** 
425s Info: [ 77467,  77699) |** 
425s Info: [ 77699,  77931) |** 
425s Info: [ 77931,  78163) | 
425s Info: [ 78163,  78395) |** 
425s Info: [ 78395,  78627) |** 
425s Info: [ 78627,  78859) |** 
425s Info: [ 78859,  79091) |** 
425s Info: [ 79091,  79323) | 
425s Info: [ 79323,  79555) |** 
425s Info: [ 79555,  79787) |** 
425s Info: [ 79787,  80019) |* 
425s Info: [ 80019,  80251) |*** 
425s Info: [ 80251,  80483) | 
425s Info: [ 80483,  80715) |** 
425s Info: [ 80715,  80947) |** 
425s Info: [ 80947,  81179) |*** 
425s Info: [ 81179,  81411) |****** 
425s Info: [ 81411,  81643) |* 
425s Info: [ 81643,  81875) |*************************************** 
426s 
426s Info: Program finished normally.
426s icetime -d hx8k -mtr example.rpt example.asc
426s // Reading input .asc file..
426s // Reading 8k chipdb file..
427s // Creating timing netlist..
427s // Timing estimate: 6.09 ns (164.22 MHz)
427s icepack example.asc example.bin
427s make: Leaving directory '/tmp/autopkgtest.eGJMaA/build.OQp/src/examples/hx8kboard'
427s make: Entering directory '/tmp/autopkgtest.eGJMaA/build.OQp/src/examples/iceblink'
427s yosys -p 'synth_ice40 -top top -json example.json' example.v
427s 
427s  /----------------------------------------------------------------------------\
427s  |                                                                            |
427s  |  yosys -- Yosys Open SYnthesis Suite                                       |
427s  |                                                                            |
427s  |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
427s  |                                                                            |
427s  |  Permission to use, copy, modify, and/or distribute this software for any  |
427s  |  purpose with or without fee is hereby granted, provided that the above    |
427s  |  copyright notice and this permission notice appear in all copies.         |
427s  |                                                                            |
427s  |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
427s  |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
427s  |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
427s  |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
427s  |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
427s  |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
427s  |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
427s  |                                                                            |
427s  \----------------------------------------------------------------------------/
427s 
427s  Yosys 0.33 (git sha1 2584903a060)
427s 
427s 
427s -- Parsing `example.v' using frontend ` -vlog2k' --
427s 
427s 1. Executing Verilog-2005 frontend: example.v
427s Parsing Verilog input from `example.v' to AST representation.
427s Storing AST representation for module `$abstract\top'.
427s Successfully finished Verilog frontend.
427s 
427s -- Running command `synth_ice40 -top top -json example.json' --
427s 
427s 2. Executing SYNTH_ICE40 pass.
427s 
427s 2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v
427s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation.
427s Generating RTLIL representation for module `\SB_IO'.
427s Generating RTLIL representation for module `\SB_GB_IO'.
427s Generating RTLIL representation for module `\SB_GB'.
427s Generating RTLIL representation for module `\SB_LUT4'.
427s Generating RTLIL representation for module `\SB_CARRY'.
427s Generating RTLIL representation for module `\SB_DFF'.
427s Generating RTLIL representation for module `\SB_DFFE'.
427s Generating RTLIL representation for module `\SB_DFFSR'.
427s Generating RTLIL representation for module `\SB_DFFR'.
427s Generating RTLIL representation for module `\SB_DFFSS'.
427s Generating RTLIL representation for module `\SB_DFFS'.
427s Generating RTLIL representation for module `\SB_DFFESR'.
427s Generating RTLIL representation for module `\SB_DFFER'.
427s Generating RTLIL representation for module `\SB_DFFESS'.
427s Generating RTLIL representation for module `\SB_DFFES'.
427s Generating RTLIL representation for module `\SB_DFFN'.
427s Generating RTLIL representation for module `\SB_DFFNE'.
427s Generating RTLIL representation for module `\SB_DFFNSR'.
427s Generating RTLIL representation for module `\SB_DFFNR'.
427s Generating RTLIL representation for module `\SB_DFFNSS'.
427s Generating RTLIL representation for module `\SB_DFFNS'.
427s Generating RTLIL representation for module `\SB_DFFNESR'.
427s Generating RTLIL representation for module `\SB_DFFNER'.
427s Generating RTLIL representation for module `\SB_DFFNESS'.
427s Generating RTLIL representation for module `\SB_DFFNES'.
427s Generating RTLIL representation for module `\SB_RAM40_4K'.
427s Generating RTLIL representation for module `\SB_RAM40_4KNR'.
427s Generating RTLIL representation for module `\SB_RAM40_4KNW'.
427s Generating RTLIL representation for module `\SB_RAM40_4KNRNW'.
427s Generating RTLIL representation for module `\ICESTORM_LC'.
427s Generating RTLIL representation for module `\SB_PLL40_CORE'.
427s Generating RTLIL representation for module `\SB_PLL40_PAD'.
427s Generating RTLIL representation for module `\SB_PLL40_2_PAD'.
427s Generating RTLIL representation for module `\SB_PLL40_2F_CORE'.
427s Generating RTLIL representation for module `\SB_PLL40_2F_PAD'.
427s Generating RTLIL representation for module `\SB_WARMBOOT'.
427s Generating RTLIL representation for module `\SB_SPRAM256KA'.
427s Generating RTLIL representation for module `\SB_HFOSC'.
427s Generating RTLIL representation for module `\SB_LFOSC'.
427s Generating RTLIL representation for module `\SB_RGBA_DRV'.
427s Generating RTLIL representation for module `\SB_LED_DRV_CUR'.
427s Generating RTLIL representation for module `\SB_RGB_DRV'.
427s Generating RTLIL representation for module `\SB_I2C'.
427s Generating RTLIL representation for module `\SB_SPI'.
427s Generating RTLIL representation for module `\SB_LEDDA_IP'.
427s Generating RTLIL representation for module `\SB_FILTER_50NS'.
427s Generating RTLIL representation for module `\SB_IO_I3C'.
427s Generating RTLIL representation for module `\SB_IO_OD'.
427s Generating RTLIL representation for module `\SB_MAC16'.
427s Generating RTLIL representation for module `\ICESTORM_RAM'.
427s Successfully finished Verilog frontend.
427s 
427s 2.2. Executing HIERARCHY pass (managing design hierarchy).
427s 
427s 2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\top'.
427s Generating RTLIL representation for module `\top'.
427s 
427s 2.3.1. Analyzing design hierarchy..
427s Top module:  \top
427s 
427s 2.3.2. Analyzing design hierarchy..
427s Top module:  \top
427s Removing unused module `$abstract\top'.
427s Removed 1 unused modules.
427s 
427s 2.4. Executing PROC pass (convert processes to netlists).
427s 
427s 2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
427s Cleaned up 0 empty switches.
427s 
427s 2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
427s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241 in module SB_DFFNES.
427s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234 in module SB_DFFNESS.
427s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230 in module SB_DFFNER.
427s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223 in module SB_DFFNESR.
427s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220 in module SB_DFFNS.
427s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217 in module SB_DFFNSS.
427s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214 in module SB_DFFNR.
427s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211 in module SB_DFFNSR.
427s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203 in module SB_DFFES.
427s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196 in module SB_DFFESS.
427s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192 in module SB_DFFER.
427s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185 in module SB_DFFESR.
427s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182 in module SB_DFFS.
427s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179 in module SB_DFFSS.
427s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176 in module SB_DFFR.
427s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173 in module SB_DFFSR.
427s Removed a total of 0 dead cases.
427s 
427s 2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
427s Removed 8 redundant assignments.
427s Promoted 25 assignments to connections.
427s 
427s 2.4.4. Executing PROC_INIT pass (extract init attributes).
427s Found init rule in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'.
427s   Set init value: \Q = 1'0
427s Found init rule in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'.
427s   Set init value: \Q = 1'0
427s Found init rule in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'.
427s   Set init value: \Q = 1'0
427s Found init rule in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'.
427s   Set init value: \Q = 1'0
427s Found init rule in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'.
427s   Set init value: \Q = 1'0
427s Found init rule in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'.
427s   Set init value: \Q = 1'0
427s Found init rule in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'.
427s   Set init value: \Q = 1'0
427s Found init rule in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'.
427s   Set init value: \Q = 1'0
427s Found init rule in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'.
427s   Set init value: \Q = 1'0
427s Found init rule in `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'.
427s   Set init value: \Q = 1'0
427s Found init rule in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'.
427s   Set init value: \Q = 1'0
427s Found init rule in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'.
427s   Set init value: \Q = 1'0
427s Found init rule in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'.
427s   Set init value: \Q = 1'0
427s Found init rule in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'.
427s   Set init value: \Q = 1'0
427s Found init rule in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'.
427s   Set init value: \Q = 1'0
427s Found init rule in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'.
427s   Set init value: \Q = 1'0
427s Found init rule in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'.
427s   Set init value: \Q = 1'0
427s Found init rule in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'.
427s   Set init value: \Q = 1'0
427s Found init rule in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'.
427s   Set init value: \Q = 1'0
427s Found init rule in `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'.
427s   Set init value: \Q = 1'0
427s Found init rule in `\top.$proc$example.v:15$384'.
427s   Set init value: \counter = 26'00000000000000000000000000
427s 
427s 2.4.5. Executing PROC_ARST pass (detect async resets in processes).
427s Found async reset \S in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
427s Found async reset \R in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
427s Found async reset \S in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
427s Found async reset \R in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
427s Found async reset \S in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
427s Found async reset \R in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
427s Found async reset \S in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'.
427s Found async reset \R in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'.
427s 
427s 2.4.6. Executing PROC_ROM pass (convert switches to ROMs).
427s Converted 0 switches.
427s <suppressed ~18 debug messages>
427s 
427s 2.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
427s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'.
427s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
427s      1/1: $0\Q[0:0]
427s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'.
427s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
427s      1/1: $0\Q[0:0]
427s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'.
427s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
427s      1/1: $0\Q[0:0]
427s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'.
427s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
427s      1/1: $0\Q[0:0]
427s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'.
427s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
427s      1/1: $0\Q[0:0]
427s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'.
427s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
427s      1/1: $0\Q[0:0]
427s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'.
427s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
427s      1/1: $0\Q[0:0]
427s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'.
427s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'.
427s      1/1: $0\Q[0:0]
427s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'.
427s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'.
427s      1/1: $0\Q[0:0]
427s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'.
427s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'.
427s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'.
427s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
427s      1/1: $0\Q[0:0]
427s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'.
427s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'.
427s      1/1: $0\Q[0:0]
427s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'.
427s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
427s      1/1: $0\Q[0:0]
427s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'.
427s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'.
427s      1/1: $0\Q[0:0]
427s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'.
427s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'.
427s      1/1: $0\Q[0:0]
427s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'.
427s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'.
427s      1/1: $0\Q[0:0]
427s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'.
427s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'.
427s      1/1: $0\Q[0:0]
427s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'.
427s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'.
427s      1/1: $0\Q[0:0]
427s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'.
427s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'.
427s      1/1: $0\Q[0:0]
427s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'.
427s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'.
427s Creating decoders for process `\top.$proc$example.v:15$384'.
427s Creating decoders for process `\top.$proc$example.v:18$381'.
427s 
427s 2.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
427s 
427s 2.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
427s Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
427s   created $adff cell `$procdff$429' with negative edge clock and positive level reset.
427s Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
427s   created $dff cell `$procdff$430' with negative edge clock.
427s Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
427s   created $adff cell `$procdff$431' with negative edge clock and positive level reset.
427s Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
427s   created $dff cell `$procdff$432' with negative edge clock.
427s Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
427s   created $adff cell `$procdff$433' with negative edge clock and positive level reset.
427s Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
427s   created $dff cell `$procdff$434' with negative edge clock.
427s Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
427s   created $adff cell `$procdff$435' with negative edge clock and positive level reset.
427s Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'.
427s   created $dff cell `$procdff$436' with negative edge clock.
427s Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'.
427s   created $dff cell `$procdff$437' with negative edge clock.
427s Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'.
427s   created $dff cell `$procdff$438' with negative edge clock.
427s Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
427s   created $adff cell `$procdff$439' with positive edge clock and positive level reset.
427s Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'.
427s   created $dff cell `$procdff$440' with positive edge clock.
427s Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
427s   created $adff cell `$procdff$441' with positive edge clock and positive level reset.
427s Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'.
427s   created $dff cell `$procdff$442' with positive edge clock.
427s Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'.
427s   created $adff cell `$procdff$443' with positive edge clock and positive level reset.
427s Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'.
427s   created $dff cell `$procdff$444' with positive edge clock.
427s Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'.
427s   created $adff cell `$procdff$445' with positive edge clock and positive level reset.
427s Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'.
427s   created $dff cell `$procdff$446' with positive edge clock.
427s Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'.
427s   created $dff cell `$procdff$447' with positive edge clock.
427s Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'.
427s   created $dff cell `$procdff$448' with positive edge clock.
427s Creating register for signal `\top.\counter' using process `\top.$proc$example.v:18$381'.
427s   created $dff cell `$procdff$449' with positive edge clock.
427s Creating register for signal `\top.\outcnt' using process `\top.$proc$example.v:18$381'.
427s   created $dff cell `$procdff$450' with positive edge clock.
427s 
427s 2.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
427s 
427s 2.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
427s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'.
427s Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
427s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
427s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'.
427s Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
427s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
427s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'.
427s Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
427s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
427s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'.
427s Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
427s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
427s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'.
427s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
427s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'.
427s Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
427s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
427s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'.
427s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
427s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'.
427s Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'.
427s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'.
427s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'.
427s Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'.
427s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'.
427s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'.
427s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'.
427s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'.
427s Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
427s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
427s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'.
427s Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'.
427s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'.
427s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'.
427s Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
427s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
427s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'.
427s Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'.
427s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'.
427s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'.
427s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'.
427s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'.
427s Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'.
427s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'.
427s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'.
427s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'.
427s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'.
427s Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'.
427s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'.
427s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'.
427s Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'.
427s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'.
427s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'.
427s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'.
427s Removing empty process `top.$proc$example.v:15$384'.
427s Removing empty process `top.$proc$example.v:18$381'.
427s Cleaned up 18 empty switches.
427s 
427s 2.4.12. Executing OPT_EXPR pass (perform const folding).
427s Optimizing module top.
427s <suppressed ~1 debug messages>
427s 
427s 2.5. Executing FLATTEN pass (flatten design).
427s 
427s 2.6. Executing TRIBUF pass.
427s 
427s 2.7. Executing DEMINOUT pass (demote inout ports to input or output).
427s 
427s 2.8. Executing OPT_EXPR pass (perform const folding).
427s Optimizing module top.
427s 
427s 2.9. Executing OPT_CLEAN pass (remove unused cells and wires).
427s Finding unused cells or wires in module \top..
427s Removed 0 unused cells and 3 unused wires.
427s <suppressed ~1 debug messages>
427s 
427s 2.10. Executing CHECK pass (checking for obvious problems).
427s Checking module top...
427s Found and reported 0 problems.
427s 
427s 2.11. Executing OPT pass (performing simple optimizations).
427s 
427s 2.11.1. Executing OPT_EXPR pass (perform const folding).
427s Optimizing module top.
427s 
427s 2.11.2. Executing OPT_MERGE pass (detect identical cells).
427s Finding identical cells in module `\top'.
427s Removed a total of 0 cells.
427s 
427s 2.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
427s Running muxtree optimizer on module \top..
427s   Creating internal representation of mux trees.
427s   No muxes found in this module.
427s Removed 0 multiplexer ports.
427s 
427s 2.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
427s   Optimizing cells in module \top.
427s Performed a total of 0 changes.
427s 
427s 2.11.5. Executing OPT_MERGE pass (detect identical cells).
427s Finding identical cells in module `\top'.
427s Removed a total of 0 cells.
427s 
427s 2.11.6. Executing OPT_DFF pass (perform DFF optimizations).
427s 
427s 2.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
427s Finding unused cells or wires in module \top..
427s 
427s 2.11.8. Executing OPT_EXPR pass (perform const folding).
427s Optimizing module top.
427s 
427s 2.11.9. Finished OPT passes. (There is nothing left to do.)
427s 
427s 2.12. Executing FSM pass (extract and optimize FSM).
427s 
427s 2.12.1. Executing FSM_DETECT pass (finding FSMs in design).
427s 
427s 2.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).
427s 
427s 2.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).
427s 
427s 2.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
427s Finding unused cells or wires in module \top..
427s 
427s 2.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).
427s 
427s 2.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
427s 
427s 2.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
427s 
427s 2.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
427s 
427s 2.13. Executing OPT pass (performing simple optimizations).
427s 
427s 2.13.1. Executing OPT_EXPR pass (perform const folding).
427s Optimizing module top.
427s 
427s 2.13.2. Executing OPT_MERGE pass (detect identical cells).
427s Finding identical cells in module `\top'.
427s Removed a total of 0 cells.
427s 
427s 2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
427s Running muxtree optimizer on module \top..
427s   Creating internal representation of mux trees.
427s   No muxes found in this module.
427s Removed 0 multiplexer ports.
427s 
427s 2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
427s   Optimizing cells in module \top.
427s Performed a total of 0 changes.
427s 
427s 2.13.5. Executing OPT_MERGE pass (detect identical cells).
427s Finding identical cells in module `\top'.
427s Removed a total of 0 cells.
427s 
427s 2.13.6. Executing OPT_DFF pass (perform DFF optimizations).
427s 
427s 2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
427s Finding unused cells or wires in module \top..
427s 
427s 2.13.8. Executing OPT_EXPR pass (perform const folding).
427s Optimizing module top.
427s 
427s 2.13.9. Finished OPT passes. (There is nothing left to do.)
427s 
427s 2.14. Executing WREDUCE pass (reducing word size of cells).
427s Removed top 31 bits (of 32) from port B of cell top.$add$example.v:19$382 ($add).
427s Removed top 6 bits (of 32) from port Y of cell top.$add$example.v:19$382 ($add).
427s 
427s 2.15. Executing PEEPOPT pass (run peephole optimizers).
427s 
427s 2.16. Executing OPT_CLEAN pass (remove unused cells and wires).
427s Finding unused cells or wires in module \top..
427s Removed 0 unused cells and 1 unused wires.
427s <suppressed ~1 debug messages>
427s 
427s 2.17. Executing SHARE pass (SAT-based resource sharing).
427s 
427s 2.18. Executing TECHMAP pass (map to technology primitives).
427s 
427s 2.18.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v
427s Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation.
427s Generating RTLIL representation for module `\_90_lut_cmp_'.
427s Successfully finished Verilog frontend.
427s 
427s 2.18.2. Continuing TECHMAP pass.
427s No more expansions possible.
427s <suppressed ~6 debug messages>
427s 
427s 2.19. Executing OPT_EXPR pass (perform const folding).
427s Optimizing module top.
427s 
427s 2.20. Executing OPT_CLEAN pass (remove unused cells and wires).
427s Finding unused cells or wires in module \top..
427s 
427s 2.21. Executing ALUMACC pass (create $alu and $macc cells).
427s Extracting $alu and $macc cells in module top:
427s   creating $macc model for $add$example.v:19$382 ($add).
427s   creating $alu model for $macc $add$example.v:19$382.
427s   creating $alu cell for $add$example.v:19$382: $auto$alumacc.cc:485:replace_alu$452
427s   created 1 $alu and 0 $macc cells.
427s 
427s 2.22. Executing OPT pass (performing simple optimizations).
427s 
427s 2.22.1. Executing OPT_EXPR pass (perform const folding).
427s Optimizing module top.
427s 
427s 2.22.2. Executing OPT_MERGE pass (detect identical cells).
427s Finding identical cells in module `\top'.
427s Removed a total of 0 cells.
427s 
427s 2.22.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
427s Running muxtree optimizer on module \top..
427s   Creating internal representation of mux trees.
427s   No muxes found in this module.
427s Removed 0 multiplexer ports.
427s 
427s 2.22.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
427s   Optimizing cells in module \top.
427s Performed a total of 0 changes.
427s 
427s 2.22.5. Executing OPT_MERGE pass (detect identical cells).
427s Finding identical cells in module `\top'.
427s Removed a total of 0 cells.
427s 
427s 2.22.6. Executing OPT_DFF pass (perform DFF optimizations).
427s 
427s 2.22.7. Executing OPT_CLEAN pass (remove unused cells and wires).
427s Finding unused cells or wires in module \top..
427s 
427s 2.22.8. Executing OPT_EXPR pass (perform const folding).
427s Optimizing module top.
427s 
427s 2.22.9. Finished OPT passes. (There is nothing left to do.)
427s 
427s 2.23. Executing MEMORY pass.
427s 
427s 2.23.1. Executing OPT_MEM pass (optimize memories).
427s Performed a total of 0 transformations.
427s 
427s 2.23.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
427s Performed a total of 0 transformations.
427s 
427s 2.23.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
427s 
427s 2.23.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
427s 
427s 2.23.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
427s 
427s 2.23.6. Executing OPT_CLEAN pass (remove unused cells and wires).
427s Finding unused cells or wires in module \top..
427s 
427s 2.23.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
427s 
427s 2.23.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
427s Performed a total of 0 transformations.
427s 
427s 2.23.9. Executing OPT_CLEAN pass (remove unused cells and wires).
427s Finding unused cells or wires in module \top..
427s 
427s 2.23.10. Executing MEMORY_COLLECT pass (generating $mem cells).
427s 
427s 2.24. Executing OPT_CLEAN pass (remove unused cells and wires).
427s Finding unused cells or wires in module \top..
427s 
427s 2.25. Executing MEMORY_LIBMAP pass (mapping memories to cells).
427s 
427s 2.26. Executing TECHMAP pass (map to technology primitives).
427s 
427s 2.26.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v
428s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation.
428s Generating RTLIL representation for module `\$__ICE40_RAM4K_'.
428s Successfully finished Verilog frontend.
428s 
428s 2.26.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/spram_map.v
428s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/spram_map.v' to AST representation.
428s Generating RTLIL representation for module `\$__ICE40_SPRAM_'.
428s Successfully finished Verilog frontend.
428s 
428s 2.26.3. Continuing TECHMAP pass.
428s No more expansions possible.
428s <suppressed ~4 debug messages>
428s 
428s 2.27. Executing ICE40_BRAMINIT pass.
428s 
428s 2.28. Executing OPT pass (performing simple optimizations).
428s 
428s 2.28.1. Executing OPT_EXPR pass (perform const folding).
428s Optimizing module top.
428s 
428s 2.28.2. Executing OPT_MERGE pass (detect identical cells).
428s Finding identical cells in module `\top'.
428s Removed a total of 0 cells.
428s 
428s 2.28.3. Executing OPT_DFF pass (perform DFF optimizations).
428s 
428s 2.28.4. Executing OPT_CLEAN pass (remove unused cells and wires).
428s Finding unused cells or wires in module \top..
428s 
428s 2.28.5. Finished fast OPT passes.
428s 
428s 2.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
428s 
428s 2.30. Executing OPT pass (performing simple optimizations).
428s 
428s 2.30.1. Executing OPT_EXPR pass (perform const folding).
428s Optimizing module top.
428s 
428s 2.30.2. Executing OPT_MERGE pass (detect identical cells).
428s Finding identical cells in module `\top'.
428s Removed a total of 0 cells.
428s 
428s 2.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
428s Running muxtree optimizer on module \top..
428s   Creating internal representation of mux trees.
428s   No muxes found in this module.
428s Removed 0 multiplexer ports.
428s 
428s 2.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
428s   Optimizing cells in module \top.
428s Performed a total of 0 changes.
428s 
428s 2.30.5. Executing OPT_MERGE pass (detect identical cells).
428s Finding identical cells in module `\top'.
428s Removed a total of 0 cells.
428s 
428s 2.30.6. Executing OPT_DFF pass (perform DFF optimizations).
428s 
428s 2.30.7. Executing OPT_CLEAN pass (remove unused cells and wires).
428s Finding unused cells or wires in module \top..
428s 
428s 2.30.8. Executing OPT_EXPR pass (perform const folding).
428s Optimizing module top.
428s 
428s 2.30.9. Finished OPT passes. (There is nothing left to do.)
428s 
428s 2.31. Executing ICE40_WRAPCARRY pass (wrap carries).
428s 
428s 2.32. Executing TECHMAP pass (map to technology primitives).
428s 
428s 2.32.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v
428s Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation.
428s Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
428s Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
428s Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
428s Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
428s Generating RTLIL representation for module `\_90_simplemap_various'.
428s Generating RTLIL representation for module `\_90_simplemap_registers'.
428s Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
428s Generating RTLIL representation for module `\_90_shift_shiftx'.
428s Generating RTLIL representation for module `\_90_fa'.
428s Generating RTLIL representation for module `\_90_lcu'.
428s Generating RTLIL representation for module `\_90_alu'.
428s Generating RTLIL representation for module `\_90_macc'.
428s Generating RTLIL representation for module `\_90_alumacc'.
428s Generating RTLIL representation for module `\$__div_mod_u'.
428s Generating RTLIL representation for module `\$__div_mod_trunc'.
428s Generating RTLIL representation for module `\_90_div'.
428s Generating RTLIL representation for module `\_90_mod'.
428s Generating RTLIL representation for module `\$__div_mod_floor'.
428s Generating RTLIL representation for module `\_90_divfloor'.
428s Generating RTLIL representation for module `\_90_modfloor'.
428s Generating RTLIL representation for module `\_90_pow'.
428s Generating RTLIL representation for module `\_90_pmux'.
428s Generating RTLIL representation for module `\_90_demux'.
428s Generating RTLIL representation for module `\_90_lut'.
428s Successfully finished Verilog frontend.
428s 
428s 2.32.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v
428s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation.
428s Generating RTLIL representation for module `\_80_ice40_alu'.
428s Successfully finished Verilog frontend.
428s 
428s 2.32.3. Continuing TECHMAP pass.
428s Using template $paramod$a8151eed7df109f18d5adf1169b40bb7b9e884a8\_80_ice40_alu for cells of type $alu.
428s Using extmapper simplemap for cells of type $dff.
428s Using extmapper simplemap for cells of type $xor.
428s Using extmapper simplemap for cells of type $mux.
428s Using extmapper simplemap for cells of type $not.
428s Using extmapper simplemap for cells of type $pos.
428s No more expansions possible.
428s <suppressed ~100 debug messages>
428s 
428s 2.33. Executing OPT pass (performing simple optimizations).
428s 
428s 2.33.1. Executing OPT_EXPR pass (perform const folding).
428s Optimizing module top.
428s <suppressed ~52 debug messages>
428s 
428s 2.33.2. Executing OPT_MERGE pass (detect identical cells).
428s Finding identical cells in module `\top'.
428s <suppressed ~3 debug messages>
428s Removed a total of 1 cells.
428s 
428s 2.33.3. Executing OPT_DFF pass (perform DFF optimizations).
428s 
428s 2.33.4. Executing OPT_CLEAN pass (remove unused cells and wires).
428s Finding unused cells or wires in module \top..
428s Removed 26 unused cells and 17 unused wires.
428s <suppressed ~27 debug messages>
428s 
428s 2.33.5. Finished fast OPT passes.
428s 
428s 2.34. Executing ICE40_OPT pass (performing simple optimizations).
428s 
428s 2.34.1. Running ICE40 specific optimizations.
428s Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$452.slice[0].carry: CO=\counter [0]
428s 
428s 2.34.2. Executing OPT_EXPR pass (perform const folding).
428s Optimizing module top.
428s 
428s 2.34.3. Executing OPT_MERGE pass (detect identical cells).
428s Finding identical cells in module `\top'.
428s Removed a total of 0 cells.
428s 
428s 2.34.4. Executing OPT_DFF pass (perform DFF optimizations).
428s 
428s 2.34.5. Executing OPT_CLEAN pass (remove unused cells and wires).
428s Finding unused cells or wires in module \top..
428s 
428s 2.34.6. Rerunning OPT passes. (Removed registers in this run.)
428s 
428s 2.34.7. Running ICE40 specific optimizations.
428s 
428s 2.34.8. Executing OPT_EXPR pass (perform const folding).
428s Optimizing module top.
428s 
428s 2.34.9. Executing OPT_MERGE pass (detect identical cells).
428s Finding identical cells in module `\top'.
428s Removed a total of 0 cells.
428s 
428s 2.34.10. Executing OPT_DFF pass (perform DFF optimizations).
428s 
428s 2.34.11. Executing OPT_CLEAN pass (remove unused cells and wires).
428s Finding unused cells or wires in module \top..
428s 
428s 2.34.12. Finished OPT passes. (There is nothing left to do.)
428s 
428s 2.35. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
428s 
428s 2.36. Executing TECHMAP pass (map to technology primitives).
428s 
428s 2.36.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v
428s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation.
428s Generating RTLIL representation for module `\$_DFF_N_'.
428s Generating RTLIL representation for module `\$_DFF_P_'.
428s Generating RTLIL representation for module `\$_DFFE_NP_'.
428s Generating RTLIL representation for module `\$_DFFE_PP_'.
428s Generating RTLIL representation for module `\$_DFF_NP0_'.
428s Generating RTLIL representation for module `\$_DFF_NP1_'.
428s Generating RTLIL representation for module `\$_DFF_PP0_'.
428s Generating RTLIL representation for module `\$_DFF_PP1_'.
428s Generating RTLIL representation for module `\$_DFFE_NP0P_'.
428s Generating RTLIL representation for module `\$_DFFE_NP1P_'.
428s Generating RTLIL representation for module `\$_DFFE_PP0P_'.
428s Generating RTLIL representation for module `\$_DFFE_PP1P_'.
428s Generating RTLIL representation for module `\$_SDFF_NP0_'.
428s Generating RTLIL representation for module `\$_SDFF_NP1_'.
428s Generating RTLIL representation for module `\$_SDFF_PP0_'.
428s Generating RTLIL representation for module `\$_SDFF_PP1_'.
428s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
428s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
428s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
428s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
428s Successfully finished Verilog frontend.
428s 
428s 2.36.2. Continuing TECHMAP pass.
428s Using template \$_DFF_P_ for cells of type $_DFF_P_.
428s No more expansions possible.
428s <suppressed ~52 debug messages>
428s 
428s 2.37. Executing OPT_EXPR pass (perform const folding).
428s Optimizing module top.
428s 
428s 2.38. Executing SIMPLEMAP pass (map simple cells to gate primitives).
428s Mapping top.$auto$alumacc.cc:485:replace_alu$452.slice[0].carry ($lut).
428s 
428s 2.39. Executing ICE40_OPT pass (performing simple optimizations).
428s 
428s 2.39.1. Running ICE40 specific optimizations.
428s 
428s 2.39.2. Executing OPT_EXPR pass (perform const folding).
428s Optimizing module top.
428s <suppressed ~14 debug messages>
428s 
428s 2.39.3. Executing OPT_MERGE pass (detect identical cells).
428s Finding identical cells in module `\top'.
428s Removed a total of 0 cells.
428s 
428s 2.39.4. Executing OPT_DFF pass (perform DFF optimizations).
428s 
428s 2.39.5. Executing OPT_CLEAN pass (remove unused cells and wires).
428s Finding unused cells or wires in module \top..
428s Removed 0 unused cells and 124 unused wires.
428s <suppressed ~1 debug messages>
428s 
428s 2.39.6. Rerunning OPT passes. (Removed registers in this run.)
428s 
428s 2.39.7. Running ICE40 specific optimizations.
428s 
428s 2.39.8. Executing OPT_EXPR pass (perform const folding).
428s Optimizing module top.
428s 
428s 2.39.9. Executing OPT_MERGE pass (detect identical cells).
428s Finding identical cells in module `\top'.
428s Removed a total of 0 cells.
428s 
428s 2.39.10. Executing OPT_DFF pass (perform DFF optimizations).
428s 
428s 2.39.11. Executing OPT_CLEAN pass (remove unused cells and wires).
428s Finding unused cells or wires in module \top..
428s 
428s 2.39.12. Finished OPT passes. (There is nothing left to do.)
428s 
428s 2.40. Executing TECHMAP pass (map to technology primitives).
428s 
428s 2.40.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v
428s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation.
428s Generating RTLIL representation for module `\$_DLATCH_N_'.
428s Generating RTLIL representation for module `\$_DLATCH_P_'.
428s Successfully finished Verilog frontend.
428s 
428s 2.40.2. Continuing TECHMAP pass.
428s No more expansions possible.
428s <suppressed ~4 debug messages>
428s 
428s 2.41. Executing ABC pass (technology mapping using ABC).
428s 
428s 2.41.1. Extracting gate netlist of module `\top' to `<abc-temp-dir>/input.blif'..
428s Extracted 1 gates and 2 wires to a netlist network with 1 inputs and 1 outputs.
428s 
428s 2.41.1.1. Executing ABC.
428s Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
428s ABC: ABC command line: "source <abc-temp-dir>/abc.script".
428s ABC: 
428s ABC: + read_blif <abc-temp-dir>/input.blif 
428s ABC: + read_lut <abc-temp-dir>/lutdefs.txt 
428s ABC: + strash 
428s ABC: + &get -n 
428s ABC: + &fraig -x 
428s ABC: + &put 
428s ABC: + scorr 
428s ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
428s ABC: + dc2 
428s ABC: + dretime 
428s ABC: + strash 
428s ABC: + dch -f 
428s ABC: + if 
428s ABC: + mfs2 
428s ABC: + lutpack -S 1 
428s ABC: + dress <abc-temp-dir>/input.blif 
428s ABC: Total number of equiv classes                =       2.
428s ABC: Participating nodes from both networks       =       2.
428s ABC: Participating nodes from the first network   =       1. (  50.00 % of nodes)
428s ABC: Participating nodes from the second network  =       1. (  50.00 % of nodes)
428s ABC: Node pairs (any polarity)                    =       1. (  50.00 % of names can be moved)
428s ABC: Node pairs (same polarity)                   =       1. (  50.00 % of names can be moved)
428s ABC: Total runtime =     0.00 sec
428s ABC: + write_blif <abc-temp-dir>/output.blif 
428s 
428s 2.41.1.2. Re-integrating ABC results.
428s ABC RESULTS:              $lut cells:        1
428s ABC RESULTS:        internal signals:        0
428s ABC RESULTS:           input signals:        1
428s ABC RESULTS:          output signals:        1
428s Removing temp directory.
428s 
428s 2.42. Executing ICE40_WRAPCARRY pass (wrap carries).
428s 
428s 2.43. Executing TECHMAP pass (map to technology primitives).
428s 
428s 2.43.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v
428s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation.
428s Generating RTLIL representation for module `\$_DFF_N_'.
428s Generating RTLIL representation for module `\$_DFF_P_'.
428s Generating RTLIL representation for module `\$_DFFE_NP_'.
428s Generating RTLIL representation for module `\$_DFFE_PP_'.
428s Generating RTLIL representation for module `\$_DFF_NP0_'.
428s Generating RTLIL representation for module `\$_DFF_NP1_'.
428s Generating RTLIL representation for module `\$_DFF_PP0_'.
428s Generating RTLIL representation for module `\$_DFF_PP1_'.
428s Generating RTLIL representation for module `\$_DFFE_NP0P_'.
428s Generating RTLIL representation for module `\$_DFFE_NP1P_'.
428s Generating RTLIL representation for module `\$_DFFE_PP0P_'.
428s Generating RTLIL representation for module `\$_DFFE_PP1P_'.
428s Generating RTLIL representation for module `\$_SDFF_NP0_'.
428s Generating RTLIL representation for module `\$_SDFF_NP1_'.
428s Generating RTLIL representation for module `\$_SDFF_PP0_'.
428s Generating RTLIL representation for module `\$_SDFF_PP1_'.
428s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
428s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
428s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
428s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
428s Successfully finished Verilog frontend.
428s 
428s 2.43.2. Continuing TECHMAP pass.
428s No more expansions possible.
428s <suppressed ~22 debug messages>
428s Removed 1 unused cells and 3 unused wires.
428s 
428s 2.44. Executing OPT_LUT pass (optimize LUTs).
428s Discovering LUTs.
428s Number of LUTs:       26
428s   1-LUT                1
428s   2-LUT                1
428s   3-LUT               24
428s   with \SB_CARRY    (#0)   24
428s   with \SB_CARRY    (#1)   24
428s 
428s Eliminating LUTs.
428s Number of LUTs:       26
428s   1-LUT                1
428s   2-LUT                1
428s   3-LUT               24
428s   with \SB_CARRY    (#0)   24
428s   with \SB_CARRY    (#1)   24
428s 
428s Combining LUTs.
428s Number of LUTs:       26
428s   1-LUT                1
428s   2-LUT                1
428s   3-LUT               24
428s   with \SB_CARRY    (#0)   24
428s   with \SB_CARRY    (#1)   24
428s 
428s Eliminated 0 LUTs.
428s Combined 0 LUTs.
428s <suppressed ~100 debug messages>
428s 
428s 2.45. Executing TECHMAP pass (map to technology primitives).
428s 
428s 2.45.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v
428s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation.
428s Generating RTLIL representation for module `\$lut'.
428s Successfully finished Verilog frontend.
428s 
428s 2.45.2. Continuing TECHMAP pass.
428s Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut.
428s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
428s No more expansions possible.
428s <suppressed ~55 debug messages>
428s Removed 0 unused cells and 52 unused wires.
428s 
428s 2.46. Executing AUTONAME pass.
428s Renamed 132 objects in module top (4 iterations).
428s <suppressed ~82 debug messages>
428s 
428s 2.47. Executing HIERARCHY pass (managing design hierarchy).
428s 
428s 2.47.1. Analyzing design hierarchy..
428s Top module:  \top
428s 
428s 2.47.2. Analyzing design hierarchy..
428s Top module:  \top
428s Removed 0 unused modules.
428s 
428s 2.48. Printing statistics.
428s 
428s === top ===
428s 
428s    Number of wires:                  9
428s    Number of wire bits:             87
428s    Number of public wires:           9
428s    Number of public wire bits:      87
428s    Number of memories:               0
428s    Number of memory bits:            0
428s    Number of processes:              0
428s    Number of cells:                 80
428s      SB_CARRY                       24
428s      SB_DFF                         30
428s      SB_LUT4                        26
428s 
428s 2.49. Executing CHECK pass (checking for obvious problems).
428s Checking module top...
428s Found and reported 0 problems.
428s 
428s 2.50. Executing JSON backend.
428s 
428s End of script. Logfile hash: c93d6c0190, CPU: user 0.96s system 0.00s, MEM: 20.00 MB peak
428s Yosys 0.33 (git sha1 2584903a060)
428s Time spent: 66% 13x read_verilog (0 sec), 7% 1x synth_ice40 (0 sec), ...
428s nextpnr-ice40 --hx1k --package vq100 --asc example.asc --pcf iceblink.pcf --json example.json
428s Info: constrained 'LED2' to bel 'X13/Y7/io1'
428s Info: constrained 'LED3' to bel 'X13/Y6/io1'
428s Info: constrained 'LED4' to bel 'X13/Y4/io1'
428s Info: constrained 'LED5' to bel 'X13/Y3/io1'
428s Info: constrained 'clk' to bel 'X0/Y9/io0'
428s 
428s Info: Packing constants..
428s Info: Packing IOs..
428s Info: Packing LUT-FFs..
428s Info:        0 LCs used as LUT4 only
428s Info:       26 LCs used as LUT4 and DFF
428s Info: Packing non-LUT FFs..
428s Info:        4 LCs used as DFF only
428s Info: Packing carries..
428s Info:        0 LCs used as CARRY only
428s Info: Packing indirect carry+LUT pairs...
428s Info:        0 LUTs merged into carry LCs
428s Info: Packing RAMs..
428s Info: Placing PLLs..
428s Info: Packing special functions..
428s Info: Packing PLLs..
428s Info: Promoting globals..
428s Info: promoting clk$SB_IO_IN (fanout 30)
428s Info: Constraining chains...
428s Info:        1 LCs used to legalise carry chains.
428s Info: Checksum: 0xabd25caf
428s 
428s Info: Annotating ports with timing budgets for target frequency 12.00 MHz
428s Info: Checksum: 0x8546a4a1
428s 
428s Info: Device utilisation:
428s Info: 	         ICESTORM_LC:    33/ 1280     2%
428s Info: 	        ICESTORM_RAM:     0/   16     0%
428s Info: 	               SB_IO:     5/  112     4%
428s Info: 	               SB_GB:     1/    8    12%
428s Info: 	        ICESTORM_PLL:     0/    1     0%
428s Info: 	         SB_WARMBOOT:     0/    1     0%
428s 
428s Info: Placed 5 cells based on constraints.
428s Info: Creating initial analytic placement for 7 cells, random placement wirelen = 81.
428s Info:     at initial placer iter 0, wirelen = 7
428s Info:     at initial placer iter 1, wirelen = 7
428s Info:     at initial placer iter 2, wirelen = 7
428s Info:     at initial placer iter 3, wirelen = 7
428s Info: Running main analytical placer, max placement attempts per cell = 10000.
428s Info:     at iteration #1, type ICESTORM_LC: wirelen solved = 7, spread = 16, legal = 25; time = 0.00s
428s Info:     at iteration #1, type SB_GB: wirelen solved = 25, spread = 25, legal = 25; time = 0.00s
428s Info:     at iteration #1, type ALL: wirelen solved = 7, spread = 8, legal = 18; time = 0.00s
428s Info:     at iteration #2, type ICESTORM_LC: wirelen solved = 11, spread = 23, legal = 24; time = 0.00s
428s Info:     at iteration #2, type SB_GB: wirelen solved = 24, spread = 24, legal = 24; time = 0.00s
428s Info:     at iteration #2, type ALL: wirelen solved = 11, spread = 23, legal = 24; time = 0.00s
428s Info:     at iteration #3, type ICESTORM_LC: wirelen solved = 11, spread = 23, legal = 24; time = 0.00s
428s Info:     at iteration #3, type SB_GB: wirelen solved = 24, spread = 24, legal = 24; time = 0.00s
428s Info:     at iteration #3, type ALL: wirelen solved = 11, spread = 23, legal = 24; time = 0.00s
428s Info:     at iteration #4, type ICESTORM_LC: wirelen solved = 13, spread = 23, legal = 25; time = 0.00s
428s Info:     at iteration #4, type SB_GB: wirelen solved = 25, spread = 25, legal = 25; time = 0.00s
428s Info:     at iteration #4, type ALL: wirelen solved = 13, spread = 23, legal = 25; time = 0.00s
428s Info:     at iteration #5, type ICESTORM_LC: wirelen solved = 13, spread = 23, legal = 25; time = 0.00s
428s Info:     at iteration #5, type SB_GB: wirelen solved = 25, spread = 25, legal = 25; time = 0.00s
428s Info:     at iteration #5, type ALL: wirelen solved = 13, spread = 23, legal = 24; time = 0.00s
428s Info:     at iteration #6, type ICESTORM_LC: wirelen solved = 13, spread = 21, legal = 23; time = 0.00s
428s Info:     at iteration #6, type SB_GB: wirelen solved = 23, spread = 23, legal = 23; time = 0.00s
428s Info:     at iteration #6, type ALL: wirelen solved = 13, spread = 21, legal = 23; time = 0.00s
428s Info: HeAP Placer Time: 0.01s
428s Info:   of which solving equations: 0.01s
428s Info:   of which spreading cells: 0.00s
428s Info:   of which strict legalisation: 0.00s
428s 
428s Info: Running simulated annealing placer for refinement.
428s Info:   at iteration #1: temp = 0.000000, timing cost = 4, wirelen = 18
428s Info:   at iteration #4: temp = 0.000000, timing cost = 4, wirelen = 16 
428s Info: SA placement time 0.00s
428s 
428s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 173.73 MHz (PASS at 12.00 MHz)
428s 
428s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> <async>: 1.13 ns
428s 
428s Info: Slack histogram:
428s Info:  legend: * represents 1 endpoint(s)
428s Info:          + represents [1,1) endpoint(s)
428s Info: [ 77577,  77809) |** 
428s Info: [ 77809,  78041) | 
428s Info: [ 78041,  78273) |** 
428s Info: [ 78273,  78505) |** 
428s Info: [ 78505,  78737) |** 
428s Info: [ 78737,  78969) |** 
428s Info: [ 78969,  79201) | 
428s Info: [ 79201,  79433) |* 
428s Info: [ 79433,  79665) |** 
428s Info: [ 79665,  79897) |** 
428s Info: [ 79897,  80129) |** 
428s Info: [ 80129,  80361) |* 
428s Info: [ 80361,  80593) | 
428s Info: [ 80593,  80825) |** 
428s Info: [ 80825,  81057) |** 
428s Info: [ 81057,  81289) |** 
428s Info: [ 81289,  81521) | 
428s Info: [ 81521,  81753) |**** 
428s Info: [ 81753,  81985) |*************************** 
428s Info: [ 81985,  82217) |**** 
428s Info: Checksum: 0x26dcd3f5
428s 
428s Info: Routing..
428s Info: Setting up routing queue.
428s Info: Routing 93 arcs.
428s Info:            |   (re-)routed arcs  |   delta    | remaining|       time spent     |
428s Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|
428s Info:         93 |        0         72 |    0    72 |         0|       0.00       0.00|
428s Info: Routing complete.
428s Info: Router1 time 0.00s
428s Info: Checksum: 0xc09595e8
428s 
428s Info: Critical path report for clock 'clk$SB_IO_IN_$glb_clk' (posedge -> posedge):
428s Info: curr total
428s Info:  0.5  0.5  Source counter_SB_LUT4_I3_LC.O
428s Info:  0.6  1.1    Net counter[0] budget 78.740997 ns (11,2) -> (11,3)
428s Info:                Sink $nextpnr_ICESTORM_LC_0.I1
428s Info:                Defined in:
428s Info:                  example.v:19.14-19.25
428s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
428s Info:  0.3  1.4  Source $nextpnr_ICESTORM_LC_0.COUT
428s Info:  0.0  1.4    Net $nextpnr_ICESTORM_LC_0$O budget 0.000000 ns (11,3) -> (11,3)
428s Info:                Sink counter_SB_LUT4_I2_15_LC.CIN
428s Info:  0.1  1.5  Source counter_SB_LUT4_I2_15_LC.COUT
428s Info:  0.0  1.5    Net counter_SB_CARRY_CI_CO[2] budget 0.000000 ns (11,3) -> (11,3)
428s Info:                Sink counter_SB_LUT4_I2_8_LC.CIN
428s Info:                Defined in:
428s Info:                  example.v:19.14-19.25
428s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
428s Info:  0.1  1.6  Source counter_SB_LUT4_I2_8_LC.COUT
428s Info:  0.0  1.6    Net counter_SB_CARRY_CI_CO[3] budget 0.000000 ns (11,3) -> (11,3)
428s Info:                Sink counter_SB_LUT4_I2_7_LC.CIN
428s Info:                Defined in:
428s Info:                  example.v:19.14-19.25
428s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
428s Info:  0.1  1.8  Source counter_SB_LUT4_I2_7_LC.COUT
428s Info:  0.0  1.8    Net counter_SB_CARRY_CI_CO[4] budget 0.000000 ns (11,3) -> (11,3)
428s Info:                Sink counter_SB_LUT4_I2_6_LC.CIN
428s Info:                Defined in:
428s Info:                  example.v:19.14-19.25
428s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
428s Info:  0.1  1.9  Source counter_SB_LUT4_I2_6_LC.COUT
428s Info:  0.0  1.9    Net counter_SB_CARRY_CI_CO[5] budget 0.000000 ns (11,3) -> (11,3)
428s Info:                Sink counter_SB_LUT4_I2_5_LC.CIN
428s Info:                Defined in:
428s Info:                  example.v:19.14-19.25
428s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
428s Info:  0.1  2.0  Source counter_SB_LUT4_I2_5_LC.COUT
428s Info:  0.0  2.0    Net counter_SB_CARRY_CI_CO[6] budget 0.000000 ns (11,3) -> (11,3)
428s Info:                Sink counter_SB_LUT4_I2_4_LC.CIN
428s Info:                Defined in:
428s Info:                  example.v:19.14-19.25
428s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
428s Info:  0.1  2.1  Source counter_SB_LUT4_I2_4_LC.COUT
428s Info:  0.0  2.1    Net counter_SB_CARRY_CI_CO[7] budget 0.000000 ns (11,3) -> (11,3)
428s Info:                Sink counter_SB_LUT4_I2_3_LC.CIN
428s Info:                Defined in:
428s Info:                  example.v:19.14-19.25
428s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
428s Info:  0.1  2.3  Source counter_SB_LUT4_I2_3_LC.COUT
428s Info:  0.2  2.5    Net counter_SB_CARRY_CI_CO[8] budget 0.190000 ns (11,3) -> (11,4)
428s Info:                Sink counter_SB_LUT4_I2_2_LC.CIN
428s icetime -d hx1k -mtr example.rpt example.asc
428s // Reading input .asc file..
428s // Reading 1k chipdb file..
428s Info:                Defined in:
428s Info:                  example.v:19.14-19.25
428s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
428s Info:  0.1  2.6  Source counter_SB_LUT4_I2_2_LC.COUT
428s Info:  0.0  2.6    Net counter_SB_CARRY_CI_CO[9] budget 0.000000 ns (11,4) -> (11,4)
428s Info:                Sink counter_SB_LUT4_I2_1_LC.CIN
428s Info:                Defined in:
428s Info:                  example.v:19.14-19.25
428s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
428s Info:  0.1  2.7  Source counter_SB_LUT4_I2_1_LC.COUT
428s Info:  0.0  2.7    Net counter_SB_CARRY_CI_CO[10] budget 0.000000 ns (11,4) -> (11,4)
428s Info:                Sink counter_SB_LUT4_I2_LC.CIN
428s Info:                Defined in:
428s Info:                  example.v:19.14-19.25
428s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
428s Info:  0.1  2.8  Source counter_SB_LUT4_I2_LC.COUT
428s Info:  0.0  2.8    Net counter_SB_CARRY_CI_CO[11] budget 0.000000 ns (11,4) -> (11,4)
428s Info:                Sink counter_SB_LUT4_I2_24_LC.CIN
428s Info:                Defined in:
428s Info:                  example.v:19.14-19.25
428s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
428s Info:  0.1  3.0  Source counter_SB_LUT4_I2_24_LC.COUT
428s Info:  0.0  3.0    Net counter_SB_CARRY_CI_CO[12] budget 0.000000 ns (11,4) -> (11,4)
428s Info:                Sink counter_SB_LUT4_I2_23_LC.CIN
428s Info:                Defined in:
428s Info:                  example.v:19.14-19.25
428s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
428s Info:  0.1  3.1  Source counter_SB_LUT4_I2_23_LC.COUT
428s Info:  0.0  3.1    Net counter_SB_CARRY_CI_CO[13] budget 0.000000 ns (11,4) -> (11,4)
428s Info:                Sink counter_SB_LUT4_I2_22_LC.CIN
428s Info:                Defined in:
428s Info:                  example.v:19.14-19.25
428s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
428s Info:  0.1  3.2  Source counter_SB_LUT4_I2_22_LC.COUT
428s Info:  0.0  3.2    Net counter_SB_CARRY_CI_CO[14] budget 0.000000 ns (11,4) -> (11,4)
428s Info:                Sink counter_SB_LUT4_I2_21_LC.CIN
428s Info:                Defined in:
428s Info:                  example.v:19.14-19.25
428s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
428s Info:  0.1  3.3  Source counter_SB_LUT4_I2_21_LC.COUT
428s Info:  0.0  3.3    Net counter_SB_CARRY_CI_CO[15] budget 0.000000 ns (11,4) -> (11,4)
428s Info:                Sink counter_SB_LUT4_I2_20_LC.CIN
428s Info:                Defined in:
428s Info:                  example.v:19.14-19.25
428s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
428s Info:  0.1  3.5  Source counter_SB_LUT4_I2_20_LC.COUT
428s Info:  0.2  3.7    Net counter_SB_CARRY_CI_CO[16] budget 0.190000 ns (11,4) -> (11,5)
428s Info:                Sink counter_SB_LUT4_I2_19_LC.CIN
428s Info:                Defined in:
428s Info:                  example.v:19.14-19.25
428s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
428s Info:  0.1  3.8  Source counter_SB_LUT4_I2_19_LC.COUT
428s Info:  0.0  3.8    Net counter_SB_CARRY_CI_CO[17] budget 0.000000 ns (11,5) -> (11,5)
428s Info:                Sink counter_SB_LUT4_I2_18_LC.CIN
428s Info:                Defined in:
428s Info:                  example.v:19.14-19.25
428s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
428s Info:  0.1  3.9  Source counter_SB_LUT4_I2_18_LC.COUT
428s Info:  0.0  3.9    Net counter_SB_CARRY_CI_CO[18] budget 0.000000 ns (11,5) -> (11,5)
428s Info:                Sink counter_SB_LUT4_I2_17_LC.CIN
428s Info:                Defined in:
428s Info:                  example.v:19.14-19.25
428s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
428s Info:  0.1  4.0  Source counter_SB_LUT4_I2_17_LC.COUT
428s Info:  0.0  4.0    Net counter_SB_CARRY_CI_CO[19] budget 0.000000 ns (11,5) -> (11,5)
428s Info:                Sink counter_SB_LUT4_I2_16_LC.CIN
428s Info:                Defined in:
428s Info:                  example.v:19.14-19.25
428s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
428s Info:  0.1  4.2  Source counter_SB_LUT4_I2_16_LC.COUT
428s Info:  0.0  4.2    Net counter_SB_CARRY_CI_CO[20] budget 0.000000 ns (11,5) -> (11,5)
428s Info:                Sink counter_SB_LUT4_I2_14_LC.CIN
428s Info:                Defined in:
428s Info:                  example.v:19.14-19.25
428s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
428s Info:  0.1  4.3  Source counter_SB_LUT4_I2_14_LC.COUT
428s Info:  0.0  4.3    Net counter_SB_CARRY_CI_CO[21] budget 0.000000 ns (11,5) -> (11,5)
428s Info:                Sink counter_SB_LUT4_I2_13_LC.CIN
428s Info:                Defined in:
428s Info:                  example.v:19.14-19.25
428s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
428s Info:  0.1  4.4  Source counter_SB_LUT4_I2_13_LC.COUT
428s Info:  0.0  4.4    Net counter_SB_CARRY_CI_CO[22] budget 0.000000 ns (11,5) -> (11,5)
428s Info:                Sink counter_SB_LUT4_I2_12_LC.CIN
428s Info:                Defined in:
428s Info:                  example.v:19.14-19.25
428s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
428s Info:  0.1  4.6  Source counter_SB_LUT4_I2_12_LC.COUT
428s Info:  0.0  4.6    Net counter_SB_CARRY_CI_CO[23] budget 0.000000 ns (11,5) -> (11,5)
428s Info:                Sink counter_SB_LUT4_I2_11_LC.CIN
428s Info:                Defined in:
428s Info:                  example.v:19.14-19.25
428s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
428s Info:  0.1  4.7  Source counter_SB_LUT4_I2_11_LC.COUT
428s Info:  0.2  4.9    Net counter_SB_CARRY_CI_CO[24] budget 0.190000 ns (11,5) -> (11,6)
428s Info:                Sink counter_SB_LUT4_I2_10_LC.CIN
428s Info:                Defined in:
428s Info:                  example.v:19.14-19.25
428s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
428s Info:  0.1  5.0  Source counter_SB_LUT4_I2_10_LC.COUT
428s Info:  0.3  5.3    Net counter_SB_CARRY_CI_CO[25] budget 0.260000 ns (11,6) -> (11,6)
428s Info:                Sink counter_SB_LUT4_I2_9_LC.I3
428s Info:                Defined in:
428s Info:                  example.v:19.14-19.25
428s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
428s Info:  0.3  5.6  Setup counter_SB_LUT4_I2_9_LC.I3
428s Info: 4.2 ns logic, 1.4 ns routing
428s 
428s Info: Critical path report for cross-domain path 'posedge clk$SB_IO_IN_$glb_clk' -> '<async>':
428s Info: curr total
428s Info:  0.5  0.5  Source LED2_SB_DFF_Q_DFFLC.O
428s Info:  0.6  1.1    Net LED2$SB_IO_OUT budget 82.792999 ns (12,6) -> (13,7)
428s Info:                Sink LED2$sb_io.D_OUT_0
428s Info:                Defined in:
428s Info:                  example.v:16.17-16.23
428s Info: 0.5 ns logic, 0.6 ns routing
428s 
428s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 178.76 MHz (PASS at 12.00 MHz)
428s 
428s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> <async>: 1.13 ns
428s 
428s Info: Slack histogram:
428s Info:  legend: * represents 1 endpoint(s)
428s Info:          + represents [1,1) endpoint(s)
428s Info: [ 77739,  77963) |** 
428s Info: [ 77963,  78187) | 
428s Info: [ 78187,  78411) |** 
428s Info: [ 78411,  78635) |** 
428s Info: [ 78635,  78859) |** 
428s Info: [ 78859,  79083) |** 
428s Info: [ 79083,  79307) | 
428s Info: [ 79307,  79531) |** 
428s Info: [ 79531,  79755) |* 
428s Info: [ 79755,  79979) |** 
428s Info: [ 79979,  80203) |*** 
428s Info: [ 80203,  80427) | 
428s Info: [ 80427,  80651) |* 
428s Info: [ 80651,  80875) |** 
428s Info: [ 80875,  81099) |* 
428s Info: [ 81099,  81323) |** 
428s Info: [ 81323,  81547) | 
428s Info: [ 81547,  81771) |**** 
428s Info: [ 81771,  81995) |*************************** 
428s Info: [ 81995,  82219) |**** 
428s 
428s Info: Program finished normally.
428s // Creating timing netlist..
428s // Timing estimate: 5.58 ns (179.07 MHz)
428s icepack example.asc example.bin
428s rm example.asc example.json
428s make: Leaving directory '/tmp/autopkgtest.eGJMaA/build.OQp/src/examples/iceblink'
428s make: Entering directory '/tmp/autopkgtest.eGJMaA/build.OQp/src/examples/icebreaker'
428s yosys -p 'synth_ice40 -top top -json example.json' example.v
428s 
428s  /----------------------------------------------------------------------------\
428s  |                                                                            |
428s  |  yosys -- Yosys Open SYnthesis Suite                                       |
428s  |                                                                            |
428s  |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
428s  |                                                                            |
428s  |  Permission to use, copy, modify, and/or distribute this software for any  |
428s  |  purpose with or without fee is hereby granted, provided that the above    |
428s  |  copyright notice and this permission notice appear in all copies.         |
428s  |                                                                            |
428s  |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
428s  |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
428s  |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
428s  |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
428s  |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
428s  |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
428s  |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
428s  |                                                                            |
428s  \----------------------------------------------------------------------------/
428s 
428s  Yosys 0.33 (git sha1 2584903a060)
428s 
428s 
428s -- Parsing `example.v' using frontend ` -vlog2k' --
428s 
428s 1. Executing Verilog-2005 frontend: example.v
428s Parsing Verilog input from `example.v' to AST representation.
428s Storing AST representation for module `$abstract\top'.
428s Successfully finished Verilog frontend.
428s 
428s -- Running command `synth_ice40 -top top -json example.json' --
428s 
428s 2. Executing SYNTH_ICE40 pass.
428s 
428s 2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v
428s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation.
428s Generating RTLIL representation for module `\SB_IO'.
428s Generating RTLIL representation for module `\SB_GB_IO'.
428s Generating RTLIL representation for module `\SB_GB'.
428s Generating RTLIL representation for module `\SB_LUT4'.
428s Generating RTLIL representation for module `\SB_CARRY'.
428s Generating RTLIL representation for module `\SB_DFF'.
428s Generating RTLIL representation for module `\SB_DFFE'.
428s Generating RTLIL representation for module `\SB_DFFSR'.
428s Generating RTLIL representation for module `\SB_DFFR'.
428s Generating RTLIL representation for module `\SB_DFFSS'.
428s Generating RTLIL representation for module `\SB_DFFS'.
428s Generating RTLIL representation for module `\SB_DFFESR'.
428s Generating RTLIL representation for module `\SB_DFFER'.
428s Generating RTLIL representation for module `\SB_DFFESS'.
428s Generating RTLIL representation for module `\SB_DFFES'.
428s Generating RTLIL representation for module `\SB_DFFN'.
428s Generating RTLIL representation for module `\SB_DFFNE'.
428s Generating RTLIL representation for module `\SB_DFFNSR'.
428s Generating RTLIL representation for module `\SB_DFFNR'.
428s Generating RTLIL representation for module `\SB_DFFNSS'.
428s Generating RTLIL representation for module `\SB_DFFNS'.
428s Generating RTLIL representation for module `\SB_DFFNESR'.
428s Generating RTLIL representation for module `\SB_DFFNER'.
428s Generating RTLIL representation for module `\SB_DFFNESS'.
428s Generating RTLIL representation for module `\SB_DFFNES'.
428s Generating RTLIL representation for module `\SB_RAM40_4K'.
428s Generating RTLIL representation for module `\SB_RAM40_4KNR'.
428s Generating RTLIL representation for module `\SB_RAM40_4KNW'.
428s Generating RTLIL representation for module `\SB_RAM40_4KNRNW'.
428s Generating RTLIL representation for module `\ICESTORM_LC'.
428s Generating RTLIL representation for module `\SB_PLL40_CORE'.
428s Generating RTLIL representation for module `\SB_PLL40_PAD'.
428s Generating RTLIL representation for module `\SB_PLL40_2_PAD'.
428s Generating RTLIL representation for module `\SB_PLL40_2F_CORE'.
428s Generating RTLIL representation for module `\SB_PLL40_2F_PAD'.
428s Generating RTLIL representation for module `\SB_WARMBOOT'.
428s Generating RTLIL representation for module `\SB_SPRAM256KA'.
428s Generating RTLIL representation for module `\SB_HFOSC'.
428s Generating RTLIL representation for module `\SB_LFOSC'.
428s Generating RTLIL representation for module `\SB_RGBA_DRV'.
428s Generating RTLIL representation for module `\SB_LED_DRV_CUR'.
428s Generating RTLIL representation for module `\SB_RGB_DRV'.
428s Generating RTLIL representation for module `\SB_I2C'.
428s Generating RTLIL representation for module `\SB_SPI'.
428s Generating RTLIL representation for module `\SB_LEDDA_IP'.
428s Generating RTLIL representation for module `\SB_FILTER_50NS'.
428s Generating RTLIL representation for module `\SB_IO_I3C'.
428s Generating RTLIL representation for module `\SB_IO_OD'.
428s Generating RTLIL representation for module `\SB_MAC16'.
428s Generating RTLIL representation for module `\ICESTORM_RAM'.
428s Successfully finished Verilog frontend.
428s 
428s 2.2. Executing HIERARCHY pass (managing design hierarchy).
428s 
428s 2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\top'.
428s Generating RTLIL representation for module `\top'.
428s 
428s 2.3.1. Analyzing design hierarchy..
428s Top module:  \top
428s 
428s 2.3.2. Analyzing design hierarchy..
428s Top module:  \top
428s Removing unused module `$abstract\top'.
428s Removed 1 unused modules.
428s 
428s 2.4. Executing PROC pass (convert processes to netlists).
428s 
428s 2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
428s Cleaned up 0 empty switches.
428s 
428s 2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
428s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241 in module SB_DFFNES.
428s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234 in module SB_DFFNESS.
428s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230 in module SB_DFFNER.
428s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223 in module SB_DFFNESR.
428s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220 in module SB_DFFNS.
428s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217 in module SB_DFFNSS.
428s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214 in module SB_DFFNR.
428s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211 in module SB_DFFNSR.
428s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203 in module SB_DFFES.
428s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196 in module SB_DFFESS.
428s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192 in module SB_DFFER.
428s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185 in module SB_DFFESR.
428s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182 in module SB_DFFS.
428s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179 in module SB_DFFSS.
428s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176 in module SB_DFFR.
428s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173 in module SB_DFFSR.
428s Removed a total of 0 dead cases.
428s 
428s 2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
428s Removed 8 redundant assignments.
428s Promoted 25 assignments to connections.
428s 
428s 2.4.4. Executing PROC_INIT pass (extract init attributes).
428s Found init rule in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'.
428s   Set init value: \Q = 1'0
428s Found init rule in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'.
428s   Set init value: \Q = 1'0
428s Found init rule in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'.
428s   Set init value: \Q = 1'0
428s Found init rule in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'.
428s   Set init value: \Q = 1'0
428s Found init rule in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'.
428s   Set init value: \Q = 1'0
428s Found init rule in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'.
428s   Set init value: \Q = 1'0
428s Found init rule in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'.
428s   Set init value: \Q = 1'0
428s Found init rule in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'.
428s   Set init value: \Q = 1'0
428s Found init rule in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'.
428s   Set init value: \Q = 1'0
428s Found init rule in `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'.
428s   Set init value: \Q = 1'0
428s Found init rule in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'.
428s   Set init value: \Q = 1'0
428s Found init rule in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'.
428s   Set init value: \Q = 1'0
428s Found init rule in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'.
428s   Set init value: \Q = 1'0
428s Found init rule in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'.
428s   Set init value: \Q = 1'0
428s Found init rule in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'.
428s   Set init value: \Q = 1'0
428s Found init rule in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'.
428s   Set init value: \Q = 1'0
428s Found init rule in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'.
428s   Set init value: \Q = 1'0
428s Found init rule in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'.
428s   Set init value: \Q = 1'0
428s Found init rule in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'.
428s   Set init value: \Q = 1'0
428s Found init rule in `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'.
428s   Set init value: \Q = 1'0
428s Found init rule in `\top.$proc$example.v:25$393'.
428s   Set init value: \counter = 27'000000000000000000000000000
428s 
428s 2.4.5. Executing PROC_ARST pass (detect async resets in processes).
428s Found async reset \S in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
428s Found async reset \R in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
428s Found async reset \S in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
428s Found async reset \R in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
428s Found async reset \S in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
428s Found async reset \R in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
428s Found async reset \S in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'.
428s Found async reset \R in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'.
428s 
428s 2.4.6. Executing PROC_ROM pass (convert switches to ROMs).
428s Converted 0 switches.
428s <suppressed ~18 debug messages>
428s 
428s 2.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
428s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'.
428s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
428s      1/1: $0\Q[0:0]
428s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'.
428s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
428s      1/1: $0\Q[0:0]
428s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'.
428s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
428s      1/1: $0\Q[0:0]
428s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'.
428s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
428s      1/1: $0\Q[0:0]
428s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'.
428s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
428s      1/1: $0\Q[0:0]
428s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'.
428s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
428s      1/1: $0\Q[0:0]
428s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'.
428s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
428s      1/1: $0\Q[0:0]
428s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'.
428s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'.
428s      1/1: $0\Q[0:0]
428s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'.
428s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'.
428s      1/1: $0\Q[0:0]
428s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'.
428s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'.
428s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'.
428s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
428s      1/1: $0\Q[0:0]
428s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'.
428s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'.
428s      1/1: $0\Q[0:0]
428s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'.
428s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
428s      1/1: $0\Q[0:0]
428s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'.
428s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'.
428s      1/1: $0\Q[0:0]
428s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'.
428s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'.
428s      1/1: $0\Q[0:0]
428s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'.
428s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'.
428s      1/1: $0\Q[0:0]
428s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'.
428s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'.
428s      1/1: $0\Q[0:0]
428s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'.
428s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'.
428s      1/1: $0\Q[0:0]
428s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'.
428s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'.
428s      1/1: $0\Q[0:0]
428s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'.
428s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'.
428s Creating decoders for process `\top.$proc$example.v:25$393'.
428s Creating decoders for process `\top.$proc$example.v:28$381'.
428s 
428s 2.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
428s 
428s 2.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
429s Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
429s   created $adff cell `$procdff$438' with negative edge clock and positive level reset.
429s Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
429s   created $dff cell `$procdff$439' with negative edge clock.
429s Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
429s   created $adff cell `$procdff$440' with negative edge clock and positive level reset.
429s Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
429s   created $dff cell `$procdff$441' with negative edge clock.
429s Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
429s   created $adff cell `$procdff$442' with negative edge clock and positive level reset.
429s Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
429s   created $dff cell `$procdff$443' with negative edge clock.
429s Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
429s   created $adff cell `$procdff$444' with negative edge clock and positive level reset.
429s Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'.
429s   created $dff cell `$procdff$445' with negative edge clock.
429s Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'.
429s   created $dff cell `$procdff$446' with negative edge clock.
429s Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'.
429s   created $dff cell `$procdff$447' with negative edge clock.
429s Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
429s   created $adff cell `$procdff$448' with positive edge clock and positive level reset.
429s Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'.
429s   created $dff cell `$procdff$449' with positive edge clock.
429s Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
429s   created $adff cell `$procdff$450' with positive edge clock and positive level reset.
429s Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'.
429s   created $dff cell `$procdff$451' with positive edge clock.
429s Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'.
429s   created $adff cell `$procdff$452' with positive edge clock and positive level reset.
429s Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'.
429s   created $dff cell `$procdff$453' with positive edge clock.
429s Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'.
429s   created $adff cell `$procdff$454' with positive edge clock and positive level reset.
429s Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'.
429s   created $dff cell `$procdff$455' with positive edge clock.
429s Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'.
429s   created $dff cell `$procdff$456' with positive edge clock.
429s Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'.
429s   created $dff cell `$procdff$457' with positive edge clock.
429s Creating register for signal `\top.\counter' using process `\top.$proc$example.v:28$381'.
429s   created $dff cell `$procdff$458' with positive edge clock.
429s Creating register for signal `\top.\outcnt' using process `\top.$proc$example.v:28$381'.
429s   created $dff cell `$procdff$459' with positive edge clock.
429s 
429s 2.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
429s 
429s 2.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
429s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'.
429s Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
429s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
429s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'.
429s Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
429s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
429s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'.
429s Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
429s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
429s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'.
429s Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
429s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
429s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'.
429s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
429s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'.
429s Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
429s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
429s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'.
429s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
429s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'.
429s Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'.
429s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'.
429s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'.
429s Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'.
429s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'.
429s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'.
429s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'.
429s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'.
429s Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
429s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
429s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'.
429s Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'.
429s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'.
429s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'.
429s Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
429s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
429s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'.
429s Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'.
429s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'.
429s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'.
429s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'.
429s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'.
429s Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'.
429s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'.
429s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'.
429s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'.
429s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'.
429s Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'.
429s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'.
429s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'.
429s Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'.
429s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'.
429s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'.
429s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'.
429s Removing empty process `top.$proc$example.v:25$393'.
429s Removing empty process `top.$proc$example.v:28$381'.
429s Cleaned up 18 empty switches.
429s 
429s 2.4.12. Executing OPT_EXPR pass (perform const folding).
429s Optimizing module top.
429s <suppressed ~3 debug messages>
429s 
429s 2.5. Executing FLATTEN pass (flatten design).
429s 
429s 2.6. Executing TRIBUF pass.
429s 
429s 2.7. Executing DEMINOUT pass (demote inout ports to input or output).
429s 
429s 2.8. Executing OPT_EXPR pass (perform const folding).
429s Optimizing module top.
429s 
429s 2.9. Executing OPT_CLEAN pass (remove unused cells and wires).
429s Finding unused cells or wires in module \top..
429s Removed 0 unused cells and 7 unused wires.
429s <suppressed ~1 debug messages>
429s 
429s 2.10. Executing CHECK pass (checking for obvious problems).
429s Checking module top...
429s Found and reported 0 problems.
429s 
429s 2.11. Executing OPT pass (performing simple optimizations).
429s 
429s 2.11.1. Executing OPT_EXPR pass (perform const folding).
429s Optimizing module top.
429s 
429s 2.11.2. Executing OPT_MERGE pass (detect identical cells).
429s Finding identical cells in module `\top'.
429s Removed a total of 0 cells.
429s 
429s 2.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
429s Running muxtree optimizer on module \top..
429s   Creating internal representation of mux trees.
429s   No muxes found in this module.
429s Removed 0 multiplexer ports.
429s 
429s 2.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
429s   Optimizing cells in module \top.
429s Performed a total of 0 changes.
429s 
429s 2.11.5. Executing OPT_MERGE pass (detect identical cells).
429s Finding identical cells in module `\top'.
429s Removed a total of 0 cells.
429s 
429s 2.11.6. Executing OPT_DFF pass (perform DFF optimizations).
429s 
429s 2.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
429s Finding unused cells or wires in module \top..
429s 
429s 2.11.8. Executing OPT_EXPR pass (perform const folding).
429s Optimizing module top.
429s 
429s 2.11.9. Finished OPT passes. (There is nothing left to do.)
429s 
429s 2.12. Executing FSM pass (extract and optimize FSM).
429s 
429s 2.12.1. Executing FSM_DETECT pass (finding FSMs in design).
429s 
429s 2.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).
429s 
429s 2.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).
429s 
429s 2.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
429s Finding unused cells or wires in module \top..
429s 
429s 2.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).
429s 
429s 2.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
429s 
429s 2.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
429s 
429s 2.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
429s 
429s 2.13. Executing OPT pass (performing simple optimizations).
429s 
429s 2.13.1. Executing OPT_EXPR pass (perform const folding).
429s Optimizing module top.
429s 
429s 2.13.2. Executing OPT_MERGE pass (detect identical cells).
429s Finding identical cells in module `\top'.
429s Removed a total of 0 cells.
429s 
429s 2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
429s Running muxtree optimizer on module \top..
429s   Creating internal representation of mux trees.
429s   No muxes found in this module.
429s Removed 0 multiplexer ports.
429s 
429s 2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
429s   Optimizing cells in module \top.
429s Performed a total of 0 changes.
429s 
429s 2.13.5. Executing OPT_MERGE pass (detect identical cells).
429s Finding identical cells in module `\top'.
429s Removed a total of 0 cells.
429s 
429s 2.13.6. Executing OPT_DFF pass (perform DFF optimizations).
429s 
429s 2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
429s Finding unused cells or wires in module \top..
429s 
429s 2.13.8. Executing OPT_EXPR pass (perform const folding).
429s Optimizing module top.
429s 
429s 2.13.9. Finished OPT passes. (There is nothing left to do.)
429s 
429s 2.14. Executing WREDUCE pass (reducing word size of cells).
429s Removed top 31 bits (of 32) from port B of cell top.$add$example.v:29$382 ($add).
429s Removed top 5 bits (of 32) from port Y of cell top.$add$example.v:29$382 ($add).
429s Removed top 1 bits (of 5) from port B of cell top.$xor$example.v:33$385 ($xor).
429s Removed top 1 bits (of 2) from port A of cell top.$add$example.v:35$387 ($add).
429s Removed top 30 bits (of 32) from port A of cell top.$shl$example.v:38$392 ($shl).
429s Removed top 28 bits (of 32) from port B of cell top.$shl$example.v:38$392 ($shl).
429s Removed top 16 bits (of 32) from port Y of cell top.$shl$example.v:38$392 ($shl).
429s Removed top 1 bits (of 2) from wire top.$logic_not$example.v:35$386_Y.
429s Removed top 16 bits (of 32) from wire top.$shl$example.v:38$392_Y.
429s 
429s 2.15. Executing PEEPOPT pass (run peephole optimizers).
429s 
429s 2.16. Executing OPT_CLEAN pass (remove unused cells and wires).
429s Finding unused cells or wires in module \top..
429s Removed 0 unused cells and 4 unused wires.
429s <suppressed ~1 debug messages>
429s 
429s 2.17. Executing SHARE pass (SAT-based resource sharing).
429s 
429s 2.18. Executing TECHMAP pass (map to technology primitives).
429s 
429s 2.18.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v
429s Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation.
429s Generating RTLIL representation for module `\_90_lut_cmp_'.
429s Successfully finished Verilog frontend.
429s 
429s 2.18.2. Continuing TECHMAP pass.
429s No more expansions possible.
429s <suppressed ~6 debug messages>
429s 
429s 2.19. Executing OPT_EXPR pass (perform const folding).
429s Optimizing module top.
429s 
429s 2.20. Executing OPT_CLEAN pass (remove unused cells and wires).
429s Finding unused cells or wires in module \top..
429s 
429s 2.21. Executing ALUMACC pass (create $alu and $macc cells).
429s Extracting $alu and $macc cells in module top:
429s   creating $macc model for $add$example.v:29$382 ($add).
429s   creating $macc model for $add$example.v:35$387 ($add).
429s   creating $macc model for $add$example.v:35$388 ($add).
429s   creating $macc model for $add$example.v:35$389 ($add).
429s   merging $macc model for $add$example.v:35$388 into $add$example.v:35$389.
429s   merging $macc model for $add$example.v:35$387 into $add$example.v:35$389.
429s   creating $alu model for $macc $add$example.v:29$382.
429s   creating $macc cell for $add$example.v:35$389: $auto$alumacc.cc:365:replace_macc$463
429s   creating $alu cell for $add$example.v:29$382: $auto$alumacc.cc:485:replace_alu$464
429s   created 1 $alu and 1 $macc cells.
429s 
429s 2.22. Executing OPT pass (performing simple optimizations).
429s 
429s 2.22.1. Executing OPT_EXPR pass (perform const folding).
429s Optimizing module top.
429s 
429s 2.22.2. Executing OPT_MERGE pass (detect identical cells).
429s Finding identical cells in module `\top'.
429s Removed a total of 0 cells.
429s 
429s 2.22.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
429s Running muxtree optimizer on module \top..
429s   Creating internal representation of mux trees.
429s   No muxes found in this module.
429s Removed 0 multiplexer ports.
429s 
429s 2.22.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
429s   Optimizing cells in module \top.
429s Performed a total of 0 changes.
429s 
429s 2.22.5. Executing OPT_MERGE pass (detect identical cells).
429s Finding identical cells in module `\top'.
429s Removed a total of 0 cells.
429s 
429s 2.22.6. Executing OPT_DFF pass (perform DFF optimizations).
429s 
429s 2.22.7. Executing OPT_CLEAN pass (remove unused cells and wires).
429s Finding unused cells or wires in module \top..
429s Removed 2 unused cells and 2 unused wires.
429s <suppressed ~3 debug messages>
429s 
429s 2.22.8. Executing OPT_EXPR pass (perform const folding).
429s Optimizing module top.
429s 
429s 2.22.9. Rerunning OPT passes. (Maybe there is more to do..)
429s 
429s 2.22.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
429s Running muxtree optimizer on module \top..
429s   Creating internal representation of mux trees.
429s   No muxes found in this module.
429s Removed 0 multiplexer ports.
429s 
429s 2.22.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
429s   Optimizing cells in module \top.
429s Performed a total of 0 changes.
429s 
429s 2.22.12. Executing OPT_MERGE pass (detect identical cells).
429s Finding identical cells in module `\top'.
429s Removed a total of 0 cells.
429s 
429s 2.22.13. Executing OPT_DFF pass (perform DFF optimizations).
429s 
429s 2.22.14. Executing OPT_CLEAN pass (remove unused cells and wires).
429s Finding unused cells or wires in module \top..
429s 
429s 2.22.15. Executing OPT_EXPR pass (perform const folding).
429s Optimizing module top.
429s 
429s 2.22.16. Finished OPT passes. (There is nothing left to do.)
429s 
429s 2.23. Executing MEMORY pass.
429s 
429s 2.23.1. Executing OPT_MEM pass (optimize memories).
429s Performed a total of 0 transformations.
429s 
429s 2.23.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
429s Performed a total of 0 transformations.
429s 
429s 2.23.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
429s 
429s 2.23.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
429s 
429s 2.23.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
429s 
429s 2.23.6. Executing OPT_CLEAN pass (remove unused cells and wires).
429s Finding unused cells or wires in module \top..
429s 
429s 2.23.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
429s 
429s 2.23.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
429s Performed a total of 0 transformations.
429s 
429s 2.23.9. Executing OPT_CLEAN pass (remove unused cells and wires).
429s Finding unused cells or wires in module \top..
429s 
429s 2.23.10. Executing MEMORY_COLLECT pass (generating $mem cells).
429s 
429s 2.24. Executing OPT_CLEAN pass (remove unused cells and wires).
429s Finding unused cells or wires in module \top..
429s 
429s 2.25. Executing MEMORY_LIBMAP pass (mapping memories to cells).
429s 
429s 2.26. Executing TECHMAP pass (map to technology primitives).
429s 
429s 2.26.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v
429s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation.
429s Generating RTLIL representation for module `\$__ICE40_RAM4K_'.
429s Successfully finished Verilog frontend.
429s 
429s 2.26.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/spram_map.v
429s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/spram_map.v' to AST representation.
429s Generating RTLIL representation for module `\$__ICE40_SPRAM_'.
429s Successfully finished Verilog frontend.
429s 
429s 2.26.3. Continuing TECHMAP pass.
429s No more expansions possible.
429s <suppressed ~4 debug messages>
429s 
429s 2.27. Executing ICE40_BRAMINIT pass.
429s 
429s 2.28. Executing OPT pass (performing simple optimizations).
429s 
429s 2.28.1. Executing OPT_EXPR pass (perform const folding).
429s Optimizing module top.
429s <suppressed ~5 debug messages>
429s 
429s 2.28.2. Executing OPT_MERGE pass (detect identical cells).
429s Finding identical cells in module `\top'.
429s Removed a total of 0 cells.
429s 
429s 2.28.3. Executing OPT_DFF pass (perform DFF optimizations).
429s 
429s 2.28.4. Executing OPT_CLEAN pass (remove unused cells and wires).
429s Finding unused cells or wires in module \top..
429s Removed 0 unused cells and 2 unused wires.
429s <suppressed ~1 debug messages>
429s 
429s 2.28.5. Finished fast OPT passes.
429s 
429s 2.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
429s 
429s 2.30. Executing OPT pass (performing simple optimizations).
429s 
429s 2.30.1. Executing OPT_EXPR pass (perform const folding).
429s Optimizing module top.
429s 
429s 2.30.2. Executing OPT_MERGE pass (detect identical cells).
429s Finding identical cells in module `\top'.
429s Removed a total of 0 cells.
429s 
429s 2.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
429s Running muxtree optimizer on module \top..
429s   Creating internal representation of mux trees.
429s   No muxes found in this module.
429s Removed 0 multiplexer ports.
429s 
429s 2.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
429s   Optimizing cells in module \top.
429s Performed a total of 0 changes.
429s 
429s 2.30.5. Executing OPT_MERGE pass (detect identical cells).
429s Finding identical cells in module `\top'.
429s Removed a total of 0 cells.
429s 
429s 2.30.6. Executing OPT_DFF pass (perform DFF optimizations).
429s 
429s 2.30.7. Executing OPT_CLEAN pass (remove unused cells and wires).
429s Finding unused cells or wires in module \top..
429s 
429s 2.30.8. Executing OPT_EXPR pass (perform const folding).
429s Optimizing module top.
429s 
429s 2.30.9. Finished OPT passes. (There is nothing left to do.)
429s 
429s 2.31. Executing ICE40_WRAPCARRY pass (wrap carries).
429s 
429s 2.32. Executing TECHMAP pass (map to technology primitives).
429s 
429s 2.32.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v
429s Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation.
429s Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
429s Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
429s Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
429s Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
429s Generating RTLIL representation for module `\_90_simplemap_various'.
429s Generating RTLIL representation for module `\_90_simplemap_registers'.
429s Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
429s Generating RTLIL representation for module `\_90_shift_shiftx'.
429s Generating RTLIL representation for module `\_90_fa'.
429s Generating RTLIL representation for module `\_90_lcu'.
429s Generating RTLIL representation for module `\_90_alu'.
429s Generating RTLIL representation for module `\_90_macc'.
429s Generating RTLIL representation for module `\_90_alumacc'.
429s Generating RTLIL representation for module `\$__div_mod_u'.
429s Generating RTLIL representation for module `\$__div_mod_trunc'.
429s Generating RTLIL representation for module `\_90_div'.
429s Generating RTLIL representation for module `\_90_mod'.
429s Generating RTLIL representation for module `\$__div_mod_floor'.
429s Generating RTLIL representation for module `\_90_divfloor'.
429s Generating RTLIL representation for module `\_90_modfloor'.
429s Generating RTLIL representation for module `\_90_pow'.
429s Generating RTLIL representation for module `\_90_pmux'.
429s Generating RTLIL representation for module `\_90_demux'.
429s Generating RTLIL representation for module `\_90_lut'.
429s Successfully finished Verilog frontend.
429s 
429s 2.32.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v
429s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation.
429s Generating RTLIL representation for module `\_80_ice40_alu'.
429s Successfully finished Verilog frontend.
429s 
429s 2.32.3. Continuing TECHMAP pass.
429s Using extmapper simplemap for cells of type $logic_not.
429s Using extmapper simplemap for cells of type $xor.
429s Using template $paramod$956e79e8f8c5e64be7438155ae50a966e615cb04\_80_ice40_alu for cells of type $alu.
429s Using extmapper simplemap for cells of type $not.
429s Using template $paramod$constmap:f945af24096ed3206033d697a5f345ea84ab075f$paramod$d3ce4eff4c23b767bd4a7404eae2f700b29e45d1\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
429s Using extmapper maccmap for cells of type $macc.
429s   add bits { \BTN1 \BTN2 \BTN3 $auto$wreduce.cc:461:run$460 [0] } (4 bits)
429s   packed 1 (1) bits / 1 words into adder tree
429s Using extmapper simplemap for cells of type $dff.
429s Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000001 for cells of type $fa.
429s Using template $paramod$7e708ae28ab761f11d0fb59d3ffc72f6a4baf5d9\_90_alu for cells of type $alu.
429s Using extmapper simplemap for cells of type $pos.
429s Using extmapper simplemap for cells of type $or.
429s Using extmapper simplemap for cells of type $and.
429s Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu.
429s No more expansions possible.
429s <suppressed ~504 debug messages>
429s 
429s 2.33. Executing OPT pass (performing simple optimizations).
429s 
429s 2.33.1. Executing OPT_EXPR pass (perform const folding).
429s Optimizing module top.
429s <suppressed ~63 debug messages>
429s 
429s 2.33.2. Executing OPT_MERGE pass (detect identical cells).
429s Finding identical cells in module `\top'.
429s <suppressed ~3 debug messages>
429s Removed a total of 1 cells.
429s 
429s 2.33.3. Executing OPT_DFF pass (perform DFF optimizations).
429s 
429s 2.33.4. Executing OPT_CLEAN pass (remove unused cells and wires).
429s Finding unused cells or wires in module \top..
429s Removed 30 unused cells and 60 unused wires.
429s <suppressed ~31 debug messages>
429s 
429s 2.33.5. Finished fast OPT passes.
429s 
429s 2.34. Executing ICE40_OPT pass (performing simple optimizations).
429s 
429s 2.34.1. Running ICE40 specific optimizations.
429s Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$464.slice[0].carry: CO=\counter [0]
429s 
429s 2.34.2. Executing OPT_EXPR pass (perform const folding).
429s Optimizing module top.
429s 
429s 2.34.3. Executing OPT_MERGE pass (detect identical cells).
429s Finding identical cells in module `\top'.
429s Removed a total of 0 cells.
429s 
429s 2.34.4. Executing OPT_DFF pass (perform DFF optimizations).
429s 
429s 2.34.5. Executing OPT_CLEAN pass (remove unused cells and wires).
429s Finding unused cells or wires in module \top..
429s 
429s 2.34.6. Rerunning OPT passes. (Removed registers in this run.)
429s 
429s 2.34.7. Running ICE40 specific optimizations.
429s 
429s 2.34.8. Executing OPT_EXPR pass (perform const folding).
429s Optimizing module top.
429s 
429s 2.34.9. Executing OPT_MERGE pass (detect identical cells).
429s Finding identical cells in module `\top'.
429s Removed a total of 0 cells.
429s 
429s 2.34.10. Executing OPT_DFF pass (perform DFF optimizations).
429s 
429s 2.34.11. Executing OPT_CLEAN pass (remove unused cells and wires).
429s Finding unused cells or wires in module \top..
429s 
429s 2.34.12. Finished OPT passes. (There is nothing left to do.)
429s 
429s 2.35. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
429s 
429s 2.36. Executing TECHMAP pass (map to technology primitives).
429s 
429s 2.36.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v
429s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation.
429s Generating RTLIL representation for module `\$_DFF_N_'.
429s Generating RTLIL representation for module `\$_DFF_P_'.
429s Generating RTLIL representation for module `\$_DFFE_NP_'.
429s Generating RTLIL representation for module `\$_DFFE_PP_'.
429s Generating RTLIL representation for module `\$_DFF_NP0_'.
429s Generating RTLIL representation for module `\$_DFF_NP1_'.
429s Generating RTLIL representation for module `\$_DFF_PP0_'.
429s Generating RTLIL representation for module `\$_DFF_PP1_'.
429s Generating RTLIL representation for module `\$_DFFE_NP0P_'.
429s Generating RTLIL representation for module `\$_DFFE_NP1P_'.
429s Generating RTLIL representation for module `\$_DFFE_PP0P_'.
429s Generating RTLIL representation for module `\$_DFFE_PP1P_'.
429s Generating RTLIL representation for module `\$_SDFF_NP0_'.
429s Generating RTLIL representation for module `\$_SDFF_NP1_'.
429s Generating RTLIL representation for module `\$_SDFF_PP0_'.
429s Generating RTLIL representation for module `\$_SDFF_PP1_'.
429s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
429s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
429s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
429s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
429s Successfully finished Verilog frontend.
429s 
429s 2.36.2. Continuing TECHMAP pass.
429s Using template \$_DFF_P_ for cells of type $_DFF_P_.
429s No more expansions possible.
429s <suppressed ~54 debug messages>
429s 
429s 2.37. Executing OPT_EXPR pass (perform const folding).
429s Optimizing module top.
429s 
429s 2.38. Executing SIMPLEMAP pass (map simple cells to gate primitives).
429s Mapping top.$auto$alumacc.cc:485:replace_alu$464.slice[0].carry ($lut).
429s 
429s 2.39. Executing ICE40_OPT pass (performing simple optimizations).
429s 
429s 2.39.1. Running ICE40 specific optimizations.
429s 
429s 2.39.2. Executing OPT_EXPR pass (perform const folding).
429s Optimizing module top.
429s <suppressed ~28 debug messages>
429s 
429s 2.39.3. Executing OPT_MERGE pass (detect identical cells).
429s Finding identical cells in module `\top'.
429s Removed a total of 0 cells.
429s 
429s 2.39.4. Executing OPT_DFF pass (perform DFF optimizations).
429s 
429s 2.39.5. Executing OPT_CLEAN pass (remove unused cells and wires).
429s Finding unused cells or wires in module \top..
429s Removed 0 unused cells and 132 unused wires.
429s <suppressed ~1 debug messages>
429s 
429s 2.39.6. Rerunning OPT passes. (Removed registers in this run.)
429s 
429s 2.39.7. Running ICE40 specific optimizations.
429s 
429s 2.39.8. Executing OPT_EXPR pass (perform const folding).
429s Optimizing module top.
429s 
429s 2.39.9. Executing OPT_MERGE pass (detect identical cells).
429s Finding identical cells in module `\top'.
429s Removed a total of 0 cells.
429s 
429s 2.39.10. Executing OPT_DFF pass (perform DFF optimizations).
429s 
429s 2.39.11. Executing OPT_CLEAN pass (remove unused cells and wires).
429s Finding unused cells or wires in module \top..
429s 
429s 2.39.12. Finished OPT passes. (There is nothing left to do.)
429s 
429s 2.40. Executing TECHMAP pass (map to technology primitives).
429s 
429s 2.40.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v
429s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation.
429s Generating RTLIL representation for module `\$_DLATCH_N_'.
429s Generating RTLIL representation for module `\$_DLATCH_P_'.
429s Successfully finished Verilog frontend.
429s 
429s 2.40.2. Continuing TECHMAP pass.
429s No more expansions possible.
429s <suppressed ~4 debug messages>
429s 
429s 2.41. Executing ABC pass (technology mapping using ABC).
429s 
429s 2.41.1. Extracting gate netlist of module `\top' to `<abc-temp-dir>/input.blif'..
429s Extracted 45 gates and 56 wires to a netlist network with 10 inputs and 23 outputs.
429s 
429s 2.41.1.1. Executing ABC.
430s Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
430s ABC: ABC command line: "source <abc-temp-dir>/abc.script".
430s ABC: 
430s ABC: + read_blif <abc-temp-dir>/input.blif 
430s ABC: + read_lut <abc-temp-dir>/lutdefs.txt 
430s ABC: + strash 
430s ABC: + &get -n 
430s ABC: + &fraig -x 
430s ABC: + &put 
430s ABC: + scorr 
430s ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
430s ABC: + dc2 
430s ABC: + dretime 
430s ABC: + strash 
430s ABC: + dch -f 
430s ABC: + if 
430s ABC: + mfs2 
430s ABC: + lutpack -S 1 
430s ABC: + dress <abc-temp-dir>/input.blif 
430s ABC: Total number of equiv classes                =      24.
430s ABC: Participating nodes from both networks       =      49.
430s ABC: Participating nodes from the first network   =      23. (  95.83 % of nodes)
430s ABC: Participating nodes from the second network  =      26. ( 108.33 % of nodes)
430s ABC: Node pairs (any polarity)                    =      23. (  95.83 % of names can be moved)
430s ABC: Node pairs (same polarity)                   =      23. (  95.83 % of names can be moved)
430s ABC: Total runtime =     0.01 sec
430s ABC: + write_blif <abc-temp-dir>/output.blif 
430s 
430s 2.41.1.2. Re-integrating ABC results.
430s ABC RESULTS:              $lut cells:       23
430s ABC RESULTS:        internal signals:       23
430s ABC RESULTS:           input signals:       10
430s ABC RESULTS:          output signals:       23
430s Removing temp directory.
430s 
430s 2.42. Executing ICE40_WRAPCARRY pass (wrap carries).
430s 
430s 2.43. Executing TECHMAP pass (map to technology primitives).
430s 
430s 2.43.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v
430s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation.
430s Generating RTLIL representation for module `\$_DFF_N_'.
430s Generating RTLIL representation for module `\$_DFF_P_'.
430s Generating RTLIL representation for module `\$_DFFE_NP_'.
430s Generating RTLIL representation for module `\$_DFFE_PP_'.
430s Generating RTLIL representation for module `\$_DFF_NP0_'.
430s Generating RTLIL representation for module `\$_DFF_NP1_'.
430s Generating RTLIL representation for module `\$_DFF_PP0_'.
430s Generating RTLIL representation for module `\$_DFF_PP1_'.
430s Generating RTLIL representation for module `\$_DFFE_NP0P_'.
430s Generating RTLIL representation for module `\$_DFFE_NP1P_'.
430s Generating RTLIL representation for module `\$_DFFE_PP0P_'.
430s Generating RTLIL representation for module `\$_DFFE_PP1P_'.
430s Generating RTLIL representation for module `\$_SDFF_NP0_'.
430s Generating RTLIL representation for module `\$_SDFF_NP1_'.
430s Generating RTLIL representation for module `\$_SDFF_PP0_'.
430s Generating RTLIL representation for module `\$_SDFF_PP1_'.
430s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
430s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
430s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
430s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
430s Successfully finished Verilog frontend.
430s 
430s 2.43.2. Continuing TECHMAP pass.
430s No more expansions possible.
430s <suppressed ~22 debug messages>
430s Removed 1 unused cells and 46 unused wires.
430s 
430s 2.44. Executing OPT_LUT pass (optimize LUTs).
430s Discovering LUTs.
430s Number of LUTs:       49
430s   1-LUT                1
430s   2-LUT                5
430s   3-LUT               25
430s   4-LUT               18
430s   with \SB_CARRY    (#0)   25
430s   with \SB_CARRY    (#1)   25
430s 
430s Eliminating LUTs.
430s Number of LUTs:       49
430s   1-LUT                1
430s   2-LUT                5
430s   3-LUT               25
430s   4-LUT               18
430s   with \SB_CARRY    (#0)   25
430s   with \SB_CARRY    (#1)   25
430s 
430s Combining LUTs.
430s Number of LUTs:       49
430s   1-LUT                1
430s   2-LUT                5
430s   3-LUT               25
430s   4-LUT               18
430s   with \SB_CARRY    (#0)   25
430s   with \SB_CARRY    (#1)   25
430s 
430s Eliminated 0 LUTs.
430s Combined 0 LUTs.
430s <suppressed ~148 debug messages>
430s 
430s 2.45. Executing TECHMAP pass (map to technology primitives).
430s 
430s 2.45.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v
430s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation.
430s Generating RTLIL representation for module `\$lut'.
430s Successfully finished Verilog frontend.
430s 
430s 2.45.2. Continuing TECHMAP pass.
430s Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut.
430s Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut.
430s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
430s Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut.
430s Using template $paramod$38524f19a670105a447163ca7c0fbdcb0f76b0d7\$lut for cells of type $lut.
430s Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut.
430s Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut.
430s Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut.
430s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
430s No more expansions possible.
430s <suppressed ~169 debug messages>
430s Removed 0 unused cells and 98 unused wires.
430s 
430s 2.46. Executing AUTONAME pass.
430s Renamed 160 objects in module top (4 iterations).
430s <suppressed ~108 debug messages>
430s 
430s 2.47. Executing HIERARCHY pass (managing design hierarchy).
430s 
430s 2.47.1. Analyzing design hierarchy..
430s Top module:  \top
430s 
430s 2.47.2. Analyzing design hierarchy..
430s Top module:  \top
430s Removed 0 unused modules.
430s 
430s 2.48. Printing statistics.
430s 
430s === top ===
430s 
430s    Number of wires:                 32
430s    Number of wire bits:            114
430s    Number of public wires:          32
430s    Number of public wire bits:     114
430s    Number of memories:               0
430s    Number of memory bits:            0
430s    Number of processes:              0
430s    Number of cells:                106
430s      SB_CARRY                       25
430s      SB_DFF                         32
430s      SB_LUT4                        49
430s 
430s 2.49. Executing CHECK pass (checking for obvious problems).
430s Checking module top...
430s Found and reported 0 problems.
430s 
430s 2.50. Executing JSON backend.
430s 
430s End of script. Logfile hash: b880fedab4, CPU: user 1.11s system 0.00s, MEM: 20.00 MB peak
430s Yosys 0.33 (git sha1 2584903a060)
430s Time spent: 59% 13x read_verilog (0 sec), 7% 19x opt_clean (0 sec), ...
430s nextpnr-ice40 --up5k --package sg48 --asc example.asc --pcf icebreaker.pcf --json example.json
430s Info: constrained 'CLK' to bel 'X12/Y31/io1'
430s Info: constrained 'BTN_N' to bel 'X16/Y0/io0'
430s Info: constrained 'LEDR_N' to bel 'X17/Y0/io0'
430s Info: constrained 'LEDG_N' to bel 'X13/Y31/io0'
430s Info: constrained 'P1A1' to bel 'X9/Y0/io0'
430s Info: constrained 'P1A2' to bel 'X8/Y0/io0'
430s Info: constrained 'P1A3' to bel 'X6/Y0/io0'
430s Info: constrained 'P1A4' to bel 'X7/Y0/io1'
430s Info: constrained 'P1A7' to bel 'X9/Y0/io1'
430s Info: constrained 'P1A8' to bel 'X7/Y0/io0'
430s Info: constrained 'P1A9' to bel 'X5/Y0/io0'
430s Info: constrained 'P1A10' to bel 'X6/Y0/io1'
430s Info: constrained 'P1B1' to bel 'X9/Y31/io0'
430s Info: constrained 'P1B2' to bel 'X8/Y31/io1'
430s Info: constrained 'P1B3' to bel 'X13/Y31/io1'
430s Info: constrained 'P1B4' to bel 'X16/Y31/io1'
430s Info: constrained 'P1B7' to bel 'X8/Y31/io0'
430s Info: constrained 'P1B8' to bel 'X9/Y31/io1'
430s Info: constrained 'P1B9' to bel 'X16/Y31/io0'
430s Info: constrained 'P1B10' to bel 'X17/Y31/io0'
430s Info: constrained 'LED1' to bel 'X18/Y31/io1'
430s Info: constrained 'LED2' to bel 'X19/Y31/io1'
430s Info: constrained 'LED3' to bel 'X18/Y0/io1'
430s Info: constrained 'BTN2' to bel 'X21/Y0/io1'
430s Info: constrained 'LED5' to bel 'X18/Y31/io0'
430s Info: constrained 'LED4' to bel 'X19/Y31/io0'
430s Info: constrained 'BTN1' to bel 'X19/Y0/io1'
430s Info: constrained 'BTN3' to bel 'X22/Y0/io1'
430s 
430s Info: Packing constants..
430s Info: Packing IOs..
430s Info: Packing LUT-FFs..
430s Info:       22 LCs used as LUT4 only
430s Info:       27 LCs used as LUT4 and DFF
430s Info: Packing non-LUT FFs..
430s Info:        5 LCs used as DFF only
430s Info: Packing carries..
430s Info:        0 LCs used as CARRY only
430s Info: Packing indirect carry+LUT pairs...
430s Info:        0 LUTs merged into carry LCs
430s Info: Packing RAMs..
430s Info: Placing PLLs..
430s Info: Packing special functions..
430s Info: Packing PLLs..
430s Info: Promoting globals..
430s Info: promoting CLK$SB_IO_IN (fanout 32)
430s Info: Constraining chains...
430s Info:        1 LCs used to legalise carry chains.
430s Info: Checksum: 0x839ec283
430s 
430s Info: Annotating ports with timing budgets for target frequency 12.00 MHz
430s Info: Checksum: 0x3e791311
430s 
430s Info: Device utilisation:
430s Info: 	         ICESTORM_LC:    57/ 5280     1%
430s Info: 	        ICESTORM_RAM:     0/   30     0%
430s Info: 	               SB_IO:    28/   96    29%
430s Info: 	               SB_GB:     1/    8    12%
430s Info: 	        ICESTORM_PLL:     0/    1     0%
430s Info: 	         SB_WARMBOOT:     0/    1     0%
430s Info: 	        ICESTORM_DSP:     0/    8     0%
430s Info: 	      ICESTORM_HFOSC:     0/    1     0%
430s Info: 	      ICESTORM_LFOSC:     0/    1     0%
430s Info: 	              SB_I2C:     0/    2     0%
430s Info: 	              SB_SPI:     0/    2     0%
430s Info: 	              IO_I3C:     0/    2     0%
430s Info: 	         SB_LEDDA_IP:     0/    1     0%
430s Info: 	         SB_RGBA_DRV:     0/    1     0%
430s Info: 	      ICESTORM_SPRAM:     0/    4     0%
430s 
430s Info: Placed 28 cells based on constraints.
430s Info: Creating initial analytic placement for 30 cells, random placement wirelen = 1015.
430s Info:     at initial placer iter 0, wirelen = 241
430s Info:     at initial placer iter 1, wirelen = 243
430s Info:     at initial placer iter 2, wirelen = 240
430s Info:     at initial placer iter 3, wirelen = 243
430s Info: Running main analytical placer, max placement attempts per cell = 10000.
430s Info:     at iteration #1, type ICESTORM_LC: wirelen solved = 240, spread = 257, legal = 285; time = 0.00s
430s Info:     at iteration #1, type SB_GB: wirelen solved = 285, spread = 285, legal = 285; time = 0.00s
430s Info:     at iteration #1, type ALL: wirelen solved = 245, spread = 266, legal = 296; time = 0.00s
430s Info: HeAP Placer Time: 0.01s
430s Info:   of which solving equations: 0.01s
430s Info:   of which spreading cells: 0.00s
430s Info:   of which strict legalisation: 0.00s
430s 
430s Info: Running simulated annealing placer for refinement.
430s Info:   at iteration #1: temp = 0.000000, timing cost = 10, wirelen = 296
430s Info:   at iteration #5: temp = 0.000000, timing cost = 10, wirelen = 257
430s Info:   at iteration #8: temp = 0.000000, timing cost = 10, wirelen = 255 
430s Info: SA placement time 0.01s
430s 
430s Info: Max frequency for clock 'CLK$SB_IO_IN_$glb_clk': 76.86 MHz (PASS at 12.00 MHz)
430s 
430s Info: Max delay <async>                       -> <async>: 11.07 ns
430s Info: Max delay posedge CLK$SB_IO_IN_$glb_clk -> <async>: 11.91 ns
430s 
430s Info: Slack histogram:
430s Info:  legend: * represents 1 endpoint(s)
430s Info:          + represents [1,1) endpoint(s)
430s Info: [ 70323,  70775) |*** 
430s Info: [ 70775,  71227) | 
430s Info: [ 71227,  71679) |**** 
430s Info: [ 71679,  72131) |******* 
430s Info: [ 72131,  72583) |*** 
430s Info: [ 72583,  73035) |** 
430s Info: [ 73035,  73487) |** 
430s Info: [ 73487,  73939) |* 
430s Info: [ 73939,  74391) |* 
430s Info: [ 74391,  74843) |** 
430s Info: [ 74843,  75295) |*** 
430s Info: [ 75295,  75747) |****** 
430s Info: [ 75747,  76199) |****** 
430s Info: [ 76199,  76651) |** 
430s Info: [ 76651,  77103) |* 
430s Info: [ 77103,  77555) |*** 
430s Info: [ 77555,  78007) |* 
430s Info: [ 78007,  78459) | 
430s Info: [ 78459,  78911) | 
430s Info: [ 78911,  79363) |********************************** 
430s Info: Checksum: 0xd20107fc
430s 
430s Info: Routing..
430s Info: Setting up routing queue.
430s Info: Routing 196 arcs.
430s Info:            |   (re-)routed arcs  |   delta    | remaining|       time spent     |
430s Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|
430s Info:        198 |        1        175 |    1   175 |         0|       0.11       0.11|
430s Info: Routing complete.
430s Info: Router1 time 0.11s
430s Info: Checksum: 0x40e74afa
430s 
430s Info: Critical path report for clock 'CLK$SB_IO_IN_$glb_clk' (posedge -> posedge):
430s Info: curr total
430s Info:  1.4  1.4  Source counter_SB_LUT4_I3_LC.O
430s Info:  1.8  3.2    Net counter[0] budget 72.830002 ns (17,26) -> (16,26)
430s Info:                Sink $nextpnr_ICESTORM_LC_0.I1
430s Info:                Defined in:
430s Info:                  example.v:29.14-29.25
430s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
430s Info:  0.7  3.8  Source $nextpnr_ICESTORM_LC_0.COUT
430s Info:  0.0  3.8    Net $nextpnr_ICESTORM_LC_0$O budget 0.000000 ns (16,26) -> (16,26)
430s Info:                Sink counter_SB_LUT4_I2_2_LC.CIN
430s Info:  0.3  4.1  Source counter_SB_LUT4_I2_2_LC.COUT
430s Info:  0.0  4.1    Net counter_SB_CARRY_CI_CO[2] budget 0.000000 ns (16,26) -> (16,26)
430s Info:                Sink counter_SB_LUT4_I2_20_LC.CIN
430s Info:                Defined in:
430s Info:                  example.v:29.14-29.25
430s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
430s Info:  0.3  4.4  Source counter_SB_LUT4_I2_20_LC.COUT
430s Info:  0.0  4.4    Net counter_SB_CARRY_CI_CO[3] budget 0.000000 ns (16,26) -> (16,26)
430s Info:                Sink counter_SB_LUT4_I2_19_LC.CIN
430s Info:                Defined in:
430s Info:                  example.v:29.14-29.25
430s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
430s Info:  0.3  4.7  Source counter_SB_LUT4_I2_19_LC.COUT
430s Info:  0.0  4.7    Net counter_SB_CARRY_CI_CO[4] budget 0.000000 ns (16,26) -> (16,26)
430s Info:                Sink counter_SB_LUT4_I2_18_LC.CIN
430s Info:                Defined in:
430s Info:                  example.v:29.14-29.25
430s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
430s Info:  0.3  4.9  Source counter_SB_LUT4_I2_18_LC.COUT
430s Info:  0.0  4.9    Net counter_SB_CARRY_CI_CO[5] budget 0.000000 ns (16,26) -> (16,26)
430s Info:                Sink counter_SB_LUT4_I2_17_LC.CIN
430s Info:                Defined in:
430s Info:                  example.v:29.14-29.25
430s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
430s Info:  0.3  5.2  Source counter_SB_LUT4_I2_17_LC.COUT
430s Info:  0.0  5.2    Net counter_SB_CARRY_CI_CO[6] budget 0.000000 ns (16,26) -> (16,26)
430s Info:                Sink counter_SB_LUT4_I2_16_LC.CIN
430s Info:                Defined in:
430s Info:                  example.v:29.14-29.25
430s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
430s Info:  0.3  5.5  Source counter_SB_LUT4_I2_16_LC.COUT
430s Info:  0.0  5.5    Net counter_SB_CARRY_CI_CO[7] budget 0.000000 ns (16,26) -> (16,26)
430s Info:                Sink counter_SB_LUT4_I2_15_LC.CIN
430s Info:                Defined in:
430s Info:                  example.v:29.14-29.25
430s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
430s Info:  0.3  5.8  Source counter_SB_LUT4_I2_15_LC.COUT
430s Info:  0.6  6.3    Net counter_SB_CARRY_CI_CO[8] budget 0.560000 ns (16,26) -> (16,27)
430s Info:                Sink counter_SB_LUT4_I2_14_LC.CIN
430s Info:                Defined in:
430s Info:                  example.v:29.14-29.25
430s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
430s Info:  0.3  6.6  Source counter_SB_LUT4_I2_14_LC.COUT
430s Info:  0.0  6.6    Net counter_SB_CARRY_CI_CO[9] budget 0.000000 ns (16,27) -> (16,27)
430s Info:                Sink counter_SB_LUT4_I2_13_LC.CIN
430s Info:                Defined in:
430s Info:                  example.v:29.14-29.25
430s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
430s Info:  0.3  6.9  Source counter_SB_LUT4_I2_13_LC.COUT
430s Info:  0.0  6.9    Net counter_SB_CARRY_CI_CO[10] budget 0.000000 ns (16,27) -> (16,27)
430s Info:                Sink counter_SB_LUT4_I2_12_LC.CIN
430s Info:                Defined in:
430s Info:                  example.v:29.14-29.25
430s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
430s Info:  0.3  7.2  Source counter_SB_LUT4_I2_12_LC.COUT
430s Info:  0.0  7.2    Net counter_SB_CARRY_CI_CO[11] budget 0.000000 ns (16,27) -> (16,27)
430s Info:                Sink counter_SB_LUT4_I2_11_LC.CIN
430s Info:                Defined in:
430s Info:                  example.v:29.14-29.25
430s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
430s Info:  0.3  7.4  Source counter_SB_LUT4_I2_11_LC.COUT
430s Info:  0.0  7.4    Net counter_SB_CARRY_CI_CO[12] budget 0.000000 ns (16,27) -> (16,27)
430s Info:                Sink counter_SB_LUT4_I2_10_LC.CIN
430s Info:                Defined in:
430s Info:                  example.v:29.14-29.25
430s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
430s Info:  0.3  7.7  Source counter_SB_LUT4_I2_10_LC.COUT
430s Info:  0.0  7.7    Net counter_SB_CARRY_CI_CO[13] budget 0.000000 ns (16,27) -> (16,27)
430s Info:                Sink counter_SB_LUT4_I2_9_LC.CIN
430s Info:                Defined in:
430s Info:                  example.v:29.14-29.25
430s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
430s Info:  0.3  8.0  Source counter_SB_LUT4_I2_9_LC.COUT
430s Info:  0.0  8.0    Net counter_SB_CARRY_CI_CO[14] budget 0.000000 ns (16,27) -> (16,27)
430s Info:                Sink counter_SB_LUT4_I2_8_LC.CIN
430s Info:                Defined in:
430s Info:                  example.v:29.14-29.25
430s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
430s Info:  0.3  8.3  Source counter_SB_LUT4_I2_8_LC.COUT
430s Info:  0.0  8.3    Net counter_SB_CARRY_CI_CO[15] budget 0.000000 ns (16,27) -> (16,27)
430s Info:                Sink counter_SB_LUT4_I2_7_LC.CIN
430s Info:                Defined in:
430s Info:                  example.v:29.14-29.25
430s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
430s Info:  0.3  8.6  Source counter_SB_LUT4_I2_7_LC.COUT
430s Info:  0.6  9.1    Net counter_SB_CARRY_CI_CO[16] budget 0.560000 ns (16,27) -> (16,28)
430s Info:                Sink counter_SB_LUT4_I2_6_LC.CIN
430s Info:                Defined in:
430s Info:                  example.v:29.14-29.25
430s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
430s Info:  0.3  9.4  Source counter_SB_LUT4_I2_6_LC.COUT
430s Info:  0.0  9.4    Net counter_SB_CARRY_CI_CO[17] budget 0.000000 ns (16,28) -> (16,28)
430s Info:                Sink counter_SB_LUT4_I2_5_LC.CIN
430s Info:                Defined in:
430s Info:                  example.v:29.14-29.25
430s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
430s Info:  0.3  9.7  Source counter_SB_LUT4_I2_5_LC.COUT
430s Info:  0.0  9.7    Net counter_SB_CARRY_CI_CO[18] budget 0.000000 ns (16,28) -> (16,28)
430s Info:                Sink counter_SB_LUT4_I2_4_LC.CIN
430s Info:                Defined in:
430s Info:                  example.v:29.14-29.25
430s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
430s Info:  0.3  9.9  Source counter_SB_LUT4_I2_4_LC.COUT
430s Info:  0.0  9.9    Net counter_SB_CARRY_CI_CO[19] budget 0.000000 ns (16,28) -> (16,28)
430s Info:                Sink counter_SB_LUT4_I2_3_LC.CIN
430s Info:                Defined in:
430s Info:                  example.v:29.14-29.25
430s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
430s Info:  0.3 10.2  Source counter_SB_LUT4_I2_3_LC.COUT
430s Info:  0.0 10.2    Net counter_SB_CARRY_CI_CO[20] budget 0.000000 ns (16,28) -> (16,28)
430s Info:                Sink counter_SB_LUT4_I2_1_LC.CIN
430s Info:                Defined in:
430s Info:                  example.v:29.14-29.25
430s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
430s Info:  0.3 10.5  Source counter_SB_LUT4_I2_1_LC.COUT
430s Info:  0.0 10.5    Net counter_SB_CARRY_CI_CO[21] budget 0.000000 ns (16,28) -> (16,28)
430s Info:                Sink counter_SB_LUT4_I2_LC.CIN
430s Info:                Defined in:
430s Info:                  example.v:29.14-29.25
430s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
430s Info:  0.3 10.8  Source counter_SB_LUT4_I2_LC.COUT
430s Info:  0.0 10.8    Net counter_SB_CARRY_CI_CO[22] budget 0.000000 ns (16,28) -> (16,28)
430s Info:                Sink counter_SB_LUT4_I2_25_LC.CIN
430s Info:                Defined in:
430s Info:                  example.v:29.14-29.25
430s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
430s Info:  0.3 11.1  Source counter_SB_LUT4_I2_25_LC.COUT
430s Info:  0.0 11.1    Net counter_SB_CARRY_CI_CO[23] budget 0.000000 ns (16,28) -> (16,28)
430s Info:                Sink counter_SB_LUT4_I2_24_LC.CIN
430s Info:                Defined in:
430s Info:                  example.v:29.14-29.25
430s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
430s Info:  0.3 11.3  Source counter_SB_LUT4_I2_24_LC.COUT
430s Info:  0.6 11.9    Net counter_SB_CARRY_CI_CO[24] budget 0.560000 ns (16,28) -> (16,29)
430s Info:                Sink counter_SB_LUT4_I2_23_LC.CIN
430s Info:                Defined in:
430s Info:                  example.v:29.14-29.25
430s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
430s Info:  0.3 12.2  Source counter_SB_LUT4_I2_23_LC.COUT
430s Info:  0.0 12.2    Net counter_SB_CARRY_CI_CO[25] budget 0.000000 ns (16,29) -> (16,29)
430s Info:                Sink counter_SB_LUT4_I2_22_LC.CIN
430s Info:                Defined in:
430s Info:                  example.v:29.14-29.25
430s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
430s Info:  0.3 12.4  Source counter_SB_LUT4_I2_22_LC.COUT
430s Info:  0.7 13.1    Net counter_SB_CARRY_CI_CO[26] budget 0.660000 ns (16,29) -> (16,29)
430s Info:                Sink counter_SB_LUT4_I2_21_LC.I3
430s Info:                Defined in:
430s Info:                  example.v:29.14-29.25
430s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
430s Info:  0.8 13.9  Setup counter_SB_LUT4_I2_21_LC.I3
430s Info: 9.8 ns logic, 4.1 ns routing
430s 
430s Info: Critical path report for cross-domain path '<async>' -> '<async>':
430s Info: curr total
430s Info:  0.0  0.0  Source BTN2$sb_io.D_IN_0
430s Info:  3.6  3.6    Net BTN2$SB_IO_IN budget 41.025002 ns (21,0) -> (16,1)
430s Info:                Sink LEDG_N_SB_LUT4_O_LC.I2
430s Info:                Defined in:
430s Info:                  example.v:12.8-12.12
430s Info:  1.2  4.8  Source LEDG_N_SB_LUT4_O_LC.O
430s Info:  7.5 12.3    Net LEDG_N$SB_IO_OUT budget 41.023998 ns (16,1) -> (13,31)
430s Info:                Sink LEDG_N$sb_io.D_OUT_0
430s Info:                Defined in:
430s Info:                  example.v:16.9-16.15
430s Info: 1.2 ns logic, 11.1 ns routing
430s 
430s Info: Critical path report for cross-domain path 'posedge CLK$SB_IO_IN_$glb_clk' -> '<async>':
430s Info: curr total
430s Info:  1.4  1.4  Source outcnt_SB_DFF_Q_3_DFFLC.O
430s Info:  7.9  9.3    Net outcnt[0] budget 40.330002 ns (15,28) -> (5,1)
430s Info:                Sink P1A10_SB_LUT4_O_LC.I0
430s Info:                Defined in:
430s Info:                  example.v:26.17-26.23
430s Info:  1.3 10.6  Source P1A10_SB_LUT4_O_LC.O
430s Info:  1.8 12.4    Net P1A10$SB_IO_OUT budget 40.328999 ns (5,1) -> (6,0)
430s Info:                Sink P1A10$sb_io.D_OUT_0
430s Info:                Defined in:
430s Info:                  example.v:18.51-18.56
430s Info: 2.7 ns logic, 9.7 ns routing
430s 
430s Info: Max frequency for clock 'CLK$SB_IO_IN_$glb_clk': 71.80 MHz (PASS at 12.00 MHz)
430s 
430s Info: Max delay <async>                       -> <async>: 12.29 ns
430s Info: Max delay posedge CLK$SB_IO_IN_$glb_clk -> <async>: 12.36 ns
430s 
430s Info: Slack histogram:
430s Info:  legend: * represents 1 endpoint(s)
430s Info:          + represents [1,1) endpoint(s)
430s Info: [ 69405,  69912) |** 
430s Info: [ 69912,  70419) |* 
430s Info: [ 70419,  70926) |* 
430s Info: [ 70926,  71433) |******** 
430s Info: [ 71433,  71940) |***** 
430s Info: [ 71940,  72447) |** 
430s Info: [ 72447,  72954) |** 
430s Info: [ 72954,  73461) | 
430s Info: [ 73461,  73968) |** 
430s Info: [ 73968,  74475) |** 
430s Info: [ 74475,  74982) |** 
430s Info: [ 74982,  75489) |***** 
430s Info: [ 75489,  75996) |*** 
430s Info: [ 75996,  76503) |****** 
430s Info: [ 76503,  77010) |*** 
430s Info: [ 77010,  77517) |** 
430s Info: [ 77517,  78024) |* 
430s Info: [ 78024,  78531) | 
430s Info: [ 78531,  79038) |******************************* 
430s Info: [ 79038,  79545) |*** 
430s 
430s Info: Program finished normally.
430s icetime -d up5k -mtr example.rpt example.asc
430s // Reading input .asc file..
430s // Reading 5k chipdb file..
431s // Creating timing netlist..
431s // Timing estimate: 13.78 ns (72.56 MHz)
431s icepack example.asc example.bin
431s make: Leaving directory '/tmp/autopkgtest.eGJMaA/build.OQp/src/examples/icebreaker'
431s make: Entering directory '/tmp/autopkgtest.eGJMaA/build.OQp/src/examples/icemulti'
431s yosys -p "synth_ice40 -top top -json app0.json" app0.v
431s 
431s  /----------------------------------------------------------------------------\
431s  |                                                                            |
431s  |  yosys -- Yosys Open SYnthesis Suite                                       |
431s  |                                                                            |
431s  |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
431s  |                                                                            |
431s  |  Permission to use, copy, modify, and/or distribute this software for any  |
431s  |  purpose with or without fee is hereby granted, provided that the above    |
431s  |  copyright notice and this permission notice appear in all copies.         |
431s  |                                                                            |
431s  |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
431s  |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
431s  |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
431s  |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
431s  |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
431s  |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
431s  |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
431s  |                                                                            |
431s  \----------------------------------------------------------------------------/
431s 
431s  Yosys 0.33 (git sha1 2584903a060)
431s 
431s 
431s -- Parsing `app0.v' using frontend ` -vlog2k' --
431s 
431s 1. Executing Verilog-2005 frontend: app0.v
431s Parsing Verilog input from `app0.v' to AST representation.
431s Storing AST representation for module `$abstract\top'.
431s Successfully finished Verilog frontend.
431s 
431s -- Running command `synth_ice40 -top top -json app0.json' --
431s 
431s 2. Executing SYNTH_ICE40 pass.
431s 
431s 2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v
431s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation.
431s Generating RTLIL representation for module `\SB_IO'.
431s Generating RTLIL representation for module `\SB_GB_IO'.
431s Generating RTLIL representation for module `\SB_GB'.
431s Generating RTLIL representation for module `\SB_LUT4'.
431s Generating RTLIL representation for module `\SB_CARRY'.
431s Generating RTLIL representation for module `\SB_DFF'.
431s Generating RTLIL representation for module `\SB_DFFE'.
431s Generating RTLIL representation for module `\SB_DFFSR'.
431s Generating RTLIL representation for module `\SB_DFFR'.
431s Generating RTLIL representation for module `\SB_DFFSS'.
431s Generating RTLIL representation for module `\SB_DFFS'.
431s Generating RTLIL representation for module `\SB_DFFESR'.
431s Generating RTLIL representation for module `\SB_DFFER'.
431s Generating RTLIL representation for module `\SB_DFFESS'.
431s Generating RTLIL representation for module `\SB_DFFES'.
431s Generating RTLIL representation for module `\SB_DFFN'.
431s Generating RTLIL representation for module `\SB_DFFNE'.
431s Generating RTLIL representation for module `\SB_DFFNSR'.
431s Generating RTLIL representation for module `\SB_DFFNR'.
431s Generating RTLIL representation for module `\SB_DFFNSS'.
431s Generating RTLIL representation for module `\SB_DFFNS'.
431s Generating RTLIL representation for module `\SB_DFFNESR'.
431s Generating RTLIL representation for module `\SB_DFFNER'.
431s Generating RTLIL representation for module `\SB_DFFNESS'.
431s Generating RTLIL representation for module `\SB_DFFNES'.
431s Generating RTLIL representation for module `\SB_RAM40_4K'.
431s Generating RTLIL representation for module `\SB_RAM40_4KNR'.
431s Generating RTLIL representation for module `\SB_RAM40_4KNW'.
431s Generating RTLIL representation for module `\SB_RAM40_4KNRNW'.
431s Generating RTLIL representation for module `\ICESTORM_LC'.
431s Generating RTLIL representation for module `\SB_PLL40_CORE'.
431s Generating RTLIL representation for module `\SB_PLL40_PAD'.
431s Generating RTLIL representation for module `\SB_PLL40_2_PAD'.
431s Generating RTLIL representation for module `\SB_PLL40_2F_CORE'.
431s Generating RTLIL representation for module `\SB_PLL40_2F_PAD'.
431s Generating RTLIL representation for module `\SB_WARMBOOT'.
431s Generating RTLIL representation for module `\SB_SPRAM256KA'.
431s Generating RTLIL representation for module `\SB_HFOSC'.
431s Generating RTLIL representation for module `\SB_LFOSC'.
431s Generating RTLIL representation for module `\SB_RGBA_DRV'.
431s Generating RTLIL representation for module `\SB_LED_DRV_CUR'.
431s Generating RTLIL representation for module `\SB_RGB_DRV'.
431s Generating RTLIL representation for module `\SB_I2C'.
431s Generating RTLIL representation for module `\SB_SPI'.
431s Generating RTLIL representation for module `\SB_LEDDA_IP'.
431s Generating RTLIL representation for module `\SB_FILTER_50NS'.
431s Generating RTLIL representation for module `\SB_IO_I3C'.
431s Generating RTLIL representation for module `\SB_IO_OD'.
431s Generating RTLIL representation for module `\SB_MAC16'.
431s Generating RTLIL representation for module `\ICESTORM_RAM'.
431s Successfully finished Verilog frontend.
431s 
431s 2.2. Executing HIERARCHY pass (managing design hierarchy).
431s 
431s 2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\top'.
431s Generating RTLIL representation for module `\top'.
431s 
431s 2.3.1. Analyzing design hierarchy..
431s Top module:  \top
431s 
431s 2.3.2. Analyzing design hierarchy..
431s Top module:  \top
431s Removing unused module `$abstract\top'.
431s Removed 1 unused modules.
431s 
431s 2.4. Executing PROC pass (convert processes to netlists).
431s 
431s 2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
431s Cleaned up 0 empty switches.
431s 
431s 2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
431s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241 in module SB_DFFNES.
431s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234 in module SB_DFFNESS.
431s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230 in module SB_DFFNER.
431s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223 in module SB_DFFNESR.
431s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220 in module SB_DFFNS.
431s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217 in module SB_DFFNSS.
431s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214 in module SB_DFFNR.
431s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211 in module SB_DFFNSR.
431s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203 in module SB_DFFES.
431s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196 in module SB_DFFESS.
431s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192 in module SB_DFFER.
431s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185 in module SB_DFFESR.
431s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182 in module SB_DFFS.
431s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179 in module SB_DFFSS.
431s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176 in module SB_DFFR.
431s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173 in module SB_DFFSR.
431s Removed a total of 0 dead cases.
431s 
431s 2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
431s Removed 8 redundant assignments.
431s Promoted 28 assignments to connections.
431s 
431s 2.4.4. Executing PROC_INIT pass (extract init attributes).
431s Found init rule in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'.
431s   Set init value: \Q = 1'0
431s Found init rule in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'.
431s   Set init value: \Q = 1'0
431s Found init rule in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'.
431s   Set init value: \Q = 1'0
431s Found init rule in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'.
431s   Set init value: \Q = 1'0
431s Found init rule in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'.
431s   Set init value: \Q = 1'0
431s Found init rule in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'.
431s   Set init value: \Q = 1'0
431s Found init rule in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'.
431s   Set init value: \Q = 1'0
431s Found init rule in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'.
431s   Set init value: \Q = 1'0
431s Found init rule in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'.
431s   Set init value: \Q = 1'0
431s Found init rule in `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'.
431s   Set init value: \Q = 1'0
431s Found init rule in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'.
431s   Set init value: \Q = 1'0
431s Found init rule in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'.
431s   Set init value: \Q = 1'0
431s Found init rule in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'.
431s   Set init value: \Q = 1'0
431s Found init rule in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'.
431s   Set init value: \Q = 1'0
431s Found init rule in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'.
431s   Set init value: \Q = 1'0
431s Found init rule in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'.
431s   Set init value: \Q = 1'0
431s Found init rule in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'.
431s   Set init value: \Q = 1'0
431s Found init rule in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'.
431s   Set init value: \Q = 1'0
431s Found init rule in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'.
431s   Set init value: \Q = 1'0
431s Found init rule in `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'.
431s   Set init value: \Q = 1'0
431s Found init rule in `\top.$proc$app0.v:9$390'.
431s   Set init value: \state = 1'0
431s Found init rule in `\top.$proc$app0.v:8$389'.
431s   Set init value: \counter2 = 4'0000
431s Found init rule in `\top.$proc$app0.v:7$388'.
431s   Set init value: \counter = 22'0000000000000000000000
431s 
431s 2.4.5. Executing PROC_ARST pass (detect async resets in processes).
431s Found async reset \S in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
431s Found async reset \R in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
431s Found async reset \S in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
431s Found async reset \R in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
431s Found async reset \S in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
431s Found async reset \R in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
431s Found async reset \S in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'.
431s Found async reset \R in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'.
431s 
431s 2.4.6. Executing PROC_ROM pass (convert switches to ROMs).
431s Converted 0 switches.
431s <suppressed ~18 debug messages>
431s 
431s 2.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
431s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'.
431s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
431s      1/1: $0\Q[0:0]
431s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'.
431s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
431s      1/1: $0\Q[0:0]
431s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'.
431s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
431s      1/1: $0\Q[0:0]
431s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'.
431s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
431s      1/1: $0\Q[0:0]
431s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'.
431s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
431s      1/1: $0\Q[0:0]
431s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'.
431s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
431s      1/1: $0\Q[0:0]
431s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'.
431s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
431s      1/1: $0\Q[0:0]
431s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'.
431s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'.
431s      1/1: $0\Q[0:0]
431s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'.
431s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'.
431s      1/1: $0\Q[0:0]
431s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'.
431s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'.
431s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'.
431s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
431s      1/1: $0\Q[0:0]
431s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'.
431s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'.
431s      1/1: $0\Q[0:0]
431s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'.
431s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
431s      1/1: $0\Q[0:0]
431s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'.
431s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'.
431s      1/1: $0\Q[0:0]
431s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'.
431s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'.
431s      1/1: $0\Q[0:0]
431s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'.
431s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'.
431s      1/1: $0\Q[0:0]
431s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'.
431s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'.
431s      1/1: $0\Q[0:0]
431s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'.
431s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'.
431s      1/1: $0\Q[0:0]
431s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'.
431s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'.
431s      1/1: $0\Q[0:0]
431s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'.
431s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'.
431s Creating decoders for process `\top.$proc$app0.v:9$390'.
431s Creating decoders for process `\top.$proc$app0.v:8$389'.
431s Creating decoders for process `\top.$proc$app0.v:7$388'.
431s Creating decoders for process `\top.$proc$app0.v:11$381'.
431s 
431s 2.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
431s 
431s 2.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
431s Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
431s   created $adff cell `$procdff$435' with negative edge clock and positive level reset.
431s Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
431s   created $dff cell `$procdff$436' with negative edge clock.
431s Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
431s   created $adff cell `$procdff$437' with negative edge clock and positive level reset.
431s Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
431s   created $dff cell `$procdff$438' with negative edge clock.
431s Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
431s   created $adff cell `$procdff$439' with negative edge clock and positive level reset.
431s Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
431s   created $dff cell `$procdff$440' with negative edge clock.
431s Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
431s   created $adff cell `$procdff$441' with negative edge clock and positive level reset.
431s Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'.
431s   created $dff cell `$procdff$442' with negative edge clock.
431s Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'.
431s   created $dff cell `$procdff$443' with negative edge clock.
431s Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'.
431s   created $dff cell `$procdff$444' with negative edge clock.
431s Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
431s   created $adff cell `$procdff$445' with positive edge clock and positive level reset.
431s Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'.
431s   created $dff cell `$procdff$446' with positive edge clock.
431s Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
431s   created $adff cell `$procdff$447' with positive edge clock and positive level reset.
431s Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'.
431s   created $dff cell `$procdff$448' with positive edge clock.
431s Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'.
431s   created $adff cell `$procdff$449' with positive edge clock and positive level reset.
431s Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'.
431s   created $dff cell `$procdff$450' with positive edge clock.
431s Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'.
431s   created $adff cell `$procdff$451' with positive edge clock and positive level reset.
431s Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'.
431s   created $dff cell `$procdff$452' with positive edge clock.
431s Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'.
431s   created $dff cell `$procdff$453' with positive edge clock.
431s Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'.
431s   created $dff cell `$procdff$454' with positive edge clock.
431s Creating register for signal `\top.\counter' using process `\top.$proc$app0.v:11$381'.
431s   created $dff cell `$procdff$455' with positive edge clock.
431s Creating register for signal `\top.\counter2' using process `\top.$proc$app0.v:11$381'.
431s   created $dff cell `$procdff$456' with positive edge clock.
431s Creating register for signal `\top.\state' using process `\top.$proc$app0.v:11$381'.
431s   created $dff cell `$procdff$457' with positive edge clock.
431s 
431s 2.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
431s 
431s 2.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
431s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'.
431s Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
431s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
431s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'.
431s Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
431s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
431s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'.
431s Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
431s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
431s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'.
431s Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
431s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
431s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'.
431s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
431s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'.
431s Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
431s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
431s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'.
431s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
431s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'.
431s Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'.
431s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'.
431s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'.
431s Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'.
431s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'.
431s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'.
431s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'.
431s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'.
431s Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
431s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
431s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'.
431s Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'.
431s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'.
431s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'.
431s Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
431s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
431s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'.
431s Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'.
431s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'.
431s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'.
431s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'.
431s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'.
431s Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'.
431s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'.
431s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'.
431s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'.
431s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'.
431s Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'.
431s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'.
431s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'.
431s Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'.
431s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'.
431s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'.
431s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'.
431s Removing empty process `top.$proc$app0.v:9$390'.
431s Removing empty process `top.$proc$app0.v:8$389'.
431s Removing empty process `top.$proc$app0.v:7$388'.
431s Removing empty process `top.$proc$app0.v:11$381'.
431s Cleaned up 18 empty switches.
431s 
431s 2.4.12. Executing OPT_EXPR pass (perform const folding).
431s Optimizing module top.
431s 
431s 2.5. Executing FLATTEN pass (flatten design).
431s 
431s 2.6. Executing TRIBUF pass.
431s 
431s 2.7. Executing DEMINOUT pass (demote inout ports to input or output).
431s 
431s 2.8. Executing OPT_EXPR pass (perform const folding).
431s Optimizing module top.
431s 
431s 2.9. Executing OPT_CLEAN pass (remove unused cells and wires).
431s Finding unused cells or wires in module \top..
431s Removed 0 unused cells and 5 unused wires.
431s <suppressed ~1 debug messages>
431s 
431s 2.10. Executing CHECK pass (checking for obvious problems).
431s Checking module top...
431s Found and reported 0 problems.
431s 
431s 2.11. Executing OPT pass (performing simple optimizations).
431s 
431s 2.11.1. Executing OPT_EXPR pass (perform const folding).
431s Optimizing module top.
431s 
431s 2.11.2. Executing OPT_MERGE pass (detect identical cells).
431s Finding identical cells in module `\top'.
431s Removed a total of 0 cells.
431s 
431s 2.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
431s Running muxtree optimizer on module \top..
431s   Creating internal representation of mux trees.
431s   No muxes found in this module.
431s Removed 0 multiplexer ports.
431s 
431s 2.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
431s   Optimizing cells in module \top.
431s Performed a total of 0 changes.
431s 
431s 2.11.5. Executing OPT_MERGE pass (detect identical cells).
431s Finding identical cells in module `\top'.
431s Removed a total of 0 cells.
431s 
431s 2.11.6. Executing OPT_DFF pass (perform DFF optimizations).
431s 
431s 2.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
431s Finding unused cells or wires in module \top..
431s 
431s 2.11.8. Executing OPT_EXPR pass (perform const folding).
431s Optimizing module top.
431s 
431s 2.11.9. Finished OPT passes. (There is nothing left to do.)
431s 
431s 2.12. Executing FSM pass (extract and optimize FSM).
431s 
431s 2.12.1. Executing FSM_DETECT pass (finding FSMs in design).
431s 
431s 2.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).
431s 
431s 2.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).
431s 
431s 2.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
431s Finding unused cells or wires in module \top..
431s 
431s 2.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).
431s 
431s 2.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
431s 
431s 2.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
431s 
431s 2.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
431s 
431s 2.13. Executing OPT pass (performing simple optimizations).
431s 
431s 2.13.1. Executing OPT_EXPR pass (perform const folding).
431s Optimizing module top.
431s 
431s 2.13.2. Executing OPT_MERGE pass (detect identical cells).
431s Finding identical cells in module `\top'.
431s Removed a total of 0 cells.
431s 
431s 2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
431s Running muxtree optimizer on module \top..
431s   Creating internal representation of mux trees.
431s   No muxes found in this module.
431s Removed 0 multiplexer ports.
431s 
431s 2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
431s   Optimizing cells in module \top.
431s Performed a total of 0 changes.
431s 
431s 2.13.5. Executing OPT_MERGE pass (detect identical cells).
431s Finding identical cells in module `\top'.
431s Removed a total of 0 cells.
431s 
431s 2.13.6. Executing OPT_DFF pass (perform DFF optimizations).
431s 
431s 2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
431s Finding unused cells or wires in module \top..
431s 
431s 2.13.8. Executing OPT_EXPR pass (perform const folding).
431s Optimizing module top.
431s 
431s 2.13.9. Finished OPT passes. (There is nothing left to do.)
431s 
431s 2.14. Executing WREDUCE pass (reducing word size of cells).
431s Removed top 31 bits (of 32) from port B of cell top.$add$app0.v:12$382 ($add).
431s Removed top 10 bits (of 32) from port Y of cell top.$add$app0.v:12$382 ($add).
431s Removed top 3 bits (of 4) from port B of cell top.$add$app0.v:13$384 ($add).
431s Removed top 3 bits (of 4) from wire top.$logic_not$app0.v:13$383_Y.
431s 
431s 2.15. Executing PEEPOPT pass (run peephole optimizers).
431s 
431s 2.16. Executing OPT_CLEAN pass (remove unused cells and wires).
431s Finding unused cells or wires in module \top..
431s Removed 0 unused cells and 2 unused wires.
431s <suppressed ~1 debug messages>
431s 
431s 2.17. Executing SHARE pass (SAT-based resource sharing).
431s 
431s 2.18. Executing TECHMAP pass (map to technology primitives).
431s 
431s 2.18.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v
431s Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation.
431s Generating RTLIL representation for module `\_90_lut_cmp_'.
431s Successfully finished Verilog frontend.
431s 
431s 2.18.2. Continuing TECHMAP pass.
431s No more expansions possible.
431s <suppressed ~6 debug messages>
431s 
431s 2.19. Executing OPT_EXPR pass (perform const folding).
431s Optimizing module top.
431s 
431s 2.20. Executing OPT_CLEAN pass (remove unused cells and wires).
431s Finding unused cells or wires in module \top..
431s 
431s 2.21. Executing ALUMACC pass (create $alu and $macc cells).
431s Extracting $alu and $macc cells in module top:
431s   creating $macc model for $add$app0.v:12$382 ($add).
431s   creating $macc model for $add$app0.v:13$384 ($add).
431s   creating $alu model for $macc $add$app0.v:13$384.
431s   creating $alu model for $macc $add$app0.v:12$382.
431s   creating $alu cell for $add$app0.v:12$382: $auto$alumacc.cc:485:replace_alu$460
431s   creating $alu cell for $add$app0.v:13$384: $auto$alumacc.cc:485:replace_alu$463
431s   created 2 $alu and 0 $macc cells.
431s 
431s 2.22. Executing OPT pass (performing simple optimizations).
431s 
431s 2.22.1. Executing OPT_EXPR pass (perform const folding).
431s Optimizing module top.
431s 
431s 2.22.2. Executing OPT_MERGE pass (detect identical cells).
431s Finding identical cells in module `\top'.
431s <suppressed ~3 debug messages>
431s Removed a total of 1 cells.
431s 
431s 2.22.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
431s Running muxtree optimizer on module \top..
431s   Creating internal representation of mux trees.
431s   No muxes found in this module.
431s Removed 0 multiplexer ports.
431s 
431s 2.22.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
431s   Optimizing cells in module \top.
431s Performed a total of 0 changes.
431s 
431s 2.22.5. Executing OPT_MERGE pass (detect identical cells).
431s Finding identical cells in module `\top'.
431s Removed a total of 0 cells.
431s 
431s 2.22.6. Executing OPT_DFF pass (perform DFF optimizations).
431s 
431s 2.22.7. Executing OPT_CLEAN pass (remove unused cells and wires).
431s Finding unused cells or wires in module \top..
431s Removed 0 unused cells and 1 unused wires.
431s <suppressed ~1 debug messages>
431s 
431s 2.22.8. Executing OPT_EXPR pass (perform const folding).
431s Optimizing module top.
431s 
431s 2.22.9. Rerunning OPT passes. (Maybe there is more to do..)
431s 
431s 2.22.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
431s Running muxtree optimizer on module \top..
431s   Creating internal representation of mux trees.
431s   No muxes found in this module.
431s Removed 0 multiplexer ports.
431s 
431s 2.22.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
431s   Optimizing cells in module \top.
431s Performed a total of 0 changes.
431s 
431s 2.22.12. Executing OPT_MERGE pass (detect identical cells).
431s Finding identical cells in module `\top'.
431s Removed a total of 0 cells.
431s 
431s 2.22.13. Executing OPT_DFF pass (perform DFF optimizations).
431s 
431s 2.22.14. Executing OPT_CLEAN pass (remove unused cells and wires).
431s Finding unused cells or wires in module \top..
431s 
431s 2.22.15. Executing OPT_EXPR pass (perform const folding).
431s Optimizing module top.
431s 
431s 2.22.16. Finished OPT passes. (There is nothing left to do.)
431s 
431s 2.23. Executing MEMORY pass.
431s 
431s 2.23.1. Executing OPT_MEM pass (optimize memories).
431s Performed a total of 0 transformations.
431s 
431s 2.23.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
431s Performed a total of 0 transformations.
431s 
431s 2.23.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
431s 
431s 2.23.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
431s 
431s 2.23.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
431s 
431s 2.23.6. Executing OPT_CLEAN pass (remove unused cells and wires).
431s Finding unused cells or wires in module \top..
431s 
431s 2.23.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
431s 
431s 2.23.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
431s Performed a total of 0 transformations.
431s 
431s 2.23.9. Executing OPT_CLEAN pass (remove unused cells and wires).
431s Finding unused cells or wires in module \top..
431s 
431s 2.23.10. Executing MEMORY_COLLECT pass (generating $mem cells).
431s 
431s 2.24. Executing OPT_CLEAN pass (remove unused cells and wires).
431s Finding unused cells or wires in module \top..
431s 
431s 2.25. Executing MEMORY_LIBMAP pass (mapping memories to cells).
431s 
431s 2.26. Executing TECHMAP pass (map to technology primitives).
431s 
431s 2.26.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v
432s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation.
432s Generating RTLIL representation for module `\$__ICE40_RAM4K_'.
432s Successfully finished Verilog frontend.
432s 
432s 2.26.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/spram_map.v
432s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/spram_map.v' to AST representation.
432s Generating RTLIL representation for module `\$__ICE40_SPRAM_'.
432s Successfully finished Verilog frontend.
432s 
432s 2.26.3. Continuing TECHMAP pass.
432s No more expansions possible.
432s <suppressed ~4 debug messages>
432s 
432s 2.27. Executing ICE40_BRAMINIT pass.
432s 
432s 2.28. Executing OPT pass (performing simple optimizations).
432s 
432s 2.28.1. Executing OPT_EXPR pass (perform const folding).
432s Optimizing module top.
432s 
432s 2.28.2. Executing OPT_MERGE pass (detect identical cells).
432s Finding identical cells in module `\top'.
432s Removed a total of 0 cells.
432s 
432s 2.28.3. Executing OPT_DFF pass (perform DFF optimizations).
432s 
432s 2.28.4. Executing OPT_CLEAN pass (remove unused cells and wires).
432s Finding unused cells or wires in module \top..
432s 
432s 2.28.5. Finished fast OPT passes.
432s 
432s 2.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
432s 
432s 2.30. Executing OPT pass (performing simple optimizations).
432s 
432s 2.30.1. Executing OPT_EXPR pass (perform const folding).
432s Optimizing module top.
432s 
432s 2.30.2. Executing OPT_MERGE pass (detect identical cells).
432s Finding identical cells in module `\top'.
432s Removed a total of 0 cells.
432s 
432s 2.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
432s Running muxtree optimizer on module \top..
432s   Creating internal representation of mux trees.
432s   No muxes found in this module.
432s Removed 0 multiplexer ports.
432s 
432s 2.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
432s   Optimizing cells in module \top.
432s Performed a total of 0 changes.
432s 
432s 2.30.5. Executing OPT_MERGE pass (detect identical cells).
432s Finding identical cells in module `\top'.
432s Removed a total of 0 cells.
432s 
432s 2.30.6. Executing OPT_DFF pass (perform DFF optimizations).
432s 
432s 2.30.7. Executing OPT_CLEAN pass (remove unused cells and wires).
432s Finding unused cells or wires in module \top..
432s 
432s 2.30.8. Executing OPT_EXPR pass (perform const folding).
432s Optimizing module top.
432s 
432s 2.30.9. Finished OPT passes. (There is nothing left to do.)
432s 
432s 2.31. Executing ICE40_WRAPCARRY pass (wrap carries).
432s 
432s 2.32. Executing TECHMAP pass (map to technology primitives).
432s 
432s 2.32.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v
432s Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation.
432s Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
432s Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
432s Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
432s Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
432s Generating RTLIL representation for module `\_90_simplemap_various'.
432s Generating RTLIL representation for module `\_90_simplemap_registers'.
432s Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
432s Generating RTLIL representation for module `\_90_shift_shiftx'.
432s Generating RTLIL representation for module `\_90_fa'.
432s Generating RTLIL representation for module `\_90_lcu'.
432s Generating RTLIL representation for module `\_90_alu'.
432s Generating RTLIL representation for module `\_90_macc'.
432s Generating RTLIL representation for module `\_90_alumacc'.
432s Generating RTLIL representation for module `\$__div_mod_u'.
432s Generating RTLIL representation for module `\$__div_mod_trunc'.
432s Generating RTLIL representation for module `\_90_div'.
432s Generating RTLIL representation for module `\_90_mod'.
432s Generating RTLIL representation for module `\$__div_mod_floor'.
432s Generating RTLIL representation for module `\_90_divfloor'.
432s Generating RTLIL representation for module `\_90_modfloor'.
432s Generating RTLIL representation for module `\_90_pow'.
432s Generating RTLIL representation for module `\_90_pmux'.
432s Generating RTLIL representation for module `\_90_demux'.
432s Generating RTLIL representation for module `\_90_lut'.
432s Successfully finished Verilog frontend.
432s 
432s 2.32.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v
432s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation.
432s Generating RTLIL representation for module `\_80_ice40_alu'.
432s Successfully finished Verilog frontend.
432s 
432s 2.32.3. Continuing TECHMAP pass.
432s Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_80_ice40_alu for cells of type $alu.
432s Using extmapper simplemap for cells of type $logic_not.
432s Using template $paramod$080e6a70eb8bfa1ccf22d9718e795074645029a4\_80_ice40_alu for cells of type $alu.
432s Using extmapper simplemap for cells of type $xor.
432s Using extmapper simplemap for cells of type $reduce_and.
432s Using extmapper simplemap for cells of type $dff.
432s Using extmapper simplemap for cells of type $mux.
432s Using extmapper simplemap for cells of type $not.
432s Using extmapper simplemap for cells of type $pos.
432s No more expansions possible.
432s <suppressed ~129 debug messages>
432s 
432s 2.33. Executing OPT pass (performing simple optimizations).
432s 
432s 2.33.1. Executing OPT_EXPR pass (perform const folding).
432s Optimizing module top.
432s <suppressed ~51 debug messages>
432s 
432s 2.33.2. Executing OPT_MERGE pass (detect identical cells).
432s Finding identical cells in module `\top'.
432s <suppressed ~3 debug messages>
432s Removed a total of 1 cells.
432s 
432s 2.33.3. Executing OPT_DFF pass (perform DFF optimizations).
432s 
432s 2.33.4. Executing OPT_CLEAN pass (remove unused cells and wires).
432s Finding unused cells or wires in module \top..
432s Removed 27 unused cells and 34 unused wires.
432s <suppressed ~28 debug messages>
432s 
432s 2.33.5. Finished fast OPT passes.
432s 
432s 2.34. Executing ICE40_OPT pass (performing simple optimizations).
432s 
432s 2.34.1. Running ICE40 specific optimizations.
432s Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$460.slice[0].carry: CO=\counter [0]
432s 
432s 2.34.2. Executing OPT_EXPR pass (perform const folding).
432s Optimizing module top.
432s 
432s 2.34.3. Executing OPT_MERGE pass (detect identical cells).
432s Finding identical cells in module `\top'.
432s Removed a total of 0 cells.
432s 
432s 2.34.4. Executing OPT_DFF pass (perform DFF optimizations).
432s 
432s 2.34.5. Executing OPT_CLEAN pass (remove unused cells and wires).
432s Finding unused cells or wires in module \top..
432s 
432s 2.34.6. Rerunning OPT passes. (Removed registers in this run.)
432s 
432s 2.34.7. Running ICE40 specific optimizations.
432s 
432s 2.34.8. Executing OPT_EXPR pass (perform const folding).
432s Optimizing module top.
432s 
432s 2.34.9. Executing OPT_MERGE pass (detect identical cells).
432s Finding identical cells in module `\top'.
432s Removed a total of 0 cells.
432s 
432s 2.34.10. Executing OPT_DFF pass (perform DFF optimizations).
432s 
432s 2.34.11. Executing OPT_CLEAN pass (remove unused cells and wires).
432s Finding unused cells or wires in module \top..
432s 
432s 2.34.12. Finished OPT passes. (There is nothing left to do.)
432s 
432s 2.35. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
432s 
432s 2.36. Executing TECHMAP pass (map to technology primitives).
432s 
432s 2.36.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v
432s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation.
432s Generating RTLIL representation for module `\$_DFF_N_'.
432s Generating RTLIL representation for module `\$_DFF_P_'.
432s Generating RTLIL representation for module `\$_DFFE_NP_'.
432s Generating RTLIL representation for module `\$_DFFE_PP_'.
432s Generating RTLIL representation for module `\$_DFF_NP0_'.
432s Generating RTLIL representation for module `\$_DFF_NP1_'.
432s Generating RTLIL representation for module `\$_DFF_PP0_'.
432s Generating RTLIL representation for module `\$_DFF_PP1_'.
432s Generating RTLIL representation for module `\$_DFFE_NP0P_'.
432s Generating RTLIL representation for module `\$_DFFE_NP1P_'.
432s Generating RTLIL representation for module `\$_DFFE_PP0P_'.
432s Generating RTLIL representation for module `\$_DFFE_PP1P_'.
432s Generating RTLIL representation for module `\$_SDFF_NP0_'.
432s Generating RTLIL representation for module `\$_SDFF_NP1_'.
432s Generating RTLIL representation for module `\$_SDFF_PP0_'.
432s Generating RTLIL representation for module `\$_SDFF_PP1_'.
432s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
432s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
432s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
432s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
432s Successfully finished Verilog frontend.
432s 
432s 2.36.2. Continuing TECHMAP pass.
432s Using template \$_DFF_P_ for cells of type $_DFF_P_.
432s No more expansions possible.
432s <suppressed ~49 debug messages>
432s 
432s 2.37. Executing OPT_EXPR pass (perform const folding).
432s Optimizing module top.
432s 
432s 2.38. Executing SIMPLEMAP pass (map simple cells to gate primitives).
432s Mapping top.$auto$alumacc.cc:485:replace_alu$460.slice[0].carry ($lut).
432s 
432s 2.39. Executing ICE40_OPT pass (performing simple optimizations).
432s 
432s 2.39.1. Running ICE40 specific optimizations.
432s 
432s 2.39.2. Executing OPT_EXPR pass (perform const folding).
432s Optimizing module top.
432s <suppressed ~14 debug messages>
432s 
432s 2.39.3. Executing OPT_MERGE pass (detect identical cells).
432s Finding identical cells in module `\top'.
432s Removed a total of 0 cells.
432s 
432s 2.39.4. Executing OPT_DFF pass (perform DFF optimizations).
432s 
432s 2.39.5. Executing OPT_CLEAN pass (remove unused cells and wires).
432s Finding unused cells or wires in module \top..
432s Removed 0 unused cells and 112 unused wires.
432s <suppressed ~1 debug messages>
432s 
432s 2.39.6. Rerunning OPT passes. (Removed registers in this run.)
432s 
432s 2.39.7. Running ICE40 specific optimizations.
432s 
432s 2.39.8. Executing OPT_EXPR pass (perform const folding).
432s Optimizing module top.
432s 
432s 2.39.9. Executing OPT_MERGE pass (detect identical cells).
432s Finding identical cells in module `\top'.
432s Removed a total of 0 cells.
432s 
432s 2.39.10. Executing OPT_DFF pass (perform DFF optimizations).
432s 
432s 2.39.11. Executing OPT_CLEAN pass (remove unused cells and wires).
432s Finding unused cells or wires in module \top..
432s 
432s 2.39.12. Finished OPT passes. (There is nothing left to do.)
432s 
432s 2.40. Executing TECHMAP pass (map to technology primitives).
432s 
432s 2.40.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v
432s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation.
432s Generating RTLIL representation for module `\$_DLATCH_N_'.
432s Generating RTLIL representation for module `\$_DLATCH_P_'.
432s Successfully finished Verilog frontend.
432s 
432s 2.40.2. Continuing TECHMAP pass.
432s No more expansions possible.
432s <suppressed ~4 debug messages>
432s 
432s 2.41. Executing ABC pass (technology mapping using ABC).
432s 
432s 2.41.1. Extracting gate netlist of module `\top' to `<abc-temp-dir>/input.blif'..
432s Extracted 27 gates and 54 wires to a netlist network with 27 inputs and 4 outputs.
432s 
432s 2.41.1.1. Executing ABC.
432s Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
432s ABC: ABC command line: "source <abc-temp-dir>/abc.script".
432s ABC: 
432s ABC: + read_blif <abc-temp-dir>/input.blif 
432s ABC: + read_lut <abc-temp-dir>/lutdefs.txt 
432s ABC: + strash 
432s ABC: + &get -n 
432s ABC: + &fraig -x 
432s ABC: + &put 
432s ABC: + scorr 
432s ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
432s ABC: + dc2 
432s ABC: + dretime 
432s ABC: + strash 
432s ABC: + dch -f 
432s ABC: + if 
432s ABC: + mfs2 
432s ABC: + lutpack -S 1 
432s ABC: + dress <abc-temp-dir>/input.blif 
432s ABC: Total number of equiv classes                =       5.
432s ABC: Participating nodes from both networks       =       9.
432s ABC: Participating nodes from the first network   =       4. (  33.33 % of nodes)
432s ABC: Participating nodes from the second network  =       5. (  41.67 % of nodes)
432s ABC: Node pairs (any polarity)                    =       4. (  33.33 % of names can be moved)
432s ABC: Node pairs (same polarity)                   =       4. (  33.33 % of names can be moved)
432s ABC: Total runtime =     0.04 sec
432s ABC: + write_blif <abc-temp-dir>/output.blif 
432s 
432s 2.41.1.2. Re-integrating ABC results.
432s ABC RESULTS:              $lut cells:       11
432s ABC RESULTS:        internal signals:       23
432s ABC RESULTS:           input signals:       27
432s ABC RESULTS:          output signals:        4
432s Removing temp directory.
432s 
432s 2.42. Executing ICE40_WRAPCARRY pass (wrap carries).
432s 
432s 2.43. Executing TECHMAP pass (map to technology primitives).
432s 
432s 2.43.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v
432s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation.
432s Generating RTLIL representation for module `\$_DFF_N_'.
432s Generating RTLIL representation for module `\$_DFF_P_'.
432s Generating RTLIL representation for module `\$_DFFE_NP_'.
432s Generating RTLIL representation for module `\$_DFFE_PP_'.
432s Generating RTLIL representation for module `\$_DFF_NP0_'.
432s Generating RTLIL representation for module `\$_DFF_NP1_'.
432s Generating RTLIL representation for module `\$_DFF_PP0_'.
432s Generating RTLIL representation for module `\$_DFF_PP1_'.
432s Generating RTLIL representation for module `\$_DFFE_NP0P_'.
432s Generating RTLIL representation for module `\$_DFFE_NP1P_'.
432s Generating RTLIL representation for module `\$_DFFE_PP0P_'.
432s Generating RTLIL representation for module `\$_DFFE_PP1P_'.
432s Generating RTLIL representation for module `\$_SDFF_NP0_'.
432s Generating RTLIL representation for module `\$_SDFF_NP1_'.
432s Generating RTLIL representation for module `\$_SDFF_PP0_'.
432s Generating RTLIL representation for module `\$_SDFF_PP1_'.
432s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
432s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
432s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
432s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
432s Successfully finished Verilog frontend.
432s 
432s 2.43.2. Continuing TECHMAP pass.
432s No more expansions possible.
432s <suppressed ~22 debug messages>
432s Removed 2 unused cells and 39 unused wires.
432s 
432s 2.44. Executing OPT_LUT pass (optimize LUTs).
432s Discovering LUTs.
432s Number of LUTs:       36
432s   1-LUT                1
432s   2-LUT                3
432s   3-LUT               25
432s   4-LUT                7
432s   with \SB_CARRY    (#0)   23
432s   with \SB_CARRY    (#1)   23
432s 
432s Eliminating LUTs.
432s Number of LUTs:       36
432s   1-LUT                1
432s   2-LUT                3
432s   3-LUT               25
432s   4-LUT                7
432s   with \SB_CARRY    (#0)   23
432s   with \SB_CARRY    (#1)   23
432s 
432s Combining LUTs.
432s Number of LUTs:       36
432s   1-LUT                1
432s   2-LUT                3
432s   3-LUT               25
432s   4-LUT                7
432s   with \SB_CARRY    (#0)   23
432s   with \SB_CARRY    (#1)   23
432s 
432s Eliminated 0 LUTs.
432s Combined 0 LUTs.
432s <suppressed ~165 debug messages>
432s 
432s 2.45. Executing TECHMAP pass (map to technology primitives).
432s 
432s 2.45.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v
432s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation.
432s Generating RTLIL representation for module `\$lut'.
432s Successfully finished Verilog frontend.
432s 
432s 2.45.2. Continuing TECHMAP pass.
432s Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut.
432s Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut.
432s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut.
432s Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut.
432s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
432s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111000 for cells of type $lut.
432s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
432s No more expansions possible.
432s <suppressed ~130 debug messages>
432s Removed 0 unused cells and 76 unused wires.
432s 
432s 2.46. Executing AUTONAME pass.
432s Renamed 723 objects in module top (15 iterations).
432s <suppressed ~96 debug messages>
432s 
432s 2.47. Executing HIERARCHY pass (managing design hierarchy).
432s 
432s 2.47.1. Analyzing design hierarchy..
432s Top module:  \top
432s 
432s 2.47.2. Analyzing design hierarchy..
432s Top module:  \top
432s Removed 0 unused modules.
432s 
432s 2.48. Printing statistics.
432s 
432s === top ===
432s 
432s    Number of wires:                 19
432s    Number of wire bits:             97
432s    Number of public wires:          19
432s    Number of public wire bits:      97
432s    Number of memories:               0
432s    Number of memory bits:            0
432s    Number of processes:              0
432s    Number of cells:                 87
432s      SB_CARRY                       23
432s      SB_DFF                         27
432s      SB_LUT4                        36
432s      SB_WARMBOOT                     1
432s 
432s 2.49. Executing CHECK pass (checking for obvious problems).
432s Checking module top...
432s Found and reported 0 problems.
432s 
432s 2.50. Executing JSON backend.
432s 
432s End of script. Logfile hash: 781a5bf3e2, CPU: user 0.97s system 0.01s, MEM: 20.00 MB peak
432s Yosys 0.33 (git sha1 2584903a060)
432s Time spent: 60% 13x read_verilog (0 sec), 9% 1x abc (0 sec), ...
432s nextpnr-ice40 --hx1k --package tq144 --asc app0.asc --pcf icestick.pcf --json app0.json
432s Warning: unmatched constraint 'RX' (on line 4)
432s Warning: unmatched constraint 'TX' (on line 5)
432s Info: constrained 'LED1' to bel 'X13/Y12/io1'
432s Info: constrained 'LED2' to bel 'X13/Y12/io0'
432s Info: constrained 'LED3' to bel 'X13/Y11/io1'
432s Info: constrained 'LED4' to bel 'X13/Y11/io0'
432s Info: constrained 'LED5' to bel 'X13/Y9/io1'
432s Info: constrained 'clk' to bel 'X0/Y8/io1'
432s 
432s Info: Packing constants..
432s Info: Packing IOs..
432s Info: Packing LUT-FFs..
432s Info:        9 LCs used as LUT4 only
432s Info:       27 LCs used as LUT4 and DFF
432s Info: Packing non-LUT FFs..
432s Info:        0 LCs used as DFF only
432s Info: Packing carries..
432s Info:        0 LCs used as CARRY only
432s Info: Packing indirect carry+LUT pairs...
432s Info:        0 LUTs merged into carry LCs
432s Info: Packing RAMs..
432s Info: Placing PLLs..
432s Info: Packing special functions..
432s Info: Packing PLLs..
432s Info: Promoting globals..
432s Info: promoting clk$SB_IO_IN (fanout 27)
432s Info: Constraining chains...
432s Info:        1 LCs used to legalise carry chains.
432s Info: Checksum: 0x7433cbcd
432s 
432s Info: Annotating ports with timing budgets for target frequency 12.00 MHz
432s Info: Checksum: 0xfc7f08ba
432s 
432s Info: Device utilisation:
432s Info: 	         ICESTORM_LC:    39/ 1280     3%
432s Info: 	        ICESTORM_RAM:     0/   16     0%
432s Info: 	               SB_IO:     6/  112     5%
432s Info: 	               SB_GB:     1/    8    12%
432s Info: 	        ICESTORM_PLL:     0/    1     0%
432s Info: 	         SB_WARMBOOT:     1/    1   100%
432s 
432s Info: Placed 6 cells based on constraints.
432s Info: Creating initial analytic placement for 17 cells, random placement wirelen = 356.
432s Info:     at initial placer iter 0, wirelen = 19
432s Info:     at initial placer iter 1, wirelen = 41
432s Info:     at initial placer iter 2, wirelen = 16
432s Info:     at initial placer iter 3, wirelen = 16
432s Info: Running main analytical placer, max placement attempts per cell = 10000.
432s Info:     at iteration #1, type ICESTORM_LC: wirelen solved = 14, spread = 84, legal = 98; time = 0.00s
432s Info:     at iteration #1, type SB_GB: wirelen solved = 98, spread = 98, legal = 98; time = 0.00s
432s Info:     at iteration #1, type SB_WARMBOOT: wirelen solved = 97, spread = 97, legal = 159; time = 0.00s
432s Info:     at iteration #1, type ALL: wirelen solved = 16, spread = 87, legal = 189; time = 0.00s
432s Info:     at iteration #2, type ICESTORM_LC: wirelen solved = 83, spread = 136, legal = 142; time = 0.00s
432s Info:     at iteration #2, type SB_GB: wirelen solved = 142, spread = 142, legal = 142; time = 0.00s
432s Info:     at iteration #2, type SB_WARMBOOT: wirelen solved = 85, spread = 85, legal = 142; time = 0.00s
432s Info:     at iteration #2, type ALL: wirelen solved = 17, spread = 50, legal = 114; time = 0.00s
432s Info:     at iteration #3, type ICESTORM_LC: wirelen solved = 84, spread = 120, legal = 128; time = 0.00s
432s Info:     at iteration #3, type SB_GB: wirelen solved = 128, spread = 128, legal = 128; time = 0.00s
432s Info:     at iteration #3, type SB_WARMBOOT: wirelen solved = 70, spread = 70, legal = 128; time = 0.00s
432s Info:     at iteration #3, type ALL: wirelen solved = 19, spread = 58, legal = 120; time = 0.00s
432s Info:     at iteration #4, type ICESTORM_LC: wirelen solved = 84, spread = 120, legal = 130; time = 0.00s
432s Info:     at iteration #4, type SB_GB: wirelen solved = 130, spread = 130, legal = 130; time = 0.00s
432s Info:     at iteration #4, type SB_WARMBOOT: wirelen solved = 72, spread = 72, legal = 130; time = 0.00s
432s Info:     at iteration #4, type ALL: wirelen solved = 20, spread = 54, legal = 117; time = 0.00s
432s Info:     at iteration #5, type ICESTORM_LC: wirelen solved = 87, spread = 124, legal = 134; time = 0.00s
432s Info:     at iteration #5, type SB_GB: wirelen solved = 134, spread = 134, legal = 134; time = 0.00s
432s Info:     at iteration #5, type SB_WARMBOOT: wirelen solved = 77, spread = 77, legal = 134; time = 0.00s
432s Info:     at iteration #5, type ALL: wirelen solved = 23, spread = 54, legal = 117; time = 0.00s
432s Info:     at iteration #6, type ICESTORM_LC: wirelen solved = 84, spread = 124, legal = 129; time = 0.00s
432s Info:     at iteration #6, type SB_GB: wirelen solved = 129, spread = 129, legal = 129; time = 0.00s
432s Info:     at iteration #6, type SB_WARMBOOT: wirelen solved = 72, spread = 72, legal = 129; time = 0.00s
432s Info:     at iteration #6, type ALL: wirelen solved = 23, spread = 54, legal = 117; time = 0.00s
432s Info:     at iteration #7, type ICESTORM_LC: wirelen solved = 84, spread = 124, legal = 134; time = 0.00s
432s Info:     at iteration #7, type SB_GB: wirelen solved = 134, spread = 134, legal = 134; time = 0.00s
432s Info:     at iteration #7, type SB_WARMBOOT: wirelen solved = 77, spread = 77, legal = 134; time = 0.00s
432s Info:     at iteration #7, type ALL: wirelen solved = 29, spread = 56, legal = 117; time = 0.00s
432s Info: HeAP Placer Time: 0.02s
432s Info:   of which solving equations: 0.01s
432s Info:   of which spreading cells: 0.00s
432s Info:   of which strict legalisation: 0.00s
432s 
432s Info: Running simulated annealing placer for refinement.
432s Info:   at iteration #1: temp = 0.000000, timing cost = 16, wirelen = 114
432s Info:   at iteration #5: temp = 0.000000, timing cost = 10, wirelen = 106
432s Info:   at iteration #7: temp = 0.000000, timing cost = 10, wirelen = 100 
432s Info: SA placement time 0.01s
432s 
432s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 173.52 MHz (PASS at 12.00 MHz)
432s 
432s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> <async>: 4.21 ns
432s 
432s Info: Slack histogram:
432s Info:  legend: * represents 1 endpoint(s)
432s Info:          + represents [1,1) endpoint(s)
432s Info: [ 77570,  77802) |** 
432s Info: [ 77802,  78034) |* 
432s Info: [ 78034,  78266) |* 
432s Info: [ 78266,  78498) |** 
432s Info: [ 78498,  78730) |** 
432s Info: [ 78730,  78962) |** 
432s Info: [ 78962,  79194) |* 
432s Info: [ 79194,  79426) |** 
432s Info: [ 79426,  79658) |** 
432s Info: [ 79658,  79890) |*** 
432s Info: [ 79890,  80122) |** 
432s Info: [ 80122,  80354) |* 
432s Info: [ 80354,  80586) | 
432s Info: [ 80586,  80818) |** 
432s Info: [ 80818,  81050) |** 
432s Info: [ 81050,  81282) |** 
432s Info: [ 81282,  81514) | 
432s Info: [ 81514,  81746) | 
432s Info: [ 81746,  81978) |**************************** 
432s Info: [ 81978,  82210) |* 
432s Info: Checksum: 0x2221aadc
432s 
432s Info: Routing..
432s Info: Setting up routing queue.
432s Info: Routing 124 arcs.
432s Info:            |   (re-)routed arcs  |   delta    | remaining|       time spent     |
432s Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|
432s Info:        124 |        0        104 |    0   104 |         0|       0.01       0.01|
432s Info: Routing complete.
432s Info: Router1 time 0.01s
432s Info: Checksum: 0xd24a3352
432s 
432s Info: Critical path report for clock 'clk$SB_IO_IN_$glb_clk' (posedge -> posedge):
432s Info: curr total
432s Info:  0.5  0.5  Source counter_SB_LUT4_I2_7_LC.O
432s Info:  0.6  1.1    Net counter[2] budget 20.291000 ns (11,9) -> (12,9)
432s Info:                Sink state_SB_LUT4_I3_I1_SB_LUT4_O_1_I3_SB_LUT4_O_LC.I0
432s Info:                Defined in:
432s Info:                  app0.v:7.22-7.29
432s Info:  0.4  1.6  Source state_SB_LUT4_I3_I1_SB_LUT4_O_1_I3_SB_LUT4_O_LC.O
432s Info:  0.6  2.2    Net state_SB_LUT4_I3_I1_SB_LUT4_O_1_I3[2] budget 20.291000 ns (12,9) -> (12,9)
432s Info:                Sink state_SB_LUT4_I3_I1_SB_LUT4_O_1_LC.I3
432s Info:                Defined in:
432s Info:                  /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
432s Info:  0.3  2.5  Source state_SB_LUT4_I3_I1_SB_LUT4_O_1_LC.O
432s Info:  1.0  3.4    Net state_SB_LUT4_I3_I1[0] budget 20.291000 ns (12,9) -> (12,12)
432s Info:                Sink counter2_SB_DFF_Q_D_SB_LUT4_O_3_I1_SB_LUT4_O_LC.I2
432s Info:                Defined in:
432s icetime -d hx1k -c 25 app0.asc
432s // Reading input .asc file..
432s // Reading 1k chipdb file..
432s Info:                  /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
432s Info:  0.4  3.8  Source counter2_SB_DFF_Q_D_SB_LUT4_O_3_I1_SB_LUT4_O_LC.O
432s Info:  0.6  4.4    Net counter2_SB_DFF_Q_D_SB_LUT4_O_3_I1 budget 20.290001 ns (12,12) -> (12,12)
432s Info:                Sink counter2_SB_DFF_Q_D_SB_LUT4_O_3_LC.I1
432s Info:                Defined in:
432s Info:                  app0.v:13.15-13.34
432s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:29.22-29.23
432s Info:  0.3  4.7  Source counter2_SB_DFF_Q_D_SB_LUT4_O_3_LC.COUT
432s Info:  0.0  4.7    Net counter2_SB_DFF_Q_D_SB_LUT4_O_3_I1_SB_CARRY_I0_CO[1] budget 0.000000 ns (12,12) -> (12,12)
432s Info:                Sink counter2_SB_DFF_Q_D_SB_LUT4_O_2_LC.CIN
432s Info:                Defined in:
432s Info:                  app0.v:13.15-13.34
432s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
432s Info:  0.1  4.8  Source counter2_SB_DFF_Q_D_SB_LUT4_O_2_LC.COUT
432s Info:  0.0  4.8    Net counter2_SB_DFF_Q_D_SB_LUT4_O_3_I1_SB_CARRY_I0_CO[2] budget 0.000000 ns (12,12) -> (12,12)
432s Info:                Sink counter2_SB_DFF_Q_D_SB_LUT4_O_1_LC.CIN
432s Info:                Defined in:
432s Info:                  app0.v:13.15-13.34
432s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
432s Info:  0.1  4.9  Source counter2_SB_DFF_Q_D_SB_LUT4_O_1_LC.COUT
432s Info:  0.3  5.2    Net counter2_SB_DFF_Q_D_SB_LUT4_O_3_I1_SB_CARRY_I0_CO[3] budget 0.260000 ns (12,12) -> (12,12)
432s Info:                Sink counter2_SB_DFF_Q_D_SB_LUT4_O_LC.I3
432s Info:                Defined in:
432s Info:                  app0.v:13.15-13.34
432s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
432s Info:  0.3  5.5  Setup counter2_SB_DFF_Q_D_SB_LUT4_O_LC.I3
432s Info: 2.5 ns logic, 3.0 ns routing
432s 
432s Info: Critical path report for cross-domain path 'posedge clk$SB_IO_IN_$glb_clk' -> '<async>':
432s Info: curr total
432s Info:  0.5  0.5  Source counter2_SB_DFF_Q_D_SB_LUT4_O_3_LC.O
432s Info:  0.6  1.1    Net counter2[0] budget 41.173000 ns (12,12) -> (12,12)
432s Info:                Sink WB_BOOT_SB_LUT4_O_LC.I0
432s Info:                Defined in:
432s Info:                  app0.v:8.12-8.20
432s Info:  0.4  1.6  Source WB_BOOT_SB_LUT4_O_LC.O
432s Info:  1.4  3.0    Net WB_BOOT budget 41.172001 ns (12,12) -> (0,0)
432s Info:                Sink WB.BOOT
432s Info:                Defined in:
432s Info:                  app0.v:24.9-24.18
432s Info: 1.0 ns logic, 2.0 ns routing
432s 
432s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 181.49 MHz (PASS at 12.00 MHz)
432s 
432s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> <async>: 3.02 ns
432s 
432s Info: Slack histogram:
432s Info:  legend: * represents 1 endpoint(s)
432s Info:          + represents [1,1) endpoint(s)
432s Info: [ 77823,  78043) |** 
432s Info: [ 78043,  78263) |* 
432s Info: [ 78263,  78483) |* 
432s Info: [ 78483,  78703) |*** 
432s Info: [ 78703,  78923) |* 
432s Info: [ 78923,  79143) |** 
432s Info: [ 79143,  79363) | 
432s Info: [ 79363,  79583) |*** 
432s Info: [ 79583,  79803) |*** 
432s Info: [ 79803,  80023) |** 
432s Info: [ 80023,  80243) |** 
432s Info: [ 80243,  80463) |* 
432s Info: [ 80463,  80683) |* 
432s Info: [ 80683,  80903) |** 
432s Info: [ 80903,  81123) |** 
432s Info: [ 81123,  81343) |* 
432s Info: [ 81343,  81563) | 
432s Info: [ 81563,  81783) | 
432s Info: [ 81783,  82003) |**************************** 
432s Info: [ 82003,  82223) |* 
432s 2 warnings, 0 errors
432s 
432s Info: Program finished normally.
432s // Creating timing netlist..
432s // Timing estimate: 5.57 ns (179.52 MHz)
432s // Checking 40.00 ns (25.00 MHz) clock constraint: PASSED.
432s icepack app0.asc app0.bin
432s yosys -p "synth_ice40 -top top -json app1.json" app1.v
432s 
432s  /----------------------------------------------------------------------------\
432s  |                                                                            |
432s  |  yosys -- Yosys Open SYnthesis Suite                                       |
432s  |                                                                            |
432s  |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
432s  |                                                                            |
432s  |  Permission to use, copy, modify, and/or distribute this software for any  |
432s  |  purpose with or without fee is hereby granted, provided that the above    |
432s  |  copyright notice and this permission notice appear in all copies.         |
432s  |                                                                            |
432s  |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
432s  |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
432s  |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
432s  |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
432s  |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
432s  |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
432s  |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
432s  |                                                                            |
432s  \----------------------------------------------------------------------------/
432s 
432s  Yosys 0.33 (git sha1 2584903a060)
432s 
432s 
432s -- Parsing `app1.v' using frontend ` -vlog2k' --
432s 
432s 1. Executing Verilog-2005 frontend: app1.v
432s Parsing Verilog input from `app1.v' to AST representation.
432s Storing AST representation for module `$abstract\top'.
432s Successfully finished Verilog frontend.
432s 
432s -- Running command `synth_ice40 -top top -json app1.json' --
432s 
432s 2. Executing SYNTH_ICE40 pass.
432s 
432s 2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v
432s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation.
432s Generating RTLIL representation for module `\SB_IO'.
432s Generating RTLIL representation for module `\SB_GB_IO'.
432s Generating RTLIL representation for module `\SB_GB'.
432s Generating RTLIL representation for module `\SB_LUT4'.
432s Generating RTLIL representation for module `\SB_CARRY'.
432s Generating RTLIL representation for module `\SB_DFF'.
432s Generating RTLIL representation for module `\SB_DFFE'.
432s Generating RTLIL representation for module `\SB_DFFSR'.
432s Generating RTLIL representation for module `\SB_DFFR'.
432s Generating RTLIL representation for module `\SB_DFFSS'.
432s Generating RTLIL representation for module `\SB_DFFS'.
432s Generating RTLIL representation for module `\SB_DFFESR'.
432s Generating RTLIL representation for module `\SB_DFFER'.
432s Generating RTLIL representation for module `\SB_DFFESS'.
432s Generating RTLIL representation for module `\SB_DFFES'.
432s Generating RTLIL representation for module `\SB_DFFN'.
432s Generating RTLIL representation for module `\SB_DFFNE'.
432s Generating RTLIL representation for module `\SB_DFFNSR'.
432s Generating RTLIL representation for module `\SB_DFFNR'.
432s Generating RTLIL representation for module `\SB_DFFNSS'.
432s Generating RTLIL representation for module `\SB_DFFNS'.
432s Generating RTLIL representation for module `\SB_DFFNESR'.
432s Generating RTLIL representation for module `\SB_DFFNER'.
432s Generating RTLIL representation for module `\SB_DFFNESS'.
432s Generating RTLIL representation for module `\SB_DFFNES'.
432s Generating RTLIL representation for module `\SB_RAM40_4K'.
432s Generating RTLIL representation for module `\SB_RAM40_4KNR'.
432s Generating RTLIL representation for module `\SB_RAM40_4KNW'.
432s Generating RTLIL representation for module `\SB_RAM40_4KNRNW'.
432s Generating RTLIL representation for module `\ICESTORM_LC'.
432s Generating RTLIL representation for module `\SB_PLL40_CORE'.
432s Generating RTLIL representation for module `\SB_PLL40_PAD'.
432s Generating RTLIL representation for module `\SB_PLL40_2_PAD'.
432s Generating RTLIL representation for module `\SB_PLL40_2F_CORE'.
432s Generating RTLIL representation for module `\SB_PLL40_2F_PAD'.
432s Generating RTLIL representation for module `\SB_WARMBOOT'.
432s Generating RTLIL representation for module `\SB_SPRAM256KA'.
432s Generating RTLIL representation for module `\SB_HFOSC'.
432s Generating RTLIL representation for module `\SB_LFOSC'.
432s Generating RTLIL representation for module `\SB_RGBA_DRV'.
432s Generating RTLIL representation for module `\SB_LED_DRV_CUR'.
432s Generating RTLIL representation for module `\SB_RGB_DRV'.
432s Generating RTLIL representation for module `\SB_I2C'.
432s Generating RTLIL representation for module `\SB_SPI'.
432s Generating RTLIL representation for module `\SB_LEDDA_IP'.
432s Generating RTLIL representation for module `\SB_FILTER_50NS'.
432s Generating RTLIL representation for module `\SB_IO_I3C'.
432s Generating RTLIL representation for module `\SB_IO_OD'.
432s Generating RTLIL representation for module `\SB_MAC16'.
432s Generating RTLIL representation for module `\ICESTORM_RAM'.
432s Successfully finished Verilog frontend.
432s 
432s 2.2. Executing HIERARCHY pass (managing design hierarchy).
432s 
432s 2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\top'.
432s Generating RTLIL representation for module `\top'.
432s 
432s 2.3.1. Analyzing design hierarchy..
432s Top module:  \top
432s 
432s 2.3.2. Analyzing design hierarchy..
432s Top module:  \top
432s Removing unused module `$abstract\top'.
432s Removed 1 unused modules.
432s 
432s 2.4. Executing PROC pass (convert processes to netlists).
432s 
432s 2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
432s Cleaned up 0 empty switches.
432s 
432s 2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
432s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241 in module SB_DFFNES.
432s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234 in module SB_DFFNESS.
432s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230 in module SB_DFFNER.
432s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223 in module SB_DFFNESR.
432s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220 in module SB_DFFNS.
432s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217 in module SB_DFFNSS.
432s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214 in module SB_DFFNR.
432s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211 in module SB_DFFNSR.
432s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203 in module SB_DFFES.
432s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196 in module SB_DFFESS.
432s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192 in module SB_DFFER.
432s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185 in module SB_DFFESR.
432s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182 in module SB_DFFS.
432s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179 in module SB_DFFSS.
432s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176 in module SB_DFFR.
432s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173 in module SB_DFFSR.
432s Removed a total of 0 dead cases.
432s 
432s 2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
432s Removed 8 redundant assignments.
432s Promoted 28 assignments to connections.
432s 
432s 2.4.4. Executing PROC_INIT pass (extract init attributes).
432s Found init rule in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'.
432s   Set init value: \Q = 1'0
432s Found init rule in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'.
432s   Set init value: \Q = 1'0
432s Found init rule in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'.
432s   Set init value: \Q = 1'0
432s Found init rule in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'.
432s   Set init value: \Q = 1'0
432s Found init rule in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'.
432s   Set init value: \Q = 1'0
432s Found init rule in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'.
432s   Set init value: \Q = 1'0
432s Found init rule in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'.
432s   Set init value: \Q = 1'0
432s Found init rule in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'.
432s   Set init value: \Q = 1'0
432s Found init rule in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'.
432s   Set init value: \Q = 1'0
432s Found init rule in `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'.
432s   Set init value: \Q = 1'0
432s Found init rule in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'.
432s   Set init value: \Q = 1'0
432s Found init rule in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'.
432s   Set init value: \Q = 1'0
432s Found init rule in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'.
432s   Set init value: \Q = 1'0
432s Found init rule in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'.
432s   Set init value: \Q = 1'0
432s Found init rule in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'.
432s   Set init value: \Q = 1'0
432s Found init rule in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'.
432s   Set init value: \Q = 1'0
432s Found init rule in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'.
432s   Set init value: \Q = 1'0
432s Found init rule in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'.
432s   Set init value: \Q = 1'0
432s Found init rule in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'.
432s   Set init value: \Q = 1'0
432s Found init rule in `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'.
432s   Set init value: \Q = 1'0
432s Found init rule in `\top.$proc$app1.v:9$390'.
432s   Set init value: \state = 1'0
432s Found init rule in `\top.$proc$app1.v:8$389'.
432s   Set init value: \counter2 = 4'0000
432s Found init rule in `\top.$proc$app1.v:7$388'.
432s   Set init value: \counter = 22'0000000000000000000000
432s 
432s 2.4.5. Executing PROC_ARST pass (detect async resets in processes).
432s Found async reset \S in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
432s Found async reset \R in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
432s Found async reset \S in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
432s Found async reset \R in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
432s Found async reset \S in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
432s Found async reset \R in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
432s Found async reset \S in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'.
432s Found async reset \R in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'.
432s 
432s 2.4.6. Executing PROC_ROM pass (convert switches to ROMs).
432s Converted 0 switches.
432s <suppressed ~18 debug messages>
432s 
432s 2.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
432s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'.
432s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
432s      1/1: $0\Q[0:0]
432s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'.
432s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
432s      1/1: $0\Q[0:0]
432s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'.
432s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
432s      1/1: $0\Q[0:0]
432s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'.
432s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
432s      1/1: $0\Q[0:0]
432s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'.
432s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
432s      1/1: $0\Q[0:0]
432s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'.
432s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
432s      1/1: $0\Q[0:0]
432s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'.
432s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
432s      1/1: $0\Q[0:0]
432s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'.
432s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'.
432s      1/1: $0\Q[0:0]
432s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'.
432s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'.
432s      1/1: $0\Q[0:0]
432s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'.
432s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'.
432s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'.
432s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
432s      1/1: $0\Q[0:0]
432s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'.
432s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'.
432s      1/1: $0\Q[0:0]
432s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'.
432s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
432s      1/1: $0\Q[0:0]
432s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'.
432s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'.
432s      1/1: $0\Q[0:0]
432s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'.
432s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'.
432s      1/1: $0\Q[0:0]
432s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'.
432s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'.
432s      1/1: $0\Q[0:0]
432s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'.
432s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'.
432s      1/1: $0\Q[0:0]
432s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'.
432s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'.
432s      1/1: $0\Q[0:0]
432s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'.
432s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'.
432s      1/1: $0\Q[0:0]
432s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'.
432s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'.
432s Creating decoders for process `\top.$proc$app1.v:9$390'.
432s Creating decoders for process `\top.$proc$app1.v:8$389'.
432s Creating decoders for process `\top.$proc$app1.v:7$388'.
432s Creating decoders for process `\top.$proc$app1.v:11$381'.
432s 
432s 2.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
432s 
432s 2.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
432s Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
432s   created $adff cell `$procdff$435' with negative edge clock and positive level reset.
432s Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
432s   created $dff cell `$procdff$436' with negative edge clock.
432s Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
432s   created $adff cell `$procdff$437' with negative edge clock and positive level reset.
432s Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
432s   created $dff cell `$procdff$438' with negative edge clock.
432s Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
432s   created $adff cell `$procdff$439' with negative edge clock and positive level reset.
432s Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
432s   created $dff cell `$procdff$440' with negative edge clock.
432s Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
432s   created $adff cell `$procdff$441' with negative edge clock and positive level reset.
432s Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'.
432s   created $dff cell `$procdff$442' with negative edge clock.
432s Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'.
432s   created $dff cell `$procdff$443' with negative edge clock.
432s Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'.
432s   created $dff cell `$procdff$444' with negative edge clock.
432s Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
432s   created $adff cell `$procdff$445' with positive edge clock and positive level reset.
432s Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'.
432s   created $dff cell `$procdff$446' with positive edge clock.
432s Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
432s   created $adff cell `$procdff$447' with positive edge clock and positive level reset.
432s Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'.
432s   created $dff cell `$procdff$448' with positive edge clock.
432s Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'.
432s   created $adff cell `$procdff$449' with positive edge clock and positive level reset.
432s Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'.
432s   created $dff cell `$procdff$450' with positive edge clock.
432s Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'.
432s   created $adff cell `$procdff$451' with positive edge clock and positive level reset.
432s Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'.
432s   created $dff cell `$procdff$452' with positive edge clock.
432s Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'.
432s   created $dff cell `$procdff$453' with positive edge clock.
432s Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'.
432s   created $dff cell `$procdff$454' with positive edge clock.
432s Creating register for signal `\top.\counter' using process `\top.$proc$app1.v:11$381'.
432s   created $dff cell `$procdff$455' with positive edge clock.
432s Creating register for signal `\top.\counter2' using process `\top.$proc$app1.v:11$381'.
432s   created $dff cell `$procdff$456' with positive edge clock.
432s Creating register for signal `\top.\state' using process `\top.$proc$app1.v:11$381'.
432s   created $dff cell `$procdff$457' with positive edge clock.
432s 
432s 2.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
432s 
432s 2.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
433s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'.
433s Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
433s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
433s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'.
433s Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
433s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
433s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'.
433s Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
433s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
433s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'.
433s Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
433s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
433s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'.
433s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
433s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'.
433s Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
433s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
433s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'.
433s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
433s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'.
433s Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'.
433s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'.
433s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'.
433s Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'.
433s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'.
433s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'.
433s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'.
433s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'.
433s Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
433s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
433s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'.
433s Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'.
433s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'.
433s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'.
433s Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
433s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
433s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'.
433s Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'.
433s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'.
433s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'.
433s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'.
433s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'.
433s Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'.
433s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'.
433s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'.
433s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'.
433s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'.
433s Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'.
433s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'.
433s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'.
433s Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'.
433s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'.
433s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'.
433s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'.
433s Removing empty process `top.$proc$app1.v:9$390'.
433s Removing empty process `top.$proc$app1.v:8$389'.
433s Removing empty process `top.$proc$app1.v:7$388'.
433s Removing empty process `top.$proc$app1.v:11$381'.
433s Cleaned up 18 empty switches.
433s 
433s 2.4.12. Executing OPT_EXPR pass (perform const folding).
433s Optimizing module top.
433s 
433s 2.5. Executing FLATTEN pass (flatten design).
433s 
433s 2.6. Executing TRIBUF pass.
433s 
433s 2.7. Executing DEMINOUT pass (demote inout ports to input or output).
433s 
433s 2.8. Executing OPT_EXPR pass (perform const folding).
433s Optimizing module top.
433s 
433s 2.9. Executing OPT_CLEAN pass (remove unused cells and wires).
433s Finding unused cells or wires in module \top..
433s Removed 0 unused cells and 5 unused wires.
433s <suppressed ~1 debug messages>
433s 
433s 2.10. Executing CHECK pass (checking for obvious problems).
433s Checking module top...
433s Found and reported 0 problems.
433s 
433s 2.11. Executing OPT pass (performing simple optimizations).
433s 
433s 2.11.1. Executing OPT_EXPR pass (perform const folding).
433s Optimizing module top.
433s 
433s 2.11.2. Executing OPT_MERGE pass (detect identical cells).
433s Finding identical cells in module `\top'.
433s Removed a total of 0 cells.
433s 
433s 2.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
433s Running muxtree optimizer on module \top..
433s   Creating internal representation of mux trees.
433s   No muxes found in this module.
433s Removed 0 multiplexer ports.
433s 
433s 2.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
433s   Optimizing cells in module \top.
433s Performed a total of 0 changes.
433s 
433s 2.11.5. Executing OPT_MERGE pass (detect identical cells).
433s Finding identical cells in module `\top'.
433s Removed a total of 0 cells.
433s 
433s 2.11.6. Executing OPT_DFF pass (perform DFF optimizations).
433s 
433s 2.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
433s Finding unused cells or wires in module \top..
433s 
433s 2.11.8. Executing OPT_EXPR pass (perform const folding).
433s Optimizing module top.
433s 
433s 2.11.9. Finished OPT passes. (There is nothing left to do.)
433s 
433s 2.12. Executing FSM pass (extract and optimize FSM).
433s 
433s 2.12.1. Executing FSM_DETECT pass (finding FSMs in design).
433s 
433s 2.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).
433s 
433s 2.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).
433s 
433s 2.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
433s Finding unused cells or wires in module \top..
433s 
433s 2.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).
433s 
433s 2.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
433s 
433s 2.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
433s 
433s 2.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
433s 
433s 2.13. Executing OPT pass (performing simple optimizations).
433s 
433s 2.13.1. Executing OPT_EXPR pass (perform const folding).
433s Optimizing module top.
433s 
433s 2.13.2. Executing OPT_MERGE pass (detect identical cells).
433s Finding identical cells in module `\top'.
433s Removed a total of 0 cells.
433s 
433s 2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
433s Running muxtree optimizer on module \top..
433s   Creating internal representation of mux trees.
433s   No muxes found in this module.
433s Removed 0 multiplexer ports.
433s 
433s 2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
433s   Optimizing cells in module \top.
433s Performed a total of 0 changes.
433s 
433s 2.13.5. Executing OPT_MERGE pass (detect identical cells).
433s Finding identical cells in module `\top'.
433s Removed a total of 0 cells.
433s 
433s 2.13.6. Executing OPT_DFF pass (perform DFF optimizations).
433s 
433s 2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
433s Finding unused cells or wires in module \top..
433s 
433s 2.13.8. Executing OPT_EXPR pass (perform const folding).
433s Optimizing module top.
433s 
433s 2.13.9. Finished OPT passes. (There is nothing left to do.)
433s 
433s 2.14. Executing WREDUCE pass (reducing word size of cells).
433s Removed top 31 bits (of 32) from port B of cell top.$add$app1.v:12$382 ($add).
433s Removed top 10 bits (of 32) from port Y of cell top.$add$app1.v:12$382 ($add).
433s Removed top 3 bits (of 4) from port B of cell top.$add$app1.v:13$384 ($add).
433s Removed top 3 bits (of 4) from wire top.$logic_not$app1.v:13$383_Y.
433s 
433s 2.15. Executing PEEPOPT pass (run peephole optimizers).
433s 
433s 2.16. Executing OPT_CLEAN pass (remove unused cells and wires).
433s Finding unused cells or wires in module \top..
433s Removed 0 unused cells and 2 unused wires.
433s <suppressed ~1 debug messages>
433s 
433s 2.17. Executing SHARE pass (SAT-based resource sharing).
433s 
433s 2.18. Executing TECHMAP pass (map to technology primitives).
433s 
433s 2.18.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v
433s Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation.
433s Generating RTLIL representation for module `\_90_lut_cmp_'.
433s Successfully finished Verilog frontend.
433s 
433s 2.18.2. Continuing TECHMAP pass.
433s No more expansions possible.
433s <suppressed ~6 debug messages>
433s 
433s 2.19. Executing OPT_EXPR pass (perform const folding).
433s Optimizing module top.
433s 
433s 2.20. Executing OPT_CLEAN pass (remove unused cells and wires).
433s Finding unused cells or wires in module \top..
433s 
433s 2.21. Executing ALUMACC pass (create $alu and $macc cells).
433s Extracting $alu and $macc cells in module top:
433s   creating $macc model for $add$app1.v:12$382 ($add).
433s   creating $macc model for $add$app1.v:13$384 ($add).
433s   creating $alu model for $macc $add$app1.v:13$384.
433s   creating $alu model for $macc $add$app1.v:12$382.
433s   creating $alu cell for $add$app1.v:12$382: $auto$alumacc.cc:485:replace_alu$460
433s   creating $alu cell for $add$app1.v:13$384: $auto$alumacc.cc:485:replace_alu$463
433s   created 2 $alu and 0 $macc cells.
433s 
433s 2.22. Executing OPT pass (performing simple optimizations).
433s 
433s 2.22.1. Executing OPT_EXPR pass (perform const folding).
433s Optimizing module top.
433s 
433s 2.22.2. Executing OPT_MERGE pass (detect identical cells).
433s Finding identical cells in module `\top'.
433s <suppressed ~3 debug messages>
433s Removed a total of 1 cells.
433s 
433s 2.22.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
433s Running muxtree optimizer on module \top..
433s   Creating internal representation of mux trees.
433s   No muxes found in this module.
433s Removed 0 multiplexer ports.
433s 
433s 2.22.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
433s   Optimizing cells in module \top.
433s Performed a total of 0 changes.
433s 
433s 2.22.5. Executing OPT_MERGE pass (detect identical cells).
433s Finding identical cells in module `\top'.
433s Removed a total of 0 cells.
433s 
433s 2.22.6. Executing OPT_DFF pass (perform DFF optimizations).
433s 
433s 2.22.7. Executing OPT_CLEAN pass (remove unused cells and wires).
433s Finding unused cells or wires in module \top..
433s Removed 0 unused cells and 1 unused wires.
433s <suppressed ~1 debug messages>
433s 
433s 2.22.8. Executing OPT_EXPR pass (perform const folding).
433s Optimizing module top.
433s 
433s 2.22.9. Rerunning OPT passes. (Maybe there is more to do..)
433s 
433s 2.22.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
433s Running muxtree optimizer on module \top..
433s   Creating internal representation of mux trees.
433s   No muxes found in this module.
433s Removed 0 multiplexer ports.
433s 
433s 2.22.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
433s   Optimizing cells in module \top.
433s Performed a total of 0 changes.
433s 
433s 2.22.12. Executing OPT_MERGE pass (detect identical cells).
433s Finding identical cells in module `\top'.
433s Removed a total of 0 cells.
433s 
433s 2.22.13. Executing OPT_DFF pass (perform DFF optimizations).
433s 
433s 2.22.14. Executing OPT_CLEAN pass (remove unused cells and wires).
433s Finding unused cells or wires in module \top..
433s 
433s 2.22.15. Executing OPT_EXPR pass (perform const folding).
433s Optimizing module top.
433s 
433s 2.22.16. Finished OPT passes. (There is nothing left to do.)
433s 
433s 2.23. Executing MEMORY pass.
433s 
433s 2.23.1. Executing OPT_MEM pass (optimize memories).
433s Performed a total of 0 transformations.
433s 
433s 2.23.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
433s Performed a total of 0 transformations.
433s 
433s 2.23.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
433s 
433s 2.23.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
433s 
433s 2.23.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
433s 
433s 2.23.6. Executing OPT_CLEAN pass (remove unused cells and wires).
433s Finding unused cells or wires in module \top..
433s 
433s 2.23.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
433s 
433s 2.23.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
433s Performed a total of 0 transformations.
433s 
433s 2.23.9. Executing OPT_CLEAN pass (remove unused cells and wires).
433s Finding unused cells or wires in module \top..
433s 
433s 2.23.10. Executing MEMORY_COLLECT pass (generating $mem cells).
433s 
433s 2.24. Executing OPT_CLEAN pass (remove unused cells and wires).
433s Finding unused cells or wires in module \top..
433s 
433s 2.25. Executing MEMORY_LIBMAP pass (mapping memories to cells).
433s 
433s 2.26. Executing TECHMAP pass (map to technology primitives).
433s 
433s 2.26.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v
433s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation.
433s Generating RTLIL representation for module `\$__ICE40_RAM4K_'.
433s Successfully finished Verilog frontend.
433s 
433s 2.26.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/spram_map.v
433s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/spram_map.v' to AST representation.
433s Generating RTLIL representation for module `\$__ICE40_SPRAM_'.
433s Successfully finished Verilog frontend.
433s 
433s 2.26.3. Continuing TECHMAP pass.
433s No more expansions possible.
433s <suppressed ~4 debug messages>
433s 
433s 2.27. Executing ICE40_BRAMINIT pass.
433s 
433s 2.28. Executing OPT pass (performing simple optimizations).
433s 
433s 2.28.1. Executing OPT_EXPR pass (perform const folding).
433s Optimizing module top.
433s 
433s 2.28.2. Executing OPT_MERGE pass (detect identical cells).
433s Finding identical cells in module `\top'.
433s Removed a total of 0 cells.
433s 
433s 2.28.3. Executing OPT_DFF pass (perform DFF optimizations).
433s 
433s 2.28.4. Executing OPT_CLEAN pass (remove unused cells and wires).
433s Finding unused cells or wires in module \top..
433s 
433s 2.28.5. Finished fast OPT passes.
433s 
433s 2.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
433s 
433s 2.30. Executing OPT pass (performing simple optimizations).
433s 
433s 2.30.1. Executing OPT_EXPR pass (perform const folding).
433s Optimizing module top.
433s 
433s 2.30.2. Executing OPT_MERGE pass (detect identical cells).
433s Finding identical cells in module `\top'.
433s Removed a total of 0 cells.
433s 
433s 2.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
433s Running muxtree optimizer on module \top..
433s   Creating internal representation of mux trees.
433s   No muxes found in this module.
433s Removed 0 multiplexer ports.
433s 
433s 2.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
433s   Optimizing cells in module \top.
433s Performed a total of 0 changes.
433s 
433s 2.30.5. Executing OPT_MERGE pass (detect identical cells).
433s Finding identical cells in module `\top'.
433s Removed a total of 0 cells.
433s 
433s 2.30.6. Executing OPT_DFF pass (perform DFF optimizations).
433s 
433s 2.30.7. Executing OPT_CLEAN pass (remove unused cells and wires).
433s Finding unused cells or wires in module \top..
433s 
433s 2.30.8. Executing OPT_EXPR pass (perform const folding).
433s Optimizing module top.
433s 
433s 2.30.9. Finished OPT passes. (There is nothing left to do.)
433s 
433s 2.31. Executing ICE40_WRAPCARRY pass (wrap carries).
433s 
433s 2.32. Executing TECHMAP pass (map to technology primitives).
433s 
433s 2.32.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v
433s Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation.
433s Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
433s Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
433s Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
433s Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
433s Generating RTLIL representation for module `\_90_simplemap_various'.
433s Generating RTLIL representation for module `\_90_simplemap_registers'.
433s Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
433s Generating RTLIL representation for module `\_90_shift_shiftx'.
433s Generating RTLIL representation for module `\_90_fa'.
433s Generating RTLIL representation for module `\_90_lcu'.
433s Generating RTLIL representation for module `\_90_alu'.
433s Generating RTLIL representation for module `\_90_macc'.
433s Generating RTLIL representation for module `\_90_alumacc'.
433s Generating RTLIL representation for module `\$__div_mod_u'.
433s Generating RTLIL representation for module `\$__div_mod_trunc'.
433s Generating RTLIL representation for module `\_90_div'.
433s Generating RTLIL representation for module `\_90_mod'.
433s Generating RTLIL representation for module `\$__div_mod_floor'.
433s Generating RTLIL representation for module `\_90_divfloor'.
433s Generating RTLIL representation for module `\_90_modfloor'.
433s Generating RTLIL representation for module `\_90_pow'.
433s Generating RTLIL representation for module `\_90_pmux'.
433s Generating RTLIL representation for module `\_90_demux'.
433s Generating RTLIL representation for module `\_90_lut'.
433s Successfully finished Verilog frontend.
433s 
433s 2.32.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v
433s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation.
433s Generating RTLIL representation for module `\_80_ice40_alu'.
433s Successfully finished Verilog frontend.
433s 
433s 2.32.3. Continuing TECHMAP pass.
433s Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_80_ice40_alu for cells of type $alu.
433s Using extmapper simplemap for cells of type $logic_not.
433s Using template $paramod$080e6a70eb8bfa1ccf22d9718e795074645029a4\_80_ice40_alu for cells of type $alu.
433s Using extmapper simplemap for cells of type $xor.
433s Using extmapper simplemap for cells of type $reduce_and.
433s Using extmapper simplemap for cells of type $dff.
433s Using extmapper simplemap for cells of type $mux.
433s Using extmapper simplemap for cells of type $not.
433s Using extmapper simplemap for cells of type $pos.
433s No more expansions possible.
433s <suppressed ~129 debug messages>
433s 
433s 2.33. Executing OPT pass (performing simple optimizations).
433s 
433s 2.33.1. Executing OPT_EXPR pass (perform const folding).
433s Optimizing module top.
433s <suppressed ~51 debug messages>
433s 
433s 2.33.2. Executing OPT_MERGE pass (detect identical cells).
433s Finding identical cells in module `\top'.
433s <suppressed ~3 debug messages>
433s Removed a total of 1 cells.
433s 
433s 2.33.3. Executing OPT_DFF pass (perform DFF optimizations).
433s 
433s 2.33.4. Executing OPT_CLEAN pass (remove unused cells and wires).
433s Finding unused cells or wires in module \top..
433s Removed 27 unused cells and 34 unused wires.
433s <suppressed ~28 debug messages>
433s 
433s 2.33.5. Finished fast OPT passes.
433s 
433s 2.34. Executing ICE40_OPT pass (performing simple optimizations).
433s 
433s 2.34.1. Running ICE40 specific optimizations.
433s Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$460.slice[0].carry: CO=\counter [0]
433s 
433s 2.34.2. Executing OPT_EXPR pass (perform const folding).
433s Optimizing module top.
433s 
433s 2.34.3. Executing OPT_MERGE pass (detect identical cells).
433s Finding identical cells in module `\top'.
433s Removed a total of 0 cells.
433s 
433s 2.34.4. Executing OPT_DFF pass (perform DFF optimizations).
433s 
433s 2.34.5. Executing OPT_CLEAN pass (remove unused cells and wires).
433s Finding unused cells or wires in module \top..
433s 
433s 2.34.6. Rerunning OPT passes. (Removed registers in this run.)
433s 
433s 2.34.7. Running ICE40 specific optimizations.
433s 
433s 2.34.8. Executing OPT_EXPR pass (perform const folding).
433s Optimizing module top.
433s 
433s 2.34.9. Executing OPT_MERGE pass (detect identical cells).
433s Finding identical cells in module `\top'.
433s Removed a total of 0 cells.
433s 
433s 2.34.10. Executing OPT_DFF pass (perform DFF optimizations).
433s 
433s 2.34.11. Executing OPT_CLEAN pass (remove unused cells and wires).
433s Finding unused cells or wires in module \top..
433s 
433s 2.34.12. Finished OPT passes. (There is nothing left to do.)
433s 
433s 2.35. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
433s 
433s 2.36. Executing TECHMAP pass (map to technology primitives).
433s 
433s 2.36.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v
433s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation.
433s Generating RTLIL representation for module `\$_DFF_N_'.
433s Generating RTLIL representation for module `\$_DFF_P_'.
433s Generating RTLIL representation for module `\$_DFFE_NP_'.
433s Generating RTLIL representation for module `\$_DFFE_PP_'.
433s Generating RTLIL representation for module `\$_DFF_NP0_'.
433s Generating RTLIL representation for module `\$_DFF_NP1_'.
433s Generating RTLIL representation for module `\$_DFF_PP0_'.
433s Generating RTLIL representation for module `\$_DFF_PP1_'.
433s Generating RTLIL representation for module `\$_DFFE_NP0P_'.
433s Generating RTLIL representation for module `\$_DFFE_NP1P_'.
433s Generating RTLIL representation for module `\$_DFFE_PP0P_'.
433s Generating RTLIL representation for module `\$_DFFE_PP1P_'.
433s Generating RTLIL representation for module `\$_SDFF_NP0_'.
433s Generating RTLIL representation for module `\$_SDFF_NP1_'.
433s Generating RTLIL representation for module `\$_SDFF_PP0_'.
433s Generating RTLIL representation for module `\$_SDFF_PP1_'.
433s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
433s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
433s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
433s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
433s Successfully finished Verilog frontend.
433s 
433s 2.36.2. Continuing TECHMAP pass.
433s Using template \$_DFF_P_ for cells of type $_DFF_P_.
433s No more expansions possible.
433s <suppressed ~49 debug messages>
433s 
433s 2.37. Executing OPT_EXPR pass (perform const folding).
433s Optimizing module top.
433s 
433s 2.38. Executing SIMPLEMAP pass (map simple cells to gate primitives).
433s Mapping top.$auto$alumacc.cc:485:replace_alu$460.slice[0].carry ($lut).
433s 
433s 2.39. Executing ICE40_OPT pass (performing simple optimizations).
433s 
433s 2.39.1. Running ICE40 specific optimizations.
433s 
433s 2.39.2. Executing OPT_EXPR pass (perform const folding).
433s Optimizing module top.
433s <suppressed ~14 debug messages>
433s 
433s 2.39.3. Executing OPT_MERGE pass (detect identical cells).
433s Finding identical cells in module `\top'.
433s Removed a total of 0 cells.
433s 
433s 2.39.4. Executing OPT_DFF pass (perform DFF optimizations).
433s 
433s 2.39.5. Executing OPT_CLEAN pass (remove unused cells and wires).
433s Finding unused cells or wires in module \top..
433s Removed 0 unused cells and 112 unused wires.
433s <suppressed ~1 debug messages>
433s 
433s 2.39.6. Rerunning OPT passes. (Removed registers in this run.)
433s 
433s 2.39.7. Running ICE40 specific optimizations.
433s 
433s 2.39.8. Executing OPT_EXPR pass (perform const folding).
433s Optimizing module top.
433s 
433s 2.39.9. Executing OPT_MERGE pass (detect identical cells).
433s Finding identical cells in module `\top'.
433s Removed a total of 0 cells.
433s 
433s 2.39.10. Executing OPT_DFF pass (perform DFF optimizations).
433s 
433s 2.39.11. Executing OPT_CLEAN pass (remove unused cells and wires).
433s Finding unused cells or wires in module \top..
433s 
433s 2.39.12. Finished OPT passes. (There is nothing left to do.)
433s 
433s 2.40. Executing TECHMAP pass (map to technology primitives).
433s 
433s 2.40.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v
433s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation.
433s Generating RTLIL representation for module `\$_DLATCH_N_'.
433s Generating RTLIL representation for module `\$_DLATCH_P_'.
433s Successfully finished Verilog frontend.
433s 
433s 2.40.2. Continuing TECHMAP pass.
433s No more expansions possible.
433s <suppressed ~4 debug messages>
433s 
433s 2.41. Executing ABC pass (technology mapping using ABC).
433s 
433s 2.41.1. Extracting gate netlist of module `\top' to `<abc-temp-dir>/input.blif'..
433s Extracted 27 gates and 54 wires to a netlist network with 27 inputs and 4 outputs.
433s 
433s 2.41.1.1. Executing ABC.
433s Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
433s ABC: ABC command line: "source <abc-temp-dir>/abc.script".
433s ABC: 
433s ABC: + read_blif <abc-temp-dir>/input.blif 
433s ABC: + read_lut <abc-temp-dir>/lutdefs.txt 
433s ABC: + strash 
433s ABC: + &get -n 
433s ABC: + &fraig -x 
433s ABC: + &put 
433s ABC: + scorr 
433s ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
433s ABC: + dc2 
433s ABC: + dretime 
433s ABC: + strash 
433s ABC: + dch -f 
433s ABC: + if 
433s ABC: + mfs2 
433s ABC: + lutpack -S 1 
433s ABC: + dress <abc-temp-dir>/input.blif 
433s ABC: Total number of equiv classes                =       5.
433s ABC: Participating nodes from both networks       =       9.
433s ABC: Participating nodes from the first network   =       4. (  33.33 % of nodes)
433s ABC: Participating nodes from the second network  =       5. (  41.67 % of nodes)
433s ABC: Node pairs (any polarity)                    =       4. (  33.33 % of names can be moved)
433s ABC: Node pairs (same polarity)                   =       4. (  33.33 % of names can be moved)
433s ABC: Total runtime =     0.04 sec
433s ABC: + write_blif <abc-temp-dir>/output.blif 
433s 
433s 2.41.1.2. Re-integrating ABC results.
433s ABC RESULTS:              $lut cells:       11
433s ABC RESULTS:        internal signals:       23
433s ABC RESULTS:           input signals:       27
433s ABC RESULTS:          output signals:        4
433s Removing temp directory.
433s 
433s 2.42. Executing ICE40_WRAPCARRY pass (wrap carries).
433s 
433s 2.43. Executing TECHMAP pass (map to technology primitives).
433s 
433s 2.43.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v
433s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation.
433s Generating RTLIL representation for module `\$_DFF_N_'.
433s Generating RTLIL representation for module `\$_DFF_P_'.
433s Generating RTLIL representation for module `\$_DFFE_NP_'.
433s Generating RTLIL representation for module `\$_DFFE_PP_'.
433s Generating RTLIL representation for module `\$_DFF_NP0_'.
433s Generating RTLIL representation for module `\$_DFF_NP1_'.
433s Generating RTLIL representation for module `\$_DFF_PP0_'.
433s Generating RTLIL representation for module `\$_DFF_PP1_'.
433s Generating RTLIL representation for module `\$_DFFE_NP0P_'.
433s Generating RTLIL representation for module `\$_DFFE_NP1P_'.
433s Generating RTLIL representation for module `\$_DFFE_PP0P_'.
433s Generating RTLIL representation for module `\$_DFFE_PP1P_'.
433s Generating RTLIL representation for module `\$_SDFF_NP0_'.
433s Generating RTLIL representation for module `\$_SDFF_NP1_'.
433s Generating RTLIL representation for module `\$_SDFF_PP0_'.
433s Generating RTLIL representation for module `\$_SDFF_PP1_'.
433s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
433s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
433s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
433s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
433s Successfully finished Verilog frontend.
433s 
433s 2.43.2. Continuing TECHMAP pass.
433s No more expansions possible.
433s <suppressed ~22 debug messages>
433s Removed 2 unused cells and 39 unused wires.
433s 
433s 2.44. Executing OPT_LUT pass (optimize LUTs).
433s Discovering LUTs.
433s Number of LUTs:       36
433s   1-LUT                1
433s   2-LUT                3
433s   3-LUT               25
433s   4-LUT                7
433s   with \SB_CARRY    (#0)   23
433s   with \SB_CARRY    (#1)   23
433s 
433s Eliminating LUTs.
433s Number of LUTs:       36
433s   1-LUT                1
433s   2-LUT                3
433s   3-LUT               25
433s   4-LUT                7
433s   with \SB_CARRY    (#0)   23
433s   with \SB_CARRY    (#1)   23
433s 
433s Combining LUTs.
433s Number of LUTs:       36
433s   1-LUT                1
433s   2-LUT                3
433s   3-LUT               25
433s   4-LUT                7
433s   with \SB_CARRY    (#0)   23
433s   with \SB_CARRY    (#1)   23
433s 
433s Eliminated 0 LUTs.
433s Combined 0 LUTs.
433s <suppressed ~165 debug messages>
433s 
433s 2.45. Executing TECHMAP pass (map to technology primitives).
433s 
433s 2.45.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v
433s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation.
433s Generating RTLIL representation for module `\$lut'.
433s Successfully finished Verilog frontend.
433s 
433s 2.45.2. Continuing TECHMAP pass.
433s Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut.
433s Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut.
433s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut.
433s Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut.
433s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
433s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111000 for cells of type $lut.
433s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
433s No more expansions possible.
433s <suppressed ~130 debug messages>
433s Removed 0 unused cells and 76 unused wires.
433s 
433s 2.46. Executing AUTONAME pass.
433s Renamed 723 objects in module top (15 iterations).
433s <suppressed ~96 debug messages>
433s 
433s 2.47. Executing HIERARCHY pass (managing design hierarchy).
433s 
433s 2.47.1. Analyzing design hierarchy..
433s Top module:  \top
433s 
433s 2.47.2. Analyzing design hierarchy..
433s Top module:  \top
433s Removed 0 unused modules.
433s 
433s 2.48. Printing statistics.
433s 
433s === top ===
433s 
433s    Number of wires:                 19
433s    Number of wire bits:             97
433s    Number of public wires:          19
433s    Number of public wire bits:      97
433s    Number of memories:               0
433s    Number of memory bits:            0
433s    Number of processes:              0
433s    Number of cells:                 87
433s      SB_CARRY                       23
433s      SB_DFF                         27
433s      SB_LUT4                        36
433s      SB_WARMBOOT                     1
433s 
433s 2.49. Executing CHECK pass (checking for obvious problems).
433s Checking module top...
433s Found and reported 0 problems.
433s 
433s 2.50. Executing JSON backend.
433s 
433s End of script. Logfile hash: ff033ab96e, CPU: user 0.97s system 0.01s, MEM: 20.00 MB peak
433s Yosys 0.33 (git sha1 2584903a060)
433s Time spent: 60% 13x read_verilog (0 sec), 9% 1x abc (0 sec), ...
433s nextpnr-ice40 --hx1k --package tq144 --asc app1.asc --pcf icestick.pcf --json app1.json
434s Warning: unmatched constraint 'RX' (on line 4)
434s Warning: unmatched constraint 'TX' (on line 5)
434s Info: constrained 'LED1' to bel 'X13/Y12/io1'
434s Info: constrained 'LED2' to bel 'X13/Y12/io0'
434s Info: constrained 'LED3' to bel 'X13/Y11/io1'
434s Info: constrained 'LED4' to bel 'X13/Y11/io0'
434s Info: constrained 'LED5' to bel 'X13/Y9/io1'
434s Info: constrained 'clk' to bel 'X0/Y8/io1'
434s 
434s Info: Packing constants..
434s Info: Packing IOs..
434s Info: Packing LUT-FFs..
434s Info:        9 LCs used as LUT4 only
434s Info:       27 LCs used as LUT4 and DFF
434s Info: Packing non-LUT FFs..
434s Info:        0 LCs used as DFF only
434s Info: Packing carries..
434s Info:        0 LCs used as CARRY only
434s Info: Packing indirect carry+LUT pairs...
434s Info:        0 LUTs merged into carry LCs
434s Info: Packing RAMs..
434s Info: Placing PLLs..
434s Info: Packing special functions..
434s Info: Packing PLLs..
434s Info: Promoting globals..
434s Info: promoting clk$SB_IO_IN (fanout 27)
434s Info: Constraining chains...
434s Info:        1 LCs used to legalise carry chains.
434s Info: Checksum: 0xaa8ed617
434s 
434s Info: Annotating ports with timing budgets for target frequency 12.00 MHz
434s Info: Checksum: 0x374ab397
434s 
434s Info: Device utilisation:
434s Info: 	         ICESTORM_LC:    39/ 1280     3%
434s Info: 	        ICESTORM_RAM:     0/   16     0%
434s Info: 	               SB_IO:     6/  112     5%
434s Info: 	               SB_GB:     1/    8    12%
434s Info: 	        ICESTORM_PLL:     0/    1     0%
434s Info: 	         SB_WARMBOOT:     1/    1   100%
434s 
434s Info: Placed 6 cells based on constraints.
434s Info: Creating initial analytic placement for 17 cells, random placement wirelen = 356.
434s Info:     at initial placer iter 0, wirelen = 19
434s Info:     at initial placer iter 1, wirelen = 41
434s Info:     at initial placer iter 2, wirelen = 16
434s Info:     at initial placer iter 3, wirelen = 16
434s Info: Running main analytical placer, max placement attempts per cell = 10000.
434s Info:     at iteration #1, type ICESTORM_LC: wirelen solved = 14, spread = 84, legal = 98; time = 0.00s
434s Info:     at iteration #1, type SB_GB: wirelen solved = 98, spread = 98, legal = 98; time = 0.00s
434s Info:     at iteration #1, type SB_WARMBOOT: wirelen solved = 97, spread = 97, legal = 159; time = 0.00s
434s Info:     at iteration #1, type ALL: wirelen solved = 16, spread = 87, legal = 189; time = 0.00s
434s Info:     at iteration #2, type ICESTORM_LC: wirelen solved = 83, spread = 136, legal = 142; time = 0.00s
434s Info:     at iteration #2, type SB_GB: wirelen solved = 142, spread = 142, legal = 142; time = 0.00s
434s Info:     at iteration #2, type SB_WARMBOOT: wirelen solved = 85, spread = 85, legal = 142; time = 0.00s
434s Info:     at iteration #2, type ALL: wirelen solved = 17, spread = 50, legal = 114; time = 0.00s
434s Info:     at iteration #3, type ICESTORM_LC: wirelen solved = 84, spread = 120, legal = 128; time = 0.00s
434s Info:     at iteration #3, type SB_GB: wirelen solved = 128, spread = 128, legal = 128; time = 0.00s
434s Info:     at iteration #3, type SB_WARMBOOT: wirelen solved = 70, spread = 70, legal = 128; time = 0.00s
434s Info:     at iteration #3, type ALL: wirelen solved = 19, spread = 58, legal = 120; time = 0.00s
434s Info:     at iteration #4, type ICESTORM_LC: wirelen solved = 84, spread = 120, legal = 130; time = 0.00s
434s Info:     at iteration #4, type SB_GB: wirelen solved = 130, spread = 130, legal = 130; time = 0.00s
434s Info:     at iteration #4, type SB_WARMBOOT: wirelen solved = 72, spread = 72, legal = 130; time = 0.00s
434s Info:     at iteration #4, type ALL: wirelen solved = 20, spread = 54, legal = 117; time = 0.00s
434s Info:     at iteration #5, type ICESTORM_LC: wirelen solved = 87, spread = 124, legal = 134; time = 0.00s
434s Info:     at iteration #5, type SB_GB: wirelen solved = 134, spread = 134, legal = 134; time = 0.00s
434s Info:     at iteration #5, type SB_WARMBOOT: wirelen solved = 77, spread = 77, legal = 134; time = 0.00s
434s Info:     at iteration #5, type ALL: wirelen solved = 23, spread = 54, legal = 117; time = 0.00s
434s Info:     at iteration #6, type ICESTORM_LC: wirelen solved = 84, spread = 124, legal = 129; time = 0.00s
434s Info:     at iteration #6, type SB_GB: wirelen solved = 129, spread = 129, legal = 129; time = 0.00s
434s Info:     at iteration #6, type SB_WARMBOOT: wirelen solved = 72, spread = 72, legal = 129; time = 0.00s
434s Info:     at iteration #6, type ALL: wirelen solved = 23, spread = 54, legal = 117; time = 0.00s
434s Info:     at iteration #7, type ICESTORM_LC: wirelen solved = 84, spread = 124, legal = 134; time = 0.00s
434s Info:     at iteration #7, type SB_GB: wirelen solved = 134, spread = 134, legal = 134; time = 0.00s
434s Info:     at iteration #7, type SB_WARMBOOT: wirelen solved = 77, spread = 77, legal = 134; time = 0.00s
434s Info:     at iteration #7, type ALL: wirelen solved = 29, spread = 56, legal = 117; time = 0.00s
434s Info: HeAP Placer Time: 0.02s
434s Info:   of which solving equations: 0.01s
434s Info:   of which spreading cells: 0.00s
434s Info:   of which strict legalisation: 0.00s
434s 
434s Info: Running simulated annealing placer for refinement.
434s Info:   at iteration #1: temp = 0.000000, timing cost = 16, wirelen = 114
434s Info:   at iteration #5: temp = 0.000000, timing cost = 10, wirelen = 106
434s Info:   at iteration #7: temp = 0.000000, timing cost = 10, wirelen = 100 
434s Info: SA placement time 0.01s
434s 
434s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 173.52 MHz (PASS at 12.00 MHz)
434s 
434s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> <async>: 4.21 ns
434s 
434s Info: Slack histogram:
434s Info:  legend: * represents 1 endpoint(s)
434s Info:          + represents [1,1) endpoint(s)
434s Info: [ 77570,  77802) |** 
434s Info: [ 77802,  78034) |* 
434s Info: [ 78034,  78266) |* 
434s Info: [ 78266,  78498) |** 
434s Info: [ 78498,  78730) |** 
434s Info: [ 78730,  78962) |** 
434s Info: [ 78962,  79194) |* 
434s Info: [ 79194,  79426) |** 
434s Info: [ 79426,  79658) |** 
434s Info: [ 79658,  79890) |*** 
434s Info: [ 79890,  80122) |** 
434s Info: [ 80122,  80354) |* 
434s Info: [ 80354,  80586) | 
434s Info: [ 80586,  80818) |** 
434s Info: [ 80818,  81050) |** 
434s Info: [ 81050,  81282) |** 
434s Info: [ 81282,  81514) | 
434s Info: [ 81514,  81746) | 
434s Info: [ 81746,  81978) |**************************** 
434s Info: [ 81978,  82210) |* 
434s Info: Checksum: 0x25fd4746
434s 
434s Info: Routing..
434s Info: Setting up routing queue.
434s Info: Routing 124 arcs.
434s Info:            |   (re-)routed arcs  |   delta    | remaining|       time spent     |
434s Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|
434s Info:        124 |        0        104 |    0   104 |         0|       0.01       0.01|
434s Info: Routing complete.
434s Info: Router1 time 0.01s
434s Info: Checksum: 0x84c7f0d5
434s 
434s Info: Critical path report for clock 'clk$SB_IO_IN_$glb_clk' (posedge -> posedge):
434s Info: curr total
434s Info:  0.5  0.5  Source counter_SB_LUT4_I2_7_LC.O
434s Info:  0.6  1.1    Net counter[2] budget 20.291000 ns (11,9) -> (12,9)
434s Info:                Sink state_SB_LUT4_I3_I1_SB_LUT4_O_1_I3_SB_LUT4_O_LC.I0
434s Info:                Defined in:
434s Info:                  app1.v:7.22-7.29
434s Info:  0.4  1.6  Source state_SB_LUT4_I3_I1_SB_LUT4_O_1_I3_SB_LUT4_O_LC.O
434s Info:  0.6  2.2    Net state_SB_LUT4_I3_I1_SB_LUT4_O_1_I3[2] budget 20.291000 ns (12,9) -> (12,9)
434s Info:                Sink state_SB_LUT4_I3_I1_SB_LUT4_O_1_LC.I3
434s Info:                Defined in:
434s Info:                  /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
434s Info:  0.3  2.5  Source state_SB_LUT4_I3_I1_SB_LUT4_O_1_LC.O
434s Info:  1.0  3.4    Net state_SB_LUT4_I3_I1[0] budget 20.291000 ns (12,9) -> (12,12)
434s Info:                Sink counter2_SB_DFF_Q_D_SB_LUT4_O_3_I1_SB_LUT4_O_LC.I2
434s Info:                Defined in:
434s Info:                  /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
434s Info:  0.4  3.8  Source counter2_SB_DFF_Q_D_SB_LUT4_O_3_I1_SB_LUT4_O_LC.O
434s Info:  0.6  4.4    Net counter2_SB_DFF_Q_D_SB_LUT4_O_3_I1 budget 20.290001 ns (12,12) -> (12,12)
434s Info:                Sink counter2_SB_DFF_Q_D_SB_LUT4_O_3_LC.I1
434s Info:                Defined in:
434s Info:                  app1.v:13.15-13.34
434s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:29.22-29.23
434s Info:  0.3  4.7  Source counter2_SB_DFF_Q_D_SB_LUT4_O_3_LC.COUT
434s Info:  0.0  4.7    Net counter2_SB_DFF_Q_D_SB_LUT4_O_3_I1_SB_CARRY_I0_CO[1] budget 0.000000 ns (12,12) -> (12,12)
434s Info:                Sink counter2_SB_DFF_Q_D_SB_LUT4_O_2_LC.CIN
434s Info:                Defined in:
434s Info:                  app1.v:13.15-13.34
434s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
434s Info:  0.1  4.8  Source counter2_SB_DFF_Q_D_SB_LUT4_O_2_LC.COUT
434s Info:  0.0  4.8    Net counter2_SB_DFF_Q_D_SB_LUT4_O_3_I1_SB_CARRY_I0_CO[2] budget 0.000000 ns (12,12) -> (12,12)
434s Info:                Sink counter2_SB_DFF_Q_D_SB_LUT4_O_1_LC.CIN
434s icetime -d hx1k -c 25 app1.asc
434s // Reading input .asc file..
434s // Reading 1k chipdb file..
434s Info:                Defined in:
434s Info:                  app1.v:13.15-13.34
434s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
434s Info:  0.1  4.9  Source counter2_SB_DFF_Q_D_SB_LUT4_O_1_LC.COUT
434s Info:  0.3  5.2    Net counter2_SB_DFF_Q_D_SB_LUT4_O_3_I1_SB_CARRY_I0_CO[3] budget 0.260000 ns (12,12) -> (12,12)
434s Info:                Sink counter2_SB_DFF_Q_D_SB_LUT4_O_LC.I3
434s Info:                Defined in:
434s Info:                  app1.v:13.15-13.34
434s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
434s Info:  0.3  5.5  Setup counter2_SB_DFF_Q_D_SB_LUT4_O_LC.I3
434s Info: 2.5 ns logic, 3.0 ns routing
434s 
434s Info: Critical path report for cross-domain path 'posedge clk$SB_IO_IN_$glb_clk' -> '<async>':
434s Info: curr total
434s Info:  0.5  0.5  Source counter2_SB_DFF_Q_D_SB_LUT4_O_3_LC.O
434s Info:  0.6  1.1    Net counter2[0] budget 41.173000 ns (12,12) -> (12,12)
434s Info:                Sink WB_BOOT_SB_LUT4_O_LC.I0
434s Info:                Defined in:
434s Info:                  app1.v:8.12-8.20
434s Info:  0.4  1.6  Source WB_BOOT_SB_LUT4_O_LC.O
434s Info:  1.4  3.0    Net WB_BOOT budget 41.172001 ns (12,12) -> (0,0)
434s Info:                Sink WB.BOOT
434s Info:                Defined in:
434s Info:                  app1.v:24.9-24.18
434s Info: 1.0 ns logic, 2.0 ns routing
434s 
434s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 181.49 MHz (PASS at 12.00 MHz)
434s 
434s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> <async>: 3.02 ns
434s 
434s Info: Slack histogram:
434s Info:  legend: * represents 1 endpoint(s)
434s Info:          + represents [1,1) endpoint(s)
434s Info: [ 77823,  78043) |** 
434s Info: [ 78043,  78263) |* 
434s Info: [ 78263,  78483) |* 
434s Info: [ 78483,  78703) |*** 
434s Info: [ 78703,  78923) |* 
434s Info: [ 78923,  79143) |** 
434s Info: [ 79143,  79363) | 
434s Info: [ 79363,  79583) |*** 
434s Info: [ 79583,  79803) |*** 
434s Info: [ 79803,  80023) |** 
434s Info: [ 80023,  80243) |** 
434s Info: [ 80243,  80463) |* 
434s Info: [ 80463,  80683) |* 
434s Info: [ 80683,  80903) |** 
434s Info: [ 80903,  81123) |** 
434s Info: [ 81123,  81343) |* 
434s Info: [ 81343,  81563) | 
434s Info: [ 81563,  81783) | 
434s Info: [ 81783,  82003) |**************************** 
434s Info: [ 82003,  82223) |* 
434s 2 warnings, 0 errors
434s 
434s Info: Program finished normally.
434s // Creating timing netlist..
434s // Timing estimate: 5.57 ns (179.52 MHz)
434s // Checking 40.00 ns (25.00 MHz) clock constraint: PASSED.
434s icepack app1.asc app1.bin
434s yosys -p "synth_ice40 -top top -json app2.json" app2.v
434s 
434s  /----------------------------------------------------------------------------\
434s  |                                                                            |
434s  |  yosys -- Yosys Open SYnthesis Suite                                       |
434s  |                                                                            |
434s  |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
434s  |                                                                            |
434s  |  Permission to use, copy, modify, and/or distribute this software for any  |
434s  |  purpose with or without fee is hereby granted, provided that the above    |
434s  |  copyright notice and this permission notice appear in all copies.         |
434s  |                                                                            |
434s  |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
434s  |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
434s  |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
434s  |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
434s  |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
434s  |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
434s  |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
434s  |                                                                            |
434s  \----------------------------------------------------------------------------/
434s 
434s  Yosys 0.33 (git sha1 2584903a060)
434s 
434s 
434s -- Parsing `app2.v' using frontend ` -vlog2k' --
434s 
434s 1. Executing Verilog-2005 frontend: app2.v
434s Parsing Verilog input from `app2.v' to AST representation.
434s Storing AST representation for module `$abstract\top'.
434s Successfully finished Verilog frontend.
434s 
434s -- Running command `synth_ice40 -top top -json app2.json' --
434s 
434s 2. Executing SYNTH_ICE40 pass.
434s 
434s 2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v
434s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation.
434s Generating RTLIL representation for module `\SB_IO'.
434s Generating RTLIL representation for module `\SB_GB_IO'.
434s Generating RTLIL representation for module `\SB_GB'.
434s Generating RTLIL representation for module `\SB_LUT4'.
434s Generating RTLIL representation for module `\SB_CARRY'.
434s Generating RTLIL representation for module `\SB_DFF'.
434s Generating RTLIL representation for module `\SB_DFFE'.
434s Generating RTLIL representation for module `\SB_DFFSR'.
434s Generating RTLIL representation for module `\SB_DFFR'.
434s Generating RTLIL representation for module `\SB_DFFSS'.
434s Generating RTLIL representation for module `\SB_DFFS'.
434s Generating RTLIL representation for module `\SB_DFFESR'.
434s Generating RTLIL representation for module `\SB_DFFER'.
434s Generating RTLIL representation for module `\SB_DFFESS'.
434s Generating RTLIL representation for module `\SB_DFFES'.
434s Generating RTLIL representation for module `\SB_DFFN'.
434s Generating RTLIL representation for module `\SB_DFFNE'.
434s Generating RTLIL representation for module `\SB_DFFNSR'.
434s Generating RTLIL representation for module `\SB_DFFNR'.
434s Generating RTLIL representation for module `\SB_DFFNSS'.
434s Generating RTLIL representation for module `\SB_DFFNS'.
434s Generating RTLIL representation for module `\SB_DFFNESR'.
434s Generating RTLIL representation for module `\SB_DFFNER'.
434s Generating RTLIL representation for module `\SB_DFFNESS'.
434s Generating RTLIL representation for module `\SB_DFFNES'.
434s Generating RTLIL representation for module `\SB_RAM40_4K'.
434s Generating RTLIL representation for module `\SB_RAM40_4KNR'.
434s Generating RTLIL representation for module `\SB_RAM40_4KNW'.
434s Generating RTLIL representation for module `\SB_RAM40_4KNRNW'.
434s Generating RTLIL representation for module `\ICESTORM_LC'.
434s Generating RTLIL representation for module `\SB_PLL40_CORE'.
434s Generating RTLIL representation for module `\SB_PLL40_PAD'.
434s Generating RTLIL representation for module `\SB_PLL40_2_PAD'.
434s Generating RTLIL representation for module `\SB_PLL40_2F_CORE'.
434s Generating RTLIL representation for module `\SB_PLL40_2F_PAD'.
434s Generating RTLIL representation for module `\SB_WARMBOOT'.
434s Generating RTLIL representation for module `\SB_SPRAM256KA'.
434s Generating RTLIL representation for module `\SB_HFOSC'.
434s Generating RTLIL representation for module `\SB_LFOSC'.
434s Generating RTLIL representation for module `\SB_RGBA_DRV'.
434s Generating RTLIL representation for module `\SB_LED_DRV_CUR'.
434s Generating RTLIL representation for module `\SB_RGB_DRV'.
434s Generating RTLIL representation for module `\SB_I2C'.
434s Generating RTLIL representation for module `\SB_SPI'.
434s Generating RTLIL representation for module `\SB_LEDDA_IP'.
434s Generating RTLIL representation for module `\SB_FILTER_50NS'.
434s Generating RTLIL representation for module `\SB_IO_I3C'.
434s Generating RTLIL representation for module `\SB_IO_OD'.
434s Generating RTLIL representation for module `\SB_MAC16'.
434s Generating RTLIL representation for module `\ICESTORM_RAM'.
434s Successfully finished Verilog frontend.
434s 
434s 2.2. Executing HIERARCHY pass (managing design hierarchy).
434s 
434s 2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\top'.
434s Generating RTLIL representation for module `\top'.
434s 
434s 2.3.1. Analyzing design hierarchy..
434s Top module:  \top
434s 
434s 2.3.2. Analyzing design hierarchy..
434s Top module:  \top
434s Removing unused module `$abstract\top'.
434s Removed 1 unused modules.
434s 
434s 2.4. Executing PROC pass (convert processes to netlists).
434s 
434s 2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
434s Cleaned up 0 empty switches.
434s 
434s 2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
434s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241 in module SB_DFFNES.
434s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234 in module SB_DFFNESS.
434s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230 in module SB_DFFNER.
434s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223 in module SB_DFFNESR.
434s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220 in module SB_DFFNS.
434s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217 in module SB_DFFNSS.
434s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214 in module SB_DFFNR.
434s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211 in module SB_DFFNSR.
434s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203 in module SB_DFFES.
434s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196 in module SB_DFFESS.
434s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192 in module SB_DFFER.
434s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185 in module SB_DFFESR.
434s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182 in module SB_DFFS.
434s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179 in module SB_DFFSS.
434s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176 in module SB_DFFR.
434s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173 in module SB_DFFSR.
434s Removed a total of 0 dead cases.
434s 
434s 2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
434s Removed 8 redundant assignments.
434s Promoted 28 assignments to connections.
434s 
434s 2.4.4. Executing PROC_INIT pass (extract init attributes).
434s Found init rule in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'.
434s   Set init value: \Q = 1'0
434s Found init rule in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'.
434s   Set init value: \Q = 1'0
434s Found init rule in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'.
434s   Set init value: \Q = 1'0
434s Found init rule in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'.
434s   Set init value: \Q = 1'0
434s Found init rule in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'.
434s   Set init value: \Q = 1'0
434s Found init rule in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'.
434s   Set init value: \Q = 1'0
434s Found init rule in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'.
434s   Set init value: \Q = 1'0
434s Found init rule in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'.
434s   Set init value: \Q = 1'0
434s Found init rule in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'.
434s   Set init value: \Q = 1'0
434s Found init rule in `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'.
434s   Set init value: \Q = 1'0
434s Found init rule in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'.
434s   Set init value: \Q = 1'0
434s Found init rule in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'.
434s   Set init value: \Q = 1'0
434s Found init rule in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'.
434s   Set init value: \Q = 1'0
434s Found init rule in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'.
434s   Set init value: \Q = 1'0
434s Found init rule in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'.
434s   Set init value: \Q = 1'0
434s Found init rule in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'.
434s   Set init value: \Q = 1'0
434s Found init rule in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'.
434s   Set init value: \Q = 1'0
434s Found init rule in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'.
434s   Set init value: \Q = 1'0
434s Found init rule in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'.
434s   Set init value: \Q = 1'0
434s Found init rule in `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'.
434s   Set init value: \Q = 1'0
434s Found init rule in `\top.$proc$app2.v:9$390'.
434s   Set init value: \state = 1'0
434s Found init rule in `\top.$proc$app2.v:8$389'.
434s   Set init value: \counter2 = 4'0000
434s Found init rule in `\top.$proc$app2.v:7$388'.
434s   Set init value: \counter = 22'0000000000000000000000
434s 
434s 2.4.5. Executing PROC_ARST pass (detect async resets in processes).
434s Found async reset \S in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
434s Found async reset \R in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
434s Found async reset \S in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
434s Found async reset \R in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
434s Found async reset \S in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
434s Found async reset \R in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
434s Found async reset \S in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'.
434s Found async reset \R in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'.
434s 
434s 2.4.6. Executing PROC_ROM pass (convert switches to ROMs).
434s Converted 0 switches.
434s <suppressed ~18 debug messages>
434s 
434s 2.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
434s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'.
434s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
434s      1/1: $0\Q[0:0]
434s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'.
434s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
434s      1/1: $0\Q[0:0]
434s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'.
434s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
434s      1/1: $0\Q[0:0]
434s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'.
434s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
434s      1/1: $0\Q[0:0]
434s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'.
434s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
434s      1/1: $0\Q[0:0]
434s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'.
434s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
434s      1/1: $0\Q[0:0]
434s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'.
434s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
434s      1/1: $0\Q[0:0]
434s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'.
434s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'.
434s      1/1: $0\Q[0:0]
434s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'.
434s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'.
434s      1/1: $0\Q[0:0]
434s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'.
434s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'.
434s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'.
434s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
434s      1/1: $0\Q[0:0]
434s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'.
434s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'.
434s      1/1: $0\Q[0:0]
434s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'.
434s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
434s      1/1: $0\Q[0:0]
434s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'.
434s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'.
434s      1/1: $0\Q[0:0]
434s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'.
434s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'.
434s      1/1: $0\Q[0:0]
434s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'.
434s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'.
434s      1/1: $0\Q[0:0]
434s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'.
434s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'.
434s      1/1: $0\Q[0:0]
434s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'.
434s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'.
434s      1/1: $0\Q[0:0]
434s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'.
434s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'.
434s      1/1: $0\Q[0:0]
434s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'.
434s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'.
434s Creating decoders for process `\top.$proc$app2.v:9$390'.
434s Creating decoders for process `\top.$proc$app2.v:8$389'.
434s Creating decoders for process `\top.$proc$app2.v:7$388'.
434s Creating decoders for process `\top.$proc$app2.v:11$381'.
434s 
434s 2.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
434s 
434s 2.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
434s Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
434s   created $adff cell `$procdff$435' with negative edge clock and positive level reset.
434s Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
434s   created $dff cell `$procdff$436' with negative edge clock.
434s Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
434s   created $adff cell `$procdff$437' with negative edge clock and positive level reset.
434s Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
434s   created $dff cell `$procdff$438' with negative edge clock.
434s Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
434s   created $adff cell `$procdff$439' with negative edge clock and positive level reset.
434s Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
434s   created $dff cell `$procdff$440' with negative edge clock.
434s Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
434s   created $adff cell `$procdff$441' with negative edge clock and positive level reset.
434s Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'.
434s   created $dff cell `$procdff$442' with negative edge clock.
434s Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'.
434s   created $dff cell `$procdff$443' with negative edge clock.
434s Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'.
434s   created $dff cell `$procdff$444' with negative edge clock.
434s Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
434s   created $adff cell `$procdff$445' with positive edge clock and positive level reset.
434s Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'.
434s   created $dff cell `$procdff$446' with positive edge clock.
434s Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
434s   created $adff cell `$procdff$447' with positive edge clock and positive level reset.
434s Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'.
434s   created $dff cell `$procdff$448' with positive edge clock.
434s Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'.
434s   created $adff cell `$procdff$449' with positive edge clock and positive level reset.
434s Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'.
434s   created $dff cell `$procdff$450' with positive edge clock.
434s Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'.
434s   created $adff cell `$procdff$451' with positive edge clock and positive level reset.
434s Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'.
434s   created $dff cell `$procdff$452' with positive edge clock.
434s Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'.
434s   created $dff cell `$procdff$453' with positive edge clock.
434s Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'.
434s   created $dff cell `$procdff$454' with positive edge clock.
434s Creating register for signal `\top.\counter' using process `\top.$proc$app2.v:11$381'.
434s   created $dff cell `$procdff$455' with positive edge clock.
434s Creating register for signal `\top.\counter2' using process `\top.$proc$app2.v:11$381'.
434s   created $dff cell `$procdff$456' with positive edge clock.
434s Creating register for signal `\top.\state' using process `\top.$proc$app2.v:11$381'.
434s   created $dff cell `$procdff$457' with positive edge clock.
434s 
434s 2.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
434s 
434s 2.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
434s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'.
434s Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
434s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
434s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'.
434s Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
434s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
434s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'.
434s Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
434s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
434s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'.
434s Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
434s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
434s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'.
434s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
434s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'.
434s Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
434s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
434s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'.
434s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
434s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'.
434s Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'.
434s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'.
434s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'.
434s Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'.
434s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'.
434s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'.
434s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'.
434s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'.
434s Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
434s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
434s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'.
434s Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'.
434s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'.
434s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'.
434s Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
434s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
434s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'.
434s Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'.
434s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'.
434s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'.
434s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'.
434s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'.
434s Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'.
434s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'.
434s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'.
434s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'.
434s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'.
434s Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'.
434s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'.
434s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'.
434s Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'.
434s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'.
434s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'.
434s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'.
434s Removing empty process `top.$proc$app2.v:9$390'.
434s Removing empty process `top.$proc$app2.v:8$389'.
434s Removing empty process `top.$proc$app2.v:7$388'.
434s Removing empty process `top.$proc$app2.v:11$381'.
434s Cleaned up 18 empty switches.
434s 
434s 2.4.12. Executing OPT_EXPR pass (perform const folding).
434s Optimizing module top.
434s 
434s 2.5. Executing FLATTEN pass (flatten design).
434s 
434s 2.6. Executing TRIBUF pass.
434s 
434s 2.7. Executing DEMINOUT pass (demote inout ports to input or output).
434s 
434s 2.8. Executing OPT_EXPR pass (perform const folding).
434s Optimizing module top.
434s 
434s 2.9. Executing OPT_CLEAN pass (remove unused cells and wires).
434s Finding unused cells or wires in module \top..
434s Removed 0 unused cells and 5 unused wires.
434s <suppressed ~1 debug messages>
434s 
434s 2.10. Executing CHECK pass (checking for obvious problems).
434s Checking module top...
434s Found and reported 0 problems.
434s 
434s 2.11. Executing OPT pass (performing simple optimizations).
434s 
434s 2.11.1. Executing OPT_EXPR pass (perform const folding).
434s Optimizing module top.
434s 
434s 2.11.2. Executing OPT_MERGE pass (detect identical cells).
434s Finding identical cells in module `\top'.
434s Removed a total of 0 cells.
434s 
434s 2.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
434s Running muxtree optimizer on module \top..
434s   Creating internal representation of mux trees.
434s   No muxes found in this module.
434s Removed 0 multiplexer ports.
434s 
434s 2.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
434s   Optimizing cells in module \top.
434s Performed a total of 0 changes.
434s 
434s 2.11.5. Executing OPT_MERGE pass (detect identical cells).
434s Finding identical cells in module `\top'.
434s Removed a total of 0 cells.
434s 
434s 2.11.6. Executing OPT_DFF pass (perform DFF optimizations).
434s 
434s 2.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
434s Finding unused cells or wires in module \top..
434s 
434s 2.11.8. Executing OPT_EXPR pass (perform const folding).
434s Optimizing module top.
434s 
434s 2.11.9. Finished OPT passes. (There is nothing left to do.)
434s 
434s 2.12. Executing FSM pass (extract and optimize FSM).
434s 
434s 2.12.1. Executing FSM_DETECT pass (finding FSMs in design).
434s 
434s 2.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).
434s 
434s 2.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).
434s 
434s 2.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
434s Finding unused cells or wires in module \top..
434s 
434s 2.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).
434s 
434s 2.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
434s 
434s 2.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
434s 
434s 2.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
434s 
434s 2.13. Executing OPT pass (performing simple optimizations).
434s 
434s 2.13.1. Executing OPT_EXPR pass (perform const folding).
434s Optimizing module top.
434s 
434s 2.13.2. Executing OPT_MERGE pass (detect identical cells).
434s Finding identical cells in module `\top'.
434s Removed a total of 0 cells.
434s 
434s 2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
434s Running muxtree optimizer on module \top..
434s   Creating internal representation of mux trees.
434s   No muxes found in this module.
434s Removed 0 multiplexer ports.
434s 
434s 2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
434s   Optimizing cells in module \top.
434s Performed a total of 0 changes.
434s 
434s 2.13.5. Executing OPT_MERGE pass (detect identical cells).
434s Finding identical cells in module `\top'.
434s Removed a total of 0 cells.
434s 
434s 2.13.6. Executing OPT_DFF pass (perform DFF optimizations).
434s 
434s 2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
434s Finding unused cells or wires in module \top..
434s 
434s 2.13.8. Executing OPT_EXPR pass (perform const folding).
434s Optimizing module top.
434s 
434s 2.13.9. Finished OPT passes. (There is nothing left to do.)
434s 
434s 2.14. Executing WREDUCE pass (reducing word size of cells).
434s Removed top 31 bits (of 32) from port B of cell top.$add$app2.v:12$382 ($add).
434s Removed top 10 bits (of 32) from port Y of cell top.$add$app2.v:12$382 ($add).
434s Removed top 3 bits (of 4) from port B of cell top.$add$app2.v:13$384 ($add).
434s Removed top 3 bits (of 4) from wire top.$logic_not$app2.v:13$383_Y.
434s 
434s 2.15. Executing PEEPOPT pass (run peephole optimizers).
434s 
434s 2.16. Executing OPT_CLEAN pass (remove unused cells and wires).
434s Finding unused cells or wires in module \top..
434s Removed 0 unused cells and 2 unused wires.
434s <suppressed ~1 debug messages>
434s 
434s 2.17. Executing SHARE pass (SAT-based resource sharing).
434s 
434s 2.18. Executing TECHMAP pass (map to technology primitives).
434s 
434s 2.18.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v
434s Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation.
434s Generating RTLIL representation for module `\_90_lut_cmp_'.
434s Successfully finished Verilog frontend.
434s 
434s 2.18.2. Continuing TECHMAP pass.
434s No more expansions possible.
434s <suppressed ~6 debug messages>
434s 
434s 2.19. Executing OPT_EXPR pass (perform const folding).
434s Optimizing module top.
434s 
434s 2.20. Executing OPT_CLEAN pass (remove unused cells and wires).
434s Finding unused cells or wires in module \top..
434s 
434s 2.21. Executing ALUMACC pass (create $alu and $macc cells).
434s Extracting $alu and $macc cells in module top:
434s   creating $macc model for $add$app2.v:12$382 ($add).
434s   creating $macc model for $add$app2.v:13$384 ($add).
434s   creating $alu model for $macc $add$app2.v:13$384.
434s   creating $alu model for $macc $add$app2.v:12$382.
434s   creating $alu cell for $add$app2.v:12$382: $auto$alumacc.cc:485:replace_alu$460
434s   creating $alu cell for $add$app2.v:13$384: $auto$alumacc.cc:485:replace_alu$463
434s   created 2 $alu and 0 $macc cells.
434s 
434s 2.22. Executing OPT pass (performing simple optimizations).
434s 
434s 2.22.1. Executing OPT_EXPR pass (perform const folding).
434s Optimizing module top.
434s 
434s 2.22.2. Executing OPT_MERGE pass (detect identical cells).
434s Finding identical cells in module `\top'.
434s <suppressed ~3 debug messages>
434s Removed a total of 1 cells.
434s 
434s 2.22.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
434s Running muxtree optimizer on module \top..
434s   Creating internal representation of mux trees.
434s   No muxes found in this module.
434s Removed 0 multiplexer ports.
434s 
434s 2.22.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
434s   Optimizing cells in module \top.
434s Performed a total of 0 changes.
434s 
434s 2.22.5. Executing OPT_MERGE pass (detect identical cells).
434s Finding identical cells in module `\top'.
434s Removed a total of 0 cells.
434s 
434s 2.22.6. Executing OPT_DFF pass (perform DFF optimizations).
434s 
434s 2.22.7. Executing OPT_CLEAN pass (remove unused cells and wires).
434s Finding unused cells or wires in module \top..
434s Removed 0 unused cells and 1 unused wires.
434s <suppressed ~1 debug messages>
434s 
434s 2.22.8. Executing OPT_EXPR pass (perform const folding).
434s Optimizing module top.
434s 
434s 2.22.9. Rerunning OPT passes. (Maybe there is more to do..)
434s 
434s 2.22.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
434s Running muxtree optimizer on module \top..
434s   Creating internal representation of mux trees.
434s   No muxes found in this module.
434s Removed 0 multiplexer ports.
434s 
434s 2.22.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
434s   Optimizing cells in module \top.
434s Performed a total of 0 changes.
434s 
434s 2.22.12. Executing OPT_MERGE pass (detect identical cells).
434s Finding identical cells in module `\top'.
434s Removed a total of 0 cells.
434s 
434s 2.22.13. Executing OPT_DFF pass (perform DFF optimizations).
434s 
434s 2.22.14. Executing OPT_CLEAN pass (remove unused cells and wires).
434s Finding unused cells or wires in module \top..
434s 
434s 2.22.15. Executing OPT_EXPR pass (perform const folding).
434s Optimizing module top.
434s 
434s 2.22.16. Finished OPT passes. (There is nothing left to do.)
434s 
434s 2.23. Executing MEMORY pass.
434s 
434s 2.23.1. Executing OPT_MEM pass (optimize memories).
434s Performed a total of 0 transformations.
434s 
434s 2.23.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
434s Performed a total of 0 transformations.
434s 
434s 2.23.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
434s 
434s 2.23.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
434s 
434s 2.23.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
434s 
434s 2.23.6. Executing OPT_CLEAN pass (remove unused cells and wires).
434s Finding unused cells or wires in module \top..
434s 
434s 2.23.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
434s 
434s 2.23.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
434s Performed a total of 0 transformations.
434s 
434s 2.23.9. Executing OPT_CLEAN pass (remove unused cells and wires).
434s Finding unused cells or wires in module \top..
434s 
434s 2.23.10. Executing MEMORY_COLLECT pass (generating $mem cells).
434s 
434s 2.24. Executing OPT_CLEAN pass (remove unused cells and wires).
434s Finding unused cells or wires in module \top..
434s 
434s 2.25. Executing MEMORY_LIBMAP pass (mapping memories to cells).
434s 
434s 2.26. Executing TECHMAP pass (map to technology primitives).
434s 
434s 2.26.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v
435s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation.
435s Generating RTLIL representation for module `\$__ICE40_RAM4K_'.
435s Successfully finished Verilog frontend.
435s 
435s 2.26.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/spram_map.v
435s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/spram_map.v' to AST representation.
435s Generating RTLIL representation for module `\$__ICE40_SPRAM_'.
435s Successfully finished Verilog frontend.
435s 
435s 2.26.3. Continuing TECHMAP pass.
435s No more expansions possible.
435s <suppressed ~4 debug messages>
435s 
435s 2.27. Executing ICE40_BRAMINIT pass.
435s 
435s 2.28. Executing OPT pass (performing simple optimizations).
435s 
435s 2.28.1. Executing OPT_EXPR pass (perform const folding).
435s Optimizing module top.
435s 
435s 2.28.2. Executing OPT_MERGE pass (detect identical cells).
435s Finding identical cells in module `\top'.
435s Removed a total of 0 cells.
435s 
435s 2.28.3. Executing OPT_DFF pass (perform DFF optimizations).
435s 
435s 2.28.4. Executing OPT_CLEAN pass (remove unused cells and wires).
435s Finding unused cells or wires in module \top..
435s 
435s 2.28.5. Finished fast OPT passes.
435s 
435s 2.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
435s 
435s 2.30. Executing OPT pass (performing simple optimizations).
435s 
435s 2.30.1. Executing OPT_EXPR pass (perform const folding).
435s Optimizing module top.
435s 
435s 2.30.2. Executing OPT_MERGE pass (detect identical cells).
435s Finding identical cells in module `\top'.
435s Removed a total of 0 cells.
435s 
435s 2.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
435s Running muxtree optimizer on module \top..
435s   Creating internal representation of mux trees.
435s   No muxes found in this module.
435s Removed 0 multiplexer ports.
435s 
435s 2.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
435s   Optimizing cells in module \top.
435s Performed a total of 0 changes.
435s 
435s 2.30.5. Executing OPT_MERGE pass (detect identical cells).
435s Finding identical cells in module `\top'.
435s Removed a total of 0 cells.
435s 
435s 2.30.6. Executing OPT_DFF pass (perform DFF optimizations).
435s 
435s 2.30.7. Executing OPT_CLEAN pass (remove unused cells and wires).
435s Finding unused cells or wires in module \top..
435s 
435s 2.30.8. Executing OPT_EXPR pass (perform const folding).
435s Optimizing module top.
435s 
435s 2.30.9. Finished OPT passes. (There is nothing left to do.)
435s 
435s 2.31. Executing ICE40_WRAPCARRY pass (wrap carries).
435s 
435s 2.32. Executing TECHMAP pass (map to technology primitives).
435s 
435s 2.32.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v
435s Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation.
435s Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
435s Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
435s Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
435s Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
435s Generating RTLIL representation for module `\_90_simplemap_various'.
435s Generating RTLIL representation for module `\_90_simplemap_registers'.
435s Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
435s Generating RTLIL representation for module `\_90_shift_shiftx'.
435s Generating RTLIL representation for module `\_90_fa'.
435s Generating RTLIL representation for module `\_90_lcu'.
435s Generating RTLIL representation for module `\_90_alu'.
435s Generating RTLIL representation for module `\_90_macc'.
435s Generating RTLIL representation for module `\_90_alumacc'.
435s Generating RTLIL representation for module `\$__div_mod_u'.
435s Generating RTLIL representation for module `\$__div_mod_trunc'.
435s Generating RTLIL representation for module `\_90_div'.
435s Generating RTLIL representation for module `\_90_mod'.
435s Generating RTLIL representation for module `\$__div_mod_floor'.
435s Generating RTLIL representation for module `\_90_divfloor'.
435s Generating RTLIL representation for module `\_90_modfloor'.
435s Generating RTLIL representation for module `\_90_pow'.
435s Generating RTLIL representation for module `\_90_pmux'.
435s Generating RTLIL representation for module `\_90_demux'.
435s Generating RTLIL representation for module `\_90_lut'.
435s Successfully finished Verilog frontend.
435s 
435s 2.32.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v
435s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation.
435s Generating RTLIL representation for module `\_80_ice40_alu'.
435s Successfully finished Verilog frontend.
435s 
435s 2.32.3. Continuing TECHMAP pass.
435s Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_80_ice40_alu for cells of type $alu.
435s Using extmapper simplemap for cells of type $logic_not.
435s Using template $paramod$080e6a70eb8bfa1ccf22d9718e795074645029a4\_80_ice40_alu for cells of type $alu.
435s Using extmapper simplemap for cells of type $xor.
435s Using extmapper simplemap for cells of type $reduce_and.
435s Using extmapper simplemap for cells of type $dff.
435s Using extmapper simplemap for cells of type $mux.
435s Using extmapper simplemap for cells of type $not.
435s Using extmapper simplemap for cells of type $pos.
435s No more expansions possible.
435s <suppressed ~129 debug messages>
435s 
435s 2.33. Executing OPT pass (performing simple optimizations).
435s 
435s 2.33.1. Executing OPT_EXPR pass (perform const folding).
435s Optimizing module top.
435s <suppressed ~51 debug messages>
435s 
435s 2.33.2. Executing OPT_MERGE pass (detect identical cells).
435s Finding identical cells in module `\top'.
435s <suppressed ~3 debug messages>
435s Removed a total of 1 cells.
435s 
435s 2.33.3. Executing OPT_DFF pass (perform DFF optimizations).
435s 
435s 2.33.4. Executing OPT_CLEAN pass (remove unused cells and wires).
435s Finding unused cells or wires in module \top..
435s Removed 27 unused cells and 34 unused wires.
435s <suppressed ~28 debug messages>
435s 
435s 2.33.5. Finished fast OPT passes.
435s 
435s 2.34. Executing ICE40_OPT pass (performing simple optimizations).
435s 
435s 2.34.1. Running ICE40 specific optimizations.
435s Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$460.slice[0].carry: CO=\counter [0]
435s 
435s 2.34.2. Executing OPT_EXPR pass (perform const folding).
435s Optimizing module top.
435s 
435s 2.34.3. Executing OPT_MERGE pass (detect identical cells).
435s Finding identical cells in module `\top'.
435s Removed a total of 0 cells.
435s 
435s 2.34.4. Executing OPT_DFF pass (perform DFF optimizations).
435s 
435s 2.34.5. Executing OPT_CLEAN pass (remove unused cells and wires).
435s Finding unused cells or wires in module \top..
435s 
435s 2.34.6. Rerunning OPT passes. (Removed registers in this run.)
435s 
435s 2.34.7. Running ICE40 specific optimizations.
435s 
435s 2.34.8. Executing OPT_EXPR pass (perform const folding).
435s Optimizing module top.
435s 
435s 2.34.9. Executing OPT_MERGE pass (detect identical cells).
435s Finding identical cells in module `\top'.
435s Removed a total of 0 cells.
435s 
435s 2.34.10. Executing OPT_DFF pass (perform DFF optimizations).
435s 
435s 2.34.11. Executing OPT_CLEAN pass (remove unused cells and wires).
435s Finding unused cells or wires in module \top..
435s 
435s 2.34.12. Finished OPT passes. (There is nothing left to do.)
435s 
435s 2.35. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
435s 
435s 2.36. Executing TECHMAP pass (map to technology primitives).
435s 
435s 2.36.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v
435s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation.
435s Generating RTLIL representation for module `\$_DFF_N_'.
435s Generating RTLIL representation for module `\$_DFF_P_'.
435s Generating RTLIL representation for module `\$_DFFE_NP_'.
435s Generating RTLIL representation for module `\$_DFFE_PP_'.
435s Generating RTLIL representation for module `\$_DFF_NP0_'.
435s Generating RTLIL representation for module `\$_DFF_NP1_'.
435s Generating RTLIL representation for module `\$_DFF_PP0_'.
435s Generating RTLIL representation for module `\$_DFF_PP1_'.
435s Generating RTLIL representation for module `\$_DFFE_NP0P_'.
435s Generating RTLIL representation for module `\$_DFFE_NP1P_'.
435s Generating RTLIL representation for module `\$_DFFE_PP0P_'.
435s Generating RTLIL representation for module `\$_DFFE_PP1P_'.
435s Generating RTLIL representation for module `\$_SDFF_NP0_'.
435s Generating RTLIL representation for module `\$_SDFF_NP1_'.
435s Generating RTLIL representation for module `\$_SDFF_PP0_'.
435s Generating RTLIL representation for module `\$_SDFF_PP1_'.
435s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
435s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
435s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
435s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
435s Successfully finished Verilog frontend.
435s 
435s 2.36.2. Continuing TECHMAP pass.
435s Using template \$_DFF_P_ for cells of type $_DFF_P_.
435s No more expansions possible.
435s <suppressed ~49 debug messages>
435s 
435s 2.37. Executing OPT_EXPR pass (perform const folding).
435s Optimizing module top.
435s 
435s 2.38. Executing SIMPLEMAP pass (map simple cells to gate primitives).
435s Mapping top.$auto$alumacc.cc:485:replace_alu$460.slice[0].carry ($lut).
435s 
435s 2.39. Executing ICE40_OPT pass (performing simple optimizations).
435s 
435s 2.39.1. Running ICE40 specific optimizations.
435s 
435s 2.39.2. Executing OPT_EXPR pass (perform const folding).
435s Optimizing module top.
435s <suppressed ~14 debug messages>
435s 
435s 2.39.3. Executing OPT_MERGE pass (detect identical cells).
435s Finding identical cells in module `\top'.
435s Removed a total of 0 cells.
435s 
435s 2.39.4. Executing OPT_DFF pass (perform DFF optimizations).
435s 
435s 2.39.5. Executing OPT_CLEAN pass (remove unused cells and wires).
435s Finding unused cells or wires in module \top..
435s Removed 0 unused cells and 112 unused wires.
435s <suppressed ~1 debug messages>
435s 
435s 2.39.6. Rerunning OPT passes. (Removed registers in this run.)
435s 
435s 2.39.7. Running ICE40 specific optimizations.
435s 
435s 2.39.8. Executing OPT_EXPR pass (perform const folding).
435s Optimizing module top.
435s 
435s 2.39.9. Executing OPT_MERGE pass (detect identical cells).
435s Finding identical cells in module `\top'.
435s Removed a total of 0 cells.
435s 
435s 2.39.10. Executing OPT_DFF pass (perform DFF optimizations).
435s 
435s 2.39.11. Executing OPT_CLEAN pass (remove unused cells and wires).
435s Finding unused cells or wires in module \top..
435s 
435s 2.39.12. Finished OPT passes. (There is nothing left to do.)
435s 
435s 2.40. Executing TECHMAP pass (map to technology primitives).
435s 
435s 2.40.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v
435s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation.
435s Generating RTLIL representation for module `\$_DLATCH_N_'.
435s Generating RTLIL representation for module `\$_DLATCH_P_'.
435s Successfully finished Verilog frontend.
435s 
435s 2.40.2. Continuing TECHMAP pass.
435s No more expansions possible.
435s <suppressed ~4 debug messages>
435s 
435s 2.41. Executing ABC pass (technology mapping using ABC).
435s 
435s 2.41.1. Extracting gate netlist of module `\top' to `<abc-temp-dir>/input.blif'..
435s Extracted 27 gates and 54 wires to a netlist network with 27 inputs and 4 outputs.
435s 
435s 2.41.1.1. Executing ABC.
435s Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
435s ABC: ABC command line: "source <abc-temp-dir>/abc.script".
435s ABC: 
435s ABC: + read_blif <abc-temp-dir>/input.blif 
435s ABC: + read_lut <abc-temp-dir>/lutdefs.txt 
435s ABC: + strash 
435s ABC: + &get -n 
435s ABC: + &fraig -x 
435s ABC: + &put 
435s ABC: + scorr 
435s ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
435s ABC: + dc2 
435s ABC: + dretime 
435s ABC: + strash 
435s ABC: + dch -f 
435s ABC: + if 
435s ABC: + mfs2 
435s ABC: + lutpack -S 1 
435s ABC: + dress <abc-temp-dir>/input.blif 
435s ABC: Total number of equiv classes                =       5.
435s ABC: Participating nodes from both networks       =       9.
435s ABC: Participating nodes from the first network   =       4. (  33.33 % of nodes)
435s ABC: Participating nodes from the second network  =       5. (  41.67 % of nodes)
435s ABC: Node pairs (any polarity)                    =       4. (  33.33 % of names can be moved)
435s ABC: Node pairs (same polarity)                   =       4. (  33.33 % of names can be moved)
435s ABC: Total runtime =     0.04 sec
435s ABC: + write_blif <abc-temp-dir>/output.blif 
435s 
435s 2.41.1.2. Re-integrating ABC results.
435s ABC RESULTS:              $lut cells:       11
435s ABC RESULTS:        internal signals:       23
435s ABC RESULTS:           input signals:       27
435s ABC RESULTS:          output signals:        4
435s Removing temp directory.
435s 
435s 2.42. Executing ICE40_WRAPCARRY pass (wrap carries).
435s 
435s 2.43. Executing TECHMAP pass (map to technology primitives).
435s 
435s 2.43.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v
435s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation.
435s Generating RTLIL representation for module `\$_DFF_N_'.
435s Generating RTLIL representation for module `\$_DFF_P_'.
435s Generating RTLIL representation for module `\$_DFFE_NP_'.
435s Generating RTLIL representation for module `\$_DFFE_PP_'.
435s Generating RTLIL representation for module `\$_DFF_NP0_'.
435s Generating RTLIL representation for module `\$_DFF_NP1_'.
435s Generating RTLIL representation for module `\$_DFF_PP0_'.
435s Generating RTLIL representation for module `\$_DFF_PP1_'.
435s Generating RTLIL representation for module `\$_DFFE_NP0P_'.
435s Generating RTLIL representation for module `\$_DFFE_NP1P_'.
435s Generating RTLIL representation for module `\$_DFFE_PP0P_'.
435s Generating RTLIL representation for module `\$_DFFE_PP1P_'.
435s Generating RTLIL representation for module `\$_SDFF_NP0_'.
435s Generating RTLIL representation for module `\$_SDFF_NP1_'.
435s Generating RTLIL representation for module `\$_SDFF_PP0_'.
435s Generating RTLIL representation for module `\$_SDFF_PP1_'.
435s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
435s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
435s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
435s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
435s Successfully finished Verilog frontend.
435s 
435s 2.43.2. Continuing TECHMAP pass.
435s No more expansions possible.
435s <suppressed ~22 debug messages>
435s Removed 2 unused cells and 39 unused wires.
435s 
435s 2.44. Executing OPT_LUT pass (optimize LUTs).
435s Discovering LUTs.
435s Number of LUTs:       36
435s   1-LUT                1
435s   2-LUT                3
435s   3-LUT               25
435s   4-LUT                7
435s   with \SB_CARRY    (#0)   23
435s   with \SB_CARRY    (#1)   23
435s 
435s Eliminating LUTs.
435s Number of LUTs:       36
435s   1-LUT                1
435s   2-LUT                3
435s   3-LUT               25
435s   4-LUT                7
435s   with \SB_CARRY    (#0)   23
435s   with \SB_CARRY    (#1)   23
435s 
435s Combining LUTs.
435s Number of LUTs:       36
435s   1-LUT                1
435s   2-LUT                3
435s   3-LUT               25
435s   4-LUT                7
435s   with \SB_CARRY    (#0)   23
435s   with \SB_CARRY    (#1)   23
435s 
435s Eliminated 0 LUTs.
435s Combined 0 LUTs.
435s <suppressed ~165 debug messages>
435s 
435s 2.45. Executing TECHMAP pass (map to technology primitives).
435s 
435s 2.45.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v
435s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation.
435s Generating RTLIL representation for module `\$lut'.
435s Successfully finished Verilog frontend.
435s 
435s 2.45.2. Continuing TECHMAP pass.
435s Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut.
435s Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut.
435s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut.
435s Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut.
435s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
435s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111000 for cells of type $lut.
435s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
435s No more expansions possible.
435s <suppressed ~130 debug messages>
435s Removed 0 unused cells and 76 unused wires.
435s 
435s 2.46. Executing AUTONAME pass.
435s Renamed 723 objects in module top (15 iterations).
435s <suppressed ~96 debug messages>
435s 
435s 2.47. Executing HIERARCHY pass (managing design hierarchy).
435s 
435s 2.47.1. Analyzing design hierarchy..
435s Top module:  \top
435s 
435s 2.47.2. Analyzing design hierarchy..
435s Top module:  \top
435s Removed 0 unused modules.
435s 
435s 2.48. Printing statistics.
435s 
435s === top ===
435s 
435s    Number of wires:                 19
435s    Number of wire bits:             97
435s    Number of public wires:          19
435s    Number of public wire bits:      97
435s    Number of memories:               0
435s    Number of memory bits:            0
435s    Number of processes:              0
435s    Number of cells:                 87
435s      SB_CARRY                       23
435s      SB_DFF                         27
435s      SB_LUT4                        36
435s      SB_WARMBOOT                     1
435s 
435s 2.49. Executing CHECK pass (checking for obvious problems).
435s Checking module top...
435s Found and reported 0 problems.
435s 
435s 2.50. Executing JSON backend.
435s 
435s End of script. Logfile hash: 065be7d3a4, CPU: user 0.96s system 0.02s, MEM: 20.00 MB peak
435s Yosys 0.33 (git sha1 2584903a060)
435s Time spent: 60% 13x read_verilog (0 sec), 10% 1x abc (0 sec), ...
435s nextpnr-ice40 --hx1k --package tq144 --asc app2.asc --pcf icestick.pcf --json app2.json
435s Warning: unmatched constraint 'RX' (on line 4)
435s Warning: unmatched constraint 'TX' (on line 5)
435s Info: constrained 'LED1' to bel 'X13/Y12/io1'
435s Info: constrained 'LED2' to bel 'X13/Y12/io0'
435s Info: constrained 'LED3' to bel 'X13/Y11/io1'
435s Info: constrained 'LED4' to bel 'X13/Y11/io0'
435s Info: constrained 'LED5' to bel 'X13/Y9/io1'
435s Info: constrained 'clk' to bel 'X0/Y8/io1'
435s 
435s Info: Packing constants..
435s Info: Packing IOs..
435s Info: Packing LUT-FFs..
435s Info:        9 LCs used as LUT4 only
435s Info:       27 LCs used as LUT4 and DFF
435s Info: Packing non-LUT FFs..
435s Info:        0 LCs used as DFF only
435s Info: Packing carries..
435s Info:        0 LCs used as CARRY only
435s Info: Packing indirect carry+LUT pairs...
435s Info:        0 LUTs merged into carry LCs
435s Info: Packing RAMs..
435s Info: Placing PLLs..
435s Info: Packing special functions..
435s Info: Packing PLLs..
435s Info: Promoting globals..
435s Info: promoting clk$SB_IO_IN (fanout 27)
435s Info: Constraining chains...
435s Info:        1 LCs used to legalise carry chains.
435s Info: Checksum: 0xcee87ee0
435s 
435s Info: Annotating ports with timing budgets for target frequency 12.00 MHz
435s Info: Checksum: 0x1b837c79
435s 
435s Info: Device utilisation:
435s Info: 	         ICESTORM_LC:    39/ 1280     3%
435s Info: 	        ICESTORM_RAM:     0/   16     0%
435s Info: 	               SB_IO:     6/  112     5%
435s Info: 	               SB_GB:     1/    8    12%
435s Info: 	        ICESTORM_PLL:     0/    1     0%
435s Info: 	         SB_WARMBOOT:     1/    1   100%
435s 
435s Info: Placed 6 cells based on constraints.
435s Info: Creating initial analytic placement for 17 cells, random placement wirelen = 333.
435s Info:     at initial placer iter 0, wirelen = 15
435s Info:     at initial placer iter 1, wirelen = 15
435s Info:     at initial placer iter 2, wirelen = 15
435s Info:     at initial placer iter 3, wirelen = 15
435s Info: Running main analytical placer, max placement attempts per cell = 10000.
435s Info:     at iteration #1, type ICESTORM_LC: wirelen solved = 21, spread = 69, legal = 69; time = 0.00s
435s Info:     at iteration #1, type SB_GB: wirelen solved = 69, spread = 69, legal = 69; time = 0.00s
435s Info:     at iteration #1, type SB_WARMBOOT: wirelen solved = 66, spread = 66, legal = 104; time = 0.00s
435s Info:     at iteration #1, type ALL: wirelen solved = 15, spread = 85, legal = 161; time = 0.00s
435s Info:     at iteration #2, type ICESTORM_LC: wirelen solved = 59, spread = 98, legal = 116; time = 0.00s
435s Info:     at iteration #2, type SB_GB: wirelen solved = 116, spread = 116, legal = 116; time = 0.00s
435s Info:     at iteration #2, type SB_WARMBOOT: wirelen solved = 79, spread = 79, legal = 116; time = 0.00s
435s Info:     at iteration #2, type ALL: wirelen solved = 18, spread = 47, legal = 95; time = 0.00s
435s Info:     at iteration #3, type ICESTORM_LC: wirelen solved = 59, spread = 95, legal = 103; time = 0.00s
435s Info:     at iteration #3, type SB_GB: wirelen solved = 103, spread = 103, legal = 103; time = 0.00s
435s Info:     at iteration #3, type SB_WARMBOOT: wirelen solved = 66, spread = 66, legal = 103; time = 0.00s
435s Info:     at iteration #3, type ALL: wirelen solved = 17, spread = 54, legal = 93; time = 0.00s
435s Info:     at iteration #4, type ICESTORM_LC: wirelen solved = 59, spread = 97, legal = 102; time = 0.00s
435s Info:     at iteration #4, type SB_GB: wirelen solved = 102, spread = 102, legal = 102; time = 0.00s
435s Info:     at iteration #4, type SB_WARMBOOT: wirelen solved = 65, spread = 65, legal = 102; time = 0.00s
435s Info:     at iteration #4, type ALL: wirelen solved = 25, spread = 54, legal = 93; time = 0.00s
435s Info:     at iteration #5, type ICESTORM_LC: wirelen solved = 60, spread = 97, legal = 107; time = 0.00s
435s Info:     at iteration #5, type SB_GB: wirelen solved = 107, spread = 107, legal = 107; time = 0.00s
435s Info:     at iteration #5, type SB_WARMBOOT: wirelen solved = 70, spread = 70, legal = 107; time = 0.00s
435s Info:     at iteration #5, type ALL: wirelen solved = 27, spread = 57, legal = 93; time = 0.00s
435s Info:     at iteration #6, type ICESTORM_LC: wirelen solved = 63, spread = 97, legal = 105; time = 0.00s
435s Info:     at iteration #6, type SB_GB: wirelen solved = 105, spread = 105, legal = 105; time = 0.00s
435s Info:     at iteration #6, type SB_WARMBOOT: wirelen solved = 70, spread = 70, legal = 105; time = 0.00s
435s Info:     at iteration #6, type ALL: wirelen solved = 22, spread = 56, legal = 93; time = 0.00s
435s Info:     at iteration #7, type ICESTORM_LC: wirelen solved = 63, spread = 97, legal = 100; time = 0.00s
435s Info:     at iteration #7, type SB_GB: wirelen solved = 100, spread = 100, legal = 100; time = 0.00s
435s Info:     at iteration #7, type SB_WARMBOOT: wirelen solved = 65, spread = 65, legal = 100; time = 0.00s
435s Info:     at iteration #7, type ALL: wirelen solved = 23, spread = 56, legal = 93; time = 0.00s
435s Info:     at iteration #8, type ICESTORM_LC: wirelen solved = 66, spread = 97, legal = 102; time = 0.00s
435s Info:     at iteration #8, type SB_GB: wirelen solved = 102, spread = 102, legal = 102; time = 0.00s
435s Info:     at iteration #8, type SB_WARMBOOT: wirelen solved = 68, spread = 68, legal = 102; time = 0.00s
435s Info:     at iteration #8, type ALL: wirelen solved = 23, spread = 56, legal = 93; time = 0.00s
435s Info: HeAP Placer Time: 0.02s
435s Info:   of which solving equations: 0.02s
435s Info:   of which spreading cells: 0.00s
435s Info:   of which strict legalisation: 0.00s
435s 
435s Info: Running simulated annealing placer for refinement.
435s Info:   at iteration #1: temp = 0.000000, timing cost = 15, wirelen = 93
435s Info:   at iteration #4: temp = 0.000000, timing cost = 10, wirelen = 77 
435s Info: SA placement time 0.00s
435s 
435s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 173.43 MHz (PASS at 12.00 MHz)
435s 
435s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> <async>: 3.94 ns
435s 
435s Info: Slack histogram:
435s Info:  legend: * represents 1 endpoint(s)
435s Info:          + represents [1,1) endpoint(s)
435s Info: [ 77567,  77783) |** 
435s Info: [ 77783,  77999) |* 
435s Info: [ 77999,  78215) | 
435s Info: [ 78215,  78431) |** 
435s Info: [ 78431,  78647) |** 
435s Info: [ 78647,  78863) |** 
435s Info: [ 78863,  79079) |* 
435s Info: [ 79079,  79295) |* 
435s Info: [ 79295,  79511) |*** 
435s Info: [ 79511,  79727) |** 
435s Info: [ 79727,  79943) |** 
435s Info: [ 79943,  80159) |** 
435s Info: [ 80159,  80375) |* 
435s Info: [ 80375,  80591) | 
435s Info: [ 80591,  80807) |** 
435s Info: [ 80807,  81023) |** 
435s Info: [ 81023,  81239) |** 
435s Info: [ 81239,  81455) | 
435s Info: [ 81455,  81671) |* 
435s Info: [ 81671,  81887) |**************************** 
435s Info: Checksum: 0xb2036c6e
435s 
435s Info: Routing..
435s Info: Setting up routing queue.
435s Info: Routing 125 arcs.
435s Info:            |   (re-)routed arcs  |   delta    | remaining|       time spent     |
435s Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|
435s Info:        125 |        0        105 |    0   105 |         0|       0.01       0.01|
435s Info: Routing complete.
435s Info: Router1 time 0.01s
435s Info: Checksum: 0xe289732b
435s 
435s Info: Critical path report for clock 'clk$SB_IO_IN_$glb_clk' (posedge -> posedge):
435s Info: curr total
435s Info:  0.5  0.5  Source counter_SB_LUT4_I2_20_LC.O
435s Info:  0.6  1.1    Net counter[10] budget 20.291000 ns (12,9) -> (11,9)
435s Info:                Sink state_SB_LUT4_I3_I1_SB_LUT4_O_I0_SB_LUT4_O_3_LC.I0
435s Info:                Defined in:
435s Info:                  app2.v:7.22-7.29
435s Info:  0.4  1.6  Source state_SB_LUT4_I3_I1_SB_LUT4_O_I0_SB_LUT4_O_3_LC.O
435s Info:  0.6  2.2    Net state_SB_LUT4_I3_I1_SB_LUT4_O_I0[0] budget 20.291000 ns (11,9) -> (11,10)
435s Info:                Sink state_SB_LUT4_I3_I1_SB_LUT4_O_LC.I0
435s Info:                Defined in:
435s Info:                  /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
435s Info:  0.4  2.6  Source state_SB_LUT4_I3_I1_SB_LUT4_O_LC.O
435s Info:  1.0  3.6    Net state_SB_LUT4_I3_I1[1] budget 20.291000 ns (11,10) -> (11,8)
435s Info:                Sink counter2_SB_DFF_Q_D_SB_LUT4_O_3_I1_SB_LUT4_O_LC.I3
435s Info:                Defined in:
435s Info:                  /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
435s Info:  0.3  3.9  Source counter2_SB_DFF_Q_D_SB_LUT4_O_3_I1_SB_LUT4_O_LC.O
435s Info:  0.6  4.5    Net counter2_SB_DFF_Q_D_SB_LUT4_O_3_I1 budget 20.290001 ns (11,8) -> (11,9)
435s Info:                Sink counter2_SB_DFF_Q_D_SB_LUT4_O_3_LC.I1
435s Info:                Defined in:
435s Info:                  app2.v:13.15-13.34
435s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:29.22-29.23
435s Info:  0.3  4.7  Source counter2_SB_DFF_Q_D_SB_LUT4_O_3_LC.COUT
435s Info:  0.0  4.7    Net counter2_SB_DFF_Q_D_SB_LUT4_O_3_I1_SB_CARRY_I0_CO[1] budget 0.000000 ns (11,9) -> (11,9)
435s Info:                Sink counter2_SB_DFF_Q_D_SB_LUT4_O_2_LC.CIN
435s Info:                Defined in:
435s Info:                  app2.v:13.15-13.34
435s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
435s Info:  0.1  4.9  Source counter2_SB_DFF_Q_D_SB_LUT4_O_2_LC.COUT
435s Info:  0.0  4.9    Net counter2_SB_DFF_Q_D_SB_LUT4_O_3_I1_SB_CARRY_I0_CO[2] budget 0.000000 ns (11,9) -> (11,9)
435s Info:                Sink counter2_SB_DFF_Q_D_SB_LUT4_O_1_LC.CIN
435s Info:                Defined in:
435s Info:                  app2.v:13.15-13.34
435s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
435s Info:  0.1  5.0  Source counter2_SB_DFF_Q_D_SB_LUT4_O_1_LC.COUT
435s Info:  0.3  5.2    Net counter2_SB_DFF_Q_D_SB_LUT4_O_3_I1_SB_CARRY_I0_CO[3] budget 0.260000 ns (11,9) -> (11,9)
435s Info:                Sink counter2_SB_DFF_Q_D_SB_LUT4_O_LC.I3
435s Info:                Defined in:
435s Info:                  app2.v:13.15-13.34
435s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
435s Info:  0.3  5.6  Setup counter2_SB_DFF_Q_D_SB_LUT4_O_LC.I3
435s Info: 2.6 ns logic, 3.0 ns routing
435s 
435s Info: Critical path report for cross-domain path 'posedge clk$SB_IO_IN_$glb_clk' -> '<async>':
435s Info: curr total
435s Info:  0.5  0.5  Source counter2_SB_DFF_Q_D_SB_LUT4_O_3_LC.O
435s Info:  0.6  1.1    Net counter2[0] budget 41.173000 ns (11,9) -> (11,9)
435s Info:                Sink WB_BOOT_SB_LUT4_O_LC.I0
435s Info:                Defined in:
435s Info:                  app2.v:8.12-8.20
435s Info:  0.4  1.6  Source WB_BOOT_SB_LUT4_O_LC.O
435s Info:  1.4  3.0    Net WB_BOOT budget 41.172001 ns (11,9) -> (0,0)
435s Info:                Sink WB.BOOT
435s Info:                Defined in:
435s Info:                  app2.v:24.9-24.18
435s icetime -d hx1k -c 25 app2.asc
435s // Reading input .asc file..
435s // Reading 1k chipdb file..
435s Info: 1.0 ns logic, 2.0 ns routing
435s 
435s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 179.21 MHz (PASS at 12.00 MHz)
435s 
435s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> <async>: 3.02 ns
435s 
435s Info: Slack histogram:
435s Info:  legend: * represents 1 endpoint(s)
435s Info:          + represents [1,1) endpoint(s)
435s Info: [ 77753,  77959) |** 
435s Info: [ 77959,  78165) |* 
435s Info: [ 78165,  78371) | 
435s Info: [ 78371,  78577) |*** 
435s Info: [ 78577,  78783) |* 
435s Info: [ 78783,  78989) |*** 
435s Info: [ 78989,  79195) | 
435s Info: [ 79195,  79401) |* 
435s Info: [ 79401,  79607) |** 
435s Info: [ 79607,  79813) |*** 
435s Info: [ 79813,  80019) |* 
435s Info: [ 80019,  80225) |*** 
435s Info: [ 80225,  80431) |* 
435s Info: [ 80431,  80637) |* 
435s Info: [ 80637,  80843) |* 
435s Info: [ 80843,  81049) |** 
435s Info: [ 81049,  81255) |** 
435s Info: [ 81255,  81461) | 
435s Info: [ 81461,  81667) |* 
435s Info: [ 81667,  81873) |**************************** 
435s 2 warnings, 0 errors
435s 
435s Info: Program finished normally.
435s // Creating timing netlist..
435s // Timing estimate: 5.63 ns (177.51 MHz)
435s // Checking 40.00 ns (25.00 MHz) clock constraint: PASSED.
435s icepack app2.asc app2.bin
435s yosys -p "synth_ice40 -top top -json app3.json" app3.v
435s 
435s  /----------------------------------------------------------------------------\
435s  |                                                                            |
435s  |  yosys -- Yosys Open SYnthesis Suite                                       |
435s  |                                                                            |
435s  |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
435s  |                                                                            |
435s  |  Permission to use, copy, modify, and/or distribute this software for any  |
435s  |  purpose with or without fee is hereby granted, provided that the above    |
435s  |  copyright notice and this permission notice appear in all copies.         |
435s  |                                                                            |
435s  |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
435s  |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
435s  |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
435s  |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
435s  |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
435s  |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
435s  |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
435s  |                                                                            |
435s  \----------------------------------------------------------------------------/
435s 
435s  Yosys 0.33 (git sha1 2584903a060)
435s 
435s 
435s -- Parsing `app3.v' using frontend ` -vlog2k' --
435s 
435s 1. Executing Verilog-2005 frontend: app3.v
435s Parsing Verilog input from `app3.v' to AST representation.
435s Storing AST representation for module `$abstract\top'.
435s Successfully finished Verilog frontend.
435s 
435s -- Running command `synth_ice40 -top top -json app3.json' --
435s 
435s 2. Executing SYNTH_ICE40 pass.
435s 
435s 2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v
435s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation.
435s Generating RTLIL representation for module `\SB_IO'.
435s Generating RTLIL representation for module `\SB_GB_IO'.
435s Generating RTLIL representation for module `\SB_GB'.
435s Generating RTLIL representation for module `\SB_LUT4'.
435s Generating RTLIL representation for module `\SB_CARRY'.
435s Generating RTLIL representation for module `\SB_DFF'.
435s Generating RTLIL representation for module `\SB_DFFE'.
435s Generating RTLIL representation for module `\SB_DFFSR'.
435s Generating RTLIL representation for module `\SB_DFFR'.
435s Generating RTLIL representation for module `\SB_DFFSS'.
435s Generating RTLIL representation for module `\SB_DFFS'.
435s Generating RTLIL representation for module `\SB_DFFESR'.
435s Generating RTLIL representation for module `\SB_DFFER'.
435s Generating RTLIL representation for module `\SB_DFFESS'.
435s Generating RTLIL representation for module `\SB_DFFES'.
435s Generating RTLIL representation for module `\SB_DFFN'.
435s Generating RTLIL representation for module `\SB_DFFNE'.
435s Generating RTLIL representation for module `\SB_DFFNSR'.
435s Generating RTLIL representation for module `\SB_DFFNR'.
435s Generating RTLIL representation for module `\SB_DFFNSS'.
435s Generating RTLIL representation for module `\SB_DFFNS'.
435s Generating RTLIL representation for module `\SB_DFFNESR'.
435s Generating RTLIL representation for module `\SB_DFFNER'.
435s Generating RTLIL representation for module `\SB_DFFNESS'.
435s Generating RTLIL representation for module `\SB_DFFNES'.
435s Generating RTLIL representation for module `\SB_RAM40_4K'.
435s Generating RTLIL representation for module `\SB_RAM40_4KNR'.
435s Generating RTLIL representation for module `\SB_RAM40_4KNW'.
435s Generating RTLIL representation for module `\SB_RAM40_4KNRNW'.
435s Generating RTLIL representation for module `\ICESTORM_LC'.
435s Generating RTLIL representation for module `\SB_PLL40_CORE'.
435s Generating RTLIL representation for module `\SB_PLL40_PAD'.
435s Generating RTLIL representation for module `\SB_PLL40_2_PAD'.
435s Generating RTLIL representation for module `\SB_PLL40_2F_CORE'.
435s Generating RTLIL representation for module `\SB_PLL40_2F_PAD'.
435s Generating RTLIL representation for module `\SB_WARMBOOT'.
435s Generating RTLIL representation for module `\SB_SPRAM256KA'.
435s Generating RTLIL representation for module `\SB_HFOSC'.
435s Generating RTLIL representation for module `\SB_LFOSC'.
435s Generating RTLIL representation for module `\SB_RGBA_DRV'.
435s Generating RTLIL representation for module `\SB_LED_DRV_CUR'.
435s Generating RTLIL representation for module `\SB_RGB_DRV'.
435s Generating RTLIL representation for module `\SB_I2C'.
435s Generating RTLIL representation for module `\SB_SPI'.
435s Generating RTLIL representation for module `\SB_LEDDA_IP'.
435s Generating RTLIL representation for module `\SB_FILTER_50NS'.
435s Generating RTLIL representation for module `\SB_IO_I3C'.
435s Generating RTLIL representation for module `\SB_IO_OD'.
435s Generating RTLIL representation for module `\SB_MAC16'.
435s Generating RTLIL representation for module `\ICESTORM_RAM'.
435s Successfully finished Verilog frontend.
435s 
435s 2.2. Executing HIERARCHY pass (managing design hierarchy).
435s 
435s 2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\top'.
435s Generating RTLIL representation for module `\top'.
435s 
435s 2.3.1. Analyzing design hierarchy..
435s Top module:  \top
435s 
435s 2.3.2. Analyzing design hierarchy..
435s Top module:  \top
435s Removing unused module `$abstract\top'.
435s Removed 1 unused modules.
435s 
435s 2.4. Executing PROC pass (convert processes to netlists).
435s 
435s 2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
435s Cleaned up 0 empty switches.
435s 
435s 2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
435s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241 in module SB_DFFNES.
435s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234 in module SB_DFFNESS.
435s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230 in module SB_DFFNER.
435s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223 in module SB_DFFNESR.
435s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220 in module SB_DFFNS.
435s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217 in module SB_DFFNSS.
435s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214 in module SB_DFFNR.
435s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211 in module SB_DFFNSR.
435s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203 in module SB_DFFES.
435s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196 in module SB_DFFESS.
435s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192 in module SB_DFFER.
435s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185 in module SB_DFFESR.
435s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182 in module SB_DFFS.
435s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179 in module SB_DFFSS.
435s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176 in module SB_DFFR.
435s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173 in module SB_DFFSR.
435s Removed a total of 0 dead cases.
435s 
435s 2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
435s Removed 8 redundant assignments.
435s Promoted 28 assignments to connections.
435s 
435s 2.4.4. Executing PROC_INIT pass (extract init attributes).
435s Found init rule in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'.
435s   Set init value: \Q = 1'0
435s Found init rule in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'.
435s   Set init value: \Q = 1'0
435s Found init rule in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'.
435s   Set init value: \Q = 1'0
435s Found init rule in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'.
435s   Set init value: \Q = 1'0
435s Found init rule in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'.
435s   Set init value: \Q = 1'0
435s Found init rule in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'.
435s   Set init value: \Q = 1'0
435s Found init rule in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'.
435s   Set init value: \Q = 1'0
435s Found init rule in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'.
435s   Set init value: \Q = 1'0
435s Found init rule in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'.
435s   Set init value: \Q = 1'0
435s Found init rule in `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'.
435s   Set init value: \Q = 1'0
435s Found init rule in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'.
435s   Set init value: \Q = 1'0
435s Found init rule in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'.
435s   Set init value: \Q = 1'0
435s Found init rule in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'.
435s   Set init value: \Q = 1'0
435s Found init rule in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'.
435s   Set init value: \Q = 1'0
435s Found init rule in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'.
435s   Set init value: \Q = 1'0
435s Found init rule in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'.
435s   Set init value: \Q = 1'0
435s Found init rule in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'.
435s   Set init value: \Q = 1'0
435s Found init rule in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'.
435s   Set init value: \Q = 1'0
435s Found init rule in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'.
435s   Set init value: \Q = 1'0
435s Found init rule in `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'.
435s   Set init value: \Q = 1'0
435s Found init rule in `\top.$proc$app3.v:9$390'.
435s   Set init value: \state = 1'0
435s Found init rule in `\top.$proc$app3.v:8$389'.
435s   Set init value: \counter2 = 4'0000
435s Found init rule in `\top.$proc$app3.v:7$388'.
435s   Set init value: \counter = 22'0000000000000000000000
435s 
435s 2.4.5. Executing PROC_ARST pass (detect async resets in processes).
435s Found async reset \S in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
435s Found async reset \R in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
435s Found async reset \S in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
435s Found async reset \R in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
435s Found async reset \S in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
435s Found async reset \R in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
435s Found async reset \S in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'.
435s Found async reset \R in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'.
435s 
435s 2.4.6. Executing PROC_ROM pass (convert switches to ROMs).
435s Converted 0 switches.
435s <suppressed ~18 debug messages>
435s 
435s 2.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
435s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'.
435s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
435s      1/1: $0\Q[0:0]
435s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'.
435s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
435s      1/1: $0\Q[0:0]
435s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'.
435s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
435s      1/1: $0\Q[0:0]
435s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'.
435s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
435s      1/1: $0\Q[0:0]
435s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'.
435s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
435s      1/1: $0\Q[0:0]
435s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'.
435s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
435s      1/1: $0\Q[0:0]
435s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'.
435s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
435s      1/1: $0\Q[0:0]
435s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'.
435s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'.
435s      1/1: $0\Q[0:0]
435s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'.
435s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'.
435s      1/1: $0\Q[0:0]
435s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'.
435s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'.
435s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'.
435s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
435s      1/1: $0\Q[0:0]
435s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'.
435s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'.
435s      1/1: $0\Q[0:0]
435s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'.
435s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
435s      1/1: $0\Q[0:0]
435s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'.
435s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'.
435s      1/1: $0\Q[0:0]
435s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'.
435s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'.
435s      1/1: $0\Q[0:0]
435s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'.
435s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'.
435s      1/1: $0\Q[0:0]
435s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'.
435s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'.
435s      1/1: $0\Q[0:0]
435s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'.
435s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'.
435s      1/1: $0\Q[0:0]
435s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'.
435s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'.
435s      1/1: $0\Q[0:0]
435s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'.
435s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'.
435s Creating decoders for process `\top.$proc$app3.v:9$390'.
435s Creating decoders for process `\top.$proc$app3.v:8$389'.
435s Creating decoders for process `\top.$proc$app3.v:7$388'.
435s Creating decoders for process `\top.$proc$app3.v:11$381'.
435s 
435s 2.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
435s 
435s 2.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
435s Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
435s   created $adff cell `$procdff$435' with negative edge clock and positive level reset.
435s Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
435s   created $dff cell `$procdff$436' with negative edge clock.
435s Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
435s   created $adff cell `$procdff$437' with negative edge clock and positive level reset.
435s Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
435s   created $dff cell `$procdff$438' with negative edge clock.
435s Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
435s   created $adff cell `$procdff$439' with negative edge clock and positive level reset.
435s Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
435s   created $dff cell `$procdff$440' with negative edge clock.
435s Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
435s   created $adff cell `$procdff$441' with negative edge clock and positive level reset.
435s Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'.
435s   created $dff cell `$procdff$442' with negative edge clock.
435s Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'.
435s   created $dff cell `$procdff$443' with negative edge clock.
435s Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'.
435s   created $dff cell `$procdff$444' with negative edge clock.
435s Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
435s   created $adff cell `$procdff$445' with positive edge clock and positive level reset.
435s Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'.
435s   created $dff cell `$procdff$446' with positive edge clock.
435s Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
435s   created $adff cell `$procdff$447' with positive edge clock and positive level reset.
435s Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'.
435s   created $dff cell `$procdff$448' with positive edge clock.
435s Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'.
435s   created $adff cell `$procdff$449' with positive edge clock and positive level reset.
435s Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'.
435s   created $dff cell `$procdff$450' with positive edge clock.
435s Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'.
435s   created $adff cell `$procdff$451' with positive edge clock and positive level reset.
435s Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'.
435s   created $dff cell `$procdff$452' with positive edge clock.
435s Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'.
435s   created $dff cell `$procdff$453' with positive edge clock.
435s Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'.
435s   created $dff cell `$procdff$454' with positive edge clock.
435s Creating register for signal `\top.\counter' using process `\top.$proc$app3.v:11$381'.
435s   created $dff cell `$procdff$455' with positive edge clock.
435s Creating register for signal `\top.\counter2' using process `\top.$proc$app3.v:11$381'.
435s   created $dff cell `$procdff$456' with positive edge clock.
435s Creating register for signal `\top.\state' using process `\top.$proc$app3.v:11$381'.
435s   created $dff cell `$procdff$457' with positive edge clock.
435s 
435s 2.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
435s 
435s 2.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
435s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'.
435s Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
435s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
435s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'.
435s Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
435s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
435s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'.
435s Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
435s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
435s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'.
435s Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
435s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
435s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'.
435s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
435s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'.
435s Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
435s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
435s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'.
435s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
435s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'.
435s Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'.
435s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'.
435s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'.
435s Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'.
435s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'.
435s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'.
435s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'.
435s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'.
435s Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
435s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
435s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'.
435s Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'.
435s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'.
435s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'.
435s Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
435s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
435s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'.
435s Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'.
435s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'.
435s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'.
435s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'.
435s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'.
435s Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'.
435s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'.
435s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'.
435s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'.
435s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'.
435s Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'.
435s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'.
435s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'.
435s Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'.
435s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'.
435s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'.
435s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'.
435s Removing empty process `top.$proc$app3.v:9$390'.
435s Removing empty process `top.$proc$app3.v:8$389'.
435s Removing empty process `top.$proc$app3.v:7$388'.
435s Removing empty process `top.$proc$app3.v:11$381'.
435s Cleaned up 18 empty switches.
435s 
435s 2.4.12. Executing OPT_EXPR pass (perform const folding).
435s Optimizing module top.
435s 
435s 2.5. Executing FLATTEN pass (flatten design).
435s 
435s 2.6. Executing TRIBUF pass.
435s 
435s 2.7. Executing DEMINOUT pass (demote inout ports to input or output).
435s 
435s 2.8. Executing OPT_EXPR pass (perform const folding).
435s Optimizing module top.
435s 
435s 2.9. Executing OPT_CLEAN pass (remove unused cells and wires).
435s Finding unused cells or wires in module \top..
435s Removed 0 unused cells and 5 unused wires.
435s <suppressed ~1 debug messages>
435s 
435s 2.10. Executing CHECK pass (checking for obvious problems).
435s Checking module top...
435s Found and reported 0 problems.
435s 
435s 2.11. Executing OPT pass (performing simple optimizations).
435s 
435s 2.11.1. Executing OPT_EXPR pass (perform const folding).
435s Optimizing module top.
435s 
435s 2.11.2. Executing OPT_MERGE pass (detect identical cells).
435s Finding identical cells in module `\top'.
435s Removed a total of 0 cells.
435s 
435s 2.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
435s Running muxtree optimizer on module \top..
435s   Creating internal representation of mux trees.
435s   No muxes found in this module.
435s Removed 0 multiplexer ports.
435s 
435s 2.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
435s   Optimizing cells in module \top.
435s Performed a total of 0 changes.
435s 
435s 2.11.5. Executing OPT_MERGE pass (detect identical cells).
435s Finding identical cells in module `\top'.
435s Removed a total of 0 cells.
435s 
435s 2.11.6. Executing OPT_DFF pass (perform DFF optimizations).
435s 
435s 2.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
435s Finding unused cells or wires in module \top..
435s 
435s 2.11.8. Executing OPT_EXPR pass (perform const folding).
435s Optimizing module top.
435s 
435s 2.11.9. Finished OPT passes. (There is nothing left to do.)
435s 
435s 2.12. Executing FSM pass (extract and optimize FSM).
435s 
435s 2.12.1. Executing FSM_DETECT pass (finding FSMs in design).
435s 
435s 2.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).
435s 
435s 2.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).
435s 
435s 2.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
435s Finding unused cells or wires in module \top..
435s 
435s 2.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).
435s 
435s 2.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
435s 
435s 2.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
436s 
436s 2.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
436s 
436s 2.13. Executing OPT pass (performing simple optimizations).
436s 
436s 2.13.1. Executing OPT_EXPR pass (perform const folding).
436s Optimizing module top.
436s 
436s 2.13.2. Executing OPT_MERGE pass (detect identical cells).
436s Finding identical cells in module `\top'.
436s Removed a total of 0 cells.
436s 
436s 2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
436s Running muxtree optimizer on module \top..
436s   Creating internal representation of mux trees.
436s   No muxes found in this module.
436s Removed 0 multiplexer ports.
436s 
436s 2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
436s   Optimizing cells in module \top.
436s Performed a total of 0 changes.
436s 
436s 2.13.5. Executing OPT_MERGE pass (detect identical cells).
436s Finding identical cells in module `\top'.
436s Removed a total of 0 cells.
436s 
436s 2.13.6. Executing OPT_DFF pass (perform DFF optimizations).
436s 
436s 2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
436s Finding unused cells or wires in module \top..
436s 
436s 2.13.8. Executing OPT_EXPR pass (perform const folding).
436s Optimizing module top.
436s 
436s 2.13.9. Finished OPT passes. (There is nothing left to do.)
436s 
436s 2.14. Executing WREDUCE pass (reducing word size of cells).
436s Removed top 31 bits (of 32) from port B of cell top.$add$app3.v:12$382 ($add).
436s Removed top 10 bits (of 32) from port Y of cell top.$add$app3.v:12$382 ($add).
436s Removed top 3 bits (of 4) from port B of cell top.$add$app3.v:13$384 ($add).
436s Removed top 3 bits (of 4) from wire top.$logic_not$app3.v:13$383_Y.
436s 
436s 2.15. Executing PEEPOPT pass (run peephole optimizers).
436s 
436s 2.16. Executing OPT_CLEAN pass (remove unused cells and wires).
436s Finding unused cells or wires in module \top..
436s Removed 0 unused cells and 2 unused wires.
436s <suppressed ~1 debug messages>
436s 
436s 2.17. Executing SHARE pass (SAT-based resource sharing).
436s 
436s 2.18. Executing TECHMAP pass (map to technology primitives).
436s 
436s 2.18.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v
436s Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation.
436s Generating RTLIL representation for module `\_90_lut_cmp_'.
436s Successfully finished Verilog frontend.
436s 
436s 2.18.2. Continuing TECHMAP pass.
436s No more expansions possible.
436s <suppressed ~6 debug messages>
436s 
436s 2.19. Executing OPT_EXPR pass (perform const folding).
436s Optimizing module top.
436s 
436s 2.20. Executing OPT_CLEAN pass (remove unused cells and wires).
436s Finding unused cells or wires in module \top..
436s 
436s 2.21. Executing ALUMACC pass (create $alu and $macc cells).
436s Extracting $alu and $macc cells in module top:
436s   creating $macc model for $add$app3.v:12$382 ($add).
436s   creating $macc model for $add$app3.v:13$384 ($add).
436s   creating $alu model for $macc $add$app3.v:13$384.
436s   creating $alu model for $macc $add$app3.v:12$382.
436s   creating $alu cell for $add$app3.v:12$382: $auto$alumacc.cc:485:replace_alu$460
436s   creating $alu cell for $add$app3.v:13$384: $auto$alumacc.cc:485:replace_alu$463
436s   created 2 $alu and 0 $macc cells.
436s 
436s 2.22. Executing OPT pass (performing simple optimizations).
436s 
436s 2.22.1. Executing OPT_EXPR pass (perform const folding).
436s Optimizing module top.
436s 
436s 2.22.2. Executing OPT_MERGE pass (detect identical cells).
436s Finding identical cells in module `\top'.
436s <suppressed ~3 debug messages>
436s Removed a total of 1 cells.
436s 
436s 2.22.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
436s Running muxtree optimizer on module \top..
436s   Creating internal representation of mux trees.
436s   No muxes found in this module.
436s Removed 0 multiplexer ports.
436s 
436s 2.22.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
436s   Optimizing cells in module \top.
436s Performed a total of 0 changes.
436s 
436s 2.22.5. Executing OPT_MERGE pass (detect identical cells).
436s Finding identical cells in module `\top'.
436s Removed a total of 0 cells.
436s 
436s 2.22.6. Executing OPT_DFF pass (perform DFF optimizations).
436s 
436s 2.22.7. Executing OPT_CLEAN pass (remove unused cells and wires).
436s Finding unused cells or wires in module \top..
436s Removed 0 unused cells and 1 unused wires.
436s <suppressed ~1 debug messages>
436s 
436s 2.22.8. Executing OPT_EXPR pass (perform const folding).
436s Optimizing module top.
436s 
436s 2.22.9. Rerunning OPT passes. (Maybe there is more to do..)
436s 
436s 2.22.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
436s Running muxtree optimizer on module \top..
436s   Creating internal representation of mux trees.
436s   No muxes found in this module.
436s Removed 0 multiplexer ports.
436s 
436s 2.22.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
436s   Optimizing cells in module \top.
436s Performed a total of 0 changes.
436s 
436s 2.22.12. Executing OPT_MERGE pass (detect identical cells).
436s Finding identical cells in module `\top'.
436s Removed a total of 0 cells.
436s 
436s 2.22.13. Executing OPT_DFF pass (perform DFF optimizations).
436s 
436s 2.22.14. Executing OPT_CLEAN pass (remove unused cells and wires).
436s Finding unused cells or wires in module \top..
436s 
436s 2.22.15. Executing OPT_EXPR pass (perform const folding).
436s Optimizing module top.
436s 
436s 2.22.16. Finished OPT passes. (There is nothing left to do.)
436s 
436s 2.23. Executing MEMORY pass.
436s 
436s 2.23.1. Executing OPT_MEM pass (optimize memories).
436s Performed a total of 0 transformations.
436s 
436s 2.23.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
436s Performed a total of 0 transformations.
436s 
436s 2.23.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
436s 
436s 2.23.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
436s 
436s 2.23.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
436s 
436s 2.23.6. Executing OPT_CLEAN pass (remove unused cells and wires).
436s Finding unused cells or wires in module \top..
436s 
436s 2.23.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
436s 
436s 2.23.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
436s Performed a total of 0 transformations.
436s 
436s 2.23.9. Executing OPT_CLEAN pass (remove unused cells and wires).
436s Finding unused cells or wires in module \top..
436s 
436s 2.23.10. Executing MEMORY_COLLECT pass (generating $mem cells).
436s 
436s 2.24. Executing OPT_CLEAN pass (remove unused cells and wires).
436s Finding unused cells or wires in module \top..
436s 
436s 2.25. Executing MEMORY_LIBMAP pass (mapping memories to cells).
436s 
436s 2.26. Executing TECHMAP pass (map to technology primitives).
436s 
436s 2.26.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v
436s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation.
436s Generating RTLIL representation for module `\$__ICE40_RAM4K_'.
436s Successfully finished Verilog frontend.
436s 
436s 2.26.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/spram_map.v
436s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/spram_map.v' to AST representation.
436s Generating RTLIL representation for module `\$__ICE40_SPRAM_'.
436s Successfully finished Verilog frontend.
436s 
436s 2.26.3. Continuing TECHMAP pass.
436s No more expansions possible.
436s <suppressed ~4 debug messages>
436s 
436s 2.27. Executing ICE40_BRAMINIT pass.
436s 
436s 2.28. Executing OPT pass (performing simple optimizations).
436s 
436s 2.28.1. Executing OPT_EXPR pass (perform const folding).
436s Optimizing module top.
436s 
436s 2.28.2. Executing OPT_MERGE pass (detect identical cells).
436s Finding identical cells in module `\top'.
436s Removed a total of 0 cells.
436s 
436s 2.28.3. Executing OPT_DFF pass (perform DFF optimizations).
436s 
436s 2.28.4. Executing OPT_CLEAN pass (remove unused cells and wires).
436s Finding unused cells or wires in module \top..
436s 
436s 2.28.5. Finished fast OPT passes.
436s 
436s 2.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
436s 
436s 2.30. Executing OPT pass (performing simple optimizations).
436s 
436s 2.30.1. Executing OPT_EXPR pass (perform const folding).
436s Optimizing module top.
436s 
436s 2.30.2. Executing OPT_MERGE pass (detect identical cells).
436s Finding identical cells in module `\top'.
436s Removed a total of 0 cells.
436s 
436s 2.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
436s Running muxtree optimizer on module \top..
436s   Creating internal representation of mux trees.
436s   No muxes found in this module.
436s Removed 0 multiplexer ports.
436s 
436s 2.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
436s   Optimizing cells in module \top.
436s Performed a total of 0 changes.
436s 
436s 2.30.5. Executing OPT_MERGE pass (detect identical cells).
436s Finding identical cells in module `\top'.
436s Removed a total of 0 cells.
436s 
436s 2.30.6. Executing OPT_DFF pass (perform DFF optimizations).
436s 
436s 2.30.7. Executing OPT_CLEAN pass (remove unused cells and wires).
436s Finding unused cells or wires in module \top..
436s 
436s 2.30.8. Executing OPT_EXPR pass (perform const folding).
436s Optimizing module top.
436s 
436s 2.30.9. Finished OPT passes. (There is nothing left to do.)
436s 
436s 2.31. Executing ICE40_WRAPCARRY pass (wrap carries).
436s 
436s 2.32. Executing TECHMAP pass (map to technology primitives).
436s 
436s 2.32.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v
436s Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation.
436s Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
436s Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
436s Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
436s Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
436s Generating RTLIL representation for module `\_90_simplemap_various'.
436s Generating RTLIL representation for module `\_90_simplemap_registers'.
436s Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
436s Generating RTLIL representation for module `\_90_shift_shiftx'.
436s Generating RTLIL representation for module `\_90_fa'.
436s Generating RTLIL representation for module `\_90_lcu'.
436s Generating RTLIL representation for module `\_90_alu'.
436s Generating RTLIL representation for module `\_90_macc'.
436s Generating RTLIL representation for module `\_90_alumacc'.
436s Generating RTLIL representation for module `\$__div_mod_u'.
436s Generating RTLIL representation for module `\$__div_mod_trunc'.
436s Generating RTLIL representation for module `\_90_div'.
436s Generating RTLIL representation for module `\_90_mod'.
436s Generating RTLIL representation for module `\$__div_mod_floor'.
436s Generating RTLIL representation for module `\_90_divfloor'.
436s Generating RTLIL representation for module `\_90_modfloor'.
436s Generating RTLIL representation for module `\_90_pow'.
436s Generating RTLIL representation for module `\_90_pmux'.
436s Generating RTLIL representation for module `\_90_demux'.
436s Generating RTLIL representation for module `\_90_lut'.
436s Successfully finished Verilog frontend.
436s 
436s 2.32.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v
436s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation.
436s Generating RTLIL representation for module `\_80_ice40_alu'.
436s Successfully finished Verilog frontend.
436s 
436s 2.32.3. Continuing TECHMAP pass.
436s Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_80_ice40_alu for cells of type $alu.
436s Using extmapper simplemap for cells of type $logic_not.
436s Using template $paramod$080e6a70eb8bfa1ccf22d9718e795074645029a4\_80_ice40_alu for cells of type $alu.
436s Using extmapper simplemap for cells of type $xor.
436s Using extmapper simplemap for cells of type $reduce_and.
436s Using extmapper simplemap for cells of type $dff.
436s Using extmapper simplemap for cells of type $mux.
436s Using extmapper simplemap for cells of type $not.
436s Using extmapper simplemap for cells of type $pos.
436s No more expansions possible.
436s <suppressed ~129 debug messages>
436s 
436s 2.33. Executing OPT pass (performing simple optimizations).
436s 
436s 2.33.1. Executing OPT_EXPR pass (perform const folding).
436s Optimizing module top.
436s <suppressed ~51 debug messages>
436s 
436s 2.33.2. Executing OPT_MERGE pass (detect identical cells).
436s Finding identical cells in module `\top'.
436s <suppressed ~3 debug messages>
436s Removed a total of 1 cells.
436s 
436s 2.33.3. Executing OPT_DFF pass (perform DFF optimizations).
436s 
436s 2.33.4. Executing OPT_CLEAN pass (remove unused cells and wires).
436s Finding unused cells or wires in module \top..
436s Removed 27 unused cells and 34 unused wires.
436s <suppressed ~28 debug messages>
436s 
436s 2.33.5. Finished fast OPT passes.
436s 
436s 2.34. Executing ICE40_OPT pass (performing simple optimizations).
436s 
436s 2.34.1. Running ICE40 specific optimizations.
436s Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$460.slice[0].carry: CO=\counter [0]
436s 
436s 2.34.2. Executing OPT_EXPR pass (perform const folding).
436s Optimizing module top.
436s 
436s 2.34.3. Executing OPT_MERGE pass (detect identical cells).
436s Finding identical cells in module `\top'.
436s Removed a total of 0 cells.
436s 
436s 2.34.4. Executing OPT_DFF pass (perform DFF optimizations).
436s 
436s 2.34.5. Executing OPT_CLEAN pass (remove unused cells and wires).
436s Finding unused cells or wires in module \top..
436s 
436s 2.34.6. Rerunning OPT passes. (Removed registers in this run.)
436s 
436s 2.34.7. Running ICE40 specific optimizations.
436s 
436s 2.34.8. Executing OPT_EXPR pass (perform const folding).
436s Optimizing module top.
436s 
436s 2.34.9. Executing OPT_MERGE pass (detect identical cells).
436s Finding identical cells in module `\top'.
436s Removed a total of 0 cells.
436s 
436s 2.34.10. Executing OPT_DFF pass (perform DFF optimizations).
436s 
436s 2.34.11. Executing OPT_CLEAN pass (remove unused cells and wires).
436s Finding unused cells or wires in module \top..
436s 
436s 2.34.12. Finished OPT passes. (There is nothing left to do.)
436s 
436s 2.35. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
436s 
436s 2.36. Executing TECHMAP pass (map to technology primitives).
436s 
436s 2.36.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v
436s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation.
436s Generating RTLIL representation for module `\$_DFF_N_'.
436s Generating RTLIL representation for module `\$_DFF_P_'.
436s Generating RTLIL representation for module `\$_DFFE_NP_'.
436s Generating RTLIL representation for module `\$_DFFE_PP_'.
436s Generating RTLIL representation for module `\$_DFF_NP0_'.
436s Generating RTLIL representation for module `\$_DFF_NP1_'.
436s Generating RTLIL representation for module `\$_DFF_PP0_'.
436s Generating RTLIL representation for module `\$_DFF_PP1_'.
436s Generating RTLIL representation for module `\$_DFFE_NP0P_'.
436s Generating RTLIL representation for module `\$_DFFE_NP1P_'.
436s Generating RTLIL representation for module `\$_DFFE_PP0P_'.
436s Generating RTLIL representation for module `\$_DFFE_PP1P_'.
436s Generating RTLIL representation for module `\$_SDFF_NP0_'.
436s Generating RTLIL representation for module `\$_SDFF_NP1_'.
436s Generating RTLIL representation for module `\$_SDFF_PP0_'.
436s Generating RTLIL representation for module `\$_SDFF_PP1_'.
436s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
436s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
436s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
436s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
436s Successfully finished Verilog frontend.
436s 
436s 2.36.2. Continuing TECHMAP pass.
436s Using template \$_DFF_P_ for cells of type $_DFF_P_.
436s No more expansions possible.
436s <suppressed ~49 debug messages>
436s 
436s 2.37. Executing OPT_EXPR pass (perform const folding).
436s Optimizing module top.
436s 
436s 2.38. Executing SIMPLEMAP pass (map simple cells to gate primitives).
436s Mapping top.$auto$alumacc.cc:485:replace_alu$460.slice[0].carry ($lut).
436s 
436s 2.39. Executing ICE40_OPT pass (performing simple optimizations).
436s 
436s 2.39.1. Running ICE40 specific optimizations.
436s 
436s 2.39.2. Executing OPT_EXPR pass (perform const folding).
436s Optimizing module top.
436s <suppressed ~14 debug messages>
436s 
436s 2.39.3. Executing OPT_MERGE pass (detect identical cells).
436s Finding identical cells in module `\top'.
436s Removed a total of 0 cells.
436s 
436s 2.39.4. Executing OPT_DFF pass (perform DFF optimizations).
436s 
436s 2.39.5. Executing OPT_CLEAN pass (remove unused cells and wires).
436s Finding unused cells or wires in module \top..
436s Removed 0 unused cells and 112 unused wires.
436s <suppressed ~1 debug messages>
436s 
436s 2.39.6. Rerunning OPT passes. (Removed registers in this run.)
436s 
436s 2.39.7. Running ICE40 specific optimizations.
436s 
436s 2.39.8. Executing OPT_EXPR pass (perform const folding).
436s Optimizing module top.
436s 
436s 2.39.9. Executing OPT_MERGE pass (detect identical cells).
436s Finding identical cells in module `\top'.
436s Removed a total of 0 cells.
436s 
436s 2.39.10. Executing OPT_DFF pass (perform DFF optimizations).
436s 
436s 2.39.11. Executing OPT_CLEAN pass (remove unused cells and wires).
436s Finding unused cells or wires in module \top..
436s 
436s 2.39.12. Finished OPT passes. (There is nothing left to do.)
436s 
436s 2.40. Executing TECHMAP pass (map to technology primitives).
436s 
436s 2.40.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v
436s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation.
436s Generating RTLIL representation for module `\$_DLATCH_N_'.
436s Generating RTLIL representation for module `\$_DLATCH_P_'.
436s Successfully finished Verilog frontend.
436s 
436s 2.40.2. Continuing TECHMAP pass.
436s No more expansions possible.
436s <suppressed ~4 debug messages>
436s 
436s 2.41. Executing ABC pass (technology mapping using ABC).
436s 
436s 2.41.1. Extracting gate netlist of module `\top' to `<abc-temp-dir>/input.blif'..
436s Extracted 27 gates and 54 wires to a netlist network with 27 inputs and 4 outputs.
436s 
436s 2.41.1.1. Executing ABC.
436s Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
436s ABC: ABC command line: "source <abc-temp-dir>/abc.script".
436s ABC: 
436s ABC: + read_blif <abc-temp-dir>/input.blif 
436s ABC: + read_lut <abc-temp-dir>/lutdefs.txt 
436s ABC: + strash 
436s ABC: + &get -n 
436s ABC: + &fraig -x 
436s ABC: + &put 
436s ABC: + scorr 
436s ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
436s ABC: + dc2 
436s ABC: + dretime 
436s ABC: + strash 
436s ABC: + dch -f 
436s ABC: + if 
436s ABC: + mfs2 
436s ABC: + lutpack -S 1 
436s ABC: + dress <abc-temp-dir>/input.blif 
436s ABC: Total number of equiv classes                =       5.
436s ABC: Participating nodes from both networks       =       9.
436s ABC: Participating nodes from the first network   =       4. (  33.33 % of nodes)
436s ABC: Participating nodes from the second network  =       5. (  41.67 % of nodes)
436s ABC: Node pairs (any polarity)                    =       4. (  33.33 % of names can be moved)
436s ABC: Node pairs (same polarity)                   =       4. (  33.33 % of names can be moved)
436s ABC: Total runtime =     0.04 sec
436s ABC: + write_blif <abc-temp-dir>/output.blif 
436s 
436s 2.41.1.2. Re-integrating ABC results.
436s ABC RESULTS:              $lut cells:       11
436s ABC RESULTS:        internal signals:       23
436s ABC RESULTS:           input signals:       27
436s ABC RESULTS:          output signals:        4
436s Removing temp directory.
436s 
436s 2.42. Executing ICE40_WRAPCARRY pass (wrap carries).
436s 
436s 2.43. Executing TECHMAP pass (map to technology primitives).
436s 
436s 2.43.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v
436s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation.
436s Generating RTLIL representation for module `\$_DFF_N_'.
436s Generating RTLIL representation for module `\$_DFF_P_'.
436s Generating RTLIL representation for module `\$_DFFE_NP_'.
436s Generating RTLIL representation for module `\$_DFFE_PP_'.
436s Generating RTLIL representation for module `\$_DFF_NP0_'.
436s Generating RTLIL representation for module `\$_DFF_NP1_'.
436s Generating RTLIL representation for module `\$_DFF_PP0_'.
436s Generating RTLIL representation for module `\$_DFF_PP1_'.
436s Generating RTLIL representation for module `\$_DFFE_NP0P_'.
436s Generating RTLIL representation for module `\$_DFFE_NP1P_'.
436s Generating RTLIL representation for module `\$_DFFE_PP0P_'.
436s Generating RTLIL representation for module `\$_DFFE_PP1P_'.
436s Generating RTLIL representation for module `\$_SDFF_NP0_'.
436s Generating RTLIL representation for module `\$_SDFF_NP1_'.
436s Generating RTLIL representation for module `\$_SDFF_PP0_'.
436s Generating RTLIL representation for module `\$_SDFF_PP1_'.
436s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
436s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
436s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
436s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
436s Successfully finished Verilog frontend.
436s 
436s 2.43.2. Continuing TECHMAP pass.
436s No more expansions possible.
436s <suppressed ~22 debug messages>
436s Removed 2 unused cells and 39 unused wires.
436s 
436s 2.44. Executing OPT_LUT pass (optimize LUTs).
436s Discovering LUTs.
436s Number of LUTs:       36
436s   1-LUT                1
436s   2-LUT                3
436s   3-LUT               25
436s   4-LUT                7
436s   with \SB_CARRY    (#0)   23
436s   with \SB_CARRY    (#1)   23
436s 
436s Eliminating LUTs.
436s Number of LUTs:       36
436s   1-LUT                1
436s   2-LUT                3
436s   3-LUT               25
436s   4-LUT                7
436s   with \SB_CARRY    (#0)   23
436s   with \SB_CARRY    (#1)   23
436s 
436s Combining LUTs.
436s Number of LUTs:       36
436s   1-LUT                1
436s   2-LUT                3
436s   3-LUT               25
436s   4-LUT                7
436s   with \SB_CARRY    (#0)   23
436s   with \SB_CARRY    (#1)   23
436s 
436s Eliminated 0 LUTs.
436s Combined 0 LUTs.
436s <suppressed ~165 debug messages>
436s 
436s 2.45. Executing TECHMAP pass (map to technology primitives).
436s 
436s 2.45.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v
436s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation.
436s Generating RTLIL representation for module `\$lut'.
436s Successfully finished Verilog frontend.
436s 
436s 2.45.2. Continuing TECHMAP pass.
436s Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut.
436s Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut.
436s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut.
436s Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut.
436s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
436s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111000 for cells of type $lut.
436s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
436s No more expansions possible.
436s <suppressed ~130 debug messages>
436s Removed 0 unused cells and 76 unused wires.
436s 
436s 2.46. Executing AUTONAME pass.
436s Renamed 723 objects in module top (15 iterations).
436s <suppressed ~96 debug messages>
436s 
436s 2.47. Executing HIERARCHY pass (managing design hierarchy).
436s 
436s 2.47.1. Analyzing design hierarchy..
436s Top module:  \top
436s 
436s 2.47.2. Analyzing design hierarchy..
436s Top module:  \top
436s Removed 0 unused modules.
436s 
436s 2.48. Printing statistics.
436s 
436s === top ===
436s 
436s    Number of wires:                 19
436s    Number of wire bits:             97
436s    Number of public wires:          19
436s    Number of public wire bits:      97
436s    Number of memories:               0
436s    Number of memory bits:            0
436s    Number of processes:              0
436s    Number of cells:                 87
436s      SB_CARRY                       23
436s      SB_DFF                         27
436s      SB_LUT4                        36
436s      SB_WARMBOOT                     1
436s 
436s 2.49. Executing CHECK pass (checking for obvious problems).
436s Checking module top...
436s Found and reported 0 problems.
436s 
436s 2.50. Executing JSON backend.
436s 
436s End of script. Logfile hash: 6ef4de1f27, CPU: user 0.97s system 0.01s, MEM: 20.00 MB peak
436s Yosys 0.33 (git sha1 2584903a060)
436s Time spent: 60% 13x read_verilog (0 sec), 9% 1x abc (0 sec), ...
436s nextpnr-ice40 --hx1k --package tq144 --asc app3.asc --pcf icestick.pcf --json app3.json
436s Warning: unmatched constraint 'RX' (on line 4)
436s Warning: unmatched constraint 'TX' (on line 5)
436s Info: constrained 'LED1' to bel 'X13/Y12/io1'
436s Info: constrained 'LED2' to bel 'X13/Y12/io0'
436s Info: constrained 'LED3' to bel 'X13/Y11/io1'
436s Info: constrained 'LED4' to bel 'X13/Y11/io0'
436s Info: constrained 'LED5' to bel 'X13/Y9/io1'
436s Info: constrained 'clk' to bel 'X0/Y8/io1'
436s 
436s Info: Packing constants..
436s Info: Packing IOs..
436s Info: Packing LUT-FFs..
436s Info:        9 LCs used as LUT4 only
436s Info:       27 LCs used as LUT4 and DFF
436s Info: Packing non-LUT FFs..
436s Info:        0 LCs used as DFF only
436s Info: Packing carries..
436s Info:        0 LCs used as CARRY only
436s Info: Packing indirect carry+LUT pairs...
436s Info:        0 LUTs merged into carry LCs
436s Info: Packing RAMs..
436s Info: Placing PLLs..
436s Info: Packing special functions..
436s Info: Packing PLLs..
436s Info: Promoting globals..
436s Info: promoting clk$SB_IO_IN (fanout 27)
436s Info: Constraining chains...
436s Info:        1 LCs used to legalise carry chains.
436s Info: Checksum: 0x3db9abae
436s 
436s Info: Annotating ports with timing budgets for target frequency 12.00 MHz
436s Info: Checksum: 0xec80ad62
436s 
436s Info: Device utilisation:
436s Info: 	         ICESTORM_LC:    39/ 1280     3%
436s Info: 	        ICESTORM_RAM:     0/   16     0%
436s Info: 	               SB_IO:     6/  112     5%
436s Info: 	               SB_GB:     1/    8    12%
436s Info: 	        ICESTORM_PLL:     0/    1     0%
436s Info: 	         SB_WARMBOOT:     1/    1   100%
436s 
436s Info: Placed 6 cells based on constraints.
436s Info: Creating initial analytic placement for 17 cells, random placement wirelen = 345.
436s Info:     at initial placer iter 0, wirelen = 9
436s Info:     at initial placer iter 1, wirelen = 9
436s Info:     at initial placer iter 2, wirelen = 9
436s Info:     at initial placer iter 3, wirelen = 9
436s Info: Running main analytical placer, max placement attempts per cell = 10000.
436s Info:     at iteration #1, type ICESTORM_LC: wirelen solved = 12, spread = 83, legal = 100; time = 0.00s
436s Info:     at iteration #1, type SB_GB: wirelen solved = 100, spread = 100, legal = 100; time = 0.00s
436s Info:     at iteration #1, type SB_WARMBOOT: wirelen solved = 99, spread = 99, legal = 145; time = 0.00s
436s Info:     at iteration #1, type ALL: wirelen solved = 9, spread = 86, legal = 143; time = 0.00s
436s Info:     at iteration #2, type ICESTORM_LC: wirelen solved = 65, spread = 98, legal = 118; time = 0.00s
436s Info:     at iteration #2, type SB_GB: wirelen solved = 118, spread = 118, legal = 118; time = 0.00s
436s Info:     at iteration #2, type SB_WARMBOOT: wirelen solved = 80, spread = 80, legal = 118; time = 0.00s
437s Info:     at iteration #2, type ALL: wirelen solved = 13, spread = 63, legal = 109; time = 0.00s
437s Info:     at iteration #3, type ICESTORM_LC: wirelen solved = 63, spread = 107, legal = 119; time = 0.00s
437s Info:     at iteration #3, type SB_GB: wirelen solved = 119, spread = 119, legal = 119; time = 0.00s
437s Info:     at iteration #3, type SB_WARMBOOT: wirelen solved = 77, spread = 77, legal = 119; time = 0.00s
437s Info:     at iteration #3, type ALL: wirelen solved = 18, spread = 66, legal = 110; time = 0.00s
437s Info:     at iteration #4, type ICESTORM_LC: wirelen solved = 62, spread = 106, legal = 116; time = 0.00s
437s Info:     at iteration #4, type SB_GB: wirelen solved = 116, spread = 116, legal = 116; time = 0.00s
437s Info:     at iteration #4, type SB_WARMBOOT: wirelen solved = 76, spread = 76, legal = 116; time = 0.00s
437s Info:     at iteration #4, type ALL: wirelen solved = 23, spread = 66, legal = 110; time = 0.00s
437s Info:     at iteration #5, type ICESTORM_LC: wirelen solved = 62, spread = 105, legal = 113; time = 0.00s
437s Info:     at iteration #5, type SB_GB: wirelen solved = 113, spread = 113, legal = 113; time = 0.00s
437s Info:     at iteration #5, type SB_WARMBOOT: wirelen solved = 73, spread = 73, legal = 113; time = 0.00s
437s Info:     at iteration #5, type ALL: wirelen solved = 21, spread = 68, legal = 110; time = 0.00s
437s Info:     at iteration #6, type ICESTORM_LC: wirelen solved = 63, spread = 105, legal = 110; time = 0.00s
437s Info:     at iteration #6, type SB_GB: wirelen solved = 110, spread = 110, legal = 110; time = 0.00s
437s Info:     at iteration #6, type SB_WARMBOOT: wirelen solved = 70, spread = 70, legal = 110; time = 0.00s
437s Info:     at iteration #6, type ALL: wirelen solved = 28, spread = 69, legal = 111; time = 0.00s
437s Info:     at iteration #7, type ICESTORM_LC: wirelen solved = 63, spread = 106, legal = 109; time = 0.00s
437s Info:     at iteration #7, type SB_GB: wirelen solved = 109, spread = 109, legal = 109; time = 0.00s
437s Info:     at iteration #7, type SB_WARMBOOT: wirelen solved = 71, spread = 71, legal = 109; time = 0.00s
437s Info:     at iteration #7, type ALL: wirelen solved = 32, spread = 74, legal = 112; time = 0.00s
437s Info: HeAP Placer Time: 0.02s
437s Info:   of which solving equations: 0.01s
437s Info:   of which spreading cells: 0.00s
437s Info:   of which strict legalisation: 0.00s
437s 
437s Info: Running simulated annealing placer for refinement.
437s Info:   at iteration #1: temp = 0.000000, timing cost = 12, wirelen = 109
437s Info:   at iteration #5: temp = 0.000000, timing cost = 16, wirelen = 86
437s Info:   at iteration #10: temp = 0.000000, timing cost = 16, wirelen = 80
437s Info:   at iteration #11: temp = 0.000000, timing cost = 16, wirelen = 80 
437s Info: SA placement time 0.01s
437s 
437s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 191.98 MHz (PASS at 12.00 MHz)
437s 
437s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> <async>: 4.14 ns
437s 
437s Info: Slack histogram:
437s Info:  legend: * represents 1 endpoint(s)
437s Info:          + represents [1,1) endpoint(s)
437s Info: [ 78124,  78329) |** 
437s Info: [ 78329,  78534) |*** 
437s Info: [ 78534,  78739) |** 
437s Info: [ 78739,  78944) |*** 
437s Info: [ 78944,  79149) | 
437s Info: [ 79149,  79354) |** 
437s Info: [ 79354,  79559) |* 
437s Info: [ 79559,  79764) |*** 
437s Info: [ 79764,  79969) |*** 
437s Info: [ 79969,  80174) |** 
437s Info: [ 80174,  80379) | 
437s Info: [ 80379,  80584) | 
437s Info: [ 80584,  80789) |** 
437s Info: [ 80789,  80994) |** 
437s Info: [ 80994,  81199) |* 
437s Info: [ 81199,  81404) |* 
437s Info: [ 81404,  81609) | 
437s Info: [ 81609,  81814) |************************* 
437s Info: [ 81814,  82019) |*** 
437s Info: [ 82019,  82224) |* 
437s Info: Checksum: 0x1fc97255
437s 
437s Info: Routing..
437s Info: Setting up routing queue.
437s Info: Routing 125 arcs.
437s Info:            |   (re-)routed arcs  |   delta    | remaining|       time spent     |
437s Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|
437s Info:        130 |        5        105 |    5   105 |         0|       0.01       0.01|
437s Info: Routing complete.
437s Info: Router1 time 0.01s
437s Info: Checksum: 0x3cac2d4b
437s 
437s Info: Critical path report for clock 'clk$SB_IO_IN_$glb_clk' (posedge -> posedge):
437s Info: curr total
437s Info:  0.5  0.5  Source counter_SB_LUT4_I2_20_LC.O
437s Info:  0.6  1.1    Net counter[10] budget 20.291000 ns (11,10) -> (12,10)
437s Info:                Sink state_SB_LUT4_I3_I1_SB_LUT4_O_I0_SB_LUT4_O_3_LC.I0
437s Info:                Defined in:
437s Info:                  app3.v:7.22-7.29
437s Info:  0.4  1.6  Source state_SB_LUT4_I3_I1_SB_LUT4_O_I0_SB_LUT4_O_3_LC.O
437s Info:  0.6  2.2    Net state_SB_LUT4_I3_I1_SB_LUT4_O_I0[0] budget 20.291000 ns (12,10) -> (12,10)
437s Info:                Sink state_SB_LUT4_I3_I1_SB_LUT4_O_LC.I0
437s Info:                Defined in:
437s Info:                  /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
437s Info:  0.4  2.6  Source state_SB_LUT4_I3_I1_SB_LUT4_O_LC.O
437s Info:  0.6  3.2    Net state_SB_LUT4_I3_I1[1] budget 20.291000 ns (12,10) -> (12,10)
437s Info:                Sink counter2_SB_DFF_Q_D_SB_LUT4_O_3_I1_SB_LUT4_O_LC.I3
437s Info:                Defined in:
437s Info:                  /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
437s Info:  0.3  3.5  Source counter2_SB_DFF_Q_D_SB_LUT4_O_3_I1_SB_LUT4_O_LC.O
437s Info:  0.6  4.1    Net counter2_SB_DFF_Q_D_SB_LUT4_O_3_I1 budget 20.290001 ns (12,10) -> (12,11)
437s Info:                Sink counter2_SB_DFF_Q_D_SB_LUT4_O_3_LC.I1
437s Info:                Defined in:
437s Info:                  app3.v:13.15-13.34
437s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:29.22-29.23
437s Info:  0.3  4.4  Source counter2_SB_DFF_Q_D_SB_LUT4_O_3_LC.COUT
437s Info:  0.0  4.4    Net counter2_SB_DFF_Q_D_SB_LUT4_O_3_I1_SB_CARRY_I0_CO[1] budget 0.000000 ns (12,11) -> (12,11)
437s Info:                Sink counter2_SB_DFF_Q_D_SB_LUT4_O_2_LC.CIN
437s Info:                Defined in:
437s Info:                  app3.v:13.15-13.34
437s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
437s Info:  0.1  4.5  Source counter2_SB_DFF_Q_D_SB_LUT4_O_2_LC.COUT
437s Info:  0.0  4.5    Net counter2_SB_DFF_Q_D_SB_LUT4_O_3_I1_SB_CARRY_I0_CO[2] budget 0.000000 ns (12,11) -> (12,11)
437s Info:                Sink counter2_SB_DFF_Q_D_SB_LUT4_O_1_LC.CIN
437s Info:                Defined in:
437s Info:                  app3.v:13.15-13.34
437s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
437s Info:  0.1  4.6  Source counter2_SB_DFF_Q_D_SB_LUT4_O_1_LC.COUT
437s Info:  0.3  4.9    Net counter2_SB_DFF_Q_D_SB_LUT4_O_3_I1_SB_CARRY_I0_CO[3] budget 0.260000 ns (12,11) -> (12,11)
437s Info:                Sink counter2_SB_DFF_Q_D_SB_LUT4_O_LC.I3
437s Info:                Defined in:
437s Info:                  app3.v:13.15-13.34
437s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
437s Info:  0.3  5.2  Setup counter2_SB_DFF_Q_D_SB_LUT4_O_LC.I3
437s Info: 2.6 ns logic, 2.6 ns routing
437s 
437s Info: Critical path report for cross-domain path 'posedge clk$SB_IO_IN_$glb_clk' -> '<async>':
437s Info: curr total
437s Info:  0.5  0.5  Source counter2_SB_DFF_Q_D_SB_LUT4_O_3_LC.O
437s Info:  0.6  1.1    Net counter2[0] budget 41.173000 ns (12,11) -> (12,11)
437s Info:                Sink WB_BOOT_SB_LUT4_O_LC.I0
437s Info:                Defined in:
437s Info:                  app3.v:8.12-8.20
437s Info:  0.4  1.6  Source WB_BOOT_SB_LUT4_O_LC.O
437s Info:  1.4  3.0    Net WB_BOOT budget 41.172001 ns (12,11) -> (0,0)
437s Info:                Sink WB.BOOT
437s Info:                Defined in:
437s Info:                  app3.v:24.9-24.18
437s Info: 1.0 ns logic, 2.0 ns routing
437s 
437s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 191.98 MHz (PASS at 12.00 MHz)
437s 
437s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> <async>: 3.02 ns
437s 
437s Info: Slack histogram:
437s Info:  legend: * represents 1 endpoint(s)
437s Info:          + represents [1,1) endpoint(s)
437s Info: [ 78124,  78329) |** 
437s Info: [ 78329,  78534) |** 
437s Info: [ 78534,  78739) |** 
437s Info: [ 78739,  78944) |*** 
437s Info: [ 78944,  79149) |* 
437s Info: [ 79149,  79354) | 
437s Info: [ 79354,  79559) |** 
437s Info: [ 79559,  79764) |** 
437s Info: [ 79764,  79969) |*** 
437s Info: [ 79969,  80174) |*** 
437s Info: [ 80174,  80379) |* 
437s Info: [ 80379,  80584) | 
437s Info: [ 80584,  80789) |** 
437s Info: [ 80789,  80994) |** 
437s Info: [ 80994,  81199) |* 
437s Info: [ 81199,  81404) |* 
437s Info: [ 81404,  81609) | 
437s Info: [ 81609,  81814) |************************* 
437s Info: [ 81814,  82019) |*** 
437s Info: [ 82019,  82224) |* 
437s 2 warnings, 0 errors
437s 
437s Info: Program finished normally.
437s icetime -d hx1k -c 25 app3.asc
437s // Reading input .asc file..
437s // Reading 1k chipdb file..
437s // Creating timing netlist..
437s // Timing estimate: 5.25 ns (190.30 MHz)
437s // Checking 40.00 ns (25.00 MHz) clock constraint: PASSED.
437s icepack app3.asc app3.bin
437s Place image 0 at 010000 .. 020000 (`app0.bin')
437s Place image 1 at 020000 .. 030000 (`app1.bin')
437s Place image 2 at 030000 .. 040000 (`app2.bin')
437s Place image 3 at 040000 .. 050000 (`app3.bin')
437s icemulti -v -A16 -p0 -o config.bin app0.bin app1.bin app2.bin app3.bin
437s make: Leaving directory '/tmp/autopkgtest.eGJMaA/build.OQp/src/examples/icemulti'
437s make: Entering directory '/tmp/autopkgtest.eGJMaA/build.OQp/src/examples/icestick'
437s yosys -p 'synth_ice40 -top top -json example.json' example.v
437s 
437s  /----------------------------------------------------------------------------\
437s  |                                                                            |
437s  |  yosys -- Yosys Open SYnthesis Suite                                       |
437s  |                                                                            |
437s  |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
437s  |                                                                            |
437s  |  Permission to use, copy, modify, and/or distribute this software for any  |
437s  |  purpose with or without fee is hereby granted, provided that the above    |
437s  |  copyright notice and this permission notice appear in all copies.         |
437s  |                                                                            |
437s  |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
437s  |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
437s  |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
437s  |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
437s  |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
437s  |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
437s  |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
437s  |                                                                            |
437s  \----------------------------------------------------------------------------/
437s 
437s  Yosys 0.33 (git sha1 2584903a060)
437s 
437s 
437s -- Parsing `example.v' using frontend ` -vlog2k' --
437s 
437s 1. Executing Verilog-2005 frontend: example.v
437s Parsing Verilog input from `example.v' to AST representation.
437s Storing AST representation for module `$abstract\top'.
437s Successfully finished Verilog frontend.
437s 
437s -- Running command `synth_ice40 -top top -json example.json' --
437s 
437s 2. Executing SYNTH_ICE40 pass.
437s 
437s 2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v
437s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation.
437s Generating RTLIL representation for module `\SB_IO'.
437s Generating RTLIL representation for module `\SB_GB_IO'.
437s Generating RTLIL representation for module `\SB_GB'.
437s Generating RTLIL representation for module `\SB_LUT4'.
437s Generating RTLIL representation for module `\SB_CARRY'.
437s Generating RTLIL representation for module `\SB_DFF'.
437s Generating RTLIL representation for module `\SB_DFFE'.
437s Generating RTLIL representation for module `\SB_DFFSR'.
437s Generating RTLIL representation for module `\SB_DFFR'.
437s Generating RTLIL representation for module `\SB_DFFSS'.
437s Generating RTLIL representation for module `\SB_DFFS'.
437s Generating RTLIL representation for module `\SB_DFFESR'.
437s Generating RTLIL representation for module `\SB_DFFER'.
437s Generating RTLIL representation for module `\SB_DFFESS'.
437s Generating RTLIL representation for module `\SB_DFFES'.
437s Generating RTLIL representation for module `\SB_DFFN'.
437s Generating RTLIL representation for module `\SB_DFFNE'.
437s Generating RTLIL representation for module `\SB_DFFNSR'.
437s Generating RTLIL representation for module `\SB_DFFNR'.
437s Generating RTLIL representation for module `\SB_DFFNSS'.
437s Generating RTLIL representation for module `\SB_DFFNS'.
437s Generating RTLIL representation for module `\SB_DFFNESR'.
437s Generating RTLIL representation for module `\SB_DFFNER'.
437s Generating RTLIL representation for module `\SB_DFFNESS'.
437s Generating RTLIL representation for module `\SB_DFFNES'.
437s Generating RTLIL representation for module `\SB_RAM40_4K'.
437s Generating RTLIL representation for module `\SB_RAM40_4KNR'.
437s Generating RTLIL representation for module `\SB_RAM40_4KNW'.
437s Generating RTLIL representation for module `\SB_RAM40_4KNRNW'.
437s Generating RTLIL representation for module `\ICESTORM_LC'.
437s Generating RTLIL representation for module `\SB_PLL40_CORE'.
437s Generating RTLIL representation for module `\SB_PLL40_PAD'.
437s Generating RTLIL representation for module `\SB_PLL40_2_PAD'.
437s Generating RTLIL representation for module `\SB_PLL40_2F_CORE'.
437s Generating RTLIL representation for module `\SB_PLL40_2F_PAD'.
437s Generating RTLIL representation for module `\SB_WARMBOOT'.
437s Generating RTLIL representation for module `\SB_SPRAM256KA'.
437s Generating RTLIL representation for module `\SB_HFOSC'.
437s Generating RTLIL representation for module `\SB_LFOSC'.
437s Generating RTLIL representation for module `\SB_RGBA_DRV'.
437s Generating RTLIL representation for module `\SB_LED_DRV_CUR'.
437s Generating RTLIL representation for module `\SB_RGB_DRV'.
437s Generating RTLIL representation for module `\SB_I2C'.
437s Generating RTLIL representation for module `\SB_SPI'.
437s Generating RTLIL representation for module `\SB_LEDDA_IP'.
437s Generating RTLIL representation for module `\SB_FILTER_50NS'.
437s Generating RTLIL representation for module `\SB_IO_I3C'.
437s Generating RTLIL representation for module `\SB_IO_OD'.
437s Generating RTLIL representation for module `\SB_MAC16'.
437s Generating RTLIL representation for module `\ICESTORM_RAM'.
437s Successfully finished Verilog frontend.
437s 
437s 2.2. Executing HIERARCHY pass (managing design hierarchy).
437s 
437s 2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\top'.
437s Generating RTLIL representation for module `\top'.
437s 
437s 2.3.1. Analyzing design hierarchy..
437s Top module:  \top
437s 
437s 2.3.2. Analyzing design hierarchy..
437s Top module:  \top
437s Removing unused module `$abstract\top'.
437s Removed 1 unused modules.
437s 
437s 2.4. Executing PROC pass (convert processes to netlists).
437s 
437s 2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
437s Cleaned up 0 empty switches.
437s 
437s 2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
437s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241 in module SB_DFFNES.
437s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234 in module SB_DFFNESS.
437s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230 in module SB_DFFNER.
437s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223 in module SB_DFFNESR.
437s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220 in module SB_DFFNS.
437s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217 in module SB_DFFNSS.
437s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214 in module SB_DFFNR.
437s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211 in module SB_DFFNSR.
437s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203 in module SB_DFFES.
437s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196 in module SB_DFFESS.
437s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192 in module SB_DFFER.
437s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185 in module SB_DFFESR.
437s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182 in module SB_DFFS.
437s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179 in module SB_DFFSS.
437s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176 in module SB_DFFR.
437s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173 in module SB_DFFSR.
437s Removed a total of 0 dead cases.
437s 
437s 2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
437s Removed 8 redundant assignments.
437s Promoted 25 assignments to connections.
437s 
437s 2.4.4. Executing PROC_INIT pass (extract init attributes).
437s Found init rule in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'.
437s   Set init value: \Q = 1'0
437s Found init rule in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'.
437s   Set init value: \Q = 1'0
437s Found init rule in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'.
437s   Set init value: \Q = 1'0
437s Found init rule in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'.
437s   Set init value: \Q = 1'0
437s Found init rule in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'.
437s   Set init value: \Q = 1'0
437s Found init rule in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'.
437s   Set init value: \Q = 1'0
437s Found init rule in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'.
437s   Set init value: \Q = 1'0
437s Found init rule in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'.
437s   Set init value: \Q = 1'0
437s Found init rule in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'.
437s   Set init value: \Q = 1'0
437s Found init rule in `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'.
437s   Set init value: \Q = 1'0
437s Found init rule in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'.
437s   Set init value: \Q = 1'0
437s Found init rule in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'.
437s   Set init value: \Q = 1'0
437s Found init rule in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'.
437s   Set init value: \Q = 1'0
437s Found init rule in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'.
437s   Set init value: \Q = 1'0
437s Found init rule in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'.
437s   Set init value: \Q = 1'0
437s Found init rule in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'.
437s   Set init value: \Q = 1'0
437s Found init rule in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'.
437s   Set init value: \Q = 1'0
437s Found init rule in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'.
437s   Set init value: \Q = 1'0
437s Found init rule in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'.
437s   Set init value: \Q = 1'0
437s Found init rule in `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'.
437s   Set init value: \Q = 1'0
437s Found init rule in `\top.$proc$example.v:13$386'.
437s   Set init value: \counter = 27'000000000000000000000000000
437s 
437s 2.4.5. Executing PROC_ARST pass (detect async resets in processes).
437s Found async reset \S in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
437s Found async reset \R in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
437s Found async reset \S in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
437s Found async reset \R in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
437s Found async reset \S in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
437s Found async reset \R in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
437s Found async reset \S in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'.
437s Found async reset \R in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'.
437s 
437s 2.4.6. Executing PROC_ROM pass (convert switches to ROMs).
437s Converted 0 switches.
437s <suppressed ~18 debug messages>
437s 
437s 2.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
437s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'.
437s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
437s      1/1: $0\Q[0:0]
437s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'.
437s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
437s      1/1: $0\Q[0:0]
437s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'.
437s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
437s      1/1: $0\Q[0:0]
437s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'.
437s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
437s      1/1: $0\Q[0:0]
437s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'.
437s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
437s      1/1: $0\Q[0:0]
437s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'.
437s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
437s      1/1: $0\Q[0:0]
437s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'.
437s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
437s      1/1: $0\Q[0:0]
437s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'.
437s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'.
437s      1/1: $0\Q[0:0]
437s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'.
437s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'.
437s      1/1: $0\Q[0:0]
437s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'.
437s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'.
437s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'.
437s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
437s      1/1: $0\Q[0:0]
437s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'.
437s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'.
437s      1/1: $0\Q[0:0]
437s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'.
437s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
437s      1/1: $0\Q[0:0]
437s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'.
437s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'.
437s      1/1: $0\Q[0:0]
437s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'.
437s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'.
437s      1/1: $0\Q[0:0]
437s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'.
437s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'.
437s      1/1: $0\Q[0:0]
437s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'.
437s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'.
437s      1/1: $0\Q[0:0]
437s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'.
437s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'.
437s      1/1: $0\Q[0:0]
437s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'.
437s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'.
437s      1/1: $0\Q[0:0]
437s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'.
437s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'.
437s Creating decoders for process `\top.$proc$example.v:13$386'.
437s Creating decoders for process `\top.$proc$example.v:16$381'.
437s 
437s 2.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
437s 
437s 2.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
437s Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
437s   created $adff cell `$procdff$431' with negative edge clock and positive level reset.
437s Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
437s   created $dff cell `$procdff$432' with negative edge clock.
437s Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
437s   created $adff cell `$procdff$433' with negative edge clock and positive level reset.
437s Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
437s   created $dff cell `$procdff$434' with negative edge clock.
437s Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
437s   created $adff cell `$procdff$435' with negative edge clock and positive level reset.
437s Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
437s   created $dff cell `$procdff$436' with negative edge clock.
437s Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
437s   created $adff cell `$procdff$437' with negative edge clock and positive level reset.
437s Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'.
437s   created $dff cell `$procdff$438' with negative edge clock.
437s Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'.
437s   created $dff cell `$procdff$439' with negative edge clock.
437s Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'.
437s   created $dff cell `$procdff$440' with negative edge clock.
437s Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
437s   created $adff cell `$procdff$441' with positive edge clock and positive level reset.
437s Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'.
437s   created $dff cell `$procdff$442' with positive edge clock.
437s Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
437s   created $adff cell `$procdff$443' with positive edge clock and positive level reset.
437s Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'.
437s   created $dff cell `$procdff$444' with positive edge clock.
437s Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'.
437s   created $adff cell `$procdff$445' with positive edge clock and positive level reset.
437s Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'.
437s   created $dff cell `$procdff$446' with positive edge clock.
437s Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'.
437s   created $adff cell `$procdff$447' with positive edge clock and positive level reset.
437s Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'.
437s   created $dff cell `$procdff$448' with positive edge clock.
437s Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'.
437s   created $dff cell `$procdff$449' with positive edge clock.
437s Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'.
437s   created $dff cell `$procdff$450' with positive edge clock.
437s Creating register for signal `\top.\counter' using process `\top.$proc$example.v:16$381'.
437s   created $dff cell `$procdff$451' with positive edge clock.
437s Creating register for signal `\top.\outcnt' using process `\top.$proc$example.v:16$381'.
437s   created $dff cell `$procdff$452' with positive edge clock.
437s 
437s 2.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
437s 
437s 2.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
437s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'.
437s Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
437s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
437s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'.
437s Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
437s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
437s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'.
437s Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
437s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
437s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'.
437s Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
437s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
437s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'.
437s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
437s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'.
437s Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
437s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
437s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'.
437s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
437s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'.
437s Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'.
437s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'.
437s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'.
437s Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'.
437s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'.
437s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'.
437s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'.
437s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'.
437s Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
437s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
437s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'.
437s Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'.
437s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'.
437s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'.
437s Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
437s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
437s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'.
437s Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'.
437s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'.
437s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'.
437s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'.
437s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'.
437s Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'.
437s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'.
437s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'.
437s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'.
437s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'.
437s Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'.
437s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'.
437s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'.
437s Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'.
437s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'.
437s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'.
437s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'.
437s Removing empty process `top.$proc$example.v:13$386'.
437s Removing empty process `top.$proc$example.v:16$381'.
437s Cleaned up 18 empty switches.
437s 
437s 2.4.12. Executing OPT_EXPR pass (perform const folding).
437s Optimizing module top.
437s <suppressed ~2 debug messages>
437s 
437s 2.5. Executing FLATTEN pass (flatten design).
437s 
437s 2.6. Executing TRIBUF pass.
437s 
437s 2.7. Executing DEMINOUT pass (demote inout ports to input or output).
437s 
437s 2.8. Executing OPT_EXPR pass (perform const folding).
437s Optimizing module top.
437s 
437s 2.9. Executing OPT_CLEAN pass (remove unused cells and wires).
437s Finding unused cells or wires in module \top..
437s Removed 0 unused cells and 5 unused wires.
437s <suppressed ~1 debug messages>
437s 
437s 2.10. Executing CHECK pass (checking for obvious problems).
437s Checking module top...
437s Found and reported 0 problems.
437s 
437s 2.11. Executing OPT pass (performing simple optimizations).
437s 
437s 2.11.1. Executing OPT_EXPR pass (perform const folding).
437s Optimizing module top.
437s 
437s 2.11.2. Executing OPT_MERGE pass (detect identical cells).
437s Finding identical cells in module `\top'.
437s Removed a total of 0 cells.
437s 
437s 2.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
437s Running muxtree optimizer on module \top..
437s   Creating internal representation of mux trees.
437s   No muxes found in this module.
437s Removed 0 multiplexer ports.
437s 
437s 2.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
437s   Optimizing cells in module \top.
437s Performed a total of 0 changes.
437s 
437s 2.11.5. Executing OPT_MERGE pass (detect identical cells).
437s Finding identical cells in module `\top'.
437s Removed a total of 0 cells.
437s 
437s 2.11.6. Executing OPT_DFF pass (perform DFF optimizations).
437s 
437s 2.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
437s Finding unused cells or wires in module \top..
437s 
437s 2.11.8. Executing OPT_EXPR pass (perform const folding).
437s Optimizing module top.
437s 
437s 2.11.9. Finished OPT passes. (There is nothing left to do.)
437s 
437s 2.12. Executing FSM pass (extract and optimize FSM).
437s 
437s 2.12.1. Executing FSM_DETECT pass (finding FSMs in design).
437s 
437s 2.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).
437s 
437s 2.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).
437s 
437s 2.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
437s Finding unused cells or wires in module \top..
437s 
437s 2.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).
437s 
437s 2.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
437s 
437s 2.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
437s 
437s 2.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
437s 
437s 2.13. Executing OPT pass (performing simple optimizations).
437s 
437s 2.13.1. Executing OPT_EXPR pass (perform const folding).
437s Optimizing module top.
437s 
437s 2.13.2. Executing OPT_MERGE pass (detect identical cells).
437s Finding identical cells in module `\top'.
437s Removed a total of 0 cells.
437s 
437s 2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
437s Running muxtree optimizer on module \top..
437s   Creating internal representation of mux trees.
437s   No muxes found in this module.
437s Removed 0 multiplexer ports.
437s 
437s 2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
437s   Optimizing cells in module \top.
437s Performed a total of 0 changes.
437s 
437s 2.13.5. Executing OPT_MERGE pass (detect identical cells).
437s Finding identical cells in module `\top'.
437s Removed a total of 0 cells.
437s 
437s 2.13.6. Executing OPT_DFF pass (perform DFF optimizations).
437s 
437s 2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
437s Finding unused cells or wires in module \top..
437s 
437s 2.13.8. Executing OPT_EXPR pass (perform const folding).
437s Optimizing module top.
437s 
437s 2.13.9. Finished OPT passes. (There is nothing left to do.)
437s 
437s 2.14. Executing WREDUCE pass (reducing word size of cells).
437s Removed top 31 bits (of 32) from port B of cell top.$add$example.v:17$382 ($add).
437s Removed top 5 bits (of 32) from port Y of cell top.$add$example.v:17$382 ($add).
437s Removed top 1 bits (of 5) from port B of cell top.$xor$example.v:21$385 ($xor).
437s 
437s 2.15. Executing PEEPOPT pass (run peephole optimizers).
437s 
437s 2.16. Executing OPT_CLEAN pass (remove unused cells and wires).
437s Finding unused cells or wires in module \top..
437s Removed 0 unused cells and 1 unused wires.
437s <suppressed ~1 debug messages>
437s 
437s 2.17. Executing SHARE pass (SAT-based resource sharing).
437s 
437s 2.18. Executing TECHMAP pass (map to technology primitives).
437s 
437s 2.18.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v
437s Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation.
437s Generating RTLIL representation for module `\_90_lut_cmp_'.
437s Successfully finished Verilog frontend.
437s 
437s 2.18.2. Continuing TECHMAP pass.
437s No more expansions possible.
437s <suppressed ~6 debug messages>
437s 
437s 2.19. Executing OPT_EXPR pass (perform const folding).
437s Optimizing module top.
437s 
437s 2.20. Executing OPT_CLEAN pass (remove unused cells and wires).
437s Finding unused cells or wires in module \top..
437s 
437s 2.21. Executing ALUMACC pass (create $alu and $macc cells).
437s Extracting $alu and $macc cells in module top:
437s   creating $macc model for $add$example.v:17$382 ($add).
437s   creating $alu model for $macc $add$example.v:17$382.
437s   creating $alu cell for $add$example.v:17$382: $auto$alumacc.cc:485:replace_alu$454
437s   created 1 $alu and 0 $macc cells.
437s 
437s 2.22. Executing OPT pass (performing simple optimizations).
437s 
437s 2.22.1. Executing OPT_EXPR pass (perform const folding).
437s Optimizing module top.
437s 
437s 2.22.2. Executing OPT_MERGE pass (detect identical cells).
437s Finding identical cells in module `\top'.
437s Removed a total of 0 cells.
437s 
437s 2.22.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
437s Running muxtree optimizer on module \top..
437s   Creating internal representation of mux trees.
437s   No muxes found in this module.
437s Removed 0 multiplexer ports.
437s 
437s 2.22.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
437s   Optimizing cells in module \top.
437s Performed a total of 0 changes.
437s 
437s 2.22.5. Executing OPT_MERGE pass (detect identical cells).
437s Finding identical cells in module `\top'.
437s Removed a total of 0 cells.
437s 
437s 2.22.6. Executing OPT_DFF pass (perform DFF optimizations).
437s 
437s 2.22.7. Executing OPT_CLEAN pass (remove unused cells and wires).
437s Finding unused cells or wires in module \top..
437s 
437s 2.22.8. Executing OPT_EXPR pass (perform const folding).
437s Optimizing module top.
437s 
437s 2.22.9. Finished OPT passes. (There is nothing left to do.)
437s 
437s 2.23. Executing MEMORY pass.
437s 
437s 2.23.1. Executing OPT_MEM pass (optimize memories).
437s Performed a total of 0 transformations.
437s 
437s 2.23.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
437s Performed a total of 0 transformations.
437s 
437s 2.23.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
437s 
437s 2.23.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
437s 
437s 2.23.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
437s 
437s 2.23.6. Executing OPT_CLEAN pass (remove unused cells and wires).
437s Finding unused cells or wires in module \top..
437s 
437s 2.23.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
437s 
437s 2.23.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
437s Performed a total of 0 transformations.
437s 
437s 2.23.9. Executing OPT_CLEAN pass (remove unused cells and wires).
437s Finding unused cells or wires in module \top..
437s 
437s 2.23.10. Executing MEMORY_COLLECT pass (generating $mem cells).
437s 
437s 2.24. Executing OPT_CLEAN pass (remove unused cells and wires).
437s Finding unused cells or wires in module \top..
437s 
437s 2.25. Executing MEMORY_LIBMAP pass (mapping memories to cells).
437s 
437s 2.26. Executing TECHMAP pass (map to technology primitives).
437s 
437s 2.26.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v
438s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation.
438s Generating RTLIL representation for module `\$__ICE40_RAM4K_'.
438s Successfully finished Verilog frontend.
438s 
438s 2.26.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/spram_map.v
438s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/spram_map.v' to AST representation.
438s Generating RTLIL representation for module `\$__ICE40_SPRAM_'.
438s Successfully finished Verilog frontend.
438s 
438s 2.26.3. Continuing TECHMAP pass.
438s No more expansions possible.
438s <suppressed ~4 debug messages>
438s 
438s 2.27. Executing ICE40_BRAMINIT pass.
438s 
438s 2.28. Executing OPT pass (performing simple optimizations).
438s 
438s 2.28.1. Executing OPT_EXPR pass (perform const folding).
438s Optimizing module top.
438s <suppressed ~5 debug messages>
438s 
438s 2.28.2. Executing OPT_MERGE pass (detect identical cells).
438s Finding identical cells in module `\top'.
438s Removed a total of 0 cells.
438s 
438s 2.28.3. Executing OPT_DFF pass (perform DFF optimizations).
438s 
438s 2.28.4. Executing OPT_CLEAN pass (remove unused cells and wires).
438s Finding unused cells or wires in module \top..
438s Removed 0 unused cells and 2 unused wires.
438s <suppressed ~1 debug messages>
438s 
438s 2.28.5. Finished fast OPT passes.
438s 
438s 2.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
438s 
438s 2.30. Executing OPT pass (performing simple optimizations).
438s 
438s 2.30.1. Executing OPT_EXPR pass (perform const folding).
438s Optimizing module top.
438s 
438s 2.30.2. Executing OPT_MERGE pass (detect identical cells).
438s Finding identical cells in module `\top'.
438s Removed a total of 0 cells.
438s 
438s 2.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
438s Running muxtree optimizer on module \top..
438s   Creating internal representation of mux trees.
438s   No muxes found in this module.
438s Removed 0 multiplexer ports.
438s 
438s 2.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
438s   Optimizing cells in module \top.
438s Performed a total of 0 changes.
438s 
438s 2.30.5. Executing OPT_MERGE pass (detect identical cells).
438s Finding identical cells in module `\top'.
438s Removed a total of 0 cells.
438s 
438s 2.30.6. Executing OPT_DFF pass (perform DFF optimizations).
438s 
438s 2.30.7. Executing OPT_CLEAN pass (remove unused cells and wires).
438s Finding unused cells or wires in module \top..
438s 
438s 2.30.8. Executing OPT_EXPR pass (perform const folding).
438s Optimizing module top.
438s 
438s 2.30.9. Finished OPT passes. (There is nothing left to do.)
438s 
438s 2.31. Executing ICE40_WRAPCARRY pass (wrap carries).
438s 
438s 2.32. Executing TECHMAP pass (map to technology primitives).
438s 
438s 2.32.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v
438s Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation.
438s Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
438s Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
438s Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
438s Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
438s Generating RTLIL representation for module `\_90_simplemap_various'.
438s Generating RTLIL representation for module `\_90_simplemap_registers'.
438s Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
438s Generating RTLIL representation for module `\_90_shift_shiftx'.
438s Generating RTLIL representation for module `\_90_fa'.
438s Generating RTLIL representation for module `\_90_lcu'.
438s Generating RTLIL representation for module `\_90_alu'.
438s Generating RTLIL representation for module `\_90_macc'.
438s Generating RTLIL representation for module `\_90_alumacc'.
438s Generating RTLIL representation for module `\$__div_mod_u'.
438s Generating RTLIL representation for module `\$__div_mod_trunc'.
438s Generating RTLIL representation for module `\_90_div'.
438s Generating RTLIL representation for module `\_90_mod'.
438s Generating RTLIL representation for module `\$__div_mod_floor'.
438s Generating RTLIL representation for module `\_90_divfloor'.
438s Generating RTLIL representation for module `\_90_modfloor'.
438s Generating RTLIL representation for module `\_90_pow'.
438s Generating RTLIL representation for module `\_90_pmux'.
438s Generating RTLIL representation for module `\_90_demux'.
438s Generating RTLIL representation for module `\_90_lut'.
438s Successfully finished Verilog frontend.
438s 
438s 2.32.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v
438s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation.
438s Generating RTLIL representation for module `\_80_ice40_alu'.
438s Successfully finished Verilog frontend.
438s 
438s 2.32.3. Continuing TECHMAP pass.
438s Using template $paramod$956e79e8f8c5e64be7438155ae50a966e615cb04\_80_ice40_alu for cells of type $alu.
438s Using extmapper simplemap for cells of type $xor.
438s Using extmapper simplemap for cells of type $dff.
438s Using extmapper simplemap for cells of type $mux.
438s Using extmapper simplemap for cells of type $not.
438s Using extmapper simplemap for cells of type $pos.
438s No more expansions possible.
438s <suppressed ~101 debug messages>
438s 
438s 2.33. Executing OPT pass (performing simple optimizations).
438s 
438s 2.33.1. Executing OPT_EXPR pass (perform const folding).
438s Optimizing module top.
438s <suppressed ~54 debug messages>
438s 
438s 2.33.2. Executing OPT_MERGE pass (detect identical cells).
438s Finding identical cells in module `\top'.
438s <suppressed ~3 debug messages>
438s Removed a total of 1 cells.
438s 
438s 2.33.3. Executing OPT_DFF pass (perform DFF optimizations).
438s 
438s 2.33.4. Executing OPT_CLEAN pass (remove unused cells and wires).
438s Finding unused cells or wires in module \top..
438s Removed 27 unused cells and 17 unused wires.
438s <suppressed ~28 debug messages>
438s 
438s 2.33.5. Finished fast OPT passes.
438s 
438s 2.34. Executing ICE40_OPT pass (performing simple optimizations).
438s 
438s 2.34.1. Running ICE40 specific optimizations.
438s Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$454.slice[0].carry: CO=\counter [0]
438s 
438s 2.34.2. Executing OPT_EXPR pass (perform const folding).
438s Optimizing module top.
438s 
438s 2.34.3. Executing OPT_MERGE pass (detect identical cells).
438s Finding identical cells in module `\top'.
438s Removed a total of 0 cells.
438s 
438s 2.34.4. Executing OPT_DFF pass (perform DFF optimizations).
438s 
438s 2.34.5. Executing OPT_CLEAN pass (remove unused cells and wires).
438s Finding unused cells or wires in module \top..
438s 
438s 2.34.6. Rerunning OPT passes. (Removed registers in this run.)
438s 
438s 2.34.7. Running ICE40 specific optimizations.
438s 
438s 2.34.8. Executing OPT_EXPR pass (perform const folding).
438s Optimizing module top.
438s 
438s 2.34.9. Executing OPT_MERGE pass (detect identical cells).
438s Finding identical cells in module `\top'.
438s Removed a total of 0 cells.
438s 
438s 2.34.10. Executing OPT_DFF pass (perform DFF optimizations).
438s 
438s 2.34.11. Executing OPT_CLEAN pass (remove unused cells and wires).
438s Finding unused cells or wires in module \top..
438s 
438s 2.34.12. Finished OPT passes. (There is nothing left to do.)
438s 
438s 2.35. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
438s 
438s 2.36. Executing TECHMAP pass (map to technology primitives).
438s 
438s 2.36.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v
438s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation.
438s Generating RTLIL representation for module `\$_DFF_N_'.
438s Generating RTLIL representation for module `\$_DFF_P_'.
438s Generating RTLIL representation for module `\$_DFFE_NP_'.
438s Generating RTLIL representation for module `\$_DFFE_PP_'.
438s Generating RTLIL representation for module `\$_DFF_NP0_'.
438s Generating RTLIL representation for module `\$_DFF_NP1_'.
438s Generating RTLIL representation for module `\$_DFF_PP0_'.
438s Generating RTLIL representation for module `\$_DFF_PP1_'.
438s Generating RTLIL representation for module `\$_DFFE_NP0P_'.
438s Generating RTLIL representation for module `\$_DFFE_NP1P_'.
438s Generating RTLIL representation for module `\$_DFFE_PP0P_'.
438s Generating RTLIL representation for module `\$_DFFE_PP1P_'.
438s Generating RTLIL representation for module `\$_SDFF_NP0_'.
438s Generating RTLIL representation for module `\$_SDFF_NP1_'.
438s Generating RTLIL representation for module `\$_SDFF_PP0_'.
438s Generating RTLIL representation for module `\$_SDFF_PP1_'.
438s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
438s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
438s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
438s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
438s Successfully finished Verilog frontend.
438s 
438s 2.36.2. Continuing TECHMAP pass.
438s Using template \$_DFF_P_ for cells of type $_DFF_P_.
438s No more expansions possible.
438s <suppressed ~54 debug messages>
438s 
438s 2.37. Executing OPT_EXPR pass (perform const folding).
438s Optimizing module top.
438s 
438s 2.38. Executing SIMPLEMAP pass (map simple cells to gate primitives).
438s Mapping top.$auto$alumacc.cc:485:replace_alu$454.slice[0].carry ($lut).
438s 
438s 2.39. Executing ICE40_OPT pass (performing simple optimizations).
438s 
438s 2.39.1. Running ICE40 specific optimizations.
438s 
438s 2.39.2. Executing OPT_EXPR pass (perform const folding).
438s Optimizing module top.
438s <suppressed ~14 debug messages>
438s 
438s 2.39.3. Executing OPT_MERGE pass (detect identical cells).
438s Finding identical cells in module `\top'.
438s Removed a total of 0 cells.
438s 
438s 2.39.4. Executing OPT_DFF pass (perform DFF optimizations).
438s 
438s 2.39.5. Executing OPT_CLEAN pass (remove unused cells and wires).
438s Finding unused cells or wires in module \top..
438s Removed 0 unused cells and 132 unused wires.
438s <suppressed ~1 debug messages>
438s 
438s 2.39.6. Rerunning OPT passes. (Removed registers in this run.)
438s 
438s 2.39.7. Running ICE40 specific optimizations.
438s 
438s 2.39.8. Executing OPT_EXPR pass (perform const folding).
438s Optimizing module top.
438s 
438s 2.39.9. Executing OPT_MERGE pass (detect identical cells).
438s Finding identical cells in module `\top'.
438s Removed a total of 0 cells.
438s 
438s 2.39.10. Executing OPT_DFF pass (perform DFF optimizations).
438s 
438s 2.39.11. Executing OPT_CLEAN pass (remove unused cells and wires).
438s Finding unused cells or wires in module \top..
438s 
438s 2.39.12. Finished OPT passes. (There is nothing left to do.)
438s 
438s 2.40. Executing TECHMAP pass (map to technology primitives).
438s 
438s 2.40.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v
438s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation.
438s Generating RTLIL representation for module `\$_DLATCH_N_'.
438s Generating RTLIL representation for module `\$_DLATCH_P_'.
438s Successfully finished Verilog frontend.
438s 
438s 2.40.2. Continuing TECHMAP pass.
438s No more expansions possible.
438s <suppressed ~4 debug messages>
438s 
438s 2.41. Executing ABC pass (technology mapping using ABC).
438s 
438s 2.41.1. Extracting gate netlist of module `\top' to `<abc-temp-dir>/input.blif'..
438s Extracted 5 gates and 11 wires to a netlist network with 6 inputs and 5 outputs.
438s 
438s 2.41.1.1. Executing ABC.
438s Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
438s ABC: ABC command line: "source <abc-temp-dir>/abc.script".
438s ABC: 
438s ABC: + read_blif <abc-temp-dir>/input.blif 
438s ABC: + read_lut <abc-temp-dir>/lutdefs.txt 
438s ABC: + strash 
438s ABC: + &get -n 
438s ABC: + &fraig -x 
438s ABC: + &put 
438s ABC: + scorr 
438s ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
438s ABC: + dc2 
438s ABC: + dretime 
438s ABC: + strash 
438s ABC: + dch -f 
438s ABC: + if 
438s ABC: + mfs2 
438s ABC: + lutpack -S 1 
438s ABC: + dress <abc-temp-dir>/input.blif 
438s ABC: Total number of equiv classes                =       6.
438s ABC: Participating nodes from both networks       =      10.
438s ABC: Participating nodes from the first network   =       5. (  83.33 % of nodes)
438s ABC: Participating nodes from the second network  =       5. (  83.33 % of nodes)
438s ABC: Node pairs (any polarity)                    =       5. (  83.33 % of names can be moved)
438s ABC: Node pairs (same polarity)                   =       5. (  83.33 % of names can be moved)
438s ABC: Total runtime =     0.00 sec
438s ABC: + write_blif <abc-temp-dir>/output.blif 
438s 
438s 2.41.1.2. Re-integrating ABC results.
438s ABC RESULTS:              $lut cells:        5
438s ABC RESULTS:        internal signals:        0
438s ABC RESULTS:           input signals:        6
438s ABC RESULTS:          output signals:        5
438s Removing temp directory.
438s 
438s 2.42. Executing ICE40_WRAPCARRY pass (wrap carries).
438s 
438s 2.43. Executing TECHMAP pass (map to technology primitives).
438s 
438s 2.43.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v
438s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation.
438s Generating RTLIL representation for module `\$_DFF_N_'.
438s Generating RTLIL representation for module `\$_DFF_P_'.
438s Generating RTLIL representation for module `\$_DFFE_NP_'.
438s Generating RTLIL representation for module `\$_DFFE_PP_'.
438s Generating RTLIL representation for module `\$_DFF_NP0_'.
438s Generating RTLIL representation for module `\$_DFF_NP1_'.
438s Generating RTLIL representation for module `\$_DFF_PP0_'.
438s Generating RTLIL representation for module `\$_DFF_PP1_'.
438s Generating RTLIL representation for module `\$_DFFE_NP0P_'.
438s Generating RTLIL representation for module `\$_DFFE_NP1P_'.
438s Generating RTLIL representation for module `\$_DFFE_PP0P_'.
438s Generating RTLIL representation for module `\$_DFFE_PP1P_'.
438s Generating RTLIL representation for module `\$_SDFF_NP0_'.
438s Generating RTLIL representation for module `\$_SDFF_NP1_'.
438s Generating RTLIL representation for module `\$_SDFF_PP0_'.
438s Generating RTLIL representation for module `\$_SDFF_PP1_'.
438s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
438s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
438s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
438s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
438s Successfully finished Verilog frontend.
438s 
438s 2.43.2. Continuing TECHMAP pass.
438s No more expansions possible.
438s <suppressed ~22 debug messages>
438s Removed 1 unused cells and 12 unused wires.
438s 
438s 2.44. Executing OPT_LUT pass (optimize LUTs).
438s Discovering LUTs.
438s Number of LUTs:       31
438s   1-LUT                1
438s   2-LUT                5
438s   3-LUT               25
438s   with \SB_CARRY    (#0)   25
438s   with \SB_CARRY    (#1)   25
438s 
438s Eliminating LUTs.
438s Number of LUTs:       31
438s   1-LUT                1
438s   2-LUT                5
438s   3-LUT               25
438s   with \SB_CARRY    (#0)   25
438s   with \SB_CARRY    (#1)   25
438s 
438s Combining LUTs.
438s Number of LUTs:       31
438s   1-LUT                1
438s   2-LUT                5
438s   3-LUT               25
438s   with \SB_CARRY    (#0)   25
438s   with \SB_CARRY    (#1)   25
438s 
438s Eliminated 0 LUTs.
438s Combined 0 LUTs.
438s <suppressed ~112 debug messages>
438s 
438s 2.45. Executing TECHMAP pass (map to technology primitives).
438s 
438s 2.45.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v
438s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation.
438s Generating RTLIL representation for module `\$lut'.
438s Successfully finished Verilog frontend.
438s 
438s 2.45.2. Continuing TECHMAP pass.
438s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
438s Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut.
438s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
438s No more expansions possible.
438s <suppressed ~73 debug messages>
438s Removed 0 unused cells and 62 unused wires.
438s 
438s 2.46. Executing AUTONAME pass.
438s Renamed 142 objects in module top (4 iterations).
438s <suppressed ~90 debug messages>
438s 
438s 2.47. Executing HIERARCHY pass (managing design hierarchy).
438s 
438s 2.47.1. Analyzing design hierarchy..
438s Top module:  \top
438s 
438s 2.47.2. Analyzing design hierarchy..
438s Top module:  \top
438s Removed 0 unused modules.
438s 
438s 2.48. Printing statistics.
438s 
438s === top ===
438s 
438s    Number of wires:                 10
438s    Number of wire bits:             92
438s    Number of public wires:          10
438s    Number of public wire bits:      92
438s    Number of memories:               0
438s    Number of memory bits:            0
438s    Number of processes:              0
438s    Number of cells:                 88
438s      SB_CARRY                       25
438s      SB_DFF                         32
438s      SB_LUT4                        31
438s 
438s 2.49. Executing CHECK pass (checking for obvious problems).
438s Checking module top...
438s Found and reported 0 problems.
438s 
438s 2.50. Executing JSON backend.
438s 
438s End of script. Logfile hash: 53dfafea51, CPU: user 0.93s system 0.03s, MEM: 20.00 MB peak
438s Yosys 0.33 (git sha1 2584903a060)
438s Time spent: 66% 13x read_verilog (0 sec), 7% 1x synth_ice40 (0 sec), ...
438s nextpnr-ice40 --hx1k --package tq144 --asc example.asc --pcf icestick.pcf --json example.json
438s Warning: unmatched constraint 'RX' (on line 4)
438s Warning: unmatched constraint 'TX' (on line 5)
438s Info: constrained 'LED1' to bel 'X13/Y12/io1'
438s Info: constrained 'LED2' to bel 'X13/Y12/io0'
438s Info: constrained 'LED3' to bel 'X13/Y11/io1'
438s Info: constrained 'LED4' to bel 'X13/Y11/io0'
438s Info: constrained 'LED5' to bel 'X13/Y9/io1'
438s Info: constrained 'clk' to bel 'X0/Y8/io1'
438s 
438s Info: Packing constants..
438s Info: Packing IOs..
438s Info: Packing LUT-FFs..
438s Info:        4 LCs used as LUT4 only
438s Info:       27 LCs used as LUT4 and DFF
438s Info: Packing non-LUT FFs..
438s Info:        5 LCs used as DFF only
438s Info: Packing carries..
438s Info:        0 LCs used as CARRY only
438s Info: Packing indirect carry+LUT pairs...
438s Info:        0 LUTs merged into carry LCs
438s Info: Packing RAMs..
438s Info: Placing PLLs..
438s Info: Packing special functions..
438s Info: Packing PLLs..
438s Info: Promoting globals..
438s Info: promoting clk$SB_IO_IN (fanout 32)
438s Info: Constraining chains...
438s Info:        1 LCs used to legalise carry chains.
438s Info: Checksum: 0xae2b0ce7
438s 
438s Info: Annotating ports with timing budgets for target frequency 12.00 MHz
438s Info: Checksum: 0x993bf822
438s 
438s Info: Device utilisation:
438s Info: 	         ICESTORM_LC:    39/ 1280     3%
438s Info: 	        ICESTORM_RAM:     0/   16     0%
438s Info: 	               SB_IO:     6/  112     5%
438s Info: 	               SB_GB:     1/    8    12%
438s Info: 	        ICESTORM_PLL:     0/    1     0%
438s Info: 	         SB_WARMBOOT:     0/    1     0%
438s 
438s Info: Placed 6 cells based on constraints.
438s Info: Creating initial analytic placement for 12 cells, random placement wirelen = 182.
438s Info:     at initial placer iter 0, wirelen = 16
438s Info:     at initial placer iter 1, wirelen = 16
438s Info:     at initial placer iter 2, wirelen = 18
438s Info:     at initial placer iter 3, wirelen = 18
438s Info: Running main analytical placer, max placement attempts per cell = 10000.
438s Info:     at iteration #1, type ICESTORM_LC: wirelen solved = 19, spread = 34, legal = 36; time = 0.00s
438s Info:     at iteration #1, type SB_GB: wirelen solved = 36, spread = 36, legal = 36; time = 0.00s
438s Info:     at iteration #1, type ALL: wirelen solved = 17, spread = 33, legal = 33; time = 0.00s
438s Info:     at iteration #2, type ICESTORM_LC: wirelen solved = 17, spread = 31, legal = 32; time = 0.00s
438s Info:     at iteration #2, type SB_GB: wirelen solved = 32, spread = 32, legal = 32; time = 0.00s
438s Info:     at iteration #2, type ALL: wirelen solved = 17, spread = 31, legal = 32; time = 0.00s
438s Info:     at iteration #3, type ICESTORM_LC: wirelen solved = 15, spread = 36, legal = 37; time = 0.00s
438s Info:     at iteration #3, type SB_GB: wirelen solved = 37, spread = 37, legal = 37; time = 0.00s
438s Info:     at iteration #3, type ALL: wirelen solved = 15, spread = 36, legal = 38; time = 0.00s
438s Info:     at iteration #4, type ICESTORM_LC: wirelen solved = 15, spread = 37, legal = 38; time = 0.00s
438s Info:     at iteration #4, type SB_GB: wirelen solved = 38, spread = 38, legal = 38; time = 0.00s
438s Info:     at iteration #4, type ALL: wirelen solved = 15, spread = 37, legal = 38; time = 0.00s
438s Info:     at iteration #5, type ICESTORM_LC: wirelen solved = 20, spread = 38, legal = 40; time = 0.00s
438s Info:     at iteration #5, type SB_GB: wirelen solved = 40, spread = 40, legal = 40; time = 0.00s
438s Info:     at iteration #5, type ALL: wirelen solved = 20, spread = 38, legal = 39; time = 0.00s
438s Info:     at iteration #6, type ICESTORM_LC: wirelen solved = 20, spread = 39, legal = 40; time = 0.00s
438s Info:     at iteration #6, type SB_GB: wirelen solved = 40, spread = 40, legal = 40; time = 0.00s
438s Info:     at iteration #6, type ALL: wirelen solved = 20, spread = 39, legal = 41; time = 0.00s
438s Info:     at iteration #7, type ICESTORM_LC: wirelen solved = 27, spread = 39, legal = 41; time = 0.00s
438s Info:     at iteration #7, type SB_GB: wirelen solved = 41, spread = 41, legal = 41; time = 0.00s
438s Info:     at iteration #7, type ALL: wirelen solved = 27, spread = 39, legal = 40; time = 0.00s
438s Info: HeAP Placer Time: 0.01s
438s Info:   of which solving equations: 0.01s
438s Info:   of which spreading cells: 0.00s
438s Info:   of which strict legalisation: 0.00s
438s 
438s Info: Running simulated annealing placer for refinement.
438s Info:   at iteration #1: temp = 0.000000, timing cost = 4, wirelen = 32
438s Info:   at iteration #5: temp = 0.000000, timing cost = 4, wirelen = 21
438s Info:   at iteration #9: temp = 0.000000, timing cost = 4, wirelen = 21 
438s Info: SA placement time 0.01s
438s 
438s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 170.01 MHz (PASS at 12.00 MHz)
438s 
438s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> <async>: 2.09 ns
438s 
438s Info: Slack histogram:
438s Info:  legend: * represents 1 endpoint(s)
438s Info:          + represents [1,1) endpoint(s)
438s Info: [ 77451,  77672) |*** 
438s Info: [ 77672,  77893) | 
438s Info: [ 77893,  78114) |* 
438s Info: [ 78114,  78335) |** 
438s Info: [ 78335,  78556) |* 
438s Info: [ 78556,  78777) |** 
438s Info: [ 78777,  78998) |** 
438s Info: [ 78998,  79219) | 
438s Info: [ 79219,  79440) |* 
438s Info: [ 79440,  79661) |** 
438s Info: [ 79661,  79882) |** 
438s Info: [ 79882,  80103) |** 
438s Info: [ 80103,  80324) |* 
438s Info: [ 80324,  80545) | 
438s Info: [ 80545,  80766) |** 
438s Info: [ 80766,  80987) |** 
438s Info: [ 80987,  81208) |* 
438s Info: [ 81208,  81429) |***** 
438s Info: [ 81429,  81650) |* 
438s Info: [ 81650,  81871) |********************************* 
438s Info: Checksum: 0xa2e17380
438s 
438s Info: Routing..
438s Info: Setting up routing queue.
438s Info: Routing 106 arcs.
438s Info:            |   (re-)routed arcs  |   delta    | remaining|       time spent     |
438s Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|
438s Info:        106 |        0         84 |    0    84 |         0|       0.00       0.00|
438s Info: Routing complete.
438s Info: Router1 time 0.00s
438s Info: Checksum: 0x30991612
438s 
438s Info: Critical path report for clock 'clk$SB_IO_IN_$glb_clk' (posedge -> posedge):
438s Info: curr total
438s Info:  0.5  0.5  Source counter_SB_LUT4_I3_LC.O
438s Info:  0.6  1.1    Net counter[0] budget 78.740997 ns (11,6) -> (11,7)
438s Info:                Sink $nextpnr_ICESTORM_LC_0.I1
438s Info:                Defined in:
438s Info:                  example.v:17.14-17.25
438s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
438s Info:  0.3  1.4  Source $nextpnr_ICESTORM_LC_0.COUT
438s Info:  0.0  1.4    Net $nextpnr_ICESTORM_LC_0$O budget 0.000000 ns (11,7) -> (11,7)
438s Info:                Sink counter_SB_LUT4_I2_20_LC.CIN
438s Info:  0.1  1.5  Source counter_SB_LUT4_I2_20_LC.COUT
438s Info:  0.0  1.5    Net counter_SB_CARRY_CI_CO[2] budget 0.000000 ns (11,7) -> (11,7)
438s Info:                Sink counter_SB_LUT4_I2_12_LC.CIN
438s Info:                Defined in:
438s Info:                  example.v:17.14-17.25
438s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
438s Info:  0.1  1.6  Source counter_SB_LUT4_I2_12_LC.COUT
438s Info:  0.0  1.6    Net counter_SB_CARRY_CI_CO[3] budget 0.000000 ns (11,7) -> (11,7)
438s Info:                Sink counter_SB_LUT4_I2_11_LC.CIN
438s Info:                Defined in:
438s Info:                  example.v:17.14-17.25
438s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
438s Info:  0.1  1.8  Source counter_SB_LUT4_I2_11_LC.COUT
438s Info:  0.0  1.8    Net counter_SB_CARRY_CI_CO[4] budget 0.000000 ns (11,7) -> (11,7)
438s Info:                Sink counter_SB_LUT4_I2_10_LC.CIN
438s Info:                Defined in:
438s Info:                  example.v:17.14-17.25
438s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
438s Info:  0.1  1.9  Source counter_SB_LUT4_I2_10_LC.COUT
438s Info:  0.0  1.9    Net counter_SB_CARRY_CI_CO[5] budget 0.000000 ns (11,7) -> (11,7)
438s Info:                Sink counter_SB_LUT4_I2_9_LC.CIN
438s Info:                Defined in:
438s Info:                  example.v:17.14-17.25
438s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
438s Info:  0.1  2.0  Source counter_SB_LUT4_I2_9_LC.COUT
438s Info:  0.0  2.0    Net counter_SB_CARRY_CI_CO[6] budget 0.000000 ns (11,7) -> (11,7)
438s Info:                Sink counter_SB_LUT4_I2_8_LC.CIN
438s Info:                Defined in:
438s Info:                  example.v:17.14-17.25
438s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
438s Info:  0.1  2.1  Source counter_SB_LUT4_I2_8_LC.COUT
438s Info:  0.0  2.1    Net counter_SB_CARRY_CI_CO[7] budget 0.000000 ns (11,7) -> (11,7)
438s Info:                Sink counter_SB_LUT4_I2_7_LC.CIN
438s Info:                Defined in:
438s Info:                  example.v:17.14-17.25
438s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
438s Info:  0.1  2.3  Source counter_SB_LUT4_I2_7_LC.COUT
438s Info:  0.2  2.5    Net counter_SB_CARRY_CI_CO[8] budget 0.190000 ns (11,7) -> (11,8)
438s Info:                Sink counter_SB_LUT4_I2_6_LC.CIN
438s Info:                Defined in:
438s Info:                  example.v:17.14-17.25
438s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
438s Info:  0.1  2.6  Source counter_SB_LUT4_I2_6_LC.COUT
438s Info:  0.0  2.6    Net counter_SB_CARRY_CI_CO[9] budget 0.000000 ns (11,8) -> (11,8)
438s Info:                Sink counter_SB_LUT4_I2_5_LC.CIN
438s Info:                Defined in:
438s Info:                  example.v:17.14-17.25
438s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
438s Info:  0.1  2.7  Source counter_SB_LUT4_I2_5_LC.COUT
438s Info:  0.0  2.7    Net counter_SB_CARRY_CI_CO[10] budget 0.000000 ns (11,8) -> (11,8)
438s Info:                Sink counter_SB_LUT4_I2_4_LC.CIN
438s Info:                Defined in:
438s Info:                  example.v:17.14-17.25
438s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
438s Info:  0.1  2.8  Source counter_SB_LUT4_I2_4_LC.COUT
438s Info:  0.0  2.8    Net counter_SB_CARRY_CI_CO[11] budget 0.000000 ns (11,8) -> (11,8)
438s Info:                Sink counter_SB_LUT4_I2_3_LC.CIN
438s Info:                Defined in:
438s Info:                  example.v:17.14-17.25
438s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
438s Info:  0.1  3.0  Source counter_SB_LUT4_I2_3_LC.COUT
438s Info:  0.0  3.0    Net counter_SB_CARRY_CI_CO[12] budget 0.000000 ns (11,8) -> (11,8)
438s Info:                Sink counter_SB_LUT4_I2_2_LC.CIN
438s Info:                Defined in:
438s Info:                  example.v:17.14-17.25
438s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
438s Info:  0.1  3.1  Source counter_SB_LUT4_I2_2_LC.COUT
438s Info:  0.0  3.1    Net counter_SB_CARRY_CI_CO[13] budget 0.000000 ns (11,8) -> (11,8)
438s Info:                Sink counter_SB_LUT4_I2_1_LC.CIN
438s Info:                Defined in:
438s Info:                  example.v:17.14-17.25
438s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
438s Info:  0.1  3.2  Source counter_SB_LUT4_I2_1_LC.COUT
438s Info:  0.0  3.2    Net counter_SB_CARRY_CI_CO[14] budget 0.000000 ns (11,8) -> (11,8)
438s Info:                Sink counter_SB_LUT4_I2_LC.CIN
438s Info:                Defined in:
438s Info:                  example.v:17.14-17.25
438s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
438s Info:  0.1  3.3  Source counter_SB_LUT4_I2_LC.COUT
438s Info:  0.0  3.3    Net counter_SB_CARRY_CI_CO[15] budget 0.000000 ns (11,8) -> (11,8)
438s Info:                Sink counter_SB_LUT4_I2_25_LC.CIN
438s Info:                Defined in:
438s Info:                  example.v:17.14-17.25
438s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
438s Info:  0.1  3.5  Source counter_SB_LUT4_I2_25_LC.COUT
438s Info:  0.2  3.7    Net counter_SB_CARRY_CI_CO[16] budget 0.190000 ns (11,8) -> (11,9)
438s Info:                Sink counter_SB_LUT4_I2_24_LC.CIN
438s Info:                Defined in:
438s Info:                  example.v:17.14-17.25
438s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
438s Info:  0.1  3.8  Source counter_SB_LUT4_I2_24_LC.COUT
438s Info:  0.0  3.8    Net counter_SB_CARRY_CI_CO[17] budget 0.000000 ns (11,9) -> (11,9)
438s Info:                Sink counter_SB_LUT4_I2_23_LC.CIN
438s Info:                Defined in:
438s Info:                  example.v:17.14-17.25
438s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
438s Info:  0.1  3.9  Source counter_SB_LUT4_I2_23_LC.COUT
438s Info:  0.0  3.9    Net counter_SB_CARRY_CI_CO[18] budget 0.000000 ns (11,9) -> (11,9)
438s Info:                Sink counter_SB_LUT4_I2_22_LC.CIN
438s Info:                Defined in:
438s Info:                  example.v:17.14-17.25
438s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
438s Info:  0.1  4.0  Source counter_SB_LUT4_I2_22_LC.COUT
438s Info:  0.0  4.0    Net counter_SB_CARRY_CI_CO[19] budget 0.000000 ns (11,9) -> (11,9)
438s Info:                Sink counter_SB_LUT4_I2_21_LC.CIN
438s Info:                Defined in:
438s Info:                  example.v:17.14-17.25
438s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
438s Info:  0.1  4.2  Source counter_SB_LUT4_I2_21_LC.COUT
438s Info:  0.0  4.2    Net counter_SB_CARRY_CI_CO[20] budget 0.000000 ns (11,9) -> (11,9)
438s Info:                Sink counter_SB_LUT4_I2_19_LC.CIN
438s Info:                Defined in:
438s Info:                  example.v:17.14-17.25
438s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
438s Info:  0.1  4.3  Source counter_SB_LUT4_I2_19_LC.COUT
438s Info:  0.0  4.3    Net counter_SB_CARRY_CI_CO[21] budget 0.000000 ns (11,9) -> (11,9)
438s Info:                Sink counter_SB_LUT4_I2_18_LC.CIN
438s Info:                Defined in:
438s Info:                  example.v:17.14-17.25
438s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
438s Info:  0.1  4.4  Source counter_SB_LUT4_I2_18_LC.COUT
438s Info:  0.0  4.4    Net counter_SB_CARRY_CI_CO[22] budget 0.000000 ns (11,9) -> (11,9)
438s Info:                Sink counter_SB_LUT4_I2_17_LC.CIN
438s Info:                Defined in:
438s Info:                  example.v:17.14-17.25
438s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
438s Info:  0.1  4.6  Source counter_SB_LUT4_I2_17_LC.COUT
438s Info:  0.0  4.6    Net counter_SB_CARRY_CI_CO[23] budget 0.000000 ns (11,9) -> (11,9)
438s Info:                Sink counter_SB_LUT4_I2_16_LC.CIN
438s Info:                Defined in:
438s Info:                  example.v:17.14-17.25
438s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
438s Info:  0.1  4.7  Source counter_SB_LUT4_I2_16_LC.COUT
438s Info:  0.2  4.9    Net counter_SB_CARRY_CI_CO[24] budget 0.190000 ns (11,9) -> (11,10)
438s Info:                Sink counter_SB_LUT4_I2_15_LC.CIN
438s Info:                Defined in:
438s Info:                  example.v:17.14-17.25
438s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
438s Info:  0.1  5.0  Source counter_SB_LUT4_I2_15_LC.COUT
438s Info:  0.0  5.0    Net counter_SB_CARRY_CI_CO[25] budget 0.000000 ns (11,10) -> (11,10)
438s Info:                Sink counter_SB_LUT4_I2_14_LC.CIN
438s Info:                Defined in:
438s Info:                  example.v:17.14-17.25
438s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
438s Info:  0.1  5.1  Source counter_SB_LUT4_I2_14_LC.COUT
438s Info:  0.3  5.4    Net counter_SB_CARRY_CI_CO[26] budget 0.260000 ns (11,10) -> (11,10)
438s Info:                Sink counter_SB_LUT4_I2_13_LC.I3
438s Info:                Defined in:
438s Info:                  example.v:17.14-17.25
438s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
438s Info:  0.3  5.7  Setup counter_SB_LUT4_I2_13_LC.I3
438s Info: 4.3 ns logic, 1.4 ns routing
438s 
438s Info: Critical path report for cross-domain path 'posedge clk$SB_IO_IN_$glb_clk' -> '<async>':
438s Info: curr total
438s Info:  0.5  0.5  Source outcnt_SB_DFF_Q_DFFLC.O
438s Info:  0.6  1.1    Net outcnt[3] budget 41.208000 ns (11,10) -> (12,11)
438s Info:                Sink LED2_SB_LUT4_O_LC.I2
438s Info:                Defined in:
438s Info:                  example.v:14.17-14.23
438s Info:  0.4  1.5  Source LED2_SB_LUT4_O_LC.O
438s Info:  0.6  2.1    Net LED2$SB_IO_OUT budget 41.207001 ns (12,11) -> (13,12)
438s Info:                Sink LED2$sb_io.D_OUT_0
438s Info:                Defined in:
438s Info:                  example.v:4.9-4.13
438s Info: 0.9 ns logic, 1.2 ns routing
438s 
438s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 174.83 MHz (PASS at 12.00 MHz)
438s 
438s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> <async>: 2.09 ns
438s 
438s Info: Slack histogram:
438s Info:  legend: * represents 1 endpoint(s)
438s Info:          + represents [1,1) endpoint(s)
438s Info: [ 77613,  77826) |*** 
438s Info: [ 77826,  78039) | 
438s Info: [ 78039,  78252) |* 
438s Info: [ 78252,  78465) |** 
438s Info: [ 78465,  78678) |* 
438s Info: [ 78678,  78891) |** 
438s Info: [ 78891,  79104) |** 
438s Info: [ 79104,  79317) | 
438s Info: [ 79317,  79530) |** 
438s Info: [ 79530,  79743) |* 
438s Info: [ 79743,  79956) |** 
438s Info: [ 79956,  80169) |** 
438s Info: [ 80169,  80382) |* 
438s Info: [ 80382,  80595) | 
438s Info: [ 80595,  80808) |** 
438s Info: [ 80808,  81021) |** 
438s Info: [ 81021,  81234) |** 
438s Info: [ 81234,  81447) |**** 
438s Info: [ 81447,  81660) |** 
438s Info: [ 81660,  81873) |******************************** 
438s 2 warnings, 0 errors
438s 
438s icetime -d hx1k -mtr example.rpt example.asc
438s Info: Program finished normally.
438s // Reading input .asc file..
438s // Reading 1k chipdb file..
438s // Creating timing netlist..
438s // Timing estimate: 5.68 ns (175.97 MHz)
438s icepack example.asc example.bin
438s make: Leaving directory '/tmp/autopkgtest.eGJMaA/build.OQp/src/examples/icestick'
438s make: Entering directory '/tmp/autopkgtest.eGJMaA/build.OQp/src/examples/icezum'
438s yosys -p 'synth_ice40 -top top -json example.json' example.v
438s 
438s  /----------------------------------------------------------------------------\
438s  |                                                                            |
438s  |  yosys -- Yosys Open SYnthesis Suite                                       |
438s  |                                                                            |
438s  |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
438s  |                                                                            |
438s  |  Permission to use, copy, modify, and/or distribute this software for any  |
438s  |  purpose with or without fee is hereby granted, provided that the above    |
438s  |  copyright notice and this permission notice appear in all copies.         |
438s  |                                                                            |
438s  |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
438s  |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
438s  |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
438s  |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
438s  |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
438s  |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
438s  |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
438s  |                                                                            |
438s  \----------------------------------------------------------------------------/
438s 
438s  Yosys 0.33 (git sha1 2584903a060)
438s 
438s 
438s -- Parsing `example.v' using frontend ` -vlog2k' --
438s 
438s 1. Executing Verilog-2005 frontend: example.v
438s Parsing Verilog input from `example.v' to AST representation.
438s Storing AST representation for module `$abstract\top'.
438s Successfully finished Verilog frontend.
438s 
438s -- Running command `synth_ice40 -top top -json example.json' --
438s 
438s 2. Executing SYNTH_ICE40 pass.
438s 
438s 2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v
438s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation.
438s Generating RTLIL representation for module `\SB_IO'.
438s Generating RTLIL representation for module `\SB_GB_IO'.
438s Generating RTLIL representation for module `\SB_GB'.
438s Generating RTLIL representation for module `\SB_LUT4'.
438s Generating RTLIL representation for module `\SB_CARRY'.
438s Generating RTLIL representation for module `\SB_DFF'.
438s Generating RTLIL representation for module `\SB_DFFE'.
438s Generating RTLIL representation for module `\SB_DFFSR'.
438s Generating RTLIL representation for module `\SB_DFFR'.
438s Generating RTLIL representation for module `\SB_DFFSS'.
438s Generating RTLIL representation for module `\SB_DFFS'.
438s Generating RTLIL representation for module `\SB_DFFESR'.
438s Generating RTLIL representation for module `\SB_DFFER'.
438s Generating RTLIL representation for module `\SB_DFFESS'.
438s Generating RTLIL representation for module `\SB_DFFES'.
438s Generating RTLIL representation for module `\SB_DFFN'.
438s Generating RTLIL representation for module `\SB_DFFNE'.
438s Generating RTLIL representation for module `\SB_DFFNSR'.
438s Generating RTLIL representation for module `\SB_DFFNR'.
438s Generating RTLIL representation for module `\SB_DFFNSS'.
438s Generating RTLIL representation for module `\SB_DFFNS'.
438s Generating RTLIL representation for module `\SB_DFFNESR'.
438s Generating RTLIL representation for module `\SB_DFFNER'.
438s Generating RTLIL representation for module `\SB_DFFNESS'.
438s Generating RTLIL representation for module `\SB_DFFNES'.
438s Generating RTLIL representation for module `\SB_RAM40_4K'.
438s Generating RTLIL representation for module `\SB_RAM40_4KNR'.
438s Generating RTLIL representation for module `\SB_RAM40_4KNW'.
438s Generating RTLIL representation for module `\SB_RAM40_4KNRNW'.
438s Generating RTLIL representation for module `\ICESTORM_LC'.
438s Generating RTLIL representation for module `\SB_PLL40_CORE'.
438s Generating RTLIL representation for module `\SB_PLL40_PAD'.
438s Generating RTLIL representation for module `\SB_PLL40_2_PAD'.
438s Generating RTLIL representation for module `\SB_PLL40_2F_CORE'.
438s Generating RTLIL representation for module `\SB_PLL40_2F_PAD'.
438s Generating RTLIL representation for module `\SB_WARMBOOT'.
438s Generating RTLIL representation for module `\SB_SPRAM256KA'.
438s Generating RTLIL representation for module `\SB_HFOSC'.
438s Generating RTLIL representation for module `\SB_LFOSC'.
438s Generating RTLIL representation for module `\SB_RGBA_DRV'.
438s Generating RTLIL representation for module `\SB_LED_DRV_CUR'.
438s Generating RTLIL representation for module `\SB_RGB_DRV'.
438s Generating RTLIL representation for module `\SB_I2C'.
438s Generating RTLIL representation for module `\SB_SPI'.
438s Generating RTLIL representation for module `\SB_LEDDA_IP'.
438s Generating RTLIL representation for module `\SB_FILTER_50NS'.
438s Generating RTLIL representation for module `\SB_IO_I3C'.
438s Generating RTLIL representation for module `\SB_IO_OD'.
438s Generating RTLIL representation for module `\SB_MAC16'.
438s Generating RTLIL representation for module `\ICESTORM_RAM'.
438s Successfully finished Verilog frontend.
438s 
438s 2.2. Executing HIERARCHY pass (managing design hierarchy).
438s 
438s 2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\top'.
438s Generating RTLIL representation for module `\top'.
438s 
438s 2.3.1. Analyzing design hierarchy..
438s Top module:  \top
438s 
438s 2.3.2. Analyzing design hierarchy..
438s Top module:  \top
438s Removing unused module `$abstract\top'.
438s Removed 1 unused modules.
438s 
438s 2.4. Executing PROC pass (convert processes to netlists).
438s 
438s 2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
438s Cleaned up 0 empty switches.
438s 
438s 2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
438s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241 in module SB_DFFNES.
438s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234 in module SB_DFFNESS.
438s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230 in module SB_DFFNER.
438s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223 in module SB_DFFNESR.
438s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220 in module SB_DFFNS.
438s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217 in module SB_DFFNSS.
438s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214 in module SB_DFFNR.
438s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211 in module SB_DFFNSR.
438s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203 in module SB_DFFES.
438s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196 in module SB_DFFESS.
438s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192 in module SB_DFFER.
438s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185 in module SB_DFFESR.
438s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182 in module SB_DFFS.
438s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179 in module SB_DFFSS.
438s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176 in module SB_DFFR.
438s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173 in module SB_DFFSR.
438s Removed a total of 0 dead cases.
438s 
438s 2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
438s Removed 8 redundant assignments.
438s Promoted 25 assignments to connections.
438s 
438s 2.4.4. Executing PROC_INIT pass (extract init attributes).
438s Found init rule in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'.
438s   Set init value: \Q = 1'0
438s Found init rule in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'.
438s   Set init value: \Q = 1'0
438s Found init rule in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'.
438s   Set init value: \Q = 1'0
438s Found init rule in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'.
438s   Set init value: \Q = 1'0
438s Found init rule in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'.
438s   Set init value: \Q = 1'0
438s Found init rule in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'.
438s   Set init value: \Q = 1'0
438s Found init rule in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'.
438s   Set init value: \Q = 1'0
438s Found init rule in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'.
438s   Set init value: \Q = 1'0
438s Found init rule in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'.
438s   Set init value: \Q = 1'0
438s Found init rule in `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'.
438s   Set init value: \Q = 1'0
438s Found init rule in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'.
438s   Set init value: \Q = 1'0
438s Found init rule in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'.
438s   Set init value: \Q = 1'0
438s Found init rule in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'.
438s   Set init value: \Q = 1'0
438s Found init rule in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'.
438s   Set init value: \Q = 1'0
438s Found init rule in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'.
438s   Set init value: \Q = 1'0
438s Found init rule in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'.
438s   Set init value: \Q = 1'0
438s Found init rule in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'.
438s   Set init value: \Q = 1'0
438s Found init rule in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'.
438s   Set init value: \Q = 1'0
438s Found init rule in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'.
438s   Set init value: \Q = 1'0
438s Found init rule in `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'.
438s   Set init value: \Q = 1'0
438s Found init rule in `\top.$proc$example.v:16$385'.
438s   Set init value: \counter = 23'00000000000000000000000
438s 
438s 2.4.5. Executing PROC_ARST pass (detect async resets in processes).
438s Found async reset \S in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
438s Found async reset \R in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
438s Found async reset \S in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
438s Found async reset \R in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
438s Found async reset \S in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
438s Found async reset \R in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
438s Found async reset \S in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'.
438s Found async reset \R in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'.
438s 
438s 2.4.6. Executing PROC_ROM pass (convert switches to ROMs).
438s Converted 0 switches.
438s <suppressed ~18 debug messages>
438s 
438s 2.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
438s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'.
438s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
438s      1/1: $0\Q[0:0]
438s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'.
438s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
438s      1/1: $0\Q[0:0]
438s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'.
438s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
438s      1/1: $0\Q[0:0]
438s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'.
438s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
438s      1/1: $0\Q[0:0]
438s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'.
438s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
438s      1/1: $0\Q[0:0]
438s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'.
438s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
438s      1/1: $0\Q[0:0]
438s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'.
438s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
438s      1/1: $0\Q[0:0]
438s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'.
438s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'.
438s      1/1: $0\Q[0:0]
438s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'.
438s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'.
438s      1/1: $0\Q[0:0]
438s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'.
438s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'.
438s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'.
438s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
438s      1/1: $0\Q[0:0]
438s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'.
438s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'.
438s      1/1: $0\Q[0:0]
438s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'.
438s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
438s      1/1: $0\Q[0:0]
438s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'.
438s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'.
438s      1/1: $0\Q[0:0]
438s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'.
438s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'.
438s      1/1: $0\Q[0:0]
438s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'.
438s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'.
438s      1/1: $0\Q[0:0]
438s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'.
438s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'.
438s      1/1: $0\Q[0:0]
438s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'.
438s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'.
438s      1/1: $0\Q[0:0]
438s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'.
438s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'.
438s      1/1: $0\Q[0:0]
438s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'.
438s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'.
438s Creating decoders for process `\top.$proc$example.v:16$385'.
438s Creating decoders for process `\top.$proc$example.v:19$381'.
438s 
438s 2.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
438s 
438s 2.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
438s Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
438s   created $adff cell `$procdff$430' with negative edge clock and positive level reset.
438s Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
438s   created $dff cell `$procdff$431' with negative edge clock.
438s Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
438s   created $adff cell `$procdff$432' with negative edge clock and positive level reset.
438s Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
438s   created $dff cell `$procdff$433' with negative edge clock.
438s Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
438s   created $adff cell `$procdff$434' with negative edge clock and positive level reset.
438s Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
438s   created $dff cell `$procdff$435' with negative edge clock.
438s Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
438s   created $adff cell `$procdff$436' with negative edge clock and positive level reset.
438s Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'.
438s   created $dff cell `$procdff$437' with negative edge clock.
438s Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'.
438s   created $dff cell `$procdff$438' with negative edge clock.
438s Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'.
438s   created $dff cell `$procdff$439' with negative edge clock.
438s Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
438s   created $adff cell `$procdff$440' with positive edge clock and positive level reset.
438s Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'.
438s   created $dff cell `$procdff$441' with positive edge clock.
438s Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
438s   created $adff cell `$procdff$442' with positive edge clock and positive level reset.
438s Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'.
438s   created $dff cell `$procdff$443' with positive edge clock.
438s Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'.
438s   created $adff cell `$procdff$444' with positive edge clock and positive level reset.
438s Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'.
438s   created $dff cell `$procdff$445' with positive edge clock.
438s Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'.
438s   created $adff cell `$procdff$446' with positive edge clock and positive level reset.
438s Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'.
438s   created $dff cell `$procdff$447' with positive edge clock.
438s Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'.
438s   created $dff cell `$procdff$448' with positive edge clock.
438s Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'.
438s   created $dff cell `$procdff$449' with positive edge clock.
438s Creating register for signal `\top.\counter' using process `\top.$proc$example.v:19$381'.
438s   created $dff cell `$procdff$450' with positive edge clock.
438s Creating register for signal `\top.\outcnt' using process `\top.$proc$example.v:19$381'.
438s   created $dff cell `$procdff$451' with positive edge clock.
438s 
438s 2.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
438s 
438s 2.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
438s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'.
438s Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
438s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
438s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'.
438s Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
438s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
438s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'.
438s Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
438s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
438s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'.
438s Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
438s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
438s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'.
438s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
438s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'.
438s Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
438s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
438s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'.
438s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
438s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'.
438s Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'.
438s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'.
438s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'.
438s Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'.
438s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'.
438s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'.
438s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'.
438s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'.
438s Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
438s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
438s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'.
438s Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'.
438s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'.
438s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'.
438s Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
438s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
438s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'.
438s Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'.
438s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'.
438s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'.
438s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'.
438s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'.
438s Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'.
438s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'.
438s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'.
438s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'.
438s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'.
438s Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'.
438s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'.
438s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'.
438s Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'.
438s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'.
438s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'.
438s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'.
438s Removing empty process `top.$proc$example.v:16$385'.
438s Removing empty process `top.$proc$example.v:19$381'.
438s Cleaned up 18 empty switches.
438s 
438s 2.4.12. Executing OPT_EXPR pass (perform const folding).
438s Optimizing module top.
438s <suppressed ~1 debug messages>
438s 
438s 2.5. Executing FLATTEN pass (flatten design).
438s 
438s 2.6. Executing TRIBUF pass.
438s 
438s 2.7. Executing DEMINOUT pass (demote inout ports to input or output).
438s 
438s 2.8. Executing OPT_EXPR pass (perform const folding).
438s Optimizing module top.
438s 
438s 2.9. Executing OPT_CLEAN pass (remove unused cells and wires).
438s Finding unused cells or wires in module \top..
438s Removed 0 unused cells and 3 unused wires.
438s <suppressed ~1 debug messages>
438s 
438s 2.10. Executing CHECK pass (checking for obvious problems).
438s Checking module top...
438s Found and reported 0 problems.
438s 
438s 2.11. Executing OPT pass (performing simple optimizations).
438s 
438s 2.11.1. Executing OPT_EXPR pass (perform const folding).
438s Optimizing module top.
438s 
438s 2.11.2. Executing OPT_MERGE pass (detect identical cells).
438s Finding identical cells in module `\top'.
438s Removed a total of 0 cells.
438s 
438s 2.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
438s Running muxtree optimizer on module \top..
438s   Creating internal representation of mux trees.
438s   No muxes found in this module.
438s Removed 0 multiplexer ports.
438s 
438s 2.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
438s   Optimizing cells in module \top.
438s Performed a total of 0 changes.
438s 
438s 2.11.5. Executing OPT_MERGE pass (detect identical cells).
438s Finding identical cells in module `\top'.
438s Removed a total of 0 cells.
438s 
438s 2.11.6. Executing OPT_DFF pass (perform DFF optimizations).
438s 
438s 2.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
438s Finding unused cells or wires in module \top..
438s 
438s 2.11.8. Executing OPT_EXPR pass (perform const folding).
438s Optimizing module top.
438s 
438s 2.11.9. Finished OPT passes. (There is nothing left to do.)
438s 
438s 2.12. Executing FSM pass (extract and optimize FSM).
438s 
438s 2.12.1. Executing FSM_DETECT pass (finding FSMs in design).
438s 
438s 2.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).
438s 
438s 2.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).
438s 
438s 2.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
438s Finding unused cells or wires in module \top..
438s 
438s 2.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).
438s 
438s 2.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
438s 
438s 2.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
438s 
438s 2.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
438s 
438s 2.13. Executing OPT pass (performing simple optimizations).
438s 
438s 2.13.1. Executing OPT_EXPR pass (perform const folding).
438s Optimizing module top.
438s 
438s 2.13.2. Executing OPT_MERGE pass (detect identical cells).
438s Finding identical cells in module `\top'.
438s Removed a total of 0 cells.
438s 
438s 2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
438s Running muxtree optimizer on module \top..
438s   Creating internal representation of mux trees.
438s   No muxes found in this module.
438s Removed 0 multiplexer ports.
438s 
438s 2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
438s   Optimizing cells in module \top.
438s Performed a total of 0 changes.
438s 
438s 2.13.5. Executing OPT_MERGE pass (detect identical cells).
438s Finding identical cells in module `\top'.
438s Removed a total of 0 cells.
438s 
438s 2.13.6. Executing OPT_DFF pass (perform DFF optimizations).
438s 
438s 2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
438s Finding unused cells or wires in module \top..
438s 
438s 2.13.8. Executing OPT_EXPR pass (perform const folding).
438s Optimizing module top.
438s 
438s 2.13.9. Finished OPT passes. (There is nothing left to do.)
438s 
438s 2.14. Executing WREDUCE pass (reducing word size of cells).
438s Removed top 31 bits (of 32) from port B of cell top.$add$example.v:20$382 ($add).
438s Removed top 9 bits (of 32) from port Y of cell top.$add$example.v:20$382 ($add).
438s Removed top 30 bits (of 32) from port A of cell top.$shl$example.v:24$384 ($shl).
438s Removed top 24 bits (of 32) from port Y of cell top.$shl$example.v:24$384 ($shl).
438s Removed top 24 bits (of 32) from wire top.$shl$example.v:24$384_Y.
438s 
438s 2.15. Executing PEEPOPT pass (run peephole optimizers).
438s 
438s 2.16. Executing OPT_CLEAN pass (remove unused cells and wires).
438s Finding unused cells or wires in module \top..
438s Removed 0 unused cells and 3 unused wires.
438s <suppressed ~1 debug messages>
438s 
438s 2.17. Executing SHARE pass (SAT-based resource sharing).
438s 
438s 2.18. Executing TECHMAP pass (map to technology primitives).
438s 
438s 2.18.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v
438s Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation.
438s Generating RTLIL representation for module `\_90_lut_cmp_'.
438s Successfully finished Verilog frontend.
438s 
438s 2.18.2. Continuing TECHMAP pass.
438s No more expansions possible.
438s <suppressed ~6 debug messages>
438s 
438s 2.19. Executing OPT_EXPR pass (perform const folding).
438s Optimizing module top.
438s 
438s 2.20. Executing OPT_CLEAN pass (remove unused cells and wires).
438s Finding unused cells or wires in module \top..
438s 
438s 2.21. Executing ALUMACC pass (create $alu and $macc cells).
438s Extracting $alu and $macc cells in module top:
438s   creating $macc model for $add$example.v:20$382 ($add).
438s   creating $alu model for $macc $add$example.v:20$382.
438s   creating $alu cell for $add$example.v:20$382: $auto$alumacc.cc:485:replace_alu$454
438s   created 1 $alu and 0 $macc cells.
438s 
438s 2.22. Executing OPT pass (performing simple optimizations).
438s 
438s 2.22.1. Executing OPT_EXPR pass (perform const folding).
438s Optimizing module top.
438s 
438s 2.22.2. Executing OPT_MERGE pass (detect identical cells).
438s Finding identical cells in module `\top'.
438s Removed a total of 0 cells.
438s 
438s 2.22.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
438s Running muxtree optimizer on module \top..
438s   Creating internal representation of mux trees.
438s   No muxes found in this module.
438s Removed 0 multiplexer ports.
438s 
438s 2.22.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
438s   Optimizing cells in module \top.
438s Performed a total of 0 changes.
438s 
438s 2.22.5. Executing OPT_MERGE pass (detect identical cells).
438s Finding identical cells in module `\top'.
438s Removed a total of 0 cells.
438s 
438s 2.22.6. Executing OPT_DFF pass (perform DFF optimizations).
438s 
438s 2.22.7. Executing OPT_CLEAN pass (remove unused cells and wires).
438s Finding unused cells or wires in module \top..
438s 
438s 2.22.8. Executing OPT_EXPR pass (perform const folding).
438s Optimizing module top.
438s 
438s 2.22.9. Finished OPT passes. (There is nothing left to do.)
438s 
438s 2.23. Executing MEMORY pass.
438s 
438s 2.23.1. Executing OPT_MEM pass (optimize memories).
438s Performed a total of 0 transformations.
438s 
438s 2.23.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
438s Performed a total of 0 transformations.
438s 
438s 2.23.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
438s 
438s 2.23.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
438s 
438s 2.23.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
438s 
438s 2.23.6. Executing OPT_CLEAN pass (remove unused cells and wires).
438s Finding unused cells or wires in module \top..
438s 
438s 2.23.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
438s 
438s 2.23.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
438s Performed a total of 0 transformations.
438s 
438s 2.23.9. Executing OPT_CLEAN pass (remove unused cells and wires).
438s Finding unused cells or wires in module \top..
438s 
438s 2.23.10. Executing MEMORY_COLLECT pass (generating $mem cells).
438s 
438s 2.24. Executing OPT_CLEAN pass (remove unused cells and wires).
438s Finding unused cells or wires in module \top..
438s 
438s 2.25. Executing MEMORY_LIBMAP pass (mapping memories to cells).
438s 
438s 2.26. Executing TECHMAP pass (map to technology primitives).
438s 
438s 2.26.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v
439s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation.
439s Generating RTLIL representation for module `\$__ICE40_RAM4K_'.
439s Successfully finished Verilog frontend.
439s 
439s 2.26.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/spram_map.v
439s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/spram_map.v' to AST representation.
439s Generating RTLIL representation for module `\$__ICE40_SPRAM_'.
439s Successfully finished Verilog frontend.
439s 
439s 2.26.3. Continuing TECHMAP pass.
439s No more expansions possible.
439s <suppressed ~4 debug messages>
439s 
439s 2.27. Executing ICE40_BRAMINIT pass.
439s 
439s 2.28. Executing OPT pass (performing simple optimizations).
439s 
439s 2.28.1. Executing OPT_EXPR pass (perform const folding).
439s Optimizing module top.
439s 
439s 2.28.2. Executing OPT_MERGE pass (detect identical cells).
439s Finding identical cells in module `\top'.
439s Removed a total of 0 cells.
439s 
439s 2.28.3. Executing OPT_DFF pass (perform DFF optimizations).
439s 
439s 2.28.4. Executing OPT_CLEAN pass (remove unused cells and wires).
439s Finding unused cells or wires in module \top..
439s 
439s 2.28.5. Finished fast OPT passes.
439s 
439s 2.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
439s 
439s 2.30. Executing OPT pass (performing simple optimizations).
439s 
439s 2.30.1. Executing OPT_EXPR pass (perform const folding).
439s Optimizing module top.
439s 
439s 2.30.2. Executing OPT_MERGE pass (detect identical cells).
439s Finding identical cells in module `\top'.
439s Removed a total of 0 cells.
439s 
439s 2.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
439s Running muxtree optimizer on module \top..
439s   Creating internal representation of mux trees.
439s   No muxes found in this module.
439s Removed 0 multiplexer ports.
439s 
439s 2.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
439s   Optimizing cells in module \top.
439s Performed a total of 0 changes.
439s 
439s 2.30.5. Executing OPT_MERGE pass (detect identical cells).
439s Finding identical cells in module `\top'.
439s Removed a total of 0 cells.
439s 
439s 2.30.6. Executing OPT_DFF pass (perform DFF optimizations).
439s 
439s 2.30.7. Executing OPT_CLEAN pass (remove unused cells and wires).
439s Finding unused cells or wires in module \top..
439s 
439s 2.30.8. Executing OPT_EXPR pass (perform const folding).
439s Optimizing module top.
439s 
439s 2.30.9. Finished OPT passes. (There is nothing left to do.)
439s 
439s 2.31. Executing ICE40_WRAPCARRY pass (wrap carries).
439s 
439s 2.32. Executing TECHMAP pass (map to technology primitives).
439s 
439s 2.32.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v
439s Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation.
439s Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
439s Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
439s Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
439s Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
439s Generating RTLIL representation for module `\_90_simplemap_various'.
439s Generating RTLIL representation for module `\_90_simplemap_registers'.
439s Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
439s Generating RTLIL representation for module `\_90_shift_shiftx'.
439s Generating RTLIL representation for module `\_90_fa'.
439s Generating RTLIL representation for module `\_90_lcu'.
439s Generating RTLIL representation for module `\_90_alu'.
439s Generating RTLIL representation for module `\_90_macc'.
439s Generating RTLIL representation for module `\_90_alumacc'.
439s Generating RTLIL representation for module `\$__div_mod_u'.
439s Generating RTLIL representation for module `\$__div_mod_trunc'.
439s Generating RTLIL representation for module `\_90_div'.
439s Generating RTLIL representation for module `\_90_mod'.
439s Generating RTLIL representation for module `\$__div_mod_floor'.
439s Generating RTLIL representation for module `\_90_divfloor'.
439s Generating RTLIL representation for module `\_90_modfloor'.
439s Generating RTLIL representation for module `\_90_pow'.
439s Generating RTLIL representation for module `\_90_pmux'.
439s Generating RTLIL representation for module `\_90_demux'.
439s Generating RTLIL representation for module `\_90_lut'.
439s Successfully finished Verilog frontend.
439s 
439s 2.32.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v
439s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation.
439s Generating RTLIL representation for module `\_80_ice40_alu'.
439s Successfully finished Verilog frontend.
439s 
439s 2.32.3. Continuing TECHMAP pass.
439s Using template $paramod$constmap:5c4fb84a0fc6ae5c0d4120d25a7a267fccccc7a8$paramod$bc0ada8317992808a26d9434f659d5d0f7acd7e1\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
439s Using template $paramod$36fdbc18fab0758c8553dda57bd33e3f8f3e8765\_80_ice40_alu for cells of type $alu.
439s Using extmapper simplemap for cells of type $dff.
439s Using extmapper simplemap for cells of type $xor.
439s Using extmapper simplemap for cells of type $not.
439s Using extmapper simplemap for cells of type $pos.
439s No more expansions possible.
439s <suppressed ~259 debug messages>
439s 
439s 2.33. Executing OPT pass (performing simple optimizations).
439s 
439s 2.33.1. Executing OPT_EXPR pass (perform const folding).
439s Optimizing module top.
439s <suppressed ~46 debug messages>
439s 
439s 2.33.2. Executing OPT_MERGE pass (detect identical cells).
439s Finding identical cells in module `\top'.
439s <suppressed ~3 debug messages>
439s Removed a total of 1 cells.
439s 
439s 2.33.3. Executing OPT_DFF pass (perform DFF optimizations).
439s 
439s 2.33.4. Executing OPT_CLEAN pass (remove unused cells and wires).
439s Finding unused cells or wires in module \top..
439s Removed 23 unused cells and 22 unused wires.
439s <suppressed ~24 debug messages>
439s 
439s 2.33.5. Finished fast OPT passes.
439s 
439s 2.34. Executing ICE40_OPT pass (performing simple optimizations).
439s 
439s 2.34.1. Running ICE40 specific optimizations.
439s Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$454.slice[0].carry: CO=\counter [0]
439s 
439s 2.34.2. Executing OPT_EXPR pass (perform const folding).
439s Optimizing module top.
439s 
439s 2.34.3. Executing OPT_MERGE pass (detect identical cells).
439s Finding identical cells in module `\top'.
439s Removed a total of 0 cells.
439s 
439s 2.34.4. Executing OPT_DFF pass (perform DFF optimizations).
439s 
439s 2.34.5. Executing OPT_CLEAN pass (remove unused cells and wires).
439s Finding unused cells or wires in module \top..
439s 
439s 2.34.6. Rerunning OPT passes. (Removed registers in this run.)
439s 
439s 2.34.7. Running ICE40 specific optimizations.
439s 
439s 2.34.8. Executing OPT_EXPR pass (perform const folding).
439s Optimizing module top.
439s 
439s 2.34.9. Executing OPT_MERGE pass (detect identical cells).
439s Finding identical cells in module `\top'.
439s Removed a total of 0 cells.
439s 
439s 2.34.10. Executing OPT_DFF pass (perform DFF optimizations).
439s 
439s 2.34.11. Executing OPT_CLEAN pass (remove unused cells and wires).
439s Finding unused cells or wires in module \top..
439s 
439s 2.34.12. Finished OPT passes. (There is nothing left to do.)
439s 
439s 2.35. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
439s 
439s 2.36. Executing TECHMAP pass (map to technology primitives).
439s 
439s 2.36.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v
439s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation.
439s Generating RTLIL representation for module `\$_DFF_N_'.
439s Generating RTLIL representation for module `\$_DFF_P_'.
439s Generating RTLIL representation for module `\$_DFFE_NP_'.
439s Generating RTLIL representation for module `\$_DFFE_PP_'.
439s Generating RTLIL representation for module `\$_DFF_NP0_'.
439s Generating RTLIL representation for module `\$_DFF_NP1_'.
439s Generating RTLIL representation for module `\$_DFF_PP0_'.
439s Generating RTLIL representation for module `\$_DFF_PP1_'.
439s Generating RTLIL representation for module `\$_DFFE_NP0P_'.
439s Generating RTLIL representation for module `\$_DFFE_NP1P_'.
439s Generating RTLIL representation for module `\$_DFFE_PP0P_'.
439s Generating RTLIL representation for module `\$_DFFE_PP1P_'.
439s Generating RTLIL representation for module `\$_SDFF_NP0_'.
439s Generating RTLIL representation for module `\$_SDFF_NP1_'.
439s Generating RTLIL representation for module `\$_SDFF_PP0_'.
439s Generating RTLIL representation for module `\$_SDFF_PP1_'.
439s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
439s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
439s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
439s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
439s Successfully finished Verilog frontend.
439s 
439s 2.36.2. Continuing TECHMAP pass.
439s Using template \$_DFF_P_ for cells of type $_DFF_P_.
439s No more expansions possible.
439s <suppressed ~48 debug messages>
439s 
439s 2.37. Executing OPT_EXPR pass (perform const folding).
439s Optimizing module top.
439s 
439s 2.38. Executing SIMPLEMAP pass (map simple cells to gate primitives).
439s Mapping top.$auto$alumacc.cc:485:replace_alu$454.slice[0].carry ($lut).
439s 
439s 2.39. Executing ICE40_OPT pass (performing simple optimizations).
439s 
439s 2.39.1. Running ICE40 specific optimizations.
439s 
439s 2.39.2. Executing OPT_EXPR pass (perform const folding).
439s Optimizing module top.
439s <suppressed ~20 debug messages>
439s 
439s 2.39.3. Executing OPT_MERGE pass (detect identical cells).
439s Finding identical cells in module `\top'.
439s Removed a total of 0 cells.
439s 
439s 2.39.4. Executing OPT_DFF pass (perform DFF optimizations).
439s 
439s 2.39.5. Executing OPT_CLEAN pass (remove unused cells and wires).
439s Finding unused cells or wires in module \top..
439s Removed 0 unused cells and 108 unused wires.
439s <suppressed ~1 debug messages>
439s 
439s 2.39.6. Rerunning OPT passes. (Removed registers in this run.)
439s 
439s 2.39.7. Running ICE40 specific optimizations.
439s 
439s 2.39.8. Executing OPT_EXPR pass (perform const folding).
439s Optimizing module top.
439s 
439s 2.39.9. Executing OPT_MERGE pass (detect identical cells).
439s Finding identical cells in module `\top'.
439s Removed a total of 0 cells.
439s 
439s 2.39.10. Executing OPT_DFF pass (perform DFF optimizations).
439s 
439s 2.39.11. Executing OPT_CLEAN pass (remove unused cells and wires).
439s Finding unused cells or wires in module \top..
439s 
439s 2.39.12. Finished OPT passes. (There is nothing left to do.)
439s 
439s 2.40. Executing TECHMAP pass (map to technology primitives).
439s 
439s 2.40.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v
439s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation.
439s Generating RTLIL representation for module `\$_DLATCH_N_'.
439s Generating RTLIL representation for module `\$_DLATCH_P_'.
439s Successfully finished Verilog frontend.
439s 
439s 2.40.2. Continuing TECHMAP pass.
439s No more expansions possible.
439s <suppressed ~4 debug messages>
439s 
439s 2.41. Executing ABC pass (technology mapping using ABC).
439s 
439s 2.41.1. Extracting gate netlist of module `\top' to `<abc-temp-dir>/input.blif'..
439s Extracted 14 gates and 19 wires to a netlist network with 4 inputs and 9 outputs.
439s 
439s 2.41.1.1. Executing ABC.
439s Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
439s ABC: ABC command line: "source <abc-temp-dir>/abc.script".
439s ABC: 
439s ABC: + read_blif <abc-temp-dir>/input.blif 
439s ABC: + read_lut <abc-temp-dir>/lutdefs.txt 
439s ABC: + strash 
439s ABC: + &get -n 
439s ABC: + &fraig -x 
439s ABC: + &put 
439s ABC: + scorr 
439s ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
439s ABC: + dc2 
439s ABC: + dretime 
439s ABC: + strash 
439s ABC: + dch -f 
439s ABC: + if 
439s ABC: + mfs2 
439s ABC: + lutpack -S 1 
439s ABC: + dress <abc-temp-dir>/input.blif 
439s ABC: Total number of equiv classes                =      10.
439s ABC: Participating nodes from both networks       =      19.
439s ABC: Participating nodes from the first network   =       9. (  90.00 % of nodes)
439s ABC: Participating nodes from the second network  =      10. ( 100.00 % of nodes)
439s ABC: Node pairs (any polarity)                    =       9. (  90.00 % of names can be moved)
439s ABC: Node pairs (same polarity)                   =       9. (  90.00 % of names can be moved)
439s ABC: Total runtime =     0.01 sec
439s ABC: + write_blif <abc-temp-dir>/output.blif 
439s 
439s 2.41.1.2. Re-integrating ABC results.
439s ABC RESULTS:              $lut cells:        9
439s ABC RESULTS:        internal signals:        6
439s ABC RESULTS:           input signals:        4
439s ABC RESULTS:          output signals:        9
439s Removing temp directory.
439s 
439s 2.42. Executing ICE40_WRAPCARRY pass (wrap carries).
439s 
439s 2.43. Executing TECHMAP pass (map to technology primitives).
439s 
439s 2.43.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v
439s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation.
439s Generating RTLIL representation for module `\$_DFF_N_'.
439s Generating RTLIL representation for module `\$_DFF_P_'.
439s Generating RTLIL representation for module `\$_DFFE_NP_'.
439s Generating RTLIL representation for module `\$_DFFE_PP_'.
439s Generating RTLIL representation for module `\$_DFF_NP0_'.
439s Generating RTLIL representation for module `\$_DFF_NP1_'.
439s Generating RTLIL representation for module `\$_DFF_PP0_'.
439s Generating RTLIL representation for module `\$_DFF_PP1_'.
439s Generating RTLIL representation for module `\$_DFFE_NP0P_'.
439s Generating RTLIL representation for module `\$_DFFE_NP1P_'.
439s Generating RTLIL representation for module `\$_DFFE_PP0P_'.
439s Generating RTLIL representation for module `\$_DFFE_PP1P_'.
439s Generating RTLIL representation for module `\$_SDFF_NP0_'.
439s Generating RTLIL representation for module `\$_SDFF_NP1_'.
439s Generating RTLIL representation for module `\$_SDFF_PP0_'.
439s Generating RTLIL representation for module `\$_SDFF_PP1_'.
439s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
439s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
439s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
439s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
439s Successfully finished Verilog frontend.
439s 
439s 2.43.2. Continuing TECHMAP pass.
439s No more expansions possible.
439s <suppressed ~22 debug messages>
439s Removed 1 unused cells and 16 unused wires.
439s 
439s 2.44. Executing OPT_LUT pass (optimize LUTs).
439s Discovering LUTs.
439s Number of LUTs:       31
439s   1-LUT                1
439s   2-LUT                1
439s   3-LUT               29
439s   with \SB_CARRY    (#0)   21
439s   with \SB_CARRY    (#1)   21
439s 
439s Eliminating LUTs.
439s Number of LUTs:       31
439s   1-LUT                1
439s   2-LUT                1
439s   3-LUT               29
439s   with \SB_CARRY    (#0)   21
439s   with \SB_CARRY    (#1)   21
439s 
439s Combining LUTs.
439s Number of LUTs:       31
439s   1-LUT                1
439s   2-LUT                1
439s   3-LUT               29
439s   with \SB_CARRY    (#0)   21
439s   with \SB_CARRY    (#1)   21
439s 
439s Eliminated 0 LUTs.
439s Combined 0 LUTs.
439s <suppressed ~104 debug messages>
439s 
439s 2.45. Executing TECHMAP pass (map to technology primitives).
439s 
439s 2.45.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v
439s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation.
439s Generating RTLIL representation for module `\$lut'.
439s Successfully finished Verilog frontend.
439s 
439s 2.45.2. Continuing TECHMAP pass.
439s Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut.
439s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut.
439s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut.
439s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
439s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut.
439s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut.
439s No more expansions possible.
439s <suppressed ~112 debug messages>
439s Removed 0 unused cells and 62 unused wires.
439s 
439s 2.46. Executing AUTONAME pass.
439s Renamed 124 objects in module top (4 iterations).
439s <suppressed ~80 debug messages>
439s 
439s 2.47. Executing HIERARCHY pass (managing design hierarchy).
439s 
439s 2.47.1. Analyzing design hierarchy..
439s Top module:  \top
439s 
439s 2.47.2. Analyzing design hierarchy..
439s Top module:  \top
439s Removed 0 unused modules.
439s 
439s 2.48. Printing statistics.
439s 
439s === top ===
439s 
439s    Number of wires:                 13
439s    Number of wire bits:             81
439s    Number of public wires:          13
439s    Number of public wire bits:      81
439s    Number of memories:               0
439s    Number of memory bits:            0
439s    Number of processes:              0
439s    Number of cells:                 78
439s      SB_CARRY                       21
439s      SB_DFF                         26
439s      SB_LUT4                        31
439s 
439s 2.49. Executing CHECK pass (checking for obvious problems).
439s Checking module top...
439s Found and reported 0 problems.
439s 
439s 2.50. Executing JSON backend.
439s 
439s End of script. Logfile hash: 89f015aa92, CPU: user 0.97s system 0.02s, MEM: 20.00 MB peak
439s Yosys 0.33 (git sha1 2584903a060)
439s Time spent: 62% 13x read_verilog (0 sec), 6% 1x synth_ice40 (0 sec), ...
439s nextpnr-ice40 --hx1k --package tq144 --asc example.asc --pcf icezum.pcf --json example.json
439s Info: constrained 'LED0' to bel 'X13/Y9/io1'
439s Info: constrained 'LED1' to bel 'X13/Y11/io0'
439s Info: constrained 'LED2' to bel 'X13/Y11/io1'
439s Info: constrained 'LED3' to bel 'X13/Y12/io0'
439s Info: constrained 'LED4' to bel 'X13/Y12/io1'
439s Info: constrained 'LED5' to bel 'X13/Y13/io0'
439s Info: constrained 'LED6' to bel 'X13/Y13/io1'
439s Info: constrained 'LED7' to bel 'X13/Y14/io0'
439s Info: constrained 'clk' to bel 'X0/Y8/io1'
439s 
439s Info: Packing constants..
439s Info: Packing IOs..
439s Info: Packing LUT-FFs..
439s Info:        8 LCs used as LUT4 only
439s Info:       23 LCs used as LUT4 and DFF
439s Info: Packing non-LUT FFs..
439s Info:        3 LCs used as DFF only
439s Info: Packing carries..
439s Info:        0 LCs used as CARRY only
439s Info: Packing indirect carry+LUT pairs...
439s Info:        0 LUTs merged into carry LCs
439s Info: Packing RAMs..
439s Info: Placing PLLs..
439s Info: Packing special functions..
439s Info: Packing PLLs..
439s Info: Promoting globals..
439s Info: promoting clk$SB_IO_IN (fanout 26)
439s Info: Constraining chains...
439s Info:        1 LCs used to legalise carry chains.
439s Info: Checksum: 0x62a7ba7d
439s 
439s Info: Annotating ports with timing budgets for target frequency 12.00 MHz
439s Info: Checksum: 0xe1af17d8
439s 
439s Info: Device utilisation:
439s Info: 	         ICESTORM_LC:    37/ 1280     2%
439s Info: 	        ICESTORM_RAM:     0/   16     0%
439s Info: 	               SB_IO:     9/  112     8%
439s Info: 	               SB_GB:     1/    8    12%
439s Info: 	        ICESTORM_PLL:     0/    1     0%
439s Info: 	         SB_WARMBOOT:     0/    1     0%
439s 
439s Info: Placed 9 cells based on constraints.
439s Info: Creating initial analytic placement for 14 cells, random placement wirelen = 180.
439s Info:     at initial placer iter 0, wirelen = 27
439s Info:     at initial placer iter 1, wirelen = 24
439s Info:     at initial placer iter 2, wirelen = 26
439s Info:     at initial placer iter 3, wirelen = 24
439s Info: Running main analytical placer, max placement attempts per cell = 10000.
439s Info:     at iteration #1, type ICESTORM_LC: wirelen solved = 26, spread = 31, legal = 30; time = 0.00s
439s Info:     at iteration #1, type SB_GB: wirelen solved = 30, spread = 30, legal = 30; time = 0.00s
439s Info:     at iteration #1, type ALL: wirelen solved = 15, spread = 18, legal = 33; time = 0.00s
439s Info:     at iteration #2, type ICESTORM_LC: wirelen solved = 25, spread = 43, legal = 43; time = 0.00s
439s Info:     at iteration #2, type SB_GB: wirelen solved = 43, spread = 43, legal = 43; time = 0.00s
439s Info:     at iteration #2, type ALL: wirelen solved = 25, spread = 43, legal = 43; time = 0.00s
439s Info:     at iteration #3, type ICESTORM_LC: wirelen solved = 29, spread = 43, legal = 43; time = 0.00s
439s Info:     at iteration #3, type SB_GB: wirelen solved = 43, spread = 43, legal = 43; time = 0.00s
439s Info:     at iteration #3, type ALL: wirelen solved = 29, spread = 43, legal = 43; time = 0.00s
439s Info:     at iteration #4, type ICESTORM_LC: wirelen solved = 27, spread = 47, legal = 47; time = 0.00s
439s Info:     at iteration #4, type SB_GB: wirelen solved = 47, spread = 47, legal = 47; time = 0.00s
439s Info:     at iteration #4, type ALL: wirelen solved = 27, spread = 47, legal = 47; time = 0.00s
439s Info:     at iteration #5, type ICESTORM_LC: wirelen solved = 29, spread = 46, legal = 46; time = 0.00s
439s Info:     at iteration #5, type SB_GB: wirelen solved = 46, spread = 46, legal = 46; time = 0.00s
439s Info:     at iteration #5, type ALL: wirelen solved = 29, spread = 44, legal = 44; time = 0.00s
439s Info:     at iteration #6, type ICESTORM_LC: wirelen solved = 27, spread = 47, legal = 47; time = 0.00s
439s Info:     at iteration #6, type SB_GB: wirelen solved = 47, spread = 47, legal = 47; time = 0.00s
439s Info:     at iteration #6, type ALL: wirelen solved = 29, spread = 49, legal = 49; time = 0.00s
439s Info: HeAP Placer Time: 0.01s
439s Info:   of which solving equations: 0.01s
439s Info:   of which spreading cells: 0.00s
439s Info:   of which strict legalisation: 0.00s
439s 
439s Info: Running simulated annealing placer for refinement.
439s Info:   at iteration #1: temp = 0.000000, timing cost = 3, wirelen = 33
439s Info:   at iteration #5: temp = 0.000000, timing cost = 3, wirelen = 24
439s Info:   at iteration #5: temp = 0.000000, timing cost = 3, wirelen = 24 
439s Info: SA placement time 0.00s
439s 
439s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 195.01 MHz (PASS at 12.00 MHz)
439s 
439s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> <async>: 2.74 ns
439s 
439s Info: Slack histogram:
439s Info:  legend: * represents 1 endpoint(s)
439s Info:          + represents [1,1) endpoint(s)
439s Info: [ 78205,  78389) |** 
439s Info: [ 78389,  78573) |* 
439s Info: [ 78573,  78757) |** 
439s Info: [ 78757,  78941) |** 
439s Info: [ 78941,  79125) | 
439s Info: [ 79125,  79309) | 
439s Info: [ 79309,  79493) |** 
439s Info: [ 79493,  79677) |* 
439s Info: [ 79677,  79861) |** 
439s Info: [ 79861,  80045) |* 
439s Info: [ 80045,  80229) |** 
439s Info: [ 80229,  80413) | 
439s Info: [ 80413,  80597) |*** 
439s Info: [ 80597,  80781) |* 
439s Info: [ 80781,  80965) |* 
439s Info: [ 80965,  81149) |** 
439s Info: [ 81149,  81333) |******* 
439s Info: [ 81333,  81517) | 
439s Info: [ 81517,  81701) | 
439s Info: [ 81701,  81885) |*************************** 
439s Info: Checksum: 0xa1bb4ca5
439s 
439s Info: Routing..
439s Info: Setting up routing queue.
439s Info: Routing 108 arcs.
439s Info:            |   (re-)routed arcs  |   delta    | remaining|       time spent     |
439s Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|
439s Info:        108 |        0         89 |    0    89 |         0|       0.00       0.00|
439s Info: Routing complete.
439s Info: Router1 time 0.00s
439s Info: Checksum: 0x4cb9f475
439s 
439s Info: Critical path report for clock 'clk$SB_IO_IN_$glb_clk' (posedge -> posedge):
439s Info: curr total
439s Info:  0.5  0.5  Source counter_SB_LUT4_I3_LC.O
439s Info:  0.6  1.1    Net counter[0] budget 79.292999 ns (12,10) -> (11,10)
439s Info:                Sink $nextpnr_ICESTORM_LC_0.I1
439s Info:                Defined in:
439s Info:                  example.v:20.14-20.25
439s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
439s Info:  0.3  1.4  Source $nextpnr_ICESTORM_LC_0.COUT
439s Info:  0.0  1.4    Net $nextpnr_ICESTORM_LC_0$O budget 0.000000 ns (11,10) -> (11,10)
439s Info:                Sink counter_SB_LUT4_I2_3_LC.CIN
439s Info:  0.1  1.5  Source counter_SB_LUT4_I2_3_LC.COUT
439s Info:  0.0  1.5    Net counter_SB_CARRY_CI_CO[2] budget 0.000000 ns (11,10) -> (11,10)
439s Info:                Sink counter_SB_LUT4_I2_21_LC.CIN
439s Info:                Defined in:
439s Info:                  example.v:20.14-20.25
439s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
439s Info:  0.1  1.6  Source counter_SB_LUT4_I2_21_LC.COUT
439s Info:  0.0  1.6    Net counter_SB_CARRY_CI_CO[3] budget 0.000000 ns (11,10) -> (11,10)
439s Info:                Sink counter_SB_LUT4_I2_20_LC.CIN
439s Info:                Defined in:
439s Info:                  example.v:20.14-20.25
439s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
439s Info:  0.1  1.8  Source counter_SB_LUT4_I2_20_LC.COUT
439s Info:  0.0  1.8    Net counter_SB_CARRY_CI_CO[4] budget 0.000000 ns (11,10) -> (11,10)
439s Info:                Sink counter_SB_LUT4_I2_19_LC.CIN
439s Info:                Defined in:
439s Info:                  example.v:20.14-20.25
439s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
439s Info:  0.1  1.9  Source counter_SB_LUT4_I2_19_LC.COUT
439s Info:  0.0  1.9    Net counter_SB_CARRY_CI_CO[5] budget 0.000000 ns (11,10) -> (11,10)
439s Info:                Sink counter_SB_LUT4_I2_18_LC.CIN
439s Info:                Defined in:
439s Info:                  example.v:20.14-20.25
439s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
439s Info:  0.1  2.0  Source counter_SB_LUT4_I2_18_LC.COUT
439s Info:  0.0  2.0    Net counter_SB_CARRY_CI_CO[6] budget 0.000000 ns (11,10) -> (11,10)
439s Info:                Sink counter_SB_LUT4_I2_17_LC.CIN
439s Info:                Defined in:
439s Info:                  example.v:20.14-20.25
439s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
439s Info:  0.1  2.1  Source counter_SB_LUT4_I2_17_LC.COUT
439s Info:  0.0  2.1    Net counter_SB_CARRY_CI_CO[7] budget 0.000000 ns (11,10) -> (11,10)
439s Info:                Sink counter_SB_LUT4_I2_16_LC.CIN
439s Info:                Defined in:
439s Info:                  example.v:20.14-20.25
439s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
439s Info:  0.1  2.3  Source counter_SB_LUT4_I2_16_LC.COUT
439s Info:  0.2  2.5    Net counter_SB_CARRY_CI_CO[8] budget 0.190000 ns (11,10) -> (11,11)
439s Info:                Sink counter_SB_LUT4_I2_15_LC.CIN
439s Info:                Defined in:
439s Info:                  example.v:20.14-20.25
439s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
439s Info:  0.1  2.6  Source counter_SB_LUT4_I2_15_LC.COUT
439s Info:  0.0  2.6    Net counter_SB_CARRY_CI_CO[9] budget 0.000000 ns (11,11) -> (11,11)
439s Info:                Sink counter_SB_LUT4_I2_14_LC.CIN
439s Info:                Defined in:
439s Info:                  example.v:20.14-20.25
439s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
439s Info:  0.1  2.7  Source counter_SB_LUT4_I2_14_LC.COUT
439s Info:  0.0  2.7    Net counter_SB_CARRY_CI_CO[10] budget 0.000000 ns (11,11) -> (11,11)
439s Info:                Sink counter_SB_LUT4_I2_13_LC.CIN
439s Info:                Defined in:
439s Info:                  example.v:20.14-20.25
439s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
439s Info:  0.1  2.8  Source counter_SB_LUT4_I2_13_LC.COUT
439s Info:  0.0  2.8    Net counter_SB_CARRY_CI_CO[11] budget 0.000000 ns (11,11) -> (11,11)
439s Info:                Sink counter_SB_LUT4_I2_12_LC.CIN
439s Info:                Defined in:
439s Info:                  example.v:20.14-20.25
439s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
439s Info:  0.1  3.0  Source counter_SB_LUT4_I2_12_LC.COUT
439s Info:  0.0  3.0    Net counter_SB_CARRY_CI_CO[12] budget 0.000000 ns (11,11) -> (11,11)
439s Info:                Sink counter_SB_LUT4_I2_11_LC.CIN
439s Info:                Defined in:
439s Info:                  example.v:20.14-20.25
439s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
439s Info:  0.1  3.1  Source counter_SB_LUT4_I2_11_LC.COUT
439s Info:  0.0  3.1    Net counter_SB_CARRY_CI_CO[13] budget 0.000000 ns (11,11) -> (11,11)
439s Info:                Sink counter_SB_LUT4_I2_10_LC.CIN
439s Info:                Defined in:
439s Info:                  example.v:20.14-20.25
439s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
439s Info:  0.1  3.2  Source counter_SB_LUT4_I2_10_LC.COUT
439s Info:  0.0  3.2    Net counter_SB_CARRY_CI_CO[14] budget 0.000000 ns (11,11) -> (11,11)
439s Info:                Sink counter_SB_LUT4_I2_9_LC.CIN
439s Info:                Defined in:
439s Info:                  example.v:20.14-20.25
439s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
439s Info:  0.1  3.3  Source counter_SB_LUT4_I2_9_LC.COUT
439s Info:  0.0  3.3    Net counter_SB_CARRY_CI_CO[15] budget 0.000000 ns (11,11) -> (11,11)
439s Info:                Sink counter_SB_LUT4_I2_8_LC.CIN
439s Info:                Defined in:
439s Info:                  example.v:20.14-20.25
439s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
439s Info:  0.1  3.5  Source counter_SB_LUT4_I2_8_LC.COUT
439s Info:  0.2  3.7    Net counter_SB_CARRY_CI_CO[16] budget 0.190000 ns (11,11) -> (11,12)
439s Info:                Sink counter_SB_LUT4_I2_7_LC.CIN
439s Info:                Defined in:
439s Info:                  example.v:20.14-20.25
439s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
439s Info:  0.1  3.8  Source counter_SB_LUT4_I2_7_LC.COUT
439s Info:  0.0  3.8    Net counter_SB_CARRY_CI_CO[17] budget 0.000000 ns (11,12) -> (11,12)
439s Info:                Sink counter_SB_LUT4_I2_6_LC.CIN
439s Info:                Defined in:
439s Info:                  example.v:20.14-20.25
439s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
439s Info:  0.1  3.9  Source counter_SB_LUT4_I2_6_LC.COUT
439s Info:  0.0  3.9    Net counter_SB_CARRY_CI_CO[18] budget 0.000000 ns (11,12) -> (11,12)
439s Info:                Sink counter_SB_LUT4_I2_5_LC.CIN
439s Info:                Defined in:
439s Info:                  example.v:20.14-20.25
439s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
439s Info:  0.1  4.0  Source counter_SB_LUT4_I2_5_LC.COUT
439s Info:  0.0  4.0    Net counter_SB_CARRY_CI_CO[19] budget 0.000000 ns (11,12) -> (11,12)
439s Info:                Sink counter_SB_LUT4_I2_4_LC.CIN
439s Info:                Defined in:
439s Info:                  example.v:20.14-20.25
439s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
439s Info:  0.1  4.2  Source counter_SB_LUT4_I2_4_LC.COUT
439s Info:  0.0  4.2    Net counter_SB_CARRY_CI_CO[20] budget 0.000000 ns (11,12) -> (11,12)
439s Info:                Sink counter_SB_LUT4_I2_2_LC.CIN
439s Info:                Defined in:
439s Info:                  example.v:20.14-20.25
439s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
439s Info:  0.1  4.3  Source counter_SB_LUT4_I2_2_LC.COUT
439s Info:  0.0  4.3    Net counter_SB_CARRY_CI_CO[21] budget 0.000000 ns (11,12) -> (11,12)
439s Info:                Sink counter_SB_LUT4_I2_1_LC.CIN
439s Info:                Defined in:
439s Info:                  example.v:20.14-20.25
439s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
439s Info:  0.1  4.4  Source counter_SB_LUT4_I2_1_LC.COUT
439s Info:  0.3  4.7    Net counter_SB_CARRY_CI_CO[22] budget 0.260000 ns (11,12) -> (11,12)
439s Info:                Sink counter_SB_LUT4_I2_LC.I3
439s Info:                Defined in:
439s Info:                  example.v:20.14-20.25
439s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
439s Info:  0.3  5.0  Setup counter_SB_LUT4_I2_LC.I3
439s Info: 3.8 ns logic, 1.2 ns routing
439s 
439s Info: Critical path report for cross-domain path 'posedge clk$SB_IO_IN_$glb_clk' -> '<async>':
439s Info: curr total
439s Info:  0.5  0.5  Source outcnt_SB_DFF_Q_DFFLC.O
439s Info:  0.6  1.1    Net outcnt[2] budget 41.196999 ns (12,12) -> (12,11)
439s Info:                Sink LED0_SB_LUT4_O_LC.I1
439s Info:                Defined in:
439s Info:                  example.v:17.17-17.23
439s Info:  0.4  1.5  Source LED0_SB_LUT4_O_LC.O
439s Info:  1.5  3.0    Net LED0$SB_IO_OUT budget 41.196999 ns (12,11) -> (13,9)
439s Info:                Sink LED0$sb_io.D_OUT_0
439s Info:                Defined in:
439s Info:                  example.v:3.9-3.13
439s Info: 0.9 ns logic, 2.1 ns routing
439s 
439s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 199.20 MHz (PASS at 12.00 MHz)
439s 
439s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> <async>: 3.02 ns
439s 
439s Info: Slack histogram:
439s Info:  legend: * represents 1 endpoint(s)
439s Info:          + represents [1,1) endpoint(s)
439s Info: [ 78313,  78491) |** 
439s Info: [ 78491,  78669) |* 
439s Info: [ 78669,  7884icetime -d hx1k -mtr example.rpt example.asc
439s 7) |** 
439s Info: [ 78847,  79025) |** 
439s Info: [ 79025,  79203) | 
439s Info: [ 79203,  79381) | 
439s Info: [ 79381,  79559) |** 
439s Info: [ 79559,  79737) |* 
439s Info: [ 79737,  79915) |** 
439s Info: [ 79915,  80093) |* 
439s Info: [ 80093,  80271) |** 
439s Info: [ 80271,  80449) |* 
439s Info: [ 80449,  80627) |** 
439s Info: [ 80627,  80805) |* 
439s Info: [ 80805,  80983) |** 
439s Info: [ 80983,  81161) |* 
439s Info: [ 81161,  81339) |******* 
439s Info: [ 81339,  81517) | 
439s Info: [ 81517,  81695) | 
439s Info: [ 81695,  81873) |*************************** 
439s 
439s Info: Program finished normally.
439s // Reading input .asc file..
439s // Reading 1k chipdb file..
440s // Creating timing netlist..
440s // Timing estimate: 4.98 ns (200.75 MHz)
440s icepack example.asc example.bin
440s make: Leaving directory '/tmp/autopkgtest.eGJMaA/build.OQp/src/examples/icezum'
440s make: Entering directory '/tmp/autopkgtest.eGJMaA/build.OQp/src/examples/up5k_rgb'
440s yosys -p 'synth_ice40 -top top -json rgb.json' rgb.v
440s 
440s  /----------------------------------------------------------------------------\
440s  |                                                                            |
440s  |  yosys -- Yosys Open SYnthesis Suite                                       |
440s  |                                                                            |
440s  |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
440s  |                                                                            |
440s  |  Permission to use, copy, modify, and/or distribute this software for any  |
440s  |  purpose with or without fee is hereby granted, provided that the above    |
440s  |  copyright notice and this permission notice appear in all copies.         |
440s  |                                                                            |
440s  |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
440s  |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
440s  |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
440s  |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
440s  |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
440s  |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
440s  |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
440s  |                                                                            |
440s  \----------------------------------------------------------------------------/
440s 
440s  Yosys 0.33 (git sha1 2584903a060)
440s 
440s 
440s -- Parsing `rgb.v' using frontend ` -vlog2k' --
440s 
440s 1. Executing Verilog-2005 frontend: rgb.v
440s Parsing Verilog input from `rgb.v' to AST representation.
440s Storing AST representation for module `$abstract\top'.
440s Successfully finished Verilog frontend.
440s 
440s -- Running command `synth_ice40 -top top -json rgb.json' --
440s 
440s 2. Executing SYNTH_ICE40 pass.
440s 
440s 2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v
440s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation.
440s Generating RTLIL representation for module `\SB_IO'.
440s Generating RTLIL representation for module `\SB_GB_IO'.
440s Generating RTLIL representation for module `\SB_GB'.
440s Generating RTLIL representation for module `\SB_LUT4'.
440s Generating RTLIL representation for module `\SB_CARRY'.
440s Generating RTLIL representation for module `\SB_DFF'.
440s Generating RTLIL representation for module `\SB_DFFE'.
440s Generating RTLIL representation for module `\SB_DFFSR'.
440s Generating RTLIL representation for module `\SB_DFFR'.
440s Generating RTLIL representation for module `\SB_DFFSS'.
440s Generating RTLIL representation for module `\SB_DFFS'.
440s Generating RTLIL representation for module `\SB_DFFESR'.
440s Generating RTLIL representation for module `\SB_DFFER'.
440s Generating RTLIL representation for module `\SB_DFFESS'.
440s Generating RTLIL representation for module `\SB_DFFES'.
440s Generating RTLIL representation for module `\SB_DFFN'.
440s Generating RTLIL representation for module `\SB_DFFNE'.
440s Generating RTLIL representation for module `\SB_DFFNSR'.
440s Generating RTLIL representation for module `\SB_DFFNR'.
440s Generating RTLIL representation for module `\SB_DFFNSS'.
440s Generating RTLIL representation for module `\SB_DFFNS'.
440s Generating RTLIL representation for module `\SB_DFFNESR'.
440s Generating RTLIL representation for module `\SB_DFFNER'.
440s Generating RTLIL representation for module `\SB_DFFNESS'.
440s Generating RTLIL representation for module `\SB_DFFNES'.
440s Generating RTLIL representation for module `\SB_RAM40_4K'.
440s Generating RTLIL representation for module `\SB_RAM40_4KNR'.
440s Generating RTLIL representation for module `\SB_RAM40_4KNW'.
440s Generating RTLIL representation for module `\SB_RAM40_4KNRNW'.
440s Generating RTLIL representation for module `\ICESTORM_LC'.
440s Generating RTLIL representation for module `\SB_PLL40_CORE'.
440s Generating RTLIL representation for module `\SB_PLL40_PAD'.
440s Generating RTLIL representation for module `\SB_PLL40_2_PAD'.
440s Generating RTLIL representation for module `\SB_PLL40_2F_CORE'.
440s Generating RTLIL representation for module `\SB_PLL40_2F_PAD'.
440s Generating RTLIL representation for module `\SB_WARMBOOT'.
440s Generating RTLIL representation for module `\SB_SPRAM256KA'.
440s Generating RTLIL representation for module `\SB_HFOSC'.
440s Generating RTLIL representation for module `\SB_LFOSC'.
440s Generating RTLIL representation for module `\SB_RGBA_DRV'.
440s Generating RTLIL representation for module `\SB_LED_DRV_CUR'.
440s Generating RTLIL representation for module `\SB_RGB_DRV'.
440s Generating RTLIL representation for module `\SB_I2C'.
440s Generating RTLIL representation for module `\SB_SPI'.
440s Generating RTLIL representation for module `\SB_LEDDA_IP'.
440s Generating RTLIL representation for module `\SB_FILTER_50NS'.
440s Generating RTLIL representation for module `\SB_IO_I3C'.
440s Generating RTLIL representation for module `\SB_IO_OD'.
440s Generating RTLIL representation for module `\SB_MAC16'.
440s Generating RTLIL representation for module `\ICESTORM_RAM'.
440s Successfully finished Verilog frontend.
440s 
440s 2.2. Executing HIERARCHY pass (managing design hierarchy).
440s 
440s 2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\top'.
440s Generating RTLIL representation for module `\top'.
440s 
440s 2.3.1. Analyzing design hierarchy..
440s Top module:  \top
440s 
440s 2.3.2. Analyzing design hierarchy..
440s Top module:  \top
440s Removing unused module `$abstract\top'.
440s Removed 1 unused modules.
440s 
440s 2.4. Executing PROC pass (convert processes to netlists).
440s 
440s 2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
440s Cleaned up 0 empty switches.
440s 
440s 2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
440s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241 in module SB_DFFNES.
440s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234 in module SB_DFFNESS.
440s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230 in module SB_DFFNER.
440s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223 in module SB_DFFNESR.
440s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220 in module SB_DFFNS.
440s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217 in module SB_DFFNSS.
440s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214 in module SB_DFFNR.
440s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211 in module SB_DFFNSR.
440s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203 in module SB_DFFES.
440s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196 in module SB_DFFESS.
440s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192 in module SB_DFFER.
440s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185 in module SB_DFFESR.
440s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182 in module SB_DFFS.
440s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179 in module SB_DFFSS.
440s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176 in module SB_DFFR.
440s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173 in module SB_DFFSR.
440s Removed a total of 0 dead cases.
440s 
440s 2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
440s Removed 8 redundant assignments.
440s Promoted 27 assignments to connections.
440s 
440s 2.4.4. Executing PROC_INIT pass (extract init attributes).
440s Found init rule in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'.
440s   Set init value: \Q = 1'0
440s Found init rule in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'.
440s   Set init value: \Q = 1'0
440s Found init rule in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'.
440s   Set init value: \Q = 1'0
440s Found init rule in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'.
440s   Set init value: \Q = 1'0
440s Found init rule in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'.
440s   Set init value: \Q = 1'0
440s Found init rule in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'.
440s   Set init value: \Q = 1'0
440s Found init rule in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'.
440s   Set init value: \Q = 1'0
440s Found init rule in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'.
440s   Set init value: \Q = 1'0
440s Found init rule in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'.
440s   Set init value: \Q = 1'0
440s Found init rule in `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'.
440s   Set init value: \Q = 1'0
440s Found init rule in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'.
440s   Set init value: \Q = 1'0
440s Found init rule in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'.
440s   Set init value: \Q = 1'0
440s Found init rule in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'.
440s   Set init value: \Q = 1'0
440s Found init rule in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'.
440s   Set init value: \Q = 1'0
440s Found init rule in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'.
440s   Set init value: \Q = 1'0
440s Found init rule in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'.
440s   Set init value: \Q = 1'0
440s Found init rule in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'.
440s   Set init value: \Q = 1'0
440s Found init rule in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'.
440s   Set init value: \Q = 1'0
440s Found init rule in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'.
440s   Set init value: \Q = 1'0
440s Found init rule in `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'.
440s   Set init value: \Q = 1'0
440s 
440s 2.4.5. Executing PROC_ARST pass (detect async resets in processes).
440s Found async reset \S in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
440s Found async reset \R in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
440s Found async reset \S in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
440s Found async reset \R in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
440s Found async reset \S in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
440s Found async reset \R in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
440s Found async reset \S in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'.
440s Found async reset \R in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'.
440s 
440s 2.4.6. Executing PROC_ROM pass (convert switches to ROMs).
440s Converted 0 switches.
440s <suppressed ~18 debug messages>
440s 
440s 2.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
440s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'.
440s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
440s      1/1: $0\Q[0:0]
440s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'.
440s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
440s      1/1: $0\Q[0:0]
440s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'.
440s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
440s      1/1: $0\Q[0:0]
440s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'.
440s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
440s      1/1: $0\Q[0:0]
440s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'.
440s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
440s      1/1: $0\Q[0:0]
440s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'.
440s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
440s      1/1: $0\Q[0:0]
440s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'.
440s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
440s      1/1: $0\Q[0:0]
440s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'.
440s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'.
440s      1/1: $0\Q[0:0]
440s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'.
440s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'.
440s      1/1: $0\Q[0:0]
440s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'.
440s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'.
440s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'.
440s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
440s      1/1: $0\Q[0:0]
440s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'.
440s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'.
440s      1/1: $0\Q[0:0]
440s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'.
440s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
440s      1/1: $0\Q[0:0]
440s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'.
440s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'.
440s      1/1: $0\Q[0:0]
440s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'.
440s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'.
440s      1/1: $0\Q[0:0]
440s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'.
440s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'.
440s      1/1: $0\Q[0:0]
440s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'.
440s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'.
440s      1/1: $0\Q[0:0]
440s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'.
440s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'.
440s      1/1: $0\Q[0:0]
440s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'.
440s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'.
440s      1/1: $0\Q[0:0]
440s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'.
440s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'.
440s Creating decoders for process `\top.$proc$rgb.v:55$415'.
440s Creating decoders for process `\top.$proc$rgb.v:17$381'.
440s 
440s 2.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
440s 
440s 2.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
440s Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
440s   created $adff cell `$procdff$467' with negative edge clock and positive level reset.
440s Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
440s   created $dff cell `$procdff$468' with negative edge clock.
440s Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
440s   created $adff cell `$procdff$469' with negative edge clock and positive level reset.
440s Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
440s   created $dff cell `$procdff$470' with negative edge clock.
440s Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
440s   created $adff cell `$procdff$471' with negative edge clock and positive level reset.
440s Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
440s   created $dff cell `$procdff$472' with negative edge clock.
440s Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
440s   created $adff cell `$procdff$473' with negative edge clock and positive level reset.
440s Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'.
440s   created $dff cell `$procdff$474' with negative edge clock.
440s Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'.
440s   created $dff cell `$procdff$475' with negative edge clock.
440s Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'.
440s   created $dff cell `$procdff$476' with negative edge clock.
440s Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
440s   created $adff cell `$procdff$477' with positive edge clock and positive level reset.
440s Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'.
440s   created $dff cell `$procdff$478' with positive edge clock.
440s Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
440s   created $adff cell `$procdff$479' with positive edge clock and positive level reset.
440s Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'.
440s   created $dff cell `$procdff$480' with positive edge clock.
440s Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'.
440s   created $adff cell `$procdff$481' with positive edge clock and positive level reset.
440s Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'.
440s   created $dff cell `$procdff$482' with positive edge clock.
440s Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'.
440s   created $adff cell `$procdff$483' with positive edge clock and positive level reset.
440s Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'.
440s   created $dff cell `$procdff$484' with positive edge clock.
440s Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'.
440s   created $dff cell `$procdff$485' with positive edge clock.
440s Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'.
440s   created $dff cell `$procdff$486' with positive edge clock.
440s Creating register for signal `\top.\pwm_ctr' using process `\top.$proc$rgb.v:55$415'.
440s   created $dff cell `$procdff$487' with positive edge clock.
440s Creating register for signal `\top.\pwm_r' using process `\top.$proc$rgb.v:55$415'.
440s   created $dff cell `$procdff$488' with positive edge clock.
440s Creating register for signal `\top.\pwm_g' using process `\top.$proc$rgb.v:55$415'.
440s   created $dff cell `$procdff$489' with positive edge clock.
440s Creating register for signal `\top.\pwm_b' using process `\top.$proc$rgb.v:55$415'.
440s   created $dff cell `$procdff$490' with positive edge clock.
440s Creating register for signal `\top.\ctr' using process `\top.$proc$rgb.v:17$381'.
440s   created $dff cell `$procdff$491' with positive edge clock.
440s 
440s 2.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
440s 
440s 2.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
440s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'.
440s Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
440s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'.
440s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'.
440s Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
440s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'.
440s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'.
440s Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
440s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'.
440s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'.
440s Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
440s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'.
440s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'.
440s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'.
440s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'.
440s Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
440s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'.
440s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'.
440s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'.
440s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'.
440s Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'.
440s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'.
440s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'.
440s Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'.
440s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'.
440s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'.
440s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'.
440s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'.
440s Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
440s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'.
440s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'.
440s Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'.
440s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'.
440s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'.
440s Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
440s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'.
440s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'.
440s Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'.
440s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'.
440s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'.
440s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'.
440s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'.
440s Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'.
440s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'.
440s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'.
440s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'.
440s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'.
440s Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'.
440s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'.
440s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'.
440s Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'.
440s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'.
440s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'.
440s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'.
440s Removing empty process `top.$proc$rgb.v:55$415'.
440s Removing empty process `top.$proc$rgb.v:17$381'.
440s Cleaned up 18 empty switches.
440s 
440s 2.4.12. Executing OPT_EXPR pass (perform const folding).
440s Optimizing module top.
440s <suppressed ~3 debug messages>
440s 
440s 2.5. Executing FLATTEN pass (flatten design).
440s 
440s 2.6. Executing TRIBUF pass.
440s 
440s 2.7. Executing DEMINOUT pass (demote inout ports to input or output).
440s 
440s 2.8. Executing OPT_EXPR pass (perform const folding).
440s Optimizing module top.
440s 
440s 2.9. Executing OPT_CLEAN pass (remove unused cells and wires).
440s Finding unused cells or wires in module \top..
440s Removed 0 unused cells and 8 unused wires.
440s <suppressed ~5 debug messages>
440s 
440s 2.10. Executing CHECK pass (checking for obvious problems).
440s Checking module top...
440s Found and reported 0 problems.
440s 
440s 2.11. Executing OPT pass (performing simple optimizations).
440s 
440s 2.11.1. Executing OPT_EXPR pass (perform const folding).
440s Optimizing module top.
440s 
440s 2.11.2. Executing OPT_MERGE pass (detect identical cells).
440s Finding identical cells in module `\top'.
440s <suppressed ~27 debug messages>
440s Removed a total of 9 cells.
440s 
440s 2.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
440s Running muxtree optimizer on module \top..
440s   Creating internal representation of mux trees.
440s   Evaluating internal representation of mux trees.
440s   Analyzing evaluation results.
440s Removed 0 multiplexer ports.
440s <suppressed ~6 debug messages>
440s 
440s 2.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
440s   Optimizing cells in module \top.
440s Performed a total of 0 changes.
440s 
440s 2.11.5. Executing OPT_MERGE pass (detect identical cells).
440s Finding identical cells in module `\top'.
440s <suppressed ~3 debug messages>
440s Removed a total of 1 cells.
440s 
440s 2.11.6. Executing OPT_DFF pass (perform DFF optimizations).
440s 
440s 2.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
440s Finding unused cells or wires in module \top..
440s Removed 0 unused cells and 10 unused wires.
440s <suppressed ~1 debug messages>
440s 
440s 2.11.8. Executing OPT_EXPR pass (perform const folding).
440s Optimizing module top.
440s 
440s 2.11.9. Rerunning OPT passes. (Maybe there is more to do..)
440s 
440s 2.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
440s Running muxtree optimizer on module \top..
440s   Creating internal representation of mux trees.
440s   Evaluating internal representation of mux trees.
440s   Analyzing evaluation results.
440s Removed 0 multiplexer ports.
440s <suppressed ~7 debug messages>
440s 
440s 2.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
440s   Optimizing cells in module \top.
440s Performed a total of 0 changes.
440s 
440s 2.11.12. Executing OPT_MERGE pass (detect identical cells).
440s Finding identical cells in module `\top'.
440s Removed a total of 0 cells.
440s 
440s 2.11.13. Executing OPT_DFF pass (perform DFF optimizations).
440s 
440s 2.11.14. Executing OPT_CLEAN pass (remove unused cells and wires).
440s Finding unused cells or wires in module \top..
440s 
440s 2.11.15. Executing OPT_EXPR pass (perform const folding).
440s Optimizing module top.
440s 
440s 2.11.16. Finished OPT passes. (There is nothing left to do.)
440s 
440s 2.12. Executing FSM pass (extract and optimize FSM).
440s 
440s 2.12.1. Executing FSM_DETECT pass (finding FSMs in design).
440s 
440s 2.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).
440s 
440s 2.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).
440s 
440s 2.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
440s Finding unused cells or wires in module \top..
440s 
440s 2.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).
440s 
440s 2.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
440s 
440s 2.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
440s 
440s 2.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
440s 
440s 2.13. Executing OPT pass (performing simple optimizations).
440s 
440s 2.13.1. Executing OPT_EXPR pass (perform const folding).
440s Optimizing module top.
440s 
440s 2.13.2. Executing OPT_MERGE pass (detect identical cells).
440s Finding identical cells in module `\top'.
440s Removed a total of 0 cells.
440s 
440s 2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
440s Running muxtree optimizer on module \top..
440s   Creating internal representation of mux trees.
440s   Evaluating internal representation of mux trees.
440s   Analyzing evaluation results.
440s Removed 0 multiplexer ports.
440s <suppressed ~7 debug messages>
440s 
440s 2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
440s   Optimizing cells in module \top.
440s Performed a total of 0 changes.
440s 
440s 2.13.5. Executing OPT_MERGE pass (detect identical cells).
440s Finding identical cells in module `\top'.
440s Removed a total of 0 cells.
440s 
440s 2.13.6. Executing OPT_DFF pass (perform DFF optimizations).
440s 
440s 2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
440s Finding unused cells or wires in module \top..
440s 
440s 2.13.8. Executing OPT_EXPR pass (perform const folding).
440s Optimizing module top.
440s 
440s 2.13.9. Finished OPT passes. (There is nothing left to do.)
440s 
440s 2.14. Executing WREDUCE pass (reducing word size of cells).
440s Removed top 31 bits (of 32) from port B of cell top.$add$rgb.v:19$382 ($add).
440s Removed top 30 bits (of 32) from port A of cell top.$mul$rgb.v:35$384 ($mul).
440s Removed top 2 bits (of 12) from port B of cell top.$mul$rgb.v:35$384 ($mul).
440s Removed top 20 bits (of 32) from port Y of cell top.$mul$rgb.v:35$384 ($mul).
440s Removed top 22 bits (of 32) from port A of cell top.$add$rgb.v:35$385 ($add).
440s Removed top 20 bits (of 32) from port B of cell top.$add$rgb.v:35$385 ($add).
440s Removed top 19 bits (of 32) from port Y of cell top.$add$rgb.v:35$385 ($add).
440s Removed top 1 bits (of 2) from port B of cell top.$eq$rgb.v:36$386 ($eq).
440s Removed top 20 bits (of 32) from port A of cell top.$sub$rgb.v:36$387 ($sub).
440s Removed top 19 bits (of 32) from port Y of cell top.$sub$rgb.v:36$387 ($sub).
440s Removed top 22 bits (of 32) from mux cell top.$ternary$rgb.v:37$390 ($mux).
440s Removed top 20 bits (of 32) from mux cell top.$ternary$rgb.v:35$392 ($mux).
440s Removed top 22 bits (of 32) from port A of cell top.$sub$rgb.v:40$394 ($sub).
440s Removed top 2 bits (of 12) from port B of cell top.$sub$rgb.v:40$394 ($sub).
440s Removed top 21 bits (of 32) from port Y of cell top.$sub$rgb.v:40$394 ($sub).
440s Removed top 20 bits (of 32) from mux cell top.$ternary$rgb.v:40$404 ($mux).
440s Removed top 20 bits (of 32) from port A of cell top.$sub$rgb.v:48$410 ($sub).
440s Removed top 20 bits (of 32) from port B of cell top.$sub$rgb.v:48$410 ($sub).
440s Removed top 19 bits (of 32) from port Y of cell top.$sub$rgb.v:48$410 ($sub).
440s Removed top 20 bits (of 32) from mux cell top.$ternary$rgb.v:46$414 ($mux).
440s Removed top 31 bits (of 32) from port B of cell top.$add$rgb.v:57$416 ($add).
440s Removed top 20 bits (of 32) from port Y of cell top.$add$rgb.v:57$416 ($add).
440s Removed top 1 bits (of 13) from port Y of cell top.$add$rgb.v:35$385 ($add).
440s Removed top 20 bits (of 32) from mux cell top.$ternary$rgb.v:36$391 ($mux).
440s Removed top 20 bits (of 32) from mux cell top.$ternary$rgb.v:41$403 ($mux).
440s Removed top 20 bits (of 32) from mux cell top.$ternary$rgb.v:47$413 ($mux).
440s Removed top 20 bits (of 32) from mux cell top.$ternary$rgb.v:42$401 ($mux).
440s Removed top 20 bits (of 32) from mux cell top.$ternary$rgb.v:48$411 ($mux).
440s Removed top 1 bits (of 13) from port Y of cell top.$sub$rgb.v:36$387 ($sub).
440s Removed top 1 bits (of 13) from port Y of cell top.$sub$rgb.v:48$410 ($sub).
440s Removed top 20 bits (of 32) from wire top.$add$rgb.v:35$385_Y.
440s Removed top 20 bits (of 32) from wire top.$mul$rgb.v:35$384_Y.
440s Removed top 20 bits (of 32) from wire top.$sub$rgb.v:36$387_Y.
440s Removed top 20 bits (of 32) from wire top.$sub$rgb.v:48$410_Y.
440s Removed top 20 bits (of 32) from wire top.$ternary$rgb.v:36$391_Y.
440s Removed top 22 bits (of 32) from wire top.$ternary$rgb.v:37$390_Y.
440s Removed top 20 bits (of 32) from wire top.$ternary$rgb.v:41$403_Y.
440s Removed top 20 bits (of 32) from wire top.$ternary$rgb.v:42$401_Y.
440s Removed top 20 bits (of 32) from wire top.$ternary$rgb.v:47$413_Y.
440s Removed top 21 bits (of 32) from wire top.$ternary$rgb.v:48$411_Y.
440s Removed top 2 bits (of 12) from wire top.fade_div4.
440s 
440s 2.15. Executing PEEPOPT pass (run peephole optimizers).
440s 
440s 2.16. Executing OPT_CLEAN pass (remove unused cells and wires).
440s Finding unused cells or wires in module \top..
440s Removed 0 unused cells and 15 unused wires.
440s <suppressed ~1 debug messages>
440s 
440s 2.17. Executing SHARE pass (SAT-based resource sharing).
440s 
440s 2.18. Executing TECHMAP pass (map to technology primitives).
440s 
440s 2.18.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v
440s Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation.
440s Generating RTLIL representation for module `\_90_lut_cmp_'.
440s Successfully finished Verilog frontend.
440s 
440s 2.18.2. Continuing TECHMAP pass.
440s No more expansions possible.
440s <suppressed ~36 debug messages>
440s 
440s 2.19. Executing OPT_EXPR pass (perform const folding).
440s Optimizing module top.
440s 
440s 2.20. Executing OPT_CLEAN pass (remove unused cells and wires).
440s Finding unused cells or wires in module \top..
440s 
440s 2.21. Executing ALUMACC pass (create $alu and $macc cells).
440s Extracting $alu and $macc cells in module top:
440s   creating $macc model for $add$rgb.v:19$382 ($add).
440s   creating $macc model for $add$rgb.v:35$385 ($add).
440s   creating $macc model for $add$rgb.v:57$416 ($add).
440s   creating $macc model for $mul$rgb.v:35$384 ($mul).
440s   creating $macc model for $sub$rgb.v:36$387 ($sub).
440s   creating $macc model for $sub$rgb.v:40$394 ($sub).
440s   creating $macc model for $sub$rgb.v:48$410 ($sub).
440s   creating $alu model for $macc $sub$rgb.v:48$410.
440s   creating $alu model for $macc $sub$rgb.v:40$394.
440s   creating $alu model for $macc $sub$rgb.v:36$387.
440s   creating $alu model for $macc $add$rgb.v:57$416.
440s   creating $alu model for $macc $add$rgb.v:35$385.
440s   creating $alu model for $macc $add$rgb.v:19$382.
440s   creating $macc cell for $mul$rgb.v:35$384: $auto$alumacc.cc:365:replace_macc$504
440s   creating $alu model for $lt$rgb.v:58$417 ($lt): new $alu
440s   creating $alu model for $lt$rgb.v:59$419 ($lt): new $alu
440s   creating $alu model for $lt$rgb.v:60$421 ($lt): new $alu
440s   creating $alu cell for $lt$rgb.v:60$421: $auto$alumacc.cc:485:replace_alu$508
440s   creating $alu cell for $lt$rgb.v:59$419: $auto$alumacc.cc:485:replace_alu$513
440s   creating $alu cell for $lt$rgb.v:58$417: $auto$alumacc.cc:485:replace_alu$524
440s   creating $alu cell for $add$rgb.v:19$382: $auto$alumacc.cc:485:replace_alu$535
440s   creating $alu cell for $add$rgb.v:35$385: $auto$alumacc.cc:485:replace_alu$538
440s   creating $alu cell for $add$rgb.v:57$416: $auto$alumacc.cc:485:replace_alu$541
440s   creating $alu cell for $sub$rgb.v:36$387: $auto$alumacc.cc:485:replace_alu$544
440s   creating $alu cell for $sub$rgb.v:40$394: $auto$alumacc.cc:485:replace_alu$547
440s   creating $alu cell for $sub$rgb.v:48$410: $auto$alumacc.cc:485:replace_alu$550
440s   created 9 $alu and 1 $macc cells.
440s 
440s 2.22. Executing OPT pass (performing simple optimizations).
440s 
440s 2.22.1. Executing OPT_EXPR pass (perform const folding).
440s Optimizing module top.
440s <suppressed ~3 debug messages>
440s 
440s 2.22.2. Executing OPT_MERGE pass (detect identical cells).
440s Finding identical cells in module `\top'.
440s Removed a total of 0 cells.
440s 
440s 2.22.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
440s Running muxtree optimizer on module \top..
440s   Creating internal representation of mux trees.
440s   Evaluating internal representation of mux trees.
440s   Analyzing evaluation results.
440s Removed 0 multiplexer ports.
440s <suppressed ~7 debug messages>
440s 
440s 2.22.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
440s   Optimizing cells in module \top.
440s Performed a total of 0 changes.
440s 
440s 2.22.5. Executing OPT_MERGE pass (detect identical cells).
440s Finding identical cells in module `\top'.
440s Removed a total of 0 cells.
440s 
440s 2.22.6. Executing OPT_DFF pass (perform DFF optimizations).
440s 
440s 2.22.7. Executing OPT_CLEAN pass (remove unused cells and wires).
440s Finding unused cells or wires in module \top..
440s Removed 3 unused cells and 6 unused wires.
440s <suppressed ~4 debug messages>
440s 
440s 2.22.8. Executing OPT_EXPR pass (perform const folding).
440s Optimizing module top.
440s 
440s 2.22.9. Rerunning OPT passes. (Maybe there is more to do..)
440s 
440s 2.22.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
440s Running muxtree optimizer on module \top..
440s   Creating internal representation of mux trees.
440s   Evaluating internal representation of mux trees.
440s   Analyzing evaluation results.
440s Removed 0 multiplexer ports.
440s <suppressed ~7 debug messages>
440s 
440s 2.22.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
440s   Optimizing cells in module \top.
440s Performed a total of 0 changes.
440s 
440s 2.22.12. Executing OPT_MERGE pass (detect identical cells).
440s Finding identical cells in module `\top'.
440s Removed a total of 0 cells.
440s 
440s 2.22.13. Executing OPT_DFF pass (perform DFF optimizations).
440s 
440s 2.22.14. Executing OPT_CLEAN pass (remove unused cells and wires).
440s Finding unused cells or wires in module \top..
440s 
440s 2.22.15. Executing OPT_EXPR pass (perform const folding).
440s Optimizing module top.
440s 
440s 2.22.16. Finished OPT passes. (There is nothing left to do.)
440s 
440s 2.23. Executing MEMORY pass.
440s 
440s 2.23.1. Executing OPT_MEM pass (optimize memories).
440s Performed a total of 0 transformations.
440s 
440s 2.23.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
440s Performed a total of 0 transformations.
440s 
440s 2.23.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
440s 
440s 2.23.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
440s 
440s 2.23.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
440s 
440s 2.23.6. Executing OPT_CLEAN pass (remove unused cells and wires).
440s Finding unused cells or wires in module \top..
440s 
440s 2.23.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
440s 
440s 2.23.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
440s Performed a total of 0 transformations.
440s 
440s 2.23.9. Executing OPT_CLEAN pass (remove unused cells and wires).
440s Finding unused cells or wires in module \top..
440s 
440s 2.23.10. Executing MEMORY_COLLECT pass (generating $mem cells).
440s 
440s 2.24. Executing OPT_CLEAN pass (remove unused cells and wires).
440s Finding unused cells or wires in module \top..
440s 
440s 2.25. Executing MEMORY_LIBMAP pass (mapping memories to cells).
440s 
440s 2.26. Executing TECHMAP pass (map to technology primitives).
440s 
440s 2.26.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v
441s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation.
441s Generating RTLIL representation for module `\$__ICE40_RAM4K_'.
441s Successfully finished Verilog frontend.
441s 
441s 2.26.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/spram_map.v
441s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/spram_map.v' to AST representation.
441s Generating RTLIL representation for module `\$__ICE40_SPRAM_'.
441s Successfully finished Verilog frontend.
441s 
441s 2.26.3. Continuing TECHMAP pass.
441s No more expansions possible.
441s <suppressed ~4 debug messages>
441s 
441s 2.27. Executing ICE40_BRAMINIT pass.
441s 
441s 2.28. Executing OPT pass (performing simple optimizations).
441s 
441s 2.28.1. Executing OPT_EXPR pass (perform const folding).
441s Optimizing module top.
441s <suppressed ~12 debug messages>
441s 
441s 2.28.2. Executing OPT_MERGE pass (detect identical cells).
441s Finding identical cells in module `\top'.
441s <suppressed ~30 debug messages>
441s Removed a total of 10 cells.
441s 
441s 2.28.3. Executing OPT_DFF pass (perform DFF optimizations).
441s 
441s 2.28.4. Executing OPT_CLEAN pass (remove unused cells and wires).
441s Finding unused cells or wires in module \top..
441s Removed 0 unused cells and 22 unused wires.
441s <suppressed ~1 debug messages>
441s 
441s 2.28.5. Finished fast OPT passes.
441s 
441s 2.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
441s 
441s 2.30. Executing OPT pass (performing simple optimizations).
441s 
441s 2.30.1. Executing OPT_EXPR pass (perform const folding).
441s Optimizing module top.
441s 
441s 2.30.2. Executing OPT_MERGE pass (detect identical cells).
441s Finding identical cells in module `\top'.
441s Removed a total of 0 cells.
441s 
441s 2.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
441s Running muxtree optimizer on module \top..
441s   Creating internal representation of mux trees.
441s   Evaluating internal representation of mux trees.
441s   Analyzing evaluation results.
441s Removed 0 multiplexer ports.
441s <suppressed ~7 debug messages>
441s 
441s 2.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
441s   Optimizing cells in module \top.
441s Performed a total of 0 changes.
441s 
441s 2.30.5. Executing OPT_MERGE pass (detect identical cells).
441s Finding identical cells in module `\top'.
441s Removed a total of 0 cells.
441s 
441s 2.30.6. Executing OPT_DFF pass (perform DFF optimizations).
441s 
441s 2.30.7. Executing OPT_CLEAN pass (remove unused cells and wires).
441s Finding unused cells or wires in module \top..
441s 
441s 2.30.8. Executing OPT_EXPR pass (perform const folding).
441s Optimizing module top.
441s 
441s 2.30.9. Finished OPT passes. (There is nothing left to do.)
441s 
441s 2.31. Executing ICE40_WRAPCARRY pass (wrap carries).
441s 
441s 2.32. Executing TECHMAP pass (map to technology primitives).
441s 
441s 2.32.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v
441s Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation.
441s Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
441s Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
441s Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
441s Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
441s Generating RTLIL representation for module `\_90_simplemap_various'.
441s Generating RTLIL representation for module `\_90_simplemap_registers'.
441s Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
441s Generating RTLIL representation for module `\_90_shift_shiftx'.
441s Generating RTLIL representation for module `\_90_fa'.
441s Generating RTLIL representation for module `\_90_lcu'.
441s Generating RTLIL representation for module `\_90_alu'.
441s Generating RTLIL representation for module `\_90_macc'.
441s Generating RTLIL representation for module `\_90_alumacc'.
441s Generating RTLIL representation for module `\$__div_mod_u'.
441s Generating RTLIL representation for module `\$__div_mod_trunc'.
441s Generating RTLIL representation for module `\_90_div'.
441s Generating RTLIL representation for module `\_90_mod'.
441s Generating RTLIL representation for module `\$__div_mod_floor'.
441s Generating RTLIL representation for module `\_90_divfloor'.
441s Generating RTLIL representation for module `\_90_modfloor'.
441s Generating RTLIL representation for module `\_90_pow'.
441s Generating RTLIL representation for module `\_90_pmux'.
441s Generating RTLIL representation for module `\_90_demux'.
441s Generating RTLIL representation for module `\_90_lut'.
441s Successfully finished Verilog frontend.
441s 
441s 2.32.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v
441s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation.
441s Generating RTLIL representation for module `\_80_ice40_alu'.
441s Successfully finished Verilog frontend.
441s 
441s 2.32.3. Continuing TECHMAP pass.
441s Using extmapper simplemap for cells of type $not.
441s Using template $paramod$b40e0f66d01d243904da425c63ff802ae596888e\_80_ice40_alu for cells of type $alu.
441s Using extmapper simplemap for cells of type $logic_not.
441s Using template $paramod$ee3d784672cdb1cb32d9a801a3af776716f16b74\_80_ice40_alu for cells of type $alu.
441s Using template $paramod$8f780356cb6cdb52f6a744190131b65634639c4e\_80_ice40_alu for cells of type $alu.
441s Using extmapper simplemap for cells of type $eq.
441s Using extmapper simplemap for cells of type $mux.
441s Using extmapper simplemap for cells of type $reduce_and.
441s Using extmapper maccmap for cells of type $macc.
441s   add \ctr [29:20] * 2'11 (10x2 bits, unsigned)
441s Using extmapper simplemap for cells of type $or.
441s Using template $paramod$6a42b6fefed750f8a1c58eab59479d960557103c\_80_ice40_alu for cells of type $alu.
441s Using extmapper simplemap for cells of type $dff.
441s Using extmapper simplemap for cells of type $and.
441s Using extmapper simplemap for cells of type $xor.
441s Using extmapper simplemap for cells of type $pos.
441s No more expansions possible.
441s <suppressed ~245 debug messages>
441s 
441s 2.33. Executing OPT pass (performing simple optimizations).
441s 
441s 2.33.1. Executing OPT_EXPR pass (perform const folding).
441s Optimizing module top.
441s <suppressed ~301 debug messages>
441s 
441s 2.33.2. Executing OPT_MERGE pass (detect identical cells).
441s Finding identical cells in module `\top'.
441s <suppressed ~222 debug messages>
441s Removed a total of 74 cells.
441s 
441s 2.33.3. Executing OPT_DFF pass (perform DFF optimizations).
441s 
441s 2.33.4. Executing OPT_CLEAN pass (remove unused cells and wires).
441s Finding unused cells or wires in module \top..
441s Removed 43 unused cells and 146 unused wires.
441s <suppressed ~44 debug messages>
441s 
441s 2.33.5. Finished fast OPT passes.
441s 
441s 2.34. Executing ICE40_OPT pass (performing simple optimizations).
441s 
441s 2.34.1. Running ICE40 specific optimizations.
441s Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$535.slice[0].carry: CO=\ctr [0]
441s Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$538.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$538.B [0]
441s Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$541.slice[0].carry: CO=\pwm_ctr [0]
441s Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$839.slice[0].carry: CO=1'0
441s Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$839.slice[11].carry: CO=1'0
441s 
441s 2.34.2. Executing OPT_EXPR pass (perform const folding).
441s Optimizing module top.
441s 
441s 2.34.3. Executing OPT_MERGE pass (detect identical cells).
441s Finding identical cells in module `\top'.
441s Removed a total of 0 cells.
441s 
441s 2.34.4. Executing OPT_DFF pass (perform DFF optimizations).
441s 
441s 2.34.5. Executing OPT_CLEAN pass (remove unused cells and wires).
441s Finding unused cells or wires in module \top..
441s Removed 0 unused cells and 1 unused wires.
441s <suppressed ~1 debug messages>
441s 
441s 2.34.6. Rerunning OPT passes. (Removed registers in this run.)
441s 
441s 2.34.7. Running ICE40 specific optimizations.
441s 
441s 2.34.8. Executing OPT_EXPR pass (perform const folding).
441s Optimizing module top.
441s 
441s 2.34.9. Executing OPT_MERGE pass (detect identical cells).
441s Finding identical cells in module `\top'.
441s Removed a total of 0 cells.
441s 
441s 2.34.10. Executing OPT_DFF pass (perform DFF optimizations).
441s 
441s 2.34.11. Executing OPT_CLEAN pass (remove unused cells and wires).
441s Finding unused cells or wires in module \top..
441s 
441s 2.34.12. Finished OPT passes. (There is nothing left to do.)
441s 
441s 2.35. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
441s 
441s 2.36. Executing TECHMAP pass (map to technology primitives).
441s 
441s 2.36.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v
441s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation.
441s Generating RTLIL representation for module `\$_DFF_N_'.
441s Generating RTLIL representation for module `\$_DFF_P_'.
441s Generating RTLIL representation for module `\$_DFFE_NP_'.
441s Generating RTLIL representation for module `\$_DFFE_PP_'.
441s Generating RTLIL representation for module `\$_DFF_NP0_'.
441s Generating RTLIL representation for module `\$_DFF_NP1_'.
441s Generating RTLIL representation for module `\$_DFF_PP0_'.
441s Generating RTLIL representation for module `\$_DFF_PP1_'.
441s Generating RTLIL representation for module `\$_DFFE_NP0P_'.
441s Generating RTLIL representation for module `\$_DFFE_NP1P_'.
441s Generating RTLIL representation for module `\$_DFFE_PP0P_'.
441s Generating RTLIL representation for module `\$_DFFE_PP1P_'.
441s Generating RTLIL representation for module `\$_SDFF_NP0_'.
441s Generating RTLIL representation for module `\$_SDFF_NP1_'.
441s Generating RTLIL representation for module `\$_SDFF_PP0_'.
441s Generating RTLIL representation for module `\$_SDFF_PP1_'.
441s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
441s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
441s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
441s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
441s Successfully finished Verilog frontend.
441s 
441s 2.36.2. Continuing TECHMAP pass.
441s Using template \$_DFF_P_ for cells of type $_DFF_P_.
441s No more expansions possible.
441s <suppressed ~69 debug messages>
441s 
441s 2.37. Executing OPT_EXPR pass (perform const folding).
441s Optimizing module top.
441s 
441s 2.38. Executing SIMPLEMAP pass (map simple cells to gate primitives).
441s Mapping top.$auto$alumacc.cc:485:replace_alu$535.slice[0].carry ($lut).
441s Mapping top.$auto$alumacc.cc:485:replace_alu$538.slice[0].carry ($lut).
441s Mapping top.$auto$alumacc.cc:485:replace_alu$541.slice[0].carry ($lut).
441s Mapping top.$auto$maccmap.cc:240:synth$839.slice[0].carry ($lut).
441s Mapping top.$auto$maccmap.cc:240:synth$839.slice[11].carry ($lut).
441s 
441s 2.39. Executing ICE40_OPT pass (performing simple optimizations).
441s 
441s 2.39.1. Running ICE40 specific optimizations.
441s 
441s 2.39.2. Executing OPT_EXPR pass (perform const folding).
441s Optimizing module top.
441s <suppressed ~74 debug messages>
441s 
441s 2.39.3. Executing OPT_MERGE pass (detect identical cells).
441s Finding identical cells in module `\top'.
441s <suppressed ~15 debug messages>
441s Removed a total of 5 cells.
441s 
441s 2.39.4. Executing OPT_DFF pass (perform DFF optimizations).
441s 
441s 2.39.5. Executing OPT_CLEAN pass (remove unused cells and wires).
441s Finding unused cells or wires in module \top..
441s Removed 0 unused cells and 209 unused wires.
441s <suppressed ~1 debug messages>
441s 
441s 2.39.6. Rerunning OPT passes. (Removed registers in this run.)
441s 
441s 2.39.7. Running ICE40 specific optimizations.
441s 
441s 2.39.8. Executing OPT_EXPR pass (perform const folding).
441s Optimizing module top.
441s 
441s 2.39.9. Executing OPT_MERGE pass (detect identical cells).
441s Finding identical cells in module `\top'.
441s Removed a total of 0 cells.
441s 
441s 2.39.10. Executing OPT_DFF pass (perform DFF optimizations).
441s 
441s 2.39.11. Executing OPT_CLEAN pass (remove unused cells and wires).
441s Finding unused cells or wires in module \top..
441s 
441s 2.39.12. Finished OPT passes. (There is nothing left to do.)
441s 
441s 2.40. Executing TECHMAP pass (map to technology primitives).
441s 
441s 2.40.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v
441s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation.
441s Generating RTLIL representation for module `\$_DLATCH_N_'.
441s Generating RTLIL representation for module `\$_DLATCH_P_'.
441s Successfully finished Verilog frontend.
441s 
441s 2.40.2. Continuing TECHMAP pass.
441s No more expansions possible.
441s <suppressed ~4 debug messages>
441s 
441s 2.41. Executing ABC pass (technology mapping using ABC).
441s 
441s 2.41.1. Extracting gate netlist of module `\top' to `<abc-temp-dir>/input.blif'..
441s Extracted 213 gates and 266 wires to a netlist network with 52 inputs and 52 outputs.
441s 
441s 2.41.1.1. Executing ABC.
441s Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
441s ABC: ABC command line: "source <abc-temp-dir>/abc.script".
441s ABC: 
441s ABC: + read_blif <abc-temp-dir>/input.blif 
441s ABC: + read_lut <abc-temp-dir>/lutdefs.txt 
441s ABC: + strash 
441s ABC: + &get -n 
441s ABC: + &fraig -x 
441s ABC: + &put 
441s ABC: + scorr 
441s ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
441s ABC: + dc2 
441s ABC: + dretime 
441s ABC: + strash 
441s ABC: + dch -f 
441s ABC: + if 
441s ABC: + mfs2 
441s ABC: + lutpack -S 1 
441s ABC: + dress <abc-temp-dir>/input.blif 
441s ABC: Total number of equiv classes                =      68.
441s ABC: Participating nodes from both networks       =     153.
441s ABC: Participating nodes from the first network   =      67. (  71.28 % of nodes)
441s ABC: Participating nodes from the second network  =      86. (  91.49 % of nodes)
441s ABC: Node pairs (any polarity)                    =      67. (  71.28 % of names can be moved)
441s ABC: Node pairs (same polarity)                   =      62. (  65.96 % of names can be moved)
441s ABC: Total runtime =     0.04 sec
441s ABC: + write_blif <abc-temp-dir>/output.blif 
441s 
441s 2.41.1.2. Re-integrating ABC results.
441s ABC RESULTS:              $lut cells:       93
441s ABC RESULTS:        internal signals:      162
441s ABC RESULTS:           input signals:       52
441s ABC RESULTS:          output signals:       52
441s Removing temp directory.
441s 
441s 2.42. Executing ICE40_WRAPCARRY pass (wrap carries).
441s 
441s 2.43. Executing TECHMAP pass (map to technology primitives).
441s 
441s 2.43.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v
441s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation.
441s Generating RTLIL representation for module `\$_DFF_N_'.
441s Generating RTLIL representation for module `\$_DFF_P_'.
441s Generating RTLIL representation for module `\$_DFFE_NP_'.
441s Generating RTLIL representation for module `\$_DFFE_PP_'.
441s Generating RTLIL representation for module `\$_DFF_NP0_'.
441s Generating RTLIL representation for module `\$_DFF_NP1_'.
441s Generating RTLIL representation for module `\$_DFF_PP0_'.
441s Generating RTLIL representation for module `\$_DFF_PP1_'.
441s Generating RTLIL representation for module `\$_DFFE_NP0P_'.
441s Generating RTLIL representation for module `\$_DFFE_NP1P_'.
441s Generating RTLIL representation for module `\$_DFFE_PP0P_'.
441s Generating RTLIL representation for module `\$_DFFE_PP1P_'.
441s Generating RTLIL representation for module `\$_SDFF_NP0_'.
441s Generating RTLIL representation for module `\$_SDFF_NP1_'.
441s Generating RTLIL representation for module `\$_SDFF_PP0_'.
441s Generating RTLIL representation for module `\$_SDFF_PP1_'.
441s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
441s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
441s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
441s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
441s Successfully finished Verilog frontend.
441s 
441s 2.43.2. Continuing TECHMAP pass.
441s No more expansions possible.
441s <suppressed ~22 debug messages>
441s Removed 39 unused cells and 151 unused wires.
441s 
441s 2.44. Executing OPT_LUT pass (optimize LUTs).
441s Discovering LUTs.
441s Number of LUTs:      156
441s   1-LUT               14
441s   2-LUT                8
441s   3-LUT               71
441s   4-LUT               63
441s   with \SB_CARRY    (#0)   60
441s   with \SB_CARRY    (#1)   61
441s 
441s Eliminating LUTs.
441s Number of LUTs:      156
441s   1-LUT               14
441s   2-LUT                8
441s   3-LUT               71
441s   4-LUT               63
441s   with \SB_CARRY    (#0)   60
441s   with \SB_CARRY    (#1)   61
441s 
441s Combining LUTs.
441s Number of LUTs:      156
441s   1-LUT               14
441s   2-LUT                8
441s   3-LUT               71
441s   4-LUT               63
441s   with \SB_CARRY    (#0)   60
441s   with \SB_CARRY    (#1)   61
441s 
441s Eliminated 0 LUTs.
441s Combined 0 LUTs.
441s <suppressed ~948 debug messages>
441s 
441s 2.45. Executing TECHMAP pass (map to technology primitives).
441s 
441s 2.45.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v
441s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation.
441s Generating RTLIL representation for module `\$lut'.
441s Successfully finished Verilog frontend.
441s 
441s 2.45.2. Continuing TECHMAP pass.
441s Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut.
441s Using template $paramod$6382f7860648fdb6f8a8dc690c25a62882cc501b\$lut for cells of type $lut.
441s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
441s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001111 for cells of type $lut.
441s Using template $paramod$4256c04bb9e86f873ba2a112f005a99a8ed41d05\$lut for cells of type $lut.
441s Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut.
441s Using template $paramod$99a2a175d178a040bb1ffceb53184fb0f59423c6\$lut for cells of type $lut.
441s Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011\$lut for cells of type $lut.
441s Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut.
441s Using template $paramod$d9d6d961a139aa8625028a83327b5b5f5f63381a\$lut for cells of type $lut.
441s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
441s Using template $paramod$9b2a235b71197211341028b71d3bf4a68e17ea7a\$lut for cells of type $lut.
441s Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut.
441s Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912\$lut for cells of type $lut.
441s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
441s Using template $paramod$cc14edb43bcbbd83b718cef08414cb23048bb6d0\$lut for cells of type $lut.
441s Using template $paramod$a56d70ffd309b1185b27bc1a5092003d8bf696be\$lut for cells of type $lut.
441s Using template $paramod$332a399730bfc61adea04021a76b1c4e4030f37d\$lut for cells of type $lut.
441s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000010 for cells of type $lut.
441s Using template $paramod$44f084d3146d098e660e97ec68aa8e73f67e1794\$lut for cells of type $lut.
441s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut.
441s Using template $paramod$59c595af41d4a5cce2d588c3a5f1342749ce7a77\$lut for cells of type $lut.
441s Using template $paramod$51e1e8d562a5735599c3873fdaa9d44b4ebfefd6\$lut for cells of type $lut.
441s No more expansions possible.
441s <suppressed ~458 debug messages>
441s Removed 0 unused cells and 327 unused wires.
441s 
441s 2.46. Executing AUTONAME pass.
441s Renamed 3173 objects in module top (23 iterations).
441s <suppressed ~344 debug messages>
441s 
441s 2.47. Executing HIERARCHY pass (managing design hierarchy).
441s 
441s 2.47.1. Analyzing design hierarchy..
441s Top module:  \top
441s 
441s 2.47.2. Analyzing design hierarchy..
441s Top module:  \top
441s Removed 0 unused modules.
441s 
441s 2.48. Printing statistics.
441s 
441s === top ===
441s 
441s    Number of wires:                 59
441s    Number of wire bits:            435
441s    Number of public wires:          59
441s    Number of public wire bits:     435
441s    Number of memories:               0
441s    Number of memory bits:            0
441s    Number of processes:              0
441s    Number of cells:                301
441s      SB_CARRY                       96
441s      SB_DFF                         47
441s      SB_HFOSC                        1
441s      SB_LUT4                       156
441s      SB_RGBA_DRV                     1
441s 
441s 2.49. Executing CHECK pass (checking for obvious problems).
441s Checking module top...
441s Found and reported 0 problems.
441s 
441s 2.50. Executing JSON backend.
441s 
441s End of script. Logfile hash: d493eeeb0c, CPU: user 1.27s system 0.03s, MEM: 20.00 MB peak
441s Yosys 0.33 (git sha1 2584903a060)
441s Time spent: 45% 13x read_verilog (0 sec), 11% 1x abc (0 sec), ...
441s nextpnr-ice40 --up5k --package sg48 --asc rgb.asc --pcf rgb.pcf --json rgb.json
441s Info: constrained 'RGB0' to bel 'X4/Y31/io0'
441s Info: constrained 'RGB1' to bel 'X5/Y31/io0'
441s Info: constrained 'RGB2' to bel 'X6/Y31/io0'
441s Info: constraining clock net 'clk' to 32.00 MHz
441s 
441s Info: Packing constants..
441s Info: Packing IOs..
441s Info: RGB2 use by SB_RGBA_DRV/SB_RGB_DRV RGBA_DRIVER, not creating SB_IO
441s Info: RGB1 use by SB_RGBA_DRV/SB_RGB_DRV RGBA_DRIVER, not creating SB_IO
441s Info: RGB0 use by SB_RGBA_DRV/SB_RGB_DRV RGBA_DRIVER, not creating SB_IO
441s Info: Packing LUT-FFs..
441s Info:      110 LCs used as LUT4 only
441s Info:       46 LCs used as LUT4 and DFF
441s Info: Packing non-LUT FFs..
441s Info:        1 LCs used as DFF only
441s Info: Packing carries..
441s Info:       38 LCs used as CARRY only
441s Info: Packing indirect carry+LUT pairs...
441s Info:       13 LUTs merged into carry LCs
441s Info: Packing RAMs..
441s Info: Placing PLLs..
441s Info: Packing special functions..
441s Info:   constrained ICESTORM_HFOSC 'inthosc_OSC' to X0/Y31/hfosc_1
441s Warning:     Overriding derived constraint of 48.0 MHz on net clk with user-specified constraint of 32.0 MHz.
441s Info:   constrained SB_RGBA_DRV 'RGBA_DRIVER' to X0/Y30/rgba_drv_0
441s Info: Packing PLLs..
441s Info: Promoting globals..
441s Info: Constraining chains...
441s Info:        4 LCs used to legalise carry chains.
441s Info: Checksum: 0xa69ff3c3
441s 
441s Info: Annotating ports with timing budgets for target frequency 12.00 MHz
441s Info: Checksum: 0xf9be7a50
441s 
441s Info: Device utilisation:
441s Info: 	         ICESTORM_LC:   188/ 5280     3%
441s Info: 	        ICESTORM_RAM:     0/   30     0%
441s Info: 	               SB_IO:     0/   96     0%
441s Info: 	               SB_GB:     1/    8    12%
441s Info: 	        ICESTORM_PLL:     0/    1     0%
441s Info: 	         SB_WARMBOOT:     0/    1     0%
441s Info: 	        ICESTORM_DSP:     0/    8     0%
441s Info: 	      ICESTORM_HFOSC:     1/    1   100%
441s Info: 	      ICESTORM_LFOSC:     0/    1     0%
441s Info: 	              SB_I2C:     0/    2     0%
441s Info: 	              SB_SPI:     0/    2     0%
441s Info: 	              IO_I3C:     0/    2     0%
441s Info: 	         SB_LEDDA_IP:     0/    1     0%
441s Info: 	         SB_RGBA_DRV:     1/    1   100%
441s Info: 	      ICESTORM_SPRAM:     0/    4     0%
441s 
441s Info: Placed 3 cells based on constraints.
441s Info: Creating initial analytic placement for 88 cells, random placement wirelen = 3874.
441s Info:     at initial placer iter 0, wirelen = 40
441s Info:     at initial placer iter 1, wirelen = 39
441s Info:     at initial placer iter 2, wirelen = 39
441s Info:     at initial placer iter 3, wirelen = 39
441s Info: Running main analytical placer, max placement attempts per cell = 10000.
441s Info:     at iteration #1, type ICESTORM_LC: wirelen solved = 39, spread = 683, legal = 691; time = 0.00s
441s Info:     at iteration #2, type ICESTORM_LC: wirelen solved = 76, spread = 657, legal = 665; time = 0.00s
441s Info:     at iteration #3, type ICESTORM_LC: wirelen solved = 46, spread = 646, legal = 650; time = 0.00s
441s Info:     at iteration #4, type ICESTORM_LC: wirelen solved = 51, spread = 615, legal = 645; time = 0.00s
441s Info:     at iteration #5, type ICESTORM_LC: wirelen solved = 90, spread = 592, legal = 615; time = 0.00s
441s Info:     at iteration #6, type ICESTORM_LC: wirelen solved = 62, spread = 552, legal = 574; time = 0.00s
441s Info:     at iteration #7, type ICESTORM_LC: wirelen solved = 69, spread = 555, legal = 561; time = 0.00s
441s Info:     at iteration #8, type ICESTORM_LC: wirelen solved = 74, spread = 562, legal = 609; time = 0.00s
441s Info:     at iteration #9, type ICESTORM_LC: wirelen solved = 94, spread = 563, legal = 578; time = 0.00s
441s Info:     at iteration #10, type ICESTORM_LC: wirelen solved = 109, spread = 545, legal = 568; time = 0.00s
441s Info:     at iteration #11, type ICESTORM_LC: wirelen solved = 121, spread = 556, legal = 617; time = 0.00s
441s Info:     at iteration #12, type ICESTORM_LC: wirelen solved = 86, spread = 543, legal = 554; time = 0.00s
441s Info:     at iteration #13, type ICESTORM_LC: wirelen solved = 120, spread = 524, legal = 557; time = 0.00s
441s Info:     at iteration #14, type ICESTORM_LC: wirelen solved = 102, spread = 533, legal = 546; time = 0.00s
441s Info:     at iteration #15, type ICESTORM_LC: wirelen solved = 147, spread = 578, legal = 596; time = 0.00s
441s Info:     at iteration #16, type ICESTORM_LC: wirelen solved = 213, spread = 537, legal = 554; time = 0.00s
441s Info:     at iteration #17, type ICESTORM_LC: wirelen solved = 166, spread = 587, legal = 628; time = 0.00s
441s Info:     at iteration #18, type ICESTORM_LC: wirelen solved = 181, spread = 649, legal = 676; time = 0.00s
441s Info:     at iteration #19, type ICESTORM_LC: wirelen solved = 197, spread = 658, legal = 722; time = 0.00s
441s Info: HeAP Placer Time: 0.12s
441s Info:   of which solving equations: 0.09s
441s Info:   of which spreading cells: 0.00s
441s Info:   of which strict legalisation: 0.00s
441s 
441s Info: Running simulated annealing placer for refinement.
441s Info:   at iteration #1: temp = 0.000000, timing cost = 115, wirelen = 546
441s Info:   at iteration #5: temp = 0.000000, timing cost = 112, wirelen = 463
441s Info:   at iteration #10: temp = 0.000000, timing cost = 110, wirelen = 438
441s Info:   at iteration #12: temp = 0.000000, timing cost = 108, wirelen = 436 
441s Info: SA placement time 0.07s
441s 
441s Info: Max frequency for clock 'clk': 40.85 MHz (PASS at 32.00 MHz)
441s 
441s Info: Max delay posedge clk -> <async>: 6.13 ns
441s 
441s Info: Slack histogram:
441s Info:  legend: * represents 1 endpoint(s)
441s Info:          + represents [1,1) endpoint(s)
441s Info: [  6770,  10325) |**** 
441s Info: [ 10325,  13880) |* 
441s Info: [ 13880,  17435) |****** 
441s Info: [ 17435,  20990) |************* 
441s Info: [ 20990,  24545) |********************* 
441s Info: [ 24545,  28100) |************************************************** 
441s Info: [ 28100,  31655) | 
441s Info: [ 31655,  35210) | 
441s Info: [ 35210,  38765) | 
441s Info: [ 38765,  42320) | 
441s Info: [ 42320,  45875) | 
441s Info: [ 45875,  49430) | 
441s Info: [ 49430,  52985) | 
441s Info: [ 52985,  56540) | 
441s Info: [ 56540,  60095) | 
441s Info: [ 60095,  63650) | 
441s Info: [ 63650,  67205) | 
441s Info: [ 67205,  70760) | 
441s Info: [ 70760,  74315) | 
441s Info: [ 74315,  77870) |*** 
441s Info: Checksum: 0x5165c354
441s 
441s Info: Routing..
441s Info: Setting up routing queue.
441s Info: Routing 642 arcs.
441s Info:            |   (re-)routed arcs  |   delta    | remaining|       time spent     |
441s Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|
441s Info:        772 |      109        580 |  109   580 |         0|       0.07       0.07|
441s Info: Routing complete.
441s Info: Router1 time 0.07s
441s Info: Checksum: 0x5f7d9565
441s 
441s Info: Critical path report for clock 'clk' (posedge -> posedge):
441s Info: curr total
441s Info:  1.4  1.4  Source ctr_SB_DFF_Q_D_SB_LUT4_O_18_LC.O
441s Info:  2.4  3.8    Net ctr[21] budget 0.000000 ns (2,16) -> (3,18)
441s Info:                Sink r_val_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_8_LC.I1
441s Info:                Defined in:
441s Info:                  /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
441s Info:  0.7  4.5  Source r_val_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_8_LC.COUT
441s Info:  0.7  5.1    Net r_val_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I3[2] budget 0.660000 ns (3,18) -> (3,18)
441s Info:                Sink r_val_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_7_LC.I3
441s Info:                Defined in:
441s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
441s Info:  0.9  6.0  Source r_val_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_7_LC.O
441s Info:  1.8  7.8    Net r_val_SB_LUT4_O_I0_SB_LUT4_O_I2[2] budget 2.195000 ns (3,18) -> (4,18)
441s Info:                Sink r_val_SB_LUT4_O_I0_SB_LUT4_O_7_LC.I2
441s Info:                Defined in:
441s Info:                  rgb.v:35.31-35.61
441s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:31.22-31.23
441s Info:  0.6  8.4  Source r_val_SB_LUT4_O_I0_SB_LUT4_O_7_LC.COUT
441s Info:  0.0  8.4    Net r_val_SB_LUT4_O_I0_SB_LUT4_O_I3[3] budget 0.000000 ns (4,18) -> (4,18)
441s Info:                Sink r_val_SB_LUT4_O_I0_SB_LUT4_O_6_LC.CIN
441s Info:                Defined in:
441s Info:                  rgb.v:35.31-35.61
441s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
441s Info:  0.3  8.7  Source r_val_SB_LUT4_O_I0_SB_LUT4_O_6_LC.COUT
441s Info:  0.0  8.7    Net r_val_SB_LUT4_O_I0_SB_LUT4_O_I3[4] budget 0.000000 ns (4,18) -> (4,18)
441s Info:                Sink r_val_SB_LUT4_O_I0_SB_LUT4_O_5_LC.CIN
441s Info:                Defined in:
441s Info:                  rgb.v:35.31-35.61
441s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
441s Info:  0.3  8.9  Source r_val_SB_LUT4_O_I0_SB_LUT4_O_5_LC.COUT
441s Info:  0.0  8.9    Net r_val_SB_LUT4_O_I0_SB_LUT4_O_I3[5] budget 0.000000 ns (4,18) -> (4,18)
441s Info:                Sink r_val_SB_LUT4_O_I0_SB_LUT4_O_4_LC.CIN
441s Info:                Defined in:
441s Info:                  rgb.v:35.31-35.61
441s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
441s Info:  0.3  9.2  Source r_val_SB_LUT4_O_I0_SB_LUT4_O_4_LC.COUT
441s Info:  0.0  9.2    Net r_val_SB_LUT4_O_I0_SB_LUT4_O_I3[6] budget 0.000000 ns (4,18) -> (4,18)
441s Info:                Sink r_val_SB_LUT4_O_I0_SB_LUT4_O_3_LC.CIN
441s Info:                Defined in:
441s Info:                  rgb.v:35.31-35.61
441s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
441s Info:  0.3  9.5  Source r_val_SB_LUT4_O_I0_SB_LUT4_O_3_LC.COUT
441s Info:  0.0  9.5    Net r_val_SB_LUT4_O_I0_SB_LUT4_O_I3[7] budget 0.000000 ns (4,18) -> (4,18)
441s Info:                Sink r_val_SB_LUT4_O_I0_SB_LUT4_O_2_LC.CIN
441s Info:                Defined in:
441s Info:                  rgb.v:35.31-35.61
441s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
441s Info:  0.3  9.8  Source r_val_SB_LUT4_O_I0_SB_LUT4_O_2_LC.COUT
441s Info:  0.6 10.3    Net r_val_SB_LUT4_O_I0_SB_LUT4_O_I3[8] budget 0.560000 ns (4,18) -> (4,19)
441s Info:                Sink r_val_SB_LUT4_O_I0_SB_LUT4_O_1_LC.CIN
441s Info:                Defined in:
441s Info:                  rgb.v:35.31-35.61
441s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
441s Info:  0.3 10.6  Source r_val_SB_LUT4_O_I0_SB_LUT4_O_1_LC.COUT
441s Info:  0.0 10.6    Net r_val_SB_LUT4_O_I0_SB_LUT4_O_I3[9] budget 0.000000 ns (4,19) -> (4,19)
441s Info:                Sink r_val_SB_LUT4_O_I0_SB_LUT4_O_LC.CIN
441s Info:                Defined in:
441s Info:                  rgb.v:35.31-35.61
441s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
441s Info:  0.3 10.9  Source r_val_SB_LUT4_O_I0_SB_LUT4_O_LC.COUT
441s Info:  0.0 10.9    Net r_val_SB_LUT4_O_I0_SB_LUT4_O_I3[10] budget 0.000000 ns (4,19) -> (4,19)
441s Info:                Sink r_val_SB_LUT4_O_I0_SB_LUT4_O_10_LC.CIN
441s Info:                Defined in:
441s Info:                  rgb.v:35.31-35.61
441s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
441s Info:  0.3 11.2  Source r_val_SB_LUT4_O_I0_SB_LUT4_O_10_LC.COUT
441s Info:  0.7 11.8    Net r_val_SB_LUT4_O_I0_SB_LUT4_O_I3[11] budget 0.660000 ns (4,19) -> (4,19)
441s Info:                Sink r_val_SB_LUT4_O_I0_SB_LUT4_O_9_LC.I3
441s Info:                Defined in:
441s Info:                  rgb.v:35.31-35.61
441s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22
441s Info:  0.9 12.7  Source r_val_SB_LUT4_O_I0_SB_LUT4_O_9_LC.O
441s Info:  1.8 14.5    Net r_val_SB_LUT4_O_I0[11] budget 4.390000 ns (4,19) -> (4,20)
441s Info:                Sink r_val_SB_LUT4_O_LC.I0
441s Info:                Defined in:
441s Info:                  rgb.v:35.31-35.61
441s Info:                  /usr/bin/../share/yosys/ice40/arith_map.v:33.26-33.27
441s Info:  1.3 15.7  Source r_val_SB_LUT4_O_LC.O
441s Info:  1.8 17.5    Net r_val[11] budget 4.390000 ns (4,20) -> (3,19)
441s Info:                Sink r_val_SB_LUT4_O_3_I3_SB_LUT4_I2_O_SB_LUT4_O_LC.I2
441s Info:                Defined in:
441s Info:                  rgb.v:32.22-32.27
441s Info:  1.2 18.7  Source r_val_SB_LUT4_O_3_I3_SB_LUT4_I2_O_SB_LUT4_O_LC.O
441s Info:  1.8 20.5    Net r_val_SB_LUT4_O_3_I3_SB_LUT4_I2_O[2] budget 3.292000 ns (3,19) -> (3,19)
441s Info:                Sink r_val_SB_LUT4_O_3_I3_SB_LUT4_I2_O_SB_LUT4_I2_LC.I2
441s Info:                Defined in:
441s Info:                  /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
441s Info:  1.2 21.7  Source r_val_SB_LUT4_O_3_I3_SB_LUT4_I2_O_SB_LUT4_I2_LC.O
441s Info:  3.1 24.7    Net pwm_r_SB_DFF_Q_D_SB_LUT4_O_I0[2] budget 3.292000 ns (3,19) -> (3,15)
441s Info:                Sink pwm_r_SB_DFF_Q_D_SB_LUT4_O_LC.I2
441s Info:                Defined in:
441s Info:                  /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
441s Info:  1.2 25.9  Setup pwm_r_SB_DFF_Q_D_SB_LUT4_O_LC.I2
441s Info: 11.5 ns logic, 14.4 ns routing
441s 
441s Info: Critical path report for cross-domain path 'posedge clk' -> '<async>':
441s Info: curr total
441s Info:  1.4  1.4  Source pwm_r_SB_DFF_Q_D_SB_LUT4_O_LC.O
441s Info:  4.9  6.3    Net pwm_r budget 81.943001 ns (3,15) -> (0,30)
441s Info:                Sink RGBA_DRIVER.RGB2PWM
441s Info:                Defined in:
441s Info:                  rgb.v:53.5-53.10
441s Info: 1.4 ns logic, 4.9 ns routing
441s 
441s Info: Max frequency for clock 'clk': 38.63 MHz (PASS at 32.00 MHz)
441s 
441s Info: Max delay posedge clk -> <async>: 6.29 ns
441s 
441s Info: Slack histogram:
441s Info:  legend: * represents 1 endpoint(s)
441s Info:          + represents [1,1) endpoint(s)
441s Info: [  5365,   8982) |**** 
441s Info: [  8982,  12599) |* 
441s Info: [ 12599,  16216) |*** 
441s Info: [ 16216,  19833) |************** 
441s Info: [ 19833,  23450) |****************** 
441s Info: [ 23450,  27067) |***************************************************** 
441s Info: [ 27067,  30684) |** 
441s Info: [ 30684,  34301) | 
441s Info: [ 34301,  37918) | 
441s Info: [ 37918,  41535) | 
441s Info: [ 41535,  45152) | 
441s Info: [ 45152,  48769) | 
441s Info: [ 48769,  52386) | 
441s Info: [ 52386,  56003) | 
441s Info: [ 56003,  59620) | 
441s Info: [ 59620,  63237) | 
441s Info: [ 63237,  66854) | 
441s Info: [ 66854,  70471) | 
441s Info: [ 70471,  74088) | 
441s Info: [ 74088,  77705) |*** 
442s 1 warning, 0 errors
442s 
442s Info: Program finished normally.
442s icepack rgb.asc rgb.bin
442s make: Leaving directory '/tmp/autopkgtest.eGJMaA/build.OQp/src/examples/up5k_rgb'
442s autopkgtest [08:09:58]: test examples-compile: -----------------------]
443s autopkgtest [08:09:59]: test examples-compile:  - - - - - - - - - - results - - - - - - - - - -
443s examples-compile     PASS
443s autopkgtest [08:09:59]: @@@@@@@@@@@@@@@@@@@@ summary
443s can-show-help        PASS (superficial)
443s examples-compile     PASS
455s Creating nova instance adt-noble-ppc64el-fpga-icestorm-20240327-080236-juju-7f2275-prod-proposed-migration-environment-3-77f572f6-6365-49d3-aa4f-a43bea3f2994 from image adt/ubuntu-noble-ppc64el-server-20240326.img (UUID a856d654-cf86-4db9-9789-e03c818e8ed3)...