0s autopkgtest [00:09:36]: starting date and time: 2024-03-16 00:09:36+0000 0s autopkgtest [00:09:36]: git checkout: b506e79c ssh-setup/nova: fix ARCH having two lines of data 0s autopkgtest [00:09:36]: host juju-7f2275-prod-proposed-migration-environment-2; command line: /home/ubuntu/autopkgtest/runner/autopkgtest --output-dir /tmp/autopkgtest-work.zo3y9skn/out --timeout-copy=6000 --setup-commands /home/ubuntu/autopkgtest-cloud/worker-config-production/setup-canonical.sh --apt-pocket=proposed=src:nextpnr,src:db5.3,src:glib2.0,src:libpng1.6,src:mtdev,src:openssl,src:python3.12,src:qtbase-opensource-src,src:readline,src:wp2latex --apt-upgrade fpga-icestorm --timeout-short=300 --timeout-copy=20000 --timeout-build=20000 '--env=ADT_TEST_TRIGGERS=nextpnr/0.6-3build4 db5.3/5.3.28+dfsg2-5build1 glib2.0/2.79.3-3ubuntu5 libpng1.6/1.6.43-3 mtdev/1.1.6-1.1 openssl/3.0.13-0ubuntu1 python3.12/3.12.2-4build2 qtbase-opensource-src/5.15.12+dfsg-3ubuntu5 readline/8.2-3.1 wp2latex/4.4~ds-1build1' -- ssh -s /home/ubuntu/autopkgtest/ssh-setup/nova -- --flavor autopkgtest --security-groups autopkgtest-juju-7f2275-prod-proposed-migration-environment-2@bos02-ppc64el-3.secgroup --name adt-noble-ppc64el-fpga-icestorm-20240316-000936-juju-7f2275-prod-proposed-migration-environment-2 --image adt/ubuntu-noble-ppc64el-server --keyname testbed-juju-7f2275-prod-proposed-migration-environment-2 --net-id=net_prod-proposed-migration -e TERM=linux -e ''"'"'http_proxy=http://squid.internal:3128'"'"'' -e ''"'"'https_proxy=http://squid.internal:3128'"'"'' -e ''"'"'no_proxy=127.0.0.1,127.0.1.1,login.ubuntu.com,localhost,localdomain,novalocal,internal,archive.ubuntu.com,ports.ubuntu.com,security.ubuntu.com,ddebs.ubuntu.com,changelogs.ubuntu.com,launchpadlibrarian.net,launchpadcontent.net,launchpad.net,10.24.0.0/24,keystone.ps5.canonical.com,objectstorage.prodstack5.canonical.com'"'"'' --mirror=http://ftpmaster.internal/ubuntu/ 107s autopkgtest [00:11:23]: testbed dpkg architecture: ppc64el 107s autopkgtest [00:11:23]: testbed apt version: 2.7.12 107s autopkgtest [00:11:23]: @@@@@@@@@@@@@@@@@@@@ test bed setup 108s Get:1 http://ftpmaster.internal/ubuntu noble-proposed InRelease [117 kB] 109s Get:2 http://ftpmaster.internal/ubuntu noble-proposed/main Sources [469 kB] 109s Get:3 http://ftpmaster.internal/ubuntu noble-proposed/multiverse Sources [49.6 kB] 109s Get:4 http://ftpmaster.internal/ubuntu noble-proposed/universe Sources [3633 kB] 110s Get:5 http://ftpmaster.internal/ubuntu noble-proposed/restricted Sources [6540 B] 110s Get:6 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el Packages [628 kB] 110s Get:7 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el c-n-f Metadata [3116 B] 110s Get:8 http://ftpmaster.internal/ubuntu noble-proposed/restricted ppc64el Packages [1372 B] 110s Get:9 http://ftpmaster.internal/ubuntu noble-proposed/restricted ppc64el c-n-f Metadata [116 B] 110s Get:10 http://ftpmaster.internal/ubuntu noble-proposed/universe ppc64el Packages [3743 kB] 110s Get:11 http://ftpmaster.internal/ubuntu noble-proposed/universe ppc64el c-n-f Metadata [8652 B] 110s Get:12 http://ftpmaster.internal/ubuntu noble-proposed/multiverse ppc64el Packages [46.2 kB] 110s Get:13 http://ftpmaster.internal/ubuntu noble-proposed/multiverse ppc64el c-n-f Metadata [116 B] 113s Fetched 8705 kB in 3s (3025 kB/s) 114s Reading package lists... 116s Reading package lists... 116s Building dependency tree... 116s Reading state information... 117s Calculating upgrade... 117s The following packages will be REMOVED: 117s libglib2.0-0 libreadline8 libssl3 117s The following NEW packages will be installed: 117s libglib2.0-0t64 libreadline8t64 libssl3t64 xdg-user-dirs 117s The following packages have been kept back: 117s libpython3.12-minimal libpython3.12-stdlib python3.12 python3.12-minimal 117s The following packages will be upgraded: 117s gir1.2-glib-2.0 libglib2.0-data openssl readline-common 117s 4 upgraded, 4 newly installed, 3 to remove and 4 not upgraded. 117s Need to get 5456 kB of archives. 117s After this operation, 212 kB of additional disk space will be used. 117s Get:1 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el gir1.2-glib-2.0 ppc64el 2.79.3-3ubuntu5 [182 kB] 117s Get:2 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libglib2.0-0t64 ppc64el 2.79.3-3ubuntu5 [1773 kB] 117s Get:3 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el readline-common all 8.2-3.1 [56.4 kB] 117s Get:4 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libreadline8t64 ppc64el 8.2-3.1 [182 kB] 117s Get:5 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el openssl ppc64el 3.0.13-0ubuntu1 [1028 kB] 117s Get:6 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libssl3t64 ppc64el 3.0.13-0ubuntu1 [2168 kB] 117s Get:7 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libglib2.0-data all 2.79.3-3ubuntu5 [46.6 kB] 117s Get:8 http://ftpmaster.internal/ubuntu noble/main ppc64el xdg-user-dirs ppc64el 0.18-1 [20.0 kB] 118s Fetched 5456 kB in 1s (6718 kB/s) 118s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 70095 files and directories currently installed.) 118s Preparing to unpack .../gir1.2-glib-2.0_2.79.3-3ubuntu5_ppc64el.deb ... 118s Unpacking gir1.2-glib-2.0:ppc64el (2.79.3-3ubuntu5) over (2.79.2-1~ubuntu1) ... 118s dpkg: libglib2.0-0:ppc64el: dependency problems, but removing anyway as you requested: 118s udisks2 depends on libglib2.0-0 (>= 2.77.0). 118s shared-mime-info depends on libglib2.0-0 (>= 2.75.3). 118s python3-gi depends on libglib2.0-0 (>= 2.77.0). 118s python3-dbus depends on libglib2.0-0 (>= 2.16.0). 118s netplan.io depends on libglib2.0-0 (>= 2.70.0). 118s netplan-generator depends on libglib2.0-0 (>= 2.70.0). 118s libxmlb2:ppc64el depends on libglib2.0-0 (>= 2.54.0). 118s libvolume-key1:ppc64el depends on libglib2.0-0 (>= 2.18.0). 118s libudisks2-0:ppc64el depends on libglib2.0-0 (>= 2.75.3). 118s libqrtr-glib0:ppc64el depends on libglib2.0-0 (>= 2.56). 118s libqmi-proxy depends on libglib2.0-0 (>= 2.30.0). 118s libqmi-glib5:ppc64el depends on libglib2.0-0 (>= 2.54.0). 118s libpolkit-gobject-1-0:ppc64el depends on libglib2.0-0 (>= 2.38.0). 118s libpolkit-agent-1-0:ppc64el depends on libglib2.0-0 (>= 2.38.0). 118s libnetplan0:ppc64el depends on libglib2.0-0 (>= 2.75.3). 118s libmm-glib0:ppc64el depends on libglib2.0-0 (>= 2.62.0). 118s libmbim-proxy depends on libglib2.0-0 (>= 2.56). 118s libmbim-glib4:ppc64el depends on libglib2.0-0 (>= 2.56). 118s libjson-glib-1.0-0:ppc64el depends on libglib2.0-0 (>= 2.75.3). 118s libjcat1:ppc64el depends on libglib2.0-0 (>= 2.75.3). 118s libgusb2:ppc64el depends on libglib2.0-0 (>= 2.75.3). 118s libgudev-1.0-0:ppc64el depends on libglib2.0-0 (>= 2.38.0). 118s libgirepository-1.0-1:ppc64el depends on libglib2.0-0 (>= 2.79.0). 118s libfwupd2:ppc64el depends on libglib2.0-0 (>= 2.79.0). 118s libblockdev3:ppc64el depends on libglib2.0-0 (>= 2.42.2). 118s libblockdev-utils3:ppc64el depends on libglib2.0-0 (>= 2.75.3). 118s libblockdev-swap3:ppc64el depends on libglib2.0-0 (>= 2.42.2). 118s libblockdev-part3:ppc64el depends on libglib2.0-0 (>= 2.42.2). 118s libblockdev-nvme3:ppc64el depends on libglib2.0-0 (>= 2.42.2). 118s libblockdev-mdraid3:ppc64el depends on libglib2.0-0 (>= 2.42.2). 118s libblockdev-loop3:ppc64el depends on libglib2.0-0 (>= 2.42.2). 118s libblockdev-fs3:ppc64el depends on libglib2.0-0 (>= 2.42.2). 118s libblockdev-crypto3:ppc64el depends on libglib2.0-0 (>= 2.42.2). 118s fwupd depends on libglib2.0-0 (>= 2.79.0). 118s bolt depends on libglib2.0-0 (>= 2.56.0). 118s 118s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 70095 files and directories currently installed.) 118s Removing libglib2.0-0:ppc64el (2.79.2-1~ubuntu1) ... 118s Selecting previously unselected package libglib2.0-0t64:ppc64el. 118s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 70070 files and directories currently installed.) 118s Preparing to unpack .../libglib2.0-0t64_2.79.3-3ubuntu5_ppc64el.deb ... 118s libglib2.0-0t64.preinst: Removing /var/lib/dpkg/info/libglib2.0-0:ppc64el.postrm to avoid loss of /usr/share/glib-2.0/schemas/gschemas.compiled... 118s removed '/var/lib/dpkg/info/libglib2.0-0:ppc64el.postrm' 118s Unpacking libglib2.0-0t64:ppc64el (2.79.3-3ubuntu5) ... 118s Preparing to unpack .../readline-common_8.2-3.1_all.deb ... 118s Unpacking readline-common (8.2-3.1) over (8.2-3) ... 118s dpkg: libreadline8:ppc64el: dependency problems, but removing anyway as you requested: 118s parted depends on libreadline8 (>= 6.0). 118s libpython3.12-stdlib:ppc64el depends on libreadline8 (>= 7.0~beta). 118s libpython3.11-stdlib:ppc64el depends on libreadline8 (>= 7.0~beta). 118s gpgsm depends on libreadline8 (>= 6.0). 118s gpgconf depends on libreadline8 (>= 6.0). 118s gpg depends on libreadline8 (>= 6.0). 118s gawk depends on libreadline8 (>= 6.0). 118s fdisk depends on libreadline8 (>= 6.0). 118s bc depends on libreadline8 (>= 6.0). 118s 118s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 70095 files and directories currently installed.) 118s Removing libreadline8:ppc64el (8.2-3) ... 118s Selecting previously unselected package libreadline8t64:ppc64el. 118s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 70083 files and directories currently installed.) 118s Preparing to unpack .../libreadline8t64_8.2-3.1_ppc64el.deb ... 118s Adding 'diversion of /lib/powerpc64le-linux-gnu/libhistory.so.8 to /lib/powerpc64le-linux-gnu/libhistory.so.8.usr-is-merged by libreadline8t64' 118s Adding 'diversion of /lib/powerpc64le-linux-gnu/libhistory.so.8.2 to /lib/powerpc64le-linux-gnu/libhistory.so.8.2.usr-is-merged by libreadline8t64' 118s Adding 'diversion of /lib/powerpc64le-linux-gnu/libreadline.so.8 to /lib/powerpc64le-linux-gnu/libreadline.so.8.usr-is-merged by libreadline8t64' 118s Adding 'diversion of /lib/powerpc64le-linux-gnu/libreadline.so.8.2 to /lib/powerpc64le-linux-gnu/libreadline.so.8.2.usr-is-merged by libreadline8t64' 118s Unpacking libreadline8t64:ppc64el (8.2-3.1) ... 118s Preparing to unpack .../openssl_3.0.13-0ubuntu1_ppc64el.deb ... 118s Unpacking openssl (3.0.13-0ubuntu1) over (3.0.10-1ubuntu4) ... 118s dpkg: libssl3:ppc64el: dependency problems, but removing anyway as you requested: 118s wget depends on libssl3 (>= 3.0.0). 118s tnftp depends on libssl3 (>= 3.0.0). 118s tcpdump depends on libssl3 (>= 3.0.0). 118s systemd-resolved depends on libssl3 (>= 3.0.0). 118s systemd depends on libssl3 (>= 3.0.0). 118s sudo depends on libssl3 (>= 3.0.0). 118s rsync depends on libssl3 (>= 3.0.0). 118s python3-cryptography depends on libssl3 (>= 3.0.0). 118s openssh-server depends on libssl3 (>= 3.0.10). 118s openssh-client depends on libssl3 (>= 3.0.10). 118s linux-headers-6.8.0-11-generic depends on libssl3 (>= 3.0.0). 118s libsystemd-shared:ppc64el depends on libssl3 (>= 3.0.0). 118s libssh-4:ppc64el depends on libssl3 (>= 3.0.0). 118s libsasl2-modules:ppc64el depends on libssl3 (>= 3.0.0). 118s libsasl2-2:ppc64el depends on libssl3 (>= 3.0.0). 118s libpython3.12-minimal:ppc64el depends on libssl3 (>= 3.0.0). 118s libpython3.11-minimal:ppc64el depends on libssl3 (>= 3.0.0). 118s libnvme1 depends on libssl3 (>= 3.0.0). 118s libkrb5-3:ppc64el depends on libssl3 (>= 3.0.0). 118s libkmod2:ppc64el depends on libssl3 (>= 3.0.0). 118s libfido2-1:ppc64el depends on libssl3 (>= 3.0.0). 118s libcurl4:ppc64el depends on libssl3 (>= 3.0.0). 118s libcryptsetup12:ppc64el depends on libssl3 (>= 3.0.0). 118s kmod depends on libssl3 (>= 3.0.0). 118s dhcpcd-base depends on libssl3 (>= 3.0.0). 118s bind9-libs:ppc64el depends on libssl3 (>= 3.0.0). 118s 119s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 70103 files and directories currently installed.) 119s Removing libssl3:ppc64el (3.0.10-1ubuntu4) ... 119s Selecting previously unselected package libssl3t64:ppc64el. 119s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 70092 files and directories currently installed.) 119s Preparing to unpack .../libssl3t64_3.0.13-0ubuntu1_ppc64el.deb ... 119s Unpacking libssl3t64:ppc64el (3.0.13-0ubuntu1) ... 119s Preparing to unpack .../libglib2.0-data_2.79.3-3ubuntu5_all.deb ... 119s Unpacking libglib2.0-data (2.79.3-3ubuntu5) over (2.79.2-1~ubuntu1) ... 119s Selecting previously unselected package xdg-user-dirs. 119s Preparing to unpack .../xdg-user-dirs_0.18-1_ppc64el.deb ... 119s Unpacking xdg-user-dirs (0.18-1) ... 119s Setting up xdg-user-dirs (0.18-1) ... 119s Setting up libssl3t64:ppc64el (3.0.13-0ubuntu1) ... 119s Setting up libglib2.0-0t64:ppc64el (2.79.3-3ubuntu5) ... 119s No schema files found: doing nothing. 119s Setting up libglib2.0-data (2.79.3-3ubuntu5) ... 119s Setting up gir1.2-glib-2.0:ppc64el (2.79.3-3ubuntu5) ... 119s Setting up openssl (3.0.13-0ubuntu1) ... 119s Setting up readline-common (8.2-3.1) ... 119s Setting up libreadline8t64:ppc64el (8.2-3.1) ... 119s Processing triggers for libc-bin (2.39-0ubuntu2) ... 119s Processing triggers for man-db (2.12.0-3) ... 119s Processing triggers for install-info (7.1-3) ... 120s Reading package lists... 120s Building dependency tree... 120s Reading state information... 120s 0 upgraded, 0 newly installed, 0 to remove and 4 not upgraded. 120s Hit:1 http://ftpmaster.internal/ubuntu noble-proposed InRelease 120s Hit:2 http://ftpmaster.internal/ubuntu noble InRelease 121s Hit:3 http://ftpmaster.internal/ubuntu noble-updates InRelease 121s Hit:4 http://ftpmaster.internal/ubuntu noble-security InRelease 122s Reading package lists... 122s Reading package lists... 122s Building dependency tree... 122s Reading state information... 122s Calculating upgrade... 122s The following packages have been kept back: 122s libpython3.12-minimal libpython3.12-stdlib python3.12 python3.12-minimal 122s 0 upgraded, 0 newly installed, 0 to remove and 4 not upgraded. 123s Reading package lists... 123s Building dependency tree... 123s Reading state information... 123s 0 upgraded, 0 newly installed, 0 to remove and 4 not upgraded. 125s autopkgtest [00:11:41]: testbed running kernel: Linux 6.8.0-11-generic #11-Ubuntu SMP Wed Feb 14 00:33:03 UTC 2024 126s autopkgtest [00:11:42]: @@@@@@@@@@@@@@@@@@@@ apt-source fpga-icestorm 128s Get:1 http://ftpmaster.internal/ubuntu noble/universe fpga-icestorm 0~20230218gitd20a5e9-1 (dsc) [2329 B] 128s Get:2 http://ftpmaster.internal/ubuntu noble/universe fpga-icestorm 0~20230218gitd20a5e9-1 (tar) [432 kB] 128s Get:3 http://ftpmaster.internal/ubuntu noble/universe fpga-icestorm 0~20230218gitd20a5e9-1 (diff) [10.3 kB] 128s gpgv: Signature made Wed Jun 14 23:39:20 2023 UTC 128s gpgv: using RSA key 57A1BF15B4F6F99B89EDB29FD39481AE1E79ACF7 128s gpgv: Can't check signature: No public key 128s dpkg-source: warning: cannot verify inline signature for ./fpga-icestorm_0~20230218gitd20a5e9-1.dsc: no acceptable signature found 128s autopkgtest [00:11:44]: testing package fpga-icestorm version 0~20230218gitd20a5e9-1 128s autopkgtest [00:11:44]: build not needed 129s autopkgtest [00:11:45]: test can-show-help: preparing testbed 130s Reading package lists... 131s Building dependency tree... 131s Reading state information... 131s Starting pkgProblemResolver with broken count: 0 131s Starting 2 pkgProblemResolver with broken count: 0 131s Done 131s The following additional packages will be installed: 131s fpga-icestorm fpga-icestorm-chipdb libftdi1 libusb-0.1-4 131s Suggested packages: 131s nextpnr-ice40 | nextpnr-ice40-qt 131s Recommended packages: 131s yosys 131s The following NEW packages will be installed: 131s autopkgtest-satdep fpga-icestorm fpga-icestorm-chipdb libftdi1 libusb-0.1-4 131s 0 upgraded, 5 newly installed, 0 to remove and 4 not upgraded. 131s Need to get 10.8 MB/10.8 MB of archives. 131s After this operation, 116 MB of additional disk space will be used. 131s Get:1 /tmp/autopkgtest.DyuG3m/1-autopkgtest-satdep.deb autopkgtest-satdep ppc64el 0 [720 B] 131s Get:2 http://ftpmaster.internal/ubuntu noble/main ppc64el libusb-0.1-4 ppc64el 2:0.1.12-35 [22.0 kB] 131s Get:3 http://ftpmaster.internal/ubuntu noble/universe ppc64el libftdi1 ppc64el 0.20-4ubuntu2 [18.8 kB] 131s Get:4 http://ftpmaster.internal/ubuntu noble/universe ppc64el fpga-icestorm ppc64el 0~20230218gitd20a5e9-1 [439 kB] 132s Get:5 http://ftpmaster.internal/ubuntu noble/universe ppc64el fpga-icestorm-chipdb all 0~20230218gitd20a5e9-1 [10.3 MB] 132s Fetched 10.8 MB in 1s (11.1 MB/s) 132s Selecting previously unselected package libusb-0.1-4:ppc64el. 132s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 70119 files and directories currently installed.) 132s Preparing to unpack .../libusb-0.1-4_2%3a0.1.12-35_ppc64el.deb ... 132s Unpacking libusb-0.1-4:ppc64el (2:0.1.12-35) ... 132s Selecting previously unselected package libftdi1:ppc64el. 132s Preparing to unpack .../libftdi1_0.20-4ubuntu2_ppc64el.deb ... 132s Unpacking libftdi1:ppc64el (0.20-4ubuntu2) ... 132s Selecting previously unselected package fpga-icestorm. 132s Preparing to unpack .../fpga-icestorm_0~20230218gitd20a5e9-1_ppc64el.deb ... 132s Unpacking fpga-icestorm (0~20230218gitd20a5e9-1) ... 133s Selecting previously unselected package fpga-icestorm-chipdb. 133s Preparing to unpack .../fpga-icestorm-chipdb_0~20230218gitd20a5e9-1_all.deb ... 133s Unpacking fpga-icestorm-chipdb (0~20230218gitd20a5e9-1) ... 133s Selecting previously unselected package autopkgtest-satdep. 133s Preparing to unpack .../1-autopkgtest-satdep.deb ... 133s Unpacking autopkgtest-satdep (0) ... 133s Setting up libusb-0.1-4:ppc64el (2:0.1.12-35) ... 133s Setting up fpga-icestorm-chipdb (0~20230218gitd20a5e9-1) ... 133s Setting up libftdi1:ppc64el (0.20-4ubuntu2) ... 133s Setting up fpga-icestorm (0~20230218gitd20a5e9-1) ... 133s Setting up autopkgtest-satdep (0) ... 133s Processing triggers for man-db (2.12.0-3) ... 134s Processing triggers for libc-bin (2.39-0ubuntu2) ... 136s (Reading database ... 70210 files and directories currently installed.) 136s Removing autopkgtest-satdep (0) ... 136s autopkgtest [00:11:52]: test can-show-help: [----------------------- 137s Simple programming tool for FTDI-based Lattice iCE programmers. 137s Usage: iceprog [-b|-n|-c] 137s iceprog -r|-R 137s iceprog -S 137s iceprog -t 137s 137s General options: 137s -d use the specified USB device [default: i:0x0403:0x6010 or i:0x0403:0x6014] 137s d: (e.g. d:002/005) 137s i:: (e.g. i:0x0403:0x6010) 137s i::: (e.g. i:0x0403:0x6010:0) 137s s::: 137s -I [ABCD] connect to the specified interface on the FTDI chip 137s [default: A] 137s -o start address for read/write [default: 0] 137s (append 'k' to the argument for size in kilobytes, 137s or 'M' for size in megabytes) 137s -s slow SPI (50 kHz instead of 6 MHz) 137s -k keep flash in powered up state (i.e. skip power down command) 137s -v verbose output 137s -i [4,32,64] select erase block size [default: 64k] 137s 137s Mode of operation: 137s [default] write file contents to flash, then verify 137s -X write file contents to flash only 137s -r read first 256 kB from flash and write to file 137s -R read the specified number of bytes from flash 137s (append 'k' to the argument for size in kilobytes, 137s or 'M' for size in megabytes) 137s -c do not write flash, only verify (`check') 137s -S perform SRAM programming 137s -t just read the flash ID sequence 137s -Q just set the flash QE=1 bit 137s 137s Erase mode (only meaningful in default mode): 137s [default] erase aligned chunks of 64kB in write mode 137s This means that some data after the written data (or 137s even before when -o is used) may be erased as well. 137s -b bulk erase entire flash before writing 137s -e erase flash as if we were writing that number of bytes 137s -n do not erase flash before writing 137s -p disable write protection before erasing or writing 137s This can be useful if flash memory appears to be 137s bricked and won't respond to erasing or programming. 137s 137s Miscellaneous options: 137s --help display this help and exit 137s -- treat all remaining arguments as filenames 137s 137s Exit status: 137s 0 on success, 137s 1 if a non-hardware error occurred (e.g., failure to read from or 137s write to a file, or invoked with invalid options), 137s 2 if communication with the hardware failed (e.g., cannot find the 137s iCE FTDI USB device), 137s 3 if verification of the data failed. 137s 137s Notes for iCEstick (iCE40HX-1k devel board): 137s An unmodified iCEstick can only be programmed via the serial flash. 137s Direct programming of the SRAM is not supported. For direct SRAM 137s programming the flash chip and one zero ohm resistor must be desoldered 137s and the FT2232H SI pin must be connected to the iCE SPI_SI pin, as shown 137s in this picture: 137s http://www.clifford.at/gallery/2014-elektronik/IMG_20141115_183838 137s 137s Notes for the iCE40-HX8K Breakout Board: 137s Make sure that the jumper settings on the board match the selected 137s mode (SRAM or FLASH). See the iCE40-HX8K user manual for details. 137s 137s If you have a bug report, please file an issue on github: 137s https://github.com/cliffordwolf/icestorm/issues 137s autopkgtest [00:11:53]: test can-show-help: -----------------------] 137s can-show-help PASS (superficial) 137s autopkgtest [00:11:53]: test can-show-help: - - - - - - - - - - results - - - - - - - - - - 138s autopkgtest [00:11:54]: test examples-compile: preparing testbed 139s Reading package lists... 139s Building dependency tree... 139s Reading state information... 139s Starting pkgProblemResolver with broken count: 0 139s Starting 2 pkgProblemResolver with broken count: 0 139s Done 140s The following additional packages will be installed: 140s adwaita-icon-theme at-spi2-common berkeley-abc dconf-gsettings-backend 140s dconf-service fontconfig fontconfig-config fonts-dejavu-core 140s fonts-dejavu-mono gir1.2-atk-1.0 gir1.2-freedesktop gir1.2-gdkpixbuf-2.0 140s gir1.2-gtk-3.0 gir1.2-harfbuzz-0.0 gir1.2-pango-1.0 graphviz 140s gtk-update-icon-cache hicolor-icon-theme humanity-icon-theme libann0 140s libatk-bridge2.0-0 libatk1.0-0 libatspi2.0-0 libavahi-client3 140s libavahi-common-data libavahi-common3 libblas3 libboost-filesystem1.83.0 140s libboost-iostreams1.83.0 libboost-program-options1.83.0 140s libboost-thread1.83.0 libcairo-gobject2 libcairo2 libcdt5 libcgraph6 140s libcolord2 libcups2 libdatrie1 libdb5.3t64 libdconf1 libdeflate0 libepoxy0 140s libfontconfig1 libgd3 libgdk-pixbuf-2.0-0 libgdk-pixbuf2.0-common 140s libgfortran5 libgraphite2-3 libgtk-3-0 libgtk-3-common libgts-0.7-5 libgvc6 140s libgvpr2 libharfbuzz-gobject0 libharfbuzz0b libice6 libjbig0 libjpeg-turbo8 140s libjpeg8 liblab-gamut1 liblapack3 liblcms2-2 liblerc4 libltdl7 140s libpango-1.0-0 libpangocairo-1.0-0 libpangoft2-1.0-0 libpangoxft-1.0-0 140s libpathplan4 libpixman-1-0 libpython3.12-minimal libpython3.12-stdlib 140s libpython3.12t64 libsharpyuv0 libsm6 libtcl8.6 libthai-data libthai0 140s libtiff6 libwayland-client0 libwayland-cursor0 libwayland-egl1 libwebp7 140s libxaw7 libxcb-render0 libxcb-shm0 libxcomposite1 libxcursor1 libxdamage1 140s libxfixes3 libxft2 libxi6 libxinerama1 libxmu6 libxpm4 libxrandr2 140s libxrender1 libxt6 nextpnr-ice40 nextpnr-ice40-chipdb python3-cairo 140s python3-click python3-colorama python3-gi-cairo python3-numpy python3.12 140s python3.12-minimal ubuntu-mono x11-common xdot yosys 140s Suggested packages: 140s gsfonts graphviz-doc colord cups-common libgd-tools gvfs liblcms2-utils 140s tcl8.6 gcc gfortran python3-dev python3-pytest python3.12-venv 140s python3.12-doc binfmt-support 140s Recommended packages: 140s librsvg2-common fonts-liberation2 at-spi2-core libgdk-pixbuf2.0-bin 140s libgtk-3-bin libgts-bin 140s The following packages will be REMOVED: 140s libdb5.3 140s The following NEW packages will be installed: 140s adwaita-icon-theme at-spi2-common autopkgtest-satdep berkeley-abc 140s dconf-gsettings-backend dconf-service fontconfig fontconfig-config 140s fonts-dejavu-core fonts-dejavu-mono gir1.2-atk-1.0 gir1.2-freedesktop 140s gir1.2-gdkpixbuf-2.0 gir1.2-gtk-3.0 gir1.2-harfbuzz-0.0 gir1.2-pango-1.0 140s graphviz gtk-update-icon-cache hicolor-icon-theme humanity-icon-theme 140s libann0 libatk-bridge2.0-0 libatk1.0-0 libatspi2.0-0 libavahi-client3 140s libavahi-common-data libavahi-common3 libblas3 libboost-filesystem1.83.0 140s libboost-iostreams1.83.0 libboost-program-options1.83.0 140s libboost-thread1.83.0 libcairo-gobject2 libcairo2 libcdt5 libcgraph6 140s libcolord2 libcups2 libdatrie1 libdb5.3t64 libdconf1 libdeflate0 libepoxy0 140s libfontconfig1 libgd3 libgdk-pixbuf-2.0-0 libgdk-pixbuf2.0-common 140s libgfortran5 libgraphite2-3 libgtk-3-0 libgtk-3-common libgts-0.7-5 libgvc6 140s libgvpr2 libharfbuzz-gobject0 libharfbuzz0b libice6 libjbig0 libjpeg-turbo8 140s libjpeg8 liblab-gamut1 liblapack3 liblcms2-2 liblerc4 libltdl7 140s libpango-1.0-0 libpangocairo-1.0-0 libpangoft2-1.0-0 libpangoxft-1.0-0 140s libpathplan4 libpixman-1-0 libpython3.12t64 libsharpyuv0 libsm6 libtcl8.6 140s libthai-data libthai0 libtiff6 libwayland-client0 libwayland-cursor0 140s libwayland-egl1 libwebp7 libxaw7 libxcb-render0 libxcb-shm0 libxcomposite1 140s libxcursor1 libxdamage1 libxfixes3 libxft2 libxi6 libxinerama1 libxmu6 140s libxpm4 libxrandr2 libxrender1 libxt6 nextpnr-ice40 nextpnr-ice40-chipdb 140s python3-cairo python3-click python3-colorama python3-gi-cairo python3-numpy 140s ubuntu-mono x11-common xdot yosys 140s The following packages will be upgraded: 140s libpython3.12-minimal libpython3.12-stdlib python3.12 python3.12-minimal 140s 4 upgraded, 108 newly installed, 1 to remove and 0 not upgraded. 140s Need to get 98.7 MB/98.7 MB of archives. 140s After this operation, 437 MB of additional disk space will be used. 140s Get:1 /tmp/autopkgtest.DyuG3m/2-autopkgtest-satdep.deb autopkgtest-satdep ppc64el 0 [736 B] 140s Get:2 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el python3.12 ppc64el 3.12.2-4build2 [645 kB] 140s Get:3 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el python3.12-minimal ppc64el 3.12.2-4build2 [2447 kB] 140s Get:4 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libpython3.12-minimal ppc64el 3.12.2-4build2 [836 kB] 140s Get:5 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libpython3.12-stdlib ppc64el 3.12.2-4build2 [2082 kB] 141s Get:6 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libdb5.3t64 ppc64el 5.3.28+dfsg2-5build1 [868 kB] 141s Get:7 http://ftpmaster.internal/ubuntu noble/main ppc64el libgdk-pixbuf2.0-common all 2.42.10+dfsg-3 [7624 B] 141s Get:8 http://ftpmaster.internal/ubuntu noble/main ppc64el libjpeg-turbo8 ppc64el 2.1.5-2ubuntu1 [212 kB] 141s Get:9 http://ftpmaster.internal/ubuntu noble/main ppc64el libjpeg8 ppc64el 8c-2ubuntu11 [2148 B] 141s Get:10 http://ftpmaster.internal/ubuntu noble/main ppc64el libdeflate0 ppc64el 1.19-1 [61.9 kB] 141s Get:11 http://ftpmaster.internal/ubuntu noble/main ppc64el libjbig0 ppc64el 2.1-6.1ubuntu1 [34.7 kB] 141s Get:12 http://ftpmaster.internal/ubuntu noble/main ppc64el liblerc4 ppc64el 4.0.0+ds-4ubuntu1 [266 kB] 141s Get:13 http://ftpmaster.internal/ubuntu noble/main ppc64el libsharpyuv0 ppc64el 1.3.2-0.4 [28.7 kB] 141s Get:14 http://ftpmaster.internal/ubuntu noble/main ppc64el libwebp7 ppc64el 1.3.2-0.4 [312 kB] 141s Get:15 http://ftpmaster.internal/ubuntu noble/main ppc64el libtiff6 ppc64el 4.5.1+git230720-3ubuntu1 [323 kB] 141s Get:16 http://ftpmaster.internal/ubuntu noble/main ppc64el libgdk-pixbuf-2.0-0 ppc64el 2.42.10+dfsg-3 [186 kB] 141s Get:17 http://ftpmaster.internal/ubuntu noble/main ppc64el gtk-update-icon-cache ppc64el 3.24.40-2ubuntu1 [53.2 kB] 141s Get:18 http://ftpmaster.internal/ubuntu noble/main ppc64el hicolor-icon-theme all 0.17-2 [9976 B] 141s Get:19 http://ftpmaster.internal/ubuntu noble/main ppc64el humanity-icon-theme all 0.6.16 [1282 kB] 141s Get:20 http://ftpmaster.internal/ubuntu noble/main ppc64el ubuntu-mono all 24.04-0ubuntu1 [151 kB] 141s Get:21 http://ftpmaster.internal/ubuntu noble/main ppc64el adwaita-icon-theme all 46~rc-1 [723 kB] 141s Get:22 http://ftpmaster.internal/ubuntu noble/main ppc64el at-spi2-common all 2.50.0-1 [7864 B] 141s Get:23 http://ftpmaster.internal/ubuntu noble/universe ppc64el berkeley-abc ppc64el 1.01+20230625git01b1bd1+dfsg-3 [5606 kB] 141s Get:24 http://ftpmaster.internal/ubuntu noble/main ppc64el libdconf1 ppc64el 0.40.0-4 [43.0 kB] 141s Get:25 http://ftpmaster.internal/ubuntu noble/main ppc64el dconf-service ppc64el 0.40.0-4 [31.0 kB] 141s Get:26 http://ftpmaster.internal/ubuntu noble/main ppc64el dconf-gsettings-backend ppc64el 0.40.0-4 [25.3 kB] 141s Get:27 http://ftpmaster.internal/ubuntu noble/main ppc64el fonts-dejavu-mono all 2.37-8 [502 kB] 141s Get:28 http://ftpmaster.internal/ubuntu noble/main ppc64el fonts-dejavu-core all 2.37-8 [835 kB] 141s Get:29 http://ftpmaster.internal/ubuntu noble/main ppc64el fontconfig-config ppc64el 2.15.0-1ubuntu1 [37.0 kB] 141s Get:30 http://ftpmaster.internal/ubuntu noble/main ppc64el libfontconfig1 ppc64el 2.15.0-1ubuntu1 [190 kB] 141s Get:31 http://ftpmaster.internal/ubuntu noble/main ppc64el fontconfig ppc64el 2.15.0-1ubuntu1 [192 kB] 141s Get:32 http://ftpmaster.internal/ubuntu noble/main ppc64el libatk1.0-0 ppc64el 2.50.0-1 [57.8 kB] 141s Get:33 http://ftpmaster.internal/ubuntu noble/main ppc64el gir1.2-atk-1.0 ppc64el 2.50.0-1 [22.8 kB] 141s Get:34 http://ftpmaster.internal/ubuntu noble/main ppc64el libpixman-1-0 ppc64el 0.42.2-1 [300 kB] 141s Get:35 http://ftpmaster.internal/ubuntu noble/main ppc64el libxcb-render0 ppc64el 1.15-1 [17.2 kB] 141s Get:36 http://ftpmaster.internal/ubuntu noble/main ppc64el libxcb-shm0 ppc64el 1.15-1 [5896 B] 141s Get:37 http://ftpmaster.internal/ubuntu noble/main ppc64el libxrender1 ppc64el 1:0.9.10-1.1 [23.3 kB] 141s Get:38 http://ftpmaster.internal/ubuntu noble/main ppc64el libcairo2 ppc64el 1.18.0-1 [735 kB] 141s Get:39 http://ftpmaster.internal/ubuntu noble/main ppc64el libcairo-gobject2 ppc64el 1.18.0-1 [127 kB] 141s Get:40 http://ftpmaster.internal/ubuntu noble/main ppc64el gir1.2-freedesktop ppc64el 1.79.1-1 [48.5 kB] 141s Get:41 http://ftpmaster.internal/ubuntu noble/main ppc64el gir1.2-gdkpixbuf-2.0 ppc64el 2.42.10+dfsg-3 [9480 B] 141s Get:42 http://ftpmaster.internal/ubuntu noble/main ppc64el libgraphite2-3 ppc64el 1.3.14-2 [105 kB] 141s Get:43 http://ftpmaster.internal/ubuntu noble/main ppc64el libharfbuzz0b ppc64el 8.3.0-2 [576 kB] 141s Get:44 http://ftpmaster.internal/ubuntu noble/main ppc64el libharfbuzz-gobject0 ppc64el 8.3.0-2 [34.7 kB] 141s Get:45 http://ftpmaster.internal/ubuntu noble/main ppc64el gir1.2-harfbuzz-0.0 ppc64el 8.3.0-2 [44.5 kB] 141s Get:46 http://ftpmaster.internal/ubuntu noble/main ppc64el libthai-data all 0.1.29-2 [158 kB] 141s Get:47 http://ftpmaster.internal/ubuntu noble/main ppc64el libdatrie1 ppc64el 0.2.13-3 [25.1 kB] 141s Get:48 http://ftpmaster.internal/ubuntu noble/main ppc64el libthai0 ppc64el 0.1.29-2 [21.4 kB] 141s Get:49 http://ftpmaster.internal/ubuntu noble/main ppc64el libpango-1.0-0 ppc64el 1.51.0+ds-4 [266 kB] 141s Get:50 http://ftpmaster.internal/ubuntu noble/main ppc64el libpangoft2-1.0-0 ppc64el 1.51.0+ds-4 [49.5 kB] 141s Get:51 http://ftpmaster.internal/ubuntu noble/main ppc64el libpangocairo-1.0-0 ppc64el 1.51.0+ds-4 [31.2 kB] 141s Get:52 http://ftpmaster.internal/ubuntu noble/main ppc64el libxft2 ppc64el 2.3.6-1 [59.8 kB] 142s Get:53 http://ftpmaster.internal/ubuntu noble/main ppc64el libpangoxft-1.0-0 ppc64el 1.51.0+ds-4 [23.0 kB] 142s Get:54 http://ftpmaster.internal/ubuntu noble/main ppc64el gir1.2-pango-1.0 ppc64el 1.51.0+ds-4 [34.9 kB] 142s Get:55 http://ftpmaster.internal/ubuntu noble/main ppc64el libxi6 ppc64el 2:1.8.1-1 [37.9 kB] 142s Get:56 http://ftpmaster.internal/ubuntu noble/main ppc64el libatspi2.0-0 ppc64el 2.50.0-1 [93.5 kB] 142s Get:57 http://ftpmaster.internal/ubuntu noble/main ppc64el libatk-bridge2.0-0 ppc64el 2.50.0-1 [75.5 kB] 142s Get:58 http://ftpmaster.internal/ubuntu noble/main ppc64el liblcms2-2 ppc64el 2.14-2 [243 kB] 142s Get:59 http://ftpmaster.internal/ubuntu noble/main ppc64el libcolord2 ppc64el 1.4.7-1 [164 kB] 142s Get:60 http://ftpmaster.internal/ubuntu noble/main ppc64el libavahi-common-data ppc64el 0.8-13ubuntu2 [29.5 kB] 142s Get:61 http://ftpmaster.internal/ubuntu noble/main ppc64el libavahi-common3 ppc64el 0.8-13ubuntu2 [25.8 kB] 142s Get:62 http://ftpmaster.internal/ubuntu noble/main ppc64el libavahi-client3 ppc64el 0.8-13ubuntu2 [30.6 kB] 142s Get:63 http://ftpmaster.internal/ubuntu noble/main ppc64el libcups2 ppc64el 2.4.6-0ubuntu3 [344 kB] 142s Get:64 http://ftpmaster.internal/ubuntu noble/main ppc64el libepoxy0 ppc64el 1.5.10-1 [247 kB] 142s Get:65 http://ftpmaster.internal/ubuntu noble/main ppc64el libwayland-client0 ppc64el 1.22.0-2.1 [29.4 kB] 142s Get:66 http://ftpmaster.internal/ubuntu noble/main ppc64el libwayland-cursor0 ppc64el 1.22.0-2.1 [11.4 kB] 142s Get:67 http://ftpmaster.internal/ubuntu noble/main ppc64el libwayland-egl1 ppc64el 1.22.0-2.1 [5626 B] 142s Get:68 http://ftpmaster.internal/ubuntu noble/main ppc64el libxcomposite1 ppc64el 1:0.4.5-1build2 [7400 B] 142s Get:69 http://ftpmaster.internal/ubuntu noble/main ppc64el libxfixes3 ppc64el 1:6.0.0-2 [11.6 kB] 142s Get:70 http://ftpmaster.internal/ubuntu noble/main ppc64el libxcursor1 ppc64el 1:1.2.1-1 [26.9 kB] 142s Get:71 http://ftpmaster.internal/ubuntu noble/main ppc64el libxdamage1 ppc64el 1:1.1.6-1 [6320 B] 142s Get:72 http://ftpmaster.internal/ubuntu noble/main ppc64el libxinerama1 ppc64el 2:1.1.4-3 [7658 B] 142s Get:73 http://ftpmaster.internal/ubuntu noble/main ppc64el libxrandr2 ppc64el 2:1.5.2-2 [22.7 kB] 142s Get:74 http://ftpmaster.internal/ubuntu noble/main ppc64el libgtk-3-common all 3.24.40-2ubuntu1 [1200 kB] 142s Get:75 http://ftpmaster.internal/ubuntu noble/main ppc64el libgtk-3-0 ppc64el 3.24.40-2ubuntu1 [3344 kB] 142s Get:76 http://ftpmaster.internal/ubuntu noble/main ppc64el gir1.2-gtk-3.0 ppc64el 3.24.40-2ubuntu1 [245 kB] 142s Get:77 http://ftpmaster.internal/ubuntu noble/universe ppc64el libann0 ppc64el 1.1.2+doc-9 [30.0 kB] 142s Get:78 http://ftpmaster.internal/ubuntu noble/universe ppc64el libcdt5 ppc64el 2.42.2-8build1 [27.3 kB] 142s Get:79 http://ftpmaster.internal/ubuntu noble/universe ppc64el libcgraph6 ppc64el 2.42.2-8build1 [54.3 kB] 142s Get:80 http://ftpmaster.internal/ubuntu noble/main ppc64el libxpm4 ppc64el 1:3.5.17-1 [48.6 kB] 142s Get:81 http://ftpmaster.internal/ubuntu noble/main ppc64el libgd3 ppc64el 2.3.3-9ubuntu1 [155 kB] 142s Get:82 http://ftpmaster.internal/ubuntu noble/universe ppc64el libgts-0.7-5 ppc64el 0.7.6+darcs121130-5 [189 kB] 142s Get:83 http://ftpmaster.internal/ubuntu noble/main ppc64el libltdl7 ppc64el 2.4.7-7 [48.0 kB] 142s Get:84 http://ftpmaster.internal/ubuntu noble/universe ppc64el libpathplan4 ppc64el 2.42.2-8build1 [30.1 kB] 142s Get:85 http://ftpmaster.internal/ubuntu noble/universe ppc64el libgvc6 ppc64el 2.42.2-8build1 [919 kB] 142s Get:86 http://ftpmaster.internal/ubuntu noble/universe ppc64el libgvpr2 ppc64el 2.42.2-8build1 [210 kB] 142s Get:87 http://ftpmaster.internal/ubuntu noble/universe ppc64el liblab-gamut1 ppc64el 2.42.2-8build1 [1860 kB] 142s Get:88 http://ftpmaster.internal/ubuntu noble/main ppc64el x11-common all 1:7.7+23ubuntu2 [23.4 kB] 142s Get:89 http://ftpmaster.internal/ubuntu noble/main ppc64el libice6 ppc64el 2:1.0.10-1build2 [49.3 kB] 142s Get:90 http://ftpmaster.internal/ubuntu noble/main ppc64el libsm6 ppc64el 2:1.2.3-1build2 [18.5 kB] 142s Get:91 http://ftpmaster.internal/ubuntu noble/main ppc64el libxt6 ppc64el 1:1.2.1-1.1 [198 kB] 142s Get:92 http://ftpmaster.internal/ubuntu noble/main ppc64el libxmu6 ppc64el 2:1.1.3-3 [57.2 kB] 142s Get:93 http://ftpmaster.internal/ubuntu noble/main ppc64el libxaw7 ppc64el 2:1.0.14-1 [227 kB] 142s Get:94 http://ftpmaster.internal/ubuntu noble/universe ppc64el graphviz ppc64el 2.42.2-8build1 [822 kB] 142s Get:95 http://ftpmaster.internal/ubuntu noble/main ppc64el libblas3 ppc64el 3.12.0-3 [227 kB] 142s Get:96 http://ftpmaster.internal/ubuntu noble/main ppc64el libboost-filesystem1.83.0 ppc64el 1.83.0-2ubuntu1 [373 kB] 142s Get:97 http://ftpmaster.internal/ubuntu noble/main ppc64el libboost-iostreams1.83.0 ppc64el 1.83.0-2ubuntu1 [340 kB] 142s Get:98 http://ftpmaster.internal/ubuntu noble/main ppc64el libboost-program-options1.83.0 ppc64el 1.83.0-2ubuntu1 [421 kB] 142s Get:99 http://ftpmaster.internal/ubuntu noble/main ppc64el libboost-thread1.83.0 ppc64el 1.83.0-2ubuntu1 [363 kB] 142s Get:100 http://ftpmaster.internal/ubuntu noble/main ppc64el libgfortran5 ppc64el 14-20240303-1ubuntu1 [574 kB] 142s Get:101 http://ftpmaster.internal/ubuntu noble/main ppc64el liblapack3 ppc64el 3.12.0-3 [2804 kB] 143s Get:102 http://ftpmaster.internal/ubuntu noble-proposed/main ppc64el libpython3.12t64 ppc64el 3.12.2-4build2 [2558 kB] 143s Get:103 http://ftpmaster.internal/ubuntu noble/main ppc64el libtcl8.6 ppc64el 8.6.13+dfsg-2 [1179 kB] 144s Get:104 http://ftpmaster.internal/ubuntu noble-proposed/universe ppc64el nextpnr-ice40-chipdb ppc64el 0.6-3build4 [47.6 MB] 148s Get:105 http://ftpmaster.internal/ubuntu noble-proposed/universe ppc64el nextpnr-ice40 ppc64el 0.6-3build4 [891 kB] 148s Get:106 http://ftpmaster.internal/ubuntu noble/main ppc64el python3-cairo ppc64el 1.25.1-2 [162 kB] 148s Get:107 http://ftpmaster.internal/ubuntu noble/main ppc64el python3-colorama all 0.4.6-4 [32.1 kB] 148s Get:108 http://ftpmaster.internal/ubuntu noble/main ppc64el python3-click all 8.1.6-1 [79.0 kB] 148s Get:109 http://ftpmaster.internal/ubuntu noble/main ppc64el python3-gi-cairo ppc64el 3.47.0-3 [9904 B] 148s Get:110 http://ftpmaster.internal/ubuntu noble/main ppc64el python3-numpy ppc64el 1:1.24.2-2 [5581 kB] 149s Get:111 http://ftpmaster.internal/ubuntu noble/universe ppc64el xdot all 1.3-1 [30.3 kB] 149s Get:112 http://ftpmaster.internal/ubuntu noble/universe ppc64el yosys ppc64el 0.23-6 [3442 kB] 149s Fetched 98.7 MB in 9s (10.8 MB/s) 149s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 70210 files and directories currently installed.) 149s Preparing to unpack .../python3.12_3.12.2-4build2_ppc64el.deb ... 149s Unpacking python3.12 (3.12.2-4build2) over (3.12.2-1) ... 149s Preparing to unpack .../python3.12-minimal_3.12.2-4build2_ppc64el.deb ... 149s Unpacking python3.12-minimal (3.12.2-4build2) over (3.12.2-1) ... 149s Preparing to unpack .../libpython3.12-minimal_3.12.2-4build2_ppc64el.deb ... 149s Unpacking libpython3.12-minimal:ppc64el (3.12.2-4build2) over (3.12.2-1) ... 150s Preparing to unpack .../libpython3.12-stdlib_3.12.2-4build2_ppc64el.deb ... 150s Unpacking libpython3.12-stdlib:ppc64el (3.12.2-4build2) over (3.12.2-1) ... 150s dpkg: libdb5.3:ppc64el: dependency problems, but removing anyway as you requested: 150s libsasl2-modules-db:ppc64el depends on libdb5.3. 150s libpython3.11-stdlib:ppc64el depends on libdb5.3. 150s libperl5.38:ppc64el depends on libdb5.3. 150s libpam-modules:ppc64el depends on libdb5.3. 150s iproute2 depends on libdb5.3. 150s apt-utils depends on libdb5.3. 150s 150s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 70208 files and directories currently installed.) 150s Removing libdb5.3:ppc64el (5.3.28+dfsg2-4) ... 150s Selecting previously unselected package libdb5.3t64:ppc64el. 150s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 70202 files and directories currently installed.) 150s Preparing to unpack .../libdb5.3t64_5.3.28+dfsg2-5build1_ppc64el.deb ... 150s Unpacking libdb5.3t64:ppc64el (5.3.28+dfsg2-5build1) ... 150s Setting up libdb5.3t64:ppc64el (5.3.28+dfsg2-5build1) ... 150s Selecting previously unselected package libgdk-pixbuf2.0-common. 150s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 70208 files and directories currently installed.) 150s Preparing to unpack .../000-libgdk-pixbuf2.0-common_2.42.10+dfsg-3_all.deb ... 150s Unpacking libgdk-pixbuf2.0-common (2.42.10+dfsg-3) ... 150s Selecting previously unselected package libjpeg-turbo8:ppc64el. 150s Preparing to unpack .../001-libjpeg-turbo8_2.1.5-2ubuntu1_ppc64el.deb ... 150s Unpacking libjpeg-turbo8:ppc64el (2.1.5-2ubuntu1) ... 150s Selecting previously unselected package libjpeg8:ppc64el. 150s Preparing to unpack .../002-libjpeg8_8c-2ubuntu11_ppc64el.deb ... 150s Unpacking libjpeg8:ppc64el (8c-2ubuntu11) ... 150s Selecting previously unselected package libdeflate0:ppc64el. 150s Preparing to unpack .../003-libdeflate0_1.19-1_ppc64el.deb ... 150s Unpacking libdeflate0:ppc64el (1.19-1) ... 150s Selecting previously unselected package libjbig0:ppc64el. 150s Preparing to unpack .../004-libjbig0_2.1-6.1ubuntu1_ppc64el.deb ... 150s Unpacking libjbig0:ppc64el (2.1-6.1ubuntu1) ... 150s Selecting previously unselected package liblerc4:ppc64el. 150s Preparing to unpack .../005-liblerc4_4.0.0+ds-4ubuntu1_ppc64el.deb ... 150s Unpacking liblerc4:ppc64el (4.0.0+ds-4ubuntu1) ... 150s Selecting previously unselected package libsharpyuv0:ppc64el. 150s Preparing to unpack .../006-libsharpyuv0_1.3.2-0.4_ppc64el.deb ... 150s Unpacking libsharpyuv0:ppc64el (1.3.2-0.4) ... 150s Selecting previously unselected package libwebp7:ppc64el. 150s Preparing to unpack .../007-libwebp7_1.3.2-0.4_ppc64el.deb ... 150s Unpacking libwebp7:ppc64el (1.3.2-0.4) ... 150s Selecting previously unselected package libtiff6:ppc64el. 150s Preparing to unpack .../008-libtiff6_4.5.1+git230720-3ubuntu1_ppc64el.deb ... 150s Unpacking libtiff6:ppc64el (4.5.1+git230720-3ubuntu1) ... 150s Selecting previously unselected package libgdk-pixbuf-2.0-0:ppc64el. 150s Preparing to unpack .../009-libgdk-pixbuf-2.0-0_2.42.10+dfsg-3_ppc64el.deb ... 150s Unpacking libgdk-pixbuf-2.0-0:ppc64el (2.42.10+dfsg-3) ... 150s Selecting previously unselected package gtk-update-icon-cache. 150s Preparing to unpack .../010-gtk-update-icon-cache_3.24.40-2ubuntu1_ppc64el.deb ... 150s Unpacking gtk-update-icon-cache (3.24.40-2ubuntu1) ... 150s Selecting previously unselected package hicolor-icon-theme. 150s Preparing to unpack .../011-hicolor-icon-theme_0.17-2_all.deb ... 150s Unpacking hicolor-icon-theme (0.17-2) ... 150s Selecting previously unselected package humanity-icon-theme. 150s Preparing to unpack .../012-humanity-icon-theme_0.6.16_all.deb ... 150s Unpacking humanity-icon-theme (0.6.16) ... 151s Selecting previously unselected package ubuntu-mono. 151s Preparing to unpack .../013-ubuntu-mono_24.04-0ubuntu1_all.deb ... 151s Unpacking ubuntu-mono (24.04-0ubuntu1) ... 152s Selecting previously unselected package adwaita-icon-theme. 152s Preparing to unpack .../014-adwaita-icon-theme_46~rc-1_all.deb ... 152s Unpacking adwaita-icon-theme (46~rc-1) ... 152s Selecting previously unselected package at-spi2-common. 152s Preparing to unpack .../015-at-spi2-common_2.50.0-1_all.deb ... 152s Unpacking at-spi2-common (2.50.0-1) ... 152s Selecting previously unselected package berkeley-abc. 152s Preparing to unpack .../016-berkeley-abc_1.01+20230625git01b1bd1+dfsg-3_ppc64el.deb ... 152s Unpacking berkeley-abc (1.01+20230625git01b1bd1+dfsg-3) ... 152s Selecting previously unselected package libdconf1:ppc64el. 152s Preparing to unpack .../017-libdconf1_0.40.0-4_ppc64el.deb ... 152s Unpacking libdconf1:ppc64el (0.40.0-4) ... 152s Selecting previously unselected package dconf-service. 152s Preparing to unpack .../018-dconf-service_0.40.0-4_ppc64el.deb ... 152s Unpacking dconf-service (0.40.0-4) ... 152s Selecting previously unselected package dconf-gsettings-backend:ppc64el. 152s Preparing to unpack .../019-dconf-gsettings-backend_0.40.0-4_ppc64el.deb ... 152s Unpacking dconf-gsettings-backend:ppc64el (0.40.0-4) ... 152s Selecting previously unselected package fonts-dejavu-mono. 152s Preparing to unpack .../020-fonts-dejavu-mono_2.37-8_all.deb ... 152s Unpacking fonts-dejavu-mono (2.37-8) ... 152s Selecting previously unselected package fonts-dejavu-core. 152s Preparing to unpack .../021-fonts-dejavu-core_2.37-8_all.deb ... 152s Unpacking fonts-dejavu-core (2.37-8) ... 152s Selecting previously unselected package fontconfig-config. 152s Preparing to unpack .../022-fontconfig-config_2.15.0-1ubuntu1_ppc64el.deb ... 152s Unpacking fontconfig-config (2.15.0-1ubuntu1) ... 152s Selecting previously unselected package libfontconfig1:ppc64el. 152s Preparing to unpack .../023-libfontconfig1_2.15.0-1ubuntu1_ppc64el.deb ... 152s Unpacking libfontconfig1:ppc64el (2.15.0-1ubuntu1) ... 152s Selecting previously unselected package fontconfig. 152s Preparing to unpack .../024-fontconfig_2.15.0-1ubuntu1_ppc64el.deb ... 152s Unpacking fontconfig (2.15.0-1ubuntu1) ... 152s Selecting previously unselected package libatk1.0-0:ppc64el. 152s Preparing to unpack .../025-libatk1.0-0_2.50.0-1_ppc64el.deb ... 152s Unpacking libatk1.0-0:ppc64el (2.50.0-1) ... 152s Selecting previously unselected package gir1.2-atk-1.0:ppc64el. 152s Preparing to unpack .../026-gir1.2-atk-1.0_2.50.0-1_ppc64el.deb ... 152s Unpacking gir1.2-atk-1.0:ppc64el (2.50.0-1) ... 152s Selecting previously unselected package libpixman-1-0:ppc64el. 152s Preparing to unpack .../027-libpixman-1-0_0.42.2-1_ppc64el.deb ... 152s Unpacking libpixman-1-0:ppc64el (0.42.2-1) ... 152s Selecting previously unselected package libxcb-render0:ppc64el. 152s Preparing to unpack .../028-libxcb-render0_1.15-1_ppc64el.deb ... 152s Unpacking libxcb-render0:ppc64el (1.15-1) ... 152s Selecting previously unselected package libxcb-shm0:ppc64el. 152s Preparing to unpack .../029-libxcb-shm0_1.15-1_ppc64el.deb ... 152s Unpacking libxcb-shm0:ppc64el (1.15-1) ... 152s Selecting previously unselected package libxrender1:ppc64el. 152s Preparing to unpack .../030-libxrender1_1%3a0.9.10-1.1_ppc64el.deb ... 152s Unpacking libxrender1:ppc64el (1:0.9.10-1.1) ... 152s Selecting previously unselected package libcairo2:ppc64el. 152s Preparing to unpack .../031-libcairo2_1.18.0-1_ppc64el.deb ... 152s Unpacking libcairo2:ppc64el (1.18.0-1) ... 152s Selecting previously unselected package libcairo-gobject2:ppc64el. 152s Preparing to unpack .../032-libcairo-gobject2_1.18.0-1_ppc64el.deb ... 152s Unpacking libcairo-gobject2:ppc64el (1.18.0-1) ... 152s Selecting previously unselected package gir1.2-freedesktop:ppc64el. 152s Preparing to unpack .../033-gir1.2-freedesktop_1.79.1-1_ppc64el.deb ... 152s Unpacking gir1.2-freedesktop:ppc64el (1.79.1-1) ... 152s Selecting previously unselected package gir1.2-gdkpixbuf-2.0:ppc64el. 152s Preparing to unpack .../034-gir1.2-gdkpixbuf-2.0_2.42.10+dfsg-3_ppc64el.deb ... 152s Unpacking gir1.2-gdkpixbuf-2.0:ppc64el (2.42.10+dfsg-3) ... 152s Selecting previously unselected package libgraphite2-3:ppc64el. 152s Preparing to unpack .../035-libgraphite2-3_1.3.14-2_ppc64el.deb ... 152s Unpacking libgraphite2-3:ppc64el (1.3.14-2) ... 152s Selecting previously unselected package libharfbuzz0b:ppc64el. 153s Preparing to unpack .../036-libharfbuzz0b_8.3.0-2_ppc64el.deb ... 153s Unpacking libharfbuzz0b:ppc64el (8.3.0-2) ... 153s Selecting previously unselected package libharfbuzz-gobject0:ppc64el. 153s Preparing to unpack .../037-libharfbuzz-gobject0_8.3.0-2_ppc64el.deb ... 153s Unpacking libharfbuzz-gobject0:ppc64el (8.3.0-2) ... 153s Selecting previously unselected package gir1.2-harfbuzz-0.0:ppc64el. 153s Preparing to unpack .../038-gir1.2-harfbuzz-0.0_8.3.0-2_ppc64el.deb ... 153s Unpacking gir1.2-harfbuzz-0.0:ppc64el (8.3.0-2) ... 153s Selecting previously unselected package libthai-data. 153s Preparing to unpack .../039-libthai-data_0.1.29-2_all.deb ... 153s Unpacking libthai-data (0.1.29-2) ... 153s Selecting previously unselected package libdatrie1:ppc64el. 153s Preparing to unpack .../040-libdatrie1_0.2.13-3_ppc64el.deb ... 153s Unpacking libdatrie1:ppc64el (0.2.13-3) ... 153s Selecting previously unselected package libthai0:ppc64el. 153s Preparing to unpack .../041-libthai0_0.1.29-2_ppc64el.deb ... 153s Unpacking libthai0:ppc64el (0.1.29-2) ... 153s Selecting previously unselected package libpango-1.0-0:ppc64el. 153s Preparing to unpack .../042-libpango-1.0-0_1.51.0+ds-4_ppc64el.deb ... 153s Unpacking libpango-1.0-0:ppc64el (1.51.0+ds-4) ... 153s Selecting previously unselected package libpangoft2-1.0-0:ppc64el. 153s Preparing to unpack .../043-libpangoft2-1.0-0_1.51.0+ds-4_ppc64el.deb ... 153s Unpacking libpangoft2-1.0-0:ppc64el (1.51.0+ds-4) ... 153s Selecting previously unselected package libpangocairo-1.0-0:ppc64el. 153s Preparing to unpack .../044-libpangocairo-1.0-0_1.51.0+ds-4_ppc64el.deb ... 153s Unpacking libpangocairo-1.0-0:ppc64el (1.51.0+ds-4) ... 153s Selecting previously unselected package libxft2:ppc64el. 153s Preparing to unpack .../045-libxft2_2.3.6-1_ppc64el.deb ... 153s Unpacking libxft2:ppc64el (2.3.6-1) ... 153s Selecting previously unselected package libpangoxft-1.0-0:ppc64el. 153s Preparing to unpack .../046-libpangoxft-1.0-0_1.51.0+ds-4_ppc64el.deb ... 153s Unpacking libpangoxft-1.0-0:ppc64el (1.51.0+ds-4) ... 153s Selecting previously unselected package gir1.2-pango-1.0:ppc64el. 153s Preparing to unpack .../047-gir1.2-pango-1.0_1.51.0+ds-4_ppc64el.deb ... 153s Unpacking gir1.2-pango-1.0:ppc64el (1.51.0+ds-4) ... 153s Selecting previously unselected package libxi6:ppc64el. 153s Preparing to unpack .../048-libxi6_2%3a1.8.1-1_ppc64el.deb ... 153s Unpacking libxi6:ppc64el (2:1.8.1-1) ... 153s Selecting previously unselected package libatspi2.0-0:ppc64el. 153s Preparing to unpack .../049-libatspi2.0-0_2.50.0-1_ppc64el.deb ... 153s Unpacking libatspi2.0-0:ppc64el (2.50.0-1) ... 153s Selecting previously unselected package libatk-bridge2.0-0:ppc64el. 153s Preparing to unpack .../050-libatk-bridge2.0-0_2.50.0-1_ppc64el.deb ... 153s Unpacking libatk-bridge2.0-0:ppc64el (2.50.0-1) ... 153s Selecting previously unselected package liblcms2-2:ppc64el. 153s Preparing to unpack .../051-liblcms2-2_2.14-2_ppc64el.deb ... 153s Unpacking liblcms2-2:ppc64el (2.14-2) ... 153s Selecting previously unselected package libcolord2:ppc64el. 153s Preparing to unpack .../052-libcolord2_1.4.7-1_ppc64el.deb ... 153s Unpacking libcolord2:ppc64el (1.4.7-1) ... 153s Selecting previously unselected package libavahi-common-data:ppc64el. 153s Preparing to unpack .../053-libavahi-common-data_0.8-13ubuntu2_ppc64el.deb ... 153s Unpacking libavahi-common-data:ppc64el (0.8-13ubuntu2) ... 153s Selecting previously unselected package libavahi-common3:ppc64el. 153s Preparing to unpack .../054-libavahi-common3_0.8-13ubuntu2_ppc64el.deb ... 153s Unpacking libavahi-common3:ppc64el (0.8-13ubuntu2) ... 153s Selecting previously unselected package libavahi-client3:ppc64el. 153s Preparing to unpack .../055-libavahi-client3_0.8-13ubuntu2_ppc64el.deb ... 153s Unpacking libavahi-client3:ppc64el (0.8-13ubuntu2) ... 153s Selecting previously unselected package libcups2:ppc64el. 153s Preparing to unpack .../056-libcups2_2.4.6-0ubuntu3_ppc64el.deb ... 153s Unpacking libcups2:ppc64el (2.4.6-0ubuntu3) ... 153s Selecting previously unselected package libepoxy0:ppc64el. 153s Preparing to unpack .../057-libepoxy0_1.5.10-1_ppc64el.deb ... 153s Unpacking libepoxy0:ppc64el (1.5.10-1) ... 153s Selecting previously unselected package libwayland-client0:ppc64el. 153s Preparing to unpack .../058-libwayland-client0_1.22.0-2.1_ppc64el.deb ... 153s Unpacking libwayland-client0:ppc64el (1.22.0-2.1) ... 153s Selecting previously unselected package libwayland-cursor0:ppc64el. 153s Preparing to unpack .../059-libwayland-cursor0_1.22.0-2.1_ppc64el.deb ... 153s Unpacking libwayland-cursor0:ppc64el (1.22.0-2.1) ... 153s Selecting previously unselected package libwayland-egl1:ppc64el. 153s Preparing to unpack .../060-libwayland-egl1_1.22.0-2.1_ppc64el.deb ... 153s Unpacking libwayland-egl1:ppc64el (1.22.0-2.1) ... 153s Selecting previously unselected package libxcomposite1:ppc64el. 153s Preparing to unpack .../061-libxcomposite1_1%3a0.4.5-1build2_ppc64el.deb ... 153s Unpacking libxcomposite1:ppc64el (1:0.4.5-1build2) ... 153s Selecting previously unselected package libxfixes3:ppc64el. 153s Preparing to unpack .../062-libxfixes3_1%3a6.0.0-2_ppc64el.deb ... 153s Unpacking libxfixes3:ppc64el (1:6.0.0-2) ... 153s Selecting previously unselected package libxcursor1:ppc64el. 153s Preparing to unpack .../063-libxcursor1_1%3a1.2.1-1_ppc64el.deb ... 153s Unpacking libxcursor1:ppc64el (1:1.2.1-1) ... 153s Selecting previously unselected package libxdamage1:ppc64el. 153s Preparing to unpack .../064-libxdamage1_1%3a1.1.6-1_ppc64el.deb ... 153s Unpacking libxdamage1:ppc64el (1:1.1.6-1) ... 153s Selecting previously unselected package libxinerama1:ppc64el. 153s Preparing to unpack .../065-libxinerama1_2%3a1.1.4-3_ppc64el.deb ... 153s Unpacking libxinerama1:ppc64el (2:1.1.4-3) ... 153s Selecting previously unselected package libxrandr2:ppc64el. 153s Preparing to unpack .../066-libxrandr2_2%3a1.5.2-2_ppc64el.deb ... 153s Unpacking libxrandr2:ppc64el (2:1.5.2-2) ... 153s Selecting previously unselected package libgtk-3-common. 153s Preparing to unpack .../067-libgtk-3-common_3.24.40-2ubuntu1_all.deb ... 153s Unpacking libgtk-3-common (3.24.40-2ubuntu1) ... 153s Selecting previously unselected package libgtk-3-0:ppc64el. 153s Preparing to unpack .../068-libgtk-3-0_3.24.40-2ubuntu1_ppc64el.deb ... 153s Unpacking libgtk-3-0:ppc64el (3.24.40-2ubuntu1) ... 153s Selecting previously unselected package gir1.2-gtk-3.0:ppc64el. 153s Preparing to unpack .../069-gir1.2-gtk-3.0_3.24.40-2ubuntu1_ppc64el.deb ... 153s Unpacking gir1.2-gtk-3.0:ppc64el (3.24.40-2ubuntu1) ... 153s Selecting previously unselected package libann0. 153s Preparing to unpack .../070-libann0_1.1.2+doc-9_ppc64el.deb ... 153s Unpacking libann0 (1.1.2+doc-9) ... 153s Selecting previously unselected package libcdt5:ppc64el. 153s Preparing to unpack .../071-libcdt5_2.42.2-8build1_ppc64el.deb ... 153s Unpacking libcdt5:ppc64el (2.42.2-8build1) ... 153s Selecting previously unselected package libcgraph6:ppc64el. 153s Preparing to unpack .../072-libcgraph6_2.42.2-8build1_ppc64el.deb ... 153s Unpacking libcgraph6:ppc64el (2.42.2-8build1) ... 153s Selecting previously unselected package libxpm4:ppc64el. 153s Preparing to unpack .../073-libxpm4_1%3a3.5.17-1_ppc64el.deb ... 153s Unpacking libxpm4:ppc64el (1:3.5.17-1) ... 153s Selecting previously unselected package libgd3:ppc64el. 153s Preparing to unpack .../074-libgd3_2.3.3-9ubuntu1_ppc64el.deb ... 153s Unpacking libgd3:ppc64el (2.3.3-9ubuntu1) ... 153s Selecting previously unselected package libgts-0.7-5:ppc64el. 153s Preparing to unpack .../075-libgts-0.7-5_0.7.6+darcs121130-5_ppc64el.deb ... 153s Unpacking libgts-0.7-5:ppc64el (0.7.6+darcs121130-5) ... 153s Selecting previously unselected package libltdl7:ppc64el. 153s Preparing to unpack .../076-libltdl7_2.4.7-7_ppc64el.deb ... 153s Unpacking libltdl7:ppc64el (2.4.7-7) ... 153s Selecting previously unselected package libpathplan4:ppc64el. 153s Preparing to unpack .../077-libpathplan4_2.42.2-8build1_ppc64el.deb ... 153s Unpacking libpathplan4:ppc64el (2.42.2-8build1) ... 153s Selecting previously unselected package libgvc6. 153s Preparing to unpack .../078-libgvc6_2.42.2-8build1_ppc64el.deb ... 153s Unpacking libgvc6 (2.42.2-8build1) ... 153s Selecting previously unselected package libgvpr2:ppc64el. 153s Preparing to unpack .../079-libgvpr2_2.42.2-8build1_ppc64el.deb ... 153s Unpacking libgvpr2:ppc64el (2.42.2-8build1) ... 153s Selecting previously unselected package liblab-gamut1:ppc64el. 153s Preparing to unpack .../080-liblab-gamut1_2.42.2-8build1_ppc64el.deb ... 153s Unpacking liblab-gamut1:ppc64el (2.42.2-8build1) ... 153s Selecting previously unselected package x11-common. 153s Preparing to unpack .../081-x11-common_1%3a7.7+23ubuntu2_all.deb ... 153s Unpacking x11-common (1:7.7+23ubuntu2) ... 154s Selecting previously unselected package libice6:ppc64el. 154s Preparing to unpack .../082-libice6_2%3a1.0.10-1build2_ppc64el.deb ... 154s Unpacking libice6:ppc64el (2:1.0.10-1build2) ... 154s Selecting previously unselected package libsm6:ppc64el. 154s Preparing to unpack .../083-libsm6_2%3a1.2.3-1build2_ppc64el.deb ... 154s Unpacking libsm6:ppc64el (2:1.2.3-1build2) ... 154s Selecting previously unselected package libxt6:ppc64el. 154s Preparing to unpack .../084-libxt6_1%3a1.2.1-1.1_ppc64el.deb ... 154s Unpacking libxt6:ppc64el (1:1.2.1-1.1) ... 154s Selecting previously unselected package libxmu6:ppc64el. 154s Preparing to unpack .../085-libxmu6_2%3a1.1.3-3_ppc64el.deb ... 154s Unpacking libxmu6:ppc64el (2:1.1.3-3) ... 154s Selecting previously unselected package libxaw7:ppc64el. 154s Preparing to unpack .../086-libxaw7_2%3a1.0.14-1_ppc64el.deb ... 154s Unpacking libxaw7:ppc64el (2:1.0.14-1) ... 154s Selecting previously unselected package graphviz. 154s Preparing to unpack .../087-graphviz_2.42.2-8build1_ppc64el.deb ... 154s Unpacking graphviz (2.42.2-8build1) ... 154s Selecting previously unselected package libblas3:ppc64el. 154s Preparing to unpack .../088-libblas3_3.12.0-3_ppc64el.deb ... 154s Unpacking libblas3:ppc64el (3.12.0-3) ... 154s Selecting previously unselected package libboost-filesystem1.83.0:ppc64el. 154s Preparing to unpack .../089-libboost-filesystem1.83.0_1.83.0-2ubuntu1_ppc64el.deb ... 154s Unpacking libboost-filesystem1.83.0:ppc64el (1.83.0-2ubuntu1) ... 154s Selecting previously unselected package libboost-iostreams1.83.0:ppc64el. 154s Preparing to unpack .../090-libboost-iostreams1.83.0_1.83.0-2ubuntu1_ppc64el.deb ... 154s Unpacking libboost-iostreams1.83.0:ppc64el (1.83.0-2ubuntu1) ... 154s Selecting previously unselected package libboost-program-options1.83.0:ppc64el. 154s Preparing to unpack .../091-libboost-program-options1.83.0_1.83.0-2ubuntu1_ppc64el.deb ... 154s Unpacking libboost-program-options1.83.0:ppc64el (1.83.0-2ubuntu1) ... 154s Selecting previously unselected package libboost-thread1.83.0:ppc64el. 154s Preparing to unpack .../092-libboost-thread1.83.0_1.83.0-2ubuntu1_ppc64el.deb ... 154s Unpacking libboost-thread1.83.0:ppc64el (1.83.0-2ubuntu1) ... 154s Selecting previously unselected package libgfortran5:ppc64el. 154s Preparing to unpack .../093-libgfortran5_14-20240303-1ubuntu1_ppc64el.deb ... 154s Unpacking libgfortran5:ppc64el (14-20240303-1ubuntu1) ... 154s Selecting previously unselected package liblapack3:ppc64el. 154s Preparing to unpack .../094-liblapack3_3.12.0-3_ppc64el.deb ... 154s Unpacking liblapack3:ppc64el (3.12.0-3) ... 154s Selecting previously unselected package libpython3.12t64:ppc64el. 154s Preparing to unpack .../095-libpython3.12t64_3.12.2-4build2_ppc64el.deb ... 154s Unpacking libpython3.12t64:ppc64el (3.12.2-4build2) ... 154s Selecting previously unselected package libtcl8.6:ppc64el. 154s Preparing to unpack .../096-libtcl8.6_8.6.13+dfsg-2_ppc64el.deb ... 154s Unpacking libtcl8.6:ppc64el (8.6.13+dfsg-2) ... 154s Selecting previously unselected package nextpnr-ice40-chipdb. 154s Preparing to unpack .../097-nextpnr-ice40-chipdb_0.6-3build4_ppc64el.deb ... 154s Unpacking nextpnr-ice40-chipdb (0.6-3build4) ... 156s Selecting previously unselected package nextpnr-ice40. 156s Preparing to unpack .../098-nextpnr-ice40_0.6-3build4_ppc64el.deb ... 156s Unpacking nextpnr-ice40 (0.6-3build4) ... 156s Selecting previously unselected package python3-cairo. 156s Preparing to unpack .../099-python3-cairo_1.25.1-2_ppc64el.deb ... 156s Unpacking python3-cairo (1.25.1-2) ... 156s Selecting previously unselected package python3-colorama. 156s Preparing to unpack .../100-python3-colorama_0.4.6-4_all.deb ... 156s Unpacking python3-colorama (0.4.6-4) ... 156s Selecting previously unselected package python3-click. 156s Preparing to unpack .../101-python3-click_8.1.6-1_all.deb ... 156s Unpacking python3-click (8.1.6-1) ... 156s Selecting previously unselected package python3-gi-cairo. 156s Preparing to unpack .../102-python3-gi-cairo_3.47.0-3_ppc64el.deb ... 156s Unpacking python3-gi-cairo (3.47.0-3) ... 156s Selecting previously unselected package python3-numpy. 156s Preparing to unpack .../103-python3-numpy_1%3a1.24.2-2_ppc64el.deb ... 156s Unpacking python3-numpy (1:1.24.2-2) ... 156s Selecting previously unselected package xdot. 156s Preparing to unpack .../104-xdot_1.3-1_all.deb ... 156s Unpacking xdot (1.3-1) ... 156s Selecting previously unselected package yosys. 156s Preparing to unpack .../105-yosys_0.23-6_ppc64el.deb ... 156s Unpacking yosys (0.23-6) ... 156s Selecting previously unselected package autopkgtest-satdep. 156s Preparing to unpack .../106-2-autopkgtest-satdep.deb ... 156s Unpacking autopkgtest-satdep (0) ... 157s Setting up libgraphite2-3:ppc64el (1.3.14-2) ... 157s Setting up liblcms2-2:ppc64el (2.14-2) ... 157s Setting up libboost-program-options1.83.0:ppc64el (1.83.0-2ubuntu1) ... 157s Setting up libpixman-1-0:ppc64el (0.42.2-1) ... 157s Setting up libsharpyuv0:ppc64el (1.3.2-0.4) ... 157s Setting up libxdamage1:ppc64el (1:1.1.6-1) ... 157s Setting up liblerc4:ppc64el (4.0.0+ds-4ubuntu1) ... 157s Setting up libxpm4:ppc64el (1:3.5.17-1) ... 157s Setting up hicolor-icon-theme (0.17-2) ... 157s Setting up libxi6:ppc64el (2:1.8.1-1) ... 157s Setting up libxrender1:ppc64el (1:0.9.10-1.1) ... 157s Setting up libdatrie1:ppc64el (0.2.13-3) ... 157s Setting up python3-colorama (0.4.6-4) ... 157s Setting up libxcb-render0:ppc64el (1.15-1) ... 157s Setting up nextpnr-ice40-chipdb (0.6-3build4) ... 157s Setting up liblab-gamut1:ppc64el (2.42.2-8build1) ... 157s Setting up libgdk-pixbuf2.0-common (2.42.10+dfsg-3) ... 157s Setting up libpython3.12-minimal:ppc64el (3.12.2-4build2) ... 157s Setting up x11-common (1:7.7+23ubuntu2) ... 158s Setting up libdeflate0:ppc64el (1.19-1) ... 158s Setting up libboost-thread1.83.0:ppc64el (1.83.0-2ubuntu1) ... 158s Setting up libxcb-shm0:ppc64el (1.15-1) ... 158s Setting up libatspi2.0-0:ppc64el (2.50.0-1) ... 158s Setting up libboost-filesystem1.83.0:ppc64el (1.83.0-2ubuntu1) ... 158s Setting up python3-click (8.1.6-1) ... 158s Setting up libjbig0:ppc64el (2.1-6.1ubuntu1) ... 158s Setting up libcolord2:ppc64el (1.4.7-1) ... 158s Setting up berkeley-abc (1.01+20230625git01b1bd1+dfsg-3) ... 158s Setting up libdconf1:ppc64el (0.40.0-4) ... 158s Setting up libgts-0.7-5:ppc64el (0.7.6+darcs121130-5) ... 158s Setting up libblas3:ppc64el (3.12.0-3) ... 158s update-alternatives: using /usr/lib/powerpc64le-linux-gnu/blas/libblas.so.3 to provide /usr/lib/powerpc64le-linux-gnu/libblas.so.3 (libblas.so.3-powerpc64le-linux-gnu) in auto mode 158s Setting up libepoxy0:ppc64el (1.5.10-1) ... 158s Setting up libxfixes3:ppc64el (1:6.0.0-2) ... 158s Setting up libboost-iostreams1.83.0:ppc64el (1.83.0-2ubuntu1) ... 158s Setting up libpathplan4:ppc64el (2.42.2-8build1) ... 158s Setting up libavahi-common-data:ppc64el (0.8-13ubuntu2) ... 158s Setting up libann0 (1.1.2+doc-9) ... 158s Setting up libxinerama1:ppc64el (2:1.1.4-3) ... 158s Setting up fonts-dejavu-mono (2.37-8) ... 158s Setting up libxrandr2:ppc64el (2:1.5.2-2) ... 158s Setting up libtcl8.6:ppc64el (8.6.13+dfsg-2) ... 158s Setting up fonts-dejavu-core (2.37-8) ... 158s Setting up libjpeg-turbo8:ppc64el (2.1.5-2ubuntu1) ... 158s Setting up libltdl7:ppc64el (2.4.7-7) ... 158s Setting up libgfortran5:ppc64el (14-20240303-1ubuntu1) ... 158s Setting up libwebp7:ppc64el (1.3.2-0.4) ... 158s Setting up at-spi2-common (2.50.0-1) ... 158s Setting up libharfbuzz0b:ppc64el (8.3.0-2) ... 158s Setting up libthai-data (0.1.29-2) ... 158s Setting up libcdt5:ppc64el (2.42.2-8build1) ... 158s Setting up libatk1.0-0:ppc64el (2.50.0-1) ... 158s Setting up libcgraph6:ppc64el (2.42.2-8build1) ... 158s Setting up libwayland-egl1:ppc64el (1.22.0-2.1) ... 158s Setting up libxcomposite1:ppc64el (1:0.4.5-1build2) ... 158s Setting up libwayland-client0:ppc64el (1.22.0-2.1) ... 158s Setting up libjpeg8:ppc64el (8c-2ubuntu11) ... 158s Setting up python3.12-minimal (3.12.2-4build2) ... 159s Setting up libice6:ppc64el (2:1.0.10-1build2) ... 159s Setting up liblapack3:ppc64el (3.12.0-3) ... 159s update-alternatives: using /usr/lib/powerpc64le-linux-gnu/lapack/liblapack.so.3 to provide /usr/lib/powerpc64le-linux-gnu/liblapack.so.3 (liblapack.so.3-powerpc64le-linux-gnu) in auto mode 159s Setting up libpython3.12-stdlib:ppc64el (3.12.2-4build2) ... 159s Setting up gir1.2-atk-1.0:ppc64el (2.50.0-1) ... 159s Setting up fontconfig-config (2.15.0-1ubuntu1) ... 159s Setting up python3.12 (3.12.2-4build2) ... 161s Setting up libxcursor1:ppc64el (1:1.2.1-1) ... 161s Setting up libavahi-common3:ppc64el (0.8-13ubuntu2) ... 161s Setting up dconf-service (0.40.0-4) ... 161s Setting up libharfbuzz-gobject0:ppc64el (8.3.0-2) ... 161s Setting up libpython3.12t64:ppc64el (3.12.2-4build2) ... 161s Setting up libatk-bridge2.0-0:ppc64el (2.50.0-1) ... 161s Setting up libthai0:ppc64el (0.1.29-2) ... 161s Setting up nextpnr-ice40 (0.6-3build4) ... 161s Setting up python3-numpy (1:1.24.2-2) ... 164s Setting up libgvpr2:ppc64el (2.42.2-8build1) ... 164s Setting up libtiff6:ppc64el (4.5.1+git230720-3ubuntu1) ... 164s Setting up libwayland-cursor0:ppc64el (1.22.0-2.1) ... 164s Setting up libgdk-pixbuf-2.0-0:ppc64el (2.42.10+dfsg-3) ... 164s Setting up libfontconfig1:ppc64el (2.15.0-1ubuntu1) ... 164s Setting up libsm6:ppc64el (2:1.2.3-1build2) ... 164s Setting up libavahi-client3:ppc64el (0.8-13ubuntu2) ... 164s Setting up gtk-update-icon-cache (3.24.40-2ubuntu1) ... 164s Setting up fontconfig (2.15.0-1ubuntu1) ... 166s Regenerating fonts cache... done. 166s Setting up libxft2:ppc64el (2.3.6-1) ... 166s Setting up dconf-gsettings-backend:ppc64el (0.40.0-4) ... 166s Setting up gir1.2-gdkpixbuf-2.0:ppc64el (2.42.10+dfsg-3) ... 166s Setting up libpango-1.0-0:ppc64el (1.51.0+ds-4) ... 166s Setting up libcairo2:ppc64el (1.18.0-1) ... 166s Setting up libgd3:ppc64el (2.3.3-9ubuntu1) ... 166s Setting up libxt6:ppc64el (1:1.2.1-1.1) ... 166s Setting up libcups2:ppc64el (2.4.6-0ubuntu3) ... 166s Setting up libcairo-gobject2:ppc64el (1.18.0-1) ... 166s Setting up libpangoft2-1.0-0:ppc64el (1.51.0+ds-4) ... 166s Setting up libgtk-3-common (3.24.40-2ubuntu1) ... 166s Setting up libpangocairo-1.0-0:ppc64el (1.51.0+ds-4) ... 166s Setting up libxmu6:ppc64el (2:1.1.3-3) ... 166s Setting up gir1.2-freedesktop:ppc64el (1.79.1-1) ... 166s Setting up python3-cairo (1.25.1-2) ... 166s Setting up libpangoxft-1.0-0:ppc64el (1.51.0+ds-4) ... 166s Setting up libxaw7:ppc64el (2:1.0.14-1) ... 166s Setting up gir1.2-harfbuzz-0.0:ppc64el (8.3.0-2) ... 166s Setting up gir1.2-pango-1.0:ppc64el (1.51.0+ds-4) ... 166s Setting up libgvc6 (2.42.2-8build1) ... 166s Setting up python3-gi-cairo (3.47.0-3) ... 166s Setting up graphviz (2.42.2-8build1) ... 166s Setting up adwaita-icon-theme (46~rc-1) ... 166s update-alternatives: using /usr/share/icons/Adwaita/cursor.theme to provide /usr/share/icons/default/index.theme (x-cursor-theme) in auto mode 166s Setting up humanity-icon-theme (0.6.16) ... 166s Setting up ubuntu-mono (24.04-0ubuntu1) ... 167s Processing triggers for systemd (255.2-3ubuntu2) ... 167s Processing triggers for man-db (2.12.0-3) ... 167s Processing triggers for libglib2.0-0t64:ppc64el (2.79.3-3ubuntu5) ... 167s Setting up libgtk-3-0:ppc64el (3.24.40-2ubuntu1) ... 167s Processing triggers for libc-bin (2.39-0ubuntu2) ... 167s Setting up gir1.2-gtk-3.0:ppc64el (3.24.40-2ubuntu1) ... 167s Setting up xdot (1.3-1) ... 167s Setting up yosys (0.23-6) ... 168s /usr/share/yosys/smtio.py:771: SyntaxWarning: invalid escape sequence '\|' 168s s = "/-\|" 168s /usr/share/yosys/smtio.py:1174: SyntaxWarning: invalid escape sequence '\[' 168s if re.match("[\[\]]", name) and name[0] != "\\": 168s Setting up autopkgtest-satdep (0) ... 170s (Reading database ... 85300 files and directories currently installed.) 170s Removing autopkgtest-satdep (0) ... 171s autopkgtest [00:12:27]: test examples-compile: [----------------------- 171s make: Entering directory '/tmp/autopkgtest.DyuG3m/build.kB5/src/examples/hx8kboard' 171s yosys -p 'synth_ice40 -top top -json example.json' example.v 171s 171s /----------------------------------------------------------------------------\ 171s | | 171s | yosys -- Yosys Open SYnthesis Suite | 171s | | 171s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 171s | | 171s | Permission to use, copy, modify, and/or distribute this software for any | 171s | purpose with or without fee is hereby granted, provided that the above | 171s | copyright notice and this permission notice appear in all copies. | 171s | | 171s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 171s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 171s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 171s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 171s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 171s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 171s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 171s | | 171s \----------------------------------------------------------------------------/ 171s 171s Yosys 0.23 (git sha1 7ce5011c24b) 171s 171s 171s -- Parsing `example.v' using frontend ` -vlog2k' -- 171s 171s 1. Executing Verilog-2005 frontend: example.v 171s Parsing Verilog input from `example.v' to AST representation. 171s Storing AST representation for module `$abstract\top'. 171s Successfully finished Verilog frontend. 171s 171s -- Running command `synth_ice40 -top top -json example.json' -- 171s 171s 2. Executing SYNTH_ICE40 pass. 171s 171s 2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v 171s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation. 171s Generating RTLIL representation for module `\SB_IO'. 171s Generating RTLIL representation for module `\SB_GB_IO'. 171s Generating RTLIL representation for module `\SB_GB'. 171s Generating RTLIL representation for module `\SB_LUT4'. 171s Generating RTLIL representation for module `\SB_CARRY'. 171s Generating RTLIL representation for module `\SB_DFF'. 171s Generating RTLIL representation for module `\SB_DFFE'. 171s Generating RTLIL representation for module `\SB_DFFSR'. 171s Generating RTLIL representation for module `\SB_DFFR'. 171s Generating RTLIL representation for module `\SB_DFFSS'. 171s Generating RTLIL representation for module `\SB_DFFS'. 171s Generating RTLIL representation for module `\SB_DFFESR'. 171s Generating RTLIL representation for module `\SB_DFFER'. 171s Generating RTLIL representation for module `\SB_DFFESS'. 171s Generating RTLIL representation for module `\SB_DFFES'. 171s Generating RTLIL representation for module `\SB_DFFN'. 171s Generating RTLIL representation for module `\SB_DFFNE'. 171s Generating RTLIL representation for module `\SB_DFFNSR'. 171s Generating RTLIL representation for module `\SB_DFFNR'. 171s Generating RTLIL representation for module `\SB_DFFNSS'. 171s Generating RTLIL representation for module `\SB_DFFNS'. 171s Generating RTLIL representation for module `\SB_DFFNESR'. 171s Generating RTLIL representation for module `\SB_DFFNER'. 171s Generating RTLIL representation for module `\SB_DFFNESS'. 171s Generating RTLIL representation for module `\SB_DFFNES'. 171s Generating RTLIL representation for module `\SB_RAM40_4K'. 171s Generating RTLIL representation for module `\SB_RAM40_4KNR'. 171s Generating RTLIL representation for module `\SB_RAM40_4KNW'. 171s Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. 171s Generating RTLIL representation for module `\ICESTORM_LC'. 171s Generating RTLIL representation for module `\SB_PLL40_CORE'. 171s Generating RTLIL representation for module `\SB_PLL40_PAD'. 171s Generating RTLIL representation for module `\SB_PLL40_2_PAD'. 171s Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. 171s Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. 171s Generating RTLIL representation for module `\SB_WARMBOOT'. 171s Generating RTLIL representation for module `\SB_SPRAM256KA'. 171s Generating RTLIL representation for module `\SB_HFOSC'. 171s Generating RTLIL representation for module `\SB_LFOSC'. 171s Generating RTLIL representation for module `\SB_RGBA_DRV'. 171s Generating RTLIL representation for module `\SB_LED_DRV_CUR'. 171s Generating RTLIL representation for module `\SB_RGB_DRV'. 171s Generating RTLIL representation for module `\SB_I2C'. 171s Generating RTLIL representation for module `\SB_SPI'. 171s Generating RTLIL representation for module `\SB_LEDDA_IP'. 171s Generating RTLIL representation for module `\SB_FILTER_50NS'. 171s Generating RTLIL representation for module `\SB_IO_I3C'. 171s Generating RTLIL representation for module `\SB_IO_OD'. 171s Generating RTLIL representation for module `\SB_MAC16'. 171s Generating RTLIL representation for module `\ICESTORM_RAM'. 171s Successfully finished Verilog frontend. 171s 171s 2.2. Executing HIERARCHY pass (managing design hierarchy). 171s 171s 2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\top'. 171s Generating RTLIL representation for module `\top'. 171s 171s 2.3.1. Analyzing design hierarchy.. 171s Top module: \top 171s 171s 2.3.2. Analyzing design hierarchy.. 171s Top module: \top 171s Removing unused module `$abstract\top'. 171s Removed 1 unused modules. 171s 171s 2.4. Executing PROC pass (convert processes to netlists). 171s 171s 2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 171s Cleaned up 0 empty switches. 171s 171s 2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 171s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241 in module SB_DFFNES. 171s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234 in module SB_DFFNESS. 171s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230 in module SB_DFFNER. 171s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223 in module SB_DFFNESR. 171s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220 in module SB_DFFNS. 171s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217 in module SB_DFFNSS. 171s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214 in module SB_DFFNR. 171s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211 in module SB_DFFNSR. 171s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203 in module SB_DFFES. 171s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196 in module SB_DFFESS. 171s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192 in module SB_DFFER. 171s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185 in module SB_DFFESR. 171s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182 in module SB_DFFS. 171s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179 in module SB_DFFSS. 171s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176 in module SB_DFFR. 171s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173 in module SB_DFFSR. 171s Removed a total of 0 dead cases. 171s 171s 2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 171s Removed 8 redundant assignments. 171s Promoted 25 assignments to connections. 171s 171s 2.4.4. Executing PROC_INIT pass (extract init attributes). 171s Found init rule in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 171s Set init value: \Q = 1'0 171s Found init rule in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 171s Set init value: \Q = 1'0 171s Found init rule in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 171s Set init value: \Q = 1'0 171s Found init rule in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 171s Set init value: \Q = 1'0 171s Found init rule in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 171s Set init value: \Q = 1'0 171s Found init rule in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 171s Set init value: \Q = 1'0 171s Found init rule in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 171s Set init value: \Q = 1'0 171s Found init rule in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 171s Set init value: \Q = 1'0 171s Found init rule in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 171s Set init value: \Q = 1'0 171s Found init rule in `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 171s Set init value: \Q = 1'0 171s Found init rule in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 171s Set init value: \Q = 1'0 171s Found init rule in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 171s Set init value: \Q = 1'0 171s Found init rule in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 171s Set init value: \Q = 1'0 171s Found init rule in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 171s Set init value: \Q = 1'0 171s Found init rule in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 171s Set init value: \Q = 1'0 171s Found init rule in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 171s Set init value: \Q = 1'0 171s Found init rule in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 171s Set init value: \Q = 1'0 171s Found init rule in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 171s Set init value: \Q = 1'0 171s Found init rule in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 171s Set init value: \Q = 1'0 171s Found init rule in `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 171s Set init value: \Q = 1'0 171s Found init rule in `\top.$proc$example.v:16$386'. 171s Set init value: \counter = 30'000000000000000000000000000000 171s 171s 2.4.5. Executing PROC_ARST pass (detect async resets in processes). 171s Found async reset \S in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 171s Found async reset \R in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 171s Found async reset \S in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 171s Found async reset \R in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 171s Found async reset \S in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 171s Found async reset \R in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 171s Found async reset \S in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 171s Found async reset \R in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 171s 171s 2.4.6. Executing PROC_ROM pass (convert switches to ROMs). 171s Converted 0 switches. 171s 171s 171s 2.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 171s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 171s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 171s 1/1: $0\Q[0:0] 171s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 171s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 171s 1/1: $0\Q[0:0] 171s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 171s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 171s 1/1: $0\Q[0:0] 171s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 171s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 171s 1/1: $0\Q[0:0] 171s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 171s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 171s 1/1: $0\Q[0:0] 171s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 171s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 171s 1/1: $0\Q[0:0] 171s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 171s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 171s 1/1: $0\Q[0:0] 171s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 171s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 171s 1/1: $0\Q[0:0] 171s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 171s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 171s 1/1: $0\Q[0:0] 171s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 171s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 171s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 171s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 171s 1/1: $0\Q[0:0] 171s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 171s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 171s 1/1: $0\Q[0:0] 171s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 171s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 171s 1/1: $0\Q[0:0] 171s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 171s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 171s 1/1: $0\Q[0:0] 171s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 171s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 171s 1/1: $0\Q[0:0] 171s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 171s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 171s 1/1: $0\Q[0:0] 171s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 171s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 171s 1/1: $0\Q[0:0] 171s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 171s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 171s 1/1: $0\Q[0:0] 171s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 171s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 171s 1/1: $0\Q[0:0] 171s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 171s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 171s Creating decoders for process `\top.$proc$example.v:16$386'. 171s Creating decoders for process `\top.$proc$example.v:19$381'. 171s 171s 2.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). 171s 171s 2.4.9. Executing PROC_DFF pass (convert process syncs to FFs). 171s Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 171s created $adff cell `$procdff$431' with negative edge clock and positive level reset. 171s Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 171s created $dff cell `$procdff$432' with negative edge clock. 171s Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 171s created $adff cell `$procdff$433' with negative edge clock and positive level reset. 171s Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 171s created $dff cell `$procdff$434' with negative edge clock. 171s Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 171s created $adff cell `$procdff$435' with negative edge clock and positive level reset. 171s Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 171s created $dff cell `$procdff$436' with negative edge clock. 171s Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 171s created $adff cell `$procdff$437' with negative edge clock and positive level reset. 171s Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 171s created $dff cell `$procdff$438' with negative edge clock. 171s Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 171s created $dff cell `$procdff$439' with negative edge clock. 171s Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 171s created $dff cell `$procdff$440' with negative edge clock. 171s Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 171s created $adff cell `$procdff$441' with positive edge clock and positive level reset. 171s Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 171s created $dff cell `$procdff$442' with positive edge clock. 171s Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 171s created $adff cell `$procdff$443' with positive edge clock and positive level reset. 171s Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 171s created $dff cell `$procdff$444' with positive edge clock. 171s Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 171s created $adff cell `$procdff$445' with positive edge clock and positive level reset. 171s Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 171s created $dff cell `$procdff$446' with positive edge clock. 171s Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 171s created $adff cell `$procdff$447' with positive edge clock and positive level reset. 171s Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 171s created $dff cell `$procdff$448' with positive edge clock. 171s Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 171s created $dff cell `$procdff$449' with positive edge clock. 171s Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 171s created $dff cell `$procdff$450' with positive edge clock. 171s Creating register for signal `\top.\counter' using process `\top.$proc$example.v:19$381'. 171s created $dff cell `$procdff$451' with positive edge clock. 171s Creating register for signal `\top.\outcnt' using process `\top.$proc$example.v:19$381'. 171s created $dff cell `$procdff$452' with positive edge clock. 171s 171s 2.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 171s 171s 2.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 171s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 171s Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 171s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 171s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 171s Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 171s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 171s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 171s Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 171s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 171s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 171s Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 171s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 171s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 171s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 171s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 171s Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 171s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 171s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 171s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 171s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 171s Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 171s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 171s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 171s Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 171s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 171s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 171s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 171s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 171s Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 171s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 171s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 171s Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 171s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 171s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 171s Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 171s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 171s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 171s Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 171s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 171s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 171s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 171s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 171s Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 171s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 171s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 171s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 171s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 171s Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 171s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 171s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 171s Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 171s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 171s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 171s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 171s Removing empty process `top.$proc$example.v:16$386'. 171s Removing empty process `top.$proc$example.v:19$381'. 171s Cleaned up 18 empty switches. 171s 171s 2.4.12. Executing OPT_EXPR pass (perform const folding). 171s Optimizing module top. 171s 171s 171s 2.5. Executing FLATTEN pass (flatten design). 171s 171s 2.6. Executing TRIBUF pass. 171s 171s 2.7. Executing DEMINOUT pass (demote inout ports to input or output). 171s 171s 2.8. Executing OPT_EXPR pass (perform const folding). 171s Optimizing module top. 171s 171s 2.9. Executing OPT_CLEAN pass (remove unused cells and wires). 171s Finding unused cells or wires in module \top.. 171s Removed 0 unused cells and 5 unused wires. 171s 171s 171s 2.10. Executing CHECK pass (checking for obvious problems). 171s Checking module top... 171s Found and reported 0 problems. 171s 171s 2.11. Executing OPT pass (performing simple optimizations). 171s 171s 2.11.1. Executing OPT_EXPR pass (perform const folding). 171s Optimizing module top. 171s 171s 2.11.2. Executing OPT_MERGE pass (detect identical cells). 171s Finding identical cells in module `\top'. 171s Removed a total of 0 cells. 171s 171s 2.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 171s Running muxtree optimizer on module \top.. 171s Creating internal representation of mux trees. 171s No muxes found in this module. 171s Removed 0 multiplexer ports. 171s 171s 2.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 171s Optimizing cells in module \top. 171s Performed a total of 0 changes. 171s 171s 2.11.5. Executing OPT_MERGE pass (detect identical cells). 171s Finding identical cells in module `\top'. 171s Removed a total of 0 cells. 171s 171s 2.11.6. Executing OPT_DFF pass (perform DFF optimizations). 171s 171s 2.11.7. Executing OPT_CLEAN pass (remove unused cells and wires). 171s Finding unused cells or wires in module \top.. 171s 171s 2.11.8. Executing OPT_EXPR pass (perform const folding). 171s Optimizing module top. 171s 171s 2.11.9. Finished OPT passes. (There is nothing left to do.) 171s 171s 2.12. Executing FSM pass (extract and optimize FSM). 171s 171s 2.12.1. Executing FSM_DETECT pass (finding FSMs in design). 171s 171s 2.12.2. Executing FSM_EXTRACT pass (extracting FSM from design). 171s 171s 2.12.3. Executing FSM_OPT pass (simple optimizations of FSMs). 171s 171s 2.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). 171s Finding unused cells or wires in module \top.. 171s 171s 2.12.5. Executing FSM_OPT pass (simple optimizations of FSMs). 171s 171s 2.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 171s 171s 2.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 171s 171s 2.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 171s 171s 2.13. Executing OPT pass (performing simple optimizations). 171s 171s 2.13.1. Executing OPT_EXPR pass (perform const folding). 171s Optimizing module top. 171s 171s 2.13.2. Executing OPT_MERGE pass (detect identical cells). 171s Finding identical cells in module `\top'. 171s Removed a total of 0 cells. 171s 171s 2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 171s Running muxtree optimizer on module \top.. 171s Creating internal representation of mux trees. 171s No muxes found in this module. 171s Removed 0 multiplexer ports. 171s 171s 2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 171s Optimizing cells in module \top. 171s Performed a total of 0 changes. 171s 171s 2.13.5. Executing OPT_MERGE pass (detect identical cells). 171s Finding identical cells in module `\top'. 171s Removed a total of 0 cells. 171s 171s 2.13.6. Executing OPT_DFF pass (perform DFF optimizations). 171s 171s 2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). 171s Finding unused cells or wires in module \top.. 171s 171s 2.13.8. Executing OPT_EXPR pass (perform const folding). 171s Optimizing module top. 171s 171s 2.13.9. Finished OPT passes. (There is nothing left to do.) 171s 171s 2.14. Executing WREDUCE pass (reducing word size of cells). 171s Removed top 31 bits (of 32) from port B of cell top.$add$example.v:20$382 ($add). 171s Removed top 2 bits (of 32) from port Y of cell top.$add$example.v:20$382 ($add). 171s Removed top 1 bits (of 8) from port B of cell top.$xor$example.v:24$385 ($xor). 171s 171s 2.15. Executing PEEPOPT pass (run peephole optimizers). 171s 171s 2.16. Executing OPT_CLEAN pass (remove unused cells and wires). 171s Finding unused cells or wires in module \top.. 171s Removed 0 unused cells and 1 unused wires. 171s 171s 171s 2.17. Executing SHARE pass (SAT-based resource sharing). 171s 171s 2.18. Executing TECHMAP pass (map to technology primitives). 171s 171s 2.18.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v 171s Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation. 171s Generating RTLIL representation for module `\_90_lut_cmp_'. 171s Successfully finished Verilog frontend. 171s 171s 2.18.2. Continuing TECHMAP pass. 171s No more expansions possible. 171s 171s 171s 2.19. Executing OPT_EXPR pass (perform const folding). 171s Optimizing module top. 171s 171s 2.20. Executing OPT_CLEAN pass (remove unused cells and wires). 171s Finding unused cells or wires in module \top.. 171s 171s 2.21. Executing ALUMACC pass (create $alu and $macc cells). 171s Extracting $alu and $macc cells in module top: 171s creating $macc model for $add$example.v:20$382 ($add). 171s creating $alu model for $macc $add$example.v:20$382. 171s creating $alu cell for $add$example.v:20$382: $auto$alumacc.cc:485:replace_alu$454 171s created 1 $alu and 0 $macc cells. 171s 171s 2.22. Executing OPT pass (performing simple optimizations). 171s 171s 2.22.1. Executing OPT_EXPR pass (perform const folding). 171s Optimizing module top. 171s 171s 2.22.2. Executing OPT_MERGE pass (detect identical cells). 171s Finding identical cells in module `\top'. 171s Removed a total of 0 cells. 171s 171s 2.22.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 171s Running muxtree optimizer on module \top.. 171s Creating internal representation of mux trees. 171s No muxes found in this module. 171s Removed 0 multiplexer ports. 171s 171s 2.22.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 171s Optimizing cells in module \top. 171s Performed a total of 0 changes. 171s 171s 2.22.5. Executing OPT_MERGE pass (detect identical cells). 171s Finding identical cells in module `\top'. 171s Removed a total of 0 cells. 171s 171s 2.22.6. Executing OPT_DFF pass (perform DFF optimizations). 171s 171s 2.22.7. Executing OPT_CLEAN pass (remove unused cells and wires). 171s Finding unused cells or wires in module \top.. 171s 171s 2.22.8. Executing OPT_EXPR pass (perform const folding). 171s Optimizing module top. 171s 171s 2.22.9. Finished OPT passes. (There is nothing left to do.) 171s 171s 2.23. Executing MEMORY pass. 171s 171s 2.23.1. Executing OPT_MEM pass (optimize memories). 171s Performed a total of 0 transformations. 171s 171s 2.23.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). 171s Performed a total of 0 transformations. 171s 171s 2.23.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 171s 171s 2.23.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 171s 171s 2.23.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 171s 171s 2.23.6. Executing OPT_CLEAN pass (remove unused cells and wires). 171s Finding unused cells or wires in module \top.. 171s 171s 2.23.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 171s 171s 2.23.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). 171s Performed a total of 0 transformations. 171s 171s 2.23.9. Executing OPT_CLEAN pass (remove unused cells and wires). 171s Finding unused cells or wires in module \top.. 171s 171s 2.23.10. Executing MEMORY_COLLECT pass (generating $mem cells). 171s 171s 2.24. Executing OPT_CLEAN pass (remove unused cells and wires). 171s Finding unused cells or wires in module \top.. 171s 171s 2.25. Executing MEMORY_LIBMAP pass (mapping memories to cells). 171s 171s 2.26. Executing TECHMAP pass (map to technology primitives). 171s 171s 2.26.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v 172s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation. 172s Generating RTLIL representation for module `\$__ICE40_RAM4K_'. 172s Successfully finished Verilog frontend. 172s 172s 2.26.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/spram_map.v 172s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/spram_map.v' to AST representation. 172s Generating RTLIL representation for module `\$__ICE40_SPRAM_'. 172s Successfully finished Verilog frontend. 172s 172s 2.26.3. Continuing TECHMAP pass. 172s No more expansions possible. 172s 172s 172s 2.27. Executing ICE40_BRAMINIT pass. 172s 172s 2.28. Executing OPT pass (performing simple optimizations). 172s 172s 2.28.1. Executing OPT_EXPR pass (perform const folding). 172s Optimizing module top. 172s 172s 172s 2.28.2. Executing OPT_MERGE pass (detect identical cells). 172s Finding identical cells in module `\top'. 172s Removed a total of 0 cells. 172s 172s 2.28.3. Executing OPT_DFF pass (perform DFF optimizations). 172s 172s 2.28.4. Executing OPT_CLEAN pass (remove unused cells and wires). 172s Finding unused cells or wires in module \top.. 172s Removed 0 unused cells and 2 unused wires. 172s 172s 172s 2.28.5. Finished fast OPT passes. 172s 172s 2.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 172s 172s 2.30. Executing OPT pass (performing simple optimizations). 172s 172s 2.30.1. Executing OPT_EXPR pass (perform const folding). 172s Optimizing module top. 172s 172s 2.30.2. Executing OPT_MERGE pass (detect identical cells). 172s Finding identical cells in module `\top'. 172s Removed a total of 0 cells. 172s 172s 2.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 172s Running muxtree optimizer on module \top.. 172s Creating internal representation of mux trees. 172s No muxes found in this module. 172s Removed 0 multiplexer ports. 172s 172s 2.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 172s Optimizing cells in module \top. 172s Performed a total of 0 changes. 172s 172s 2.30.5. Executing OPT_MERGE pass (detect identical cells). 172s Finding identical cells in module `\top'. 172s Removed a total of 0 cells. 172s 172s 2.30.6. Executing OPT_DFF pass (perform DFF optimizations). 172s 172s 2.30.7. Executing OPT_CLEAN pass (remove unused cells and wires). 172s Finding unused cells or wires in module \top.. 172s 172s 2.30.8. Executing OPT_EXPR pass (perform const folding). 172s Optimizing module top. 172s 172s 2.30.9. Finished OPT passes. (There is nothing left to do.) 172s 172s 2.31. Executing ICE40_WRAPCARRY pass (wrap carries). 172s 172s 2.32. Executing TECHMAP pass (map to technology primitives). 172s 172s 2.32.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v 172s Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation. 172s Generating RTLIL representation for module `\_90_simplemap_bool_ops'. 172s Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. 172s Generating RTLIL representation for module `\_90_simplemap_logic_ops'. 172s Generating RTLIL representation for module `\_90_simplemap_compare_ops'. 172s Generating RTLIL representation for module `\_90_simplemap_various'. 172s Generating RTLIL representation for module `\_90_simplemap_registers'. 172s Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. 172s Generating RTLIL representation for module `\_90_shift_shiftx'. 172s Generating RTLIL representation for module `\_90_fa'. 172s Generating RTLIL representation for module `\_90_lcu'. 172s Generating RTLIL representation for module `\_90_alu'. 172s Generating RTLIL representation for module `\_90_macc'. 172s Generating RTLIL representation for module `\_90_alumacc'. 172s Generating RTLIL representation for module `\$__div_mod_u'. 172s Generating RTLIL representation for module `\$__div_mod_trunc'. 172s Generating RTLIL representation for module `\_90_div'. 172s Generating RTLIL representation for module `\_90_mod'. 172s Generating RTLIL representation for module `\$__div_mod_floor'. 172s Generating RTLIL representation for module `\_90_divfloor'. 172s Generating RTLIL representation for module `\_90_modfloor'. 172s Generating RTLIL representation for module `\_90_pow'. 172s Generating RTLIL representation for module `\_90_pmux'. 172s Generating RTLIL representation for module `\_90_demux'. 172s Generating RTLIL representation for module `\_90_lut'. 172s Successfully finished Verilog frontend. 172s 172s 2.32.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v 172s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation. 172s Generating RTLIL representation for module `\_80_ice40_alu'. 172s Successfully finished Verilog frontend. 172s 172s 2.32.3. Continuing TECHMAP pass. 172s Using template $paramod$44a13d10af618e7fbe7b9aad2f6151ffcee1e2fa\_80_ice40_alu for cells of type $alu. 172s Using extmapper simplemap for cells of type $xor. 172s Using extmapper simplemap for cells of type $dff. 172s Using extmapper simplemap for cells of type $mux. 172s Using extmapper simplemap for cells of type $not. 172s Using extmapper simplemap for cells of type $pos. 172s No more expansions possible. 172s 172s 172s 2.33. Executing OPT pass (performing simple optimizations). 172s 172s 2.33.1. Executing OPT_EXPR pass (perform const folding). 172s Optimizing module top. 172s 172s 172s 2.33.2. Executing OPT_MERGE pass (detect identical cells). 172s Finding identical cells in module `\top'. 172s 172s Removed a total of 1 cells. 172s 172s 2.33.3. Executing OPT_DFF pass (perform DFF optimizations). 172s 172s 2.33.4. Executing OPT_CLEAN pass (remove unused cells and wires). 172s Finding unused cells or wires in module \top.. 172s Removed 30 unused cells and 17 unused wires. 172s 172s 172s 2.33.5. Finished fast OPT passes. 172s 172s 2.34. Executing ICE40_OPT pass (performing simple optimizations). 172s 172s 2.34.1. Running ICE40 specific optimizations. 172s Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$454.slice[0].carry: CO=\counter [0] 172s 172s 2.34.2. Executing OPT_EXPR pass (perform const folding). 172s Optimizing module top. 172s 172s 2.34.3. Executing OPT_MERGE pass (detect identical cells). 172s Finding identical cells in module `\top'. 172s Removed a total of 0 cells. 172s 172s 2.34.4. Executing OPT_DFF pass (perform DFF optimizations). 172s 172s 2.34.5. Executing OPT_CLEAN pass (remove unused cells and wires). 172s Finding unused cells or wires in module \top.. 172s 172s 2.34.6. Rerunning OPT passes. (Removed registers in this run.) 172s 172s 2.34.7. Running ICE40 specific optimizations. 172s 172s 2.34.8. Executing OPT_EXPR pass (perform const folding). 172s Optimizing module top. 172s 172s 2.34.9. Executing OPT_MERGE pass (detect identical cells). 172s Finding identical cells in module `\top'. 172s Removed a total of 0 cells. 172s 172s 2.34.10. Executing OPT_DFF pass (perform DFF optimizations). 172s 172s 2.34.11. Executing OPT_CLEAN pass (remove unused cells and wires). 172s Finding unused cells or wires in module \top.. 172s 172s 2.34.12. Finished OPT passes. (There is nothing left to do.) 172s 172s 2.35. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 172s 172s 2.36. Executing TECHMAP pass (map to technology primitives). 172s 172s 2.36.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 172s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 172s Generating RTLIL representation for module `\$_DFF_N_'. 172s Generating RTLIL representation for module `\$_DFF_P_'. 172s Generating RTLIL representation for module `\$_DFFE_NP_'. 172s Generating RTLIL representation for module `\$_DFFE_PP_'. 172s Generating RTLIL representation for module `\$_DFF_NP0_'. 172s Generating RTLIL representation for module `\$_DFF_NP1_'. 172s Generating RTLIL representation for module `\$_DFF_PP0_'. 172s Generating RTLIL representation for module `\$_DFF_PP1_'. 172s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 172s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 172s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 172s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 172s Generating RTLIL representation for module `\$_SDFF_NP0_'. 172s Generating RTLIL representation for module `\$_SDFF_NP1_'. 172s Generating RTLIL representation for module `\$_SDFF_PP0_'. 172s Generating RTLIL representation for module `\$_SDFF_PP1_'. 172s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 172s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 172s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 172s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 172s Successfully finished Verilog frontend. 172s 172s 2.36.2. Continuing TECHMAP pass. 172s Using template \$_DFF_P_ for cells of type $_DFF_P_. 172s No more expansions possible. 172s 172s 172s 2.37. Executing OPT_EXPR pass (perform const folding). 172s Optimizing module top. 172s 172s 2.38. Executing SIMPLEMAP pass (map simple cells to gate primitives). 172s Mapping top.$auto$alumacc.cc:485:replace_alu$454.slice[0].carry ($lut). 172s 172s 2.39. Executing ICE40_OPT pass (performing simple optimizations). 172s 172s 2.39.1. Running ICE40 specific optimizations. 172s 172s 2.39.2. Executing OPT_EXPR pass (perform const folding). 172s Optimizing module top. 172s 172s 172s 2.39.3. Executing OPT_MERGE pass (detect identical cells). 172s Finding identical cells in module `\top'. 172s Removed a total of 0 cells. 172s 172s 2.39.4. Executing OPT_DFF pass (perform DFF optimizations). 172s 172s 2.39.5. Executing OPT_CLEAN pass (remove unused cells and wires). 172s Finding unused cells or wires in module \top.. 172s Removed 0 unused cells and 156 unused wires. 172s 172s 172s 2.39.6. Rerunning OPT passes. (Removed registers in this run.) 172s 172s 2.39.7. Running ICE40 specific optimizations. 172s 172s 2.39.8. Executing OPT_EXPR pass (perform const folding). 172s Optimizing module top. 172s 172s 2.39.9. Executing OPT_MERGE pass (detect identical cells). 172s Finding identical cells in module `\top'. 172s Removed a total of 0 cells. 172s 172s 2.39.10. Executing OPT_DFF pass (perform DFF optimizations). 172s 172s 2.39.11. Executing OPT_CLEAN pass (remove unused cells and wires). 172s Finding unused cells or wires in module \top.. 172s 172s 2.39.12. Finished OPT passes. (There is nothing left to do.) 172s 172s 2.40. Executing TECHMAP pass (map to technology primitives). 172s 172s 2.40.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v 172s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation. 172s Generating RTLIL representation for module `\$_DLATCH_N_'. 172s Generating RTLIL representation for module `\$_DLATCH_P_'. 172s Successfully finished Verilog frontend. 172s 172s 2.40.2. Continuing TECHMAP pass. 172s No more expansions possible. 172s 172s 172s 2.41. Executing ABC pass (technology mapping using ABC). 172s 172s 2.41.1. Extracting gate netlist of module `\top' to `/input.blif'.. 172s Extracted 8 gates and 17 wires to a netlist network with 9 inputs and 8 outputs. 172s 172s 2.41.1.1. Executing ABC. 172s Running ABC command: "berkeley-abc" -s -f /abc.script 2>&1 172s ABC: ABC command line: "source /abc.script". 172s ABC: 172s ABC: + read_blif /input.blif 172s ABC: + read_lut /lutdefs.txt 172s ABC: + strash 172s ABC: + &get -n 172s ABC: + &fraig -x 172s ABC: + &put 172s ABC: + scorr 172s ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). 172s ABC: + dc2 172s ABC: + dretime 172s ABC: + strash 172s ABC: + dch -f 172s ABC: + if 172s ABC: + mfs2 172s ABC: + lutpack -S 1 172s ABC: + dress /input.blif 172s ABC: Total number of equiv classes = 9. 172s ABC: Participating nodes from both networks = 16. 172s ABC: Participating nodes from the first network = 8. ( 88.89 % of nodes) 172s ABC: Participating nodes from the second network = 8. ( 88.89 % of nodes) 172s ABC: Node pairs (any polarity) = 8. ( 88.89 % of names can be moved) 172s ABC: Node pairs (same polarity) = 8. ( 88.89 % of names can be moved) 172s ABC: Total runtime = 0.00 sec 172s ABC: + write_blif /output.blif 172s 172s 2.41.1.2. Re-integrating ABC results. 172s ABC RESULTS: $lut cells: 8 172s ABC RESULTS: internal signals: 0 172s ABC RESULTS: input signals: 9 172s ABC RESULTS: output signals: 8 172s Removing temp directory. 172s 172s 2.42. Executing ICE40_WRAPCARRY pass (wrap carries). 172s 172s 2.43. Executing TECHMAP pass (map to technology primitives). 172s 172s 2.43.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 172s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 172s Generating RTLIL representation for module `\$_DFF_N_'. 172s Generating RTLIL representation for module `\$_DFF_P_'. 172s Generating RTLIL representation for module `\$_DFFE_NP_'. 172s Generating RTLIL representation for module `\$_DFFE_PP_'. 172s Generating RTLIL representation for module `\$_DFF_NP0_'. 172s Generating RTLIL representation for module `\$_DFF_NP1_'. 172s Generating RTLIL representation for module `\$_DFF_PP0_'. 172s Generating RTLIL representation for module `\$_DFF_PP1_'. 172s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 172s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 172s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 172s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 172s Generating RTLIL representation for module `\$_SDFF_NP0_'. 172s Generating RTLIL representation for module `\$_SDFF_NP1_'. 172s Generating RTLIL representation for module `\$_SDFF_PP0_'. 172s Generating RTLIL representation for module `\$_SDFF_PP1_'. 172s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 172s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 172s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 172s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 172s Successfully finished Verilog frontend. 172s 172s 2.43.2. Continuing TECHMAP pass. 172s No more expansions possible. 172s 172s Removed 1 unused cells and 18 unused wires. 172s 172s 2.44. Executing OPT_LUT pass (optimize LUTs). 172s Discovering LUTs. 172s Number of LUTs: 37 172s 1-LUT 1 172s 2-LUT 8 172s 3-LUT 28 172s with \SB_CARRY (#0) 28 172s with \SB_CARRY (#1) 28 172s 172s Eliminating LUTs. 172s Number of LUTs: 37 172s 1-LUT 1 172s 2-LUT 8 172s 3-LUT 28 172s with \SB_CARRY (#0) 28 172s with \SB_CARRY (#1) 28 172s 172s Combining LUTs. 172s Number of LUTs: 37 172s 1-LUT 1 172s 2-LUT 8 172s 3-LUT 28 172s with \SB_CARRY (#0) 28 172s with \SB_CARRY (#1) 28 172s 172s Eliminated 0 LUTs. 172s Combined 0 LUTs. 172s 172s 172s 2.45. Executing TECHMAP pass (map to technology primitives). 172s 172s 2.45.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v 172s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation. 172s Generating RTLIL representation for module `\$lut'. 172s Successfully finished Verilog frontend. 172s 172s 2.45.2. Continuing TECHMAP pass. 172s Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut. 172s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut. 172s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. 172s No more expansions possible. 172s 172s Removed 0 unused cells and 74 unused wires. 172s 172s 2.46. Executing AUTONAME pass. 172s Renamed 163 objects in module top (4 iterations). 172s 172s 172s 2.47. Executing HIERARCHY pass (managing design hierarchy). 172s 172s 2.47.1. Analyzing design hierarchy.. 172s Top module: \top 172s 172s 2.47.2. Analyzing design hierarchy.. 172s Top module: \top 172s Removed 0 unused modules. 172s 172s 2.48. Printing statistics. 172s 172s === top === 172s 172s Number of wires: 13 172s Number of wire bits: 107 172s Number of public wires: 13 172s Number of public wire bits: 107 172s Number of memories: 0 172s Number of memory bits: 0 172s Number of processes: 0 172s Number of cells: 103 172s SB_CARRY 28 172s SB_DFF 38 172s SB_LUT4 37 172s 172s 2.49. Executing CHECK pass (checking for obvious problems). 172s Checking module top... 172s Found and reported 0 problems. 172s 172s 2.50. Executing JSON backend. 172s 172s End of script. Logfile hash: a82be2095c, CPU: user 0.98s system 0.03s, MEM: 22.00 MB peak 172s Yosys 0.23 (git sha1 7ce5011c24b) 172s Time spent: 67% 13x read_verilog (0 sec), 6% 1x synth_ice40 (0 sec), ... 172s nextpnr-ice40 --hx8k --package ct256 --asc example.asc --pcf hx8kboard.pcf --json example.json 172s Info: constrained 'LED0' to bel 'X7/Y33/io1' 172s Info: constrained 'LED1' to bel 'X6/Y33/io1' 172s Info: constrained 'LED2' to bel 'X5/Y33/io1' 172s Info: constrained 'LED3' to bel 'X4/Y33/io1' 172s Info: constrained 'LED4' to bel 'X4/Y33/io0' 172s Info: constrained 'LED5' to bel 'X3/Y33/io1' 172s Info: constrained 'LED6' to bel 'X3/Y33/io0' 172s Info: constrained 'LED7' to bel 'X1/Y33/io0' 172s Info: constrained 'clk' to bel 'X0/Y16/io1' 172s 172s Info: Packing constants.. 172s Info: Packing IOs.. 172s Info: Packing LUT-FFs.. 172s Info: 7 LCs used as LUT4 only 172s Info: 30 LCs used as LUT4 and DFF 172s Info: Packing non-LUT FFs.. 172s Info: 8 LCs used as DFF only 172s Info: Packing carries.. 172s Info: 0 LCs used as CARRY only 172s Info: Packing indirect carry+LUT pairs... 172s Info: 0 LUTs merged into carry LCs 172s Info: Packing RAMs.. 172s Info: Placing PLLs.. 172s Info: Packing special functions.. 172s Info: Packing PLLs.. 172s Info: Promoting globals.. 172s Info: promoting clk$SB_IO_IN (fanout 38) 172s Info: Constraining chains... 172s Info: 1 LCs used to legalise carry chains. 172s Info: Checksum: 0x74fa9ee4 172s 172s Info: Annotating ports with timing budgets for target frequency 12.00 MHz 172s Info: Checksum: 0x4df74e96 172s 172s Info: Device utilisation: 172s Info: ICESTORM_LC: 48/ 7680 0% 172s Info: ICESTORM_RAM: 0/ 32 0% 172s Info: SB_IO: 9/ 256 3% 172s Info: SB_GB: 1/ 8 12% 172s Info: ICESTORM_PLL: 0/ 2 0% 172s Info: SB_WARMBOOT: 0/ 1 0% 172s 172s Info: Placed 9 cells based on constraints. 172s Info: Creating initial analytic placement for 18 cells, random placement wirelen = 571. 172s Info: at initial placer iter 0, wirelen = 26 172s Info: at initial placer iter 1, wirelen = 21 172s Info: at initial placer iter 2, wirelen = 20 172s Info: at initial placer iter 3, wirelen = 21 172s Info: Running main analytical placer, max placement attempts per cell = 10000. 172s Info: at iteration #1, type ICESTORM_LC: wirelen solved = 20, spread = 50, legal = 50; time = 0.00s 172s Info: at iteration #1, type SB_GB: wirelen solved = 50, spread = 50, legal = 50; time = 0.00s 172s Info: at iteration #1, type ALL: wirelen solved = 20, spread = 45, legal = 49; time = 0.00s 172s Info: at iteration #2, type ICESTORM_LC: wirelen solved = 32, spread = 47, legal = 51; time = 0.00s 172s Info: at iteration #2, type SB_GB: wirelen solved = 51, spread = 51, legal = 51; time = 0.00s 172s Info: at iteration #2, type ALL: wirelen solved = 31, spread = 44, legal = 48; time = 0.00s 172s Info: at iteration #3, type ICESTORM_LC: wirelen solved = 29, spread = 58, legal = 62; time = 0.00s 172s Info: at iteration #3, type SB_GB: wirelen solved = 62, spread = 62, legal = 62; time = 0.00s 172s Info: at iteration #3, type ALL: wirelen solved = 27, spread = 60, legal = 62; time = 0.00s 172s Info: at iteration #4, type ICESTORM_LC: wirelen solved = 29, spread = 52, legal = 64; time = 0.00s 172s Info: at iteration #4, type SB_GB: wirelen solved = 64, spread = 64, legal = 64; time = 0.00s 172s Info: at iteration #4, type ALL: wirelen solved = 29, spread = 52, legal = 62; time = 0.00s 172s Info: at iteration #5, type ICESTORM_LC: wirelen solved = 30, spread = 53, legal = 60; time = 0.00s 172s Info: at iteration #5, type SB_GB: wirelen solved = 60, spread = 60, legal = 60; time = 0.00s 172s Info: at iteration #5, type ALL: wirelen solved = 30, spread = 53, legal = 57; time = 0.00s 172s Info: at iteration #6, type ICESTORM_LC: wirelen solved = 34, spread = 44, legal = 57; time = 0.00s 172s Info: at iteration #6, type SB_GB: wirelen solved = 57, spread = 57, legal = 57; time = 0.00s 172s Info: at iteration #6, type ALL: wirelen solved = 34, spread = 44, legal = 61; time = 0.00s 172s Info: at iteration #7, type ICESTORM_LC: wirelen solved = 34, spread = 44, legal = 59; time = 0.00s 172s Info: at iteration #7, type SB_GB: wirelen solved = 59, spread = 59, legal = 59; time = 0.00s 172s Info: at iteration #7, type ALL: wirelen solved = 34, spread = 44, legal = 57; time = 0.00s 172s Info: HeAP Placer Time: 0.02s 172s Info: of which solving equations: 0.01s 172s Info: of which spreading cells: 0.00s 172s Info: of which strict legalisation: 0.00s 172s 172s Info: Running simulated annealing placer for refinement. 172s Info: at iteration #1: temp = 0.000000, timing cost = 3, wirelen = 48 172s Info: at iteration #5: temp = 0.000000, timing cost = 4, wirelen = 33 172s Info: at iteration #10: temp = 0.000000, timing cost = 4, wirelen = 32 172s Info: at iteration #11: temp = 0.000000, timing cost = 4, wirelen = 32 172s Info: SA placement time 0.01s 172s 172s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 159.74 MHz (PASS at 12.00 MHz) 172s 172s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> : 2.72 ns 172s 172s Info: Slack histogram: 172s Info: legend: * represents 1 endpoint(s) 172s Info: + represents [1,1) endpoint(s) 172s Info: [ 77073, 77313) |** 172s Info: [ 77313, 77553) |** 172s Info: [ 77553, 77793) |** 172s Info: [ 77793, 78033) | 172s Info: [ 78033, 78273) |** 172s Info: [ 78273, 78513) |** 172s Info: [ 78513, 78753) |** 172s Info: [ 78753, 78993) |** 172s Info: [ 78993, 79233) | 172s Info: [ 79233, 79473) |** 172s Info: [ 79473, 79713) |* 172s Info: [ 79713, 79953) |** 172s Info: [ 79953, 80193) |*** 172s Info: [ 80193, 80433) | 172s Info: [ 80433, 80673) |** 172s Info: [ 80673, 80913) |*** 172s Info: [ 80913, 81153) |** 172s Info: [ 81153, 81393) |****** 172s Info: [ 81393, 81633) |* 172s Info: [ 81633, 81873) |*************************************** 172s Info: Checksum: 0xa7a876a4 172s 172s Info: Routing.. 172s Info: Setting up routing queue. 172s Info: Routing 126 arcs. 172s Info: | (re-)routed arcs | delta | remaining| time spent | 172s Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| 172s Info: 126 | 0 101 | 0 101 | 0| 0.01 0.01| 172s Info: Routing complete. 172s Info: Router1 time 0.01s 172s Info: Checksum: 0x3ab1ef41 172s 172s Info: Critical path report for clock 'clk$SB_IO_IN_$glb_clk' (posedge -> posedge): 172s Info: curr total 172s Info: 0.5 0.5 Source counter_SB_LUT4_I3_LC.O 172s Info: 0.6 1.1 Net counter[0] budget 78.411003 ns (2,29) -> (3,29) 172s Info: Sink $nextpnr_ICESTORM_LC_0.I1 172s Info: Defined in: 172s Info: example.v:20.14-20.25 172s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 172s Info: 0.3 1.4 Source $nextpnr_ICESTORM_LC_0.COUT 172s Info: 0.0 1.4 Net $nextpnr_ICESTORM_LC_0$O budget 0.000000 ns (3,29) -> (3,29) 172s Info: Sink counter_SB_LUT4_I2_26_LC.CIN 172s Info: 0.1 1.5 Source counter_SB_LUT4_I2_26_LC.COUT 172s Info: 0.0 1.5 Net counter_SB_CARRY_CI_CO[2] budget 0.000000 ns (3,29) -> (3,29) 172s Info: Sink counter_SB_LUT4_I2_15_LC.CIN 172s Info: Defined in: 172s Info: example.v:20.14-20.25 172s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 172s Info: 0.1 1.6 Source counter_SB_LUT4_I2_15_LC.COUT 172s Info: 0.0 1.6 Net counter_SB_CARRY_CI_CO[3] budget 0.000000 ns (3,29) -> (3,29) 172s Info: Sink counter_SB_LUT4_I2_14_LC.CIN 172s Info: Defined in: 172s Info: example.v:20.14-20.25 172s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 172s Info: 0.1 1.8 Source counter_SB_LUT4_I2_14_LC.COUT 172s Info: 0.0 1.8 Net counter_SB_CARRY_CI_CO[4] budget 0.000000 ns (3,29) -> (3,29) 172s Info: Sink counter_SB_LUT4_I2_13_LC.CIN 172s Info: Defined in: 172s Info: example.v:20.14-20.25 172s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 172s Info: 0.1 1.9 Source counter_SB_LUT4_I2_13_LC.COUT 172s Info: 0.0 1.9 Net counter_SB_CARRY_CI_CO[5] budget 0.000000 ns (3,29) -> (3,29) 172s Info: Sink counter_SB_LUT4_I2_12_LC.CIN 172s Info: Defined in: 172s Info: example.v:20.14-20.25 172s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 172s Info: 0.1 2.0 Source counter_SB_LUT4_I2_12_LC.COUT 172s Info: 0.0 2.0 Net counter_SB_CARRY_CI_CO[6] budget 0.000000 ns (3,29) -> (3,29) 172s Info: Sink counter_SB_LUT4_I2_11_LC.CIN 172s Info: Defined in: 172s Info: example.v:20.14-20.25 172s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 172s Info: 0.1 2.1 Source counter_SB_LUT4_I2_11_LC.COUT 172s Info: 0.0 2.1 Net counter_SB_CARRY_CI_CO[7] budget 0.000000 ns (3,29) -> (3,29) 172s Info: Sink counter_SB_LUT4_I2_10_LC.CIN 172s Info: Defined in: 172s Info: example.v:20.14-20.25 172s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 172s Info: 0.1 2.3 Source counter_SB_LUT4_I2_10_LC.COUT 172s Info: 0.2 2.5 Net counter_SB_CARRY_CI_CO[8] budget 0.190000 ns (3,29) -> (3,30) 172s Info: Sink counter_SB_LUT4_I2_9_LC.CIN 172s Info: Defined in: 172s Info: example.v:20.14-20.25 172s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 172s Info: 0.1 2.6 Source counter_SB_LUT4_I2_9_LC.COUT 172s Info: 0.0 2.6 Net counter_SB_CARRY_CI_CO[9] budget 0.000000 ns (3,30) -> (3,30) 172s Info: Sink counter_SB_LUT4_I2_8_LC.CIN 172s Info: Defined in: 172s Info: example.v:20.14-20.25 172s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 172s Info: 0.1 2.7 Source counter_SB_LUT4_I2_8_LC.COUT 172s Info: 0.0 2.7 Net counter_SB_CARRY_CI_CO[10] budget 0.000000 ns (3,30) -> (3,30) 172s Info: Sink counter_SB_LUT4_I2_7_LC.CIN 172s Info: Defined in: 172s Info: example.v:20.14-20.25 172s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 172s Info: 0.1 2.8 Source counter_SB_LUT4_I2_7_LC.COUT 172s Info: 0.0 2.8 Net counter_SB_CARRY_CI_CO[11] budget 0.000000 ns (3,30) -> (3,30) 172s Info: Sink counter_SB_LUT4_I2_6_LC.CIN 172s Info: Defined in: 172s Info: example.v:20.14-20.25 172s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 172s Info: 0.1 3.0 Source counter_SB_LUT4_I2_6_LC.COUT 172s Info: 0.0 3.0 Net counter_SB_CARRY_CI_CO[12] budget 0.000000 ns (3,30) -> (3,30) 172s Info: Sink counter_SB_LUT4_I2_5_LC.CIN 172s Info: Defined in: 172s Info: example.v:20.14-20.25 172s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 172s Info: 0.1 3.1 Source counter_SB_LUT4_I2_5_LC.COUT 172s Info: 0.0 3.1 Net counter_SB_CARRY_CI_CO[13] budget 0.000000 ns (3,30) -> (3,30) 172s Info: Sink counter_SB_LUT4_I2_4_LC.CIN 172s Info: Defined in: 172s Info: example.v:20.14-20.25 172s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 172s Info: 0.1 3.2 Source counter_SB_LUT4_I2_4_LC.COUT 172s Info: 0.0 3.2 Net counter_SB_CARRY_CI_CO[14] budget 0.000000 ns (3,30) -> (3,30) 172s Info: Sink counter_SB_LUT4_I2_3_LC.CIN 172s Info: Defined in: 172s Info: example.v:20.14-20.25 172s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 172s Info: 0.1 3.3 Source counter_SB_LUT4_I2_3_LC.COUT 172s Info: 0.0 3.3 Net counter_SB_CARRY_CI_CO[15] budget 0.000000 ns (3,30) -> (3,30) 172s Info: Sink counter_SB_LUT4_I2_2_LC.CIN 172s Info: Defined in: 172s Info: example.v:20.14-20.25 172s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 172s Info: 0.1 3.5 Source counter_SB_LUT4_I2_2_LC.COUT 172s Info: 0.2 3.7 Net counter_SB_CARRY_CI_CO[16] budget 0.190000 ns (3,30) -> (3,31) 172s Info: Sink counter_SB_LUT4_I2_1_LC.CIN 172s Info: Defined in: 172s Info: example.v:20.14-20.25 172s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 172s Info: 0.1 3.8 Source counter_SB_LUT4_I2_1_LC.COUT 172s Info: 0.0 3.8 Net counter_SB_CARRY_CI_CO[17] budget 0.000000 ns (3,31) -> (3,31) 172s Info: Sink counter_SB_LUT4_I2_LC.CIN 172s Info: Defined in: 172s Info: example.v:20.14-20.25 172s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 172s Info: 0.1 3.9 Source counter_SB_LUT4_I2_LC.COUT 172s Info: 0.0 3.9 Net counter_SB_CARRY_CI_CO[18] budget 0.000000 ns (3,31) -> (3,31) 172s Info: Sink counter_SB_LUT4_I2_28_LC.CIN 172s Info: Defined in: 172s Info: example.v:20.14-20.25 172s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 172s Info: 0.1 4.0 Source counter_SB_LUT4_I2_28_LC.COUT 172s Info: 0.0 4.0 Net counter_SB_CARRY_CI_CO[19] budget 0.000000 ns (3,31) -> (3,31) 172s Info: Sink counter_SB_LUT4_I2_27_LC.CIN 172s Info: Defined in: 172s Info: example.v:20.14-20.25 172s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 172s Info: 0.1 4.2 Source counter_SB_LUT4_I2_27_LC.COUT 172s Info: 0.0 4.2 Net counter_SB_CARRY_CI_CO[20] budget 0.000000 ns (3,31) -> (3,31) 172s Info: Sink counter_SB_LUT4_I2_25_LC.CIN 172s Info: Defined in: 172s Info: example.v:20.14-20.25 172s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 172s Info: 0.1 4.3 Source counter_SB_LUT4_I2_25_LC.COUT 172s Info: 0.0 4.3 Net counter_SB_CARRY_CI_CO[21] budget 0.000000 ns (3,31) -> (3,31) 172s Info: Sink counter_SB_LUT4_I2_24_LC.CIN 172s Info: Defined in: 172s Info: example.v:20.14-20.25 172s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 172s Info: 0.1 4.4 Source counter_SB_LUT4_I2_24_LC.COUT 172s Info: 0.0 4.4 Net counter_SB_CARRY_CI_CO[22] budget 0.000000 ns (3,31) -> (3,31) 172s Info: Sink counter_SB_LUT4_I2_23_LC.CIN 172s Info: Defined in: 172s Info: example.v:20.14-20.25 172s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 172s Info: 0.1 4.6 Source counter_SB_LUT4_I2_23_LC.COUT 172s Info: 0.0 4.6 Net counter_SB_CARRY_CI_CO[23] budget 0.000000 ns (3,31) -> (3,31) 172s Info: Sink counter_SB_LUT4_I2_22_LC.CIN 172s Info: Defined in: 172s Info: example.v:20.14-20.25 172s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 172s Info: 0.1 4.7 Source counter_SB_LUT4_I2_22_LC.COUT 172s Info: 0.2 4.9 Net counter_SB_CARRY_CI_CO[24] budget 0.190000 ns (3,31) -> (3,32) 172s Info: Sink counter_SB_LUT4_I2_21_LC.CIN 172s Info: Defined in: 172s Info: example.v:20.14-20.25 172s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 172s Info: 0.1 5.0 Source counter_SB_LUT4_I2_21_LC.COUT 172s Info: 0.0 5.0 Net counter_SB_CARRY_CI_CO[25] budget 0.000000 ns (3,32) -> (3,32) 172s Info: Sink counter_SB_LUT4_I2_20_LC.CIN 172s Info: Defined in: 172s Info: example.v:20.14-20.25 172s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 172s Info: 0.1 5.1 Source counter_SB_LUT4_I2_20_LC.COUT 172s Info: 0.0 5.1 Net counter_SB_CARRY_CI_CO[26] budget 0.000000 ns (3,32) -> (3,32) 172s Info: Sink counter_SB_LUT4_I2_19_LC.CIN 172s Info: Defined in: 172s Info: example.v:20.14-20.25 172s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 172s Info: 0.1 5.3 Source counter_SB_LUT4_I2_19_LC.COUT 172s Info: 0.0 5.3 Net counter_SB_CARRY_CI_CO[27] budget 0.000000 ns (3,32) -> (3,32) 172s Info: Sink counter_SB_LUT4_I2_18_LC.CIN 172s Info: Defined in: 172s Info: example.v:20.14-20.25 172s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 172s Info: 0.1 5.4 Source counter_SB_LUT4_I2_18_LC.COUT 172s Info: 0.0 5.4 Net counter_SB_CARRY_CI_CO[28] budget 0.000000 ns (3,32) -> (3,32) 172s Info: Sink counter_SB_LUT4_I2_17_LC.CIN 172s Info: Defined in: 172s Info: example.v:20.14-20.25 172s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 172s Info: 0.1 5.5 Source counter_SB_LUT4_I2_17_LC.COUT 172s Info: 0.3 5.8 Net counter_SB_CARRY_CI_CO[29] budget 0.260000 ns (3,32) -> (3,32) 172s Info: Sink counter_SB_LUT4_I2_16_LC.I3 172s Info: Defined in: 172s Info: example.v:20.14-20.25 172s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 172s Info: 0.3 6.1 Setup counter_SB_LUT4_I2_16_LC.I3 172s Info: 4.7 ns logic, 1.4 ns routing 172s 172s Info: Critical path report for cross-domain path 'posedge clk$SB_IO_IN_$glb_clk' -> '': 172s Info: curr total 172s Info: 0.5 0.5 Source outcnt_SB_DFF_Q_DFFLC.O 172s Info: 1.2 1.8 Net outcnt[6] budget 41.208000 ns (3,32) -> (6,32) 172s Info: Sink LED1_SB_LUT4_O_LC.I2 172s Info: Defined in: 172s Info: example.v:17.17-17.23 172s Info: 0.4 2.1 Source LED1_SB_LUT4_O_LC.O 172s Info: 0.6 2.7 Net LED1$SB_IO_OUT budget 41.207001 ns (6,32) -> (6,33) 172s Info: Sink LED1$sb_io.D_OUT_0 172s Info: Defined in: 172s Info: example.v:4.9-4.13 172s Info: 0.9 ns logic, 1.8 ns routing 172s 172s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 163.99 MHz (PASS at 12.00 MHz) 172s 172s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> : 2.72 ns 172s 172s Info: Slack histogram: 172s Info: legend: * represents 1 endpoint(s) 172s Info: + represents [1,1) endpoint(s) 172s Info: [ 77235, 77467) |** 172s Info: [ 77467, 77699) |** 172s Info: [ 77699, 77931) |** 172s Info: [ 77931, 78163) | 172s Info: [ 78163, 78395) |** 172s Info: [ 78395, 78627) |** 172s Info: [ 78627, 78859) |** 172s Info: [ 78859, 79091) |** 172s Info: [ 79091, 79323) | 172s Info: [ 79323, 79555) |** 172s Info: [ 79555, 79787) |** 172s Info: [ 79787, 80019) |* 172s Info: [ 80019, 80251) |*** 172s Info: [ 80251, 80483) | 172s Info: [ 80483, 80715) |** 172s Info: [ 80715, 80947) |** 172s Info: [ 80947, 81179) |*** 172s Info: [ 81179, 81411) |****** 172s Info: [ 81411, 81643) |* 172s Info: [ 81643, 81875) |*************************************** 172s 172s Info: Program finished normally. 172s icetime -d hx8k -mtr example.rpt example.asc 172s // Reading input .asc file.. 172s // Reading 8k chipdb file.. 174s // Creating timing netlist.. 174s // Timing estimate: 6.09 ns (164.22 MHz) 174s icepack example.asc example.bin 174s make: Leaving directory '/tmp/autopkgtest.DyuG3m/build.kB5/src/examples/hx8kboard' 174s make: Entering directory '/tmp/autopkgtest.DyuG3m/build.kB5/src/examples/iceblink' 174s yosys -p 'synth_ice40 -top top -json example.json' example.v 174s 174s /----------------------------------------------------------------------------\ 174s | | 174s | yosys -- Yosys Open SYnthesis Suite | 174s | | 174s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 174s | | 174s | Permission to use, copy, modify, and/or distribute this software for any | 174s | purpose with or without fee is hereby granted, provided that the above | 174s | copyright notice and this permission notice appear in all copies. | 174s | | 174s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 174s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 174s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 174s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 174s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 174s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 174s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 174s | | 174s \----------------------------------------------------------------------------/ 174s 174s Yosys 0.23 (git sha1 7ce5011c24b) 174s 174s 174s -- Parsing `example.v' using frontend ` -vlog2k' -- 174s 174s 1. Executing Verilog-2005 frontend: example.v 174s Parsing Verilog input from `example.v' to AST representation. 174s Storing AST representation for module `$abstract\top'. 174s Successfully finished Verilog frontend. 174s 174s -- Running command `synth_ice40 -top top -json example.json' -- 174s 174s 2. Executing SYNTH_ICE40 pass. 174s 174s 2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v 174s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation. 174s Generating RTLIL representation for module `\SB_IO'. 174s Generating RTLIL representation for module `\SB_GB_IO'. 174s Generating RTLIL representation for module `\SB_GB'. 174s Generating RTLIL representation for module `\SB_LUT4'. 174s Generating RTLIL representation for module `\SB_CARRY'. 174s Generating RTLIL representation for module `\SB_DFF'. 174s Generating RTLIL representation for module `\SB_DFFE'. 174s Generating RTLIL representation for module `\SB_DFFSR'. 174s Generating RTLIL representation for module `\SB_DFFR'. 174s Generating RTLIL representation for module `\SB_DFFSS'. 174s Generating RTLIL representation for module `\SB_DFFS'. 174s Generating RTLIL representation for module `\SB_DFFESR'. 174s Generating RTLIL representation for module `\SB_DFFER'. 174s Generating RTLIL representation for module `\SB_DFFESS'. 174s Generating RTLIL representation for module `\SB_DFFES'. 174s Generating RTLIL representation for module `\SB_DFFN'. 174s Generating RTLIL representation for module `\SB_DFFNE'. 174s Generating RTLIL representation for module `\SB_DFFNSR'. 174s Generating RTLIL representation for module `\SB_DFFNR'. 174s Generating RTLIL representation for module `\SB_DFFNSS'. 174s Generating RTLIL representation for module `\SB_DFFNS'. 174s Generating RTLIL representation for module `\SB_DFFNESR'. 174s Generating RTLIL representation for module `\SB_DFFNER'. 174s Generating RTLIL representation for module `\SB_DFFNESS'. 174s Generating RTLIL representation for module `\SB_DFFNES'. 174s Generating RTLIL representation for module `\SB_RAM40_4K'. 174s Generating RTLIL representation for module `\SB_RAM40_4KNR'. 174s Generating RTLIL representation for module `\SB_RAM40_4KNW'. 174s Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. 174s Generating RTLIL representation for module `\ICESTORM_LC'. 174s Generating RTLIL representation for module `\SB_PLL40_CORE'. 174s Generating RTLIL representation for module `\SB_PLL40_PAD'. 174s Generating RTLIL representation for module `\SB_PLL40_2_PAD'. 174s Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. 174s Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. 174s Generating RTLIL representation for module `\SB_WARMBOOT'. 174s Generating RTLIL representation for module `\SB_SPRAM256KA'. 174s Generating RTLIL representation for module `\SB_HFOSC'. 174s Generating RTLIL representation for module `\SB_LFOSC'. 174s Generating RTLIL representation for module `\SB_RGBA_DRV'. 174s Generating RTLIL representation for module `\SB_LED_DRV_CUR'. 174s Generating RTLIL representation for module `\SB_RGB_DRV'. 174s Generating RTLIL representation for module `\SB_I2C'. 174s Generating RTLIL representation for module `\SB_SPI'. 174s Generating RTLIL representation for module `\SB_LEDDA_IP'. 174s Generating RTLIL representation for module `\SB_FILTER_50NS'. 174s Generating RTLIL representation for module `\SB_IO_I3C'. 174s Generating RTLIL representation for module `\SB_IO_OD'. 174s Generating RTLIL representation for module `\SB_MAC16'. 174s Generating RTLIL representation for module `\ICESTORM_RAM'. 174s Successfully finished Verilog frontend. 174s 174s 2.2. Executing HIERARCHY pass (managing design hierarchy). 174s 174s 2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\top'. 174s Generating RTLIL representation for module `\top'. 174s 174s 2.3.1. Analyzing design hierarchy.. 174s Top module: \top 174s 174s 2.3.2. Analyzing design hierarchy.. 174s Top module: \top 174s Removing unused module `$abstract\top'. 174s Removed 1 unused modules. 174s 174s 2.4. Executing PROC pass (convert processes to netlists). 174s 174s 2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 174s Cleaned up 0 empty switches. 174s 174s 2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 174s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241 in module SB_DFFNES. 174s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234 in module SB_DFFNESS. 174s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230 in module SB_DFFNER. 174s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223 in module SB_DFFNESR. 174s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220 in module SB_DFFNS. 174s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217 in module SB_DFFNSS. 174s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214 in module SB_DFFNR. 174s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211 in module SB_DFFNSR. 174s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203 in module SB_DFFES. 174s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196 in module SB_DFFESS. 174s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192 in module SB_DFFER. 174s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185 in module SB_DFFESR. 174s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182 in module SB_DFFS. 174s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179 in module SB_DFFSS. 174s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176 in module SB_DFFR. 174s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173 in module SB_DFFSR. 174s Removed a total of 0 dead cases. 174s 174s 2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 174s Removed 8 redundant assignments. 174s Promoted 25 assignments to connections. 174s 174s 2.4.4. Executing PROC_INIT pass (extract init attributes). 174s Found init rule in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 174s Set init value: \Q = 1'0 174s Found init rule in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 174s Set init value: \Q = 1'0 174s Found init rule in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 174s Set init value: \Q = 1'0 174s Found init rule in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 174s Set init value: \Q = 1'0 174s Found init rule in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 174s Set init value: \Q = 1'0 174s Found init rule in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 174s Set init value: \Q = 1'0 174s Found init rule in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 174s Set init value: \Q = 1'0 174s Found init rule in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 174s Set init value: \Q = 1'0 174s Found init rule in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 174s Set init value: \Q = 1'0 174s Found init rule in `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 174s Set init value: \Q = 1'0 174s Found init rule in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 174s Set init value: \Q = 1'0 174s Found init rule in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 174s Set init value: \Q = 1'0 174s Found init rule in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 174s Set init value: \Q = 1'0 174s Found init rule in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 174s Set init value: \Q = 1'0 174s Found init rule in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 174s Set init value: \Q = 1'0 174s Found init rule in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 174s Set init value: \Q = 1'0 174s Found init rule in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 174s Set init value: \Q = 1'0 174s Found init rule in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 174s Set init value: \Q = 1'0 174s Found init rule in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 174s Set init value: \Q = 1'0 174s Found init rule in `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 174s Set init value: \Q = 1'0 174s Found init rule in `\top.$proc$example.v:15$384'. 174s Set init value: \counter = 26'00000000000000000000000000 174s 174s 2.4.5. Executing PROC_ARST pass (detect async resets in processes). 174s Found async reset \S in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 174s Found async reset \R in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 174s Found async reset \S in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 174s Found async reset \R in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 174s Found async reset \S in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 174s Found async reset \R in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 174s Found async reset \S in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 174s Found async reset \R in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 174s 174s 2.4.6. Executing PROC_ROM pass (convert switches to ROMs). 174s Converted 0 switches. 174s 174s 174s 2.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 174s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 174s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 174s 1/1: $0\Q[0:0] 174s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 174s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 174s 1/1: $0\Q[0:0] 174s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 174s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 174s 1/1: $0\Q[0:0] 174s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 174s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 174s 1/1: $0\Q[0:0] 174s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 174s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 174s 1/1: $0\Q[0:0] 174s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 174s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 174s 1/1: $0\Q[0:0] 174s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 174s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 174s 1/1: $0\Q[0:0] 174s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 174s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 174s 1/1: $0\Q[0:0] 174s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 174s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 174s 1/1: $0\Q[0:0] 174s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 174s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 174s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 174s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 174s 1/1: $0\Q[0:0] 174s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 174s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 174s 1/1: $0\Q[0:0] 174s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 174s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 174s 1/1: $0\Q[0:0] 174s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 174s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 174s 1/1: $0\Q[0:0] 174s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 174s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 174s 1/1: $0\Q[0:0] 174s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 174s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 174s 1/1: $0\Q[0:0] 174s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 174s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 174s 1/1: $0\Q[0:0] 174s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 174s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 174s 1/1: $0\Q[0:0] 174s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 174s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 174s 1/1: $0\Q[0:0] 174s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 174s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 174s Creating decoders for process `\top.$proc$example.v:15$384'. 174s Creating decoders for process `\top.$proc$example.v:18$381'. 174s 174s 2.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). 174s 174s 2.4.9. Executing PROC_DFF pass (convert process syncs to FFs). 174s Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 174s created $adff cell `$procdff$429' with negative edge clock and positive level reset. 174s Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 174s created $dff cell `$procdff$430' with negative edge clock. 174s Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 174s created $adff cell `$procdff$431' with negative edge clock and positive level reset. 174s Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 174s created $dff cell `$procdff$432' with negative edge clock. 174s Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 174s created $adff cell `$procdff$433' with negative edge clock and positive level reset. 174s Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 174s created $dff cell `$procdff$434' with negative edge clock. 174s Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 174s created $adff cell `$procdff$435' with negative edge clock and positive level reset. 174s Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 174s created $dff cell `$procdff$436' with negative edge clock. 174s Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 174s created $dff cell `$procdff$437' with negative edge clock. 174s Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 174s created $dff cell `$procdff$438' with negative edge clock. 174s Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 174s created $adff cell `$procdff$439' with positive edge clock and positive level reset. 174s Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 174s created $dff cell `$procdff$440' with positive edge clock. 174s Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 174s created $adff cell `$procdff$441' with positive edge clock and positive level reset. 174s Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 174s created $dff cell `$procdff$442' with positive edge clock. 174s Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 174s created $adff cell `$procdff$443' with positive edge clock and positive level reset. 174s Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 174s created $dff cell `$procdff$444' with positive edge clock. 174s Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 174s created $adff cell `$procdff$445' with positive edge clock and positive level reset. 174s Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 174s created $dff cell `$procdff$446' with positive edge clock. 174s Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 174s created $dff cell `$procdff$447' with positive edge clock. 174s Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 174s created $dff cell `$procdff$448' with positive edge clock. 174s Creating register for signal `\top.\counter' using process `\top.$proc$example.v:18$381'. 174s created $dff cell `$procdff$449' with positive edge clock. 174s Creating register for signal `\top.\outcnt' using process `\top.$proc$example.v:18$381'. 174s created $dff cell `$procdff$450' with positive edge clock. 174s 174s 2.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 174s 174s 2.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 174s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 174s Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 174s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 174s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 174s Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 174s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 174s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 174s Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 174s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 174s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 174s Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 174s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 174s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 174s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 174s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 174s Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 174s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 174s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 174s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 174s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 174s Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 174s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 174s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 174s Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 174s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 174s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 174s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 174s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 174s Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 174s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 174s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 174s Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 174s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 174s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 174s Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 174s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 174s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 174s Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 174s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 174s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 174s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 174s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 174s Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 174s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 174s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 174s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 174s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 174s Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 174s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 174s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 174s Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 174s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 174s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 174s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 174s Removing empty process `top.$proc$example.v:15$384'. 174s Removing empty process `top.$proc$example.v:18$381'. 174s Cleaned up 18 empty switches. 174s 174s 2.4.12. Executing OPT_EXPR pass (perform const folding). 174s Optimizing module top. 174s 174s 174s 2.5. Executing FLATTEN pass (flatten design). 174s 174s 2.6. Executing TRIBUF pass. 174s 174s 2.7. Executing DEMINOUT pass (demote inout ports to input or output). 174s 174s 2.8. Executing OPT_EXPR pass (perform const folding). 174s Optimizing module top. 174s 174s 2.9. Executing OPT_CLEAN pass (remove unused cells and wires). 174s Finding unused cells or wires in module \top.. 174s Removed 0 unused cells and 3 unused wires. 174s 174s 174s 2.10. Executing CHECK pass (checking for obvious problems). 174s Checking module top... 174s Found and reported 0 problems. 174s 174s 2.11. Executing OPT pass (performing simple optimizations). 174s 174s 2.11.1. Executing OPT_EXPR pass (perform const folding). 174s Optimizing module top. 174s 174s 2.11.2. Executing OPT_MERGE pass (detect identical cells). 174s Finding identical cells in module `\top'. 174s Removed a total of 0 cells. 174s 174s 2.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 174s Running muxtree optimizer on module \top.. 174s Creating internal representation of mux trees. 174s No muxes found in this module. 174s Removed 0 multiplexer ports. 174s 174s 2.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 174s Optimizing cells in module \top. 174s Performed a total of 0 changes. 174s 174s 2.11.5. Executing OPT_MERGE pass (detect identical cells). 174s Finding identical cells in module `\top'. 174s Removed a total of 0 cells. 174s 174s 2.11.6. Executing OPT_DFF pass (perform DFF optimizations). 174s 174s 2.11.7. Executing OPT_CLEAN pass (remove unused cells and wires). 174s Finding unused cells or wires in module \top.. 174s 174s 2.11.8. Executing OPT_EXPR pass (perform const folding). 174s Optimizing module top. 174s 174s 2.11.9. Finished OPT passes. (There is nothing left to do.) 174s 174s 2.12. Executing FSM pass (extract and optimize FSM). 174s 174s 2.12.1. Executing FSM_DETECT pass (finding FSMs in design). 174s 174s 2.12.2. Executing FSM_EXTRACT pass (extracting FSM from design). 174s 174s 2.12.3. Executing FSM_OPT pass (simple optimizations of FSMs). 174s 174s 2.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). 174s Finding unused cells or wires in module \top.. 174s 174s 2.12.5. Executing FSM_OPT pass (simple optimizations of FSMs). 174s 174s 2.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 174s 174s 2.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 174s 174s 2.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 174s 174s 2.13. Executing OPT pass (performing simple optimizations). 174s 174s 2.13.1. Executing OPT_EXPR pass (perform const folding). 174s Optimizing module top. 174s 174s 2.13.2. Executing OPT_MERGE pass (detect identical cells). 174s Finding identical cells in module `\top'. 174s Removed a total of 0 cells. 174s 174s 2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 174s Running muxtree optimizer on module \top.. 174s Creating internal representation of mux trees. 174s No muxes found in this module. 174s Removed 0 multiplexer ports. 174s 174s 2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 174s Optimizing cells in module \top. 174s Performed a total of 0 changes. 174s 174s 2.13.5. Executing OPT_MERGE pass (detect identical cells). 174s Finding identical cells in module `\top'. 174s Removed a total of 0 cells. 174s 174s 2.13.6. Executing OPT_DFF pass (perform DFF optimizations). 174s 174s 2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). 174s Finding unused cells or wires in module \top.. 174s 174s 2.13.8. Executing OPT_EXPR pass (perform const folding). 174s Optimizing module top. 174s 174s 2.13.9. Finished OPT passes. (There is nothing left to do.) 174s 174s 2.14. Executing WREDUCE pass (reducing word size of cells). 174s Removed top 31 bits (of 32) from port B of cell top.$add$example.v:19$382 ($add). 174s Removed top 6 bits (of 32) from port Y of cell top.$add$example.v:19$382 ($add). 174s 174s 2.15. Executing PEEPOPT pass (run peephole optimizers). 174s 174s 2.16. Executing OPT_CLEAN pass (remove unused cells and wires). 174s Finding unused cells or wires in module \top.. 174s Removed 0 unused cells and 1 unused wires. 174s 174s 174s 2.17. Executing SHARE pass (SAT-based resource sharing). 174s 174s 2.18. Executing TECHMAP pass (map to technology primitives). 174s 174s 2.18.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v 174s Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation. 174s Generating RTLIL representation for module `\_90_lut_cmp_'. 174s Successfully finished Verilog frontend. 174s 174s 2.18.2. Continuing TECHMAP pass. 174s No more expansions possible. 174s 174s 174s 2.19. Executing OPT_EXPR pass (perform const folding). 174s Optimizing module top. 174s 174s 2.20. Executing OPT_CLEAN pass (remove unused cells and wires). 174s Finding unused cells or wires in module \top.. 174s 174s 2.21. Executing ALUMACC pass (create $alu and $macc cells). 174s Extracting $alu and $macc cells in module top: 174s creating $macc model for $add$example.v:19$382 ($add). 174s creating $alu model for $macc $add$example.v:19$382. 174s creating $alu cell for $add$example.v:19$382: $auto$alumacc.cc:485:replace_alu$452 174s created 1 $alu and 0 $macc cells. 174s 174s 2.22. Executing OPT pass (performing simple optimizations). 174s 174s 2.22.1. Executing OPT_EXPR pass (perform const folding). 174s Optimizing module top. 174s 174s 2.22.2. Executing OPT_MERGE pass (detect identical cells). 174s Finding identical cells in module `\top'. 174s Removed a total of 0 cells. 174s 174s 2.22.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 174s Running muxtree optimizer on module \top.. 174s Creating internal representation of mux trees. 174s No muxes found in this module. 174s Removed 0 multiplexer ports. 174s 174s 2.22.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 174s Optimizing cells in module \top. 174s Performed a total of 0 changes. 174s 174s 2.22.5. Executing OPT_MERGE pass (detect identical cells). 174s Finding identical cells in module `\top'. 174s Removed a total of 0 cells. 174s 174s 2.22.6. Executing OPT_DFF pass (perform DFF optimizations). 174s 174s 2.22.7. Executing OPT_CLEAN pass (remove unused cells and wires). 174s Finding unused cells or wires in module \top.. 174s 174s 2.22.8. Executing OPT_EXPR pass (perform const folding). 174s Optimizing module top. 174s 174s 2.22.9. Finished OPT passes. (There is nothing left to do.) 174s 174s 2.23. Executing MEMORY pass. 174s 174s 2.23.1. Executing OPT_MEM pass (optimize memories). 174s Performed a total of 0 transformations. 174s 174s 2.23.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). 174s Performed a total of 0 transformations. 174s 174s 2.23.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 174s 174s 2.23.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 174s 174s 2.23.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 174s 174s 2.23.6. Executing OPT_CLEAN pass (remove unused cells and wires). 174s Finding unused cells or wires in module \top.. 174s 174s 2.23.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 174s 174s 2.23.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). 174s Performed a total of 0 transformations. 174s 174s 2.23.9. Executing OPT_CLEAN pass (remove unused cells and wires). 174s Finding unused cells or wires in module \top.. 174s 174s 2.23.10. Executing MEMORY_COLLECT pass (generating $mem cells). 174s 174s 2.24. Executing OPT_CLEAN pass (remove unused cells and wires). 174s Finding unused cells or wires in module \top.. 174s 174s 2.25. Executing MEMORY_LIBMAP pass (mapping memories to cells). 174s 174s 2.26. Executing TECHMAP pass (map to technology primitives). 174s 174s 2.26.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v 175s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation. 175s Generating RTLIL representation for module `\$__ICE40_RAM4K_'. 175s Successfully finished Verilog frontend. 175s 175s 2.26.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/spram_map.v 175s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/spram_map.v' to AST representation. 175s Generating RTLIL representation for module `\$__ICE40_SPRAM_'. 175s Successfully finished Verilog frontend. 175s 175s 2.26.3. Continuing TECHMAP pass. 175s No more expansions possible. 175s 175s 175s 2.27. Executing ICE40_BRAMINIT pass. 175s 175s 2.28. Executing OPT pass (performing simple optimizations). 175s 175s 2.28.1. Executing OPT_EXPR pass (perform const folding). 175s Optimizing module top. 175s 175s 2.28.2. Executing OPT_MERGE pass (detect identical cells). 175s Finding identical cells in module `\top'. 175s Removed a total of 0 cells. 175s 175s 2.28.3. Executing OPT_DFF pass (perform DFF optimizations). 175s 175s 2.28.4. Executing OPT_CLEAN pass (remove unused cells and wires). 175s Finding unused cells or wires in module \top.. 175s 175s 2.28.5. Finished fast OPT passes. 175s 175s 2.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 175s 175s 2.30. Executing OPT pass (performing simple optimizations). 175s 175s 2.30.1. Executing OPT_EXPR pass (perform const folding). 175s Optimizing module top. 175s 175s 2.30.2. Executing OPT_MERGE pass (detect identical cells). 175s Finding identical cells in module `\top'. 175s Removed a total of 0 cells. 175s 175s 2.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 175s Running muxtree optimizer on module \top.. 175s Creating internal representation of mux trees. 175s No muxes found in this module. 175s Removed 0 multiplexer ports. 175s 175s 2.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 175s Optimizing cells in module \top. 175s Performed a total of 0 changes. 175s 175s 2.30.5. Executing OPT_MERGE pass (detect identical cells). 175s Finding identical cells in module `\top'. 175s Removed a total of 0 cells. 175s 175s 2.30.6. Executing OPT_DFF pass (perform DFF optimizations). 175s 175s 2.30.7. Executing OPT_CLEAN pass (remove unused cells and wires). 175s Finding unused cells or wires in module \top.. 175s 175s 2.30.8. Executing OPT_EXPR pass (perform const folding). 175s Optimizing module top. 175s 175s 2.30.9. Finished OPT passes. (There is nothing left to do.) 175s 175s 2.31. Executing ICE40_WRAPCARRY pass (wrap carries). 175s 175s 2.32. Executing TECHMAP pass (map to technology primitives). 175s 175s 2.32.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v 175s Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation. 175s Generating RTLIL representation for module `\_90_simplemap_bool_ops'. 175s Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. 175s Generating RTLIL representation for module `\_90_simplemap_logic_ops'. 175s Generating RTLIL representation for module `\_90_simplemap_compare_ops'. 175s Generating RTLIL representation for module `\_90_simplemap_various'. 175s Generating RTLIL representation for module `\_90_simplemap_registers'. 175s Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. 175s Generating RTLIL representation for module `\_90_shift_shiftx'. 175s Generating RTLIL representation for module `\_90_fa'. 175s Generating RTLIL representation for module `\_90_lcu'. 175s Generating RTLIL representation for module `\_90_alu'. 175s Generating RTLIL representation for module `\_90_macc'. 175s Generating RTLIL representation for module `\_90_alumacc'. 175s Generating RTLIL representation for module `\$__div_mod_u'. 175s Generating RTLIL representation for module `\$__div_mod_trunc'. 175s Generating RTLIL representation for module `\_90_div'. 175s Generating RTLIL representation for module `\_90_mod'. 175s Generating RTLIL representation for module `\$__div_mod_floor'. 175s Generating RTLIL representation for module `\_90_divfloor'. 175s Generating RTLIL representation for module `\_90_modfloor'. 175s Generating RTLIL representation for module `\_90_pow'. 175s Generating RTLIL representation for module `\_90_pmux'. 175s Generating RTLIL representation for module `\_90_demux'. 175s Generating RTLIL representation for module `\_90_lut'. 175s Successfully finished Verilog frontend. 175s 175s 2.32.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v 175s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation. 175s Generating RTLIL representation for module `\_80_ice40_alu'. 175s Successfully finished Verilog frontend. 175s 175s 2.32.3. Continuing TECHMAP pass. 175s Using template $paramod$a8151eed7df109f18d5adf1169b40bb7b9e884a8\_80_ice40_alu for cells of type $alu. 175s Using extmapper simplemap for cells of type $dff. 175s Using extmapper simplemap for cells of type $xor. 175s Using extmapper simplemap for cells of type $mux. 175s Using extmapper simplemap for cells of type $not. 175s Using extmapper simplemap for cells of type $pos. 175s No more expansions possible. 175s 175s 175s 2.33. Executing OPT pass (performing simple optimizations). 175s 175s 2.33.1. Executing OPT_EXPR pass (perform const folding). 175s Optimizing module top. 175s 175s 175s 2.33.2. Executing OPT_MERGE pass (detect identical cells). 175s Finding identical cells in module `\top'. 175s 175s Removed a total of 1 cells. 175s 175s 2.33.3. Executing OPT_DFF pass (perform DFF optimizations). 175s 175s 2.33.4. Executing OPT_CLEAN pass (remove unused cells and wires). 175s Finding unused cells or wires in module \top.. 175s Removed 26 unused cells and 17 unused wires. 175s 175s 175s 2.33.5. Finished fast OPT passes. 175s 175s 2.34. Executing ICE40_OPT pass (performing simple optimizations). 175s 175s 2.34.1. Running ICE40 specific optimizations. 175s Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$452.slice[0].carry: CO=\counter [0] 175s 175s 2.34.2. Executing OPT_EXPR pass (perform const folding). 175s Optimizing module top. 175s 175s 2.34.3. Executing OPT_MERGE pass (detect identical cells). 175s Finding identical cells in module `\top'. 175s Removed a total of 0 cells. 175s 175s 2.34.4. Executing OPT_DFF pass (perform DFF optimizations). 175s 175s 2.34.5. Executing OPT_CLEAN pass (remove unused cells and wires). 175s Finding unused cells or wires in module \top.. 175s 175s 2.34.6. Rerunning OPT passes. (Removed registers in this run.) 175s 175s 2.34.7. Running ICE40 specific optimizations. 175s 175s 2.34.8. Executing OPT_EXPR pass (perform const folding). 175s Optimizing module top. 175s 175s 2.34.9. Executing OPT_MERGE pass (detect identical cells). 175s Finding identical cells in module `\top'. 175s Removed a total of 0 cells. 175s 175s 2.34.10. Executing OPT_DFF pass (perform DFF optimizations). 175s 175s 2.34.11. Executing OPT_CLEAN pass (remove unused cells and wires). 175s Finding unused cells or wires in module \top.. 175s 175s 2.34.12. Finished OPT passes. (There is nothing left to do.) 175s 175s 2.35. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 175s 175s 2.36. Executing TECHMAP pass (map to technology primitives). 175s 175s 2.36.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 175s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 175s Generating RTLIL representation for module `\$_DFF_N_'. 175s Generating RTLIL representation for module `\$_DFF_P_'. 175s Generating RTLIL representation for module `\$_DFFE_NP_'. 175s Generating RTLIL representation for module `\$_DFFE_PP_'. 175s Generating RTLIL representation for module `\$_DFF_NP0_'. 175s Generating RTLIL representation for module `\$_DFF_NP1_'. 175s Generating RTLIL representation for module `\$_DFF_PP0_'. 175s Generating RTLIL representation for module `\$_DFF_PP1_'. 175s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 175s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 175s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 175s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 175s Generating RTLIL representation for module `\$_SDFF_NP0_'. 175s Generating RTLIL representation for module `\$_SDFF_NP1_'. 175s Generating RTLIL representation for module `\$_SDFF_PP0_'. 175s Generating RTLIL representation for module `\$_SDFF_PP1_'. 175s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 175s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 175s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 175s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 175s Successfully finished Verilog frontend. 175s 175s 2.36.2. Continuing TECHMAP pass. 175s Using template \$_DFF_P_ for cells of type $_DFF_P_. 175s No more expansions possible. 175s 175s 175s 2.37. Executing OPT_EXPR pass (perform const folding). 175s Optimizing module top. 175s 175s 2.38. Executing SIMPLEMAP pass (map simple cells to gate primitives). 175s Mapping top.$auto$alumacc.cc:485:replace_alu$452.slice[0].carry ($lut). 175s 175s 2.39. Executing ICE40_OPT pass (performing simple optimizations). 175s 175s 2.39.1. Running ICE40 specific optimizations. 175s 175s 2.39.2. Executing OPT_EXPR pass (perform const folding). 175s Optimizing module top. 175s 175s 175s 2.39.3. Executing OPT_MERGE pass (detect identical cells). 175s Finding identical cells in module `\top'. 175s Removed a total of 0 cells. 175s 175s 2.39.4. Executing OPT_DFF pass (perform DFF optimizations). 175s 175s 2.39.5. Executing OPT_CLEAN pass (remove unused cells and wires). 175s Finding unused cells or wires in module \top.. 175s Removed 0 unused cells and 124 unused wires. 175s 175s 175s 2.39.6. Rerunning OPT passes. (Removed registers in this run.) 175s 175s 2.39.7. Running ICE40 specific optimizations. 175s 175s 2.39.8. Executing OPT_EXPR pass (perform const folding). 175s Optimizing module top. 175s 175s 2.39.9. Executing OPT_MERGE pass (detect identical cells). 175s Finding identical cells in module `\top'. 175s Removed a total of 0 cells. 175s 175s 2.39.10. Executing OPT_DFF pass (perform DFF optimizations). 175s 175s 2.39.11. Executing OPT_CLEAN pass (remove unused cells and wires). 175s Finding unused cells or wires in module \top.. 175s 175s 2.39.12. Finished OPT passes. (There is nothing left to do.) 175s 175s 2.40. Executing TECHMAP pass (map to technology primitives). 175s 175s 2.40.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v 175s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation. 175s Generating RTLIL representation for module `\$_DLATCH_N_'. 175s Generating RTLIL representation for module `\$_DLATCH_P_'. 175s Successfully finished Verilog frontend. 175s 175s 2.40.2. Continuing TECHMAP pass. 175s No more expansions possible. 175s 175s 175s 2.41. Executing ABC pass (technology mapping using ABC). 175s 175s 2.41.1. Extracting gate netlist of module `\top' to `/input.blif'.. 175s Extracted 1 gates and 2 wires to a netlist network with 1 inputs and 1 outputs. 175s 175s 2.41.1.1. Executing ABC. 175s Running ABC command: "berkeley-abc" -s -f /abc.script 2>&1 175s ABC: ABC command line: "source /abc.script". 175s ABC: 175s ABC: + read_blif /input.blif 175s ABC: + read_lut /lutdefs.txt 175s ABC: + strash 175s ABC: + &get -n 175s ABC: + &fraig -x 175s ABC: + &put 175s ABC: + scorr 175s ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). 175s ABC: + dc2 175s ABC: + dretime 175s ABC: + strash 175s ABC: + dch -f 175s ABC: + if 175s ABC: + mfs2 175s ABC: + lutpack -S 1 175s ABC: + dress /input.blif 175s ABC: Total number of equiv classes = 2. 175s ABC: Participating nodes from both networks = 2. 175s ABC: Participating nodes from the first network = 1. ( 50.00 % of nodes) 175s ABC: Participating nodes from the second network = 1. ( 50.00 % of nodes) 175s ABC: Node pairs (any polarity) = 1. ( 50.00 % of names can be moved) 175s ABC: Node pairs (same polarity) = 1. ( 50.00 % of names can be moved) 175s ABC: Total runtime = 0.00 sec 175s ABC: + write_blif /output.blif 175s 175s 2.41.1.2. Re-integrating ABC results. 175s ABC RESULTS: $lut cells: 1 175s ABC RESULTS: internal signals: 0 175s ABC RESULTS: input signals: 1 175s ABC RESULTS: output signals: 1 175s Removing temp directory. 175s 175s 2.42. Executing ICE40_WRAPCARRY pass (wrap carries). 175s 175s 2.43. Executing TECHMAP pass (map to technology primitives). 175s 175s 2.43.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 175s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 175s Generating RTLIL representation for module `\$_DFF_N_'. 175s Generating RTLIL representation for module `\$_DFF_P_'. 175s Generating RTLIL representation for module `\$_DFFE_NP_'. 175s Generating RTLIL representation for module `\$_DFFE_PP_'. 175s Generating RTLIL representation for module `\$_DFF_NP0_'. 175s Generating RTLIL representation for module `\$_DFF_NP1_'. 175s Generating RTLIL representation for module `\$_DFF_PP0_'. 175s Generating RTLIL representation for module `\$_DFF_PP1_'. 175s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 175s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 175s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 175s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 175s Generating RTLIL representation for module `\$_SDFF_NP0_'. 175s Generating RTLIL representation for module `\$_SDFF_NP1_'. 175s Generating RTLIL representation for module `\$_SDFF_PP0_'. 175s Generating RTLIL representation for module `\$_SDFF_PP1_'. 175s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 175s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 175s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 175s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 175s Successfully finished Verilog frontend. 175s 175s 2.43.2. Continuing TECHMAP pass. 175s No more expansions possible. 175s 175s Removed 1 unused cells and 3 unused wires. 175s 175s 2.44. Executing OPT_LUT pass (optimize LUTs). 175s Discovering LUTs. 175s Number of LUTs: 26 175s 1-LUT 1 175s 2-LUT 1 175s 3-LUT 24 175s with \SB_CARRY (#0) 24 175s with \SB_CARRY (#1) 24 175s 175s Eliminating LUTs. 175s Number of LUTs: 26 175s 1-LUT 1 175s 2-LUT 1 175s 3-LUT 24 175s with \SB_CARRY (#0) 24 175s with \SB_CARRY (#1) 24 175s 175s Combining LUTs. 175s Number of LUTs: 26 175s 1-LUT 1 175s 2-LUT 1 175s 3-LUT 24 175s with \SB_CARRY (#0) 24 175s with \SB_CARRY (#1) 24 175s 175s Eliminated 0 LUTs. 175s Combined 0 LUTs. 175s 175s 175s 2.45. Executing TECHMAP pass (map to technology primitives). 175s 175s 2.45.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v 175s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation. 175s Generating RTLIL representation for module `\$lut'. 175s Successfully finished Verilog frontend. 175s 175s 2.45.2. Continuing TECHMAP pass. 175s Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut. 175s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. 175s No more expansions possible. 175s 175s Removed 0 unused cells and 52 unused wires. 175s 175s 2.46. Executing AUTONAME pass. 175s Renamed 132 objects in module top (4 iterations). 175s 175s 175s 2.47. Executing HIERARCHY pass (managing design hierarchy). 175s 175s 2.47.1. Analyzing design hierarchy.. 175s Top module: \top 175s 175s 2.47.2. Analyzing design hierarchy.. 175s Top module: \top 175s Removed 0 unused modules. 175s 175s 2.48. Printing statistics. 175s 175s === top === 175s 175s Number of wires: 9 175s Number of wire bits: 87 175s Number of public wires: 9 175s Number of public wire bits: 87 175s Number of memories: 0 175s Number of memory bits: 0 175s Number of processes: 0 175s Number of cells: 80 175s SB_CARRY 24 175s SB_DFF 30 175s SB_LUT4 26 175s 175s 2.49. Executing CHECK pass (checking for obvious problems). 175s Checking module top... 175s Found and reported 0 problems. 175s 175s 2.50. Executing JSON backend. 175s 175s End of script. Logfile hash: 7602206948, CPU: user 0.98s system 0.01s, MEM: 22.00 MB peak 175s Yosys 0.23 (git sha1 7ce5011c24b) 175s Time spent: 68% 13x read_verilog (0 sec), 6% 1x synth_ice40 (0 sec), ... 175s nextpnr-ice40 --hx1k --package vq100 --asc example.asc --pcf iceblink.pcf --json example.json 175s Info: constrained 'LED2' to bel 'X13/Y7/io1' 175s Info: constrained 'LED3' to bel 'X13/Y6/io1' 175s Info: constrained 'LED4' to bel 'X13/Y4/io1' 175s Info: constrained 'LED5' to bel 'X13/Y3/io1' 175s Info: constrained 'clk' to bel 'X0/Y9/io0' 175s 175s Info: Packing constants.. 175s Info: Packing IOs.. 175s Info: Packing LUT-FFs.. 175s Info: 0 LCs used as LUT4 only 175s Info: 26 LCs used as LUT4 and DFF 175s Info: Packing non-LUT FFs.. 175s Info: 4 LCs used as DFF only 175s Info: Packing carries.. 175s Info: 0 LCs used as CARRY only 175s Info: Packing indirect carry+LUT pairs... 175s Info: 0 LUTs merged into carry LCs 175s Info: Packing RAMs.. 175s Info: Placing PLLs.. 175s Info: Packing special functions.. 175s Info: Packing PLLs.. 175s Info: Promoting globals.. 175s Info: promoting clk$SB_IO_IN (fanout 30) 175s Info: Constraining chains... 175s Info: 1 LCs used to legalise carry chains. 175s Info: Checksum: 0xabd25caf 175s 175s Info: Annotating ports with timing budgets for target frequency 12.00 MHz 175s Info: Checksum: 0x8546a4a1 175s 175s Info: Device utilisation: 175s Info: ICESTORM_LC: 33/ 1280 2% 175s Info: ICESTORM_RAM: 0/ 16 0% 175s Info: SB_IO: 5/ 112 4% 175s Info: SB_GB: 1/ 8 12% 175s Info: ICESTORM_PLL: 0/ 1 0% 175s Info: SB_WARMBOOT: 0/ 1 0% 175s 175s Info: Placed 5 cells based on constraints. 175s Info: Creating initial analytic placement for 7 cells, random placement wirelen = 81. 175s Info: at initial placer iter 0, wirelen = 7 175s Info: at initial placer iter 1, wirelen = 7 175s Info: at initial placer iter 2, wirelen = 7 175s Info: at initial placer iter 3, wirelen = 7 175s Info: Running main analytical placer, max placement attempts per cell = 10000. 175s Info: at iteration #1, type ICESTORM_LC: wirelen solved = 7, spread = 16, legal = 25; time = 0.00s 175s Info: at iteration #1, type SB_GB: wirelen solved = 25, spread = 25, legal = 25; time = 0.00s 175s Info: at iteration #1, type ALL: wirelen solved = 7, spread = 8, legal = 18; time = 0.00s 175s Info: at iteration #2, type ICESTORM_LC: wirelen solved = 11, spread = 23, legal = 24; time = 0.00s 175s Info: at iteration #2, type SB_GB: wirelen solved = 24, spread = 24, legal = 24; time = 0.00s 175s Info: at iteration #2, type ALL: wirelen solved = 11, spread = 23, legal = 24; time = 0.00s 175s Info: at iteration #3, type ICESTORM_LC: wirelen solved = 11, spread = 23, legal = 24; time = 0.00s 175s Info: at iteration #3, type SB_GB: wirelen solved = 24, spread = 24, legal = 24; time = 0.00s 175s Info: at iteration #3, type ALL: wirelen solved = 11, spread = 23, legal = 24; time = 0.00s 175s Info: at iteration #4, type ICESTORM_LC: wirelen solved = 13, spread = 23, legal = 25; time = 0.00s 175s Info: at iteration #4, type SB_GB: wirelen solved = 25, spread = 25, legal = 25; time = 0.00s 175s Info: at iteration #4, type ALL: wirelen solved = 13, spread = 23, legal = 25; time = 0.00s 175s Info: at iteration #5, type ICESTORM_LC: wirelen solved = 13, spread = 23, legal = 25; time = 0.00s 175s Info: at iteration #5, type SB_GB: wirelen solved = 25, spread = 25, legal = 25; time = 0.00s 175s Info: at iteration #5, type ALL: wirelen solved = 13, spread = 23, legal = 24; time = 0.00s 175s Info: at iteration #6, type ICESTORM_LC: wirelen solved = 13, spread = 21, legal = 23; time = 0.00s 175s Info: at iteration #6, type SB_GB: wirelen solved = 23, spread = 23, legal = 23; time = 0.00s 175s Info: at iteration #6, type ALL: wirelen solved = 13, spread = 21, legal = 23; time = 0.00s 175s Info: HeAP Placer Time: 0.01s 175s Info: of which solving equations: 0.01s 175s Info: of which spreading cells: 0.00s 175s Info: of which strict legalisation: 0.00s 175s 175s Info: Running simulated annealing placer for refinement. 175s Info: at iteration #1: temp = 0.000000, timing cost = 4, wirelen = 18 175s Info: at iteration #4: temp = 0.000000, timing cost = 4, wirelen = 16 175s Info: SA placement time 0.00s 175s 175s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 173.73 MHz (PASS at 12.00 MHz) 175s 175s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> : 1.13 ns 175s 175s Info: Slack histogram: 175s Info: legend: * represents 1 endpoint(s) 175s Info: + represents [1,1) endpoint(s) 175s Info: [ 77577, 77809) |** 175s Info: [ 77809, 78041) | 175s Info: [ 78041, 78273) |** 175s Info: [ 78273, 78505) |** 175s Info: [ 78505, 78737) |** 175s Info: [ 78737, 78969) |** 175s Info: [ 78969, 79201) | 175s Info: [ 79201, 79433) |* 175s Info: [ 79433, 79665) |** 175s Info: [ 79665, 79897) |** 175s Info: [ 79897, 80129) |** 175s Info: [ 80129, 80361) |* 175s Info: [ 80361, 80593) | 175s Info: [ 80593, 80825) |** 175s Info: [ 80825, 81057) |** 175s Info: [ 81057, 81289) |** 175s Info: [ 81289, 81521) | 175s Info: [ 81521, 81753) |**** 175s Info: [ 81753, 81985) |*************************** 175s Info: [ 81985, 82217) |**** 175s Info: Checksum: 0x26dcd3f5 175s 175s Info: Routing.. 175s Info: Setting up routing queue. 175s Info: Routing 93 arcs. 175s Info: | (re-)routed arcs | delta | remaining| time spent | 175s Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| 175s Info: 93 | 0 72 | 0 72 | 0| 0.00 0.00| 175s Info: Routing complete. 175s Info: Router1 time 0.00s 175s Info: Checksum: 0xc09595e8 175s 175s Info: Critical path report for clock 'clk$SB_IO_IN_$glb_clk' (posedge -> posedge): 175s Info: curr total 175s Info: 0.5 0.5 Source counter_SB_LUT4_I3_LC.O 175s Info: 0.6 1.1 Net counter[0] budget 78.740997 ns (11,2) -> (11,3) 175s Info: Sink $nextpnr_ICESTORM_LC_0.I1 175s Info: Defined in: 175s Info: example.v:19.14-19.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.3 1.4 Source $nextpnr_ICESTORM_LC_0.COUT 175s Info: 0.0 1.4 Net $nextpnr_ICESTORM_LC_0$O budget 0.000000 ns (11,3) -> (11,3) 175s Info: Sink counter_SB_LUT4_I2_15_LC.CIN 175s Info: 0.1 1.5 Source counter_SB_LUT4_I2_15_LC.COUT 175s Info: 0.0 1.5 Net counter_SB_CARRY_CI_CO[2] budget 0.000000 ns (11,3) -> (11,3) 175s Info: Sink counter_SB_LUT4_I2_8_LC.CIN 175s Info: Defined in: 175s Info: example.v:19.14-19.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.1 1.6 Source counter_SB_LUT4_I2_8_LC.COUT 175s Info: 0.0 1.6 Net counter_SB_CARRY_CI_CO[3] budget 0.000000 ns (11,3) -> (11,3) 175s Info: Sink counter_SB_LUT4_I2_7_LC.CIN 175s Info: Defined in: 175s Info: example.v:19.14-19.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.1 1.8 Source counter_SB_LUT4_I2_7_LC.COUT 175s Info: 0.0 1.8 Net counter_SB_CARRY_CI_CO[4] budget 0.000000 ns (11,3) -> (11,3) 175s Info: Sink counter_SB_LUT4_I2_6_LC.CIN 175s Info: Defined in: 175s Info: example.v:19.14-19.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.1 1.9 Source counter_SB_LUT4_I2_6_LC.COUT 175s Info: 0.0 1.9 Net counter_SB_CARRY_CI_CO[5] budget 0.000000 ns (11,3) -> (11,3) 175s Info: Sink counter_SB_LUT4_I2_5_LC.CIN 175s Info: Defined in: 175s Info: example.v:19.14-19.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.1 2.0 Source counter_SB_LUT4_I2_5_LC.COUT 175s Info: 0.0 2.0 Net counter_SB_CARRY_CI_CO[6] budget 0.000000 ns (11,3) -> (11,3) 175s Info: Sink counter_SB_LUT4_I2_4_LC.CIN 175s Info: Defined in: 175s Info: example.v:19.14-19.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.1 2.1 Source counter_SB_LUT4_I2_4_LC.COUT 175s Info: 0.0 2.1 Net counter_SB_CARRY_CI_CO[7] budget 0.000000 ns (11,3) -> (11,3) 175s Info: Sink counter_SB_LUT4_I2_3_LC.CIN 175s Info: Defined in: 175s Info: example.v:19.14-19.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.1 2.3 Source counter_SB_LUT4_I2_3_LC.COUT 175s Info: 0.2 2.5 Net counter_SB_CARRY_CI_CO[8] budget 0.190000 ns (11,3) -> (11,4) 175s Info: Sink counter_SB_LUT4_I2_2_LC.CIN 175s Info: Defined in: 175s Info: example.v:19.14-19.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.1 2.6 Source counter_SB_LUT4_I2_2_LC.COUT 175s Info: 0.0 2.6 Net counter_SB_CARRY_CI_CO[9] budget 0.000000 ns (11,4) -> (11,4) 175s Info: Sink counter_SB_LUT4_I2_1_LC.CIN 175s Info: Defined in: 175s Info: example.v:19.14-19.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.1 2.7 Source counter_SB_LUT4_I2_1_LC.COUT 175s Info: 0.0 2.7 Net counter_SB_CARRY_CI_CO[10] budget 0.000000 ns (11,4) -> (11,4) 175s Info: Sink counter_SB_LUT4_I2_LC.CIN 175s Info: Defined in: 175s Info: example.v:19.14-19.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.1 2.8 Source counter_SB_LUT4_I2_LC.COUT 175s Info: 0.0 2.8 Net counter_SB_CARRY_CI_CO[11] budget 0.000000 ns (11,4) -> (11,4) 175s Info: Sink counter_SB_LUT4_I2_24_LC.CIN 175s Info: Defined in: 175s Info: example.v:19.14-19.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.1 3.0 Source counter_SB_LUT4_I2_24_LC.COUT 175s Info: 0.0 3.0 Net counter_SB_CARRY_CI_CO[12] budget 0.000000 ns (11,4) -> (11,4) 175s Info: Sink counter_SB_LUT4_I2_23_LC.CIN 175s Info: Defined in: 175s Info: example.v:19.14-19.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.1 3.1 Source counter_SB_LUT4_I2_23_LC.COUT 175s Info: 0.0 3.1 Net counter_SB_CARRY_CI_CO[13] budget 0.000000 ns (11,4) -> (11,4) 175s Info: Sink counter_SB_LUT4_I2_22_LC.CIN 175s Info: Defined in: 175s Info: example.v:19.14-19.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.1 3.2 Source counter_SB_LUT4_I2_22_LC.COUT 175s Info: 0.0 3.2 Net counter_SB_CARRY_CI_CO[14] budget 0.000000 ns (11,4) -> (11,4) 175s Info: Sink counter_SB_LUT4_I2_21_LC.CIN 175s Info: Defined in: 175s icetime -d hx1k -mtr example.rpt example.asc 175s // Reading input .asc file.. 175s // Reading 1k chipdb file.. 175s Info: example.v:19.14-19.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.1 3.3 Source counter_SB_LUT4_I2_21_LC.COUT 175s Info: 0.0 3.3 Net counter_SB_CARRY_CI_CO[15] budget 0.000000 ns (11,4) -> (11,4) 175s Info: Sink counter_SB_LUT4_I2_20_LC.CIN 175s Info: Defined in: 175s Info: example.v:19.14-19.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.1 3.5 Source counter_SB_LUT4_I2_20_LC.COUT 175s Info: 0.2 3.7 Net counter_SB_CARRY_CI_CO[16] budget 0.190000 ns (11,4) -> (11,5) 175s Info: Sink counter_SB_LUT4_I2_19_LC.CIN 175s Info: Defined in: 175s Info: example.v:19.14-19.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.1 3.8 Source counter_SB_LUT4_I2_19_LC.COUT 175s Info: 0.0 3.8 Net counter_SB_CARRY_CI_CO[17] budget 0.000000 ns (11,5) -> (11,5) 175s Info: Sink counter_SB_LUT4_I2_18_LC.CIN 175s Info: Defined in: 175s Info: example.v:19.14-19.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.1 3.9 Source counter_SB_LUT4_I2_18_LC.COUT 175s Info: 0.0 3.9 Net counter_SB_CARRY_CI_CO[18] budget 0.000000 ns (11,5) -> (11,5) 175s Info: Sink counter_SB_LUT4_I2_17_LC.CIN 175s Info: Defined in: 175s Info: example.v:19.14-19.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.1 4.0 Source counter_SB_LUT4_I2_17_LC.COUT 175s Info: 0.0 4.0 Net counter_SB_CARRY_CI_CO[19] budget 0.000000 ns (11,5) -> (11,5) 175s Info: Sink counter_SB_LUT4_I2_16_LC.CIN 175s Info: Defined in: 175s Info: example.v:19.14-19.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.1 4.2 Source counter_SB_LUT4_I2_16_LC.COUT 175s Info: 0.0 4.2 Net counter_SB_CARRY_CI_CO[20] budget 0.000000 ns (11,5) -> (11,5) 175s Info: Sink counter_SB_LUT4_I2_14_LC.CIN 175s Info: Defined in: 175s Info: example.v:19.14-19.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.1 4.3 Source counter_SB_LUT4_I2_14_LC.COUT 175s Info: 0.0 4.3 Net counter_SB_CARRY_CI_CO[21] budget 0.000000 ns (11,5) -> (11,5) 175s Info: Sink counter_SB_LUT4_I2_13_LC.CIN 175s Info: Defined in: 175s Info: example.v:19.14-19.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.1 4.4 Source counter_SB_LUT4_I2_13_LC.COUT 175s Info: 0.0 4.4 Net counter_SB_CARRY_CI_CO[22] budget 0.000000 ns (11,5) -> (11,5) 175s Info: Sink counter_SB_LUT4_I2_12_LC.CIN 175s Info: Defined in: 175s Info: example.v:19.14-19.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.1 4.6 Source counter_SB_LUT4_I2_12_LC.COUT 175s Info: 0.0 4.6 Net counter_SB_CARRY_CI_CO[23] budget 0.000000 ns (11,5) -> (11,5) 175s Info: Sink counter_SB_LUT4_I2_11_LC.CIN 175s Info: Defined in: 175s Info: example.v:19.14-19.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.1 4.7 Source counter_SB_LUT4_I2_11_LC.COUT 175s Info: 0.2 4.9 Net counter_SB_CARRY_CI_CO[24] budget 0.190000 ns (11,5) -> (11,6) 175s Info: Sink counter_SB_LUT4_I2_10_LC.CIN 175s Info: Defined in: 175s Info: example.v:19.14-19.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.1 5.0 Source counter_SB_LUT4_I2_10_LC.COUT 175s Info: 0.3 5.3 Net counter_SB_CARRY_CI_CO[25] budget 0.260000 ns (11,6) -> (11,6) 175s Info: Sink counter_SB_LUT4_I2_9_LC.I3 175s Info: Defined in: 175s Info: example.v:19.14-19.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.3 5.6 Setup counter_SB_LUT4_I2_9_LC.I3 175s Info: 4.2 ns logic, 1.4 ns routing 175s 175s Info: Critical path report for cross-domain path 'posedge clk$SB_IO_IN_$glb_clk' -> '': 175s Info: curr total 175s Info: 0.5 0.5 Source LED2_SB_DFF_Q_DFFLC.O 175s Info: 0.6 1.1 Net LED2$SB_IO_OUT budget 82.792999 ns (12,6) -> (13,7) 175s Info: Sink LED2$sb_io.D_OUT_0 175s Info: Defined in: 175s Info: example.v:16.17-16.23 175s Info: 0.5 ns logic, 0.6 ns routing 175s 175s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 178.76 MHz (PASS at 12.00 MHz) 175s 175s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> : 1.13 ns 175s 175s Info: Slack histogram: 175s Info: legend: * represents 1 endpoint(s) 175s Info: + represents [1,1) endpoint(s) 175s Info: [ 77739, 77963) |** 175s Info: [ 77963, 78187) | 175s Info: [ 78187, 78411) |** 175s Info: [ 78411, 78635) |** 175s Info: [ 78635, 78859) |** 175s Info: [ 78859, 79083) |** 175s Info: [ 79083, 79307) | 175s Info: [ 79307, 79531) |** 175s Info: [ 79531, 79755) |* 175s Info: [ 79755, 79979) |** 175s Info: [ 79979, 80203) |*** 175s Info: [ 80203, 80427) | 175s Info: [ 80427, 80651) |* 175s Info: [ 80651, 80875) |** 175s Info: [ 80875, 81099) |* 175s Info: [ 81099, 81323) |** 175s Info: [ 81323, 81547) | 175s Info: [ 81547, 81771) |**** 175s Info: [ 81771, 81995) |*************************** 175s Info: [ 81995, 82219) |**** 175s 175s Info: Program finished normally. 175s // Creating timing netlist.. 175s // Timing estimate: 5.58 ns (179.07 MHz) 175s icepack example.asc example.bin 175s rm example.asc example.json 175s make: Leaving directory '/tmp/autopkgtest.DyuG3m/build.kB5/src/examples/iceblink' 175s make: Entering directory '/tmp/autopkgtest.DyuG3m/build.kB5/src/examples/icebreaker' 175s yosys -p 'synth_ice40 -top top -json example.json' example.v 175s 175s /----------------------------------------------------------------------------\ 175s | | 175s | yosys -- Yosys Open SYnthesis Suite | 175s | | 175s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 175s | | 175s | Permission to use, copy, modify, and/or distribute this software for any | 175s | purpose with or without fee is hereby granted, provided that the above | 175s | copyright notice and this permission notice appear in all copies. | 175s | | 175s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 175s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 175s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 175s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 175s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 175s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 175s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 175s | | 175s \----------------------------------------------------------------------------/ 175s 175s Yosys 0.23 (git sha1 7ce5011c24b) 175s 175s 175s -- Parsing `example.v' using frontend ` -vlog2k' -- 175s 175s 1. Executing Verilog-2005 frontend: example.v 175s Parsing Verilog input from `example.v' to AST representation. 175s Storing AST representation for module `$abstract\top'. 175s Successfully finished Verilog frontend. 175s 175s -- Running command `synth_ice40 -top top -json example.json' -- 175s 175s 2. Executing SYNTH_ICE40 pass. 175s 175s 2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v 175s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation. 175s Generating RTLIL representation for module `\SB_IO'. 175s Generating RTLIL representation for module `\SB_GB_IO'. 175s Generating RTLIL representation for module `\SB_GB'. 175s Generating RTLIL representation for module `\SB_LUT4'. 175s Generating RTLIL representation for module `\SB_CARRY'. 175s Generating RTLIL representation for module `\SB_DFF'. 175s Generating RTLIL representation for module `\SB_DFFE'. 175s Generating RTLIL representation for module `\SB_DFFSR'. 175s Generating RTLIL representation for module `\SB_DFFR'. 175s Generating RTLIL representation for module `\SB_DFFSS'. 175s Generating RTLIL representation for module `\SB_DFFS'. 175s Generating RTLIL representation for module `\SB_DFFESR'. 175s Generating RTLIL representation for module `\SB_DFFER'. 175s Generating RTLIL representation for module `\SB_DFFESS'. 175s Generating RTLIL representation for module `\SB_DFFES'. 175s Generating RTLIL representation for module `\SB_DFFN'. 175s Generating RTLIL representation for module `\SB_DFFNE'. 175s Generating RTLIL representation for module `\SB_DFFNSR'. 175s Generating RTLIL representation for module `\SB_DFFNR'. 175s Generating RTLIL representation for module `\SB_DFFNSS'. 175s Generating RTLIL representation for module `\SB_DFFNS'. 175s Generating RTLIL representation for module `\SB_DFFNESR'. 175s Generating RTLIL representation for module `\SB_DFFNER'. 175s Generating RTLIL representation for module `\SB_DFFNESS'. 175s Generating RTLIL representation for module `\SB_DFFNES'. 175s Generating RTLIL representation for module `\SB_RAM40_4K'. 175s Generating RTLIL representation for module `\SB_RAM40_4KNR'. 175s Generating RTLIL representation for module `\SB_RAM40_4KNW'. 175s Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. 175s Generating RTLIL representation for module `\ICESTORM_LC'. 175s Generating RTLIL representation for module `\SB_PLL40_CORE'. 175s Generating RTLIL representation for module `\SB_PLL40_PAD'. 175s Generating RTLIL representation for module `\SB_PLL40_2_PAD'. 175s Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. 175s Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. 175s Generating RTLIL representation for module `\SB_WARMBOOT'. 175s Generating RTLIL representation for module `\SB_SPRAM256KA'. 175s Generating RTLIL representation for module `\SB_HFOSC'. 175s Generating RTLIL representation for module `\SB_LFOSC'. 175s Generating RTLIL representation for module `\SB_RGBA_DRV'. 175s Generating RTLIL representation for module `\SB_LED_DRV_CUR'. 175s Generating RTLIL representation for module `\SB_RGB_DRV'. 175s Generating RTLIL representation for module `\SB_I2C'. 175s Generating RTLIL representation for module `\SB_SPI'. 175s Generating RTLIL representation for module `\SB_LEDDA_IP'. 175s Generating RTLIL representation for module `\SB_FILTER_50NS'. 175s Generating RTLIL representation for module `\SB_IO_I3C'. 175s Generating RTLIL representation for module `\SB_IO_OD'. 175s Generating RTLIL representation for module `\SB_MAC16'. 175s Generating RTLIL representation for module `\ICESTORM_RAM'. 175s Successfully finished Verilog frontend. 175s 175s 2.2. Executing HIERARCHY pass (managing design hierarchy). 175s 175s 2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\top'. 175s Generating RTLIL representation for module `\top'. 175s 175s 2.3.1. Analyzing design hierarchy.. 175s Top module: \top 175s 175s 2.3.2. Analyzing design hierarchy.. 175s Top module: \top 175s Removing unused module `$abstract\top'. 175s Removed 1 unused modules. 175s 175s 2.4. Executing PROC pass (convert processes to netlists). 175s 175s 2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 175s Cleaned up 0 empty switches. 175s 175s 2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 175s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241 in module SB_DFFNES. 175s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234 in module SB_DFFNESS. 175s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230 in module SB_DFFNER. 175s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223 in module SB_DFFNESR. 175s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220 in module SB_DFFNS. 175s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217 in module SB_DFFNSS. 175s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214 in module SB_DFFNR. 175s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211 in module SB_DFFNSR. 175s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203 in module SB_DFFES. 175s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196 in module SB_DFFESS. 175s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192 in module SB_DFFER. 175s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185 in module SB_DFFESR. 175s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182 in module SB_DFFS. 175s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179 in module SB_DFFSS. 175s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176 in module SB_DFFR. 175s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173 in module SB_DFFSR. 175s Removed a total of 0 dead cases. 175s 175s 2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 175s Removed 8 redundant assignments. 175s Promoted 25 assignments to connections. 175s 175s 2.4.4. Executing PROC_INIT pass (extract init attributes). 175s Found init rule in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 175s Set init value: \Q = 1'0 175s Found init rule in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 175s Set init value: \Q = 1'0 175s Found init rule in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 175s Set init value: \Q = 1'0 175s Found init rule in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 175s Set init value: \Q = 1'0 175s Found init rule in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 175s Set init value: \Q = 1'0 175s Found init rule in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 175s Set init value: \Q = 1'0 175s Found init rule in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 175s Set init value: \Q = 1'0 175s Found init rule in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 175s Set init value: \Q = 1'0 175s Found init rule in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 175s Set init value: \Q = 1'0 175s Found init rule in `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 175s Set init value: \Q = 1'0 175s Found init rule in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 175s Set init value: \Q = 1'0 175s Found init rule in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 175s Set init value: \Q = 1'0 175s Found init rule in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 175s Set init value: \Q = 1'0 175s Found init rule in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 175s Set init value: \Q = 1'0 175s Found init rule in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 175s Set init value: \Q = 1'0 175s Found init rule in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 175s Set init value: \Q = 1'0 175s Found init rule in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 175s Set init value: \Q = 1'0 175s Found init rule in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 175s Set init value: \Q = 1'0 175s Found init rule in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 175s Set init value: \Q = 1'0 175s Found init rule in `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 175s Set init value: \Q = 1'0 175s Found init rule in `\top.$proc$example.v:25$393'. 175s Set init value: \counter = 27'000000000000000000000000000 175s 175s 2.4.5. Executing PROC_ARST pass (detect async resets in processes). 175s Found async reset \S in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 175s Found async reset \R in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 175s Found async reset \S in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 175s Found async reset \R in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 175s Found async reset \S in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 175s Found async reset \R in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 175s Found async reset \S in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 175s Found async reset \R in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 175s 175s 2.4.6. Executing PROC_ROM pass (convert switches to ROMs). 175s Converted 0 switches. 175s 175s 175s 2.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 175s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 175s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 175s 1/1: $0\Q[0:0] 175s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 175s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 175s 1/1: $0\Q[0:0] 175s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 175s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 175s 1/1: $0\Q[0:0] 175s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 175s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 175s 1/1: $0\Q[0:0] 175s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 175s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 175s 1/1: $0\Q[0:0] 175s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 175s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 175s 1/1: $0\Q[0:0] 175s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 175s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 175s 1/1: $0\Q[0:0] 175s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 175s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 175s 1/1: $0\Q[0:0] 175s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 175s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 175s 1/1: $0\Q[0:0] 175s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 175s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 175s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 175s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 175s 1/1: $0\Q[0:0] 175s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 175s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 175s 1/1: $0\Q[0:0] 175s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 175s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 175s 1/1: $0\Q[0:0] 175s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 175s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 175s 1/1: $0\Q[0:0] 175s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 175s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 175s 1/1: $0\Q[0:0] 175s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 175s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 175s 1/1: $0\Q[0:0] 175s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 175s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 175s 1/1: $0\Q[0:0] 175s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 175s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 175s 1/1: $0\Q[0:0] 175s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 175s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 175s 1/1: $0\Q[0:0] 175s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 175s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 175s Creating decoders for process `\top.$proc$example.v:25$393'. 175s Creating decoders for process `\top.$proc$example.v:28$381'. 175s 175s 2.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). 175s 175s 2.4.9. Executing PROC_DFF pass (convert process syncs to FFs). 175s Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 175s created $adff cell `$procdff$438' with negative edge clock and positive level reset. 175s Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 175s created $dff cell `$procdff$439' with negative edge clock. 175s Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 175s created $adff cell `$procdff$440' with negative edge clock and positive level reset. 175s Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 175s created $dff cell `$procdff$441' with negative edge clock. 175s Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 175s created $adff cell `$procdff$442' with negative edge clock and positive level reset. 175s Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 175s created $dff cell `$procdff$443' with negative edge clock. 175s Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 175s created $adff cell `$procdff$444' with negative edge clock and positive level reset. 175s Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 175s created $dff cell `$procdff$445' with negative edge clock. 175s Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 175s created $dff cell `$procdff$446' with negative edge clock. 175s Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 175s created $dff cell `$procdff$447' with negative edge clock. 175s Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 175s created $adff cell `$procdff$448' with positive edge clock and positive level reset. 175s Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 175s created $dff cell `$procdff$449' with positive edge clock. 175s Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 175s created $adff cell `$procdff$450' with positive edge clock and positive level reset. 175s Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 175s created $dff cell `$procdff$451' with positive edge clock. 175s Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 175s created $adff cell `$procdff$452' with positive edge clock and positive level reset. 175s Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 175s created $dff cell `$procdff$453' with positive edge clock. 175s Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 175s created $adff cell `$procdff$454' with positive edge clock and positive level reset. 175s Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 175s created $dff cell `$procdff$455' with positive edge clock. 175s Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 175s created $dff cell `$procdff$456' with positive edge clock. 175s Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 175s created $dff cell `$procdff$457' with positive edge clock. 175s Creating register for signal `\top.\counter' using process `\top.$proc$example.v:28$381'. 175s created $dff cell `$procdff$458' with positive edge clock. 175s Creating register for signal `\top.\outcnt' using process `\top.$proc$example.v:28$381'. 175s created $dff cell `$procdff$459' with positive edge clock. 175s 175s 2.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 175s 175s 2.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 175s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 175s Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 175s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 175s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 175s Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 175s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 175s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 175s Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 175s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 175s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 175s Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 175s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 175s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 175s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 175s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 175s Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 175s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 175s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 175s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 175s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 175s Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 175s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 175s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 175s Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 175s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 175s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 175s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 175s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 175s Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 175s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 175s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 175s Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 175s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 175s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 175s Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 175s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 175s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 175s Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 175s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 175s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 175s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 175s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 175s Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 175s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 175s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 175s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 175s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 175s Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 175s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 175s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 175s Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 175s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 175s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 175s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 175s Removing empty process `top.$proc$example.v:25$393'. 175s Removing empty process `top.$proc$example.v:28$381'. 175s Cleaned up 18 empty switches. 175s 175s 2.4.12. Executing OPT_EXPR pass (perform const folding). 175s Optimizing module top. 175s 175s 175s 2.5. Executing FLATTEN pass (flatten design). 175s 175s 2.6. Executing TRIBUF pass. 175s 175s 2.7. Executing DEMINOUT pass (demote inout ports to input or output). 175s 175s 2.8. Executing OPT_EXPR pass (perform const folding). 175s Optimizing module top. 175s 175s 2.9. Executing OPT_CLEAN pass (remove unused cells and wires). 175s Finding unused cells or wires in module \top.. 175s Removed 0 unused cells and 6 unused wires. 175s 175s 175s 2.10. Executing CHECK pass (checking for obvious problems). 175s Checking module top... 175s Found and reported 0 problems. 175s 175s 2.11. Executing OPT pass (performing simple optimizations). 175s 175s 2.11.1. Executing OPT_EXPR pass (perform const folding). 175s Optimizing module top. 175s 175s 2.11.2. Executing OPT_MERGE pass (detect identical cells). 175s Finding identical cells in module `\top'. 175s Removed a total of 0 cells. 175s 175s 2.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 175s Running muxtree optimizer on module \top.. 175s Creating internal representation of mux trees. 175s No muxes found in this module. 175s Removed 0 multiplexer ports. 175s 175s 2.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 175s Optimizing cells in module \top. 175s Performed a total of 0 changes. 175s 175s 2.11.5. Executing OPT_MERGE pass (detect identical cells). 175s Finding identical cells in module `\top'. 175s Removed a total of 0 cells. 175s 175s 2.11.6. Executing OPT_DFF pass (perform DFF optimizations). 175s 175s 2.11.7. Executing OPT_CLEAN pass (remove unused cells and wires). 175s Finding unused cells or wires in module \top.. 175s 175s 2.11.8. Executing OPT_EXPR pass (perform const folding). 175s Optimizing module top. 175s 175s 2.11.9. Finished OPT passes. (There is nothing left to do.) 175s 175s 2.12. Executing FSM pass (extract and optimize FSM). 175s 175s 2.12.1. Executing FSM_DETECT pass (finding FSMs in design). 175s 175s 2.12.2. Executing FSM_EXTRACT pass (extracting FSM from design). 175s 175s 2.12.3. Executing FSM_OPT pass (simple optimizations of FSMs). 175s 175s 2.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). 175s Finding unused cells or wires in module \top.. 175s 175s 2.12.5. Executing FSM_OPT pass (simple optimizations of FSMs). 175s 175s 2.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 175s 175s 2.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 175s 175s 2.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 175s 175s 2.13. Executing OPT pass (performing simple optimizations). 175s 175s 2.13.1. Executing OPT_EXPR pass (perform const folding). 175s Optimizing module top. 175s 175s 2.13.2. Executing OPT_MERGE pass (detect identical cells). 175s Finding identical cells in module `\top'. 175s Removed a total of 0 cells. 175s 175s 2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 175s Running muxtree optimizer on module \top.. 175s Creating internal representation of mux trees. 175s No muxes found in this module. 175s Removed 0 multiplexer ports. 175s 175s 2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 175s Optimizing cells in module \top. 175s Performed a total of 0 changes. 175s 175s 2.13.5. Executing OPT_MERGE pass (detect identical cells). 175s Finding identical cells in module `\top'. 175s Removed a total of 0 cells. 175s 175s 2.13.6. Executing OPT_DFF pass (perform DFF optimizations). 175s 175s 2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). 175s Finding unused cells or wires in module \top.. 175s 175s 2.13.8. Executing OPT_EXPR pass (perform const folding). 175s Optimizing module top. 175s 175s 2.13.9. Finished OPT passes. (There is nothing left to do.) 175s 175s 2.14. Executing WREDUCE pass (reducing word size of cells). 175s Removed top 31 bits (of 32) from port B of cell top.$add$example.v:29$382 ($add). 175s Removed top 5 bits (of 32) from port Y of cell top.$add$example.v:29$382 ($add). 175s Removed top 1 bits (of 5) from port B of cell top.$xor$example.v:33$385 ($xor). 175s Removed top 1 bits (of 2) from port A of cell top.$add$example.v:35$387 ($add). 175s Removed top 28 bits (of 32) from port B of cell top.$and$example.v:38$391 ($and). 175s Removed top 27 bits (of 32) from port Y of cell top.$and$example.v:38$391 ($and). 175s Removed top 30 bits (of 32) from port A of cell top.$shl$example.v:38$392 ($shl). 175s Removed top 27 bits (of 32) from port B of cell top.$shl$example.v:38$392 ($shl). 175s Removed top 16 bits (of 32) from port Y of cell top.$shl$example.v:38$392 ($shl). 175s Removed top 27 bits (of 32) from wire top.$and$example.v:38$391_Y. 175s Removed top 1 bits (of 2) from wire top.$logic_not$example.v:35$386_Y. 175s Removed top 16 bits (of 32) from wire top.$shl$example.v:38$392_Y. 175s 175s 2.15. Executing PEEPOPT pass (run peephole optimizers). 175s 175s 2.16. Executing OPT_CLEAN pass (remove unused cells and wires). 175s Finding unused cells or wires in module \top.. 175s Removed 0 unused cells and 5 unused wires. 175s 175s 175s 2.17. Executing SHARE pass (SAT-based resource sharing). 175s 175s 2.18. Executing TECHMAP pass (map to technology primitives). 175s 175s 2.18.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v 175s Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation. 175s Generating RTLIL representation for module `\_90_lut_cmp_'. 175s Successfully finished Verilog frontend. 175s 175s 2.18.2. Continuing TECHMAP pass. 175s No more expansions possible. 175s 175s 175s 2.19. Executing OPT_EXPR pass (perform const folding). 175s Optimizing module top. 175s 175s 2.20. Executing OPT_CLEAN pass (remove unused cells and wires). 175s Finding unused cells or wires in module \top.. 175s 175s 2.21. Executing ALUMACC pass (create $alu and $macc cells). 175s Extracting $alu and $macc cells in module top: 175s creating $macc model for $add$example.v:29$382 ($add). 175s creating $macc model for $add$example.v:35$387 ($add). 175s creating $macc model for $add$example.v:35$388 ($add). 175s creating $macc model for $add$example.v:35$389 ($add). 175s merging $macc model for $add$example.v:35$388 into $add$example.v:35$389. 175s merging $macc model for $add$example.v:35$387 into $add$example.v:35$389. 175s creating $alu model for $macc $add$example.v:29$382. 175s creating $macc cell for $add$example.v:35$389: $auto$alumacc.cc:365:replace_macc$464 175s creating $alu cell for $add$example.v:29$382: $auto$alumacc.cc:485:replace_alu$465 175s created 1 $alu and 1 $macc cells. 175s 175s 2.22. Executing OPT pass (performing simple optimizations). 175s 175s 2.22.1. Executing OPT_EXPR pass (perform const folding). 175s Optimizing module top. 175s 175s 2.22.2. Executing OPT_MERGE pass (detect identical cells). 175s Finding identical cells in module `\top'. 175s Removed a total of 0 cells. 175s 175s 2.22.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 175s Running muxtree optimizer on module \top.. 175s Creating internal representation of mux trees. 175s No muxes found in this module. 175s Removed 0 multiplexer ports. 175s 175s 2.22.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 175s Optimizing cells in module \top. 175s Performed a total of 0 changes. 175s 175s 2.22.5. Executing OPT_MERGE pass (detect identical cells). 175s Finding identical cells in module `\top'. 175s Removed a total of 0 cells. 175s 175s 2.22.6. Executing OPT_DFF pass (perform DFF optimizations). 175s 175s 2.22.7. Executing OPT_CLEAN pass (remove unused cells and wires). 175s Finding unused cells or wires in module \top.. 175s Removed 2 unused cells and 2 unused wires. 175s 175s 175s 2.22.8. Executing OPT_EXPR pass (perform const folding). 175s Optimizing module top. 175s 175s 2.22.9. Rerunning OPT passes. (Maybe there is more to do..) 175s 175s 2.22.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 175s Running muxtree optimizer on module \top.. 175s Creating internal representation of mux trees. 175s No muxes found in this module. 175s Removed 0 multiplexer ports. 175s 175s 2.22.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 175s Optimizing cells in module \top. 175s Performed a total of 0 changes. 175s 175s 2.22.12. Executing OPT_MERGE pass (detect identical cells). 175s Finding identical cells in module `\top'. 175s Removed a total of 0 cells. 175s 175s 2.22.13. Executing OPT_DFF pass (perform DFF optimizations). 175s 175s 2.22.14. Executing OPT_CLEAN pass (remove unused cells and wires). 175s Finding unused cells or wires in module \top.. 175s 175s 2.22.15. Executing OPT_EXPR pass (perform const folding). 175s Optimizing module top. 175s 175s 2.22.16. Finished OPT passes. (There is nothing left to do.) 175s 175s 2.23. Executing MEMORY pass. 175s 175s 2.23.1. Executing OPT_MEM pass (optimize memories). 175s Performed a total of 0 transformations. 175s 175s 2.23.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). 175s Performed a total of 0 transformations. 175s 175s 2.23.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 175s 175s 2.23.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 175s 175s 2.23.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 175s 175s 2.23.6. Executing OPT_CLEAN pass (remove unused cells and wires). 175s Finding unused cells or wires in module \top.. 175s 175s 2.23.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 175s 175s 2.23.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). 175s Performed a total of 0 transformations. 175s 175s 2.23.9. Executing OPT_CLEAN pass (remove unused cells and wires). 175s Finding unused cells or wires in module \top.. 175s 175s 2.23.10. Executing MEMORY_COLLECT pass (generating $mem cells). 175s 175s 2.24. Executing OPT_CLEAN pass (remove unused cells and wires). 175s Finding unused cells or wires in module \top.. 175s 175s 2.25. Executing MEMORY_LIBMAP pass (mapping memories to cells). 175s 175s 2.26. Executing TECHMAP pass (map to technology primitives). 175s 175s 2.26.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v 176s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation. 176s Generating RTLIL representation for module `\$__ICE40_RAM4K_'. 176s Successfully finished Verilog frontend. 176s 176s 2.26.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/spram_map.v 176s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/spram_map.v' to AST representation. 176s Generating RTLIL representation for module `\$__ICE40_SPRAM_'. 176s Successfully finished Verilog frontend. 176s 176s 2.26.3. Continuing TECHMAP pass. 176s No more expansions possible. 176s 176s 176s 2.27. Executing ICE40_BRAMINIT pass. 176s 176s 2.28. Executing OPT pass (performing simple optimizations). 176s 176s 2.28.1. Executing OPT_EXPR pass (perform const folding). 176s Optimizing module top. 176s 176s 176s 2.28.2. Executing OPT_MERGE pass (detect identical cells). 176s Finding identical cells in module `\top'. 176s Removed a total of 0 cells. 176s 176s 2.28.3. Executing OPT_DFF pass (perform DFF optimizations). 176s 176s 2.28.4. Executing OPT_CLEAN pass (remove unused cells and wires). 176s Finding unused cells or wires in module \top.. 176s Removed 0 unused cells and 5 unused wires. 176s 176s 176s 2.28.5. Finished fast OPT passes. 176s 176s 2.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 176s 176s 2.30. Executing OPT pass (performing simple optimizations). 176s 176s 2.30.1. Executing OPT_EXPR pass (perform const folding). 176s Optimizing module top. 176s 176s 2.30.2. Executing OPT_MERGE pass (detect identical cells). 176s Finding identical cells in module `\top'. 176s Removed a total of 0 cells. 176s 176s 2.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 176s Running muxtree optimizer on module \top.. 176s Creating internal representation of mux trees. 176s No muxes found in this module. 176s Removed 0 multiplexer ports. 176s 176s 2.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 176s Optimizing cells in module \top. 176s Performed a total of 0 changes. 176s 176s 2.30.5. Executing OPT_MERGE pass (detect identical cells). 176s Finding identical cells in module `\top'. 176s Removed a total of 0 cells. 176s 176s 2.30.6. Executing OPT_DFF pass (perform DFF optimizations). 176s 176s 2.30.7. Executing OPT_CLEAN pass (remove unused cells and wires). 176s Finding unused cells or wires in module \top.. 176s 176s 2.30.8. Executing OPT_EXPR pass (perform const folding). 176s Optimizing module top. 176s 176s 2.30.9. Finished OPT passes. (There is nothing left to do.) 176s 176s 2.31. Executing ICE40_WRAPCARRY pass (wrap carries). 176s 176s 2.32. Executing TECHMAP pass (map to technology primitives). 176s 176s 2.32.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v 176s Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation. 176s Generating RTLIL representation for module `\_90_simplemap_bool_ops'. 176s Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. 176s Generating RTLIL representation for module `\_90_simplemap_logic_ops'. 176s Generating RTLIL representation for module `\_90_simplemap_compare_ops'. 176s Generating RTLIL representation for module `\_90_simplemap_various'. 176s Generating RTLIL representation for module `\_90_simplemap_registers'. 176s Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. 176s Generating RTLIL representation for module `\_90_shift_shiftx'. 176s Generating RTLIL representation for module `\_90_fa'. 176s Generating RTLIL representation for module `\_90_lcu'. 176s Generating RTLIL representation for module `\_90_alu'. 176s Generating RTLIL representation for module `\_90_macc'. 176s Generating RTLIL representation for module `\_90_alumacc'. 176s Generating RTLIL representation for module `\$__div_mod_u'. 176s Generating RTLIL representation for module `\$__div_mod_trunc'. 176s Generating RTLIL representation for module `\_90_div'. 176s Generating RTLIL representation for module `\_90_mod'. 176s Generating RTLIL representation for module `\$__div_mod_floor'. 176s Generating RTLIL representation for module `\_90_divfloor'. 176s Generating RTLIL representation for module `\_90_modfloor'. 176s Generating RTLIL representation for module `\_90_pow'. 176s Generating RTLIL representation for module `\_90_pmux'. 176s Generating RTLIL representation for module `\_90_demux'. 176s Generating RTLIL representation for module `\_90_lut'. 176s Successfully finished Verilog frontend. 176s 176s 2.32.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v 176s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation. 176s Generating RTLIL representation for module `\_80_ice40_alu'. 176s Successfully finished Verilog frontend. 176s 176s 2.32.3. Continuing TECHMAP pass. 176s Using extmapper simplemap for cells of type $logic_not. 176s Using extmapper simplemap for cells of type $xor. 176s Using template $paramod$956e79e8f8c5e64be7438155ae50a966e615cb04\_80_ice40_alu for cells of type $alu. 176s Using extmapper simplemap for cells of type $not. 176s Using template $paramod$constmap:9b90168b0f8ca06b2b949f1a9c9bc3e813ea8531$paramod$288516fc4f16924f26258e65716d87e1f82fa03e\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. 176s Using extmapper maccmap for cells of type $macc. 176s add bits { \BTN1 \BTN2 \BTN3 $auto$wreduce.cc:455:run$461 [0] } (4 bits) 176s packed 1 (1) bits / 1 words into adder tree 176s Using extmapper simplemap for cells of type $dff. 176s Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000001 for cells of type $fa. 176s Using template $paramod$7e708ae28ab761f11d0fb59d3ffc72f6a4baf5d9\_90_alu for cells of type $alu. 176s Using extmapper simplemap for cells of type $pos. 176s Using extmapper simplemap for cells of type $or. 176s Using extmapper simplemap for cells of type $and. 176s Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu. 176s No more expansions possible. 176s 176s 176s 2.33. Executing OPT pass (performing simple optimizations). 176s 176s 2.33.1. Executing OPT_EXPR pass (perform const folding). 176s Optimizing module top. 176s 176s 176s 2.33.2. Executing OPT_MERGE pass (detect identical cells). 176s Finding identical cells in module `\top'. 176s 176s Removed a total of 1 cells. 176s 176s 2.33.3. Executing OPT_DFF pass (perform DFF optimizations). 176s 176s 2.33.4. Executing OPT_CLEAN pass (remove unused cells and wires). 176s Finding unused cells or wires in module \top.. 176s Removed 30 unused cells and 60 unused wires. 176s 176s 176s 2.33.5. Finished fast OPT passes. 176s 176s 2.34. Executing ICE40_OPT pass (performing simple optimizations). 176s 176s 2.34.1. Running ICE40 specific optimizations. 176s Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$465.slice[0].carry: CO=\counter [0] 176s 176s 2.34.2. Executing OPT_EXPR pass (perform const folding). 176s Optimizing module top. 176s 176s 2.34.3. Executing OPT_MERGE pass (detect identical cells). 176s Finding identical cells in module `\top'. 176s Removed a total of 0 cells. 176s 176s 2.34.4. Executing OPT_DFF pass (perform DFF optimizations). 176s 176s 2.34.5. Executing OPT_CLEAN pass (remove unused cells and wires). 176s Finding unused cells or wires in module \top.. 176s 176s 2.34.6. Rerunning OPT passes. (Removed registers in this run.) 176s 176s 2.34.7. Running ICE40 specific optimizations. 176s 176s 2.34.8. Executing OPT_EXPR pass (perform const folding). 176s Optimizing module top. 176s 176s 2.34.9. Executing OPT_MERGE pass (detect identical cells). 176s Finding identical cells in module `\top'. 176s Removed a total of 0 cells. 176s 176s 2.34.10. Executing OPT_DFF pass (perform DFF optimizations). 176s 176s 2.34.11. Executing OPT_CLEAN pass (remove unused cells and wires). 176s Finding unused cells or wires in module \top.. 176s 176s 2.34.12. Finished OPT passes. (There is nothing left to do.) 176s 176s 2.35. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 176s 176s 2.36. Executing TECHMAP pass (map to technology primitives). 176s 176s 2.36.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 176s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 176s Generating RTLIL representation for module `\$_DFF_N_'. 176s Generating RTLIL representation for module `\$_DFF_P_'. 176s Generating RTLIL representation for module `\$_DFFE_NP_'. 176s Generating RTLIL representation for module `\$_DFFE_PP_'. 176s Generating RTLIL representation for module `\$_DFF_NP0_'. 176s Generating RTLIL representation for module `\$_DFF_NP1_'. 176s Generating RTLIL representation for module `\$_DFF_PP0_'. 176s Generating RTLIL representation for module `\$_DFF_PP1_'. 176s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 176s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 176s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 176s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 176s Generating RTLIL representation for module `\$_SDFF_NP0_'. 176s Generating RTLIL representation for module `\$_SDFF_NP1_'. 176s Generating RTLIL representation for module `\$_SDFF_PP0_'. 176s Generating RTLIL representation for module `\$_SDFF_PP1_'. 176s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 176s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 176s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 176s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 176s Successfully finished Verilog frontend. 176s 176s 2.36.2. Continuing TECHMAP pass. 176s Using template \$_DFF_P_ for cells of type $_DFF_P_. 176s No more expansions possible. 176s 176s 176s 2.37. Executing OPT_EXPR pass (perform const folding). 176s Optimizing module top. 176s 176s 2.38. Executing SIMPLEMAP pass (map simple cells to gate primitives). 176s Mapping top.$auto$alumacc.cc:485:replace_alu$465.slice[0].carry ($lut). 176s 176s 2.39. Executing ICE40_OPT pass (performing simple optimizations). 176s 176s 2.39.1. Running ICE40 specific optimizations. 176s 176s 2.39.2. Executing OPT_EXPR pass (perform const folding). 176s Optimizing module top. 176s 176s 176s 2.39.3. Executing OPT_MERGE pass (detect identical cells). 176s Finding identical cells in module `\top'. 176s Removed a total of 0 cells. 176s 176s 2.39.4. Executing OPT_DFF pass (perform DFF optimizations). 176s 176s 2.39.5. Executing OPT_CLEAN pass (remove unused cells and wires). 176s Finding unused cells or wires in module \top.. 176s Removed 0 unused cells and 132 unused wires. 176s 176s 176s 2.39.6. Rerunning OPT passes. (Removed registers in this run.) 176s 176s 2.39.7. Running ICE40 specific optimizations. 176s 176s 2.39.8. Executing OPT_EXPR pass (perform const folding). 176s Optimizing module top. 176s 176s 2.39.9. Executing OPT_MERGE pass (detect identical cells). 176s Finding identical cells in module `\top'. 176s Removed a total of 0 cells. 176s 176s 2.39.10. Executing OPT_DFF pass (perform DFF optimizations). 176s 176s 2.39.11. Executing OPT_CLEAN pass (remove unused cells and wires). 176s Finding unused cells or wires in module \top.. 176s 176s 2.39.12. Finished OPT passes. (There is nothing left to do.) 176s 176s 2.40. Executing TECHMAP pass (map to technology primitives). 176s 176s 2.40.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v 176s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation. 176s Generating RTLIL representation for module `\$_DLATCH_N_'. 176s Generating RTLIL representation for module `\$_DLATCH_P_'. 176s Successfully finished Verilog frontend. 176s 176s 2.40.2. Continuing TECHMAP pass. 176s No more expansions possible. 176s 176s 176s 2.41. Executing ABC pass (technology mapping using ABC). 176s 176s 2.41.1. Extracting gate netlist of module `\top' to `/input.blif'.. 176s Extracted 45 gates and 56 wires to a netlist network with 10 inputs and 23 outputs. 176s 176s 2.41.1.1. Executing ABC. 176s Running ABC command: "berkeley-abc" -s -f /abc.script 2>&1 176s ABC: ABC command line: "source /abc.script". 176s ABC: 176s ABC: + read_blif /input.blif 176s ABC: + read_lut /lutdefs.txt 176s ABC: + strash 176s ABC: + &get -n 176s ABC: + &fraig -x 176s ABC: + &put 176s ABC: + scorr 176s ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). 176s ABC: + dc2 176s ABC: + dretime 176s ABC: + strash 176s ABC: + dch -f 176s ABC: + if 176s ABC: + mfs2 176s ABC: + lutpack -S 1 176s ABC: + dress /input.blif 176s ABC: Total number of equiv classes = 24. 176s ABC: Participating nodes from both networks = 49. 176s ABC: Participating nodes from the first network = 23. ( 95.83 % of nodes) 176s ABC: Participating nodes from the second network = 26. ( 108.33 % of nodes) 176s ABC: Node pairs (any polarity) = 23. ( 95.83 % of names can be moved) 176s ABC: Node pairs (same polarity) = 23. ( 95.83 % of names can be moved) 176s ABC: Total runtime = 0.01 sec 176s ABC: + write_blif /output.blif 176s 176s 2.41.1.2. Re-integrating ABC results. 176s ABC RESULTS: $lut cells: 23 176s ABC RESULTS: internal signals: 23 176s ABC RESULTS: input signals: 10 176s ABC RESULTS: output signals: 23 176s Removing temp directory. 176s 176s 2.42. Executing ICE40_WRAPCARRY pass (wrap carries). 176s 176s 2.43. Executing TECHMAP pass (map to technology primitives). 176s 176s 2.43.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 176s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 176s Generating RTLIL representation for module `\$_DFF_N_'. 176s Generating RTLIL representation for module `\$_DFF_P_'. 176s Generating RTLIL representation for module `\$_DFFE_NP_'. 176s Generating RTLIL representation for module `\$_DFFE_PP_'. 176s Generating RTLIL representation for module `\$_DFF_NP0_'. 176s Generating RTLIL representation for module `\$_DFF_NP1_'. 176s Generating RTLIL representation for module `\$_DFF_PP0_'. 176s Generating RTLIL representation for module `\$_DFF_PP1_'. 176s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 176s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 176s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 176s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 176s Generating RTLIL representation for module `\$_SDFF_NP0_'. 176s Generating RTLIL representation for module `\$_SDFF_NP1_'. 176s Generating RTLIL representation for module `\$_SDFF_PP0_'. 176s Generating RTLIL representation for module `\$_SDFF_PP1_'. 176s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 176s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 176s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 176s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 176s Successfully finished Verilog frontend. 176s 176s 2.43.2. Continuing TECHMAP pass. 176s No more expansions possible. 176s 176s Removed 1 unused cells and 46 unused wires. 176s 176s 2.44. Executing OPT_LUT pass (optimize LUTs). 176s Discovering LUTs. 176s Number of LUTs: 49 176s 1-LUT 1 176s 2-LUT 5 176s 3-LUT 25 176s 4-LUT 18 176s with \SB_CARRY (#0) 25 176s with \SB_CARRY (#1) 25 176s 176s Eliminating LUTs. 176s Number of LUTs: 49 176s 1-LUT 1 176s 2-LUT 5 176s 3-LUT 25 176s 4-LUT 18 176s with \SB_CARRY (#0) 25 176s with \SB_CARRY (#1) 25 176s 176s Combining LUTs. 176s Number of LUTs: 49 176s 1-LUT 1 176s 2-LUT 5 176s 3-LUT 25 176s 4-LUT 18 176s with \SB_CARRY (#0) 25 176s with \SB_CARRY (#1) 25 176s 176s Eliminated 0 LUTs. 176s Combined 0 LUTs. 176s 176s 176s 2.45. Executing TECHMAP pass (map to technology primitives). 176s 176s 2.45.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v 176s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation. 176s Generating RTLIL representation for module `\$lut'. 176s Successfully finished Verilog frontend. 176s 176s 2.45.2. Continuing TECHMAP pass. 176s Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut. 176s Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut. 176s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut. 176s Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut. 176s Using template $paramod$38524f19a670105a447163ca7c0fbdcb0f76b0d7\$lut for cells of type $lut. 176s Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut. 176s Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut. 176s Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut. 176s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. 176s No more expansions possible. 176s 176s Removed 0 unused cells and 98 unused wires. 176s 176s 2.46. Executing AUTONAME pass. 176s Renamed 160 objects in module top (4 iterations). 176s 176s 176s 2.47. Executing HIERARCHY pass (managing design hierarchy). 176s 176s 2.47.1. Analyzing design hierarchy.. 176s Top module: \top 176s 176s 2.47.2. Analyzing design hierarchy.. 176s Top module: \top 176s Removed 0 unused modules. 176s 176s 2.48. Printing statistics. 176s 176s === top === 176s 176s Number of wires: 32 176s Number of wire bits: 114 176s Number of public wires: 32 176s Number of public wire bits: 114 176s Number of memories: 0 176s Number of memory bits: 0 176s Number of processes: 0 176s Number of cells: 106 176s SB_CARRY 25 176s SB_DFF 32 176s SB_LUT4 49 176s 176s 2.49. Executing CHECK pass (checking for obvious problems). 176s Checking module top... 176s Found and reported 0 problems. 176s 176s 2.50. Executing JSON backend. 176s 176s End of script. Logfile hash: 5e0858e2ba, CPU: user 1.08s system 0.02s, MEM: 22.00 MB peak 176s Yosys 0.23 (git sha1 7ce5011c24b) 176s Time spent: 59% 13x read_verilog (0 sec), 7% 1x abc (0 sec), ... 176s nextpnr-ice40 --up5k --package sg48 --asc example.asc --pcf icebreaker.pcf --json example.json 176s Info: constrained 'CLK' to bel 'X12/Y31/io1' 176s Info: constrained 'BTN_N' to bel 'X16/Y0/io0' 176s Info: constrained 'LEDR_N' to bel 'X17/Y0/io0' 176s Info: constrained 'LEDG_N' to bel 'X13/Y31/io0' 176s Info: constrained 'P1A1' to bel 'X9/Y0/io0' 176s Info: constrained 'P1A2' to bel 'X8/Y0/io0' 176s Info: constrained 'P1A3' to bel 'X6/Y0/io0' 176s Info: constrained 'P1A4' to bel 'X7/Y0/io1' 176s Info: constrained 'P1A7' to bel 'X9/Y0/io1' 176s Info: constrained 'P1A8' to bel 'X7/Y0/io0' 176s Info: constrained 'P1A9' to bel 'X5/Y0/io0' 176s Info: constrained 'P1A10' to bel 'X6/Y0/io1' 176s Info: constrained 'P1B1' to bel 'X9/Y31/io0' 176s Info: constrained 'P1B2' to bel 'X8/Y31/io1' 176s Info: constrained 'P1B3' to bel 'X13/Y31/io1' 176s Info: constrained 'P1B4' to bel 'X16/Y31/io1' 176s Info: constrained 'P1B7' to bel 'X8/Y31/io0' 176s Info: constrained 'P1B8' to bel 'X9/Y31/io1' 176s Info: constrained 'P1B9' to bel 'X16/Y31/io0' 176s Info: constrained 'P1B10' to bel 'X17/Y31/io0' 176s Info: constrained 'LED1' to bel 'X18/Y31/io1' 176s Info: constrained 'LED2' to bel 'X19/Y31/io1' 176s Info: constrained 'LED3' to bel 'X18/Y0/io1' 176s Info: constrained 'BTN2' to bel 'X21/Y0/io1' 176s Info: constrained 'LED5' to bel 'X18/Y31/io0' 176s Info: constrained 'LED4' to bel 'X19/Y31/io0' 176s Info: constrained 'BTN1' to bel 'X19/Y0/io1' 176s Info: constrained 'BTN3' to bel 'X22/Y0/io1' 176s 176s Info: Packing constants.. 176s Info: Packing IOs.. 176s Info: Packing LUT-FFs.. 176s Info: 22 LCs used as LUT4 only 176s Info: 27 LCs used as LUT4 and DFF 176s Info: Packing non-LUT FFs.. 176s Info: 5 LCs used as DFF only 176s Info: Packing carries.. 176s Info: 0 LCs used as CARRY only 176s Info: Packing indirect carry+LUT pairs... 176s Info: 0 LUTs merged into carry LCs 176s Info: Packing RAMs.. 176s Info: Placing PLLs.. 176s Info: Packing special functions.. 176s Info: Packing PLLs.. 176s Info: Promoting globals.. 176s Info: promoting CLK$SB_IO_IN (fanout 32) 176s Info: Constraining chains... 176s Info: 1 LCs used to legalise carry chains. 176s Info: Checksum: 0xb7f7ed8b 176s 176s Info: Annotating ports with timing budgets for target frequency 12.00 MHz 176s Info: Checksum: 0xed88872c 176s 176s Info: Device utilisation: 176s Info: ICESTORM_LC: 57/ 5280 1% 176s Info: ICESTORM_RAM: 0/ 30 0% 176s Info: SB_IO: 28/ 96 29% 176s Info: SB_GB: 1/ 8 12% 176s Info: ICESTORM_PLL: 0/ 1 0% 176s Info: SB_WARMBOOT: 0/ 1 0% 176s Info: ICESTORM_DSP: 0/ 8 0% 176s Info: ICESTORM_HFOSC: 0/ 1 0% 176s Info: ICESTORM_LFOSC: 0/ 1 0% 176s Info: SB_I2C: 0/ 2 0% 176s Info: SB_SPI: 0/ 2 0% 176s Info: IO_I3C: 0/ 2 0% 176s Info: SB_LEDDA_IP: 0/ 1 0% 176s Info: SB_RGBA_DRV: 0/ 1 0% 176s Info: ICESTORM_SPRAM: 0/ 4 0% 176s 176s Info: Placed 28 cells based on constraints. 176s Info: Creating initial analytic placement for 30 cells, random placement wirelen = 1117. 176s Info: at initial placer iter 0, wirelen = 243 176s Info: at initial placer iter 1, wirelen = 245 176s Info: at initial placer iter 2, wirelen = 242 176s Info: at initial placer iter 3, wirelen = 245 176s Info: Running main analytical placer, max placement attempts per cell = 10000. 176s Info: at iteration #1, type ICESTORM_LC: wirelen solved = 242, spread = 260, legal = 288; time = 0.00s 176s Info: at iteration #1, type SB_GB: wirelen solved = 288, spread = 288, legal = 288; time = 0.00s 176s Info: at iteration #1, type ALL: wirelen solved = 245, spread = 265, legal = 299; time = 0.00s 176s Info: HeAP Placer Time: 0.01s 176s Info: of which solving equations: 0.01s 176s Info: of which spreading cells: 0.00s 176s Info: of which strict legalisation: 0.00s 176s 176s Info: Running simulated annealing placer for refinement. 176s Info: at iteration #1: temp = 0.000000, timing cost = 10, wirelen = 299 176s Info: at iteration #5: temp = 0.000000, timing cost = 10, wirelen = 252 176s Info: at iteration #10: temp = 0.000000, timing cost = 10, wirelen = 250 176s Info: at iteration #11: temp = 0.000000, timing cost = 10, wirelen = 248 176s Info: SA placement time 0.01s 176s 176s Info: Max frequency for clock 'CLK$SB_IO_IN_$glb_clk': 76.86 MHz (PASS at 12.00 MHz) 176s 176s Info: Max delay -> : 11.07 ns 176s Info: Max delay posedge CLK$SB_IO_IN_$glb_clk -> : 12.54 ns 176s 176s Info: Slack histogram: 176s Info: legend: * represents 1 endpoint(s) 176s Info: + represents [1,1) endpoint(s) 176s Info: [ 70323, 70775) |*** 176s Info: [ 70775, 71227) |* 176s Info: [ 71227, 71679) |* 176s Info: [ 71679, 72131) |********* 176s Info: [ 72131, 72583) |*** 176s Info: [ 72583, 73035) |** 176s Info: [ 73035, 73487) |** 176s Info: [ 73487, 73939) |* 176s Info: [ 73939, 74391) |* 176s Info: [ 74391, 74843) |** 176s Info: [ 74843, 75295) |****** 176s Info: [ 75295, 75747) |**** 176s Info: [ 75747, 76199) |*** 176s Info: [ 76199, 76651) |**** 176s Info: [ 76651, 77103) |* 176s Info: [ 77103, 77555) |*** 176s Info: [ 77555, 78007) |* 176s Info: [ 78007, 78459) | 176s Info: [ 78459, 78911) | 176s Info: [ 78911, 79363) |********************************** 176s Info: Checksum: 0xa7f4dfe8 176s 176s Info: Routing.. 176s Info: Setting up routing queue. 176s Info: Routing 194 arcs. 176s Info: | (re-)routed arcs | delta | remaining| time spent | 176s Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| 177s Info: 194 | 0 172 | 0 172 | 0| 0.12 0.12| 177s Info: Routing complete. 177s Info: Router1 time 0.12s 177s Info: Checksum: 0x5b3eaafc 177s 177s Info: Critical path report for clock 'CLK$SB_IO_IN_$glb_clk' (posedge -> posedge): 177s Info: curr total 177s Info: 1.4 1.4 Source counter_SB_LUT4_I3_LC.O 177s Info: 1.8 3.2 Net counter[0] budget 72.830002 ns (15,25) -> (16,25) 177s Info: Sink $nextpnr_ICESTORM_LC_0.I1 177s Info: Defined in: 177s Info: example.v:29.14-29.25 177s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 177s Info: 0.7 3.8 Source $nextpnr_ICESTORM_LC_0.COUT 177s Info: 0.0 3.8 Net $nextpnr_ICESTORM_LC_0$O budget 0.000000 ns (16,25) -> (16,25) 177s Info: Sink counter_SB_LUT4_I2_15_LC.CIN 177s Info: 0.3 4.1 Source counter_SB_LUT4_I2_15_LC.COUT 177s Info: 0.0 4.1 Net counter_SB_CARRY_CI_CO[2] budget 0.000000 ns (16,25) -> (16,25) 177s Info: Sink counter_SB_LUT4_I2_7_LC.CIN 177s Info: Defined in: 177s Info: example.v:29.14-29.25 177s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 177s Info: 0.3 4.4 Source counter_SB_LUT4_I2_7_LC.COUT 177s Info: 0.0 4.4 Net counter_SB_CARRY_CI_CO[3] budget 0.000000 ns (16,25) -> (16,25) 177s Info: Sink counter_SB_LUT4_I2_6_LC.CIN 177s Info: Defined in: 177s Info: example.v:29.14-29.25 177s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 177s Info: 0.3 4.7 Source counter_SB_LUT4_I2_6_LC.COUT 177s Info: 0.0 4.7 Net counter_SB_CARRY_CI_CO[4] budget 0.000000 ns (16,25) -> (16,25) 177s Info: Sink counter_SB_LUT4_I2_5_LC.CIN 177s Info: Defined in: 177s Info: example.v:29.14-29.25 177s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 177s Info: 0.3 4.9 Source counter_SB_LUT4_I2_5_LC.COUT 177s Info: 0.0 4.9 Net counter_SB_CARRY_CI_CO[5] budget 0.000000 ns (16,25) -> (16,25) 177s Info: Sink counter_SB_LUT4_I2_4_LC.CIN 177s Info: Defined in: 177s Info: example.v:29.14-29.25 177s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 177s Info: 0.3 5.2 Source counter_SB_LUT4_I2_4_LC.COUT 177s Info: 0.0 5.2 Net counter_SB_CARRY_CI_CO[6] budget 0.000000 ns (16,25) -> (16,25) 177s Info: Sink counter_SB_LUT4_I2_3_LC.CIN 177s Info: Defined in: 177s Info: example.v:29.14-29.25 177s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 177s Info: 0.3 5.5 Source counter_SB_LUT4_I2_3_LC.COUT 177s Info: 0.0 5.5 Net counter_SB_CARRY_CI_CO[7] budget 0.000000 ns (16,25) -> (16,25) 177s Info: Sink counter_SB_LUT4_I2_2_LC.CIN 177s Info: Defined in: 177s Info: example.v:29.14-29.25 177s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 177s Info: 0.3 5.8 Source counter_SB_LUT4_I2_2_LC.COUT 177s Info: 0.6 6.3 Net counter_SB_CARRY_CI_CO[8] budget 0.560000 ns (16,25) -> (16,26) 177s Info: Sink counter_SB_LUT4_I2_1_LC.CIN 177s Info: Defined in: 177s Info: example.v:29.14-29.25 177s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 177s Info: 0.3 6.6 Source counter_SB_LUT4_I2_1_LC.COUT 177s Info: 0.0 6.6 Net counter_SB_CARRY_CI_CO[9] budget 0.000000 ns (16,26) -> (16,26) 177s Info: Sink counter_SB_LUT4_I2_LC.CIN 177s Info: Defined in: 177s Info: example.v:29.14-29.25 177s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 177s Info: 0.3 6.9 Source counter_SB_LUT4_I2_LC.COUT 177s Info: 0.0 6.9 Net counter_SB_CARRY_CI_CO[10] budget 0.000000 ns (16,26) -> (16,26) 177s Info: Sink counter_SB_LUT4_I2_25_LC.CIN 177s Info: Defined in: 177s Info: example.v:29.14-29.25 177s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 177s Info: 0.3 7.2 Source counter_SB_LUT4_I2_25_LC.COUT 177s Info: 0.0 7.2 Net counter_SB_CARRY_CI_CO[11] budget 0.000000 ns (16,26) -> (16,26) 177s Info: Sink counter_SB_LUT4_I2_24_LC.CIN 177s Info: Defined in: 177s Info: example.v:29.14-29.25 177s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 177s Info: 0.3 7.4 Source counter_SB_LUT4_I2_24_LC.COUT 177s Info: 0.0 7.4 Net counter_SB_CARRY_CI_CO[12] budget 0.000000 ns (16,26) -> (16,26) 177s Info: Sink counter_SB_LUT4_I2_23_LC.CIN 177s Info: Defined in: 177s Info: example.v:29.14-29.25 177s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 177s Info: 0.3 7.7 Source counter_SB_LUT4_I2_23_LC.COUT 177s Info: 0.0 7.7 Net counter_SB_CARRY_CI_CO[13] budget 0.000000 ns (16,26) -> (16,26) 177s Info: Sink counter_SB_LUT4_I2_22_LC.CIN 177s Info: Defined in: 177s Info: example.v:29.14-29.25 177s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 177s Info: 0.3 8.0 Source counter_SB_LUT4_I2_22_LC.COUT 177s Info: 0.0 8.0 Net counter_SB_CARRY_CI_CO[14] budget 0.000000 ns (16,26) -> (16,26) 177s Info: Sink counter_SB_LUT4_I2_21_LC.CIN 177s Info: Defined in: 177s Info: example.v:29.14-29.25 177s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 177s Info: 0.3 8.3 Source counter_SB_LUT4_I2_21_LC.COUT 177s Info: 0.0 8.3 Net counter_SB_CARRY_CI_CO[15] budget 0.000000 ns (16,26) -> (16,26) 177s Info: Sink counter_SB_LUT4_I2_20_LC.CIN 177s Info: Defined in: 177s Info: example.v:29.14-29.25 177s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 177s Info: 0.3 8.6 Source counter_SB_LUT4_I2_20_LC.COUT 177s Info: 0.6 9.1 Net counter_SB_CARRY_CI_CO[16] budget 0.560000 ns (16,26) -> (16,27) 177s Info: Sink counter_SB_LUT4_I2_19_LC.CIN 177s Info: Defined in: 177s Info: example.v:29.14-29.25 177s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 177s Info: 0.3 9.4 Source counter_SB_LUT4_I2_19_LC.COUT 177s Info: 0.0 9.4 Net counter_SB_CARRY_CI_CO[17] budget 0.000000 ns (16,27) -> (16,27) 177s Info: Sink counter_SB_LUT4_I2_18_LC.CIN 177s Info: Defined in: 177s Info: example.v:29.14-29.25 177s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 177s Info: 0.3 9.7 Source counter_SB_LUT4_I2_18_LC.COUT 177s Info: 0.0 9.7 Net counter_SB_CARRY_CI_CO[18] budget 0.000000 ns (16,27) -> (16,27) 177s Info: Sink counter_SB_LUT4_I2_17_LC.CIN 177s Info: Defined in: 177s Info: example.v:29.14-29.25 177s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 177s Info: 0.3 9.9 Source counter_SB_LUT4_I2_17_LC.COUT 177s Info: 0.0 9.9 Net counter_SB_CARRY_CI_CO[19] budget 0.000000 ns (16,27) -> (16,27) 177s Info: Sink counter_SB_LUT4_I2_16_LC.CIN 177s Info: Defined in: 177s Info: example.v:29.14-29.25 177s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 177s Info: 0.3 10.2 Source counter_SB_LUT4_I2_16_LC.COUT 177s Info: 0.0 10.2 Net counter_SB_CARRY_CI_CO[20] budget 0.000000 ns (16,27) -> (16,27) 177s Info: Sink counter_SB_LUT4_I2_14_LC.CIN 177s Info: Defined in: 177s Info: example.v:29.14-29.25 177s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 177s Info: 0.3 10.5 Source counter_SB_LUT4_I2_14_LC.COUT 177s Info: 0.0 10.5 Net counter_SB_CARRY_CI_CO[21] budget 0.000000 ns (16,27) -> (16,27) 177s Info: Sink counter_SB_LUT4_I2_13_LC.CIN 177s Info: Defined in: 177s Info: example.v:29.14-29.25 177s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 177s Info: 0.3 10.8 Source counter_SB_LUT4_I2_13_LC.COUT 177s Info: 0.0 10.8 Net counter_SB_CARRY_CI_CO[22] budget 0.000000 ns (16,27) -> (16,27) 177s Info: Sink counter_SB_LUT4_I2_12_LC.CIN 177s Info: Defined in: 177s Info: example.v:29.14-29.25 177s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 177s Info: 0.3 11.1 Source counter_SB_LUT4_I2_12_LC.COUT 177s Info: 0.0 11.1 Net counter_SB_CARRY_CI_CO[23] budget 0.000000 ns (16,27) -> (16,27) 177s Info: Sink counter_SB_LUT4_I2_11_LC.CIN 177s Info: Defined in: 177s Info: example.v:29.14-29.25 177s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 177s Info: 0.3 11.3 Source counter_SB_LUT4_I2_11_LC.COUT 177s Info: 0.6 11.9 Net counter_SB_CARRY_CI_CO[24] budget 0.560000 ns (16,27) -> (16,28) 177s Info: Sink counter_SB_LUT4_I2_10_LC.CIN 177s Info: Defined in: 177s Info: example.v:29.14-29.25 177s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 177s Info: 0.3 12.2 Source counter_SB_LUT4_I2_10_LC.COUT 177s Info: 0.0 12.2 Net counter_SB_CARRY_CI_CO[25] budget 0.000000 ns (16,28) -> (16,28) 177s Info: Sink counter_SB_LUT4_I2_9_LC.CIN 177s Info: Defined in: 177s Info: example.v:29.14-29.25 177s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 177s Info: 0.3 12.4 Source counter_SB_LUT4_I2_9_LC.COUT 177s Info: 0.7 13.1 Net counter_SB_CARRY_CI_CO[26] budget 0.660000 ns (16,28) -> (16,28) 177s Info: Sink counter_SB_LUT4_I2_8_LC.I3 177s Info: Defined in: 177s Info: example.v:29.14-29.25 177s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 177s Info: 0.8 13.9 Setup counter_SB_LUT4_I2_8_LC.I3 177s Info: 9.8 ns logic, 4.1 ns routing 177s 177s Info: Critical path report for cross-domain path '' -> '': 177s Info: curr total 177s Info: 0.0 0.0 Source BTN3$sb_io.D_IN_0 177s Info: 3.6 3.6 Net BTN3$SB_IO_IN budget 41.025002 ns (22,0) -> (17,1) 177s Info: Sink LEDG_N_SB_LUT4_O_LC.I3 177s Info: Defined in: 177s Info: example.v:13.8-13.12 177s Info: 0.9 4.5 Source LEDG_N_SB_LUT4_O_LC.O 177s Info: 7.0 11.5 Net LEDG_N$SB_IO_OUT budget 41.023998 ns (17,1) -> (13,31) 177s Info: Sink LEDG_N$sb_io.D_OUT_0 177s Info: Defined in: 177s Info: example.v:16.9-16.15 177s Info: 0.9 ns logic, 10.6 ns routing 177s 177s Info: Critical path report for cross-domain path 'posedge CLK$SB_IO_IN_$glb_clk' -> '': 177s Info: curr total 177s Info: 1.4 1.4 Source outcnt_SB_DFF_Q_1_DFFLC.O 177s Info: 7.5 8.9 Net outcnt[2] budget 40.330002 ns (16,28) -> (7,1) 177s Info: Sink P1A9_SB_LUT4_O_LC.I1 177s Info: Defined in: 177s Info: example.v:26.17-26.23 177s Info: 1.2 10.1 Source P1A9_SB_LUT4_O_LC.O 177s Info: 3.1 13.2 Net P1A9$SB_IO_OUT budget 40.328999 ns (7,1) -> (5,0) 177s Info: Sink P1A9$sb_io.D_OUT_0 177s Info: Defined in: 177s Info: example.v:18.45-18.49 177s Info: 2.6 ns logic, 10.5 ns routing 177s 177s Info: Max frequency for clock 'CLK$SB_IO_IN_$glb_clk': 71.80 MHz (PASS at 12.00 MHz) 177s 177s Info: Max delay -> : 11.52 ns 177s Info: Max delay posedge CLK$SB_IO_IN_$glb_clk -> : 13.17 ns 177s 177s Info: Slack histogram: 177s Info: legend: * represents 1 endpoint(s) 177s Info: + represents [1,1) endpoint(s) 177s Info: [ 69405, 69903) |** 177s Info: [ 69903, 70401) |** 177s Info: [ 70401, 70899) |* 177s Info: [ 70899, 71397) |*** 177s Info: [ 71397, 71895) |******** 177s Info: [ 71895, 72393) |** 177s Info: [ 72393, 72891) |*** 177s Info: [ 72891, 73389) | 177s Info: [ 73389, 73887) |** 177s Info: [ 73887, 74385) |* 177s Info: [ 74385, 74883) |** 177s Info: [ 74883, 75381) |**** 177s Info: [ 75381, 75879) |***** 177s Info: [ 75879, 76377) |** 177s Info: [ 76377, 76875) |***** 177s Info: [ 76875, 77373) |*** 177s Info: [ 77373, 77871) |** 177s Info: [ 77871, 78369) | 177s Info: [ 78369, 78867) | 177s Info: [ 78867, 79365) |********************************** 177s 177s Info: Program finished normally. 177s icetime -d up5k -mtr example.rpt example.asc 177s // Reading input .asc file.. 177s // Reading 5k chipdb file.. 178s // Creating timing netlist.. 178s // Timing estimate: 13.73 ns (72.84 MHz) 178s icepack example.asc example.bin 178s make: Leaving directory '/tmp/autopkgtest.DyuG3m/build.kB5/src/examples/icebreaker' 178s make: Entering directory '/tmp/autopkgtest.DyuG3m/build.kB5/src/examples/icemulti' 178s yosys -p "synth_ice40 -top top -json app0.json" app0.v 178s 178s /----------------------------------------------------------------------------\ 178s | | 178s | yosys -- Yosys Open SYnthesis Suite | 178s | | 178s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 178s | | 178s | Permission to use, copy, modify, and/or distribute this software for any | 178s | purpose with or without fee is hereby granted, provided that the above | 178s | copyright notice and this permission notice appear in all copies. | 178s | | 178s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 178s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 178s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 178s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 178s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 178s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 178s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 178s | | 178s \----------------------------------------------------------------------------/ 178s 178s Yosys 0.23 (git sha1 7ce5011c24b) 178s 178s 178s -- Parsing `app0.v' using frontend ` -vlog2k' -- 178s 178s 1. Executing Verilog-2005 frontend: app0.v 178s Parsing Verilog input from `app0.v' to AST representation. 178s Storing AST representation for module `$abstract\top'. 178s Successfully finished Verilog frontend. 178s 178s -- Running command `synth_ice40 -top top -json app0.json' -- 178s 178s 2. Executing SYNTH_ICE40 pass. 178s 178s 2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v 178s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation. 178s Generating RTLIL representation for module `\SB_IO'. 178s Generating RTLIL representation for module `\SB_GB_IO'. 178s Generating RTLIL representation for module `\SB_GB'. 178s Generating RTLIL representation for module `\SB_LUT4'. 178s Generating RTLIL representation for module `\SB_CARRY'. 178s Generating RTLIL representation for module `\SB_DFF'. 178s Generating RTLIL representation for module `\SB_DFFE'. 178s Generating RTLIL representation for module `\SB_DFFSR'. 178s Generating RTLIL representation for module `\SB_DFFR'. 178s Generating RTLIL representation for module `\SB_DFFSS'. 178s Generating RTLIL representation for module `\SB_DFFS'. 178s Generating RTLIL representation for module `\SB_DFFESR'. 178s Generating RTLIL representation for module `\SB_DFFER'. 178s Generating RTLIL representation for module `\SB_DFFESS'. 178s Generating RTLIL representation for module `\SB_DFFES'. 178s Generating RTLIL representation for module `\SB_DFFN'. 178s Generating RTLIL representation for module `\SB_DFFNE'. 178s Generating RTLIL representation for module `\SB_DFFNSR'. 178s Generating RTLIL representation for module `\SB_DFFNR'. 178s Generating RTLIL representation for module `\SB_DFFNSS'. 178s Generating RTLIL representation for module `\SB_DFFNS'. 178s Generating RTLIL representation for module `\SB_DFFNESR'. 178s Generating RTLIL representation for module `\SB_DFFNER'. 178s Generating RTLIL representation for module `\SB_DFFNESS'. 178s Generating RTLIL representation for module `\SB_DFFNES'. 178s Generating RTLIL representation for module `\SB_RAM40_4K'. 178s Generating RTLIL representation for module `\SB_RAM40_4KNR'. 178s Generating RTLIL representation for module `\SB_RAM40_4KNW'. 178s Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. 178s Generating RTLIL representation for module `\ICESTORM_LC'. 178s Generating RTLIL representation for module `\SB_PLL40_CORE'. 178s Generating RTLIL representation for module `\SB_PLL40_PAD'. 178s Generating RTLIL representation for module `\SB_PLL40_2_PAD'. 178s Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. 178s Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. 178s Generating RTLIL representation for module `\SB_WARMBOOT'. 178s Generating RTLIL representation for module `\SB_SPRAM256KA'. 178s Generating RTLIL representation for module `\SB_HFOSC'. 178s Generating RTLIL representation for module `\SB_LFOSC'. 178s Generating RTLIL representation for module `\SB_RGBA_DRV'. 178s Generating RTLIL representation for module `\SB_LED_DRV_CUR'. 178s Generating RTLIL representation for module `\SB_RGB_DRV'. 178s Generating RTLIL representation for module `\SB_I2C'. 178s Generating RTLIL representation for module `\SB_SPI'. 178s Generating RTLIL representation for module `\SB_LEDDA_IP'. 178s Generating RTLIL representation for module `\SB_FILTER_50NS'. 178s Generating RTLIL representation for module `\SB_IO_I3C'. 178s Generating RTLIL representation for module `\SB_IO_OD'. 178s Generating RTLIL representation for module `\SB_MAC16'. 178s Generating RTLIL representation for module `\ICESTORM_RAM'. 178s Successfully finished Verilog frontend. 178s 178s 2.2. Executing HIERARCHY pass (managing design hierarchy). 178s 178s 2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\top'. 178s Generating RTLIL representation for module `\top'. 178s 178s 2.3.1. Analyzing design hierarchy.. 178s Top module: \top 178s 178s 2.3.2. Analyzing design hierarchy.. 178s Top module: \top 178s Removing unused module `$abstract\top'. 178s Removed 1 unused modules. 178s 178s 2.4. Executing PROC pass (convert processes to netlists). 178s 178s 2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 178s Cleaned up 0 empty switches. 178s 178s 2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 178s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241 in module SB_DFFNES. 178s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234 in module SB_DFFNESS. 178s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230 in module SB_DFFNER. 178s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223 in module SB_DFFNESR. 178s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220 in module SB_DFFNS. 178s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217 in module SB_DFFNSS. 178s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214 in module SB_DFFNR. 178s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211 in module SB_DFFNSR. 178s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203 in module SB_DFFES. 178s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196 in module SB_DFFESS. 178s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192 in module SB_DFFER. 178s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185 in module SB_DFFESR. 178s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182 in module SB_DFFS. 178s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179 in module SB_DFFSS. 178s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176 in module SB_DFFR. 178s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173 in module SB_DFFSR. 178s Removed a total of 0 dead cases. 178s 178s 2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 178s Removed 8 redundant assignments. 178s Promoted 28 assignments to connections. 178s 178s 2.4.4. Executing PROC_INIT pass (extract init attributes). 178s Found init rule in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 178s Set init value: \Q = 1'0 178s Found init rule in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 178s Set init value: \Q = 1'0 178s Found init rule in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 178s Set init value: \Q = 1'0 178s Found init rule in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 178s Set init value: \Q = 1'0 178s Found init rule in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 178s Set init value: \Q = 1'0 178s Found init rule in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 178s Set init value: \Q = 1'0 178s Found init rule in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 178s Set init value: \Q = 1'0 178s Found init rule in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 178s Set init value: \Q = 1'0 178s Found init rule in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 178s Set init value: \Q = 1'0 178s Found init rule in `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 178s Set init value: \Q = 1'0 178s Found init rule in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 178s Set init value: \Q = 1'0 178s Found init rule in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 178s Set init value: \Q = 1'0 178s Found init rule in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 178s Set init value: \Q = 1'0 178s Found init rule in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 178s Set init value: \Q = 1'0 178s Found init rule in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 178s Set init value: \Q = 1'0 178s Found init rule in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 178s Set init value: \Q = 1'0 178s Found init rule in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 178s Set init value: \Q = 1'0 178s Found init rule in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 178s Set init value: \Q = 1'0 178s Found init rule in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 178s Set init value: \Q = 1'0 178s Found init rule in `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 178s Set init value: \Q = 1'0 178s Found init rule in `\top.$proc$app0.v:9$390'. 178s Set init value: \state = 1'0 178s Found init rule in `\top.$proc$app0.v:8$389'. 178s Set init value: \counter2 = 4'0000 178s Found init rule in `\top.$proc$app0.v:7$388'. 178s Set init value: \counter = 22'0000000000000000000000 178s 178s 2.4.5. Executing PROC_ARST pass (detect async resets in processes). 178s Found async reset \S in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 178s Found async reset \R in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 178s Found async reset \S in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 178s Found async reset \R in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 178s Found async reset \S in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 178s Found async reset \R in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 178s Found async reset \S in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 178s Found async reset \R in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 178s 178s 2.4.6. Executing PROC_ROM pass (convert switches to ROMs). 178s Converted 0 switches. 178s 178s 178s 2.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 178s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 178s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 178s 1/1: $0\Q[0:0] 178s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 178s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 178s 1/1: $0\Q[0:0] 178s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 178s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 178s 1/1: $0\Q[0:0] 178s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 178s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 178s 1/1: $0\Q[0:0] 178s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 178s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 178s 1/1: $0\Q[0:0] 178s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 178s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 178s 1/1: $0\Q[0:0] 178s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 178s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 178s 1/1: $0\Q[0:0] 178s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 178s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 178s 1/1: $0\Q[0:0] 178s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 178s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 178s 1/1: $0\Q[0:0] 178s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 178s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 178s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 178s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 178s 1/1: $0\Q[0:0] 178s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 178s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 178s 1/1: $0\Q[0:0] 178s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 178s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 178s 1/1: $0\Q[0:0] 178s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 178s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 178s 1/1: $0\Q[0:0] 178s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 178s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 178s 1/1: $0\Q[0:0] 178s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 178s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 178s 1/1: $0\Q[0:0] 178s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 178s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 178s 1/1: $0\Q[0:0] 178s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 178s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 178s 1/1: $0\Q[0:0] 178s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 178s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 178s 1/1: $0\Q[0:0] 178s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 178s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 178s Creating decoders for process `\top.$proc$app0.v:9$390'. 178s Creating decoders for process `\top.$proc$app0.v:8$389'. 178s Creating decoders for process `\top.$proc$app0.v:7$388'. 178s Creating decoders for process `\top.$proc$app0.v:11$381'. 178s 178s 2.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). 178s 178s 2.4.9. Executing PROC_DFF pass (convert process syncs to FFs). 178s Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 178s created $adff cell `$procdff$435' with negative edge clock and positive level reset. 178s Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 178s created $dff cell `$procdff$436' with negative edge clock. 178s Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 178s created $adff cell `$procdff$437' with negative edge clock and positive level reset. 178s Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 178s created $dff cell `$procdff$438' with negative edge clock. 178s Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 178s created $adff cell `$procdff$439' with negative edge clock and positive level reset. 178s Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 178s created $dff cell `$procdff$440' with negative edge clock. 178s Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 178s created $adff cell `$procdff$441' with negative edge clock and positive level reset. 178s Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 178s created $dff cell `$procdff$442' with negative edge clock. 178s Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 178s created $dff cell `$procdff$443' with negative edge clock. 178s Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 178s created $dff cell `$procdff$444' with negative edge clock. 178s Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 178s created $adff cell `$procdff$445' with positive edge clock and positive level reset. 178s Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 178s created $dff cell `$procdff$446' with positive edge clock. 178s Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 178s created $adff cell `$procdff$447' with positive edge clock and positive level reset. 178s Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 178s created $dff cell `$procdff$448' with positive edge clock. 178s Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 178s created $adff cell `$procdff$449' with positive edge clock and positive level reset. 178s Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 178s created $dff cell `$procdff$450' with positive edge clock. 178s Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 178s created $adff cell `$procdff$451' with positive edge clock and positive level reset. 178s Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 178s created $dff cell `$procdff$452' with positive edge clock. 178s Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 178s created $dff cell `$procdff$453' with positive edge clock. 178s Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 178s created $dff cell `$procdff$454' with positive edge clock. 178s Creating register for signal `\top.\counter' using process `\top.$proc$app0.v:11$381'. 178s created $dff cell `$procdff$455' with positive edge clock. 178s Creating register for signal `\top.\counter2' using process `\top.$proc$app0.v:11$381'. 178s created $dff cell `$procdff$456' with positive edge clock. 178s Creating register for signal `\top.\state' using process `\top.$proc$app0.v:11$381'. 178s created $dff cell `$procdff$457' with positive edge clock. 178s 178s 2.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 178s 178s 2.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 178s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 178s Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 178s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 178s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 178s Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 178s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 178s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 178s Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 178s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 178s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 178s Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 178s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 178s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 178s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 178s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 178s Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 178s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 178s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 178s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 178s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 178s Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 178s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 178s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 178s Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 178s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 178s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 178s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 178s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 178s Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 178s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 178s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 178s Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 178s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 178s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 178s Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 178s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 178s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 178s Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 178s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 178s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 178s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 178s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 178s Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 178s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 178s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 178s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 178s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 178s Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 178s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 178s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 178s Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 178s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 178s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 178s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 178s Removing empty process `top.$proc$app0.v:9$390'. 178s Removing empty process `top.$proc$app0.v:8$389'. 178s Removing empty process `top.$proc$app0.v:7$388'. 178s Removing empty process `top.$proc$app0.v:11$381'. 178s Cleaned up 18 empty switches. 178s 178s 2.4.12. Executing OPT_EXPR pass (perform const folding). 178s Optimizing module top. 178s 178s 2.5. Executing FLATTEN pass (flatten design). 178s 178s 2.6. Executing TRIBUF pass. 178s 178s 2.7. Executing DEMINOUT pass (demote inout ports to input or output). 178s 178s 2.8. Executing OPT_EXPR pass (perform const folding). 178s Optimizing module top. 178s 178s 2.9. Executing OPT_CLEAN pass (remove unused cells and wires). 178s Finding unused cells or wires in module \top.. 178s Removed 0 unused cells and 5 unused wires. 178s 178s 178s 2.10. Executing CHECK pass (checking for obvious problems). 178s Checking module top... 178s Found and reported 0 problems. 178s 178s 2.11. Executing OPT pass (performing simple optimizations). 178s 178s 2.11.1. Executing OPT_EXPR pass (perform const folding). 178s Optimizing module top. 178s 178s 2.11.2. Executing OPT_MERGE pass (detect identical cells). 178s Finding identical cells in module `\top'. 178s Removed a total of 0 cells. 178s 178s 2.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 178s Running muxtree optimizer on module \top.. 178s Creating internal representation of mux trees. 178s No muxes found in this module. 178s Removed 0 multiplexer ports. 178s 178s 2.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 178s Optimizing cells in module \top. 178s Performed a total of 0 changes. 178s 178s 2.11.5. Executing OPT_MERGE pass (detect identical cells). 178s Finding identical cells in module `\top'. 178s Removed a total of 0 cells. 178s 178s 2.11.6. Executing OPT_DFF pass (perform DFF optimizations). 178s 178s 2.11.7. Executing OPT_CLEAN pass (remove unused cells and wires). 178s Finding unused cells or wires in module \top.. 178s 178s 2.11.8. Executing OPT_EXPR pass (perform const folding). 178s Optimizing module top. 178s 178s 2.11.9. Finished OPT passes. (There is nothing left to do.) 178s 178s 2.12. Executing FSM pass (extract and optimize FSM). 178s 178s 2.12.1. Executing FSM_DETECT pass (finding FSMs in design). 178s 178s 2.12.2. Executing FSM_EXTRACT pass (extracting FSM from design). 178s 178s 2.12.3. Executing FSM_OPT pass (simple optimizations of FSMs). 178s 178s 2.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). 178s Finding unused cells or wires in module \top.. 178s 178s 2.12.5. Executing FSM_OPT pass (simple optimizations of FSMs). 178s 178s 2.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 178s 178s 2.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 178s 178s 2.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 178s 178s 2.13. Executing OPT pass (performing simple optimizations). 178s 178s 2.13.1. Executing OPT_EXPR pass (perform const folding). 178s Optimizing module top. 178s 178s 2.13.2. Executing OPT_MERGE pass (detect identical cells). 178s Finding identical cells in module `\top'. 178s Removed a total of 0 cells. 178s 178s 2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 178s Running muxtree optimizer on module \top.. 178s Creating internal representation of mux trees. 178s No muxes found in this module. 178s Removed 0 multiplexer ports. 178s 178s 2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 178s Optimizing cells in module \top. 178s Performed a total of 0 changes. 178s 178s 2.13.5. Executing OPT_MERGE pass (detect identical cells). 178s Finding identical cells in module `\top'. 178s Removed a total of 0 cells. 178s 178s 2.13.6. Executing OPT_DFF pass (perform DFF optimizations). 178s 178s 2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). 178s Finding unused cells or wires in module \top.. 178s 178s 2.13.8. Executing OPT_EXPR pass (perform const folding). 178s Optimizing module top. 178s 178s 2.13.9. Finished OPT passes. (There is nothing left to do.) 178s 178s 2.14. Executing WREDUCE pass (reducing word size of cells). 178s Removed top 31 bits (of 32) from port B of cell top.$add$app0.v:12$382 ($add). 178s Removed top 10 bits (of 32) from port Y of cell top.$add$app0.v:12$382 ($add). 178s Removed top 3 bits (of 4) from port B of cell top.$add$app0.v:13$384 ($add). 178s Removed top 3 bits (of 4) from wire top.$logic_not$app0.v:13$383_Y. 178s 178s 2.15. Executing PEEPOPT pass (run peephole optimizers). 178s 178s 2.16. Executing OPT_CLEAN pass (remove unused cells and wires). 178s Finding unused cells or wires in module \top.. 178s Removed 0 unused cells and 2 unused wires. 178s 178s 178s 2.17. Executing SHARE pass (SAT-based resource sharing). 178s 178s 2.18. Executing TECHMAP pass (map to technology primitives). 178s 178s 2.18.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v 178s Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation. 178s Generating RTLIL representation for module `\_90_lut_cmp_'. 178s Successfully finished Verilog frontend. 178s 178s 2.18.2. Continuing TECHMAP pass. 178s No more expansions possible. 178s 178s 178s 2.19. Executing OPT_EXPR pass (perform const folding). 178s Optimizing module top. 178s 178s 2.20. Executing OPT_CLEAN pass (remove unused cells and wires). 178s Finding unused cells or wires in module \top.. 178s 178s 2.21. Executing ALUMACC pass (create $alu and $macc cells). 178s Extracting $alu and $macc cells in module top: 178s creating $macc model for $add$app0.v:12$382 ($add). 178s creating $macc model for $add$app0.v:13$384 ($add). 178s creating $alu model for $macc $add$app0.v:13$384. 178s creating $alu model for $macc $add$app0.v:12$382. 178s creating $alu cell for $add$app0.v:12$382: $auto$alumacc.cc:485:replace_alu$460 178s creating $alu cell for $add$app0.v:13$384: $auto$alumacc.cc:485:replace_alu$463 178s created 2 $alu and 0 $macc cells. 178s 178s 2.22. Executing OPT pass (performing simple optimizations). 178s 178s 2.22.1. Executing OPT_EXPR pass (perform const folding). 178s Optimizing module top. 178s 178s 2.22.2. Executing OPT_MERGE pass (detect identical cells). 178s Finding identical cells in module `\top'. 178s 178s Removed a total of 1 cells. 178s 178s 2.22.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 178s Running muxtree optimizer on module \top.. 178s Creating internal representation of mux trees. 178s No muxes found in this module. 178s Removed 0 multiplexer ports. 178s 178s 2.22.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 178s Optimizing cells in module \top. 178s Performed a total of 0 changes. 178s 178s 2.22.5. Executing OPT_MERGE pass (detect identical cells). 178s Finding identical cells in module `\top'. 178s Removed a total of 0 cells. 178s 178s 2.22.6. Executing OPT_DFF pass (perform DFF optimizations). 178s 178s 2.22.7. Executing OPT_CLEAN pass (remove unused cells and wires). 178s Finding unused cells or wires in module \top.. 178s Removed 0 unused cells and 1 unused wires. 178s 178s 178s 2.22.8. Executing OPT_EXPR pass (perform const folding). 178s Optimizing module top. 178s 178s 2.22.9. Rerunning OPT passes. (Maybe there is more to do..) 178s 178s 2.22.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 178s Running muxtree optimizer on module \top.. 178s Creating internal representation of mux trees. 178s No muxes found in this module. 178s Removed 0 multiplexer ports. 178s 178s 2.22.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 178s Optimizing cells in module \top. 178s Performed a total of 0 changes. 178s 178s 2.22.12. Executing OPT_MERGE pass (detect identical cells). 178s Finding identical cells in module `\top'. 178s Removed a total of 0 cells. 178s 178s 2.22.13. Executing OPT_DFF pass (perform DFF optimizations). 178s 178s 2.22.14. Executing OPT_CLEAN pass (remove unused cells and wires). 178s Finding unused cells or wires in module \top.. 178s 178s 2.22.15. Executing OPT_EXPR pass (perform const folding). 178s Optimizing module top. 178s 178s 2.22.16. Finished OPT passes. (There is nothing left to do.) 178s 178s 2.23. Executing MEMORY pass. 178s 178s 2.23.1. Executing OPT_MEM pass (optimize memories). 178s Performed a total of 0 transformations. 178s 178s 2.23.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). 178s Performed a total of 0 transformations. 178s 178s 2.23.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 178s 178s 2.23.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 178s 178s 2.23.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 178s 178s 2.23.6. Executing OPT_CLEAN pass (remove unused cells and wires). 178s Finding unused cells or wires in module \top.. 178s 178s 2.23.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 178s 178s 2.23.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). 178s Performed a total of 0 transformations. 178s 178s 2.23.9. Executing OPT_CLEAN pass (remove unused cells and wires). 178s Finding unused cells or wires in module \top.. 178s 178s 2.23.10. Executing MEMORY_COLLECT pass (generating $mem cells). 178s 178s 2.24. Executing OPT_CLEAN pass (remove unused cells and wires). 178s Finding unused cells or wires in module \top.. 178s 178s 2.25. Executing MEMORY_LIBMAP pass (mapping memories to cells). 178s 178s 2.26. Executing TECHMAP pass (map to technology primitives). 178s 178s 2.26.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v 179s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation. 179s Generating RTLIL representation for module `\$__ICE40_RAM4K_'. 179s Successfully finished Verilog frontend. 179s 179s 2.26.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/spram_map.v 179s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/spram_map.v' to AST representation. 179s Generating RTLIL representation for module `\$__ICE40_SPRAM_'. 179s Successfully finished Verilog frontend. 179s 179s 2.26.3. Continuing TECHMAP pass. 179s No more expansions possible. 179s 179s 179s 2.27. Executing ICE40_BRAMINIT pass. 179s 179s 2.28. Executing OPT pass (performing simple optimizations). 179s 179s 2.28.1. Executing OPT_EXPR pass (perform const folding). 179s Optimizing module top. 179s 179s 2.28.2. Executing OPT_MERGE pass (detect identical cells). 179s Finding identical cells in module `\top'. 179s Removed a total of 0 cells. 179s 179s 2.28.3. Executing OPT_DFF pass (perform DFF optimizations). 179s 179s 2.28.4. Executing OPT_CLEAN pass (remove unused cells and wires). 179s Finding unused cells or wires in module \top.. 179s 179s 2.28.5. Finished fast OPT passes. 179s 179s 2.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 179s 179s 2.30. Executing OPT pass (performing simple optimizations). 179s 179s 2.30.1. Executing OPT_EXPR pass (perform const folding). 179s Optimizing module top. 179s 179s 2.30.2. Executing OPT_MERGE pass (detect identical cells). 179s Finding identical cells in module `\top'. 179s Removed a total of 0 cells. 179s 179s 2.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 179s Running muxtree optimizer on module \top.. 179s Creating internal representation of mux trees. 179s No muxes found in this module. 179s Removed 0 multiplexer ports. 179s 179s 2.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 179s Optimizing cells in module \top. 179s Performed a total of 0 changes. 179s 179s 2.30.5. Executing OPT_MERGE pass (detect identical cells). 179s Finding identical cells in module `\top'. 179s Removed a total of 0 cells. 179s 179s 2.30.6. Executing OPT_DFF pass (perform DFF optimizations). 179s 179s 2.30.7. Executing OPT_CLEAN pass (remove unused cells and wires). 179s Finding unused cells or wires in module \top.. 179s 179s 2.30.8. Executing OPT_EXPR pass (perform const folding). 179s Optimizing module top. 179s 179s 2.30.9. Finished OPT passes. (There is nothing left to do.) 179s 179s 2.31. Executing ICE40_WRAPCARRY pass (wrap carries). 179s 179s 2.32. Executing TECHMAP pass (map to technology primitives). 179s 179s 2.32.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v 179s Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation. 179s Generating RTLIL representation for module `\_90_simplemap_bool_ops'. 179s Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. 179s Generating RTLIL representation for module `\_90_simplemap_logic_ops'. 179s Generating RTLIL representation for module `\_90_simplemap_compare_ops'. 179s Generating RTLIL representation for module `\_90_simplemap_various'. 179s Generating RTLIL representation for module `\_90_simplemap_registers'. 179s Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. 179s Generating RTLIL representation for module `\_90_shift_shiftx'. 179s Generating RTLIL representation for module `\_90_fa'. 179s Generating RTLIL representation for module `\_90_lcu'. 179s Generating RTLIL representation for module `\_90_alu'. 179s Generating RTLIL representation for module `\_90_macc'. 179s Generating RTLIL representation for module `\_90_alumacc'. 179s Generating RTLIL representation for module `\$__div_mod_u'. 179s Generating RTLIL representation for module `\$__div_mod_trunc'. 179s Generating RTLIL representation for module `\_90_div'. 179s Generating RTLIL representation for module `\_90_mod'. 179s Generating RTLIL representation for module `\$__div_mod_floor'. 179s Generating RTLIL representation for module `\_90_divfloor'. 179s Generating RTLIL representation for module `\_90_modfloor'. 179s Generating RTLIL representation for module `\_90_pow'. 179s Generating RTLIL representation for module `\_90_pmux'. 179s Generating RTLIL representation for module `\_90_demux'. 179s Generating RTLIL representation for module `\_90_lut'. 179s Successfully finished Verilog frontend. 179s 179s 2.32.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v 179s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation. 179s Generating RTLIL representation for module `\_80_ice40_alu'. 179s Successfully finished Verilog frontend. 179s 179s 2.32.3. Continuing TECHMAP pass. 179s Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_80_ice40_alu for cells of type $alu. 179s Using extmapper simplemap for cells of type $logic_not. 179s Using template $paramod$080e6a70eb8bfa1ccf22d9718e795074645029a4\_80_ice40_alu for cells of type $alu. 179s Using extmapper simplemap for cells of type $xor. 179s Using extmapper simplemap for cells of type $reduce_and. 179s Using extmapper simplemap for cells of type $dff. 179s Using extmapper simplemap for cells of type $mux. 179s Using extmapper simplemap for cells of type $not. 179s Using extmapper simplemap for cells of type $pos. 179s No more expansions possible. 179s 179s 179s 2.33. Executing OPT pass (performing simple optimizations). 179s 179s 2.33.1. Executing OPT_EXPR pass (perform const folding). 179s Optimizing module top. 179s 179s 179s 2.33.2. Executing OPT_MERGE pass (detect identical cells). 179s Finding identical cells in module `\top'. 179s 179s Removed a total of 1 cells. 179s 179s 2.33.3. Executing OPT_DFF pass (perform DFF optimizations). 179s 179s 2.33.4. Executing OPT_CLEAN pass (remove unused cells and wires). 179s Finding unused cells or wires in module \top.. 179s Removed 27 unused cells and 34 unused wires. 179s 179s 179s 2.33.5. Finished fast OPT passes. 179s 179s 2.34. Executing ICE40_OPT pass (performing simple optimizations). 179s 179s 2.34.1. Running ICE40 specific optimizations. 179s Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$460.slice[0].carry: CO=\counter [0] 179s 179s 2.34.2. Executing OPT_EXPR pass (perform const folding). 179s Optimizing module top. 179s 179s 2.34.3. Executing OPT_MERGE pass (detect identical cells). 179s Finding identical cells in module `\top'. 179s Removed a total of 0 cells. 179s 179s 2.34.4. Executing OPT_DFF pass (perform DFF optimizations). 179s 179s 2.34.5. Executing OPT_CLEAN pass (remove unused cells and wires). 179s Finding unused cells or wires in module \top.. 179s 179s 2.34.6. Rerunning OPT passes. (Removed registers in this run.) 179s 179s 2.34.7. Running ICE40 specific optimizations. 179s 179s 2.34.8. Executing OPT_EXPR pass (perform const folding). 179s Optimizing module top. 179s 179s 2.34.9. Executing OPT_MERGE pass (detect identical cells). 179s Finding identical cells in module `\top'. 179s Removed a total of 0 cells. 179s 179s 2.34.10. Executing OPT_DFF pass (perform DFF optimizations). 179s 179s 2.34.11. Executing OPT_CLEAN pass (remove unused cells and wires). 179s Finding unused cells or wires in module \top.. 179s 179s 2.34.12. Finished OPT passes. (There is nothing left to do.) 179s 179s 2.35. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 179s 179s 2.36. Executing TECHMAP pass (map to technology primitives). 179s 179s 2.36.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 179s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 179s Generating RTLIL representation for module `\$_DFF_N_'. 179s Generating RTLIL representation for module `\$_DFF_P_'. 179s Generating RTLIL representation for module `\$_DFFE_NP_'. 179s Generating RTLIL representation for module `\$_DFFE_PP_'. 179s Generating RTLIL representation for module `\$_DFF_NP0_'. 179s Generating RTLIL representation for module `\$_DFF_NP1_'. 179s Generating RTLIL representation for module `\$_DFF_PP0_'. 179s Generating RTLIL representation for module `\$_DFF_PP1_'. 179s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 179s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 179s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 179s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 179s Generating RTLIL representation for module `\$_SDFF_NP0_'. 179s Generating RTLIL representation for module `\$_SDFF_NP1_'. 179s Generating RTLIL representation for module `\$_SDFF_PP0_'. 179s Generating RTLIL representation for module `\$_SDFF_PP1_'. 179s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 179s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 179s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 179s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 179s Successfully finished Verilog frontend. 179s 179s 2.36.2. Continuing TECHMAP pass. 179s Using template \$_DFF_P_ for cells of type $_DFF_P_. 179s No more expansions possible. 179s 179s 179s 2.37. Executing OPT_EXPR pass (perform const folding). 179s Optimizing module top. 179s 179s 2.38. Executing SIMPLEMAP pass (map simple cells to gate primitives). 179s Mapping top.$auto$alumacc.cc:485:replace_alu$460.slice[0].carry ($lut). 179s 179s 2.39. Executing ICE40_OPT pass (performing simple optimizations). 179s 179s 2.39.1. Running ICE40 specific optimizations. 179s 179s 2.39.2. Executing OPT_EXPR pass (perform const folding). 179s Optimizing module top. 179s 179s 179s 2.39.3. Executing OPT_MERGE pass (detect identical cells). 179s Finding identical cells in module `\top'. 179s Removed a total of 0 cells. 179s 179s 2.39.4. Executing OPT_DFF pass (perform DFF optimizations). 179s 179s 2.39.5. Executing OPT_CLEAN pass (remove unused cells and wires). 179s Finding unused cells or wires in module \top.. 179s Removed 0 unused cells and 112 unused wires. 179s 179s 179s 2.39.6. Rerunning OPT passes. (Removed registers in this run.) 179s 179s 2.39.7. Running ICE40 specific optimizations. 179s 179s 2.39.8. Executing OPT_EXPR pass (perform const folding). 179s Optimizing module top. 179s 179s 2.39.9. Executing OPT_MERGE pass (detect identical cells). 179s Finding identical cells in module `\top'. 179s Removed a total of 0 cells. 179s 179s 2.39.10. Executing OPT_DFF pass (perform DFF optimizations). 179s 179s 2.39.11. Executing OPT_CLEAN pass (remove unused cells and wires). 179s Finding unused cells or wires in module \top.. 179s 179s 2.39.12. Finished OPT passes. (There is nothing left to do.) 179s 179s 2.40. Executing TECHMAP pass (map to technology primitives). 179s 179s 2.40.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v 179s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation. 179s Generating RTLIL representation for module `\$_DLATCH_N_'. 179s Generating RTLIL representation for module `\$_DLATCH_P_'. 179s Successfully finished Verilog frontend. 179s 179s 2.40.2. Continuing TECHMAP pass. 179s No more expansions possible. 179s 179s 179s 2.41. Executing ABC pass (technology mapping using ABC). 179s 179s 2.41.1. Extracting gate netlist of module `\top' to `/input.blif'.. 179s Extracted 27 gates and 54 wires to a netlist network with 27 inputs and 4 outputs. 179s 179s 2.41.1.1. Executing ABC. 179s Running ABC command: "berkeley-abc" -s -f /abc.script 2>&1 179s ABC: ABC command line: "source /abc.script". 179s ABC: 179s ABC: + read_blif /input.blif 179s ABC: + read_lut /lutdefs.txt 179s ABC: + strash 179s ABC: + &get -n 179s ABC: + &fraig -x 179s ABC: + &put 179s ABC: + scorr 179s ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). 179s ABC: + dc2 179s ABC: + dretime 179s ABC: + strash 179s ABC: + dch -f 179s ABC: + if 179s ABC: + mfs2 179s ABC: + lutpack -S 1 179s ABC: + dress /input.blif 179s ABC: Total number of equiv classes = 5. 179s ABC: Participating nodes from both networks = 9. 179s ABC: Participating nodes from the first network = 4. ( 30.77 % of nodes) 179s ABC: Participating nodes from the second network = 5. ( 38.46 % of nodes) 179s ABC: Node pairs (any polarity) = 4. ( 30.77 % of names can be moved) 179s ABC: Node pairs (same polarity) = 4. ( 30.77 % of names can be moved) 179s ABC: Total runtime = 0.08 sec 179s ABC: + write_blif /output.blif 179s 179s 2.41.1.2. Re-integrating ABC results. 179s ABC RESULTS: $lut cells: 12 179s ABC RESULTS: internal signals: 23 179s ABC RESULTS: input signals: 27 179s ABC RESULTS: output signals: 4 179s Removing temp directory. 179s 179s 2.42. Executing ICE40_WRAPCARRY pass (wrap carries). 179s 179s 2.43. Executing TECHMAP pass (map to technology primitives). 179s 179s 2.43.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 179s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 179s Generating RTLIL representation for module `\$_DFF_N_'. 179s Generating RTLIL representation for module `\$_DFF_P_'. 179s Generating RTLIL representation for module `\$_DFFE_NP_'. 179s Generating RTLIL representation for module `\$_DFFE_PP_'. 179s Generating RTLIL representation for module `\$_DFF_NP0_'. 179s Generating RTLIL representation for module `\$_DFF_NP1_'. 179s Generating RTLIL representation for module `\$_DFF_PP0_'. 179s Generating RTLIL representation for module `\$_DFF_PP1_'. 179s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 179s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 179s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 179s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 179s Generating RTLIL representation for module `\$_SDFF_NP0_'. 179s Generating RTLIL representation for module `\$_SDFF_NP1_'. 179s Generating RTLIL representation for module `\$_SDFF_PP0_'. 179s Generating RTLIL representation for module `\$_SDFF_PP1_'. 179s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 179s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 179s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 179s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 179s Successfully finished Verilog frontend. 179s 179s 2.43.2. Continuing TECHMAP pass. 179s No more expansions possible. 179s 179s Removed 2 unused cells and 39 unused wires. 179s 179s 2.44. Executing OPT_LUT pass (optimize LUTs). 179s Discovering LUTs. 179s Number of LUTs: 37 179s 1-LUT 1 179s 2-LUT 4 179s 3-LUT 25 179s 4-LUT 7 179s with \SB_CARRY (#0) 23 179s with \SB_CARRY (#1) 23 179s 179s Eliminating LUTs. 179s Number of LUTs: 37 179s 1-LUT 1 179s 2-LUT 4 179s 3-LUT 25 179s 4-LUT 7 179s with \SB_CARRY (#0) 23 179s with \SB_CARRY (#1) 23 179s 179s Combining LUTs. 179s Number of LUTs: 37 179s 1-LUT 1 179s 2-LUT 4 179s 3-LUT 25 179s 4-LUT 7 179s with \SB_CARRY (#0) 23 179s with \SB_CARRY (#1) 23 179s 179s Eliminated 0 LUTs. 179s Combined 0 LUTs. 179s 179s 179s 2.45. Executing TECHMAP pass (map to technology primitives). 179s 179s 2.45.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v 179s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation. 179s Generating RTLIL representation for module `\$lut'. 179s Successfully finished Verilog frontend. 179s 179s 2.45.2. Continuing TECHMAP pass. 179s Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut. 179s Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut. 179s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut. 179s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. 179s Using template $paramod$415b9dd3a15783ae56c103f189fd8e182f997441\$lut for cells of type $lut. 179s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. 179s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. 179s Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut. 179s No more expansions possible. 179s 179s Removed 0 unused cells and 78 unused wires. 179s 179s 2.46. Executing AUTONAME pass. 179s Renamed 463 objects in module top (10 iterations). 179s 179s 179s 2.47. Executing HIERARCHY pass (managing design hierarchy). 179s 179s 2.47.1. Analyzing design hierarchy.. 179s Top module: \top 179s 179s 2.47.2. Analyzing design hierarchy.. 179s Top module: \top 179s Removed 0 unused modules. 179s 179s 2.48. Printing statistics. 179s 179s === top === 179s 179s Number of wires: 20 179s Number of wire bits: 99 179s Number of public wires: 20 179s Number of public wire bits: 99 179s Number of memories: 0 179s Number of memory bits: 0 179s Number of processes: 0 179s Number of cells: 88 179s SB_CARRY 23 179s SB_DFF 27 179s SB_LUT4 37 179s SB_WARMBOOT 1 179s 179s 2.49. Executing CHECK pass (checking for obvious problems). 179s Checking module top... 179s Found and reported 0 problems. 179s 179s 2.50. Executing JSON backend. 179s 179s End of script. Logfile hash: 61b78d00a9, CPU: user 1.00s system 0.02s, MEM: 22.00 MB peak 179s Yosys 0.23 (git sha1 7ce5011c24b) 179s Time spent: 60% 13x read_verilog (0 sec), 13% 1x abc (0 sec), ... 179s nextpnr-ice40 --hx1k --package tq144 --asc app0.asc --pcf icestick.pcf --json app0.json 179s Warning: unmatched constraint 'RX' (on line 4) 179s Warning: unmatched constraint 'TX' (on line 5) 179s Info: constrained 'LED1' to bel 'X13/Y12/io1' 179s Info: constrained 'LED2' to bel 'X13/Y12/io0' 179s Info: constrained 'LED3' to bel 'X13/Y11/io1' 179s Info: constrained 'LED4' to bel 'X13/Y11/io0' 179s Info: constrained 'LED5' to bel 'X13/Y9/io1' 179s Info: constrained 'clk' to bel 'X0/Y8/io1' 179s 179s Info: Packing constants.. 179s Info: Packing IOs.. 179s Info: Packing LUT-FFs.. 179s Info: 10 LCs used as LUT4 only 179s Info: 27 LCs used as LUT4 and DFF 179s Info: Packing non-LUT FFs.. 179s Info: 0 LCs used as DFF only 179s Info: Packing carries.. 179s Info: 0 LCs used as CARRY only 179s Info: Packing indirect carry+LUT pairs... 179s Info: 0 LUTs merged into carry LCs 179s Info: Packing RAMs.. 179s Info: Placing PLLs.. 179s Info: Packing special functions.. 179s Info: Packing PLLs.. 179s Info: Promoting globals.. 179s Info: promoting clk$SB_IO_IN (fanout 27) 179s Info: Constraining chains... 179s Info: 1 LCs used to legalise carry chains. 179s Info: Checksum: 0x431c6341 179s 179s Info: Annotating ports with timing budgets for target frequency 12.00 MHz 179s Info: Checksum: 0x82f7d2ce 179s 179s Info: Device utilisation: 179s Info: ICESTORM_LC: 40/ 1280 3% 179s Info: ICESTORM_RAM: 0/ 16 0% 179s Info: SB_IO: 6/ 112 5% 179s Info: SB_GB: 1/ 8 12% 179s Info: ICESTORM_PLL: 0/ 1 0% 179s Info: SB_WARMBOOT: 1/ 1 100% 179s 179s Info: Placed 6 cells based on constraints. 179s Info: Creating initial analytic placement for 18 cells, random placement wirelen = 358. 179s Info: at initial placer iter 0, wirelen = 17 179s Info: at initial placer iter 1, wirelen = 14 179s Info: at initial placer iter 2, wirelen = 14 179s Info: at initial placer iter 3, wirelen = 14 179s Info: Running main analytical placer, max placement attempts per cell = 10000. 179s Info: at iteration #1, type ICESTORM_LC: wirelen solved = 16, spread = 61, legal = 87; time = 0.00s 179s Info: at iteration #1, type SB_GB: wirelen solved = 87, spread = 87, legal = 87; time = 0.00s 179s Info: at iteration #1, type SB_WARMBOOT: wirelen solved = 87, spread = 87, legal = 147; time = 0.00s 179s Info: at iteration #1, type ALL: wirelen solved = 28, spread = 75, legal = 119; time = 0.00s 179s Info: at iteration #2, type ICESTORM_LC: wirelen solved = 86, spread = 140, legal = 173; time = 0.00s 179s Info: at iteration #2, type SB_GB: wirelen solved = 173, spread = 173, legal = 173; time = 0.00s 179s Info: at iteration #2, type SB_WARMBOOT: wirelen solved = 121, spread = 121, legal = 173; time = 0.00s 179s Info: at iteration #2, type ALL: wirelen solved = 19, spread = 73, legal = 135; time = 0.00s 179s Info: at iteration #3, type ICESTORM_LC: wirelen solved = 84, spread = 131, legal = 149; time = 0.00s 179s Info: at iteration #3, type SB_GB: wirelen solved = 149, spread = 149, legal = 149; time = 0.00s 179s Info: at iteration #3, type SB_WARMBOOT: wirelen solved = 93, spread = 93, legal = 149; time = 0.00s 179s Info: at iteration #3, type ALL: wirelen solved = 20, spread = 78, legal = 140; time = 0.00s 179s Info: at iteration #4, type ICESTORM_LC: wirelen solved = 86, spread = 141, legal = 146; time = 0.00s 179s Info: at iteration #4, type SB_GB: wirelen solved = 146, spread = 146, legal = 146; time = 0.00s 179s Info: at iteration #4, type SB_WARMBOOT: wirelen solved = 88, spread = 88, legal = 146; time = 0.00s 179s Info: at iteration #4, type ALL: wirelen solved = 20, spread = 78, legal = 140; time = 0.00s 179s Info: at iteration #5, type ICESTORM_LC: wirelen solved = 83, spread = 138, legal = 146; time = 0.00s 179s Info: at iteration #5, type SB_GB: wirelen solved = 146, spread = 146, legal = 146; time = 0.00s 179s Info: at iteration #5, type SB_WARMBOOT: wirelen solved = 87, spread = 87, legal = 146; time = 0.00s 179s Info: at iteration #5, type ALL: wirelen solved = 26, spread = 78, legal = 140; time = 0.00s 179s Info: at iteration #6, type ICESTORM_LC: wirelen solved = 85, spread = 138, legal = 141; time = 0.00s 179s Info: at iteration #6, type SB_GB: wirelen solved = 141, spread = 141, legal = 141; time = 0.00s 179s Info: at iteration #6, type SB_WARMBOOT: wirelen solved = 82, spread = 82, legal = 141; time = 0.00s 179s Info: at iteration #6, type ALL: wirelen solved = 27, spread = 78, legal = 140; time = 0.00s 179s Info: HeAP Placer Time: 0.02s 179s Info: of which solving equations: 0.01s 179s Info: of which spreading cells: 0.00s 179s Info: of which strict legalisation: 0.00s 179s 179s Info: Running simulated annealing placer for refinement. 179s Info: at iteration #1: temp = 0.000000, timing cost = 20, wirelen = 119 179s Info: at iteration #5: temp = 0.000000, timing cost = 12, wirelen = 107 179s Info: at iteration #6: temp = 0.000000, timing cost = 12, wirelen = 107 179s Info: SA placement time 0.01s 179s 179s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 172.89 MHz (PASS at 12.00 MHz) 179s 179s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> : 4.14 ns 179s 179s Info: Slack histogram: 179s Info: legend: * represents 1 endpoint(s) 179s Info: + represents [1,1) endpoint(s) 179s Info: [ 77549, 77766) |** 179s Info: [ 77766, 77983) |* 179s Info: [ 77983, 78200) | 179s Info: [ 78200, 78417) |** 179s Info: [ 78417, 78634) |** 179s Info: [ 78634, 78851) |** 179s Info: [ 78851, 79068) |* 179s Info: [ 79068, 79285) |*** 179s Info: [ 79285, 79502) |** 179s Info: [ 79502, 79719) |** 179s Info: [ 79719, 79936) |** 179s Info: [ 79936, 80153) |** 179s Info: [ 80153, 80370) |* 179s Info: [ 80370, 80587) | 179s Info: [ 80587, 80804) |** 179s Info: [ 80804, 81021) |** 179s Info: [ 81021, 81238) |** 179s Info: [ 81238, 81455) | 179s Info: [ 81455, 81672) |* 179s Info: [ 81672, 81889) |**************************** 179s Info: Checksum: 0xf7071520 179s 179s Info: Routing.. 179s Info: Setting up routing queue. 179s Info: Routing 127 arcs. 179s Info: | (re-)routed arcs | delta | remaining| time spent | 179s Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| 179s Info: 128 | 1 107 | 1 107 | 0| 0.01 0.01| 179s Info: Routing complete. 179s Info: Router1 time 0.01s 179s Info: Checksum: 0x443c7f0b 179s 179s Info: Critical path report for clock 'clk$SB_IO_IN_$glb_clk' (posedge -> posedge): 179s Info: curr total 179s Info: 0.5 0.5 Source counter_SB_LUT4_I2_7_LC.O 179s Info: 0.6 1.1 Net counter[2] budget 20.292999 ns (12,10) -> (11,10) 179s Info: Sink state_SB_LUT4_I3_I0_SB_LUT4_O_2_I3_SB_LUT4_O_LC.I0 179s Info: Defined in: 179s Info: app0.v:7.22-7.29 179s Info: 0.4 1.6 Source state_SB_LUT4_I3_I0_SB_LUT4_O_2_I3_SB_LUT4_O_LC.O 179s Info: 0.6 2.2 Net state_SB_LUT4_I3_I0_SB_LUT4_O_2_I3[2] budget 20.292999 ns (11,10) -> (11,10) 179s Info: Sink state_SB_LUT4_I3_I0_SB_LUT4_O_2_LC.I3 179s Info: Defined in: 179s Info: /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 179s Info: 0.3 2.5 Source state_SB_LUT4_I3_I0_SB_LUT4_O_2_LC.O 179s Info: 1.0 3.4 Net state_SB_LUT4_I3_I0[0] budget 20.292000 ns (11,10) -> (11,13) 179s Info: Sink counter2_SB_LUT4_I2_3_I1_SB_LUT4_O_LC.I1 179s Info: Defined in: 179s Info: /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 179s Info: 0.4 3.8 Source counter2_SB_LUT4_I2_3_I1_SB_LUT4_O_LC.O 179s Info: 0.6 4.4 Net counter2_SB_LUT4_I2_3_I1 budget 20.292000 ns (11,13) -> (11,12) 179s Info: Sink counter2_SB_LUT4_I2_3_LC.I1 179s Info: Defined in: 179s Info: app0.v:13.15-13.34 179s Info: /usr/bin/../share/yosys/ice40/arith_map.v:29.22-29.23 179s Info: 0.3 4.7 Source counter2_SB_LUT4_I2_3_LC.COUT 179s Info: 0.0 4.7 Net counter2_SB_CARRY_I1_CO[1] budget 0.000000 ns (11,12) -> (11,12) 179s Info: Sink counter2_SB_LUT4_I2_2_LC.CIN 179s Info: Defined in: 179s Info: app0.v:13.15-13.34 179s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 179s Info: 0.1 4.8 Source counter2_SB_LUT4_I2_2_LC.COUT 179s Info: 0.0 4.8 Net counter2_SB_CARRY_I1_CO[2] budget 0.000000 ns (11,12) -> (11,12) 179s Info: Sink counter2_SB_LUT4_I2_1_LC.CIN 179s Info: Defined in: 179s Info: app0.v:13.15-13.34 179s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 179s Info: 0.1 4.9 Source counter2_SB_LUT4_I2_1_LC.COUT 179s Info: 0.3 5.2 Net counter2_SB_CARRY_I1_CO[3] budget 0.260000 ns (11,12) -> (11,12) 179s Info: Sink counter2_SB_LUT4_I2_LC.I3 179s Info: Defined in: 179s Info: app0.v:13.15-13.34 179s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 179s Info: 0.3 5.5 Setup counter2_SB_LUT4_I2_LC.I3 179s Info: 2.5 ns logic, 3.0 ns routing 179s 179s Info: Critical path report for cross-domain path 'posedge clk$SB_IO_IN_$glb_clk' -> '': 179s Info: curr total 179s Info: 0.5 0.5 Source counter2_SB_LUT4_I2_3_LC.O 179s Info: 0.6 1.1 Net counter2[0] budget 41.173000 ns (11,12) -> (11,12) 179s Info: Sink WB_BOOT_SB_LUT4_O_LC.I0 179s Info: Defined in: 179s Info: app0.v:8.12-8.20 179s Info: 0.4 1.6 Source WB_BOOT_SB_LUT4_O_LC.O 179s Info: 1.8 3.4 Net WB_BOOT budget 41.172001 ns (11,12) -> (0,0) 179s Info: Sink WB.BOOT 179s Info: Defined in: 179s Info: app0.v:24.9-24.18 179s Info: 1.0 ns logic, 2.4 ns routing 179s 179s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 180.80 MHz (PASS at 12.00 MHz) 179s 179s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> : 3.39 ns 179s 179s Info: Slack histogram: 179s Info: legend: * represents 1 endpoint(s) 179s Info: + represents [1,1) endpoint(s) 179s Info: [ 77802, 78006) |** 179s Info: [ 78006, 78210) |* 179s Info: [ 78210, 78414) | 179s Info: [ 78414, 78618) |*** 179s Info: [ 78618, 78822) |** 179s Info: [ 78822, 79026) |** 179s Info: [ 79026, 79230) | 179s Info: [ 79230, 79434) |** 179s Info: [ 79434, 79638) |** 179s Info: [ 79638, 79842) |*** 179s Info: [ 79842, 80046) |*** 179s Info: [ 80046, 80250) |** 179s Info: [ 80250, 80454) | 179s Info: [ 80454, 80658) |* 179s Info: [ 80658, 80862) |** 179s Info: [ 80862, 81066) |* 179s Info: [ 81066, 81270) |** 179s Info: [ 81270, 81474) | 179s Info: [ 81474, 81678) |* 179s Info: [ 81678, 81882) |**************************** 179s 2 warnings, 0 errors 179s 179s Info: Program finished normally. 179s icetime -d hx1k -c 25 app0.asc 179s // Reading input .asc file.. 179s // Reading 1k chipdb file.. 179s // Creating timing netlist.. 179s // Timing estimate: 5.54 ns (180.65 MHz) 179s // Checking 40.00 ns (25.00 MHz) clock constraint: PASSED. 179s icepack app0.asc app0.bin 180s yosys -p "synth_ice40 -top top -json app1.json" app1.v 180s 180s /----------------------------------------------------------------------------\ 180s | | 180s | yosys -- Yosys Open SYnthesis Suite | 180s | | 180s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 180s | | 180s | Permission to use, copy, modify, and/or distribute this software for any | 180s | purpose with or without fee is hereby granted, provided that the above | 180s | copyright notice and this permission notice appear in all copies. | 180s | | 180s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 180s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 180s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 180s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 180s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 180s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 180s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 180s | | 180s \----------------------------------------------------------------------------/ 180s 180s Yosys 0.23 (git sha1 7ce5011c24b) 180s 180s 180s -- Parsing `app1.v' using frontend ` -vlog2k' -- 180s 180s 1. Executing Verilog-2005 frontend: app1.v 180s Parsing Verilog input from `app1.v' to AST representation. 180s Storing AST representation for module `$abstract\top'. 180s Successfully finished Verilog frontend. 180s 180s -- Running command `synth_ice40 -top top -json app1.json' -- 180s 180s 2. Executing SYNTH_ICE40 pass. 180s 180s 2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v 180s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation. 180s Generating RTLIL representation for module `\SB_IO'. 180s Generating RTLIL representation for module `\SB_GB_IO'. 180s Generating RTLIL representation for module `\SB_GB'. 180s Generating RTLIL representation for module `\SB_LUT4'. 180s Generating RTLIL representation for module `\SB_CARRY'. 180s Generating RTLIL representation for module `\SB_DFF'. 180s Generating RTLIL representation for module `\SB_DFFE'. 180s Generating RTLIL representation for module `\SB_DFFSR'. 180s Generating RTLIL representation for module `\SB_DFFR'. 180s Generating RTLIL representation for module `\SB_DFFSS'. 180s Generating RTLIL representation for module `\SB_DFFS'. 180s Generating RTLIL representation for module `\SB_DFFESR'. 180s Generating RTLIL representation for module `\SB_DFFER'. 180s Generating RTLIL representation for module `\SB_DFFESS'. 180s Generating RTLIL representation for module `\SB_DFFES'. 180s Generating RTLIL representation for module `\SB_DFFN'. 180s Generating RTLIL representation for module `\SB_DFFNE'. 180s Generating RTLIL representation for module `\SB_DFFNSR'. 180s Generating RTLIL representation for module `\SB_DFFNR'. 180s Generating RTLIL representation for module `\SB_DFFNSS'. 180s Generating RTLIL representation for module `\SB_DFFNS'. 180s Generating RTLIL representation for module `\SB_DFFNESR'. 180s Generating RTLIL representation for module `\SB_DFFNER'. 180s Generating RTLIL representation for module `\SB_DFFNESS'. 180s Generating RTLIL representation for module `\SB_DFFNES'. 180s Generating RTLIL representation for module `\SB_RAM40_4K'. 180s Generating RTLIL representation for module `\SB_RAM40_4KNR'. 180s Generating RTLIL representation for module `\SB_RAM40_4KNW'. 180s Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. 180s Generating RTLIL representation for module `\ICESTORM_LC'. 180s Generating RTLIL representation for module `\SB_PLL40_CORE'. 180s Generating RTLIL representation for module `\SB_PLL40_PAD'. 180s Generating RTLIL representation for module `\SB_PLL40_2_PAD'. 180s Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. 180s Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. 180s Generating RTLIL representation for module `\SB_WARMBOOT'. 180s Generating RTLIL representation for module `\SB_SPRAM256KA'. 180s Generating RTLIL representation for module `\SB_HFOSC'. 180s Generating RTLIL representation for module `\SB_LFOSC'. 180s Generating RTLIL representation for module `\SB_RGBA_DRV'. 180s Generating RTLIL representation for module `\SB_LED_DRV_CUR'. 180s Generating RTLIL representation for module `\SB_RGB_DRV'. 180s Generating RTLIL representation for module `\SB_I2C'. 180s Generating RTLIL representation for module `\SB_SPI'. 180s Generating RTLIL representation for module `\SB_LEDDA_IP'. 180s Generating RTLIL representation for module `\SB_FILTER_50NS'. 180s Generating RTLIL representation for module `\SB_IO_I3C'. 180s Generating RTLIL representation for module `\SB_IO_OD'. 180s Generating RTLIL representation for module `\SB_MAC16'. 180s Generating RTLIL representation for module `\ICESTORM_RAM'. 180s Successfully finished Verilog frontend. 180s 180s 2.2. Executing HIERARCHY pass (managing design hierarchy). 180s 180s 2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\top'. 180s Generating RTLIL representation for module `\top'. 180s 180s 2.3.1. Analyzing design hierarchy.. 180s Top module: \top 180s 180s 2.3.2. Analyzing design hierarchy.. 180s Top module: \top 180s Removing unused module `$abstract\top'. 180s Removed 1 unused modules. 180s 180s 2.4. Executing PROC pass (convert processes to netlists). 180s 180s 2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 180s Cleaned up 0 empty switches. 180s 180s 2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 180s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241 in module SB_DFFNES. 180s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234 in module SB_DFFNESS. 180s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230 in module SB_DFFNER. 180s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223 in module SB_DFFNESR. 180s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220 in module SB_DFFNS. 180s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217 in module SB_DFFNSS. 180s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214 in module SB_DFFNR. 180s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211 in module SB_DFFNSR. 180s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203 in module SB_DFFES. 180s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196 in module SB_DFFESS. 180s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192 in module SB_DFFER. 180s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185 in module SB_DFFESR. 180s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182 in module SB_DFFS. 180s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179 in module SB_DFFSS. 180s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176 in module SB_DFFR. 180s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173 in module SB_DFFSR. 180s Removed a total of 0 dead cases. 180s 180s 2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 180s Removed 8 redundant assignments. 180s Promoted 28 assignments to connections. 180s 180s 2.4.4. Executing PROC_INIT pass (extract init attributes). 180s Found init rule in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 180s Set init value: \Q = 1'0 180s Found init rule in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 180s Set init value: \Q = 1'0 180s Found init rule in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 180s Set init value: \Q = 1'0 180s Found init rule in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 180s Set init value: \Q = 1'0 180s Found init rule in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 180s Set init value: \Q = 1'0 180s Found init rule in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 180s Set init value: \Q = 1'0 180s Found init rule in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 180s Set init value: \Q = 1'0 180s Found init rule in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 180s Set init value: \Q = 1'0 180s Found init rule in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 180s Set init value: \Q = 1'0 180s Found init rule in `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 180s Set init value: \Q = 1'0 180s Found init rule in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 180s Set init value: \Q = 1'0 180s Found init rule in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 180s Set init value: \Q = 1'0 180s Found init rule in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 180s Set init value: \Q = 1'0 180s Found init rule in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 180s Set init value: \Q = 1'0 180s Found init rule in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 180s Set init value: \Q = 1'0 180s Found init rule in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 180s Set init value: \Q = 1'0 180s Found init rule in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 180s Set init value: \Q = 1'0 180s Found init rule in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 180s Set init value: \Q = 1'0 180s Found init rule in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 180s Set init value: \Q = 1'0 180s Found init rule in `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 180s Set init value: \Q = 1'0 180s Found init rule in `\top.$proc$app1.v:9$390'. 180s Set init value: \state = 1'0 180s Found init rule in `\top.$proc$app1.v:8$389'. 180s Set init value: \counter2 = 4'0000 180s Found init rule in `\top.$proc$app1.v:7$388'. 180s Set init value: \counter = 22'0000000000000000000000 180s 180s 2.4.5. Executing PROC_ARST pass (detect async resets in processes). 180s Found async reset \S in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 180s Found async reset \R in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 180s Found async reset \S in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 180s Found async reset \R in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 180s Found async reset \S in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 180s Found async reset \R in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 180s Found async reset \S in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 180s Found async reset \R in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 180s 180s 2.4.6. Executing PROC_ROM pass (convert switches to ROMs). 180s Converted 0 switches. 180s 180s 180s 2.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 180s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 180s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 180s 1/1: $0\Q[0:0] 180s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 180s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 180s 1/1: $0\Q[0:0] 180s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 180s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 180s 1/1: $0\Q[0:0] 180s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 180s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 180s 1/1: $0\Q[0:0] 180s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 180s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 180s 1/1: $0\Q[0:0] 180s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 180s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 180s 1/1: $0\Q[0:0] 180s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 180s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 180s 1/1: $0\Q[0:0] 180s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 180s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 180s 1/1: $0\Q[0:0] 180s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 180s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 180s 1/1: $0\Q[0:0] 180s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 180s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 180s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 180s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 180s 1/1: $0\Q[0:0] 180s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 180s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 180s 1/1: $0\Q[0:0] 180s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 180s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 180s 1/1: $0\Q[0:0] 180s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 180s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 180s 1/1: $0\Q[0:0] 180s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 180s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 180s 1/1: $0\Q[0:0] 180s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 180s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 180s 1/1: $0\Q[0:0] 180s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 180s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 180s 1/1: $0\Q[0:0] 180s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 180s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 180s 1/1: $0\Q[0:0] 180s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 180s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 180s 1/1: $0\Q[0:0] 180s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 180s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 180s Creating decoders for process `\top.$proc$app1.v:9$390'. 180s Creating decoders for process `\top.$proc$app1.v:8$389'. 180s Creating decoders for process `\top.$proc$app1.v:7$388'. 180s Creating decoders for process `\top.$proc$app1.v:11$381'. 180s 180s 2.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). 180s 180s 2.4.9. Executing PROC_DFF pass (convert process syncs to FFs). 180s Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 180s created $adff cell `$procdff$435' with negative edge clock and positive level reset. 180s Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 180s created $dff cell `$procdff$436' with negative edge clock. 180s Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 180s created $adff cell `$procdff$437' with negative edge clock and positive level reset. 180s Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 180s created $dff cell `$procdff$438' with negative edge clock. 180s Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 180s created $adff cell `$procdff$439' with negative edge clock and positive level reset. 180s Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 180s created $dff cell `$procdff$440' with negative edge clock. 180s Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 180s created $adff cell `$procdff$441' with negative edge clock and positive level reset. 180s Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 180s created $dff cell `$procdff$442' with negative edge clock. 180s Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 180s created $dff cell `$procdff$443' with negative edge clock. 180s Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 180s created $dff cell `$procdff$444' with negative edge clock. 180s Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 180s created $adff cell `$procdff$445' with positive edge clock and positive level reset. 180s Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 180s created $dff cell `$procdff$446' with positive edge clock. 180s Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 180s created $adff cell `$procdff$447' with positive edge clock and positive level reset. 180s Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 180s created $dff cell `$procdff$448' with positive edge clock. 180s Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 180s created $adff cell `$procdff$449' with positive edge clock and positive level reset. 180s Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 180s created $dff cell `$procdff$450' with positive edge clock. 180s Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 180s created $adff cell `$procdff$451' with positive edge clock and positive level reset. 180s Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 180s created $dff cell `$procdff$452' with positive edge clock. 180s Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 180s created $dff cell `$procdff$453' with positive edge clock. 180s Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 180s created $dff cell `$procdff$454' with positive edge clock. 180s Creating register for signal `\top.\counter' using process `\top.$proc$app1.v:11$381'. 180s created $dff cell `$procdff$455' with positive edge clock. 180s Creating register for signal `\top.\counter2' using process `\top.$proc$app1.v:11$381'. 180s created $dff cell `$procdff$456' with positive edge clock. 180s Creating register for signal `\top.\state' using process `\top.$proc$app1.v:11$381'. 180s created $dff cell `$procdff$457' with positive edge clock. 180s 180s 2.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 180s 180s 2.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 180s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 180s Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 180s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 180s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 180s Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 180s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 180s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 180s Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 180s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 180s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 180s Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 180s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 180s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 180s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 180s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 180s Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 180s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 180s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 180s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 180s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 180s Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 180s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 180s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 180s Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 180s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 180s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 180s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 180s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 180s Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 180s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 180s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 180s Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 180s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 180s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 180s Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 180s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 180s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 180s Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 180s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 180s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 180s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 180s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 180s Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 180s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 180s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 180s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 180s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 180s Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 180s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 180s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 180s Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 180s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 180s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 180s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 180s Removing empty process `top.$proc$app1.v:9$390'. 180s Removing empty process `top.$proc$app1.v:8$389'. 180s Removing empty process `top.$proc$app1.v:7$388'. 180s Removing empty process `top.$proc$app1.v:11$381'. 180s Cleaned up 18 empty switches. 180s 180s 2.4.12. Executing OPT_EXPR pass (perform const folding). 180s Optimizing module top. 180s 180s 2.5. Executing FLATTEN pass (flatten design). 180s 180s 2.6. Executing TRIBUF pass. 180s 180s 2.7. Executing DEMINOUT pass (demote inout ports to input or output). 180s 180s 2.8. Executing OPT_EXPR pass (perform const folding). 180s Optimizing module top. 180s 180s 2.9. Executing OPT_CLEAN pass (remove unused cells and wires). 180s Finding unused cells or wires in module \top.. 180s Removed 0 unused cells and 5 unused wires. 180s 180s 180s 2.10. Executing CHECK pass (checking for obvious problems). 180s Checking module top... 180s Found and reported 0 problems. 180s 180s 2.11. Executing OPT pass (performing simple optimizations). 180s 180s 2.11.1. Executing OPT_EXPR pass (perform const folding). 180s Optimizing module top. 180s 180s 2.11.2. Executing OPT_MERGE pass (detect identical cells). 180s Finding identical cells in module `\top'. 180s Removed a total of 0 cells. 180s 180s 2.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 180s Running muxtree optimizer on module \top.. 180s Creating internal representation of mux trees. 180s No muxes found in this module. 180s Removed 0 multiplexer ports. 180s 180s 2.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 180s Optimizing cells in module \top. 180s Performed a total of 0 changes. 180s 180s 2.11.5. Executing OPT_MERGE pass (detect identical cells). 180s Finding identical cells in module `\top'. 180s Removed a total of 0 cells. 180s 180s 2.11.6. Executing OPT_DFF pass (perform DFF optimizations). 180s 180s 2.11.7. Executing OPT_CLEAN pass (remove unused cells and wires). 180s Finding unused cells or wires in module \top.. 180s 180s 2.11.8. Executing OPT_EXPR pass (perform const folding). 180s Optimizing module top. 180s 180s 2.11.9. Finished OPT passes. (There is nothing left to do.) 180s 180s 2.12. Executing FSM pass (extract and optimize FSM). 180s 180s 2.12.1. Executing FSM_DETECT pass (finding FSMs in design). 180s 180s 2.12.2. Executing FSM_EXTRACT pass (extracting FSM from design). 180s 180s 2.12.3. Executing FSM_OPT pass (simple optimizations of FSMs). 180s 180s 2.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). 180s Finding unused cells or wires in module \top.. 180s 180s 2.12.5. Executing FSM_OPT pass (simple optimizations of FSMs). 180s 180s 2.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 180s 180s 2.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 180s 180s 2.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 180s 180s 2.13. Executing OPT pass (performing simple optimizations). 180s 180s 2.13.1. Executing OPT_EXPR pass (perform const folding). 180s Optimizing module top. 180s 180s 2.13.2. Executing OPT_MERGE pass (detect identical cells). 180s Finding identical cells in module `\top'. 180s Removed a total of 0 cells. 180s 180s 2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 180s Running muxtree optimizer on module \top.. 180s Creating internal representation of mux trees. 180s No muxes found in this module. 180s Removed 0 multiplexer ports. 180s 180s 2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 180s Optimizing cells in module \top. 180s Performed a total of 0 changes. 180s 180s 2.13.5. Executing OPT_MERGE pass (detect identical cells). 180s Finding identical cells in module `\top'. 180s Removed a total of 0 cells. 180s 180s 2.13.6. Executing OPT_DFF pass (perform DFF optimizations). 180s 180s 2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). 180s Finding unused cells or wires in module \top.. 180s 180s 2.13.8. Executing OPT_EXPR pass (perform const folding). 180s Optimizing module top. 180s 180s 2.13.9. Finished OPT passes. (There is nothing left to do.) 180s 180s 2.14. Executing WREDUCE pass (reducing word size of cells). 180s Removed top 31 bits (of 32) from port B of cell top.$add$app1.v:12$382 ($add). 180s Removed top 10 bits (of 32) from port Y of cell top.$add$app1.v:12$382 ($add). 180s Removed top 3 bits (of 4) from port B of cell top.$add$app1.v:13$384 ($add). 180s Removed top 3 bits (of 4) from wire top.$logic_not$app1.v:13$383_Y. 180s 180s 2.15. Executing PEEPOPT pass (run peephole optimizers). 180s 180s 2.16. Executing OPT_CLEAN pass (remove unused cells and wires). 180s Finding unused cells or wires in module \top.. 180s Removed 0 unused cells and 2 unused wires. 180s 180s 180s 2.17. Executing SHARE pass (SAT-based resource sharing). 180s 180s 2.18. Executing TECHMAP pass (map to technology primitives). 180s 180s 2.18.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v 180s Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation. 180s Generating RTLIL representation for module `\_90_lut_cmp_'. 180s Successfully finished Verilog frontend. 180s 180s 2.18.2. Continuing TECHMAP pass. 180s No more expansions possible. 180s 180s 180s 2.19. Executing OPT_EXPR pass (perform const folding). 180s Optimizing module top. 180s 180s 2.20. Executing OPT_CLEAN pass (remove unused cells and wires). 180s Finding unused cells or wires in module \top.. 180s 180s 2.21. Executing ALUMACC pass (create $alu and $macc cells). 180s Extracting $alu and $macc cells in module top: 180s creating $macc model for $add$app1.v:12$382 ($add). 180s creating $macc model for $add$app1.v:13$384 ($add). 180s creating $alu model for $macc $add$app1.v:13$384. 180s creating $alu model for $macc $add$app1.v:12$382. 180s creating $alu cell for $add$app1.v:12$382: $auto$alumacc.cc:485:replace_alu$460 180s creating $alu cell for $add$app1.v:13$384: $auto$alumacc.cc:485:replace_alu$463 180s created 2 $alu and 0 $macc cells. 180s 180s 2.22. Executing OPT pass (performing simple optimizations). 180s 180s 2.22.1. Executing OPT_EXPR pass (perform const folding). 180s Optimizing module top. 180s 180s 2.22.2. Executing OPT_MERGE pass (detect identical cells). 180s Finding identical cells in module `\top'. 180s 180s Removed a total of 1 cells. 180s 180s 2.22.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 180s Running muxtree optimizer on module \top.. 180s Creating internal representation of mux trees. 180s No muxes found in this module. 180s Removed 0 multiplexer ports. 180s 180s 2.22.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 180s Optimizing cells in module \top. 180s Performed a total of 0 changes. 180s 180s 2.22.5. Executing OPT_MERGE pass (detect identical cells). 180s Finding identical cells in module `\top'. 180s Removed a total of 0 cells. 180s 180s 2.22.6. Executing OPT_DFF pass (perform DFF optimizations). 180s 180s 2.22.7. Executing OPT_CLEAN pass (remove unused cells and wires). 180s Finding unused cells or wires in module \top.. 180s Removed 0 unused cells and 1 unused wires. 180s 180s 180s 2.22.8. Executing OPT_EXPR pass (perform const folding). 180s Optimizing module top. 180s 180s 2.22.9. Rerunning OPT passes. (Maybe there is more to do..) 180s 180s 2.22.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 180s Running muxtree optimizer on module \top.. 180s Creating internal representation of mux trees. 180s No muxes found in this module. 180s Removed 0 multiplexer ports. 180s 180s 2.22.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 180s Optimizing cells in module \top. 180s Performed a total of 0 changes. 180s 180s 2.22.12. Executing OPT_MERGE pass (detect identical cells). 180s Finding identical cells in module `\top'. 180s Removed a total of 0 cells. 180s 180s 2.22.13. Executing OPT_DFF pass (perform DFF optimizations). 180s 180s 2.22.14. Executing OPT_CLEAN pass (remove unused cells and wires). 180s Finding unused cells or wires in module \top.. 180s 180s 2.22.15. Executing OPT_EXPR pass (perform const folding). 180s Optimizing module top. 180s 180s 2.22.16. Finished OPT passes. (There is nothing left to do.) 180s 180s 2.23. Executing MEMORY pass. 180s 180s 2.23.1. Executing OPT_MEM pass (optimize memories). 180s Performed a total of 0 transformations. 180s 180s 2.23.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). 180s Performed a total of 0 transformations. 180s 180s 2.23.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 180s 180s 2.23.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 180s 180s 2.23.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 180s 180s 2.23.6. Executing OPT_CLEAN pass (remove unused cells and wires). 180s Finding unused cells or wires in module \top.. 180s 180s 2.23.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 180s 180s 2.23.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). 180s Performed a total of 0 transformations. 180s 180s 2.23.9. Executing OPT_CLEAN pass (remove unused cells and wires). 180s Finding unused cells or wires in module \top.. 180s 180s 2.23.10. Executing MEMORY_COLLECT pass (generating $mem cells). 180s 180s 2.24. Executing OPT_CLEAN pass (remove unused cells and wires). 180s Finding unused cells or wires in module \top.. 180s 180s 2.25. Executing MEMORY_LIBMAP pass (mapping memories to cells). 180s 180s 2.26. Executing TECHMAP pass (map to technology primitives). 180s 180s 2.26.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v 180s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation. 180s Generating RTLIL representation for module `\$__ICE40_RAM4K_'. 180s Successfully finished Verilog frontend. 180s 180s 2.26.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/spram_map.v 180s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/spram_map.v' to AST representation. 180s Generating RTLIL representation for module `\$__ICE40_SPRAM_'. 180s Successfully finished Verilog frontend. 180s 180s 2.26.3. Continuing TECHMAP pass. 180s No more expansions possible. 180s 180s 180s 2.27. Executing ICE40_BRAMINIT pass. 180s 180s 2.28. Executing OPT pass (performing simple optimizations). 180s 180s 2.28.1. Executing OPT_EXPR pass (perform const folding). 180s Optimizing module top. 180s 180s 2.28.2. Executing OPT_MERGE pass (detect identical cells). 180s Finding identical cells in module `\top'. 180s Removed a total of 0 cells. 180s 180s 2.28.3. Executing OPT_DFF pass (perform DFF optimizations). 180s 180s 2.28.4. Executing OPT_CLEAN pass (remove unused cells and wires). 180s Finding unused cells or wires in module \top.. 180s 180s 2.28.5. Finished fast OPT passes. 180s 180s 2.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 180s 180s 2.30. Executing OPT pass (performing simple optimizations). 180s 180s 2.30.1. Executing OPT_EXPR pass (perform const folding). 180s Optimizing module top. 180s 180s 2.30.2. Executing OPT_MERGE pass (detect identical cells). 180s Finding identical cells in module `\top'. 180s Removed a total of 0 cells. 180s 180s 2.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 180s Running muxtree optimizer on module \top.. 180s Creating internal representation of mux trees. 180s No muxes found in this module. 180s Removed 0 multiplexer ports. 180s 180s 2.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 180s Optimizing cells in module \top. 180s Performed a total of 0 changes. 180s 180s 2.30.5. Executing OPT_MERGE pass (detect identical cells). 180s Finding identical cells in module `\top'. 180s Removed a total of 0 cells. 180s 180s 2.30.6. Executing OPT_DFF pass (perform DFF optimizations). 180s 180s 2.30.7. Executing OPT_CLEAN pass (remove unused cells and wires). 180s Finding unused cells or wires in module \top.. 180s 180s 2.30.8. Executing OPT_EXPR pass (perform const folding). 180s Optimizing module top. 180s 180s 2.30.9. Finished OPT passes. (There is nothing left to do.) 180s 180s 2.31. Executing ICE40_WRAPCARRY pass (wrap carries). 180s 180s 2.32. Executing TECHMAP pass (map to technology primitives). 180s 180s 2.32.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v 180s Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation. 180s Generating RTLIL representation for module `\_90_simplemap_bool_ops'. 180s Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. 180s Generating RTLIL representation for module `\_90_simplemap_logic_ops'. 180s Generating RTLIL representation for module `\_90_simplemap_compare_ops'. 180s Generating RTLIL representation for module `\_90_simplemap_various'. 180s Generating RTLIL representation for module `\_90_simplemap_registers'. 180s Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. 180s Generating RTLIL representation for module `\_90_shift_shiftx'. 180s Generating RTLIL representation for module `\_90_fa'. 180s Generating RTLIL representation for module `\_90_lcu'. 180s Generating RTLIL representation for module `\_90_alu'. 180s Generating RTLIL representation for module `\_90_macc'. 180s Generating RTLIL representation for module `\_90_alumacc'. 180s Generating RTLIL representation for module `\$__div_mod_u'. 180s Generating RTLIL representation for module `\$__div_mod_trunc'. 180s Generating RTLIL representation for module `\_90_div'. 180s Generating RTLIL representation for module `\_90_mod'. 180s Generating RTLIL representation for module `\$__div_mod_floor'. 180s Generating RTLIL representation for module `\_90_divfloor'. 180s Generating RTLIL representation for module `\_90_modfloor'. 180s Generating RTLIL representation for module `\_90_pow'. 180s Generating RTLIL representation for module `\_90_pmux'. 180s Generating RTLIL representation for module `\_90_demux'. 180s Generating RTLIL representation for module `\_90_lut'. 180s Successfully finished Verilog frontend. 180s 180s 2.32.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v 180s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation. 180s Generating RTLIL representation for module `\_80_ice40_alu'. 180s Successfully finished Verilog frontend. 180s 180s 2.32.3. Continuing TECHMAP pass. 180s Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_80_ice40_alu for cells of type $alu. 180s Using extmapper simplemap for cells of type $logic_not. 180s Using template $paramod$080e6a70eb8bfa1ccf22d9718e795074645029a4\_80_ice40_alu for cells of type $alu. 180s Using extmapper simplemap for cells of type $xor. 180s Using extmapper simplemap for cells of type $reduce_and. 180s Using extmapper simplemap for cells of type $dff. 180s Using extmapper simplemap for cells of type $mux. 180s Using extmapper simplemap for cells of type $not. 180s Using extmapper simplemap for cells of type $pos. 180s No more expansions possible. 180s 180s 180s 2.33. Executing OPT pass (performing simple optimizations). 180s 180s 2.33.1. Executing OPT_EXPR pass (perform const folding). 180s Optimizing module top. 180s 180s 180s 2.33.2. Executing OPT_MERGE pass (detect identical cells). 180s Finding identical cells in module `\top'. 180s 180s Removed a total of 1 cells. 180s 180s 2.33.3. Executing OPT_DFF pass (perform DFF optimizations). 180s 180s 2.33.4. Executing OPT_CLEAN pass (remove unused cells and wires). 180s Finding unused cells or wires in module \top.. 180s Removed 27 unused cells and 34 unused wires. 180s 180s 180s 2.33.5. Finished fast OPT passes. 180s 180s 2.34. Executing ICE40_OPT pass (performing simple optimizations). 180s 180s 2.34.1. Running ICE40 specific optimizations. 180s Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$460.slice[0].carry: CO=\counter [0] 180s 180s 2.34.2. Executing OPT_EXPR pass (perform const folding). 180s Optimizing module top. 180s 180s 2.34.3. Executing OPT_MERGE pass (detect identical cells). 180s Finding identical cells in module `\top'. 180s Removed a total of 0 cells. 180s 180s 2.34.4. Executing OPT_DFF pass (perform DFF optimizations). 180s 180s 2.34.5. Executing OPT_CLEAN pass (remove unused cells and wires). 180s Finding unused cells or wires in module \top.. 180s 180s 2.34.6. Rerunning OPT passes. (Removed registers in this run.) 180s 180s 2.34.7. Running ICE40 specific optimizations. 180s 180s 2.34.8. Executing OPT_EXPR pass (perform const folding). 180s Optimizing module top. 180s 180s 2.34.9. Executing OPT_MERGE pass (detect identical cells). 180s Finding identical cells in module `\top'. 180s Removed a total of 0 cells. 180s 180s 2.34.10. Executing OPT_DFF pass (perform DFF optimizations). 180s 180s 2.34.11. Executing OPT_CLEAN pass (remove unused cells and wires). 180s Finding unused cells or wires in module \top.. 180s 180s 2.34.12. Finished OPT passes. (There is nothing left to do.) 180s 180s 2.35. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 180s 180s 2.36. Executing TECHMAP pass (map to technology primitives). 180s 180s 2.36.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 180s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 180s Generating RTLIL representation for module `\$_DFF_N_'. 180s Generating RTLIL representation for module `\$_DFF_P_'. 180s Generating RTLIL representation for module `\$_DFFE_NP_'. 180s Generating RTLIL representation for module `\$_DFFE_PP_'. 180s Generating RTLIL representation for module `\$_DFF_NP0_'. 180s Generating RTLIL representation for module `\$_DFF_NP1_'. 180s Generating RTLIL representation for module `\$_DFF_PP0_'. 180s Generating RTLIL representation for module `\$_DFF_PP1_'. 180s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 180s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 180s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 180s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 180s Generating RTLIL representation for module `\$_SDFF_NP0_'. 180s Generating RTLIL representation for module `\$_SDFF_NP1_'. 180s Generating RTLIL representation for module `\$_SDFF_PP0_'. 180s Generating RTLIL representation for module `\$_SDFF_PP1_'. 180s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 180s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 180s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 180s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 180s Successfully finished Verilog frontend. 180s 180s 2.36.2. Continuing TECHMAP pass. 180s Using template \$_DFF_P_ for cells of type $_DFF_P_. 180s No more expansions possible. 180s 180s 180s 2.37. Executing OPT_EXPR pass (perform const folding). 180s Optimizing module top. 180s 180s 2.38. Executing SIMPLEMAP pass (map simple cells to gate primitives). 180s Mapping top.$auto$alumacc.cc:485:replace_alu$460.slice[0].carry ($lut). 180s 180s 2.39. Executing ICE40_OPT pass (performing simple optimizations). 180s 180s 2.39.1. Running ICE40 specific optimizations. 180s 180s 2.39.2. Executing OPT_EXPR pass (perform const folding). 180s Optimizing module top. 180s 180s 180s 2.39.3. Executing OPT_MERGE pass (detect identical cells). 180s Finding identical cells in module `\top'. 180s Removed a total of 0 cells. 180s 180s 2.39.4. Executing OPT_DFF pass (perform DFF optimizations). 180s 180s 2.39.5. Executing OPT_CLEAN pass (remove unused cells and wires). 180s Finding unused cells or wires in module \top.. 180s Removed 0 unused cells and 112 unused wires. 180s 180s 180s 2.39.6. Rerunning OPT passes. (Removed registers in this run.) 180s 180s 2.39.7. Running ICE40 specific optimizations. 180s 180s 2.39.8. Executing OPT_EXPR pass (perform const folding). 180s Optimizing module top. 180s 180s 2.39.9. Executing OPT_MERGE pass (detect identical cells). 180s Finding identical cells in module `\top'. 180s Removed a total of 0 cells. 180s 180s 2.39.10. Executing OPT_DFF pass (perform DFF optimizations). 180s 180s 2.39.11. Executing OPT_CLEAN pass (remove unused cells and wires). 180s Finding unused cells or wires in module \top.. 180s 180s 2.39.12. Finished OPT passes. (There is nothing left to do.) 180s 180s 2.40. Executing TECHMAP pass (map to technology primitives). 180s 180s 2.40.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v 180s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation. 180s Generating RTLIL representation for module `\$_DLATCH_N_'. 180s Generating RTLIL representation for module `\$_DLATCH_P_'. 180s Successfully finished Verilog frontend. 180s 180s 2.40.2. Continuing TECHMAP pass. 180s No more expansions possible. 180s 180s 180s 2.41. Executing ABC pass (technology mapping using ABC). 180s 180s 2.41.1. Extracting gate netlist of module `\top' to `/input.blif'.. 180s Extracted 27 gates and 54 wires to a netlist network with 27 inputs and 4 outputs. 180s 180s 2.41.1.1. Executing ABC. 181s Running ABC command: "berkeley-abc" -s -f /abc.script 2>&1 181s ABC: ABC command line: "source /abc.script". 181s ABC: 181s ABC: + read_blif /input.blif 181s ABC: + read_lut /lutdefs.txt 181s ABC: + strash 181s ABC: + &get -n 181s ABC: + &fraig -x 181s ABC: + &put 181s ABC: + scorr 181s ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). 181s ABC: + dc2 181s ABC: + dretime 181s ABC: + strash 181s ABC: + dch -f 181s ABC: + if 181s ABC: + mfs2 181s ABC: + lutpack -S 1 181s ABC: + dress /input.blif 181s ABC: Total number of equiv classes = 5. 181s ABC: Participating nodes from both networks = 9. 181s ABC: Participating nodes from the first network = 4. ( 30.77 % of nodes) 181s ABC: Participating nodes from the second network = 5. ( 38.46 % of nodes) 181s ABC: Node pairs (any polarity) = 4. ( 30.77 % of names can be moved) 181s ABC: Node pairs (same polarity) = 4. ( 30.77 % of names can be moved) 181s ABC: Total runtime = 0.08 sec 181s ABC: + write_blif /output.blif 181s 181s 2.41.1.2. Re-integrating ABC results. 181s ABC RESULTS: $lut cells: 12 181s ABC RESULTS: internal signals: 23 181s ABC RESULTS: input signals: 27 181s ABC RESULTS: output signals: 4 181s Removing temp directory. 181s 181s 2.42. Executing ICE40_WRAPCARRY pass (wrap carries). 181s 181s 2.43. Executing TECHMAP pass (map to technology primitives). 181s 181s 2.43.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 181s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 181s Generating RTLIL representation for module `\$_DFF_N_'. 181s Generating RTLIL representation for module `\$_DFF_P_'. 181s Generating RTLIL representation for module `\$_DFFE_NP_'. 181s Generating RTLIL representation for module `\$_DFFE_PP_'. 181s Generating RTLIL representation for module `\$_DFF_NP0_'. 181s Generating RTLIL representation for module `\$_DFF_NP1_'. 181s Generating RTLIL representation for module `\$_DFF_PP0_'. 181s Generating RTLIL representation for module `\$_DFF_PP1_'. 181s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 181s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 181s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 181s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 181s Generating RTLIL representation for module `\$_SDFF_NP0_'. 181s Generating RTLIL representation for module `\$_SDFF_NP1_'. 181s Generating RTLIL representation for module `\$_SDFF_PP0_'. 181s Generating RTLIL representation for module `\$_SDFF_PP1_'. 181s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 181s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 181s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 181s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 181s Successfully finished Verilog frontend. 181s 181s 2.43.2. Continuing TECHMAP pass. 181s No more expansions possible. 181s 181s Removed 2 unused cells and 39 unused wires. 181s 181s 2.44. Executing OPT_LUT pass (optimize LUTs). 181s Discovering LUTs. 181s Number of LUTs: 37 181s 1-LUT 1 181s 2-LUT 4 181s 3-LUT 25 181s 4-LUT 7 181s with \SB_CARRY (#0) 23 181s with \SB_CARRY (#1) 23 181s 181s Eliminating LUTs. 181s Number of LUTs: 37 181s 1-LUT 1 181s 2-LUT 4 181s 3-LUT 25 181s 4-LUT 7 181s with \SB_CARRY (#0) 23 181s with \SB_CARRY (#1) 23 181s 181s Combining LUTs. 181s Number of LUTs: 37 181s 1-LUT 1 181s 2-LUT 4 181s 3-LUT 25 181s 4-LUT 7 181s with \SB_CARRY (#0) 23 181s with \SB_CARRY (#1) 23 181s 181s Eliminated 0 LUTs. 181s Combined 0 LUTs. 181s 181s 181s 2.45. Executing TECHMAP pass (map to technology primitives). 181s 181s 2.45.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v 181s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation. 181s Generating RTLIL representation for module `\$lut'. 181s Successfully finished Verilog frontend. 181s 181s 2.45.2. Continuing TECHMAP pass. 181s Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut. 181s Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut. 181s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut. 181s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. 181s Using template $paramod$415b9dd3a15783ae56c103f189fd8e182f997441\$lut for cells of type $lut. 181s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. 181s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. 181s Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut. 181s No more expansions possible. 181s 181s Removed 0 unused cells and 78 unused wires. 181s 181s 2.46. Executing AUTONAME pass. 181s Renamed 463 objects in module top (10 iterations). 181s 181s 181s 2.47. Executing HIERARCHY pass (managing design hierarchy). 181s 181s 2.47.1. Analyzing design hierarchy.. 181s Top module: \top 181s 181s 2.47.2. Analyzing design hierarchy.. 181s Top module: \top 181s Removed 0 unused modules. 181s 181s 2.48. Printing statistics. 181s 181s === top === 181s 181s Number of wires: 20 181s Number of wire bits: 99 181s Number of public wires: 20 181s Number of public wire bits: 99 181s Number of memories: 0 181s Number of memory bits: 0 181s Number of processes: 0 181s Number of cells: 88 181s SB_CARRY 23 181s SB_DFF 27 181s SB_LUT4 37 181s SB_WARMBOOT 1 181s 181s 2.49. Executing CHECK pass (checking for obvious problems). 181s Checking module top... 181s Found and reported 0 problems. 181s 181s 2.50. Executing JSON backend. 181s 181s End of script. Logfile hash: 630c0abba3, CPU: user 1.01s system 0.01s, MEM: 22.00 MB peak 181s Yosys 0.23 (git sha1 7ce5011c24b) 181s Time spent: 60% 13x read_verilog (0 sec), 13% 1x abc (0 sec), ... 181s nextpnr-ice40 --hx1k --package tq144 --asc app1.asc --pcf icestick.pcf --json app1.json 181s Warning: unmatched constraint 'RX' (on line 4) 181s Warning: unmatched constraint 'TX' (on line 5) 181s Info: constrained 'LED1' to bel 'X13/Y12/io1' 181s Info: constrained 'LED2' to bel 'X13/Y12/io0' 181s Info: constrained 'LED3' to bel 'X13/Y11/io1' 181s Info: constrained 'LED4' to bel 'X13/Y11/io0' 181s Info: constrained 'LED5' to bel 'X13/Y9/io1' 181s Info: constrained 'clk' to bel 'X0/Y8/io1' 181s 181s Info: Packing constants.. 181s Info: Packing IOs.. 181s Info: Packing LUT-FFs.. 181s Info: 10 LCs used as LUT4 only 181s Info: 27 LCs used as LUT4 and DFF 181s Info: Packing non-LUT FFs.. 181s Info: 0 LCs used as DFF only 181s Info: Packing carries.. 181s Info: 0 LCs used as CARRY only 181s Info: Packing indirect carry+LUT pairs... 181s Info: 0 LUTs merged into carry LCs 181s Info: Packing RAMs.. 181s Info: Placing PLLs.. 181s Info: Packing special functions.. 181s Info: Packing PLLs.. 181s Info: Promoting globals.. 181s Info: promoting clk$SB_IO_IN (fanout 27) 181s Info: Constraining chains... 181s Info: 1 LCs used to legalise carry chains. 181s Info: Checksum: 0xb506605d 181s 181s Info: Annotating ports with timing budgets for target frequency 12.00 MHz 181s Info: Checksum: 0x14b02b09 181s 181s Info: Device utilisation: 181s Info: ICESTORM_LC: 40/ 1280 3% 181s Info: ICESTORM_RAM: 0/ 16 0% 181s Info: SB_IO: 6/ 112 5% 181s Info: SB_GB: 1/ 8 12% 181s Info: ICESTORM_PLL: 0/ 1 0% 181s Info: SB_WARMBOOT: 1/ 1 100% 181s 181s Info: Placed 6 cells based on constraints. 181s Info: Creating initial analytic placement for 18 cells, random placement wirelen = 358. 181s Info: at initial placer iter 0, wirelen = 17 181s Info: at initial placer iter 1, wirelen = 14 181s Info: at initial placer iter 2, wirelen = 14 181s Info: at initial placer iter 3, wirelen = 14 181s Info: Running main analytical placer, max placement attempts per cell = 10000. 181s Info: at iteration #1, type ICESTORM_LC: wirelen solved = 16, spread = 61, legal = 87; time = 0.00s 181s Info: at iteration #1, type SB_GB: wirelen solved = 87, spread = 87, legal = 87; time = 0.00s 181s Info: at iteration #1, type SB_WARMBOOT: wirelen solved = 87, spread = 87, legal = 147; time = 0.00s 181s Info: at iteration #1, type ALL: wirelen solved = 28, spread = 75, legal = 119; time = 0.00s 181s Info: at iteration #2, type ICESTORM_LC: wirelen solved = 86, spread = 140, legal = 173; time = 0.00s 181s Info: at iteration #2, type SB_GB: wirelen solved = 173, spread = 173, legal = 173; time = 0.00s 181s Info: at iteration #2, type SB_WARMBOOT: wirelen solved = 121, spread = 121, legal = 173; time = 0.00s 181s Info: at iteration #2, type ALL: wirelen solved = 19, spread = 73, legal = 135; time = 0.00s 181s Info: at iteration #3, type ICESTORM_LC: wirelen solved = 84, spread = 131, legal = 149; time = 0.00s 181s Info: at iteration #3, type SB_GB: wirelen solved = 149, spread = 149, legal = 149; time = 0.00s 181s Info: at iteration #3, type SB_WARMBOOT: wirelen solved = 93, spread = 93, legal = 149; time = 0.00s 181s Info: at iteration #3, type ALL: wirelen solved = 20, spread = 78, legal = 140; time = 0.00s 181s Info: at iteration #4, type ICESTORM_LC: wirelen solved = 86, spread = 141, legal = 146; time = 0.00s 181s Info: at iteration #4, type SB_GB: wirelen solved = 146, spread = 146, legal = 146; time = 0.00s 181s Info: at iteration #4, type SB_WARMBOOT: wirelen solved = 88, spread = 88, legal = 146; time = 0.00s 181s Info: at iteration #4, type ALL: wirelen solved = 20, spread = 78, legal = 140; time = 0.00s 181s Info: at iteration #5, type ICESTORM_LC: wirelen solved = 83, spread = 138, legal = 146; time = 0.00s 181s Info: at iteration #5, type SB_GB: wirelen solved = 146, spread = 146, legal = 146; time = 0.00s 181s Info: at iteration #5, type SB_WARMBOOT: wirelen solved = 87, spread = 87, legal = 146; time = 0.00s 181s Info: at iteration #5, type ALL: wirelen solved = 26, spread = 78, legal = 140; time = 0.00s 181s Info: at iteration #6, type ICESTORM_LC: wirelen solved = 85, spread = 138, legal = 141; time = 0.00s 181s Info: at iteration #6, type SB_GB: wirelen solved = 141, spread = 141, legal = 141; time = 0.00s 181s Info: at iteration #6, type SB_WARMBOOT: wirelen solved = 82, spread = 82, legal = 141; time = 0.00s 181s Info: at iteration #6, type ALL: wirelen solved = 27, spread = 78, legal = 140; time = 0.00s 181s Info: HeAP Placer Time: 0.02s 181s Info: of which solving equations: 0.01s 181s Info: of which spreading cells: 0.00s 181s Info: of which strict legalisation: 0.00s 181s 181s Info: Running simulated annealing placer for refinement. 181s Info: at iteration #1: temp = 0.000000, timing cost = 20, wirelen = 119 181s Info: at iteration #5: temp = 0.000000, timing cost = 12, wirelen = 107 181s Info: at iteration #6: temp = 0.000000, timing cost = 12, wirelen = 107 181s Info: SA placement time 0.01s 181s 181s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 172.89 MHz (PASS at 12.00 MHz) 181s 181s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> : 4.14 ns 181s 181s Info: Slack histogram: 181s Info: legend: * represents 1 endpoint(s) 181s Info: + represents [1,1) endpoint(s) 181s Info: [ 77549, 77766) |** 181s Info: [ 77766, 77983) |* 181s Info: [ 77983, 78200) | 181s Info: [ 78200, 78417) |** 181s Info: [ 78417, 78634) |** 181s Info: [ 78634, 78851) |** 181s Info: [ 78851, 79068) |* 181s Info: [ 79068, 79285) |*** 181s Info: [ 79285, 79502) |** 181s Info: [ 79502, 79719) |** 181s Info: [ 79719, 79936) |** 181s Info: [ 79936, 80153) |** 181s Info: [ 80153, 80370) |* 181s Info: [ 80370, 80587) | 181s Info: [ 80587, 80804) |** 181s Info: [ 80804, 81021) |** 181s Info: [ 81021, 81238) |** 181s Info: [ 81238, 81455) | 181s Info: [ 81455, 81672) |* 181s Info: [ 81672, 81889) |**************************** 181s Info: Checksum: 0xaf6b4360 181s 181s Info: Routing.. 181s Info: Setting up routing queue. 181s Info: Routing 127 arcs. 181s Info: | (re-)routed arcs | delta | remaining| time spent | 181s Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| 181s Info: 128 | 1 107 | 1 107 | 0| 0.01 0.01| 181s Info: Routing complete. 181s Info: Router1 time 0.01s 181s Info: Checksum: 0x157cf516 181s 181s Info: Critical path report for clock 'clk$SB_IO_IN_$glb_clk' (posedge -> posedge): 181s Info: curr total 181s Info: 0.5 0.5 Source counter_SB_LUT4_I2_7_LC.O 181s Info: 0.6 1.1 Net counter[2] budget 20.292999 ns (12,10) -> (11,10) 181s Info: Sink state_SB_LUT4_I3_I0_SB_LUT4_O_2_I3_SB_LUT4_O_LC.I0 181s Info: Defined in: 181s Info: app1.v:7.22-7.29 181s Info: 0.4 1.6 Source state_SB_LUT4_I3_I0_SB_LUT4_O_2_I3_SB_LUT4_O_LC.O 181s Info: 0.6 2.2 Net state_SB_LUT4_I3_I0_SB_LUT4_O_2_I3[2] budget 20.292999 ns (11,10) -> (11,10) 181s Info: Sink state_SB_LUT4_I3_I0_SB_LUT4_O_2_LC.I3 181s Info: Defined in: 181s Info: /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 181s Info: 0.3 2.5 Source state_SB_LUT4_I3_I0_SB_LUT4_O_2_LC.O 181s Info: 1.0 3.4 Net state_SB_LUT4_I3_I0[0] budget 20.292000 ns (11,10) -> (11,13) 181s Info: Sink counter2_SB_LUT4_I2_3_I1_SB_LUT4_O_LC.I1 181s Info: Defined in: 181s Info: /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 181s Info: 0.4 3.8 Source counter2_SB_LUT4_I2_3_I1_SB_LUT4_O_LC.O 181s Info: 0.6 4.4 Net counter2_SB_LUT4_I2_3_I1 budget 20.292000 ns (11,13) -> (11,12) 181s Info: Sink counter2_SB_LUT4_I2_3_LC.I1 181s Info: Defined in: 181s Info: app1.v:13.15-13.34 181s Info: /usr/bin/../share/yosys/ice40/arith_map.v:29.22-29.23 181s Info: 0.3 4.7 Source counter2_SB_LUT4_I2_3_LC.COUT 181s Info: 0.0 4.7 Net counter2_SB_CARRY_I1_CO[1] budget 0.000000 ns (11,12) -> (11,12) 181s Info: Sink counter2_SB_LUT4_I2_2_LC.CIN 181s Info: Defined in: 181s Info: app1.v:13.15-13.34 181s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 181s Info: 0.1 4.8 Source counter2_SB_LUT4_I2_2_LC.COUT 181s Info: 0.0 4.8 Net counter2_SB_CARRY_I1_CO[2] budget 0.000000 ns (11,12) -> (11,12) 181s Info: Sink counter2_SB_LUT4_I2_1_LC.CIN 181s Info: Defined in: 181s Info: app1.v:13.15-13.34 181s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 181s Info: 0.1 4.9 Source counter2_SB_LUT4_I2_1_LC.COUT 181s Info: 0.3 5.2 Net counter2_SB_CARRY_I1_CO[3] budget 0.260000 ns (11,12) -> (11,12) 181s Info: Sink counter2_SB_LUT4_I2_LC.I3 181s Info: Defined in: 181s Info: app1.v:13.15-13.34 181s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 181s Info: 0.3 5.5 Setup counter2_SB_LUT4_I2_LC.I3 181s Info: 2.5 ns logic, 3.0 ns routing 181s 181s Info: Critical path report for cross-domain path 'posedge clk$SB_IO_IN_$glb_clk' -> '': 181s Info: curr total 181s Info: 0.5 0.5 Source counter2_SB_LUT4_I2_3_LC.O 181s Info: 0.6 1.1 Net counter2[0] budget 41.173000 ns (11,12) -> (11,12) 181s Info: Sink WB_BOOT_SB_LUT4_O_LC.I0 181s Info: Defined in: 181s Info: app1.v:8.12-8.20 181s Info: 0.4 1.6 Source WB_BOOT_SB_LUT4_O_LC.O 181s Info: 1.8 3.4 Net WB_BOOT budget 41.172001 ns (11,12) -> (0,0) 181s Info: Sink WB.BOOT 181s Info: Defined in: 181s Info: app1.v:24.9-24.18 181s Info: 1.0 ns logic, 2.4 ns routing 181s 181s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 180.80 MHz (PASS at 12.00 MHz) 181s 181s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> : 3.39 ns 181s 181s Info: Slack histogram: 181s Info: legend: * represents 1 endpoint(s) 181s Info: + represents [1,1) endpoint(s) 181s Info: [ 77802, 78006) |** 181s Info: [ 78006, 78210) |* 181s Info: [ 78210, 78414) | 181s Info: [ 78414, 78618) |*** 181s Info: [ 78618, 78822) |** 181s Info: [ 78822, 79026) |** 181s Info: [ 79026, 79230) | 181s Info: [ 79230, 79434) |** 181s Info: [ 79434, 79638) |** 181s Info: [ 79638, 79842) |*** 181s Info: [ 79842, 80046) |*** 181s Info: [ 80046, 80250) |** 181s Info: [ 80250, 80454) | 181s Info: [ 80454, 80658) |* 181s Info: [ 80658, 80862) |** 181s Info: [ 80862, 81066) |* 181s Info: [ 81066, 81270) |** 181s Info: [ 81270, 81474) | 181s Info: [ 81474, 81678) |* 181s Info: [ 81678, 81882) |**************************** 181s 2 warnings, 0 errors 181s 181s Info: Program finished normally. 181s icetime -d hx1k -c 25 app1.asc 181s // Reading input .asc file.. 181s // Reading 1k chipdb file.. 181s // Creating timing netlist.. 181s // Timing estimate: 5.54 ns (180.65 MHz) 181s // Checking 40.00 ns (25.00 MHz) clock constraint: PASSED. 181s icepack app1.asc app1.bin 181s yosys -p "synth_ice40 -top top -json app2.json" app2.v 181s 181s /----------------------------------------------------------------------------\ 181s | | 181s | yosys -- Yosys Open SYnthesis Suite | 181s | | 181s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 181s | | 181s | Permission to use, copy, modify, and/or distribute this software for any | 181s | purpose with or without fee is hereby granted, provided that the above | 181s | copyright notice and this permission notice appear in all copies. | 181s | | 181s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 181s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 181s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 181s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 181s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 181s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 181s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 181s | | 181s \----------------------------------------------------------------------------/ 181s 181s Yosys 0.23 (git sha1 7ce5011c24b) 181s 181s 181s -- Parsing `app2.v' using frontend ` -vlog2k' -- 181s 181s 1. Executing Verilog-2005 frontend: app2.v 181s Parsing Verilog input from `app2.v' to AST representation. 181s Storing AST representation for module `$abstract\top'. 181s Successfully finished Verilog frontend. 181s 181s -- Running command `synth_ice40 -top top -json app2.json' -- 181s 181s 2. Executing SYNTH_ICE40 pass. 181s 181s 2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v 181s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation. 181s Generating RTLIL representation for module `\SB_IO'. 181s Generating RTLIL representation for module `\SB_GB_IO'. 181s Generating RTLIL representation for module `\SB_GB'. 181s Generating RTLIL representation for module `\SB_LUT4'. 181s Generating RTLIL representation for module `\SB_CARRY'. 181s Generating RTLIL representation for module `\SB_DFF'. 181s Generating RTLIL representation for module `\SB_DFFE'. 181s Generating RTLIL representation for module `\SB_DFFSR'. 181s Generating RTLIL representation for module `\SB_DFFR'. 181s Generating RTLIL representation for module `\SB_DFFSS'. 181s Generating RTLIL representation for module `\SB_DFFS'. 181s Generating RTLIL representation for module `\SB_DFFESR'. 181s Generating RTLIL representation for module `\SB_DFFER'. 181s Generating RTLIL representation for module `\SB_DFFESS'. 181s Generating RTLIL representation for module `\SB_DFFES'. 181s Generating RTLIL representation for module `\SB_DFFN'. 181s Generating RTLIL representation for module `\SB_DFFNE'. 181s Generating RTLIL representation for module `\SB_DFFNSR'. 181s Generating RTLIL representation for module `\SB_DFFNR'. 181s Generating RTLIL representation for module `\SB_DFFNSS'. 181s Generating RTLIL representation for module `\SB_DFFNS'. 181s Generating RTLIL representation for module `\SB_DFFNESR'. 181s Generating RTLIL representation for module `\SB_DFFNER'. 181s Generating RTLIL representation for module `\SB_DFFNESS'. 181s Generating RTLIL representation for module `\SB_DFFNES'. 181s Generating RTLIL representation for module `\SB_RAM40_4K'. 181s Generating RTLIL representation for module `\SB_RAM40_4KNR'. 181s Generating RTLIL representation for module `\SB_RAM40_4KNW'. 181s Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. 181s Generating RTLIL representation for module `\ICESTORM_LC'. 181s Generating RTLIL representation for module `\SB_PLL40_CORE'. 181s Generating RTLIL representation for module `\SB_PLL40_PAD'. 181s Generating RTLIL representation for module `\SB_PLL40_2_PAD'. 181s Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. 181s Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. 181s Generating RTLIL representation for module `\SB_WARMBOOT'. 181s Generating RTLIL representation for module `\SB_SPRAM256KA'. 181s Generating RTLIL representation for module `\SB_HFOSC'. 181s Generating RTLIL representation for module `\SB_LFOSC'. 181s Generating RTLIL representation for module `\SB_RGBA_DRV'. 181s Generating RTLIL representation for module `\SB_LED_DRV_CUR'. 181s Generating RTLIL representation for module `\SB_RGB_DRV'. 181s Generating RTLIL representation for module `\SB_I2C'. 181s Generating RTLIL representation for module `\SB_SPI'. 181s Generating RTLIL representation for module `\SB_LEDDA_IP'. 181s Generating RTLIL representation for module `\SB_FILTER_50NS'. 181s Generating RTLIL representation for module `\SB_IO_I3C'. 181s Generating RTLIL representation for module `\SB_IO_OD'. 181s Generating RTLIL representation for module `\SB_MAC16'. 181s Generating RTLIL representation for module `\ICESTORM_RAM'. 181s Successfully finished Verilog frontend. 181s 181s 2.2. Executing HIERARCHY pass (managing design hierarchy). 181s 181s 2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\top'. 181s Generating RTLIL representation for module `\top'. 181s 181s 2.3.1. Analyzing design hierarchy.. 181s Top module: \top 181s 181s 2.3.2. Analyzing design hierarchy.. 181s Top module: \top 181s Removing unused module `$abstract\top'. 181s Removed 1 unused modules. 181s 181s 2.4. Executing PROC pass (convert processes to netlists). 181s 181s 2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 181s Cleaned up 0 empty switches. 181s 181s 2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 181s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241 in module SB_DFFNES. 181s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234 in module SB_DFFNESS. 181s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230 in module SB_DFFNER. 181s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223 in module SB_DFFNESR. 181s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220 in module SB_DFFNS. 181s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217 in module SB_DFFNSS. 181s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214 in module SB_DFFNR. 181s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211 in module SB_DFFNSR. 181s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203 in module SB_DFFES. 181s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196 in module SB_DFFESS. 181s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192 in module SB_DFFER. 181s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185 in module SB_DFFESR. 181s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182 in module SB_DFFS. 181s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179 in module SB_DFFSS. 181s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176 in module SB_DFFR. 181s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173 in module SB_DFFSR. 181s Removed a total of 0 dead cases. 181s 181s 2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 181s Removed 8 redundant assignments. 181s Promoted 28 assignments to connections. 181s 181s 2.4.4. Executing PROC_INIT pass (extract init attributes). 181s Found init rule in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 181s Set init value: \Q = 1'0 181s Found init rule in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 181s Set init value: \Q = 1'0 181s Found init rule in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 181s Set init value: \Q = 1'0 181s Found init rule in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 181s Set init value: \Q = 1'0 181s Found init rule in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 181s Set init value: \Q = 1'0 181s Found init rule in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 181s Set init value: \Q = 1'0 181s Found init rule in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 181s Set init value: \Q = 1'0 181s Found init rule in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 181s Set init value: \Q = 1'0 181s Found init rule in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 181s Set init value: \Q = 1'0 181s Found init rule in `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 181s Set init value: \Q = 1'0 181s Found init rule in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 181s Set init value: \Q = 1'0 181s Found init rule in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 181s Set init value: \Q = 1'0 181s Found init rule in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 181s Set init value: \Q = 1'0 181s Found init rule in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 181s Set init value: \Q = 1'0 181s Found init rule in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 181s Set init value: \Q = 1'0 181s Found init rule in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 181s Set init value: \Q = 1'0 181s Found init rule in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 181s Set init value: \Q = 1'0 181s Found init rule in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 181s Set init value: \Q = 1'0 181s Found init rule in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 181s Set init value: \Q = 1'0 181s Found init rule in `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 181s Set init value: \Q = 1'0 181s Found init rule in `\top.$proc$app2.v:9$390'. 181s Set init value: \state = 1'0 181s Found init rule in `\top.$proc$app2.v:8$389'. 181s Set init value: \counter2 = 4'0000 181s Found init rule in `\top.$proc$app2.v:7$388'. 181s Set init value: \counter = 22'0000000000000000000000 181s 181s 2.4.5. Executing PROC_ARST pass (detect async resets in processes). 181s Found async reset \S in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 181s Found async reset \R in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 181s Found async reset \S in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 181s Found async reset \R in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 181s Found async reset \S in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 181s Found async reset \R in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 181s Found async reset \S in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 181s Found async reset \R in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 181s 181s 2.4.6. Executing PROC_ROM pass (convert switches to ROMs). 181s Converted 0 switches. 181s 181s 181s 2.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 181s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 181s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 181s 1/1: $0\Q[0:0] 181s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 181s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 181s 1/1: $0\Q[0:0] 181s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 181s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 181s 1/1: $0\Q[0:0] 181s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 181s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 181s 1/1: $0\Q[0:0] 181s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 181s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 181s 1/1: $0\Q[0:0] 181s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 181s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 181s 1/1: $0\Q[0:0] 181s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 181s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 181s 1/1: $0\Q[0:0] 181s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 181s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 181s 1/1: $0\Q[0:0] 181s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 181s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 181s 1/1: $0\Q[0:0] 181s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 181s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 181s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 181s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 181s 1/1: $0\Q[0:0] 181s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 181s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 181s 1/1: $0\Q[0:0] 181s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 181s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 181s 1/1: $0\Q[0:0] 181s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 181s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 181s 1/1: $0\Q[0:0] 181s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 181s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 181s 1/1: $0\Q[0:0] 181s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 181s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 181s 1/1: $0\Q[0:0] 181s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 181s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 181s 1/1: $0\Q[0:0] 181s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 181s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 181s 1/1: $0\Q[0:0] 181s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 181s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 181s 1/1: $0\Q[0:0] 181s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 181s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 181s Creating decoders for process `\top.$proc$app2.v:9$390'. 181s Creating decoders for process `\top.$proc$app2.v:8$389'. 181s Creating decoders for process `\top.$proc$app2.v:7$388'. 181s Creating decoders for process `\top.$proc$app2.v:11$381'. 181s 181s 2.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). 181s 181s 2.4.9. Executing PROC_DFF pass (convert process syncs to FFs). 181s Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 181s created $adff cell `$procdff$435' with negative edge clock and positive level reset. 181s Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 181s created $dff cell `$procdff$436' with negative edge clock. 181s Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 181s created $adff cell `$procdff$437' with negative edge clock and positive level reset. 181s Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 181s created $dff cell `$procdff$438' with negative edge clock. 181s Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 181s created $adff cell `$procdff$439' with negative edge clock and positive level reset. 181s Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 181s created $dff cell `$procdff$440' with negative edge clock. 181s Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 181s created $adff cell `$procdff$441' with negative edge clock and positive level reset. 181s Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 181s created $dff cell `$procdff$442' with negative edge clock. 181s Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 181s created $dff cell `$procdff$443' with negative edge clock. 181s Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 181s created $dff cell `$procdff$444' with negative edge clock. 181s Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 181s created $adff cell `$procdff$445' with positive edge clock and positive level reset. 181s Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 181s created $dff cell `$procdff$446' with positive edge clock. 181s Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 181s created $adff cell `$procdff$447' with positive edge clock and positive level reset. 181s Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 181s created $dff cell `$procdff$448' with positive edge clock. 181s Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 181s created $adff cell `$procdff$449' with positive edge clock and positive level reset. 181s Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 181s created $dff cell `$procdff$450' with positive edge clock. 181s Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 181s created $adff cell `$procdff$451' with positive edge clock and positive level reset. 181s Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 181s created $dff cell `$procdff$452' with positive edge clock. 181s Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 181s created $dff cell `$procdff$453' with positive edge clock. 181s Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 181s created $dff cell `$procdff$454' with positive edge clock. 181s Creating register for signal `\top.\counter' using process `\top.$proc$app2.v:11$381'. 181s created $dff cell `$procdff$455' with positive edge clock. 181s Creating register for signal `\top.\counter2' using process `\top.$proc$app2.v:11$381'. 181s created $dff cell `$procdff$456' with positive edge clock. 181s Creating register for signal `\top.\state' using process `\top.$proc$app2.v:11$381'. 181s created $dff cell `$procdff$457' with positive edge clock. 181s 181s 2.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 181s 181s 2.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 181s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 181s Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 181s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 181s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 181s Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 181s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 181s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 181s Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 181s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 181s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 181s Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 181s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 181s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 181s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 181s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 181s Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 181s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 181s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 181s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 181s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 181s Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 181s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 181s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 181s Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 181s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 181s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 181s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 181s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 181s Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 181s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 181s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 181s Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 181s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 181s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 181s Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 181s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 181s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 181s Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 181s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 181s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 181s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 181s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 181s Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 181s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 181s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 181s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 181s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 181s Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 181s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 181s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 181s Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 181s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 181s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 181s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 181s Removing empty process `top.$proc$app2.v:9$390'. 181s Removing empty process `top.$proc$app2.v:8$389'. 181s Removing empty process `top.$proc$app2.v:7$388'. 181s Removing empty process `top.$proc$app2.v:11$381'. 181s Cleaned up 18 empty switches. 181s 181s 2.4.12. Executing OPT_EXPR pass (perform const folding). 181s Optimizing module top. 181s 181s 2.5. Executing FLATTEN pass (flatten design). 181s 181s 2.6. Executing TRIBUF pass. 181s 181s 2.7. Executing DEMINOUT pass (demote inout ports to input or output). 181s 181s 2.8. Executing OPT_EXPR pass (perform const folding). 181s Optimizing module top. 181s 181s 2.9. Executing OPT_CLEAN pass (remove unused cells and wires). 181s Finding unused cells or wires in module \top.. 181s Removed 0 unused cells and 5 unused wires. 181s 181s 181s 2.10. Executing CHECK pass (checking for obvious problems). 181s Checking module top... 181s Found and reported 0 problems. 181s 181s 2.11. Executing OPT pass (performing simple optimizations). 181s 181s 2.11.1. Executing OPT_EXPR pass (perform const folding). 181s Optimizing module top. 181s 181s 2.11.2. Executing OPT_MERGE pass (detect identical cells). 181s Finding identical cells in module `\top'. 181s Removed a total of 0 cells. 181s 181s 2.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 181s Running muxtree optimizer on module \top.. 181s Creating internal representation of mux trees. 181s No muxes found in this module. 181s Removed 0 multiplexer ports. 181s 181s 2.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 181s Optimizing cells in module \top. 181s Performed a total of 0 changes. 181s 181s 2.11.5. Executing OPT_MERGE pass (detect identical cells). 181s Finding identical cells in module `\top'. 181s Removed a total of 0 cells. 181s 181s 2.11.6. Executing OPT_DFF pass (perform DFF optimizations). 181s 181s 2.11.7. Executing OPT_CLEAN pass (remove unused cells and wires). 181s Finding unused cells or wires in module \top.. 181s 181s 2.11.8. Executing OPT_EXPR pass (perform const folding). 181s Optimizing module top. 181s 181s 2.11.9. Finished OPT passes. (There is nothing left to do.) 181s 181s 2.12. Executing FSM pass (extract and optimize FSM). 181s 181s 2.12.1. Executing FSM_DETECT pass (finding FSMs in design). 181s 181s 2.12.2. Executing FSM_EXTRACT pass (extracting FSM from design). 181s 181s 2.12.3. Executing FSM_OPT pass (simple optimizations of FSMs). 181s 181s 2.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). 181s Finding unused cells or wires in module \top.. 181s 181s 2.12.5. Executing FSM_OPT pass (simple optimizations of FSMs). 181s 181s 2.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 181s 181s 2.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 181s 181s 2.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 181s 181s 2.13. Executing OPT pass (performing simple optimizations). 181s 181s 2.13.1. Executing OPT_EXPR pass (perform const folding). 181s Optimizing module top. 181s 181s 2.13.2. Executing OPT_MERGE pass (detect identical cells). 181s Finding identical cells in module `\top'. 181s Removed a total of 0 cells. 181s 181s 2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 181s Running muxtree optimizer on module \top.. 181s Creating internal representation of mux trees. 181s No muxes found in this module. 181s Removed 0 multiplexer ports. 181s 181s 2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 181s Optimizing cells in module \top. 181s Performed a total of 0 changes. 181s 181s 2.13.5. Executing OPT_MERGE pass (detect identical cells). 181s Finding identical cells in module `\top'. 181s Removed a total of 0 cells. 181s 181s 2.13.6. Executing OPT_DFF pass (perform DFF optimizations). 181s 181s 2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). 181s Finding unused cells or wires in module \top.. 181s 181s 2.13.8. Executing OPT_EXPR pass (perform const folding). 181s Optimizing module top. 181s 181s 2.13.9. Finished OPT passes. (There is nothing left to do.) 181s 181s 2.14. Executing WREDUCE pass (reducing word size of cells). 181s Removed top 31 bits (of 32) from port B of cell top.$add$app2.v:12$382 ($add). 181s Removed top 10 bits (of 32) from port Y of cell top.$add$app2.v:12$382 ($add). 181s Removed top 3 bits (of 4) from port B of cell top.$add$app2.v:13$384 ($add). 181s Removed top 3 bits (of 4) from wire top.$logic_not$app2.v:13$383_Y. 181s 181s 2.15. Executing PEEPOPT pass (run peephole optimizers). 181s 181s 2.16. Executing OPT_CLEAN pass (remove unused cells and wires). 181s Finding unused cells or wires in module \top.. 181s Removed 0 unused cells and 2 unused wires. 181s 181s 181s 2.17. Executing SHARE pass (SAT-based resource sharing). 181s 181s 2.18. Executing TECHMAP pass (map to technology primitives). 181s 181s 2.18.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v 181s Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation. 181s Generating RTLIL representation for module `\_90_lut_cmp_'. 181s Successfully finished Verilog frontend. 181s 181s 2.18.2. Continuing TECHMAP pass. 181s No more expansions possible. 181s 181s 181s 2.19. Executing OPT_EXPR pass (perform const folding). 181s Optimizing module top. 181s 181s 2.20. Executing OPT_CLEAN pass (remove unused cells and wires). 181s Finding unused cells or wires in module \top.. 181s 181s 2.21. Executing ALUMACC pass (create $alu and $macc cells). 181s Extracting $alu and $macc cells in module top: 181s creating $macc model for $add$app2.v:12$382 ($add). 181s creating $macc model for $add$app2.v:13$384 ($add). 181s creating $alu model for $macc $add$app2.v:13$384. 181s creating $alu model for $macc $add$app2.v:12$382. 181s creating $alu cell for $add$app2.v:12$382: $auto$alumacc.cc:485:replace_alu$460 181s creating $alu cell for $add$app2.v:13$384: $auto$alumacc.cc:485:replace_alu$463 181s created 2 $alu and 0 $macc cells. 181s 181s 2.22. Executing OPT pass (performing simple optimizations). 181s 181s 2.22.1. Executing OPT_EXPR pass (perform const folding). 181s Optimizing module top. 181s 181s 2.22.2. Executing OPT_MERGE pass (detect identical cells). 181s Finding identical cells in module `\top'. 181s 181s Removed a total of 1 cells. 181s 181s 2.22.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 181s Running muxtree optimizer on module \top.. 181s Creating internal representation of mux trees. 181s No muxes found in this module. 181s Removed 0 multiplexer ports. 181s 181s 2.22.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 181s Optimizing cells in module \top. 181s Performed a total of 0 changes. 181s 181s 2.22.5. Executing OPT_MERGE pass (detect identical cells). 181s Finding identical cells in module `\top'. 181s Removed a total of 0 cells. 181s 181s 2.22.6. Executing OPT_DFF pass (perform DFF optimizations). 181s 181s 2.22.7. Executing OPT_CLEAN pass (remove unused cells and wires). 181s Finding unused cells or wires in module \top.. 181s Removed 0 unused cells and 1 unused wires. 181s 181s 181s 2.22.8. Executing OPT_EXPR pass (perform const folding). 181s Optimizing module top. 181s 181s 2.22.9. Rerunning OPT passes. (Maybe there is more to do..) 181s 181s 2.22.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 181s Running muxtree optimizer on module \top.. 181s Creating internal representation of mux trees. 181s No muxes found in this module. 181s Removed 0 multiplexer ports. 181s 181s 2.22.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 181s Optimizing cells in module \top. 181s Performed a total of 0 changes. 181s 181s 2.22.12. Executing OPT_MERGE pass (detect identical cells). 181s Finding identical cells in module `\top'. 181s Removed a total of 0 cells. 181s 181s 2.22.13. Executing OPT_DFF pass (perform DFF optimizations). 181s 181s 2.22.14. Executing OPT_CLEAN pass (remove unused cells and wires). 181s Finding unused cells or wires in module \top.. 181s 181s 2.22.15. Executing OPT_EXPR pass (perform const folding). 181s Optimizing module top. 181s 181s 2.22.16. Finished OPT passes. (There is nothing left to do.) 181s 181s 2.23. Executing MEMORY pass. 181s 181s 2.23.1. Executing OPT_MEM pass (optimize memories). 181s Performed a total of 0 transformations. 181s 181s 2.23.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). 181s Performed a total of 0 transformations. 181s 181s 2.23.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 181s 181s 2.23.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 181s 181s 2.23.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 181s 181s 2.23.6. Executing OPT_CLEAN pass (remove unused cells and wires). 181s Finding unused cells or wires in module \top.. 181s 181s 2.23.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 181s 181s 2.23.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). 181s Performed a total of 0 transformations. 181s 181s 2.23.9. Executing OPT_CLEAN pass (remove unused cells and wires). 181s Finding unused cells or wires in module \top.. 181s 181s 2.23.10. Executing MEMORY_COLLECT pass (generating $mem cells). 181s 181s 2.24. Executing OPT_CLEAN pass (remove unused cells and wires). 181s Finding unused cells or wires in module \top.. 181s 181s 2.25. Executing MEMORY_LIBMAP pass (mapping memories to cells). 181s 181s 2.26. Executing TECHMAP pass (map to technology primitives). 181s 181s 2.26.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v 182s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation. 182s Generating RTLIL representation for module `\$__ICE40_RAM4K_'. 182s Successfully finished Verilog frontend. 182s 182s 2.26.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/spram_map.v 182s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/spram_map.v' to AST representation. 182s Generating RTLIL representation for module `\$__ICE40_SPRAM_'. 182s Successfully finished Verilog frontend. 182s 182s 2.26.3. Continuing TECHMAP pass. 182s No more expansions possible. 182s 182s 182s 2.27. Executing ICE40_BRAMINIT pass. 182s 182s 2.28. Executing OPT pass (performing simple optimizations). 182s 182s 2.28.1. Executing OPT_EXPR pass (perform const folding). 182s Optimizing module top. 182s 182s 2.28.2. Executing OPT_MERGE pass (detect identical cells). 182s Finding identical cells in module `\top'. 182s Removed a total of 0 cells. 182s 182s 2.28.3. Executing OPT_DFF pass (perform DFF optimizations). 182s 182s 2.28.4. Executing OPT_CLEAN pass (remove unused cells and wires). 182s Finding unused cells or wires in module \top.. 182s 182s 2.28.5. Finished fast OPT passes. 182s 182s 2.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 182s 182s 2.30. Executing OPT pass (performing simple optimizations). 182s 182s 2.30.1. Executing OPT_EXPR pass (perform const folding). 182s Optimizing module top. 182s 182s 2.30.2. Executing OPT_MERGE pass (detect identical cells). 182s Finding identical cells in module `\top'. 182s Removed a total of 0 cells. 182s 182s 2.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 182s Running muxtree optimizer on module \top.. 182s Creating internal representation of mux trees. 182s No muxes found in this module. 182s Removed 0 multiplexer ports. 182s 182s 2.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 182s Optimizing cells in module \top. 182s Performed a total of 0 changes. 182s 182s 2.30.5. Executing OPT_MERGE pass (detect identical cells). 182s Finding identical cells in module `\top'. 182s Removed a total of 0 cells. 182s 182s 2.30.6. Executing OPT_DFF pass (perform DFF optimizations). 182s 182s 2.30.7. Executing OPT_CLEAN pass (remove unused cells and wires). 182s Finding unused cells or wires in module \top.. 182s 182s 2.30.8. Executing OPT_EXPR pass (perform const folding). 182s Optimizing module top. 182s 182s 2.30.9. Finished OPT passes. (There is nothing left to do.) 182s 182s 2.31. Executing ICE40_WRAPCARRY pass (wrap carries). 182s 182s 2.32. Executing TECHMAP pass (map to technology primitives). 182s 182s 2.32.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v 182s Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation. 182s Generating RTLIL representation for module `\_90_simplemap_bool_ops'. 182s Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. 182s Generating RTLIL representation for module `\_90_simplemap_logic_ops'. 182s Generating RTLIL representation for module `\_90_simplemap_compare_ops'. 182s Generating RTLIL representation for module `\_90_simplemap_various'. 182s Generating RTLIL representation for module `\_90_simplemap_registers'. 182s Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. 182s Generating RTLIL representation for module `\_90_shift_shiftx'. 182s Generating RTLIL representation for module `\_90_fa'. 182s Generating RTLIL representation for module `\_90_lcu'. 182s Generating RTLIL representation for module `\_90_alu'. 182s Generating RTLIL representation for module `\_90_macc'. 182s Generating RTLIL representation for module `\_90_alumacc'. 182s Generating RTLIL representation for module `\$__div_mod_u'. 182s Generating RTLIL representation for module `\$__div_mod_trunc'. 182s Generating RTLIL representation for module `\_90_div'. 182s Generating RTLIL representation for module `\_90_mod'. 182s Generating RTLIL representation for module `\$__div_mod_floor'. 182s Generating RTLIL representation for module `\_90_divfloor'. 182s Generating RTLIL representation for module `\_90_modfloor'. 182s Generating RTLIL representation for module `\_90_pow'. 182s Generating RTLIL representation for module `\_90_pmux'. 182s Generating RTLIL representation for module `\_90_demux'. 182s Generating RTLIL representation for module `\_90_lut'. 182s Successfully finished Verilog frontend. 182s 182s 2.32.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v 182s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation. 182s Generating RTLIL representation for module `\_80_ice40_alu'. 182s Successfully finished Verilog frontend. 182s 182s 2.32.3. Continuing TECHMAP pass. 182s Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_80_ice40_alu for cells of type $alu. 182s Using extmapper simplemap for cells of type $logic_not. 182s Using template $paramod$080e6a70eb8bfa1ccf22d9718e795074645029a4\_80_ice40_alu for cells of type $alu. 182s Using extmapper simplemap for cells of type $xor. 182s Using extmapper simplemap for cells of type $reduce_and. 182s Using extmapper simplemap for cells of type $dff. 182s Using extmapper simplemap for cells of type $mux. 182s Using extmapper simplemap for cells of type $not. 182s Using extmapper simplemap for cells of type $pos. 182s No more expansions possible. 182s 182s 182s 2.33. Executing OPT pass (performing simple optimizations). 182s 182s 2.33.1. Executing OPT_EXPR pass (perform const folding). 182s Optimizing module top. 182s 182s 182s 2.33.2. Executing OPT_MERGE pass (detect identical cells). 182s Finding identical cells in module `\top'. 182s 182s Removed a total of 1 cells. 182s 182s 2.33.3. Executing OPT_DFF pass (perform DFF optimizations). 182s 182s 2.33.4. Executing OPT_CLEAN pass (remove unused cells and wires). 182s Finding unused cells or wires in module \top.. 182s Removed 27 unused cells and 34 unused wires. 182s 182s 182s 2.33.5. Finished fast OPT passes. 182s 182s 2.34. Executing ICE40_OPT pass (performing simple optimizations). 182s 182s 2.34.1. Running ICE40 specific optimizations. 182s Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$460.slice[0].carry: CO=\counter [0] 182s 182s 2.34.2. Executing OPT_EXPR pass (perform const folding). 182s Optimizing module top. 182s 182s 2.34.3. Executing OPT_MERGE pass (detect identical cells). 182s Finding identical cells in module `\top'. 182s Removed a total of 0 cells. 182s 182s 2.34.4. Executing OPT_DFF pass (perform DFF optimizations). 182s 182s 2.34.5. Executing OPT_CLEAN pass (remove unused cells and wires). 182s Finding unused cells or wires in module \top.. 182s 182s 2.34.6. Rerunning OPT passes. (Removed registers in this run.) 182s 182s 2.34.7. Running ICE40 specific optimizations. 182s 182s 2.34.8. Executing OPT_EXPR pass (perform const folding). 182s Optimizing module top. 182s 182s 2.34.9. Executing OPT_MERGE pass (detect identical cells). 182s Finding identical cells in module `\top'. 182s Removed a total of 0 cells. 182s 182s 2.34.10. Executing OPT_DFF pass (perform DFF optimizations). 182s 182s 2.34.11. Executing OPT_CLEAN pass (remove unused cells and wires). 182s Finding unused cells or wires in module \top.. 182s 182s 2.34.12. Finished OPT passes. (There is nothing left to do.) 182s 182s 2.35. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 182s 182s 2.36. Executing TECHMAP pass (map to technology primitives). 182s 182s 2.36.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 182s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 182s Generating RTLIL representation for module `\$_DFF_N_'. 182s Generating RTLIL representation for module `\$_DFF_P_'. 182s Generating RTLIL representation for module `\$_DFFE_NP_'. 182s Generating RTLIL representation for module `\$_DFFE_PP_'. 182s Generating RTLIL representation for module `\$_DFF_NP0_'. 182s Generating RTLIL representation for module `\$_DFF_NP1_'. 182s Generating RTLIL representation for module `\$_DFF_PP0_'. 182s Generating RTLIL representation for module `\$_DFF_PP1_'. 182s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 182s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 182s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 182s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 182s Generating RTLIL representation for module `\$_SDFF_NP0_'. 182s Generating RTLIL representation for module `\$_SDFF_NP1_'. 182s Generating RTLIL representation for module `\$_SDFF_PP0_'. 182s Generating RTLIL representation for module `\$_SDFF_PP1_'. 182s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 182s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 182s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 182s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 182s Successfully finished Verilog frontend. 182s 182s 2.36.2. Continuing TECHMAP pass. 182s Using template \$_DFF_P_ for cells of type $_DFF_P_. 182s No more expansions possible. 182s 182s 182s 2.37. Executing OPT_EXPR pass (perform const folding). 182s Optimizing module top. 182s 182s 2.38. Executing SIMPLEMAP pass (map simple cells to gate primitives). 182s Mapping top.$auto$alumacc.cc:485:replace_alu$460.slice[0].carry ($lut). 182s 182s 2.39. Executing ICE40_OPT pass (performing simple optimizations). 182s 182s 2.39.1. Running ICE40 specific optimizations. 182s 182s 2.39.2. Executing OPT_EXPR pass (perform const folding). 182s Optimizing module top. 182s 182s 182s 2.39.3. Executing OPT_MERGE pass (detect identical cells). 182s Finding identical cells in module `\top'. 182s Removed a total of 0 cells. 182s 182s 2.39.4. Executing OPT_DFF pass (perform DFF optimizations). 182s 182s 2.39.5. Executing OPT_CLEAN pass (remove unused cells and wires). 182s Finding unused cells or wires in module \top.. 182s Removed 0 unused cells and 112 unused wires. 182s 182s 182s 2.39.6. Rerunning OPT passes. (Removed registers in this run.) 182s 182s 2.39.7. Running ICE40 specific optimizations. 182s 182s 2.39.8. Executing OPT_EXPR pass (perform const folding). 182s Optimizing module top. 182s 182s 2.39.9. Executing OPT_MERGE pass (detect identical cells). 182s Finding identical cells in module `\top'. 182s Removed a total of 0 cells. 182s 182s 2.39.10. Executing OPT_DFF pass (perform DFF optimizations). 182s 182s 2.39.11. Executing OPT_CLEAN pass (remove unused cells and wires). 182s Finding unused cells or wires in module \top.. 182s 182s 2.39.12. Finished OPT passes. (There is nothing left to do.) 182s 182s 2.40. Executing TECHMAP pass (map to technology primitives). 182s 182s 2.40.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v 182s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation. 182s Generating RTLIL representation for module `\$_DLATCH_N_'. 182s Generating RTLIL representation for module `\$_DLATCH_P_'. 182s Successfully finished Verilog frontend. 182s 182s 2.40.2. Continuing TECHMAP pass. 182s No more expansions possible. 182s 182s 182s 2.41. Executing ABC pass (technology mapping using ABC). 182s 182s 2.41.1. Extracting gate netlist of module `\top' to `/input.blif'.. 182s Extracted 27 gates and 54 wires to a netlist network with 27 inputs and 4 outputs. 182s 182s 2.41.1.1. Executing ABC. 182s Running ABC command: "berkeley-abc" -s -f /abc.script 2>&1 182s ABC: ABC command line: "source /abc.script". 182s ABC: 182s ABC: + read_blif /input.blif 182s ABC: + read_lut /lutdefs.txt 182s ABC: + strash 182s ABC: + &get -n 182s ABC: + &fraig -x 182s ABC: + &put 182s ABC: + scorr 182s ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). 182s ABC: + dc2 182s ABC: + dretime 182s ABC: + strash 182s ABC: + dch -f 182s ABC: + if 182s ABC: + mfs2 182s ABC: + lutpack -S 1 182s ABC: + dress /input.blif 182s ABC: Total number of equiv classes = 5. 182s ABC: Participating nodes from both networks = 9. 182s ABC: Participating nodes from the first network = 4. ( 30.77 % of nodes) 182s ABC: Participating nodes from the second network = 5. ( 38.46 % of nodes) 182s ABC: Node pairs (any polarity) = 4. ( 30.77 % of names can be moved) 182s ABC: Node pairs (same polarity) = 4. ( 30.77 % of names can be moved) 182s ABC: Total runtime = 0.08 sec 182s ABC: + write_blif /output.blif 182s 182s 2.41.1.2. Re-integrating ABC results. 182s ABC RESULTS: $lut cells: 12 182s ABC RESULTS: internal signals: 23 182s ABC RESULTS: input signals: 27 182s ABC RESULTS: output signals: 4 182s Removing temp directory. 182s 182s 2.42. Executing ICE40_WRAPCARRY pass (wrap carries). 182s 182s 2.43. Executing TECHMAP pass (map to technology primitives). 182s 182s 2.43.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 182s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 182s Generating RTLIL representation for module `\$_DFF_N_'. 182s Generating RTLIL representation for module `\$_DFF_P_'. 182s Generating RTLIL representation for module `\$_DFFE_NP_'. 182s Generating RTLIL representation for module `\$_DFFE_PP_'. 182s Generating RTLIL representation for module `\$_DFF_NP0_'. 182s Generating RTLIL representation for module `\$_DFF_NP1_'. 182s Generating RTLIL representation for module `\$_DFF_PP0_'. 182s Generating RTLIL representation for module `\$_DFF_PP1_'. 182s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 182s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 182s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 182s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 182s Generating RTLIL representation for module `\$_SDFF_NP0_'. 182s Generating RTLIL representation for module `\$_SDFF_NP1_'. 182s Generating RTLIL representation for module `\$_SDFF_PP0_'. 182s Generating RTLIL representation for module `\$_SDFF_PP1_'. 182s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 182s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 182s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 182s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 182s Successfully finished Verilog frontend. 182s 182s 2.43.2. Continuing TECHMAP pass. 182s No more expansions possible. 182s 182s Removed 2 unused cells and 39 unused wires. 182s 182s 2.44. Executing OPT_LUT pass (optimize LUTs). 182s Discovering LUTs. 182s Number of LUTs: 37 182s 1-LUT 1 182s 2-LUT 4 182s 3-LUT 25 182s 4-LUT 7 182s with \SB_CARRY (#0) 23 182s with \SB_CARRY (#1) 23 182s 182s Eliminating LUTs. 182s Number of LUTs: 37 182s 1-LUT 1 182s 2-LUT 4 182s 3-LUT 25 182s 4-LUT 7 182s with \SB_CARRY (#0) 23 182s with \SB_CARRY (#1) 23 182s 182s Combining LUTs. 182s Number of LUTs: 37 182s 1-LUT 1 182s 2-LUT 4 182s 3-LUT 25 182s 4-LUT 7 182s with \SB_CARRY (#0) 23 182s with \SB_CARRY (#1) 23 182s 182s Eliminated 0 LUTs. 182s Combined 0 LUTs. 182s 182s 182s 2.45. Executing TECHMAP pass (map to technology primitives). 182s 182s 2.45.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v 182s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation. 182s Generating RTLIL representation for module `\$lut'. 182s Successfully finished Verilog frontend. 182s 182s 2.45.2. Continuing TECHMAP pass. 182s Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut. 182s Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut. 182s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut. 182s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. 182s Using template $paramod$415b9dd3a15783ae56c103f189fd8e182f997441\$lut for cells of type $lut. 182s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. 182s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. 182s Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut. 182s No more expansions possible. 182s 182s Removed 0 unused cells and 78 unused wires. 182s 182s 2.46. Executing AUTONAME pass. 182s Renamed 463 objects in module top (10 iterations). 182s 182s 182s 2.47. Executing HIERARCHY pass (managing design hierarchy). 182s 182s 2.47.1. Analyzing design hierarchy.. 182s Top module: \top 182s 182s 2.47.2. Analyzing design hierarchy.. 182s Top module: \top 182s Removed 0 unused modules. 182s 182s 2.48. Printing statistics. 182s 182s === top === 182s 182s Number of wires: 20 182s Number of wire bits: 99 182s Number of public wires: 20 182s Number of public wire bits: 99 182s Number of memories: 0 182s Number of memory bits: 0 182s Number of processes: 0 182s Number of cells: 88 182s SB_CARRY 23 182s SB_DFF 27 182s SB_LUT4 37 182s SB_WARMBOOT 1 182s 182s 2.49. Executing CHECK pass (checking for obvious problems). 182s Checking module top... 182s Found and reported 0 problems. 182s 182s 2.50. Executing JSON backend. 182s 182s End of script. Logfile hash: 407d82241c, CPU: user 1.01s system 0.01s, MEM: 22.00 MB peak 182s Yosys 0.23 (git sha1 7ce5011c24b) 182s Time spent: 60% 13x read_verilog (0 sec), 13% 1x abc (0 sec), ... 182s nextpnr-ice40 --hx1k --package tq144 --asc app2.asc --pcf icestick.pcf --json app2.json 182s Warning: unmatched constraint 'RX' (on line 4) 182s Warning: unmatched constraint 'TX' (on line 5) 182s Info: constrained 'LED1' to bel 'X13/Y12/io1' 182s Info: constrained 'LED2' to bel 'X13/Y12/io0' 182s Info: constrained 'LED3' to bel 'X13/Y11/io1' 182s Info: constrained 'LED4' to bel 'X13/Y11/io0' 182s Info: constrained 'LED5' to bel 'X13/Y9/io1' 182s Info: constrained 'clk' to bel 'X0/Y8/io1' 182s 182s Info: Packing constants.. 182s Info: Packing IOs.. 182s Info: Packing LUT-FFs.. 182s Info: 10 LCs used as LUT4 only 182s Info: 27 LCs used as LUT4 and DFF 182s Info: Packing non-LUT FFs.. 182s Info: 0 LCs used as DFF only 182s Info: Packing carries.. 182s Info: 0 LCs used as CARRY only 182s Info: Packing indirect carry+LUT pairs... 182s Info: 0 LUTs merged into carry LCs 182s Info: Packing RAMs.. 182s Info: Placing PLLs.. 182s Info: Packing special functions.. 182s Info: Packing PLLs.. 182s Info: Promoting globals.. 182s Info: promoting clk$SB_IO_IN (fanout 27) 182s Info: Constraining chains... 182s Info: 1 LCs used to legalise carry chains. 182s Info: Checksum: 0x56217244 182s 182s Info: Annotating ports with timing budgets for target frequency 12.00 MHz 182s Info: Checksum: 0x1d95d669 182s 182s Info: Device utilisation: 182s Info: ICESTORM_LC: 40/ 1280 3% 182s Info: ICESTORM_RAM: 0/ 16 0% 182s Info: SB_IO: 6/ 112 5% 182s Info: SB_GB: 1/ 8 12% 182s Info: ICESTORM_PLL: 0/ 1 0% 182s Info: SB_WARMBOOT: 1/ 1 100% 182s 182s Info: Placed 6 cells based on constraints. 182s Info: Creating initial analytic placement for 18 cells, random placement wirelen = 338. 182s Info: at initial placer iter 0, wirelen = 21 182s Info: at initial placer iter 1, wirelen = 14 182s Info: at initial placer iter 2, wirelen = 14 182s Info: at initial placer iter 3, wirelen = 14 182s Info: Running main analytical placer, max placement attempts per cell = 10000. 182s Info: at iteration #1, type ICESTORM_LC: wirelen solved = 14, spread = 75, legal = 75; time = 0.00s 182s Info: at iteration #1, type SB_GB: wirelen solved = 75, spread = 75, legal = 75; time = 0.00s 182s Info: at iteration #1, type SB_WARMBOOT: wirelen solved = 72, spread = 72, legal = 110; time = 0.00s 182s Info: at iteration #1, type ALL: wirelen solved = 16, spread = 75, legal = 110; time = 0.00s 182s Info: at iteration #2, type ICESTORM_LC: wirelen solved = 60, spread = 117, legal = 125; time = 0.00s 182s Info: at iteration #2, type SB_GB: wirelen solved = 125, spread = 125, legal = 125; time = 0.00s 182s Info: at iteration #2, type SB_WARMBOOT: wirelen solved = 88, spread = 88, legal = 125; time = 0.00s 182s Info: at iteration #2, type ALL: wirelen solved = 17, spread = 62, legal = 101; time = 0.00s 182s Info: at iteration #3, type ICESTORM_LC: wirelen solved = 62, spread = 99, legal = 107; time = 0.00s 182s Info: at iteration #3, type SB_GB: wirelen solved = 107, spread = 107, legal = 107; time = 0.00s 182s Info: at iteration #3, type SB_WARMBOOT: wirelen solved = 72, spread = 72, legal = 107; time = 0.00s 182s Info: at iteration #3, type ALL: wirelen solved = 18, spread = 68, legal = 104; time = 0.00s 182s Info: at iteration #4, type ICESTORM_LC: wirelen solved = 60, spread = 109, legal = 110; time = 0.00s 182s Info: at iteration #4, type SB_GB: wirelen solved = 110, spread = 110, legal = 110; time = 0.00s 182s Info: at iteration #4, type SB_WARMBOOT: wirelen solved = 77, spread = 77, legal = 110; time = 0.00s 182s Info: at iteration #4, type ALL: wirelen solved = 20, spread = 67, legal = 104; time = 0.00s 182s Info: at iteration #5, type ICESTORM_LC: wirelen solved = 62, spread = 109, legal = 113; time = 0.00s 182s Info: at iteration #5, type SB_GB: wirelen solved = 113, spread = 113, legal = 113; time = 0.00s 182s Info: at iteration #5, type SB_WARMBOOT: wirelen solved = 80, spread = 80, legal = 113; time = 0.00s 182s Info: at iteration #5, type ALL: wirelen solved = 26, spread = 67, legal = 104; time = 0.00s 182s Info: at iteration #6, type ICESTORM_LC: wirelen solved = 62, spread = 109, legal = 113; time = 0.00s 182s Info: at iteration #6, type SB_GB: wirelen solved = 113, spread = 113, legal = 113; time = 0.00s 182s Info: at iteration #6, type SB_WARMBOOT: wirelen solved = 77, spread = 77, legal = 113; time = 0.00s 182s Info: at iteration #6, type ALL: wirelen solved = 24, spread = 70, legal = 104; time = 0.00s 182s Info: at iteration #7, type ICESTORM_LC: wirelen solved = 61, spread = 110, legal = 113; time = 0.00s 182s Info: at iteration #7, type SB_GB: wirelen solved = 113, spread = 113, legal = 113; time = 0.00s 182s Info: at iteration #7, type SB_WARMBOOT: wirelen solved = 82, spread = 82, legal = 113; time = 0.00s 182s Info: at iteration #7, type ALL: wirelen solved = 29, spread = 79, legal = 113; time = 0.00s 182s Info: HeAP Placer Time: 0.02s 182s Info: of which solving equations: 0.02s 182s Info: of which spreading cells: 0.00s 182s Info: of which strict legalisation: 0.00s 182s 182s Info: Running simulated annealing placer for refinement. 182s Info: at iteration #1: temp = 0.000000, timing cost = 10, wirelen = 101 182s Info: at iteration #5: temp = 0.000000, timing cost = 17, wirelen = 79 182s Info: at iteration #10: temp = 0.000000, timing cost = 17, wirelen = 77 182s Info: at iteration #10: temp = 0.000000, timing cost = 17, wirelen = 77 182s Info: SA placement time 0.01s 182s 182s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 192.23 MHz (PASS at 12.00 MHz) 182s 182s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> : 3.87 ns 182s 182s Info: Slack histogram: 182s Info: legend: * represents 1 endpoint(s) 182s Info: + represents [1,1) endpoint(s) 182s Info: [ 78131, 78318) |** 182s Info: [ 78318, 78505) |*** 182s Info: [ 78505, 78692) |* 182s Info: [ 78692, 78879) |*** 182s Info: [ 78879, 79066) |* 182s Info: [ 79066, 79253) | 182s Info: [ 79253, 79440) |* 182s Info: [ 79440, 79627) |*** 182s Info: [ 79627, 79814) |**** 182s Info: [ 79814, 80001) |** 182s Info: [ 80001, 80188) |** 182s Info: [ 80188, 80375) | 182s Info: [ 80375, 80562) | 182s Info: [ 80562, 80749) |** 182s Info: [ 80749, 80936) |* 182s Info: [ 80936, 81123) |** 182s Info: [ 81123, 81310) |* 182s Info: [ 81310, 81497) | 182s Info: [ 81497, 81684) |* 182s Info: [ 81684, 81871) |**************************** 182s Info: Checksum: 0x8c1f252b 182s 182s Info: Routing.. 182s Info: Setting up routing queue. 182s Info: Routing 127 arcs. 182s Info: | (re-)routed arcs | delta | remaining| time spent | 182s Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| 182s Info: 128 | 1 107 | 1 107 | 0| 0.01 0.01| 182s Info: Routing complete. 182s Info: Router1 time 0.01s 182s Info: Checksum: 0xe1821464 182s 182s Info: Critical path report for clock 'clk$SB_IO_IN_$glb_clk' (posedge -> posedge): 182s Info: curr total 182s Info: 0.5 0.5 Source counter_SB_LUT4_I2_3_LC.O 182s Info: 0.6 1.1 Net counter[6] budget 20.292999 ns (12,8) -> (11,9) 182s Info: Sink state_SB_LUT4_I3_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_LC.I0 182s Info: Defined in: 182s Info: app2.v:7.22-7.29 182s Info: 0.4 1.6 Source state_SB_LUT4_I3_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_LC.O 182s Info: 0.6 2.2 Net state_SB_LUT4_I3_I0_SB_LUT4_O_1_I2[0] budget 20.292999 ns (11,9) -> (11,9) 182s Info: Sink state_SB_LUT4_I3_I0_SB_LUT4_O_1_LC.I2 182s Info: Defined in: 182s Info: /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 182s Info: 0.4 2.5 Source state_SB_LUT4_I3_I0_SB_LUT4_O_1_LC.O 182s Info: 0.6 3.1 Net state_SB_LUT4_I3_I0[1] budget 20.292000 ns (11,9) -> (11,9) 182s Info: Sink counter2_SB_LUT4_I2_3_I1_SB_LUT4_O_LC.I2 182s Info: Defined in: 182s Info: /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 182s Info: 0.4 3.5 Source counter2_SB_LUT4_I2_3_I1_SB_LUT4_O_LC.O 182s Info: 0.6 4.1 Net counter2_SB_LUT4_I2_3_I1 budget 20.292000 ns (11,9) -> (11,8) 182s Info: Sink counter2_SB_LUT4_I2_3_LC.I1 182s Info: Defined in: 182s Info: app2.v:13.15-13.34 182s Info: /usr/bin/../share/yosys/ice40/arith_map.v:29.22-29.23 182s Info: 0.3 4.4 Source counter2_SB_LUT4_I2_3_LC.COUT 182s Info: 0.0 4.4 Net counter2_SB_CARRY_I1_CO[1] budget 0.000000 ns (11,8) -> (11,8) 182s Info: Sink counter2_SB_LUT4_I2_2_LC.CIN 182s Info: Defined in: 182s Info: app2.v:13.15-13.34 182s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 182s Info: 0.1 4.5 Source counter2_SB_LUT4_I2_2_LC.COUT 182s Info: 0.0 4.5 Net counter2_SB_CARRY_I1_CO[2] budget 0.000000 ns (11,8) -> (11,8) 182s Info: Sink counter2_SB_LUT4_I2_1_LC.CIN 182s Info: Defined in: 182s Info: app2.v:13.15-13.34 182s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 182s Info: 0.1 4.6 Source counter2_SB_LUT4_I2_1_LC.COUT 182s Info: 0.3 4.9 Net counter2_SB_CARRY_I1_CO[3] budget 0.260000 ns (11,8) -> (11,8) 182s Info: Sink counter2_SB_LUT4_I2_LC.I3 182s Info: Defined in: 182s Info: app2.v:13.15-13.34 182s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 182s Info: 0.3 5.2 Setup counter2_SB_LUT4_I2_LC.I3 182s Info: 2.6 ns logic, 2.6 ns routing 182s 182s Info: Critical path report for cross-domain path 'posedge clk$SB_IO_IN_$glb_clk' -> '': 182s Info: curr total 182s Info: 0.5 0.5 Source counter2_SB_LUT4_I2_3_LC.O 182s Info: 0.6 1.1 Net counter2[0] budget 41.173000 ns (11,8) -> (11,8) 182s Info: Sink WB_BOOT_SB_LUT4_O_LC.I0 182s Info: Defined in: 182s Info: app2.v:8.12-8.20 182s Info: 0.4 1.6 Source WB_BOOT_SB_LUT4_O_LC.O 182s Info: 1.1 2.6 Net WB_BOOT budget 41.172001 ns (11,8) -> (0,0) 182s Info: Sink WB.BOOT 182s Info: Defined in: 182s Info: app2.v:24.9-24.18 182s Info: 1.0 ns logic, 1.7 ns routing 182s 182s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 192.23 MHz (PASS at 12.00 MHz) 182s 182s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> : 2.65 ns 182s 182s Info: Slack histogram: 182s Info: legend: * represents 1 endpoint(s) 182s Info: + represents [1,1) endpoint(s) 182s Info: [ 78131, 78318) |** 182s Info: [ 78318, 78505) |** 182s Info: [ 78505, 78692) |** 182s Info: [ 78692, 78879) |** 182s Info: [ 78879, 79066) |** 182s Info: [ 79066, 79253) | 182s Info: [ 79253, 79440) |* 182s Info: [ 79440, 79627) |* 182s Info: [ 79627, 79814) |***** 182s Info: [ 79814, 80001) |* 182s Info: [ 80001, 80188) |*** 182s Info: [ 80188, 80375) | 182s Info: [ 80375, 80562) | 182s Info: [ 80562, 80749) |*** 182s Info: [ 80749, 80936) |* 182s Info: [ 80936, 81123) |** 182s Info: [ 81123, 81310) |* 182s Info: [ 81310, 81497) | 182s Info: [ 81497, 81684) |* 182s Info: [ 81684, 81871) |**************************** 182s 2 warnings, 0 errors 182s 182s Info: Program finished normally. 182s icetime -d hx1k -c 25 app2.asc 182s // Reading input .asc file.. 182s // Reading 1k chipdb file.. 183s // Creating timing netlist.. 183s // Timing estimate: 5.21 ns (192.09 MHz) 183s // Checking 40.00 ns (25.00 MHz) clock constraint: PASSED. 183s icepack app2.asc app2.bin 183s yosys -p "synth_ice40 -top top -json app3.json" app3.v 183s 183s /----------------------------------------------------------------------------\ 183s | | 183s | yosys -- Yosys Open SYnthesis Suite | 183s | | 183s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 183s | | 183s | Permission to use, copy, modify, and/or distribute this software for any | 183s | purpose with or without fee is hereby granted, provided that the above | 183s | copyright notice and this permission notice appear in all copies. | 183s | | 183s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 183s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 183s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 183s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 183s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 183s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 183s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 183s | | 183s \----------------------------------------------------------------------------/ 183s 183s Yosys 0.23 (git sha1 7ce5011c24b) 183s 183s 183s -- Parsing `app3.v' using frontend ` -vlog2k' -- 183s 183s 1. Executing Verilog-2005 frontend: app3.v 183s Parsing Verilog input from `app3.v' to AST representation. 183s Storing AST representation for module `$abstract\top'. 183s Successfully finished Verilog frontend. 183s 183s -- Running command `synth_ice40 -top top -json app3.json' -- 183s 183s 2. Executing SYNTH_ICE40 pass. 183s 183s 2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v 183s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation. 183s Generating RTLIL representation for module `\SB_IO'. 183s Generating RTLIL representation for module `\SB_GB_IO'. 183s Generating RTLIL representation for module `\SB_GB'. 183s Generating RTLIL representation for module `\SB_LUT4'. 183s Generating RTLIL representation for module `\SB_CARRY'. 183s Generating RTLIL representation for module `\SB_DFF'. 183s Generating RTLIL representation for module `\SB_DFFE'. 183s Generating RTLIL representation for module `\SB_DFFSR'. 183s Generating RTLIL representation for module `\SB_DFFR'. 183s Generating RTLIL representation for module `\SB_DFFSS'. 183s Generating RTLIL representation for module `\SB_DFFS'. 183s Generating RTLIL representation for module `\SB_DFFESR'. 183s Generating RTLIL representation for module `\SB_DFFER'. 183s Generating RTLIL representation for module `\SB_DFFESS'. 183s Generating RTLIL representation for module `\SB_DFFES'. 183s Generating RTLIL representation for module `\SB_DFFN'. 183s Generating RTLIL representation for module `\SB_DFFNE'. 183s Generating RTLIL representation for module `\SB_DFFNSR'. 183s Generating RTLIL representation for module `\SB_DFFNR'. 183s Generating RTLIL representation for module `\SB_DFFNSS'. 183s Generating RTLIL representation for module `\SB_DFFNS'. 183s Generating RTLIL representation for module `\SB_DFFNESR'. 183s Generating RTLIL representation for module `\SB_DFFNER'. 183s Generating RTLIL representation for module `\SB_DFFNESS'. 183s Generating RTLIL representation for module `\SB_DFFNES'. 183s Generating RTLIL representation for module `\SB_RAM40_4K'. 183s Generating RTLIL representation for module `\SB_RAM40_4KNR'. 183s Generating RTLIL representation for module `\SB_RAM40_4KNW'. 183s Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. 183s Generating RTLIL representation for module `\ICESTORM_LC'. 183s Generating RTLIL representation for module `\SB_PLL40_CORE'. 183s Generating RTLIL representation for module `\SB_PLL40_PAD'. 183s Generating RTLIL representation for module `\SB_PLL40_2_PAD'. 183s Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. 183s Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. 183s Generating RTLIL representation for module `\SB_WARMBOOT'. 183s Generating RTLIL representation for module `\SB_SPRAM256KA'. 183s Generating RTLIL representation for module `\SB_HFOSC'. 183s Generating RTLIL representation for module `\SB_LFOSC'. 183s Generating RTLIL representation for module `\SB_RGBA_DRV'. 183s Generating RTLIL representation for module `\SB_LED_DRV_CUR'. 183s Generating RTLIL representation for module `\SB_RGB_DRV'. 183s Generating RTLIL representation for module `\SB_I2C'. 183s Generating RTLIL representation for module `\SB_SPI'. 183s Generating RTLIL representation for module `\SB_LEDDA_IP'. 183s Generating RTLIL representation for module `\SB_FILTER_50NS'. 183s Generating RTLIL representation for module `\SB_IO_I3C'. 183s Generating RTLIL representation for module `\SB_IO_OD'. 183s Generating RTLIL representation for module `\SB_MAC16'. 183s Generating RTLIL representation for module `\ICESTORM_RAM'. 183s Successfully finished Verilog frontend. 183s 183s 2.2. Executing HIERARCHY pass (managing design hierarchy). 183s 183s 2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\top'. 183s Generating RTLIL representation for module `\top'. 183s 183s 2.3.1. Analyzing design hierarchy.. 183s Top module: \top 183s 183s 2.3.2. Analyzing design hierarchy.. 183s Top module: \top 183s Removing unused module `$abstract\top'. 183s Removed 1 unused modules. 183s 183s 2.4. Executing PROC pass (convert processes to netlists). 183s 183s 2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 183s Cleaned up 0 empty switches. 183s 183s 2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 183s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241 in module SB_DFFNES. 183s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234 in module SB_DFFNESS. 183s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230 in module SB_DFFNER. 183s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223 in module SB_DFFNESR. 183s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220 in module SB_DFFNS. 183s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217 in module SB_DFFNSS. 183s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214 in module SB_DFFNR. 183s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211 in module SB_DFFNSR. 183s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203 in module SB_DFFES. 183s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196 in module SB_DFFESS. 183s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192 in module SB_DFFER. 183s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185 in module SB_DFFESR. 183s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182 in module SB_DFFS. 183s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179 in module SB_DFFSS. 183s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176 in module SB_DFFR. 183s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173 in module SB_DFFSR. 183s Removed a total of 0 dead cases. 183s 183s 2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 183s Removed 8 redundant assignments. 183s Promoted 28 assignments to connections. 183s 183s 2.4.4. Executing PROC_INIT pass (extract init attributes). 183s Found init rule in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 183s Set init value: \Q = 1'0 183s Found init rule in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 183s Set init value: \Q = 1'0 183s Found init rule in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 183s Set init value: \Q = 1'0 183s Found init rule in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 183s Set init value: \Q = 1'0 183s Found init rule in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 183s Set init value: \Q = 1'0 183s Found init rule in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 183s Set init value: \Q = 1'0 183s Found init rule in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 183s Set init value: \Q = 1'0 183s Found init rule in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 183s Set init value: \Q = 1'0 183s Found init rule in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 183s Set init value: \Q = 1'0 183s Found init rule in `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 183s Set init value: \Q = 1'0 183s Found init rule in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 183s Set init value: \Q = 1'0 183s Found init rule in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 183s Set init value: \Q = 1'0 183s Found init rule in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 183s Set init value: \Q = 1'0 183s Found init rule in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 183s Set init value: \Q = 1'0 183s Found init rule in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 183s Set init value: \Q = 1'0 183s Found init rule in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 183s Set init value: \Q = 1'0 183s Found init rule in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 183s Set init value: \Q = 1'0 183s Found init rule in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 183s Set init value: \Q = 1'0 183s Found init rule in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 183s Set init value: \Q = 1'0 183s Found init rule in `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 183s Set init value: \Q = 1'0 183s Found init rule in `\top.$proc$app3.v:9$390'. 183s Set init value: \state = 1'0 183s Found init rule in `\top.$proc$app3.v:8$389'. 183s Set init value: \counter2 = 4'0000 183s Found init rule in `\top.$proc$app3.v:7$388'. 183s Set init value: \counter = 22'0000000000000000000000 183s 183s 2.4.5. Executing PROC_ARST pass (detect async resets in processes). 183s Found async reset \S in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 183s Found async reset \R in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 183s Found async reset \S in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 183s Found async reset \R in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 183s Found async reset \S in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 183s Found async reset \R in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 183s Found async reset \S in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 183s Found async reset \R in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 183s 183s 2.4.6. Executing PROC_ROM pass (convert switches to ROMs). 183s Converted 0 switches. 183s 183s 183s 2.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 183s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 183s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 183s 1/1: $0\Q[0:0] 183s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 183s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 183s 1/1: $0\Q[0:0] 183s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 183s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 183s 1/1: $0\Q[0:0] 183s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 183s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 183s 1/1: $0\Q[0:0] 183s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 183s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 183s 1/1: $0\Q[0:0] 183s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 183s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 183s 1/1: $0\Q[0:0] 183s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 183s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 183s 1/1: $0\Q[0:0] 183s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 183s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 183s 1/1: $0\Q[0:0] 183s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 183s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 183s 1/1: $0\Q[0:0] 183s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 183s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 183s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 183s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 183s 1/1: $0\Q[0:0] 183s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 183s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 183s 1/1: $0\Q[0:0] 183s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 183s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 183s 1/1: $0\Q[0:0] 183s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 183s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 183s 1/1: $0\Q[0:0] 183s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 183s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 183s 1/1: $0\Q[0:0] 183s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 183s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 183s 1/1: $0\Q[0:0] 183s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 183s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 183s 1/1: $0\Q[0:0] 183s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 183s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 183s 1/1: $0\Q[0:0] 183s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 183s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 183s 1/1: $0\Q[0:0] 183s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 183s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 183s Creating decoders for process `\top.$proc$app3.v:9$390'. 183s Creating decoders for process `\top.$proc$app3.v:8$389'. 183s Creating decoders for process `\top.$proc$app3.v:7$388'. 183s Creating decoders for process `\top.$proc$app3.v:11$381'. 183s 183s 2.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). 183s 183s 2.4.9. Executing PROC_DFF pass (convert process syncs to FFs). 183s Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 183s created $adff cell `$procdff$435' with negative edge clock and positive level reset. 183s Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 183s created $dff cell `$procdff$436' with negative edge clock. 183s Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 183s created $adff cell `$procdff$437' with negative edge clock and positive level reset. 183s Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 183s created $dff cell `$procdff$438' with negative edge clock. 183s Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 183s created $adff cell `$procdff$439' with negative edge clock and positive level reset. 183s Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 183s created $dff cell `$procdff$440' with negative edge clock. 183s Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 183s created $adff cell `$procdff$441' with negative edge clock and positive level reset. 183s Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 183s created $dff cell `$procdff$442' with negative edge clock. 183s Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 183s created $dff cell `$procdff$443' with negative edge clock. 183s Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 183s created $dff cell `$procdff$444' with negative edge clock. 183s Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 183s created $adff cell `$procdff$445' with positive edge clock and positive level reset. 183s Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 183s created $dff cell `$procdff$446' with positive edge clock. 183s Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 183s created $adff cell `$procdff$447' with positive edge clock and positive level reset. 183s Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 183s created $dff cell `$procdff$448' with positive edge clock. 183s Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 183s created $adff cell `$procdff$449' with positive edge clock and positive level reset. 183s Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 183s created $dff cell `$procdff$450' with positive edge clock. 183s Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 183s created $adff cell `$procdff$451' with positive edge clock and positive level reset. 183s Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 183s created $dff cell `$procdff$452' with positive edge clock. 183s Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 183s created $dff cell `$procdff$453' with positive edge clock. 183s Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 183s created $dff cell `$procdff$454' with positive edge clock. 183s Creating register for signal `\top.\counter' using process `\top.$proc$app3.v:11$381'. 183s created $dff cell `$procdff$455' with positive edge clock. 183s Creating register for signal `\top.\counter2' using process `\top.$proc$app3.v:11$381'. 183s created $dff cell `$procdff$456' with positive edge clock. 183s Creating register for signal `\top.\state' using process `\top.$proc$app3.v:11$381'. 183s created $dff cell `$procdff$457' with positive edge clock. 183s 183s 2.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 183s 183s 2.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 183s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 183s Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 183s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 183s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 183s Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 183s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 183s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 183s Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 183s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 183s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 183s Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 183s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 183s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 183s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 183s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 183s Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 183s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 183s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 183s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 183s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 183s Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 183s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 183s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 183s Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 183s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 183s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 183s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 183s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 183s Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 183s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 183s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 183s Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 183s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 183s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 183s Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 183s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 183s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 183s Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 183s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 183s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 183s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 183s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 183s Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 183s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 183s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 183s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 183s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 183s Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 183s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 183s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 183s Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 183s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 183s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 183s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 183s Removing empty process `top.$proc$app3.v:9$390'. 183s Removing empty process `top.$proc$app3.v:8$389'. 183s Removing empty process `top.$proc$app3.v:7$388'. 183s Removing empty process `top.$proc$app3.v:11$381'. 183s Cleaned up 18 empty switches. 183s 183s 2.4.12. Executing OPT_EXPR pass (perform const folding). 183s Optimizing module top. 183s 183s 2.5. Executing FLATTEN pass (flatten design). 183s 183s 2.6. Executing TRIBUF pass. 183s 183s 2.7. Executing DEMINOUT pass (demote inout ports to input or output). 183s 183s 2.8. Executing OPT_EXPR pass (perform const folding). 183s Optimizing module top. 183s 183s 2.9. Executing OPT_CLEAN pass (remove unused cells and wires). 183s Finding unused cells or wires in module \top.. 183s Removed 0 unused cells and 5 unused wires. 183s 183s 183s 2.10. Executing CHECK pass (checking for obvious problems). 183s Checking module top... 183s Found and reported 0 problems. 183s 183s 2.11. Executing OPT pass (performing simple optimizations). 183s 183s 2.11.1. Executing OPT_EXPR pass (perform const folding). 183s Optimizing module top. 183s 183s 2.11.2. Executing OPT_MERGE pass (detect identical cells). 183s Finding identical cells in module `\top'. 183s Removed a total of 0 cells. 183s 183s 2.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 183s Running muxtree optimizer on module \top.. 183s Creating internal representation of mux trees. 183s No muxes found in this module. 183s Removed 0 multiplexer ports. 183s 183s 2.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 183s Optimizing cells in module \top. 183s Performed a total of 0 changes. 183s 183s 2.11.5. Executing OPT_MERGE pass (detect identical cells). 183s Finding identical cells in module `\top'. 183s Removed a total of 0 cells. 183s 183s 2.11.6. Executing OPT_DFF pass (perform DFF optimizations). 183s 183s 2.11.7. Executing OPT_CLEAN pass (remove unused cells and wires). 183s Finding unused cells or wires in module \top.. 183s 183s 2.11.8. Executing OPT_EXPR pass (perform const folding). 183s Optimizing module top. 183s 183s 2.11.9. Finished OPT passes. (There is nothing left to do.) 183s 183s 2.12. Executing FSM pass (extract and optimize FSM). 183s 183s 2.12.1. Executing FSM_DETECT pass (finding FSMs in design). 183s 183s 2.12.2. Executing FSM_EXTRACT pass (extracting FSM from design). 183s 183s 2.12.3. Executing FSM_OPT pass (simple optimizations of FSMs). 183s 183s 2.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). 183s Finding unused cells or wires in module \top.. 183s 183s 2.12.5. Executing FSM_OPT pass (simple optimizations of FSMs). 183s 183s 2.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 183s 183s 2.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 183s 183s 2.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 183s 183s 2.13. Executing OPT pass (performing simple optimizations). 183s 183s 2.13.1. Executing OPT_EXPR pass (perform const folding). 183s Optimizing module top. 183s 183s 2.13.2. Executing OPT_MERGE pass (detect identical cells). 183s Finding identical cells in module `\top'. 183s Removed a total of 0 cells. 183s 183s 2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 183s Running muxtree optimizer on module \top.. 183s Creating internal representation of mux trees. 183s No muxes found in this module. 183s Removed 0 multiplexer ports. 183s 183s 2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 183s Optimizing cells in module \top. 183s Performed a total of 0 changes. 183s 183s 2.13.5. Executing OPT_MERGE pass (detect identical cells). 183s Finding identical cells in module `\top'. 183s Removed a total of 0 cells. 183s 183s 2.13.6. Executing OPT_DFF pass (perform DFF optimizations). 183s 183s 2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). 183s Finding unused cells or wires in module \top.. 183s 183s 2.13.8. Executing OPT_EXPR pass (perform const folding). 183s Optimizing module top. 183s 183s 2.13.9. Finished OPT passes. (There is nothing left to do.) 183s 183s 2.14. Executing WREDUCE pass (reducing word size of cells). 183s Removed top 31 bits (of 32) from port B of cell top.$add$app3.v:12$382 ($add). 183s Removed top 10 bits (of 32) from port Y of cell top.$add$app3.v:12$382 ($add). 183s Removed top 3 bits (of 4) from port B of cell top.$add$app3.v:13$384 ($add). 183s Removed top 3 bits (of 4) from wire top.$logic_not$app3.v:13$383_Y. 183s 183s 2.15. Executing PEEPOPT pass (run peephole optimizers). 183s 183s 2.16. Executing OPT_CLEAN pass (remove unused cells and wires). 183s Finding unused cells or wires in module \top.. 183s Removed 0 unused cells and 2 unused wires. 183s 183s 183s 2.17. Executing SHARE pass (SAT-based resource sharing). 183s 183s 2.18. Executing TECHMAP pass (map to technology primitives). 183s 183s 2.18.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v 183s Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation. 183s Generating RTLIL representation for module `\_90_lut_cmp_'. 183s Successfully finished Verilog frontend. 183s 183s 2.18.2. Continuing TECHMAP pass. 183s No more expansions possible. 183s 183s 183s 2.19. Executing OPT_EXPR pass (perform const folding). 183s Optimizing module top. 183s 183s 2.20. Executing OPT_CLEAN pass (remove unused cells and wires). 183s Finding unused cells or wires in module \top.. 183s 183s 2.21. Executing ALUMACC pass (create $alu and $macc cells). 183s Extracting $alu and $macc cells in module top: 183s creating $macc model for $add$app3.v:12$382 ($add). 183s creating $macc model for $add$app3.v:13$384 ($add). 183s creating $alu model for $macc $add$app3.v:13$384. 183s creating $alu model for $macc $add$app3.v:12$382. 183s creating $alu cell for $add$app3.v:12$382: $auto$alumacc.cc:485:replace_alu$460 183s creating $alu cell for $add$app3.v:13$384: $auto$alumacc.cc:485:replace_alu$463 183s created 2 $alu and 0 $macc cells. 183s 183s 2.22. Executing OPT pass (performing simple optimizations). 183s 183s 2.22.1. Executing OPT_EXPR pass (perform const folding). 183s Optimizing module top. 183s 183s 2.22.2. Executing OPT_MERGE pass (detect identical cells). 183s Finding identical cells in module `\top'. 183s 183s Removed a total of 1 cells. 183s 183s 2.22.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 183s Running muxtree optimizer on module \top.. 183s Creating internal representation of mux trees. 183s No muxes found in this module. 183s Removed 0 multiplexer ports. 183s 183s 2.22.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 183s Optimizing cells in module \top. 183s Performed a total of 0 changes. 183s 183s 2.22.5. Executing OPT_MERGE pass (detect identical cells). 183s Finding identical cells in module `\top'. 183s Removed a total of 0 cells. 183s 183s 2.22.6. Executing OPT_DFF pass (perform DFF optimizations). 183s 183s 2.22.7. Executing OPT_CLEAN pass (remove unused cells and wires). 183s Finding unused cells or wires in module \top.. 183s Removed 0 unused cells and 1 unused wires. 183s 183s 183s 2.22.8. Executing OPT_EXPR pass (perform const folding). 183s Optimizing module top. 183s 183s 2.22.9. Rerunning OPT passes. (Maybe there is more to do..) 183s 183s 2.22.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 183s Running muxtree optimizer on module \top.. 183s Creating internal representation of mux trees. 183s No muxes found in this module. 183s Removed 0 multiplexer ports. 183s 183s 2.22.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 183s Optimizing cells in module \top. 183s Performed a total of 0 changes. 183s 183s 2.22.12. Executing OPT_MERGE pass (detect identical cells). 183s Finding identical cells in module `\top'. 183s Removed a total of 0 cells. 183s 183s 2.22.13. Executing OPT_DFF pass (perform DFF optimizations). 183s 183s 2.22.14. Executing OPT_CLEAN pass (remove unused cells and wires). 183s Finding unused cells or wires in module \top.. 183s 183s 2.22.15. Executing OPT_EXPR pass (perform const folding). 183s Optimizing module top. 183s 183s 2.22.16. Finished OPT passes. (There is nothing left to do.) 183s 183s 2.23. Executing MEMORY pass. 183s 183s 2.23.1. Executing OPT_MEM pass (optimize memories). 183s Performed a total of 0 transformations. 183s 183s 2.23.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). 183s Performed a total of 0 transformations. 183s 183s 2.23.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 183s 183s 2.23.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 183s 183s 2.23.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 183s 183s 2.23.6. Executing OPT_CLEAN pass (remove unused cells and wires). 183s Finding unused cells or wires in module \top.. 183s 183s 2.23.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 183s 183s 2.23.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). 183s Performed a total of 0 transformations. 183s 183s 2.23.9. Executing OPT_CLEAN pass (remove unused cells and wires). 183s Finding unused cells or wires in module \top.. 183s 183s 2.23.10. Executing MEMORY_COLLECT pass (generating $mem cells). 183s 183s 2.24. Executing OPT_CLEAN pass (remove unused cells and wires). 183s Finding unused cells or wires in module \top.. 183s 183s 2.25. Executing MEMORY_LIBMAP pass (mapping memories to cells). 183s 183s 2.26. Executing TECHMAP pass (map to technology primitives). 183s 183s 2.26.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v 184s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation. 184s Generating RTLIL representation for module `\$__ICE40_RAM4K_'. 184s Successfully finished Verilog frontend. 184s 184s 2.26.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/spram_map.v 184s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/spram_map.v' to AST representation. 184s Generating RTLIL representation for module `\$__ICE40_SPRAM_'. 184s Successfully finished Verilog frontend. 184s 184s 2.26.3. Continuing TECHMAP pass. 184s No more expansions possible. 184s 184s 184s 2.27. Executing ICE40_BRAMINIT pass. 184s 184s 2.28. Executing OPT pass (performing simple optimizations). 184s 184s 2.28.1. Executing OPT_EXPR pass (perform const folding). 184s Optimizing module top. 184s 184s 2.28.2. Executing OPT_MERGE pass (detect identical cells). 184s Finding identical cells in module `\top'. 184s Removed a total of 0 cells. 184s 184s 2.28.3. Executing OPT_DFF pass (perform DFF optimizations). 184s 184s 2.28.4. Executing OPT_CLEAN pass (remove unused cells and wires). 184s Finding unused cells or wires in module \top.. 184s 184s 2.28.5. Finished fast OPT passes. 184s 184s 2.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 184s 184s 2.30. Executing OPT pass (performing simple optimizations). 184s 184s 2.30.1. Executing OPT_EXPR pass (perform const folding). 184s Optimizing module top. 184s 184s 2.30.2. Executing OPT_MERGE pass (detect identical cells). 184s Finding identical cells in module `\top'. 184s Removed a total of 0 cells. 184s 184s 2.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 184s Running muxtree optimizer on module \top.. 184s Creating internal representation of mux trees. 184s No muxes found in this module. 184s Removed 0 multiplexer ports. 184s 184s 2.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 184s Optimizing cells in module \top. 184s Performed a total of 0 changes. 184s 184s 2.30.5. Executing OPT_MERGE pass (detect identical cells). 184s Finding identical cells in module `\top'. 184s Removed a total of 0 cells. 184s 184s 2.30.6. Executing OPT_DFF pass (perform DFF optimizations). 184s 184s 2.30.7. Executing OPT_CLEAN pass (remove unused cells and wires). 184s Finding unused cells or wires in module \top.. 184s 184s 2.30.8. Executing OPT_EXPR pass (perform const folding). 184s Optimizing module top. 184s 184s 2.30.9. Finished OPT passes. (There is nothing left to do.) 184s 184s 2.31. Executing ICE40_WRAPCARRY pass (wrap carries). 184s 184s 2.32. Executing TECHMAP pass (map to technology primitives). 184s 184s 2.32.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v 184s Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation. 184s Generating RTLIL representation for module `\_90_simplemap_bool_ops'. 184s Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. 184s Generating RTLIL representation for module `\_90_simplemap_logic_ops'. 184s Generating RTLIL representation for module `\_90_simplemap_compare_ops'. 184s Generating RTLIL representation for module `\_90_simplemap_various'. 184s Generating RTLIL representation for module `\_90_simplemap_registers'. 184s Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. 184s Generating RTLIL representation for module `\_90_shift_shiftx'. 184s Generating RTLIL representation for module `\_90_fa'. 184s Generating RTLIL representation for module `\_90_lcu'. 184s Generating RTLIL representation for module `\_90_alu'. 184s Generating RTLIL representation for module `\_90_macc'. 184s Generating RTLIL representation for module `\_90_alumacc'. 184s Generating RTLIL representation for module `\$__div_mod_u'. 184s Generating RTLIL representation for module `\$__div_mod_trunc'. 184s Generating RTLIL representation for module `\_90_div'. 184s Generating RTLIL representation for module `\_90_mod'. 184s Generating RTLIL representation for module `\$__div_mod_floor'. 184s Generating RTLIL representation for module `\_90_divfloor'. 184s Generating RTLIL representation for module `\_90_modfloor'. 184s Generating RTLIL representation for module `\_90_pow'. 184s Generating RTLIL representation for module `\_90_pmux'. 184s Generating RTLIL representation for module `\_90_demux'. 184s Generating RTLIL representation for module `\_90_lut'. 184s Successfully finished Verilog frontend. 184s 184s 2.32.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v 184s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation. 184s Generating RTLIL representation for module `\_80_ice40_alu'. 184s Successfully finished Verilog frontend. 184s 184s 2.32.3. Continuing TECHMAP pass. 184s Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_80_ice40_alu for cells of type $alu. 184s Using extmapper simplemap for cells of type $logic_not. 184s Using template $paramod$080e6a70eb8bfa1ccf22d9718e795074645029a4\_80_ice40_alu for cells of type $alu. 184s Using extmapper simplemap for cells of type $xor. 184s Using extmapper simplemap for cells of type $reduce_and. 184s Using extmapper simplemap for cells of type $dff. 184s Using extmapper simplemap for cells of type $mux. 184s Using extmapper simplemap for cells of type $not. 184s Using extmapper simplemap for cells of type $pos. 184s No more expansions possible. 184s 184s 184s 2.33. Executing OPT pass (performing simple optimizations). 184s 184s 2.33.1. Executing OPT_EXPR pass (perform const folding). 184s Optimizing module top. 184s 184s 184s 2.33.2. Executing OPT_MERGE pass (detect identical cells). 184s Finding identical cells in module `\top'. 184s 184s Removed a total of 1 cells. 184s 184s 2.33.3. Executing OPT_DFF pass (perform DFF optimizations). 184s 184s 2.33.4. Executing OPT_CLEAN pass (remove unused cells and wires). 184s Finding unused cells or wires in module \top.. 184s Removed 27 unused cells and 34 unused wires. 184s 184s 184s 2.33.5. Finished fast OPT passes. 184s 184s 2.34. Executing ICE40_OPT pass (performing simple optimizations). 184s 184s 2.34.1. Running ICE40 specific optimizations. 184s Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$460.slice[0].carry: CO=\counter [0] 184s 184s 2.34.2. Executing OPT_EXPR pass (perform const folding). 184s Optimizing module top. 184s 184s 2.34.3. Executing OPT_MERGE pass (detect identical cells). 184s Finding identical cells in module `\top'. 184s Removed a total of 0 cells. 184s 184s 2.34.4. Executing OPT_DFF pass (perform DFF optimizations). 184s 184s 2.34.5. Executing OPT_CLEAN pass (remove unused cells and wires). 184s Finding unused cells or wires in module \top.. 184s 184s 2.34.6. Rerunning OPT passes. (Removed registers in this run.) 184s 184s 2.34.7. Running ICE40 specific optimizations. 184s 184s 2.34.8. Executing OPT_EXPR pass (perform const folding). 184s Optimizing module top. 184s 184s 2.34.9. Executing OPT_MERGE pass (detect identical cells). 184s Finding identical cells in module `\top'. 184s Removed a total of 0 cells. 184s 184s 2.34.10. Executing OPT_DFF pass (perform DFF optimizations). 184s 184s 2.34.11. Executing OPT_CLEAN pass (remove unused cells and wires). 184s Finding unused cells or wires in module \top.. 184s 184s 2.34.12. Finished OPT passes. (There is nothing left to do.) 184s 184s 2.35. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 184s 184s 2.36. Executing TECHMAP pass (map to technology primitives). 184s 184s 2.36.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 184s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 184s Generating RTLIL representation for module `\$_DFF_N_'. 184s Generating RTLIL representation for module `\$_DFF_P_'. 184s Generating RTLIL representation for module `\$_DFFE_NP_'. 184s Generating RTLIL representation for module `\$_DFFE_PP_'. 184s Generating RTLIL representation for module `\$_DFF_NP0_'. 184s Generating RTLIL representation for module `\$_DFF_NP1_'. 184s Generating RTLIL representation for module `\$_DFF_PP0_'. 184s Generating RTLIL representation for module `\$_DFF_PP1_'. 184s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 184s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 184s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 184s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 184s Generating RTLIL representation for module `\$_SDFF_NP0_'. 184s Generating RTLIL representation for module `\$_SDFF_NP1_'. 184s Generating RTLIL representation for module `\$_SDFF_PP0_'. 184s Generating RTLIL representation for module `\$_SDFF_PP1_'. 184s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 184s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 184s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 184s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 184s Successfully finished Verilog frontend. 184s 184s 2.36.2. Continuing TECHMAP pass. 184s Using template \$_DFF_P_ for cells of type $_DFF_P_. 184s No more expansions possible. 184s 184s 184s 2.37. Executing OPT_EXPR pass (perform const folding). 184s Optimizing module top. 184s 184s 2.38. Executing SIMPLEMAP pass (map simple cells to gate primitives). 184s Mapping top.$auto$alumacc.cc:485:replace_alu$460.slice[0].carry ($lut). 184s 184s 2.39. Executing ICE40_OPT pass (performing simple optimizations). 184s 184s 2.39.1. Running ICE40 specific optimizations. 184s 184s 2.39.2. Executing OPT_EXPR pass (perform const folding). 184s Optimizing module top. 184s 184s 184s 2.39.3. Executing OPT_MERGE pass (detect identical cells). 184s Finding identical cells in module `\top'. 184s Removed a total of 0 cells. 184s 184s 2.39.4. Executing OPT_DFF pass (perform DFF optimizations). 184s 184s 2.39.5. Executing OPT_CLEAN pass (remove unused cells and wires). 184s Finding unused cells or wires in module \top.. 184s Removed 0 unused cells and 112 unused wires. 184s 184s 184s 2.39.6. Rerunning OPT passes. (Removed registers in this run.) 184s 184s 2.39.7. Running ICE40 specific optimizations. 184s 184s 2.39.8. Executing OPT_EXPR pass (perform const folding). 184s Optimizing module top. 184s 184s 2.39.9. Executing OPT_MERGE pass (detect identical cells). 184s Finding identical cells in module `\top'. 184s Removed a total of 0 cells. 184s 184s 2.39.10. Executing OPT_DFF pass (perform DFF optimizations). 184s 184s 2.39.11. Executing OPT_CLEAN pass (remove unused cells and wires). 184s Finding unused cells or wires in module \top.. 184s 184s 2.39.12. Finished OPT passes. (There is nothing left to do.) 184s 184s 2.40. Executing TECHMAP pass (map to technology primitives). 184s 184s 2.40.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v 184s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation. 184s Generating RTLIL representation for module `\$_DLATCH_N_'. 184s Generating RTLIL representation for module `\$_DLATCH_P_'. 184s Successfully finished Verilog frontend. 184s 184s 2.40.2. Continuing TECHMAP pass. 184s No more expansions possible. 184s 184s 184s 2.41. Executing ABC pass (technology mapping using ABC). 184s 184s 2.41.1. Extracting gate netlist of module `\top' to `/input.blif'.. 184s Extracted 27 gates and 54 wires to a netlist network with 27 inputs and 4 outputs. 184s 184s 2.41.1.1. Executing ABC. 184s Running ABC command: "berkeley-abc" -s -f /abc.script 2>&1 184s ABC: ABC command line: "source /abc.script". 184s ABC: 184s ABC: + read_blif /input.blif 184s ABC: + read_lut /lutdefs.txt 184s ABC: + strash 184s ABC: + &get -n 184s ABC: + &fraig -x 184s ABC: + &put 184s ABC: + scorr 184s ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). 184s ABC: + dc2 184s ABC: + dretime 184s ABC: + strash 184s ABC: + dch -f 184s ABC: + if 184s ABC: + mfs2 184s ABC: + lutpack -S 1 184s ABC: + dress /input.blif 184s ABC: Total number of equiv classes = 5. 184s ABC: Participating nodes from both networks = 9. 184s ABC: Participating nodes from the first network = 4. ( 30.77 % of nodes) 184s ABC: Participating nodes from the second network = 5. ( 38.46 % of nodes) 184s ABC: Node pairs (any polarity) = 4. ( 30.77 % of names can be moved) 184s ABC: Node pairs (same polarity) = 4. ( 30.77 % of names can be moved) 184s ABC: Total runtime = 0.08 sec 184s ABC: + write_blif /output.blif 184s 184s 2.41.1.2. Re-integrating ABC results. 184s ABC RESULTS: $lut cells: 12 184s ABC RESULTS: internal signals: 23 184s ABC RESULTS: input signals: 27 184s ABC RESULTS: output signals: 4 184s Removing temp directory. 184s 184s 2.42. Executing ICE40_WRAPCARRY pass (wrap carries). 184s 184s 2.43. Executing TECHMAP pass (map to technology primitives). 184s 184s 2.43.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 184s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 184s Generating RTLIL representation for module `\$_DFF_N_'. 184s Generating RTLIL representation for module `\$_DFF_P_'. 184s Generating RTLIL representation for module `\$_DFFE_NP_'. 184s Generating RTLIL representation for module `\$_DFFE_PP_'. 184s Generating RTLIL representation for module `\$_DFF_NP0_'. 184s Generating RTLIL representation for module `\$_DFF_NP1_'. 184s Generating RTLIL representation for module `\$_DFF_PP0_'. 184s Generating RTLIL representation for module `\$_DFF_PP1_'. 184s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 184s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 184s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 184s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 184s Generating RTLIL representation for module `\$_SDFF_NP0_'. 184s Generating RTLIL representation for module `\$_SDFF_NP1_'. 184s Generating RTLIL representation for module `\$_SDFF_PP0_'. 184s Generating RTLIL representation for module `\$_SDFF_PP1_'. 184s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 184s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 184s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 184s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 184s Successfully finished Verilog frontend. 184s 184s 2.43.2. Continuing TECHMAP pass. 184s No more expansions possible. 184s 184s Removed 2 unused cells and 39 unused wires. 184s 184s 2.44. Executing OPT_LUT pass (optimize LUTs). 184s Discovering LUTs. 184s Number of LUTs: 37 184s 1-LUT 1 184s 2-LUT 4 184s 3-LUT 25 184s 4-LUT 7 184s with \SB_CARRY (#0) 23 184s with \SB_CARRY (#1) 23 184s 184s Eliminating LUTs. 184s Number of LUTs: 37 184s 1-LUT 1 184s 2-LUT 4 184s 3-LUT 25 184s 4-LUT 7 184s with \SB_CARRY (#0) 23 184s with \SB_CARRY (#1) 23 184s 184s Combining LUTs. 184s Number of LUTs: 37 184s 1-LUT 1 184s 2-LUT 4 184s 3-LUT 25 184s 4-LUT 7 184s with \SB_CARRY (#0) 23 184s with \SB_CARRY (#1) 23 184s 184s Eliminated 0 LUTs. 184s Combined 0 LUTs. 184s 184s 184s 2.45. Executing TECHMAP pass (map to technology primitives). 184s 184s 2.45.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v 184s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation. 184s Generating RTLIL representation for module `\$lut'. 184s Successfully finished Verilog frontend. 184s 184s 2.45.2. Continuing TECHMAP pass. 184s Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut. 184s Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut. 184s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut. 184s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. 184s Using template $paramod$415b9dd3a15783ae56c103f189fd8e182f997441\$lut for cells of type $lut. 184s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. 184s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. 184s Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut. 184s No more expansions possible. 184s 184s Removed 0 unused cells and 78 unused wires. 184s 184s 2.46. Executing AUTONAME pass. 184s Renamed 463 objects in module top (10 iterations). 184s 184s 184s 2.47. Executing HIERARCHY pass (managing design hierarchy). 184s 184s 2.47.1. Analyzing design hierarchy.. 184s Top module: \top 184s 184s 2.47.2. Analyzing design hierarchy.. 184s Top module: \top 184s Removed 0 unused modules. 184s 184s 2.48. Printing statistics. 184s 184s === top === 184s 184s Number of wires: 20 184s Number of wire bits: 99 184s Number of public wires: 20 184s Number of public wire bits: 99 184s Number of memories: 0 184s Number of memory bits: 0 184s Number of processes: 0 184s Number of cells: 88 184s SB_CARRY 23 184s SB_DFF 27 184s SB_LUT4 37 184s SB_WARMBOOT 1 184s 184s 2.49. Executing CHECK pass (checking for obvious problems). 184s Checking module top... 184s Found and reported 0 problems. 184s 184s 2.50. Executing JSON backend. 184s 184s End of script. Logfile hash: 7ee6023405, CPU: user 1.02s system 0.00s, MEM: 22.00 MB peak 184s Yosys 0.23 (git sha1 7ce5011c24b) 184s Time spent: 60% 13x read_verilog (0 sec), 13% 1x abc (0 sec), ... 184s nextpnr-ice40 --hx1k --package tq144 --asc app3.asc --pcf icestick.pcf --json app3.json 184s Warning: unmatched constraint 'RX' (on line 4) 184s Warning: unmatched constraint 'TX' (on line 5) 184s Info: constrained 'LED1' to bel 'X13/Y12/io1' 184s Info: constrained 'LED2' to bel 'X13/Y12/io0' 184s Info: constrained 'LED3' to bel 'X13/Y11/io1' 184s Info: constrained 'LED4' to bel 'X13/Y11/io0' 184s Info: constrained 'LED5' to bel 'X13/Y9/io1' 184s Info: constrained 'clk' to bel 'X0/Y8/io1' 184s 184s Info: Packing constants.. 184s Info: Packing IOs.. 184s Info: Packing LUT-FFs.. 184s Info: 10 LCs used as LUT4 only 184s Info: 27 LCs used as LUT4 and DFF 184s Info: Packing non-LUT FFs.. 184s Info: 0 LCs used as DFF only 184s Info: Packing carries.. 184s Info: 0 LCs used as CARRY only 184s Info: Packing indirect carry+LUT pairs... 184s Info: 0 LUTs merged into carry LCs 184s Info: Packing RAMs.. 184s Info: Placing PLLs.. 184s Info: Packing special functions.. 184s Info: Packing PLLs.. 184s Info: Promoting globals.. 184s Info: promoting clk$SB_IO_IN (fanout 27) 184s Info: Constraining chains... 184s Info: 1 LCs used to legalise carry chains. 184s Info: Checksum: 0x3e0450db 184s 184s Info: Annotating ports with timing budgets for target frequency 12.00 MHz 184s Info: Checksum: 0x98381def 184s 184s Info: Device utilisation: 184s Info: ICESTORM_LC: 40/ 1280 3% 184s Info: ICESTORM_RAM: 0/ 16 0% 184s Info: SB_IO: 6/ 112 5% 184s Info: SB_GB: 1/ 8 12% 184s Info: ICESTORM_PLL: 0/ 1 0% 184s Info: SB_WARMBOOT: 1/ 1 100% 184s 184s Info: Placed 6 cells based on constraints. 184s Info: Creating initial analytic placement for 18 cells, random placement wirelen = 338. 184s Info: at initial placer iter 0, wirelen = 14 184s Info: at initial placer iter 1, wirelen = 12 184s Info: at initial placer iter 2, wirelen = 12 184s Info: at initial placer iter 3, wirelen = 12 184s Info: Running main analytical placer, max placement attempts per cell = 10000. 184s Info: at iteration #1, type ICESTORM_LC: wirelen solved = 21, spread = 63, legal = 85; time = 0.00s 184s Info: at iteration #1, type SB_GB: wirelen solved = 85, spread = 85, legal = 85; time = 0.00s 184s Info: at iteration #1, type SB_WARMBOOT: wirelen solved = 84, spread = 84, legal = 130; time = 0.00s 184s Info: at iteration #1, type ALL: wirelen solved = 24, spread = 67, legal = 123; time = 0.00s 184s Info: at iteration #2, type ICESTORM_LC: wirelen solved = 67, spread = 115, legal = 139; time = 0.00s 184s Info: at iteration #2, type SB_GB: wirelen solved = 139, spread = 139, legal = 139; time = 0.00s 184s Info: at iteration #2, type SB_WARMBOOT: wirelen solved = 101, spread = 101, legal = 139; time = 0.00s 184s Info: at iteration #2, type ALL: wirelen solved = 15, spread = 72, legal = 118; time = 0.00s 184s Info: at iteration #3, type ICESTORM_LC: wirelen solved = 62, spread = 111, legal = 127; time = 0.00s 184s Info: at iteration #3, type SB_GB: wirelen solved = 127, spread = 127, legal = 127; time = 0.00s 184s Info: at iteration #3, type SB_WARMBOOT: wirelen solved = 85, spread = 85, legal = 127; time = 0.00s 184s Info: at iteration #3, type ALL: wirelen solved = 17, spread = 75, legal = 119; time = 0.00s 184s Info: at iteration #4, type ICESTORM_LC: wirelen solved = 63, spread = 117, legal = 125; time = 0.00s 184s Info: at iteration #4, type SB_GB: wirelen solved = 125, spread = 125, legal = 125; time = 0.00s 184s Info: at iteration #4, type SB_WARMBOOT: wirelen solved = 85, spread = 85, legal = 125; time = 0.00s 184s Info: at iteration #4, type ALL: wirelen solved = 24, spread = 75, legal = 119; time = 0.00s 184s Info: at iteration #5, type ICESTORM_LC: wirelen solved = 63, spread = 117, legal = 125; time = 0.00s 184s Info: at iteration #5, type SB_GB: wirelen solved = 125, spread = 125, legal = 125; time = 0.00s 184s Info: at iteration #5, type SB_WARMBOOT: wirelen solved = 85, spread = 85, legal = 125; time = 0.00s 184s Info: at iteration #5, type ALL: wirelen solved = 27, spread = 82, legal = 122; time = 0.00s 184s Info: at iteration #6, type ICESTORM_LC: wirelen solved = 63, spread = 118, legal = 124; time = 0.00s 184s Info: at iteration #6, type SB_GB: wirelen solved = 124, spread = 124, legal = 124; time = 0.00s 184s Info: at iteration #6, type SB_WARMBOOT: wirelen solved = 86, spread = 86, legal = 124; time = 0.00s 184s Info: at iteration #6, type ALL: wirelen solved = 25, spread = 81, legal = 121; time = 0.00s 184s Info: at iteration #7, type ICESTORM_LC: wirelen solved = 67, spread = 118, legal = 129; time = 0.00s 184s Info: at iteration #7, type SB_GB: wirelen solved = 129, spread = 129, legal = 129; time = 0.00s 184s Info: at iteration #7, type SB_WARMBOOT: wirelen solved = 91, spread = 91, legal = 129; time = 0.00s 184s Info: at iteration #7, type ALL: wirelen solved = 25, spread = 83, legal = 121; time = 0.00s 184s Info: HeAP Placer Time: 0.02s 184s Info: of which solving equations: 0.02s 184s Info: of which spreading cells: 0.00s 184s Info: of which strict legalisation: 0.00s 184s 184s Info: Running simulated annealing placer for refinement. 184s Info: at iteration #1: temp = 0.000000, timing cost = 22, wirelen = 118 184s Info: at iteration #5: temp = 0.000000, timing cost = 13, wirelen = 85 184s Info: at iteration #10: temp = 0.000000, timing cost = 12, wirelen = 83 184s Info: at iteration #12: temp = 0.000000, timing cost = 13, wirelen = 83 184s Info: SA placement time 0.01s 184s 184s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 174.92 MHz (PASS at 12.00 MHz) 184s 184s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> : 4.07 ns 184s 184s Info: Slack histogram: 184s Info: legend: * represents 1 endpoint(s) 184s Info: + represents [1,1) endpoint(s) 184s Info: [ 77616, 77846) |** 184s Info: [ 77846, 78076) |* 184s Info: [ 78076, 78306) |* 184s Info: [ 78306, 78536) |** 184s Info: [ 78536, 78766) |** 184s Info: [ 78766, 78996) |** 184s Info: [ 78996, 79226) | 184s Info: [ 79226, 79456) |**** 184s Info: [ 79456, 79686) |** 184s Info: [ 79686, 79916) |*** 184s Info: [ 79916, 80146) |** 184s Info: [ 80146, 80376) |* 184s Info: [ 80376, 80606) |* 184s Info: [ 80606, 80836) |* 184s Info: [ 80836, 81066) |** 184s Info: [ 81066, 81296) |** 184s Info: [ 81296, 81526) | 184s Info: [ 81526, 81756) | 184s Info: [ 81756, 81986) |**************************** 184s Info: [ 81986, 82216) |* 184s Info: Checksum: 0xe8d6913e 184s 184s Info: Routing.. 184s Info: Setting up routing queue. 184s Info: Routing 127 arcs. 184s Info: | (re-)routed arcs | delta | remaining| time spent | 184s Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| 184s Info: 127 | 0 107 | 0 107 | 0| 0.01 0.01| 184s Info: Routing complete. 184s Info: Router1 time 0.01s 184s Info: Checksum: 0x13664bd1 184s 184s Info: Critical path report for clock 'clk$SB_IO_IN_$glb_clk' (posedge -> posedge): 184s Info: curr total 184s Info: 0.5 0.5 Source counter_SB_LUT4_I2_7_LC.O 184s Info: 0.6 1.1 Net counter[2] budget 20.292999 ns (11,9) -> (12,9) 184s Info: Sink state_SB_LUT4_I3_I0_SB_LUT4_O_2_I3_SB_LUT4_O_LC.I0 184s Info: Defined in: 184s Info: app3.v:7.22-7.29 184s Info: 0.4 1.6 Source state_SB_LUT4_I3_I0_SB_LUT4_O_2_I3_SB_LUT4_O_LC.O 184s Info: 0.6 2.2 Net state_SB_LUT4_I3_I0_SB_LUT4_O_2_I3[2] budget 20.292999 ns (12,9) -> (12,9) 184s Info: Sink state_SB_LUT4_I3_I0_SB_LUT4_O_2_LC.I3 184s Info: Defined in: 184s Info: /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 184s Info: 0.3 2.5 Source state_SB_LUT4_I3_I0_SB_LUT4_O_2_LC.O 184s Info: 1.0 3.4 Net state_SB_LUT4_I3_I0[0] budget 20.292000 ns (12,9) -> (12,11) 184s Info: Sink counter2_SB_LUT4_I2_3_I1_SB_LUT4_O_LC.I1 184s Info: Defined in: 184s Info: /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 184s Info: 0.4 3.8 Source counter2_SB_LUT4_I2_3_I1_SB_LUT4_O_LC.O 184s Info: 0.6 4.4 Net counter2_SB_LUT4_I2_3_I1 budget 20.292000 ns (12,11) -> (12,10) 184s Info: Sink counter2_SB_LUT4_I2_3_LC.I1 184s Info: Defined in: 184s Info: app3.v:13.15-13.34 184s Info: /usr/bin/../share/yosys/ice40/arith_map.v:29.22-29.23 184s Info: 0.3 4.7 Source counter2_SB_LUT4_I2_3_LC.COUT 184s Info: 0.0 4.7 Net counter2_SB_CARRY_I1_CO[1] budget 0.000000 ns (12,10) -> (12,10) 184s Info: Sink counter2_SB_LUT4_I2_2_LC.CIN 184s Info: Defined in: 184s Info: app3.v:13.15-13.34 184s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 184s Info: 0.1 4.8 Source counter2_SB_LUT4_I2_2_LC.COUT 184s Info: 0.0 4.8 Net counter2_SB_CARRY_I1_CO[2] budget 0.000000 ns (12,10) -> (12,10) 184s Info: Sink counter2_SB_LUT4_I2_1_LC.CIN 184s Info: Defined in: 184s Info: app3.v:13.15-13.34 184s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 184s Info: 0.1 4.9 Source counter2_SB_LUT4_I2_1_LC.COUT 184s Info: 0.3 5.2 Net counter2_SB_CARRY_I1_CO[3] budget 0.260000 ns (12,10) -> (12,10) 184s Info: Sink counter2_SB_LUT4_I2_LC.I3 184s Info: Defined in: 184s Info: app3.v:13.15-13.34 184s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 184s Info: 0.3 5.5 Setup counter2_SB_LUT4_I2_LC.I3 184s Info: 2.5 ns logic, 3.0 ns routing 184s 184s Info: Critical path report for cross-domain path 'posedge clk$SB_IO_IN_$glb_clk' -> '': 184s Info: curr total 184s Info: 0.5 0.5 Source counter2_SB_LUT4_I2_3_LC.O 184s Info: 0.6 1.1 Net counter2[0] budget 41.173000 ns (12,10) -> (12,10) 184s Info: Sink WB_BOOT_SB_LUT4_O_LC.I0 184s Info: Defined in: 184s Info: app3.v:8.12-8.20 184s Info: 0.4 1.6 Source WB_BOOT_SB_LUT4_O_LC.O 184s Info: 1.4 3.0 Net WB_BOOT budget 41.172001 ns (12,10) -> (0,0) 184s Info: Sink WB.BOOT 184s Info: Defined in: 184s Info: app3.v:24.9-24.18 184s Info: 1.0 ns logic, 2.0 ns routing 184s 184s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 180.80 MHz (PASS at 12.00 MHz) 184s 184s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> : 3.02 ns 184s 184s Info: Slack histogram: 184s Info: legend: * represents 1 endpoint(s) 184s Info: + represents [1,1) endpoint(s) 184s Info: [ 77802, 78023) |** 184s Info: [ 78023, 78244) |* 184s Info: [ 78244, 78465) |* 184s Info: [ 78465, 78686) |** 184s Info: [ 78686, 78907) |** 184s Info: [ 78907, 79128) |** 184s Info: [ 79128, 79349) | 184s Info: [ 79349, 79570) |**** 184s Info: [ 79570, 79791) |*** 184s Info: [ 79791, 80012) |* 184s Info: [ 80012, 80233) |*** 184s Info: [ 80233, 80454) |* 184s Info: [ 80454, 80675) |* 184s Info: [ 80675, 80896) |** 184s Info: [ 80896, 81117) |** 184s Info: [ 81117, 81338) |* 184s Info: [ 81338, 81559) | 184s Info: [ 81559, 81780) | 184s Info: [ 81780, 82001) |**************************** 184s Info: [ 82001, 82222) |* 184s 2 warnings, 0 errors 184s 184s Info: Program finished normally. 184s icetime -d hx1k -c 25 app3.asc 184s // Reading input .asc file.. 184s // Reading 1k chipdb file.. 184s // Creating timing netlist.. 184s // Timing estimate: 5.61 ns (178.39 MHz) 184s // Checking 40.00 ns (25.00 MHz) clock constraint: PASSED. 184s icepack app3.asc app3.bin 184s icemulti -v -A16 -p0 -o config.bin app0.bin app1.bin app2.bin app3.bin 184s Place image 0 at 010000 .. 020000 (`app0.bin') 184s Place image 1 at 020000 .. 030000 (`app1.bin') 184s Place image 2 at 030000 .. 040000 (`app2.bin') 184s Place image 3 at 040000 .. 050000 (`app3.bin') 184s make: Leaving directory '/tmp/autopkgtest.DyuG3m/build.kB5/src/examples/icemulti' 184s make: Entering directory '/tmp/autopkgtest.DyuG3m/build.kB5/src/examples/icestick' 184s yosys -p 'synth_ice40 -top top -json example.json' example.v 184s 184s /----------------------------------------------------------------------------\ 184s | | 184s | yosys -- Yosys Open SYnthesis Suite | 184s | | 184s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 184s | | 184s | Permission to use, copy, modify, and/or distribute this software for any | 184s | purpose with or without fee is hereby granted, provided that the above | 184s | copyright notice and this permission notice appear in all copies. | 184s | | 184s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 184s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 184s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 184s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 184s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 184s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 184s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 184s | | 184s \----------------------------------------------------------------------------/ 184s 184s Yosys 0.23 (git sha1 7ce5011c24b) 184s 184s 184s -- Parsing `example.v' using frontend ` -vlog2k' -- 184s 184s 1. Executing Verilog-2005 frontend: example.v 184s Parsing Verilog input from `example.v' to AST representation. 184s Storing AST representation for module `$abstract\top'. 184s Successfully finished Verilog frontend. 184s 184s -- Running command `synth_ice40 -top top -json example.json' -- 184s 184s 2. Executing SYNTH_ICE40 pass. 184s 184s 2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v 184s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation. 184s Generating RTLIL representation for module `\SB_IO'. 184s Generating RTLIL representation for module `\SB_GB_IO'. 184s Generating RTLIL representation for module `\SB_GB'. 184s Generating RTLIL representation for module `\SB_LUT4'. 184s Generating RTLIL representation for module `\SB_CARRY'. 184s Generating RTLIL representation for module `\SB_DFF'. 184s Generating RTLIL representation for module `\SB_DFFE'. 184s Generating RTLIL representation for module `\SB_DFFSR'. 184s Generating RTLIL representation for module `\SB_DFFR'. 184s Generating RTLIL representation for module `\SB_DFFSS'. 184s Generating RTLIL representation for module `\SB_DFFS'. 184s Generating RTLIL representation for module `\SB_DFFESR'. 184s Generating RTLIL representation for module `\SB_DFFER'. 184s Generating RTLIL representation for module `\SB_DFFESS'. 184s Generating RTLIL representation for module `\SB_DFFES'. 184s Generating RTLIL representation for module `\SB_DFFN'. 184s Generating RTLIL representation for module `\SB_DFFNE'. 184s Generating RTLIL representation for module `\SB_DFFNSR'. 184s Generating RTLIL representation for module `\SB_DFFNR'. 184s Generating RTLIL representation for module `\SB_DFFNSS'. 184s Generating RTLIL representation for module `\SB_DFFNS'. 184s Generating RTLIL representation for module `\SB_DFFNESR'. 184s Generating RTLIL representation for module `\SB_DFFNER'. 184s Generating RTLIL representation for module `\SB_DFFNESS'. 184s Generating RTLIL representation for module `\SB_DFFNES'. 184s Generating RTLIL representation for module `\SB_RAM40_4K'. 184s Generating RTLIL representation for module `\SB_RAM40_4KNR'. 184s Generating RTLIL representation for module `\SB_RAM40_4KNW'. 184s Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. 184s Generating RTLIL representation for module `\ICESTORM_LC'. 184s Generating RTLIL representation for module `\SB_PLL40_CORE'. 184s Generating RTLIL representation for module `\SB_PLL40_PAD'. 184s Generating RTLIL representation for module `\SB_PLL40_2_PAD'. 184s Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. 184s Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. 184s Generating RTLIL representation for module `\SB_WARMBOOT'. 184s Generating RTLIL representation for module `\SB_SPRAM256KA'. 184s Generating RTLIL representation for module `\SB_HFOSC'. 184s Generating RTLIL representation for module `\SB_LFOSC'. 184s Generating RTLIL representation for module `\SB_RGBA_DRV'. 184s Generating RTLIL representation for module `\SB_LED_DRV_CUR'. 184s Generating RTLIL representation for module `\SB_RGB_DRV'. 184s Generating RTLIL representation for module `\SB_I2C'. 184s Generating RTLIL representation for module `\SB_SPI'. 184s Generating RTLIL representation for module `\SB_LEDDA_IP'. 184s Generating RTLIL representation for module `\SB_FILTER_50NS'. 184s Generating RTLIL representation for module `\SB_IO_I3C'. 184s Generating RTLIL representation for module `\SB_IO_OD'. 184s Generating RTLIL representation for module `\SB_MAC16'. 184s Generating RTLIL representation for module `\ICESTORM_RAM'. 184s Successfully finished Verilog frontend. 184s 184s 2.2. Executing HIERARCHY pass (managing design hierarchy). 184s 184s 2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\top'. 184s Generating RTLIL representation for module `\top'. 184s 184s 2.3.1. Analyzing design hierarchy.. 184s Top module: \top 184s 184s 2.3.2. Analyzing design hierarchy.. 184s Top module: \top 184s Removing unused module `$abstract\top'. 184s Removed 1 unused modules. 184s 184s 2.4. Executing PROC pass (convert processes to netlists). 184s 184s 2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 184s Cleaned up 0 empty switches. 184s 184s 2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 184s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241 in module SB_DFFNES. 184s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234 in module SB_DFFNESS. 184s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230 in module SB_DFFNER. 184s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223 in module SB_DFFNESR. 184s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220 in module SB_DFFNS. 184s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217 in module SB_DFFNSS. 184s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214 in module SB_DFFNR. 184s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211 in module SB_DFFNSR. 184s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203 in module SB_DFFES. 184s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196 in module SB_DFFESS. 184s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192 in module SB_DFFER. 184s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185 in module SB_DFFESR. 184s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182 in module SB_DFFS. 184s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179 in module SB_DFFSS. 184s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176 in module SB_DFFR. 184s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173 in module SB_DFFSR. 184s Removed a total of 0 dead cases. 184s 184s 2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 184s Removed 8 redundant assignments. 184s Promoted 25 assignments to connections. 184s 184s 2.4.4. Executing PROC_INIT pass (extract init attributes). 184s Found init rule in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 184s Set init value: \Q = 1'0 184s Found init rule in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 184s Set init value: \Q = 1'0 184s Found init rule in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 184s Set init value: \Q = 1'0 184s Found init rule in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 184s Set init value: \Q = 1'0 184s Found init rule in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 184s Set init value: \Q = 1'0 184s Found init rule in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 184s Set init value: \Q = 1'0 184s Found init rule in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 184s Set init value: \Q = 1'0 184s Found init rule in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 184s Set init value: \Q = 1'0 184s Found init rule in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 184s Set init value: \Q = 1'0 184s Found init rule in `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 184s Set init value: \Q = 1'0 184s Found init rule in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 184s Set init value: \Q = 1'0 184s Found init rule in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 184s Set init value: \Q = 1'0 184s Found init rule in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 184s Set init value: \Q = 1'0 184s Found init rule in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 184s Set init value: \Q = 1'0 184s Found init rule in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 184s Set init value: \Q = 1'0 184s Found init rule in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 184s Set init value: \Q = 1'0 184s Found init rule in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 184s Set init value: \Q = 1'0 184s Found init rule in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 184s Set init value: \Q = 1'0 184s Found init rule in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 184s Set init value: \Q = 1'0 184s Found init rule in `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 184s Set init value: \Q = 1'0 184s Found init rule in `\top.$proc$example.v:13$386'. 184s Set init value: \counter = 27'000000000000000000000000000 184s 184s 2.4.5. Executing PROC_ARST pass (detect async resets in processes). 184s Found async reset \S in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 184s Found async reset \R in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 184s Found async reset \S in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 184s Found async reset \R in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 184s Found async reset \S in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 184s Found async reset \R in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 184s Found async reset \S in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 184s Found async reset \R in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 184s 184s 2.4.6. Executing PROC_ROM pass (convert switches to ROMs). 184s Converted 0 switches. 184s 184s 184s 2.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 184s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 184s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 184s 1/1: $0\Q[0:0] 184s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 184s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 184s 1/1: $0\Q[0:0] 184s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 184s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 184s 1/1: $0\Q[0:0] 184s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 184s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 184s 1/1: $0\Q[0:0] 184s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 184s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 184s 1/1: $0\Q[0:0] 184s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 184s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 184s 1/1: $0\Q[0:0] 184s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 184s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 184s 1/1: $0\Q[0:0] 184s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 184s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 184s 1/1: $0\Q[0:0] 184s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 184s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 184s 1/1: $0\Q[0:0] 184s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 184s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 184s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 184s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 184s 1/1: $0\Q[0:0] 184s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 184s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 184s 1/1: $0\Q[0:0] 184s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 184s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 184s 1/1: $0\Q[0:0] 184s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 184s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 184s 1/1: $0\Q[0:0] 184s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 184s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 184s 1/1: $0\Q[0:0] 184s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 184s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 184s 1/1: $0\Q[0:0] 184s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 184s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 184s 1/1: $0\Q[0:0] 184s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 184s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 184s 1/1: $0\Q[0:0] 184s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 184s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 184s 1/1: $0\Q[0:0] 184s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 184s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 184s Creating decoders for process `\top.$proc$example.v:13$386'. 184s Creating decoders for process `\top.$proc$example.v:16$381'. 184s 184s 2.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). 184s 184s 2.4.9. Executing PROC_DFF pass (convert process syncs to FFs). 184s Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 184s created $adff cell `$procdff$431' with negative edge clock and positive level reset. 184s Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 184s created $dff cell `$procdff$432' with negative edge clock. 184s Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 184s created $adff cell `$procdff$433' with negative edge clock and positive level reset. 184s Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 184s created $dff cell `$procdff$434' with negative edge clock. 184s Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 184s created $adff cell `$procdff$435' with negative edge clock and positive level reset. 184s Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 184s created $dff cell `$procdff$436' with negative edge clock. 184s Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 184s created $adff cell `$procdff$437' with negative edge clock and positive level reset. 184s Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 184s created $dff cell `$procdff$438' with negative edge clock. 184s Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 184s created $dff cell `$procdff$439' with negative edge clock. 184s Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 184s created $dff cell `$procdff$440' with negative edge clock. 184s Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 184s created $adff cell `$procdff$441' with positive edge clock and positive level reset. 184s Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 184s created $dff cell `$procdff$442' with positive edge clock. 184s Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 184s created $adff cell `$procdff$443' with positive edge clock and positive level reset. 184s Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 184s created $dff cell `$procdff$444' with positive edge clock. 184s Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 184s created $adff cell `$procdff$445' with positive edge clock and positive level reset. 184s Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 184s created $dff cell `$procdff$446' with positive edge clock. 184s Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 184s created $adff cell `$procdff$447' with positive edge clock and positive level reset. 184s Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 184s created $dff cell `$procdff$448' with positive edge clock. 184s Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 184s created $dff cell `$procdff$449' with positive edge clock. 184s Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 184s created $dff cell `$procdff$450' with positive edge clock. 184s Creating register for signal `\top.\counter' using process `\top.$proc$example.v:16$381'. 184s created $dff cell `$procdff$451' with positive edge clock. 184s Creating register for signal `\top.\outcnt' using process `\top.$proc$example.v:16$381'. 184s created $dff cell `$procdff$452' with positive edge clock. 184s 184s 2.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 184s 184s 2.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 184s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 184s Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 184s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 184s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 184s Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 184s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 184s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 184s Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 184s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 184s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 184s Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 184s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 184s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 184s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 184s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 184s Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 184s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 184s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 184s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 184s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 184s Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 184s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 184s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 184s Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 184s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 184s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 184s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 184s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 184s Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 184s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 184s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 184s Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 184s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 184s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 184s Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 184s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 184s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 184s Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 184s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 184s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 184s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 184s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 184s Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 184s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 184s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 184s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 184s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 184s Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 184s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 184s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 184s Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 184s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 184s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 184s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 184s Removing empty process `top.$proc$example.v:13$386'. 184s Removing empty process `top.$proc$example.v:16$381'. 184s Cleaned up 18 empty switches. 184s 184s 2.4.12. Executing OPT_EXPR pass (perform const folding). 184s Optimizing module top. 184s 184s 184s 2.5. Executing FLATTEN pass (flatten design). 184s 184s 2.6. Executing TRIBUF pass. 184s 184s 2.7. Executing DEMINOUT pass (demote inout ports to input or output). 184s 184s 2.8. Executing OPT_EXPR pass (perform const folding). 184s Optimizing module top. 184s 184s 2.9. Executing OPT_CLEAN pass (remove unused cells and wires). 184s Finding unused cells or wires in module \top.. 184s Removed 0 unused cells and 5 unused wires. 184s 184s 184s 2.10. Executing CHECK pass (checking for obvious problems). 184s Checking module top... 184s Found and reported 0 problems. 184s 184s 2.11. Executing OPT pass (performing simple optimizations). 184s 184s 2.11.1. Executing OPT_EXPR pass (perform const folding). 184s Optimizing module top. 184s 184s 2.11.2. Executing OPT_MERGE pass (detect identical cells). 184s Finding identical cells in module `\top'. 184s Removed a total of 0 cells. 184s 184s 2.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 184s Running muxtree optimizer on module \top.. 184s Creating internal representation of mux trees. 184s No muxes found in this module. 184s Removed 0 multiplexer ports. 184s 184s 2.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 184s Optimizing cells in module \top. 184s Performed a total of 0 changes. 184s 184s 2.11.5. Executing OPT_MERGE pass (detect identical cells). 184s Finding identical cells in module `\top'. 184s Removed a total of 0 cells. 184s 184s 2.11.6. Executing OPT_DFF pass (perform DFF optimizations). 184s 184s 2.11.7. Executing OPT_CLEAN pass (remove unused cells and wires). 185s Finding unused cells or wires in module \top.. 185s 185s 2.11.8. Executing OPT_EXPR pass (perform const folding). 185s Optimizing module top. 185s 185s 2.11.9. Finished OPT passes. (There is nothing left to do.) 185s 185s 2.12. Executing FSM pass (extract and optimize FSM). 185s 185s 2.12.1. Executing FSM_DETECT pass (finding FSMs in design). 185s 185s 2.12.2. Executing FSM_EXTRACT pass (extracting FSM from design). 185s 185s 2.12.3. Executing FSM_OPT pass (simple optimizations of FSMs). 185s 185s 2.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). 185s Finding unused cells or wires in module \top.. 185s 185s 2.12.5. Executing FSM_OPT pass (simple optimizations of FSMs). 185s 185s 2.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 185s 185s 2.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 185s 185s 2.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 185s 185s 2.13. Executing OPT pass (performing simple optimizations). 185s 185s 2.13.1. Executing OPT_EXPR pass (perform const folding). 185s Optimizing module top. 185s 185s 2.13.2. Executing OPT_MERGE pass (detect identical cells). 185s Finding identical cells in module `\top'. 185s Removed a total of 0 cells. 185s 185s 2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 185s Running muxtree optimizer on module \top.. 185s Creating internal representation of mux trees. 185s No muxes found in this module. 185s Removed 0 multiplexer ports. 185s 185s 2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 185s Optimizing cells in module \top. 185s Performed a total of 0 changes. 185s 185s 2.13.5. Executing OPT_MERGE pass (detect identical cells). 185s Finding identical cells in module `\top'. 185s Removed a total of 0 cells. 185s 185s 2.13.6. Executing OPT_DFF pass (perform DFF optimizations). 185s 185s 2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). 185s Finding unused cells or wires in module \top.. 185s 185s 2.13.8. Executing OPT_EXPR pass (perform const folding). 185s Optimizing module top. 185s 185s 2.13.9. Finished OPT passes. (There is nothing left to do.) 185s 185s 2.14. Executing WREDUCE pass (reducing word size of cells). 185s Removed top 31 bits (of 32) from port B of cell top.$add$example.v:17$382 ($add). 185s Removed top 5 bits (of 32) from port Y of cell top.$add$example.v:17$382 ($add). 185s Removed top 1 bits (of 5) from port B of cell top.$xor$example.v:21$385 ($xor). 185s 185s 2.15. Executing PEEPOPT pass (run peephole optimizers). 185s 185s 2.16. Executing OPT_CLEAN pass (remove unused cells and wires). 185s Finding unused cells or wires in module \top.. 185s Removed 0 unused cells and 1 unused wires. 185s 185s 185s 2.17. Executing SHARE pass (SAT-based resource sharing). 185s 185s 2.18. Executing TECHMAP pass (map to technology primitives). 185s 185s 2.18.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v 185s Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation. 185s Generating RTLIL representation for module `\_90_lut_cmp_'. 185s Successfully finished Verilog frontend. 185s 185s 2.18.2. Continuing TECHMAP pass. 185s No more expansions possible. 185s 185s 185s 2.19. Executing OPT_EXPR pass (perform const folding). 185s Optimizing module top. 185s 185s 2.20. Executing OPT_CLEAN pass (remove unused cells and wires). 185s Finding unused cells or wires in module \top.. 185s 185s 2.21. Executing ALUMACC pass (create $alu and $macc cells). 185s Extracting $alu and $macc cells in module top: 185s creating $macc model for $add$example.v:17$382 ($add). 185s creating $alu model for $macc $add$example.v:17$382. 185s creating $alu cell for $add$example.v:17$382: $auto$alumacc.cc:485:replace_alu$454 185s created 1 $alu and 0 $macc cells. 185s 185s 2.22. Executing OPT pass (performing simple optimizations). 185s 185s 2.22.1. Executing OPT_EXPR pass (perform const folding). 185s Optimizing module top. 185s 185s 2.22.2. Executing OPT_MERGE pass (detect identical cells). 185s Finding identical cells in module `\top'. 185s Removed a total of 0 cells. 185s 185s 2.22.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 185s Running muxtree optimizer on module \top.. 185s Creating internal representation of mux trees. 185s No muxes found in this module. 185s Removed 0 multiplexer ports. 185s 185s 2.22.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 185s Optimizing cells in module \top. 185s Performed a total of 0 changes. 185s 185s 2.22.5. Executing OPT_MERGE pass (detect identical cells). 185s Finding identical cells in module `\top'. 185s Removed a total of 0 cells. 185s 185s 2.22.6. Executing OPT_DFF pass (perform DFF optimizations). 185s 185s 2.22.7. Executing OPT_CLEAN pass (remove unused cells and wires). 185s Finding unused cells or wires in module \top.. 185s 185s 2.22.8. Executing OPT_EXPR pass (perform const folding). 185s Optimizing module top. 185s 185s 2.22.9. Finished OPT passes. (There is nothing left to do.) 185s 185s 2.23. Executing MEMORY pass. 185s 185s 2.23.1. Executing OPT_MEM pass (optimize memories). 185s Performed a total of 0 transformations. 185s 185s 2.23.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). 185s Performed a total of 0 transformations. 185s 185s 2.23.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 185s 185s 2.23.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 185s 185s 2.23.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 185s 185s 2.23.6. Executing OPT_CLEAN pass (remove unused cells and wires). 185s Finding unused cells or wires in module \top.. 185s 185s 2.23.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 185s 185s 2.23.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). 185s Performed a total of 0 transformations. 185s 185s 2.23.9. Executing OPT_CLEAN pass (remove unused cells and wires). 185s Finding unused cells or wires in module \top.. 185s 185s 2.23.10. Executing MEMORY_COLLECT pass (generating $mem cells). 185s 185s 2.24. Executing OPT_CLEAN pass (remove unused cells and wires). 185s Finding unused cells or wires in module \top.. 185s 185s 2.25. Executing MEMORY_LIBMAP pass (mapping memories to cells). 185s 185s 2.26. Executing TECHMAP pass (map to technology primitives). 185s 185s 2.26.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v 186s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation. 186s Generating RTLIL representation for module `\$__ICE40_RAM4K_'. 186s Successfully finished Verilog frontend. 186s 186s 2.26.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/spram_map.v 186s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/spram_map.v' to AST representation. 186s Generating RTLIL representation for module `\$__ICE40_SPRAM_'. 186s Successfully finished Verilog frontend. 186s 186s 2.26.3. Continuing TECHMAP pass. 186s No more expansions possible. 186s Warning: unmatched constraint 'RX' (on line 4) 186s Warning: unmatched constraint 'TX' (on line 5) 186s 186s 186s 2.27. Executing ICE40_BRAMINIT pass. 186s 186s 2.28. Executing OPT pass (performing simple optimizations). 186s 186s 2.28.1. Executing OPT_EXPR pass (perform const folding). 186s Optimizing module top. 186s 186s 186s 2.28.2. Executing OPT_MERGE pass (detect identical cells). 186s Finding identical cells in module `\top'. 186s Removed a total of 0 cells. 186s 186s 2.28.3. Executing OPT_DFF pass (perform DFF optimizations). 186s 186s 2.28.4. Executing OPT_CLEAN pass (remove unused cells and wires). 186s Finding unused cells or wires in module \top.. 186s Removed 0 unused cells and 2 unused wires. 186s 186s 186s 2.28.5. Finished fast OPT passes. 186s 186s 2.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 186s 186s 2.30. Executing OPT pass (performing simple optimizations). 186s 186s 2.30.1. Executing OPT_EXPR pass (perform const folding). 186s Optimizing module top. 186s 186s 2.30.2. Executing OPT_MERGE pass (detect identical cells). 186s Finding identical cells in module `\top'. 186s Removed a total of 0 cells. 186s 186s 2.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 186s Running muxtree optimizer on module \top.. 186s Creating internal representation of mux trees. 186s No muxes found in this module. 186s Removed 0 multiplexer ports. 186s 186s 2.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 186s Optimizing cells in module \top. 186s Performed a total of 0 changes. 186s 186s 2.30.5. Executing OPT_MERGE pass (detect identical cells). 186s Finding identical cells in module `\top'. 186s Removed a total of 0 cells. 186s 186s 2.30.6. Executing OPT_DFF pass (perform DFF optimizations). 186s 186s 2.30.7. Executing OPT_CLEAN pass (remove unused cells and wires). 186s Finding unused cells or wires in module \top.. 186s 186s 2.30.8. Executing OPT_EXPR pass (perform const folding). 186s Optimizing module top. 186s 186s 2.30.9. Finished OPT passes. (There is nothing left to do.) 186s 186s 2.31. Executing ICE40_WRAPCARRY pass (wrap carries). 186s 186s 2.32. Executing TECHMAP pass (map to technology primitives). 186s 186s 2.32.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v 186s Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation. 186s Generating RTLIL representation for module `\_90_simplemap_bool_ops'. 186s Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. 186s Generating RTLIL representation for module `\_90_simplemap_logic_ops'. 186s Generating RTLIL representation for module `\_90_simplemap_compare_ops'. 186s Generating RTLIL representation for module `\_90_simplemap_various'. 186s Generating RTLIL representation for module `\_90_simplemap_registers'. 186s Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. 186s Generating RTLIL representation for module `\_90_shift_shiftx'. 186s Generating RTLIL representation for module `\_90_fa'. 186s Generating RTLIL representation for module `\_90_lcu'. 186s Generating RTLIL representation for module `\_90_alu'. 186s Generating RTLIL representation for module `\_90_macc'. 186s Generating RTLIL representation for module `\_90_alumacc'. 186s Generating RTLIL representation for module `\$__div_mod_u'. 186s Generating RTLIL representation for module `\$__div_mod_trunc'. 186s Generating RTLIL representation for module `\_90_div'. 186s Generating RTLIL representation for module `\_90_mod'. 186s Generating RTLIL representation for module `\$__div_mod_floor'. 186s Generating RTLIL representation for module `\_90_divfloor'. 186s Generating RTLIL representation for module `\_90_modfloor'. 186s Generating RTLIL representation for module `\_90_pow'. 186s Generating RTLIL representation for module `\_90_pmux'. 186s Generating RTLIL representation for module `\_90_demux'. 186s Generating RTLIL representation for module `\_90_lut'. 186s Successfully finished Verilog frontend. 186s 186s 2.32.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v 186s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation. 186s Generating RTLIL representation for module `\_80_ice40_alu'. 186s Successfully finished Verilog frontend. 186s 186s 2.32.3. Continuing TECHMAP pass. 186s Using template $paramod$956e79e8f8c5e64be7438155ae50a966e615cb04\_80_ice40_alu for cells of type $alu. 186s Using extmapper simplemap for cells of type $xor. 186s Using extmapper simplemap for cells of type $dff. 186s Using extmapper simplemap for cells of type $mux. 186s Using extmapper simplemap for cells of type $not. 186s Using extmapper simplemap for cells of type $pos. 186s No more expansions possible. 186s 186s 186s 2.33. Executing OPT pass (performing simple optimizations). 186s 186s 2.33.1. Executing OPT_EXPR pass (perform const folding). 186s Optimizing module top. 186s 186s 186s 2.33.2. Executing OPT_MERGE pass (detect identical cells). 186s Finding identical cells in module `\top'. 186s 186s Removed a total of 1 cells. 186s 186s 2.33.3. Executing OPT_DFF pass (perform DFF optimizations). 186s 186s 2.33.4. Executing OPT_CLEAN pass (remove unused cells and wires). 186s Finding unused cells or wires in module \top.. 186s Removed 27 unused cells and 17 unused wires. 186s 186s 186s 2.33.5. Finished fast OPT passes. 186s 186s 2.34. Executing ICE40_OPT pass (performing simple optimizations). 186s 186s 2.34.1. Running ICE40 specific optimizations. 186s Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$454.slice[0].carry: CO=\counter [0] 186s 186s 2.34.2. Executing OPT_EXPR pass (perform const folding). 186s Optimizing module top. 186s 186s 2.34.3. Executing OPT_MERGE pass (detect identical cells). 186s Finding identical cells in module `\top'. 186s Removed a total of 0 cells. 186s 186s 2.34.4. Executing OPT_DFF pass (perform DFF optimizations). 186s 186s 2.34.5. Executing OPT_CLEAN pass (remove unused cells and wires). 186s Finding unused cells or wires in module \top.. 186s 186s 2.34.6. Rerunning OPT passes. (Removed registers in this run.) 186s 186s 2.34.7. Running ICE40 specific optimizations. 186s 186s 2.34.8. Executing OPT_EXPR pass (perform const folding). 186s Optimizing module top. 186s 186s 2.34.9. Executing OPT_MERGE pass (detect identical cells). 186s Finding identical cells in module `\top'. 186s Removed a total of 0 cells. 186s 186s 2.34.10. Executing OPT_DFF pass (perform DFF optimizations). 186s 186s 2.34.11. Executing OPT_CLEAN pass (remove unused cells and wires). 186s Finding unused cells or wires in module \top.. 186s 186s 2.34.12. Finished OPT passes. (There is nothing left to do.) 186s 186s 2.35. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 186s 186s 2.36. Executing TECHMAP pass (map to technology primitives). 186s 186s 2.36.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 186s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 186s Generating RTLIL representation for module `\$_DFF_N_'. 186s Generating RTLIL representation for module `\$_DFF_P_'. 186s Generating RTLIL representation for module `\$_DFFE_NP_'. 186s Generating RTLIL representation for module `\$_DFFE_PP_'. 186s Generating RTLIL representation for module `\$_DFF_NP0_'. 186s Generating RTLIL representation for module `\$_DFF_NP1_'. 186s Generating RTLIL representation for module `\$_DFF_PP0_'. 186s Generating RTLIL representation for module `\$_DFF_PP1_'. 186s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 186s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 186s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 186s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 186s Generating RTLIL representation for module `\$_SDFF_NP0_'. 186s Generating RTLIL representation for module `\$_SDFF_NP1_'. 186s Generating RTLIL representation for module `\$_SDFF_PP0_'. 186s Generating RTLIL representation for module `\$_SDFF_PP1_'. 186s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 186s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 186s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 186s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 186s Successfully finished Verilog frontend. 186s 186s 2.36.2. Continuing TECHMAP pass. 186s Using template \$_DFF_P_ for cells of type $_DFF_P_. 186s No more expansions possible. 186s 186s 186s 2.37. Executing OPT_EXPR pass (perform const folding). 186s Optimizing module top. 186s 186s 2.38. Executing SIMPLEMAP pass (map simple cells to gate primitives). 186s Mapping top.$auto$alumacc.cc:485:replace_alu$454.slice[0].carry ($lut). 186s 186s 2.39. Executing ICE40_OPT pass (performing simple optimizations). 186s 186s 2.39.1. Running ICE40 specific optimizations. 186s 186s 2.39.2. Executing OPT_EXPR pass (perform const folding). 186s Optimizing module top. 186s 186s 186s 2.39.3. Executing OPT_MERGE pass (detect identical cells). 186s Finding identical cells in module `\top'. 186s Removed a total of 0 cells. 186s 186s 2.39.4. Executing OPT_DFF pass (perform DFF optimizations). 186s 186s 2.39.5. Executing OPT_CLEAN pass (remove unused cells and wires). 186s Finding unused cells or wires in module \top.. 186s Removed 0 unused cells and 132 unused wires. 186s 186s 186s 2.39.6. Rerunning OPT passes. (Removed registers in this run.) 186s 186s 2.39.7. Running ICE40 specific optimizations. 186s 186s 2.39.8. Executing OPT_EXPR pass (perform const folding). 186s Optimizing module top. 186s 186s 2.39.9. Executing OPT_MERGE pass (detect identical cells). 186s Finding identical cells in module `\top'. 186s Removed a total of 0 cells. 186s 186s 2.39.10. Executing OPT_DFF pass (perform DFF optimizations). 186s 186s 2.39.11. Executing OPT_CLEAN pass (remove unused cells and wires). 186s Finding unused cells or wires in module \top.. 186s 186s 2.39.12. Finished OPT passes. (There is nothing left to do.) 186s 186s 2.40. Executing TECHMAP pass (map to technology primitives). 186s 186s 2.40.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v 186s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation. 186s Generating RTLIL representation for module `\$_DLATCH_N_'. 186s Generating RTLIL representation for module `\$_DLATCH_P_'. 186s Successfully finished Verilog frontend. 186s 186s 2.40.2. Continuing TECHMAP pass. 186s No more expansions possible. 186s 186s 186s 2.41. Executing ABC pass (technology mapping using ABC). 186s 186s 2.41.1. Extracting gate netlist of module `\top' to `/input.blif'.. 186s Extracted 5 gates and 11 wires to a netlist network with 6 inputs and 5 outputs. 186s 186s 2.41.1.1. Executing ABC. 186s Running ABC command: "berkeley-abc" -s -f /abc.script 2>&1 186s ABC: ABC command line: "source /abc.script". 186s ABC: 186s ABC: + read_blif /input.blif 186s ABC: + read_lut /lutdefs.txt 186s ABC: + strash 186s ABC: + &get -n 186s ABC: + &fraig -x 186s ABC: + &put 186s ABC: + scorr 186s ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). 186s ABC: + dc2 186s ABC: + dretime 186s ABC: + strash 186s ABC: + dch -f 186s ABC: + if 186s ABC: + mfs2 186s ABC: + lutpack -S 1 186s ABC: + dress /input.blif 186s ABC: Total number of equiv classes = 6. 186s ABC: Participating nodes from both networks = 10. 186s ABC: Participating nodes from the first network = 5. ( 83.33 % of nodes) 186s ABC: Participating nodes from the second network = 5. ( 83.33 % of nodes) 186s ABC: Node pairs (any polarity) = 5. ( 83.33 % of names can be moved) 186s ABC: Node pairs (same polarity) = 5. ( 83.33 % of names can be moved) 186s ABC: Total runtime = 0.00 sec 186s ABC: + write_blif /output.blif 186s 186s 2.41.1.2. Re-integrating ABC results. 186s ABC RESULTS: $lut cells: 5 186s ABC RESULTS: internal signals: 0 186s ABC RESULTS: input signals: 6 186s ABC RESULTS: output signals: 5 186s Removing temp directory. 186s 186s 2.42. Executing ICE40_WRAPCARRY pass (wrap carries). 186s 186s 2.43. Executing TECHMAP pass (map to technology primitives). 186s 186s 2.43.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 186s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 186s Generating RTLIL representation for module `\$_DFF_N_'. 186s Generating RTLIL representation for module `\$_DFF_P_'. 186s Generating RTLIL representation for module `\$_DFFE_NP_'. 186s Generating RTLIL representation for module `\$_DFFE_PP_'. 186s Generating RTLIL representation for module `\$_DFF_NP0_'. 186s Generating RTLIL representation for module `\$_DFF_NP1_'. 186s Generating RTLIL representation for module `\$_DFF_PP0_'. 186s Generating RTLIL representation for module `\$_DFF_PP1_'. 186s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 186s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 186s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 186s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 186s Generating RTLIL representation for module `\$_SDFF_NP0_'. 186s Generating RTLIL representation for module `\$_SDFF_NP1_'. 186s Generating RTLIL representation for module `\$_SDFF_PP0_'. 186s Generating RTLIL representation for module `\$_SDFF_PP1_'. 186s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 186s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 186s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 186s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 186s Successfully finished Verilog frontend. 186s 186s 2.43.2. Continuing TECHMAP pass. 186s No more expansions possible. 186s 186s Removed 1 unused cells and 12 unused wires. 186s 186s 2.44. Executing OPT_LUT pass (optimize LUTs). 186s Discovering LUTs. 186s Number of LUTs: 31 186s 1-LUT 1 186s 2-LUT 5 186s 3-LUT 25 186s with \SB_CARRY (#0) 25 186s with \SB_CARRY (#1) 25 186s 186s Eliminating LUTs. 186s Number of LUTs: 31 186s 1-LUT 1 186s 2-LUT 5 186s 3-LUT 25 186s with \SB_CARRY (#0) 25 186s with \SB_CARRY (#1) 25 186s 186s Combining LUTs. 186s Number of LUTs: 31 186s 1-LUT 1 186s 2-LUT 5 186s 3-LUT 25 186s with \SB_CARRY (#0) 25 186s with \SB_CARRY (#1) 25 186s 186s Eliminated 0 LUTs. 186s Combined 0 LUTs. 186s 186s 186s 2.45. Executing TECHMAP pass (map to technology primitives). 186s 186s 2.45.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v 186s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation. 186s Generating RTLIL representation for module `\$lut'. 186s Successfully finished Verilog frontend. 186s 186s 2.45.2. Continuing TECHMAP pass. 186s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut. 186s Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut. 186s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. 186s No more expansions possible. 186s 186s Removed 0 unused cells and 62 unused wires. 186s 186s 2.46. Executing AUTONAME pass. 186s Renamed 142 objects in module top (4 iterations). 186s 186s 186s 2.47. Executing HIERARCHY pass (managing design hierarchy). 186s 186s 2.47.1. Analyzing design hierarchy.. 186s Top module: \top 186s 186s 2.47.2. Analyzing design hierarchy.. 186s Top module: \top 186s Removed 0 unused modules. 186s 186s 2.48. Printing statistics. 186s 186s === top === 186s 186s Number of wires: 10 186s Number of wire bits: 92 186s Number of public wires: 10 186s Number of public wire bits: 92 186s Number of memories: 0 186s Number of memory bits: 0 186s Number of processes: 0 186s Number of cells: 88 186s SB_CARRY 25 186s SB_DFF 32 186s SB_LUT4 31 186s 186s 2.49. Executing CHECK pass (checking for obvious problems). 186s Checking module top... 186s Found and reported 0 problems. 186s 186s 2.50. Executing JSON backend. 186s 186s End of script. Logfile hash: 7b17f9bd89, CPU: user 0.99s system 0.01s, MEM: 22.00 MB peak 186s Yosys 0.23 (git sha1 7ce5011c24b) 186s Time spent: 68% 13x read_verilog (0 sec), 6% 1x synth_ice40 (0 sec), ... 186s nextpnr-ice40 --hx1k --package tq144 --asc example.asc --pcf icestick.pcf --json example.json 186s Info: constrained 'LED1' to bel 'X13/Y12/io1' 186s Info: constrained 'LED2' to bel 'X13/Y12/io0' 186s Info: constrained 'LED3' to bel 'X13/Y11/io1' 186s Info: constrained 'LED4' to bel 'X13/Y11/io0' 186s Info: constrained 'LED5' to bel 'X13/Y9/io1' 186s Info: constrained 'clk' to bel 'X0/Y8/io1' 186s 186s Info: Packing constants.. 186s Info: Packing IOs.. 186s Info: Packing LUT-FFs.. 186s Info: 4 LCs used as LUT4 only 186s Info: 27 LCs used as LUT4 and DFF 186s Info: Packing non-LUT FFs.. 186s Info: 5 LCs used as DFF only 186s Info: Packing carries.. 186s Info: 0 LCs used as CARRY only 186s Info: Packing indirect carry+LUT pairs... 186s Info: 0 LUTs merged into carry LCs 186s Info: Packing RAMs.. 186s Info: Placing PLLs.. 186s Info: Packing special functions.. 186s Info: Packing PLLs.. 186s Info: Promoting globals.. 186s Info: promoting clk$SB_IO_IN (fanout 32) 186s Info: Constraining chains... 186s Info: 1 LCs used to legalise carry chains. 186s Info: Checksum: 0xae2b0ce7 186s 186s Info: Annotating ports with timing budgets for target frequency 12.00 MHz 186s Info: Checksum: 0x993bf822 186s 186s Info: Device utilisation: 186s Info: ICESTORM_LC: 39/ 1280 3% 186s Info: ICESTORM_RAM: 0/ 16 0% 186s Info: SB_IO: 6/ 112 5% 186s Info: SB_GB: 1/ 8 12% 186s Info: ICESTORM_PLL: 0/ 1 0% 186s Info: SB_WARMBOOT: 0/ 1 0% 186s 186s Info: Placed 6 cells based on constraints. 186s Info: Creating initial analytic placement for 12 cells, random placement wirelen = 182. 186s Info: at initial placer iter 0, wirelen = 16 186s Info: at initial placer iter 1, wirelen = 16 186s Info: at initial placer iter 2, wirelen = 18 186s Info: at initial placer iter 3, wirelen = 18 186s Info: Running main analytical placer, max placement attempts per cell = 10000. 186s Info: at iteration #1, type ICESTORM_LC: wirelen solved = 19, spread = 34, legal = 36; time = 0.00s 186s Info: at iteration #1, type SB_GB: wirelen solved = 36, spread = 36, legal = 36; time = 0.00s 186s Info: at iteration #1, type ALL: wirelen solved = 17, spread = 33, legal = 33; time = 0.00s 186s Info: at iteration #2, type ICESTORM_LC: wirelen solved = 17, spread = 31, legal = 32; time = 0.00s 186s Info: at iteration #2, type SB_GB: wirelen solved = 32, spread = 32, legal = 32; time = 0.00s 186s Info: at iteration #2, type ALL: wirelen solved = 17, spread = 31, legal = 32; time = 0.00s 186s Info: at iteration #3, type ICESTORM_LC: wirelen solved = 15, spread = 36, legal = 37; time = 0.00s 186s Info: at iteration #3, type SB_GB: wirelen solved = 37, spread = 37, legal = 37; time = 0.00s 186s Info: at iteration #3, type ALL: wirelen solved = 15, spread = 36, legal = 38; time = 0.00s 186s Info: at iteration #4, type ICESTORM_LC: wirelen solved = 15, spread = 37, legal = 38; time = 0.00s 186s Info: at iteration #4, type SB_GB: wirelen solved = 38, spread = 38, legal = 38; time = 0.00s 186s Info: at iteration #4, type ALL: wirelen solved = 15, spread = 37, legal = 38; time = 0.00s 186s Info: at iteration #5, type ICESTORM_LC: wirelen solved = 20, spread = 38, legal = 40; time = 0.00s 186s Info: at iteration #5, type SB_GB: wirelen solved = 40, spread = 40, legal = 40; time = 0.00s 186s Info: at iteration #5, type ALL: wirelen solved = 20, spread = 38, legal = 39; time = 0.00s 186s Info: at iteration #6, type ICESTORM_LC: wirelen solved = 20, spread = 39, legal = 40; time = 0.00s 186s Info: at iteration #6, type SB_GB: wirelen solved = 40, spread = 40, legal = 40; time = 0.00s 186s Info: at iteration #6, type ALL: wirelen solved = 20, spread = 39, legal = 41; time = 0.00s 186s Info: at iteration #7, type ICESTORM_LC: wirelen solved = 27, spread = 39, legal = 41; time = 0.00s 186s Info: at iteration #7, type SB_GB: wirelen solved = 41, spread = 41, legal = 41; time = 0.00s 186s Info: at iteration #7, type ALL: wirelen solved = 27, spread = 39, legal = 40; time = 0.00s 186s Info: HeAP Placer Time: 0.02s 186s Info: of which solving equations: 0.01s 186s Info: of which spreading cells: 0.00s 186s Info: of which strict legalisation: 0.00s 186s 186s Info: Running simulated annealing placer for refinement. 186s Info: at iteration #1: temp = 0.000000, timing cost = 4, wirelen = 32 186s Info: at iteration #5: temp = 0.000000, timing cost = 4, wirelen = 21 186s Info: at iteration #9: temp = 0.000000, timing cost = 4, wirelen = 21 186s Info: SA placement time 0.01s 186s 186s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 170.01 MHz (PASS at 12.00 MHz) 186s 186s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> : 2.09 ns 186s 186s Info: Slack histogram: 186s Info: legend: * represents 1 endpoint(s) 186s Info: + represents [1,1) endpoint(s) 186s Info: [ 77451, 77672) |*** 186s Info: [ 77672, 77893) | 186s Info: [ 77893, 78114) |* 186s Info: [ 78114, 78335) |** 186s Info: [ 78335, 78556) |* 186s Info: [ 78556, 78777) |** 186s Info: [ 78777, 78998) |** 186s Info: [ 78998, 79219) | 186s Info: [ 79219, 79440) |* 186s Info: [ 79440, 79661) |** 186s Info: [ 79661, 79882) |** 186s Info: [ 79882, 80103) |** 186s Info: [ 80103, 80324) |* 186s Info: [ 80324, 80545) | 186s Info: [ 80545, 80766) |** 186s Info: [ 80766, 80987) |** 186s Info: [ 80987, 81208) |* 186s Info: [ 81208, 81429) |***** 186s Info: [ 81429, 81650) |* 186s Info: [ 81650, 81871) |********************************* 186s Info: Checksum: 0xa2e17380 186s 186s Info: Routing.. 186s Info: Setting up routing queue. 186s Info: Routing 106 arcs. 186s Info: | (re-)routed arcs | delta | remaining| time spent | 186s Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| 186s Info: 106 | 0 84 | 0 84 | 0| 0.00 0.00| 186s Info: Routing complete. 186s Info: Router1 time 0.00s 186s Info: Checksum: 0x30991612 186s 186s Info: Critical path report for clock 'clk$SB_IO_IN_$glb_clk' (posedge -> posedge): 186s Info: curr total 186s Info: 0.5 0.5 Source counter_SB_LUT4_I3_LC.O 186s Info: 0.6 1.1 Net counter[0] budget 78.740997 ns (11,6) -> (11,7) 186s Info: Sink $nextpnr_ICESTORM_LC_0.I1 186s Info: Defined in: 186s Info: example.v:17.14-17.25 186s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 186s Info: 0.3 1.4 Source $nextpnr_ICESTORM_LC_0.COUT 186s Info: 0.0 1.4 Net $nextpnr_ICESTORM_LC_0$O budget 0.000000 ns (11,7) -> (11,7) 186s Info: Sink counter_SB_LUT4_I2_20_LC.CIN 186s Info: 0.1 1.5 Source counter_SB_LUT4_I2_20_LC.COUT 186s Info: 0.0 1.5 Net counter_SB_CARRY_CI_CO[2] budget 0.000000 ns (11,7) -> (11,7) 186s Info: Sink counter_SB_LUT4_I2_12_LC.CIN 186s Info: Defined in: 186s Info: example.v:17.14-17.25 186s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 186s Info: 0.1 1.6 Source counter_SB_LUT4_I2_12_LC.COUT 186s Info: 0.0 1.6 Net counter_SB_CARRY_CI_CO[3] budget 0.000000 ns (11,7) -> (11,7) 186s Info: Sink counter_SB_LUT4_I2_11_LC.CIN 186s Info: Defined in: 186s Info: example.v:17.14-17.25 186s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 186s Info: 0.1 1.8 Source counter_SB_LUT4_I2_11_LC.COUT 186s Info: 0.0 1.8 Net counter_SB_CARRY_CI_CO[4] budget 0.000000 ns (11,7) -> (11,7) 186s Info: Sink counter_SB_LUT4_I2_10_LC.CIN 186s Info: Defined in: 186s Info: example.v:17.14-17.25 186s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 186s Info: 0.1 1.9 Source counter_SB_LUT4_I2_10_LC.COUT 186s Info: 0.0 1.9 Net counter_SB_CARRY_CI_CO[5] budget 0.000000 ns (11,7) -> (11,7) 186s Info: Sink counter_SB_LUT4_I2_9_LC.CIN 186s Info: Defined in: 186s Info: example.v:17.14-17.25 186s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 186s Info: 0.1 2.0 Source counter_SB_LUT4_I2_9_LC.COUT 186s Info: 0.0 2.0 Net counter_SB_CARRY_CI_CO[6] budget 0.000000 ns (11,7) -> (11,7) 186s Info: Sink counter_SB_LUT4_I2_8_LC.CIN 186s Info: Defined in: 186s Info: example.v:17.14-17.25 186s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 186s Info: 0.1 2.1 Source counter_SB_LUT4_I2_8_LC.COUT 186s Info: 0.0 2.1 Net counter_SB_CARRY_CI_CO[7] budget 0.000000 ns (11,7) -> (11,7) 186s Info: Sink counter_SB_LUT4_I2_7_LC.CIN 186s Info: Defined in: 186s Info: example.v:17.14-17.25 186s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 186s Info: 0.1 2.3 Source counter_SB_LUT4_I2_7_LC.COUT 186s Info: 0.2 2.5 Net counter_SB_CARRY_CI_CO[8] budget 0.190000 ns (11,7) -> (11,8) 186s Info: Sink counter_SB_LUT4_I2_6_LC.CIN 186s Info: Defined in: 186s Info: example.v:17.14-17.25 186s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 186s Info: 0.1 2.6 Source counter_SB_LUT4_I2_6_LC.COUT 186s Info: 0.0 2.6 Net counter_SB_CARRY_CI_CO[9] budget 0.000000 ns (11,8) -> (11,8) 186s Info: Sink counter_SB_LUT4_I2_5_LC.CIN 186s Info: Defined in: 186s Info: example.v:17.14-17.25 186s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 186s Info: 0.1 2.7 Source counter_SB_LUT4_I2_5_LC.COUT 186s Info: 0.0 2.7 Net counter_SB_CARRY_CI_CO[10] budget 0.000000 ns (11,8) -> (11,8) 186s Info: Sink counter_SB_LUT4_I2_4_LC.CIN 186s Info: Defined in: 186s Info: example.v:17.14-17.25 186s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 186s Info: 0.1 2.8 Source counter_SB_LUT4_I2_4_LC.COUT 186s Info: 0.0 2.8 Net counter_SB_CARRY_CI_CO[11] budget 0.000000 ns (11,8) -> (11,8) 186s Info: Sink counter_SB_LUT4_I2_3_LC.CIN 186s Info: Defined in: 186s Info: example.v:17.14-17.25 186s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 186s Info: 0.1 3.0 Source counter_SB_LUT4_I2_3_LC.COUT 186s Info: 0.0 3.0 Net counter_SB_CARRY_CI_CO[12] budget 0.000000 ns (11,8) -> (11,8) 186s Info: Sink counter_SB_LUT4_I2_2_LC.CIN 186s Info: Defined in: 186s Info: example.v:17.14-17.25 186s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 186s Info: 0.1 3.1 Source counter_SB_LUT4_I2_2_LC.COUT 186s Info: 0.0 3.1 Net counter_SB_CARRY_CI_CO[13] budget 0.000000 ns (11,8) -> (11,8) 186s Info: Sink counter_SB_LUT4_I2_1_LC.CIN 186s Info: Defined in: 186s Info: example.v:17.14-17.25 186s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 186s Info: 0.1 3.2 Source counter_SB_LUT4_I2_1_LC.COUT 186s Info: 0.0 3.2 Net counter_SB_CARRY_CI_CO[14] budget 0.000000 ns (11,8) -> (11,8) 186s Info: Sink counter_SB_LUT4_I2_LC.CIN 186s Info: Defined in: 186s Info: example.v:17.14-17.25 186s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 186s Info: 0.1 3.3 Source counter_SB_LUT4_I2_LC.COUT 186s Info: 0.0 3.3 Net counter_SB_CARRY_CI_CO[15] budget 0.000000 ns (11,8) -> (11,8) 186s Info: Sink counter_SB_LUT4_I2_25_LC.CIN 186s Info: Defined in: 186s Info: example.v:17.14-17.25 186s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 186s Info: 0.1 3.5 Source counter_SB_LUT4_I2_25_LC.COUT 186s Info: 0.2 3.7 Net counter_SB_CARRY_CI_CO[16] budget 0.190000 ns (11,8) -> (11,9) 186s Info: Sink counter_SB_LUT4_I2_24_LC.CIN 186s Info: Defined in: 186s Info: example.v:17.14-17.25 186s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 186s Info: 0.1 3.8 Source counter_SB_LUT4_I2_24_LC.COUT 186s Info: 0.0 3.8 Net counter_SB_CARRY_CI_CO[17] budget 0.000000 ns (11,9) -> (11,9) 186s Info: Sink counter_SB_LUT4_I2_23_LC.CIN 186s Info: Defined in: 186s Info: example.v:17.14-17.25 186s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 186s Info: 0.1 3.9 Source counter_SB_LUT4_I2_23_LC.COUT 186s Info: 0.0 3.9 Net counter_SB_CARRY_CI_CO[18] budget 0.000000 ns (11,9) -> (11,9) 186s Info: Sink counter_SB_LUT4_I2_22_LC.CIN 186s Info: Defined in: 186s Info: example.v:17.14-17.25 186s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 186s Info: 0.1 4.0 Source counter_SB_LUT4_I2_22_LC.COUT 186s Info: 0.0 4.0 Net counter_SB_CARRY_CI_CO[19] budget 0.000000 ns (11,9) -> (11,9) 186s Info: Sink counter_SB_LUT4_I2_21_LC.CIN 186s Info: Defined in: 186s Info: example.v:17.14-17.25 186s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 186s Info: 0.1 4.2 Source counter_SB_LUT4_I2_21_LC.COUT 186s Info: 0.0 4.2 Net counter_SB_CARRY_CI_CO[20] budget 0.000000 ns (11,9) -> (11,9) 186s Info: Sink counter_SB_LUT4_I2_19_LC.CIN 186s Info: Defined in: 186s Info: example.v:17.14-17.25 186s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 186s Info: 0.1 4.3 Source counter_SB_LUT4_I2_19_LC.COUT 186s Info: 0.0 4.3 Net counter_SB_CARRY_CI_CO[21] budget 0.000000 ns (11,9) -> (11,9) 186s Info: Sink counter_SB_LUT4_I2_18_LC.CIN 186s Info: Defined in: 186s Info: example.v:17.14-17.25 186s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 186s Info: 0.1 4.4 Source counter_SB_LUT4_I2_18_LC.COUT 186s Info: 0.0 4.4 Net counter_SB_CARRY_CI_CO[22] budget 0.000000 ns (11,9) -> (11,9) 186s Info: Sink counter_SB_LUT4_I2_17_LC.CIN 186s Info: Defined in: 186s Info: example.v:17.14-17.25 186s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 186s Info: 0.1 4.6 Source counter_SB_LUT4_I2_17_LC.COUT 186s Info: 0.0 4.6 Net counter_SB_CARRY_CI_CO[23] budget 0.000000 ns (11,9) -> (11,9) 186s Info: Sink counter_SB_LUT4_I2_16_LC.CIN 186s Info: Defined in: 186s Info: example.v:17.14-17.25 186s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 186s Info: 0.1 4.7 Source counter_SB_LUT4_I2_16_LC.COUT 186s Info: 0.2 4.9 Net counter_SB_CARRY_CI_CO[24] budget 0.190000 ns (11,9) -> (11,10) 186s Info: Sink counter_SB_LUT4_I2_15_LC.CIN 186s Info: Defined in: 186s Info: example.v:17.14-17.25 186s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 186s Info: 0.1 5.0 Source counter_SB_LUT4_I2_15_LC.COUT 186s Info: 0.0 5.0 Net counter_SB_CARRY_CI_CO[25] budget 0.000000 ns (11,10) -> (11,10) 186s Info: Sink counter_SB_LUT4_I2_14_LC.CIN 186s Info: Defined in: 186s Info: example.v:17.14-17.25 186s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 186s Info: 0.1 5.1 Source counter_SB_LUT4_I2_14_LC.COUT 186s Info: 0.3 5.4 Net counter_SB_CARRY_CI_CO[26] budget 0.260000 ns (11,10) -> (11,10) 186s Info: Sink counter_SB_LUT4_I2_13_LC.I3 186s Info: Defined in: 186s Info: example.v:17.14-17.25 186s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 186s Info: 0.3 5.7 Setup counter_SB_LUT4_I2_13_LC.I3 186s Info: 4.3 ns logic, 1.4 ns routing 186s 186s Info: Critical path report for cross-domain path 'posedge clk$SB_IO_IN_$glb_clk' -> '': 186s Info: curr total 186s Info: 0.5 0.5 Source outcnt_SB_DFF_Q_DFFLC.O 186s Info: 0.6 1.1 Net outcnt[3] budget 41.208000 ns (11,10) -> (12,11) 186s Info: Sink LED2_SB_LUT4_O_LC.I2 186s Info: Defined in: 186s Info: example.v:14.17-14.23 186s Info: 0.4 1.5 Source LED2_SB_LUT4_O_LC.O 186s Info: 0.6 2.1 Net LED2$SB_IO_OUT budget 41.207001 ns (12,11) -> (13,12) 186s Info: Sink LED2$sb_io.D_OUT_0 186s Info: Defined in: 186s Info: example.v:4.9-4.13 186s Info: 0.9 ns logic, 1.2 ns routing 186s 186s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 174.83 MHz (PASS at 12.00 MHz) 186s 186s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> : 2.09 ns 186s 186s Info: Slack histogram: 186s Info: legend: * represents 1 endpoint(s) 186s Info: + represents [1,1) endpoint(s) 186s Info: [ 77613, 77826) |*** 186s Info: [ 77826, 78039) | 186s Info: [ 78039, 78252) |* 186s Info: [ 78252, 78465) |** 186s Info: [ 78465, 78678) |* 186s Info: [ 78678, 78891) |** 186s Info: [ 78891, 79104) |** 186s Info: [ 79104, 79317) | 186s Info: [ 79317, 79530) |** 186s Info: [ 79530, 79743) |* 186s Info: [ 79743, 79956) |** 186s Info: [ 79956, 80169) |** 186s Info: [ 80169, 80382) |* 186s Info: [ 80382, 80595) | 186s Info: [ 80595, 80808) |** 186s Info: [ 80808, 81021) |** 186s Info: [ 81021, 81234) |** 186s Info: [ 81234, 81447) |**** 186s Info: [ 81447, 81660) |** 186s Info: [ 81660, 81873) |******************************** 186s 2 warnings, 0 errors 186s 186s Info: Program finished normally. 186s icetime -d hx1k -mtr example.rpt example.asc 186s // Reading input .asc file.. 186s // Reading 1k chipdb file.. 186s // Creating timing netlist.. 186s // Timing estimate: 5.68 ns (175.97 MHz) 186s icepack example.asc example.bin 186s make: Leaving directory '/tmp/autopkgtest.DyuG3m/build.kB5/src/examples/icestick' 186s make: Entering directory '/tmp/autopkgtest.DyuG3m/build.kB5/src/examples/icezum' 186s yosys -p 'synth_ice40 -top top -json example.json' example.v 186s 186s /----------------------------------------------------------------------------\ 186s | | 186s | yosys -- Yosys Open SYnthesis Suite | 186s | | 186s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 186s | | 186s | Permission to use, copy, modify, and/or distribute this software for any | 186s | purpose with or without fee is hereby granted, provided that the above | 186s | copyright notice and this permission notice appear in all copies. | 186s | | 186s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 186s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 186s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 186s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 186s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 186s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 186s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 186s | | 186s \----------------------------------------------------------------------------/ 186s 186s Yosys 0.23 (git sha1 7ce5011c24b) 186s 186s 186s -- Parsing `example.v' using frontend ` -vlog2k' -- 186s 186s 1. Executing Verilog-2005 frontend: example.v 186s Parsing Verilog input from `example.v' to AST representation. 186s Storing AST representation for module `$abstract\top'. 186s Successfully finished Verilog frontend. 186s 186s -- Running command `synth_ice40 -top top -json example.json' -- 186s 186s 2. Executing SYNTH_ICE40 pass. 186s 186s 2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v 186s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation. 186s Generating RTLIL representation for module `\SB_IO'. 186s Generating RTLIL representation for module `\SB_GB_IO'. 186s Generating RTLIL representation for module `\SB_GB'. 186s Generating RTLIL representation for module `\SB_LUT4'. 186s Generating RTLIL representation for module `\SB_CARRY'. 186s Generating RTLIL representation for module `\SB_DFF'. 186s Generating RTLIL representation for module `\SB_DFFE'. 186s Generating RTLIL representation for module `\SB_DFFSR'. 186s Generating RTLIL representation for module `\SB_DFFR'. 186s Generating RTLIL representation for module `\SB_DFFSS'. 186s Generating RTLIL representation for module `\SB_DFFS'. 186s Generating RTLIL representation for module `\SB_DFFESR'. 186s Generating RTLIL representation for module `\SB_DFFER'. 186s Generating RTLIL representation for module `\SB_DFFESS'. 186s Generating RTLIL representation for module `\SB_DFFES'. 186s Generating RTLIL representation for module `\SB_DFFN'. 186s Generating RTLIL representation for module `\SB_DFFNE'. 186s Generating RTLIL representation for module `\SB_DFFNSR'. 186s Generating RTLIL representation for module `\SB_DFFNR'. 186s Generating RTLIL representation for module `\SB_DFFNSS'. 186s Generating RTLIL representation for module `\SB_DFFNS'. 186s Generating RTLIL representation for module `\SB_DFFNESR'. 186s Generating RTLIL representation for module `\SB_DFFNER'. 186s Generating RTLIL representation for module `\SB_DFFNESS'. 186s Generating RTLIL representation for module `\SB_DFFNES'. 186s Generating RTLIL representation for module `\SB_RAM40_4K'. 186s Generating RTLIL representation for module `\SB_RAM40_4KNR'. 186s Generating RTLIL representation for module `\SB_RAM40_4KNW'. 186s Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. 186s Generating RTLIL representation for module `\ICESTORM_LC'. 186s Generating RTLIL representation for module `\SB_PLL40_CORE'. 186s Generating RTLIL representation for module `\SB_PLL40_PAD'. 186s Generating RTLIL representation for module `\SB_PLL40_2_PAD'. 186s Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. 186s Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. 186s Generating RTLIL representation for module `\SB_WARMBOOT'. 186s Generating RTLIL representation for module `\SB_SPRAM256KA'. 186s Generating RTLIL representation for module `\SB_HFOSC'. 186s Generating RTLIL representation for module `\SB_LFOSC'. 186s Generating RTLIL representation for module `\SB_RGBA_DRV'. 186s Generating RTLIL representation for module `\SB_LED_DRV_CUR'. 186s Generating RTLIL representation for module `\SB_RGB_DRV'. 186s Generating RTLIL representation for module `\SB_I2C'. 186s Generating RTLIL representation for module `\SB_SPI'. 186s Generating RTLIL representation for module `\SB_LEDDA_IP'. 186s Generating RTLIL representation for module `\SB_FILTER_50NS'. 186s Generating RTLIL representation for module `\SB_IO_I3C'. 186s Generating RTLIL representation for module `\SB_IO_OD'. 186s Generating RTLIL representation for module `\SB_MAC16'. 186s Generating RTLIL representation for module `\ICESTORM_RAM'. 186s Successfully finished Verilog frontend. 186s 186s 2.2. Executing HIERARCHY pass (managing design hierarchy). 186s 186s 2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\top'. 186s Generating RTLIL representation for module `\top'. 186s 186s 2.3.1. Analyzing design hierarchy.. 186s Top module: \top 186s 186s 2.3.2. Analyzing design hierarchy.. 186s Top module: \top 186s Removing unused module `$abstract\top'. 186s Removed 1 unused modules. 186s 186s 2.4. Executing PROC pass (convert processes to netlists). 186s 186s 2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 186s Cleaned up 0 empty switches. 186s 186s 2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 186s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241 in module SB_DFFNES. 186s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234 in module SB_DFFNESS. 186s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230 in module SB_DFFNER. 186s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223 in module SB_DFFNESR. 186s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220 in module SB_DFFNS. 186s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217 in module SB_DFFNSS. 186s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214 in module SB_DFFNR. 186s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211 in module SB_DFFNSR. 186s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203 in module SB_DFFES. 186s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196 in module SB_DFFESS. 186s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192 in module SB_DFFER. 186s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185 in module SB_DFFESR. 186s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182 in module SB_DFFS. 186s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179 in module SB_DFFSS. 186s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176 in module SB_DFFR. 186s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173 in module SB_DFFSR. 186s Removed a total of 0 dead cases. 186s 186s 2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 186s Removed 8 redundant assignments. 186s Promoted 25 assignments to connections. 186s 186s 2.4.4. Executing PROC_INIT pass (extract init attributes). 186s Found init rule in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 186s Set init value: \Q = 1'0 186s Found init rule in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 186s Set init value: \Q = 1'0 186s Found init rule in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 186s Set init value: \Q = 1'0 186s Found init rule in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 186s Set init value: \Q = 1'0 186s Found init rule in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 186s Set init value: \Q = 1'0 186s Found init rule in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 186s Set init value: \Q = 1'0 186s Found init rule in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 186s Set init value: \Q = 1'0 186s Found init rule in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 186s Set init value: \Q = 1'0 186s Found init rule in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 186s Set init value: \Q = 1'0 186s Found init rule in `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 186s Set init value: \Q = 1'0 186s Found init rule in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 186s Set init value: \Q = 1'0 186s Found init rule in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 186s Set init value: \Q = 1'0 186s Found init rule in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 186s Set init value: \Q = 1'0 186s Found init rule in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 186s Set init value: \Q = 1'0 186s Found init rule in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 186s Set init value: \Q = 1'0 186s Found init rule in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 186s Set init value: \Q = 1'0 186s Found init rule in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 186s Set init value: \Q = 1'0 186s Found init rule in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 186s Set init value: \Q = 1'0 186s Found init rule in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 186s Set init value: \Q = 1'0 186s Found init rule in `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 186s Set init value: \Q = 1'0 186s Found init rule in `\top.$proc$example.v:16$385'. 186s Set init value: \counter = 23'00000000000000000000000 186s 186s 2.4.5. Executing PROC_ARST pass (detect async resets in processes). 186s Found async reset \S in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 186s Found async reset \R in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 186s Found async reset \S in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 186s Found async reset \R in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 186s Found async reset \S in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 186s Found async reset \R in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 186s Found async reset \S in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 186s Found async reset \R in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 186s 186s 2.4.6. Executing PROC_ROM pass (convert switches to ROMs). 186s Converted 0 switches. 186s 186s 186s 2.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 186s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 186s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 186s 1/1: $0\Q[0:0] 186s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 186s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 186s 1/1: $0\Q[0:0] 186s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 186s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 186s 1/1: $0\Q[0:0] 186s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 186s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 186s 1/1: $0\Q[0:0] 186s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 186s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 186s 1/1: $0\Q[0:0] 186s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 186s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 186s 1/1: $0\Q[0:0] 186s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 186s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 186s 1/1: $0\Q[0:0] 186s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 186s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 186s 1/1: $0\Q[0:0] 186s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 186s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 186s 1/1: $0\Q[0:0] 186s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 186s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 186s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 186s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 186s 1/1: $0\Q[0:0] 186s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 186s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 186s 1/1: $0\Q[0:0] 186s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 186s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 186s 1/1: $0\Q[0:0] 186s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 186s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 186s 1/1: $0\Q[0:0] 186s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 186s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 186s 1/1: $0\Q[0:0] 186s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 186s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 186s 1/1: $0\Q[0:0] 186s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 186s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 186s 1/1: $0\Q[0:0] 186s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 186s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 186s 1/1: $0\Q[0:0] 186s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 186s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 186s 1/1: $0\Q[0:0] 186s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 186s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 186s Creating decoders for process `\top.$proc$example.v:16$385'. 186s Creating decoders for process `\top.$proc$example.v:19$381'. 186s 186s 2.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). 186s 186s 2.4.9. Executing PROC_DFF pass (convert process syncs to FFs). 186s Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 186s created $adff cell `$procdff$430' with negative edge clock and positive level reset. 186s Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 186s created $dff cell `$procdff$431' with negative edge clock. 186s Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 186s created $adff cell `$procdff$432' with negative edge clock and positive level reset. 186s Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 186s created $dff cell `$procdff$433' with negative edge clock. 186s Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 186s created $adff cell `$procdff$434' with negative edge clock and positive level reset. 186s Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 186s created $dff cell `$procdff$435' with negative edge clock. 186s Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 186s created $adff cell `$procdff$436' with negative edge clock and positive level reset. 186s Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 186s created $dff cell `$procdff$437' with negative edge clock. 186s Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 186s created $dff cell `$procdff$438' with negative edge clock. 186s Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 186s created $dff cell `$procdff$439' with negative edge clock. 186s Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 186s created $adff cell `$procdff$440' with positive edge clock and positive level reset. 186s Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 186s created $dff cell `$procdff$441' with positive edge clock. 186s Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 186s created $adff cell `$procdff$442' with positive edge clock and positive level reset. 186s Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 186s created $dff cell `$procdff$443' with positive edge clock. 186s Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 186s created $adff cell `$procdff$444' with positive edge clock and positive level reset. 186s Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 186s created $dff cell `$procdff$445' with positive edge clock. 186s Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 186s created $adff cell `$procdff$446' with positive edge clock and positive level reset. 186s Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 186s created $dff cell `$procdff$447' with positive edge clock. 186s Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 186s created $dff cell `$procdff$448' with positive edge clock. 186s Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 186s created $dff cell `$procdff$449' with positive edge clock. 186s Creating register for signal `\top.\counter' using process `\top.$proc$example.v:19$381'. 186s created $dff cell `$procdff$450' with positive edge clock. 186s Creating register for signal `\top.\outcnt' using process `\top.$proc$example.v:19$381'. 186s created $dff cell `$procdff$451' with positive edge clock. 186s 186s 2.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 186s 186s 2.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 186s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 186s Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 186s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 186s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 186s Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 186s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 186s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 186s Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 186s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 186s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 186s Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 186s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 186s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 186s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 186s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 186s Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 186s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 186s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 186s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 186s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 186s Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 186s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 186s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 186s Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 186s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 186s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 186s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 186s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 186s Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 186s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 186s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 186s Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 186s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 186s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 186s Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 186s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 186s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 186s Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 186s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 186s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 186s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 186s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 186s Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 186s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 186s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 186s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 186s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 186s Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 186s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 186s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 186s Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 186s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 186s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 186s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 186s Removing empty process `top.$proc$example.v:16$385'. 186s Removing empty process `top.$proc$example.v:19$381'. 186s Cleaned up 18 empty switches. 186s 186s 2.4.12. Executing OPT_EXPR pass (perform const folding). 186s Optimizing module top. 186s 186s 186s 2.5. Executing FLATTEN pass (flatten design). 186s 186s 2.6. Executing TRIBUF pass. 186s 186s 2.7. Executing DEMINOUT pass (demote inout ports to input or output). 186s 186s 2.8. Executing OPT_EXPR pass (perform const folding). 186s Optimizing module top. 186s 186s 2.9. Executing OPT_CLEAN pass (remove unused cells and wires). 186s Finding unused cells or wires in module \top.. 186s Removed 0 unused cells and 3 unused wires. 186s 186s 186s 2.10. Executing CHECK pass (checking for obvious problems). 186s Checking module top... 186s Found and reported 0 problems. 186s 186s 2.11. Executing OPT pass (performing simple optimizations). 186s 186s 2.11.1. Executing OPT_EXPR pass (perform const folding). 186s Optimizing module top. 186s 186s 2.11.2. Executing OPT_MERGE pass (detect identical cells). 186s Finding identical cells in module `\top'. 186s Removed a total of 0 cells. 186s 186s 2.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 186s Running muxtree optimizer on module \top.. 186s Creating internal representation of mux trees. 186s No muxes found in this module. 186s Removed 0 multiplexer ports. 186s 186s 2.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 186s Optimizing cells in module \top. 186s Performed a total of 0 changes. 186s 186s 2.11.5. Executing OPT_MERGE pass (detect identical cells). 186s Finding identical cells in module `\top'. 186s Removed a total of 0 cells. 186s 186s 2.11.6. Executing OPT_DFF pass (perform DFF optimizations). 186s 186s 2.11.7. Executing OPT_CLEAN pass (remove unused cells and wires). 186s Finding unused cells or wires in module \top.. 186s 186s 2.11.8. Executing OPT_EXPR pass (perform const folding). 186s Optimizing module top. 186s 186s 2.11.9. Finished OPT passes. (There is nothing left to do.) 186s 186s 2.12. Executing FSM pass (extract and optimize FSM). 186s 186s 2.12.1. Executing FSM_DETECT pass (finding FSMs in design). 186s 186s 2.12.2. Executing FSM_EXTRACT pass (extracting FSM from design). 186s 186s 2.12.3. Executing FSM_OPT pass (simple optimizations of FSMs). 186s 186s 2.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). 186s Finding unused cells or wires in module \top.. 186s 186s 2.12.5. Executing FSM_OPT pass (simple optimizations of FSMs). 186s 186s 2.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 186s 186s 2.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 186s 186s 2.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 186s 186s 2.13. Executing OPT pass (performing simple optimizations). 186s 186s 2.13.1. Executing OPT_EXPR pass (perform const folding). 186s Optimizing module top. 186s 186s 2.13.2. Executing OPT_MERGE pass (detect identical cells). 186s Finding identical cells in module `\top'. 186s Removed a total of 0 cells. 186s 186s 2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 186s Running muxtree optimizer on module \top.. 186s Creating internal representation of mux trees. 186s No muxes found in this module. 186s Removed 0 multiplexer ports. 186s 186s 2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 186s Optimizing cells in module \top. 186s Performed a total of 0 changes. 186s 186s 2.13.5. Executing OPT_MERGE pass (detect identical cells). 186s Finding identical cells in module `\top'. 186s Removed a total of 0 cells. 186s 186s 2.13.6. Executing OPT_DFF pass (perform DFF optimizations). 186s 186s 2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). 186s Finding unused cells or wires in module \top.. 186s 186s 2.13.8. Executing OPT_EXPR pass (perform const folding). 186s Optimizing module top. 186s 186s 2.13.9. Finished OPT passes. (There is nothing left to do.) 186s 186s 2.14. Executing WREDUCE pass (reducing word size of cells). 186s Removed top 31 bits (of 32) from port B of cell top.$add$example.v:20$382 ($add). 186s Removed top 9 bits (of 32) from port Y of cell top.$add$example.v:20$382 ($add). 186s Removed top 30 bits (of 32) from port A of cell top.$shl$example.v:24$384 ($shl). 186s Removed top 24 bits (of 32) from port Y of cell top.$shl$example.v:24$384 ($shl). 186s Removed top 24 bits (of 32) from wire top.$shl$example.v:24$384_Y. 186s 186s 2.15. Executing PEEPOPT pass (run peephole optimizers). 186s 186s 2.16. Executing OPT_CLEAN pass (remove unused cells and wires). 186s Finding unused cells or wires in module \top.. 186s Removed 0 unused cells and 3 unused wires. 186s 186s 186s 2.17. Executing SHARE pass (SAT-based resource sharing). 186s 186s 2.18. Executing TECHMAP pass (map to technology primitives). 186s 186s 2.18.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v 186s Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation. 186s Generating RTLIL representation for module `\_90_lut_cmp_'. 186s Successfully finished Verilog frontend. 186s 186s 2.18.2. Continuing TECHMAP pass. 186s No more expansions possible. 186s 186s 186s 2.19. Executing OPT_EXPR pass (perform const folding). 186s Optimizing module top. 186s 186s 2.20. Executing OPT_CLEAN pass (remove unused cells and wires). 186s Finding unused cells or wires in module \top.. 186s 186s 2.21. Executing ALUMACC pass (create $alu and $macc cells). 186s Extracting $alu and $macc cells in module top: 186s creating $macc model for $add$example.v:20$382 ($add). 186s creating $alu model for $macc $add$example.v:20$382. 186s creating $alu cell for $add$example.v:20$382: $auto$alumacc.cc:485:replace_alu$454 186s created 1 $alu and 0 $macc cells. 186s 186s 2.22. Executing OPT pass (performing simple optimizations). 186s 186s 2.22.1. Executing OPT_EXPR pass (perform const folding). 186s Optimizing module top. 186s 186s 2.22.2. Executing OPT_MERGE pass (detect identical cells). 186s Finding identical cells in module `\top'. 186s Removed a total of 0 cells. 186s 186s 2.22.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 186s Running muxtree optimizer on module \top.. 186s Creating internal representation of mux trees. 186s No muxes found in this module. 186s Removed 0 multiplexer ports. 186s 186s 2.22.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 186s Optimizing cells in module \top. 186s Performed a total of 0 changes. 186s 186s 2.22.5. Executing OPT_MERGE pass (detect identical cells). 186s Finding identical cells in module `\top'. 186s Removed a total of 0 cells. 186s 186s 2.22.6. Executing OPT_DFF pass (perform DFF optimizations). 186s 186s 2.22.7. Executing OPT_CLEAN pass (remove unused cells and wires). 186s Finding unused cells or wires in module \top.. 186s 186s 2.22.8. Executing OPT_EXPR pass (perform const folding). 186s Optimizing module top. 186s 186s 2.22.9. Finished OPT passes. (There is nothing left to do.) 186s 186s 2.23. Executing MEMORY pass. 186s 186s 2.23.1. Executing OPT_MEM pass (optimize memories). 186s Performed a total of 0 transformations. 186s 186s 2.23.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). 186s Performed a total of 0 transformations. 186s 186s 2.23.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 186s 186s 2.23.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 186s 186s 2.23.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 186s 186s 2.23.6. Executing OPT_CLEAN pass (remove unused cells and wires). 186s Finding unused cells or wires in module \top.. 186s 186s 2.23.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 186s 186s 2.23.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). 186s Performed a total of 0 transformations. 186s 186s 2.23.9. Executing OPT_CLEAN pass (remove unused cells and wires). 186s Finding unused cells or wires in module \top.. 186s 186s 2.23.10. Executing MEMORY_COLLECT pass (generating $mem cells). 186s 186s 2.24. Executing OPT_CLEAN pass (remove unused cells and wires). 186s Finding unused cells or wires in module \top.. 186s 186s 2.25. Executing MEMORY_LIBMAP pass (mapping memories to cells). 186s 186s 2.26. Executing TECHMAP pass (map to technology primitives). 186s 186s 2.26.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v 187s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation. 187s Generating RTLIL representation for module `\$__ICE40_RAM4K_'. 187s Successfully finished Verilog frontend. 187s 187s 2.26.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/spram_map.v 187s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/spram_map.v' to AST representation. 187s Generating RTLIL representation for module `\$__ICE40_SPRAM_'. 187s Successfully finished Verilog frontend. 187s 187s 2.26.3. Continuing TECHMAP pass. 187s No more expansions possible. 187s 187s 187s 2.27. Executing ICE40_BRAMINIT pass. 187s 187s 2.28. Executing OPT pass (performing simple optimizations). 187s 187s 2.28.1. Executing OPT_EXPR pass (perform const folding). 187s Optimizing module top. 187s 187s 2.28.2. Executing OPT_MERGE pass (detect identical cells). 187s Finding identical cells in module `\top'. 187s Removed a total of 0 cells. 187s 187s 2.28.3. Executing OPT_DFF pass (perform DFF optimizations). 187s 187s 2.28.4. Executing OPT_CLEAN pass (remove unused cells and wires). 187s Finding unused cells or wires in module \top.. 187s 187s 2.28.5. Finished fast OPT passes. 187s 187s 2.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 187s 187s 2.30. Executing OPT pass (performing simple optimizations). 187s 187s 2.30.1. Executing OPT_EXPR pass (perform const folding). 187s Optimizing module top. 187s 187s 2.30.2. Executing OPT_MERGE pass (detect identical cells). 187s Finding identical cells in module `\top'. 187s Removed a total of 0 cells. 187s 187s 2.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 187s Running muxtree optimizer on module \top.. 187s Creating internal representation of mux trees. 187s No muxes found in this module. 187s Removed 0 multiplexer ports. 187s 187s 2.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 187s Optimizing cells in module \top. 187s Performed a total of 0 changes. 187s 187s 2.30.5. Executing OPT_MERGE pass (detect identical cells). 187s Finding identical cells in module `\top'. 187s Removed a total of 0 cells. 187s 187s 2.30.6. Executing OPT_DFF pass (perform DFF optimizations). 187s 187s 2.30.7. Executing OPT_CLEAN pass (remove unused cells and wires). 187s Finding unused cells or wires in module \top.. 187s 187s 2.30.8. Executing OPT_EXPR pass (perform const folding). 187s Optimizing module top. 187s 187s 2.30.9. Finished OPT passes. (There is nothing left to do.) 187s 187s 2.31. Executing ICE40_WRAPCARRY pass (wrap carries). 187s 187s 2.32. Executing TECHMAP pass (map to technology primitives). 187s 187s 2.32.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v 187s Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation. 187s Generating RTLIL representation for module `\_90_simplemap_bool_ops'. 187s Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. 187s Generating RTLIL representation for module `\_90_simplemap_logic_ops'. 187s Generating RTLIL representation for module `\_90_simplemap_compare_ops'. 187s Generating RTLIL representation for module `\_90_simplemap_various'. 187s Generating RTLIL representation for module `\_90_simplemap_registers'. 187s Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. 187s Generating RTLIL representation for module `\_90_shift_shiftx'. 187s Generating RTLIL representation for module `\_90_fa'. 187s Generating RTLIL representation for module `\_90_lcu'. 187s Generating RTLIL representation for module `\_90_alu'. 187s Generating RTLIL representation for module `\_90_macc'. 187s Generating RTLIL representation for module `\_90_alumacc'. 187s Generating RTLIL representation for module `\$__div_mod_u'. 187s Generating RTLIL representation for module `\$__div_mod_trunc'. 187s Generating RTLIL representation for module `\_90_div'. 187s Generating RTLIL representation for module `\_90_mod'. 187s Generating RTLIL representation for module `\$__div_mod_floor'. 187s Generating RTLIL representation for module `\_90_divfloor'. 187s Generating RTLIL representation for module `\_90_modfloor'. 187s Generating RTLIL representation for module `\_90_pow'. 187s Generating RTLIL representation for module `\_90_pmux'. 187s Generating RTLIL representation for module `\_90_demux'. 187s Generating RTLIL representation for module `\_90_lut'. 187s Successfully finished Verilog frontend. 187s 187s 2.32.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v 187s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation. 187s Generating RTLIL representation for module `\_80_ice40_alu'. 187s Successfully finished Verilog frontend. 187s 187s 2.32.3. Continuing TECHMAP pass. 187s Using template $paramod$constmap:5c4fb84a0fc6ae5c0d4120d25a7a267fccccc7a8$paramod$bc0ada8317992808a26d9434f659d5d0f7acd7e1\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. 187s Using template $paramod$36fdbc18fab0758c8553dda57bd33e3f8f3e8765\_80_ice40_alu for cells of type $alu. 187s Using extmapper simplemap for cells of type $dff. 187s Using extmapper simplemap for cells of type $xor. 187s Using extmapper simplemap for cells of type $not. 187s Using extmapper simplemap for cells of type $pos. 187s No more expansions possible. 187s 187s 187s 2.33. Executing OPT pass (performing simple optimizations). 187s 187s 2.33.1. Executing OPT_EXPR pass (perform const folding). 187s Optimizing module top. 187s 187s 187s 2.33.2. Executing OPT_MERGE pass (detect identical cells). 187s Finding identical cells in module `\top'. 187s 187s Removed a total of 1 cells. 187s 187s 2.33.3. Executing OPT_DFF pass (perform DFF optimizations). 187s 187s 2.33.4. Executing OPT_CLEAN pass (remove unused cells and wires). 187s Finding unused cells or wires in module \top.. 187s Removed 23 unused cells and 22 unused wires. 187s 187s 187s 2.33.5. Finished fast OPT passes. 187s 187s 2.34. Executing ICE40_OPT pass (performing simple optimizations). 187s 187s 2.34.1. Running ICE40 specific optimizations. 187s Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$454.slice[0].carry: CO=\counter [0] 187s 187s 2.34.2. Executing OPT_EXPR pass (perform const folding). 187s Optimizing module top. 187s 187s 2.34.3. Executing OPT_MERGE pass (detect identical cells). 187s Finding identical cells in module `\top'. 187s Removed a total of 0 cells. 187s 187s 2.34.4. Executing OPT_DFF pass (perform DFF optimizations). 187s 187s 2.34.5. Executing OPT_CLEAN pass (remove unused cells and wires). 187s Finding unused cells or wires in module \top.. 187s 187s 2.34.6. Rerunning OPT passes. (Removed registers in this run.) 187s 187s 2.34.7. Running ICE40 specific optimizations. 187s 187s 2.34.8. Executing OPT_EXPR pass (perform const folding). 187s Optimizing module top. 187s 187s 2.34.9. Executing OPT_MERGE pass (detect identical cells). 187s Finding identical cells in module `\top'. 187s Removed a total of 0 cells. 187s 187s 2.34.10. Executing OPT_DFF pass (perform DFF optimizations). 187s 187s 2.34.11. Executing OPT_CLEAN pass (remove unused cells and wires). 187s Finding unused cells or wires in module \top.. 187s 187s 2.34.12. Finished OPT passes. (There is nothing left to do.) 187s 187s 2.35. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 187s 187s 2.36. Executing TECHMAP pass (map to technology primitives). 187s 187s 2.36.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 187s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 187s Generating RTLIL representation for module `\$_DFF_N_'. 187s Generating RTLIL representation for module `\$_DFF_P_'. 187s Generating RTLIL representation for module `\$_DFFE_NP_'. 187s Generating RTLIL representation for module `\$_DFFE_PP_'. 187s Generating RTLIL representation for module `\$_DFF_NP0_'. 187s Generating RTLIL representation for module `\$_DFF_NP1_'. 187s Generating RTLIL representation for module `\$_DFF_PP0_'. 187s Generating RTLIL representation for module `\$_DFF_PP1_'. 187s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 187s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 187s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 187s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 187s Generating RTLIL representation for module `\$_SDFF_NP0_'. 187s Generating RTLIL representation for module `\$_SDFF_NP1_'. 187s Generating RTLIL representation for module `\$_SDFF_PP0_'. 187s Generating RTLIL representation for module `\$_SDFF_PP1_'. 187s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 187s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 187s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 187s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 187s Successfully finished Verilog frontend. 187s 187s 2.36.2. Continuing TECHMAP pass. 187s Using template \$_DFF_P_ for cells of type $_DFF_P_. 187s No more expansions possible. 187s 187s 187s 2.37. Executing OPT_EXPR pass (perform const folding). 187s Optimizing module top. 187s 187s 2.38. Executing SIMPLEMAP pass (map simple cells to gate primitives). 187s Mapping top.$auto$alumacc.cc:485:replace_alu$454.slice[0].carry ($lut). 187s 187s 2.39. Executing ICE40_OPT pass (performing simple optimizations). 187s 187s 2.39.1. Running ICE40 specific optimizations. 187s 187s 2.39.2. Executing OPT_EXPR pass (perform const folding). 187s Optimizing module top. 187s 187s 187s 2.39.3. Executing OPT_MERGE pass (detect identical cells). 187s Finding identical cells in module `\top'. 187s Removed a total of 0 cells. 187s 187s 2.39.4. Executing OPT_DFF pass (perform DFF optimizations). 187s 187s 2.39.5. Executing OPT_CLEAN pass (remove unused cells and wires). 187s Finding unused cells or wires in module \top.. 187s Removed 0 unused cells and 108 unused wires. 187s 187s 187s 2.39.6. Rerunning OPT passes. (Removed registers in this run.) 187s 187s 2.39.7. Running ICE40 specific optimizations. 187s 187s 2.39.8. Executing OPT_EXPR pass (perform const folding). 187s Optimizing module top. 187s 187s 2.39.9. Executing OPT_MERGE pass (detect identical cells). 187s Finding identical cells in module `\top'. 187s Removed a total of 0 cells. 187s 187s 2.39.10. Executing OPT_DFF pass (perform DFF optimizations). 187s 187s 2.39.11. Executing OPT_CLEAN pass (remove unused cells and wires). 187s Finding unused cells or wires in module \top.. 187s 187s 2.39.12. Finished OPT passes. (There is nothing left to do.) 187s 187s 2.40. Executing TECHMAP pass (map to technology primitives). 187s 187s 2.40.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v 187s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation. 187s Generating RTLIL representation for module `\$_DLATCH_N_'. 187s Generating RTLIL representation for module `\$_DLATCH_P_'. 187s Successfully finished Verilog frontend. 187s 187s 2.40.2. Continuing TECHMAP pass. 187s No more expansions possible. 187s 187s 187s 2.41. Executing ABC pass (technology mapping using ABC). 187s 187s 2.41.1. Extracting gate netlist of module `\top' to `/input.blif'.. 187s Extracted 14 gates and 19 wires to a netlist network with 4 inputs and 9 outputs. 187s 187s 2.41.1.1. Executing ABC. 187s Running ABC command: "berkeley-abc" -s -f /abc.script 2>&1 187s ABC: ABC command line: "source /abc.script". 187s ABC: 187s ABC: + read_blif /input.blif 187s ABC: + read_lut /lutdefs.txt 187s ABC: + strash 187s ABC: + &get -n 187s ABC: + &fraig -x 187s ABC: + &put 187s ABC: + scorr 187s ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). 187s ABC: + dc2 187s ABC: + dretime 187s ABC: + strash 187s ABC: + dch -f 187s ABC: + if 187s ABC: + mfs2 187s ABC: + lutpack -S 1 187s ABC: + dress /input.blif 187s ABC: Total number of equiv classes = 10. 187s ABC: Participating nodes from both networks = 19. 187s ABC: Participating nodes from the first network = 9. ( 90.00 % of nodes) 187s ABC: Participating nodes from the second network = 10. ( 100.00 % of nodes) 187s ABC: Node pairs (any polarity) = 9. ( 90.00 % of names can be moved) 187s ABC: Node pairs (same polarity) = 9. ( 90.00 % of names can be moved) 187s ABC: Total runtime = 0.01 sec 187s ABC: + write_blif /output.blif 187s 187s 2.41.1.2. Re-integrating ABC results. 187s ABC RESULTS: $lut cells: 9 187s ABC RESULTS: internal signals: 6 187s ABC RESULTS: input signals: 4 187s ABC RESULTS: output signals: 9 187s Removing temp directory. 187s 187s 2.42. Executing ICE40_WRAPCARRY pass (wrap carries). 187s 187s 2.43. Executing TECHMAP pass (map to technology primitives). 187s 187s 2.43.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 187s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 187s Generating RTLIL representation for module `\$_DFF_N_'. 187s Generating RTLIL representation for module `\$_DFF_P_'. 187s Generating RTLIL representation for module `\$_DFFE_NP_'. 187s Generating RTLIL representation for module `\$_DFFE_PP_'. 187s Generating RTLIL representation for module `\$_DFF_NP0_'. 187s Generating RTLIL representation for module `\$_DFF_NP1_'. 187s Generating RTLIL representation for module `\$_DFF_PP0_'. 187s Generating RTLIL representation for module `\$_DFF_PP1_'. 187s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 187s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 187s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 187s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 187s Generating RTLIL representation for module `\$_SDFF_NP0_'. 187s Generating RTLIL representation for module `\$_SDFF_NP1_'. 187s Generating RTLIL representation for module `\$_SDFF_PP0_'. 187s Generating RTLIL representation for module `\$_SDFF_PP1_'. 187s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 187s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 187s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 187s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 187s Successfully finished Verilog frontend. 187s 187s 2.43.2. Continuing TECHMAP pass. 187s No more expansions possible. 187s 187s Removed 1 unused cells and 16 unused wires. 187s 187s 2.44. Executing OPT_LUT pass (optimize LUTs). 187s Discovering LUTs. 187s Number of LUTs: 31 187s 1-LUT 1 187s 2-LUT 1 187s 3-LUT 29 187s with \SB_CARRY (#0) 21 187s with \SB_CARRY (#1) 21 187s 187s Eliminating LUTs. 187s Number of LUTs: 31 187s 1-LUT 1 187s 2-LUT 1 187s 3-LUT 29 187s with \SB_CARRY (#0) 21 187s with \SB_CARRY (#1) 21 187s 187s Combining LUTs. 187s Number of LUTs: 31 187s 1-LUT 1 187s 2-LUT 1 187s 3-LUT 29 187s with \SB_CARRY (#0) 21 187s with \SB_CARRY (#1) 21 187s 187s Eliminated 0 LUTs. 187s Combined 0 LUTs. 187s 187s 187s 2.45. Executing TECHMAP pass (map to technology primitives). 187s 187s 2.45.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v 187s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation. 187s Generating RTLIL representation for module `\$lut'. 187s Successfully finished Verilog frontend. 187s 187s 2.45.2. Continuing TECHMAP pass. 187s Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut. 187s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut. 187s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut. 187s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. 187s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. 187s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut. 187s No more expansions possible. 187s 187s Removed 0 unused cells and 62 unused wires. 187s 187s 2.46. Executing AUTONAME pass. 187s Renamed 124 objects in module top (4 iterations). 187s 187s 187s 2.47. Executing HIERARCHY pass (managing design hierarchy). 187s 187s 2.47.1. Analyzing design hierarchy.. 187s Top module: \top 187s 187s 2.47.2. Analyzing design hierarchy.. 187s Top module: \top 187s Removed 0 unused modules. 187s 187s 2.48. Printing statistics. 187s 187s === top === 187s 187s Number of wires: 13 187s Number of wire bits: 81 187s Number of public wires: 13 187s Number of public wire bits: 81 187s Number of memories: 0 187s Number of memory bits: 0 187s Number of processes: 0 187s Number of cells: 78 187s SB_CARRY 21 187s SB_DFF 26 187s SB_LUT4 31 187s 187s 2.49. Executing CHECK pass (checking for obvious problems). 187s Checking module top... 187s Found and reported 0 problems. 187s 187s 2.50. Executing JSON backend. 187s 187s End of script. Logfile hash: 681b620f38, CPU: user 0.98s system 0.04s, MEM: 22.00 MB peak 187s Yosys 0.23 (git sha1 7ce5011c24b) 187s Time spent: 64% 13x read_verilog (0 sec), 6% 1x abc (0 sec), ... 187s nextpnr-ice40 --hx1k --package tq144 --asc example.asc --pcf icezum.pcf --json example.json 187s Info: constrained 'LED0' to bel 'X13/Y9/io1' 187s Info: constrained 'LED1' to bel 'X13/Y11/io0' 187s Info: constrained 'LED2' to bel 'X13/Y11/io1' 187s Info: constrained 'LED3' to bel 'X13/Y12/io0' 187s Info: constrained 'LED4' to bel 'X13/Y12/io1' 187s Info: constrained 'LED5' to bel 'X13/Y13/io0' 187s Info: constrained 'LED6' to bel 'X13/Y13/io1' 187s Info: constrained 'LED7' to bel 'X13/Y14/io0' 187s Info: constrained 'clk' to bel 'X0/Y8/io1' 187s 187s Info: Packing constants.. 187s Info: Packing IOs.. 187s Info: Packing LUT-FFs.. 187s Info: 8 LCs used as LUT4 only 187s Info: 23 LCs used as LUT4 and DFF 187s Info: Packing non-LUT FFs.. 187s Info: 3 LCs used as DFF only 187s Info: Packing carries.. 187s Info: 0 LCs used as CARRY only 187s Info: Packing indirect carry+LUT pairs... 187s Info: 0 LUTs merged into carry LCs 187s Info: Packing RAMs.. 187s Info: Placing PLLs.. 187s Info: Packing special functions.. 187s Info: Packing PLLs.. 187s Info: Promoting globals.. 187s Info: promoting clk$SB_IO_IN (fanout 26) 187s Info: Constraining chains... 187s Info: 1 LCs used to legalise carry chains. 187s Info: Checksum: 0x62a7ba7d 187s 187s Info: Annotating ports with timing budgets for target frequency 12.00 MHz 187s Info: Checksum: 0xe1af17d8 187s 187s Info: Device utilisation: 187s Info: ICESTORM_LC: 37/ 1280 2% 187s Info: ICESTORM_RAM: 0/ 16 0% 187s Info: SB_IO: 9/ 112 8% 187s Info: SB_GB: 1/ 8 12% 187s Info: ICESTORM_PLL: 0/ 1 0% 187s Info: SB_WARMBOOT: 0/ 1 0% 187s 187s Info: Placed 9 cells based on constraints. 187s Info: Creating initial analytic placement for 14 cells, random placement wirelen = 180. 187s Info: at initial placer iter 0, wirelen = 27 187s Info: at initial placer iter 1, wirelen = 24 187s Info: at initial placer iter 2, wirelen = 26 187s Info: at initial placer iter 3, wirelen = 24 187s Info: Running main analytical placer, max placement attempts per cell = 10000. 187s Info: at iteration #1, type ICESTORM_LC: wirelen solved = 26, spread = 31, legal = 30; time = 0.00s 187s Info: at iteration #1, type SB_GB: wirelen solved = 30, spread = 30, legal = 30; time = 0.00s 187s Info: at iteration #1, type ALL: wirelen solved = 15, spread = 18, legal = 33; time = 0.00s 187s Info: at iteration #2, type ICESTORM_LC: wirelen solved = 25, spread = 43, legal = 43; time = 0.00s 187s Info: at iteration #2, type SB_GB: wirelen solved = 43, spread = 43, legal = 43; time = 0.00s 187s Info: at iteration #2, type ALL: wirelen solved = 25, spread = 43, legal = 43; time = 0.00s 187s Info: at iteration #3, type ICESTORM_LC: wirelen solved = 29, spread = 43, legal = 43; time = 0.00s 187s Info: at iteration #3, type SB_GB: wirelen solved = 43, spread = 43, legal = 43; time = 0.00s 187s Info: at iteration #3, type ALL: wirelen solved = 29, spread = 43, legal = 43; time = 0.00s 187s Info: at iteration #4, type ICESTORM_LC: wirelen solved = 27, spread = 47, legal = 47; time = 0.00s 187s Info: at iteration #4, type SB_GB: wirelen solved = 47, spread = 47, legal = 47; time = 0.00s 187s Info: at iteration #4, type ALL: wirelen solved = 27, spread = 47, legal = 47; time = 0.00s 187s Info: at iteration #5, type ICESTORM_LC: wirelen solved = 29, spread = 46, legal = 46; time = 0.00s 187s Info: at iteration #5, type SB_GB: wirelen solved = 46, spread = 46, legal = 46; time = 0.00s 187s Info: at iteration #5, type ALL: wirelen solved = 29, spread = 44, legal = 44; time = 0.00s 187s Info: at iteration #6, type ICESTORM_LC: wirelen solved = 27, spread = 47, legal = 47; time = 0.00s 187s Info: at iteration #6, type SB_GB: wirelen solved = 47, spread = 47, legal = 47; time = 0.00s 187s Info: at iteration #6, type ALL: wirelen solved = 29, spread = 49, legal = 49; time = 0.00s 187s Info: HeAP Placer Time: 0.01s 187s Info: of which solving equations: 0.01s 187s Info: of which spreading cells: 0.00s 187s Info: of which strict legalisation: 0.00s 187s 187s Info: Running simulated annealing placer for refinement. 187s Info: at iteration #1: temp = 0.000000, timing cost = 3, wirelen = 33 187s Info: at iteration #5: temp = 0.000000, timing cost = 3, wirelen = 24 187s Info: at iteration #5: temp = 0.000000, timing cost = 3, wirelen = 24 187s Info: SA placement time 0.00s 187s 187s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 195.01 MHz (PASS at 12.00 MHz) 187s 187s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> : 2.74 ns 187s 187s Info: Slack histogram: 187s Info: legend: * represents 1 endpoint(s) 187s Info: + represents [1,1) endpoint(s) 187s Info: [ 78205, 78389) |** 187s Info: [ 78389, 78573) |* 187s Info: [ 78573, 78757) |** 187s Info: [ 78757, 78941) |** 187s Info: [ 78941, 79125) | 187s Info: [ 79125, 79309) | 187s Info: [ 79309, 79493) |** 187s Info: [ 79493, 79677) |* 187s Info: [ 79677, 79861) |** 187s Info: [ 79861, 80045) |* 187s Info: [ 80045, 80229) |** 187s Info: [ 80229, 80413) | 187s Info: [ 80413, 80597) |*** 187s Info: [ 80597, 80781) |* 187s Info: [ 80781, 80965) |* 187s Info: [ 80965, 81149) |** 187s Info: [ 81149, 81333) |******* 187s Info: [ 81333, 81517) | 187s Info: [ 81517, 81701) | 187s Info: [ 81701, 81885) |*************************** 187s Info: Checksum: 0xa1bb4ca5 187s 187s Info: Routing.. 187s Info: Setting up routing queue. 187s Info: Routing 108 arcs. 187s Info: | (re-)routed arcs | delta | remaining| time spent | 187s Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| 187s Info: 108 | 0 89 | 0 89 | 0| 0.00 0.00| 187s Info: Routing complete. 187s Info: Router1 time 0.00s 187s Info: Checksum: 0x4cb9f475 187s 187s Info: Critical path report for clock 'clk$SB_IO_IN_$glb_clk' (posedge -> posedge): 187s Info: curr total 187s Info: 0.5 0.5 Source counter_SB_LUT4_I3_LC.O 187s Info: 0.6 1.1 Net counter[0] budget 79.292999 ns (12,10) -> (11,10) 187s Info: Sink $nextpnr_ICESTORM_LC_0.I1 187s Info: Defined in: 187s Info: example.v:20.14-20.25 187s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 187s Info: 0.3 1.4 Source $nextpnr_ICESTORM_LC_0.COUT 187s Info: 0.0 1.4 Net $nextpnr_ICESTORM_LC_0$O budget 0.000000 ns (11,10) -> (11,10) 187s Info: Sink counter_SB_LUT4_I2_3_LC.CIN 187s Info: 0.1 1.5 Source counter_SB_LUT4_I2_3_LC.COUT 187s Info: 0.0 1.5 Net counter_SB_CARRY_CI_CO[2] budget 0.000000 ns (11,10) -> (11,10) 187s Info: Sink counter_SB_LUT4_I2_21_LC.CIN 187s Info: Defined in: 187s Info: example.v:20.14-20.25 187s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 187s Info: 0.1 1.6 Source counter_SB_LUT4_I2_21_LC.COUT 187s Info: 0.0 1.6 Net counter_SB_CARRY_CI_CO[3] budget 0.000000 ns (11,10) -> (11,10) 187s Info: Sink counter_SB_LUT4_I2_20_LC.CIN 187s Info: Defined in: 187s Info: example.v:20.14-20.25 187s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 187s Info: 0.1 1.8 Source counter_SB_LUT4_I2_20_LC.COUT 187s Info: 0.0 1.8 Net counter_SB_CARRY_CI_CO[4] budget 0.000000 ns (11,10) -> (11,10) 187s Info: Sink counter_SB_LUT4_I2_19_LC.CIN 187s Info: Defined in: 187s Info: example.v:20.14-20.25 187s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 187s Info: 0.1 1.9 Source counter_SB_LUT4_I2_19_LC.COUT 187s Info: 0.0 1.9 Net counter_SB_CARRY_CI_CO[5] budget 0.000000 ns (11,10) -> (11,10) 187s Info: Sink counter_SB_LUT4_I2_18_LC.CIN 187s Info: Defined in: 187s Info: example.v:20.14-20.25 187s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 187s Info: 0.1 2.0 Source counter_SB_LUT4_I2_18_LC.COUT 187s Info: 0.0 2.0 Net counter_SB_CARRY_CI_CO[6] budget 0.000000 ns (11,10) -> (11,10) 187s Info: Sink counter_SB_LUT4_I2_17_LC.CIN 187s Info: Defined in: 187s Info: example.v:20.14-20.25 187s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 187s Info: 0.1 2.1 Source counter_SB_LUT4_I2_17_LC.COUT 187s Info: 0.0 2.1 Net counter_SB_CARRY_CI_CO[7] budget 0.000000 ns (11,10) -> (11,10) 187s Info: Sink counter_SB_LUT4_I2_16_LC.CIN 187s Info: Defined in: 187s Info: example.v:20.14-20.25 187s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 187s Info: 0.1 2.3 Source counter_SB_LUT4_I2_16_LC.COUT 187s Info: 0.2 2.5 Net counter_SB_CARRY_CI_CO[8] budget 0.190000 ns (11,10) -> (11,11) 187s Info: Sink counter_SB_LUT4_I2_15_LC.CIN 187s Info: Defined in: 187s Info: example.v:20.14-20.25 187s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 187s Info: 0.1 2.6 Source counter_SB_LUT4_I2_15_LC.COUT 187s Info: 0.0 2.6 Net counter_SB_CARRY_CI_CO[9] budget 0.000000 ns (11,11) -> (11,11) 187s Info: Sink counter_SB_LUT4_I2_14_LC.CIN 187s Info: Defined in: 187s Info: example.v:20.14-20.25 187s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 187s Info: 0.1 2.7 Source counter_SB_LUT4_I2_14_LC.COUT 187s Info: 0.0 2.7 Net counter_SB_CARRY_CI_CO[10] budget 0.000000 ns (11,11) -> (11,11) 187s Info: Sink counter_SB_LUT4_I2_13_LC.CIN 187s Info: Defined in: 187s Info: example.v:20.14-20.25 187s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 187s Info: 0.1 2.8 Source counter_SB_LUT4_I2_13_LC.COUT 187s Info: 0.0 2.8 Net counter_SB_CARRY_CI_CO[11] budget 0.000000 ns (11,11) -> (11,11) 187s Info: Sink counter_SB_LUT4_I2_12_LC.CIN 187s Info: Defined in: 187s Info: example.v:20.14-20.25 187s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 187s Info: 0.1 3.0 Source counter_SB_LUT4_I2_12_LC.COUT 187s Info: 0.0 3.0 Net counter_SB_CARRY_CI_CO[12] budget 0.000000 ns (11,11) -> (11,11) 187s Info: Sink counter_SB_LUT4_I2_11_LC.CIN 187s Info: Defined in: 187s Info: example.v:20.14-20.25 187s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 187s Info: 0.1 3.1 Source counter_SB_LUT4_I2_11_LC.COUT 187s Info: 0.0 3.1 Net counter_SB_CARRY_CI_CO[13] budget 0.000000 ns (11,11) -> (11,11) 187s Info: Sink counter_SB_LUT4_I2_10_LC.CIN 187s Info: Defined in: 187s Info: example.v:20.14-20.25 187s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 187s Info: 0.1 3.2 Source counter_SB_LUT4_I2_10_LC.COUT 187s Info: 0.0 3.2 Net counter_SB_CARRY_CI_CO[14] budget 0.000000 ns (11,11) -> (11,11) 187s Info: Sink counter_SB_LUT4_I2_9_LC.CIN 187s Info: Defined in: 187s Info: example.v:20.14-20.25 187s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 187s Info: 0.1 3.3 Source counter_SB_LUT4_I2_9_LC.COUT 187s Info: 0.0 3.3 Net counter_SB_CARRY_CI_CO[15] budget 0.000000 ns (11,11) -> (11,11) 187s Info: Sink counter_SB_LUT4_I2_8_LC.CIN 187s Info: Defined in: 187s Info: example.v:20.14-20.25 187s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 187s Info: 0.1 3.5 Source counter_SB_LUT4_I2_8_LC.COUT 187s Info: 0.2 3.7 Net counter_SB_CARRY_CI_CO[16] budget 0.190000 ns (11,11) -> (11,12) 187s Info: Sink counter_SB_LUT4_I2_7_LC.CIN 187s Info: Defined in: 187s Info: example.v:20.14-20.25 187s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 187s Info: 0.1 3.8 Source counter_SB_LUT4_I2_7_LC.COUT 187s Info: 0.0 3.8 Net counter_SB_CARRY_CI_CO[17] budget 0.000000 ns (11,12) -> (11,12) 187s Info: Sink counter_SB_LUT4_I2_6_LC.CIN 187s Info: Defined in: 187s Info: example.v:20.14-20.25 187s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 187s Info: 0.1 3.9 Source counter_SB_LUT4_I2_6_LC.COUT 187s Info: 0.0 3.9 Net counter_SB_CARRY_CI_CO[18] budget 0.000000 ns (11,12) -> (11,12) 187s Info: Sink counter_SB_LUT4_I2_5_LC.CIN 187s Info: Defined in: 187s Info: example.v:20.14-20.25 187s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 187s Info: 0.1 4.0 Source counter_SB_LUT4_I2_5_LC.COUT 187s Info: 0.0 4.0 Net counter_SB_CARRY_CI_CO[19] budget 0.000000 ns (11,12) -> (11,12) 187s Info: Sink counter_SB_LUT4_I2_4_LC.CIN 187s Info: Defined in: 187s Info: example.v:20.14-20.25 187s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 187s Info: 0.1 4.2 Source counter_SB_LUT4_I2_4_LC.COUT 187s Info: 0.0 4.2 Net counter_SB_CARRY_CI_CO[20] budget 0.000000 ns (11,12) -> (11,12) 187s Info: Sink counter_SB_LUT4_I2_2_LC.CIN 187s Info: Defined in: 187s Info: example.v:20.14-20.25 187s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 187s Info: 0.1 4.3 Source counter_SB_LUT4_I2_2_LC.COUT 187s Info: 0.0 4.3 Net counter_SB_CARRY_CI_CO[21] budget 0.000000 ns (11,12) -> (11,12) 187s Info: Sink counter_SB_LUT4_I2_1_LC.CIN 187s Info: Defined in: 187s Info: example.v:20.14-20.25 187s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 187s Info: 0.1 4.4 Source counter_SB_LUT4_I2_1_LC.COUT 187s Info: 0.3 4.7 Net counter_SB_CARRY_CI_CO[22] budget 0.260000 ns (11,12) -> (11,12) 187s Info: Sink counter_SB_LUT4_I2_LC.I3 187s Info: Defined in: 187s Info: example.v:20.14-20.25 187s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 187s Info: 0.3 5.0 Setup counter_SB_LUT4_I2_LC.I3 187s Info: 3.8 ns logic, 1.2 ns routing 187s 187s Info: Critical path report for cross-domain path 'posedge clk$SB_IO_IN_$glb_clk' -> '': 187s Info: curr total 187s Info: 0.5 0.5 Source outcnt_SB_DFF_Q_DFFLC.O 187s Info: 0.6 1.1 Net outcnt[2] budget 41.196999 ns (12,12) -> (12,11) 187s Info: Sink LED0_SB_LUT4_O_LC.I1 187s Info: Defined in: 187s Info: example.v:17.17-17.23 187s Info: 0.4 1.5 Source LED0_SB_LUT4_O_LC.O 187s Info: 1.5 3.0 Net LED0$SB_IO_OUT budget 41.196999 ns (12,11) -> (13,9) 187s Info: Sink LED0$sb_io.D_OUT_0 187s Info: Defined in: 187s Info: example.v:3.9-3.13 187s Info: 0.9 ns logic, 2.1 ns routing 187s 187s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 199.20 MHz (PASS at 12.00 MHz) 187s 187s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> : 3.02 ns 187s 187s Info: Slack histogram: 187s Info: legend: * represents 1 endpoint(s) 187s Info: + represents [1,1) endpoint(s) 187s Info: [ 78313, 78491) |** 187s Info: [ 78491, 78669) |* 187s Info: [ 78669, 78847) |** 187s Info: [ 78847, 79025) |** 187s Info: [ 79025, 79203) | 187s Info: [ 79203, 79381) | 187s Info: [ 79381, 79559) |** 187s Info: [ 79559, 79737) |* 187s Info: [ 79737, 79915) |** 187s Info: [ 79915, 80093) |* 187s Info: [ 80093, 80271) |** 187s Info: [ 80271, 80449) |* 187s Info: [ 80449, 80627) |** 187s Info: [ 80627, 80805) |* 187s Info: [ 80805, 80983) |** 187s Info: [ 80983, 81161) |* 187s Info: [ 81161, 81339) |******* 187s Info: [ 81339, 81517) | 187s Info: [ 81517, 81695) | 187s Info: [ 81695, 81873) |*************************** 187s 187s Info: Program finished normally. 187s icetime -d hx1k -mtr example.rpt example.asc 187s // Reading input .asc file.. 187s // Reading 1k chipdb file.. 187s // Creating timing netlist.. 187s // Timing estimate: 4.98 ns (200.75 MHz) 187s icepack example.asc example.bin 187s make: Leaving directory '/tmp/autopkgtest.DyuG3m/build.kB5/src/examples/icezum' 187s make: Entering directory '/tmp/autopkgtest.DyuG3m/build.kB5/src/examples/up5k_rgb' 187s yosys -p 'synth_ice40 -top top -json rgb.json' rgb.v 187s 187s /----------------------------------------------------------------------------\ 187s | | 187s | yosys -- Yosys Open SYnthesis Suite | 187s | | 187s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 187s | | 187s | Permission to use, copy, modify, and/or distribute this software for any | 187s | purpose with or without fee is hereby granted, provided that the above | 187s | copyright notice and this permission notice appear in all copies. | 187s | | 187s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 187s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 187s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 187s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 187s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 187s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 187s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 187s | | 187s \----------------------------------------------------------------------------/ 187s 187s Yosys 0.23 (git sha1 7ce5011c24b) 187s 187s 187s -- Parsing `rgb.v' using frontend ` -vlog2k' -- 187s 187s 1. Executing Verilog-2005 frontend: rgb.v 187s Parsing Verilog input from `rgb.v' to AST representation. 187s Storing AST representation for module `$abstract\top'. 187s Successfully finished Verilog frontend. 187s 187s -- Running command `synth_ice40 -top top -json rgb.json' -- 187s 187s 2. Executing SYNTH_ICE40 pass. 187s 187s 2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v 187s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation. 187s Generating RTLIL representation for module `\SB_IO'. 187s Generating RTLIL representation for module `\SB_GB_IO'. 187s Generating RTLIL representation for module `\SB_GB'. 187s Generating RTLIL representation for module `\SB_LUT4'. 187s Generating RTLIL representation for module `\SB_CARRY'. 187s Generating RTLIL representation for module `\SB_DFF'. 187s Generating RTLIL representation for module `\SB_DFFE'. 187s Generating RTLIL representation for module `\SB_DFFSR'. 187s Generating RTLIL representation for module `\SB_DFFR'. 187s Generating RTLIL representation for module `\SB_DFFSS'. 187s Generating RTLIL representation for module `\SB_DFFS'. 187s Generating RTLIL representation for module `\SB_DFFESR'. 187s Generating RTLIL representation for module `\SB_DFFER'. 187s Generating RTLIL representation for module `\SB_DFFESS'. 187s Generating RTLIL representation for module `\SB_DFFES'. 187s Generating RTLIL representation for module `\SB_DFFN'. 187s Generating RTLIL representation for module `\SB_DFFNE'. 187s Generating RTLIL representation for module `\SB_DFFNSR'. 187s Generating RTLIL representation for module `\SB_DFFNR'. 187s Generating RTLIL representation for module `\SB_DFFNSS'. 187s Generating RTLIL representation for module `\SB_DFFNS'. 187s Generating RTLIL representation for module `\SB_DFFNESR'. 187s Generating RTLIL representation for module `\SB_DFFNER'. 187s Generating RTLIL representation for module `\SB_DFFNESS'. 187s Generating RTLIL representation for module `\SB_DFFNES'. 187s Generating RTLIL representation for module `\SB_RAM40_4K'. 187s Generating RTLIL representation for module `\SB_RAM40_4KNR'. 187s Generating RTLIL representation for module `\SB_RAM40_4KNW'. 187s Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. 187s Generating RTLIL representation for module `\ICESTORM_LC'. 187s Generating RTLIL representation for module `\SB_PLL40_CORE'. 187s Generating RTLIL representation for module `\SB_PLL40_PAD'. 187s Generating RTLIL representation for module `\SB_PLL40_2_PAD'. 187s Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. 187s Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. 187s Generating RTLIL representation for module `\SB_WARMBOOT'. 187s Generating RTLIL representation for module `\SB_SPRAM256KA'. 187s Generating RTLIL representation for module `\SB_HFOSC'. 187s Generating RTLIL representation for module `\SB_LFOSC'. 187s Generating RTLIL representation for module `\SB_RGBA_DRV'. 187s Generating RTLIL representation for module `\SB_LED_DRV_CUR'. 187s Generating RTLIL representation for module `\SB_RGB_DRV'. 187s Generating RTLIL representation for module `\SB_I2C'. 187s Generating RTLIL representation for module `\SB_SPI'. 187s Generating RTLIL representation for module `\SB_LEDDA_IP'. 187s Generating RTLIL representation for module `\SB_FILTER_50NS'. 187s Generating RTLIL representation for module `\SB_IO_I3C'. 187s Generating RTLIL representation for module `\SB_IO_OD'. 187s Generating RTLIL representation for module `\SB_MAC16'. 187s Generating RTLIL representation for module `\ICESTORM_RAM'. 187s Successfully finished Verilog frontend. 187s 187s 2.2. Executing HIERARCHY pass (managing design hierarchy). 187s 187s 2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\top'. 187s Generating RTLIL representation for module `\top'. 187s 187s 2.3.1. Analyzing design hierarchy.. 187s Top module: \top 187s 187s 2.3.2. Analyzing design hierarchy.. 187s Top module: \top 187s Removing unused module `$abstract\top'. 187s Removed 1 unused modules. 187s 187s 2.4. Executing PROC pass (convert processes to netlists). 187s 187s 2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 187s Cleaned up 0 empty switches. 187s 187s 2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 187s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241 in module SB_DFFNES. 187s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234 in module SB_DFFNESS. 187s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230 in module SB_DFFNER. 187s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223 in module SB_DFFNESR. 187s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220 in module SB_DFFNS. 187s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217 in module SB_DFFNSS. 187s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214 in module SB_DFFNR. 187s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211 in module SB_DFFNSR. 187s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203 in module SB_DFFES. 187s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196 in module SB_DFFESS. 187s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192 in module SB_DFFER. 187s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185 in module SB_DFFESR. 187s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182 in module SB_DFFS. 187s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179 in module SB_DFFSS. 187s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176 in module SB_DFFR. 187s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173 in module SB_DFFSR. 187s Removed a total of 0 dead cases. 187s 187s 2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 187s Removed 8 redundant assignments. 187s Promoted 27 assignments to connections. 187s 187s 2.4.4. Executing PROC_INIT pass (extract init attributes). 187s Found init rule in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 187s Set init value: \Q = 1'0 187s Found init rule in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 187s Set init value: \Q = 1'0 187s Found init rule in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 187s Set init value: \Q = 1'0 187s Found init rule in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 187s Set init value: \Q = 1'0 187s Found init rule in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 187s Set init value: \Q = 1'0 187s Found init rule in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 187s Set init value: \Q = 1'0 187s Found init rule in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 187s Set init value: \Q = 1'0 187s Found init rule in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 187s Set init value: \Q = 1'0 187s Found init rule in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 187s Set init value: \Q = 1'0 187s Found init rule in `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 187s Set init value: \Q = 1'0 187s Found init rule in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 187s Set init value: \Q = 1'0 187s Found init rule in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 187s Set init value: \Q = 1'0 187s Found init rule in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 187s Set init value: \Q = 1'0 187s Found init rule in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 187s Set init value: \Q = 1'0 187s Found init rule in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 187s Set init value: \Q = 1'0 187s Found init rule in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 187s Set init value: \Q = 1'0 187s Found init rule in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 187s Set init value: \Q = 1'0 187s Found init rule in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 187s Set init value: \Q = 1'0 187s Found init rule in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 187s Set init value: \Q = 1'0 187s Found init rule in `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 187s Set init value: \Q = 1'0 187s 187s 2.4.5. Executing PROC_ARST pass (detect async resets in processes). 187s Found async reset \S in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 187s Found async reset \R in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 187s Found async reset \S in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 187s Found async reset \R in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 187s Found async reset \S in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 187s Found async reset \R in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 187s Found async reset \S in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 187s Found async reset \R in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 187s 187s 2.4.6. Executing PROC_ROM pass (convert switches to ROMs). 187s Converted 0 switches. 187s 187s 187s 2.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 187s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 187s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 187s 1/1: $0\Q[0:0] 187s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 187s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 187s 1/1: $0\Q[0:0] 187s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 187s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 187s 1/1: $0\Q[0:0] 187s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 187s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 187s 1/1: $0\Q[0:0] 187s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 187s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 187s 1/1: $0\Q[0:0] 187s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 187s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 187s 1/1: $0\Q[0:0] 187s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 187s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 187s 1/1: $0\Q[0:0] 187s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 187s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 187s 1/1: $0\Q[0:0] 187s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 187s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 187s 1/1: $0\Q[0:0] 187s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 187s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 187s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 187s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 187s 1/1: $0\Q[0:0] 187s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 187s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 187s 1/1: $0\Q[0:0] 187s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 187s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 187s 1/1: $0\Q[0:0] 187s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 187s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 187s 1/1: $0\Q[0:0] 187s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 187s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 187s 1/1: $0\Q[0:0] 187s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 187s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 187s 1/1: $0\Q[0:0] 187s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 187s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 187s 1/1: $0\Q[0:0] 187s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 187s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 187s 1/1: $0\Q[0:0] 187s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 187s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 187s 1/1: $0\Q[0:0] 187s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 187s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 187s Creating decoders for process `\top.$proc$rgb.v:55$415'. 187s Creating decoders for process `\top.$proc$rgb.v:17$381'. 187s 187s 2.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). 187s 187s 2.4.9. Executing PROC_DFF pass (convert process syncs to FFs). 187s Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 187s created $adff cell `$procdff$467' with negative edge clock and positive level reset. 187s Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 187s created $dff cell `$procdff$468' with negative edge clock. 187s Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 187s created $adff cell `$procdff$469' with negative edge clock and positive level reset. 187s Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 187s created $dff cell `$procdff$470' with negative edge clock. 187s Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 187s created $adff cell `$procdff$471' with negative edge clock and positive level reset. 187s Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 187s created $dff cell `$procdff$472' with negative edge clock. 187s Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 187s created $adff cell `$procdff$473' with negative edge clock and positive level reset. 187s Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 187s created $dff cell `$procdff$474' with negative edge clock. 187s Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 187s created $dff cell `$procdff$475' with negative edge clock. 187s Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 187s created $dff cell `$procdff$476' with negative edge clock. 187s Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 187s created $adff cell `$procdff$477' with positive edge clock and positive level reset. 187s Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 187s created $dff cell `$procdff$478' with positive edge clock. 187s Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 187s created $adff cell `$procdff$479' with positive edge clock and positive level reset. 187s Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 187s created $dff cell `$procdff$480' with positive edge clock. 187s Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 187s created $adff cell `$procdff$481' with positive edge clock and positive level reset. 187s Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 187s created $dff cell `$procdff$482' with positive edge clock. 187s Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 187s created $adff cell `$procdff$483' with positive edge clock and positive level reset. 187s Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 187s created $dff cell `$procdff$484' with positive edge clock. 187s Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 187s created $dff cell `$procdff$485' with positive edge clock. 187s Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 187s created $dff cell `$procdff$486' with positive edge clock. 187s Creating register for signal `\top.\pwm_ctr' using process `\top.$proc$rgb.v:55$415'. 187s created $dff cell `$procdff$487' with positive edge clock. 187s Creating register for signal `\top.\pwm_r' using process `\top.$proc$rgb.v:55$415'. 187s created $dff cell `$procdff$488' with positive edge clock. 187s Creating register for signal `\top.\pwm_g' using process `\top.$proc$rgb.v:55$415'. 187s created $dff cell `$procdff$489' with positive edge clock. 187s Creating register for signal `\top.\pwm_b' using process `\top.$proc$rgb.v:55$415'. 187s created $dff cell `$procdff$490' with positive edge clock. 187s Creating register for signal `\top.\ctr' using process `\top.$proc$rgb.v:17$381'. 187s created $dff cell `$procdff$491' with positive edge clock. 187s 187s 2.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 187s 187s 2.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 187s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 187s Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 187s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 187s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 187s Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 187s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 187s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 187s Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 187s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 187s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 187s Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 187s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 187s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 187s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 187s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 187s Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 187s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 187s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 187s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 187s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 187s Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 187s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 187s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 187s Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 187s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 187s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 187s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 187s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 187s Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 187s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 187s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 187s Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 187s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 187s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 187s Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 187s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 187s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 187s Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 187s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 187s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 187s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 187s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 187s Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 187s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 187s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 187s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 187s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 187s Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 187s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 187s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 187s Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 187s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 187s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 187s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 187s Removing empty process `top.$proc$rgb.v:55$415'. 187s Removing empty process `top.$proc$rgb.v:17$381'. 187s Cleaned up 18 empty switches. 187s 187s 2.4.12. Executing OPT_EXPR pass (perform const folding). 187s Optimizing module top. 187s 187s 187s 2.5. Executing FLATTEN pass (flatten design). 187s 187s 2.6. Executing TRIBUF pass. 187s 187s 2.7. Executing DEMINOUT pass (demote inout ports to input or output). 187s 187s 2.8. Executing OPT_EXPR pass (perform const folding). 187s Optimizing module top. 187s 187s 2.9. Executing OPT_CLEAN pass (remove unused cells and wires). 187s Finding unused cells or wires in module \top.. 187s Removed 0 unused cells and 8 unused wires. 187s 187s 187s 2.10. Executing CHECK pass (checking for obvious problems). 188s Checking module top... 188s Found and reported 0 problems. 188s 188s 2.11. Executing OPT pass (performing simple optimizations). 188s 188s 2.11.1. Executing OPT_EXPR pass (perform const folding). 188s Optimizing module top. 188s 188s 2.11.2. Executing OPT_MERGE pass (detect identical cells). 188s Finding identical cells in module `\top'. 188s 188s Removed a total of 9 cells. 188s 188s 2.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 188s Running muxtree optimizer on module \top.. 188s Creating internal representation of mux trees. 188s Evaluating internal representation of mux trees. 188s Analyzing evaluation results. 188s Removed 0 multiplexer ports. 188s 188s 188s 2.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 188s Optimizing cells in module \top. 188s Performed a total of 0 changes. 188s 188s 2.11.5. Executing OPT_MERGE pass (detect identical cells). 188s Finding identical cells in module `\top'. 188s 188s Removed a total of 1 cells. 188s 188s 2.11.6. Executing OPT_DFF pass (perform DFF optimizations). 188s 188s 2.11.7. Executing OPT_CLEAN pass (remove unused cells and wires). 188s Finding unused cells or wires in module \top.. 188s Removed 0 unused cells and 10 unused wires. 188s 188s 188s 2.11.8. Executing OPT_EXPR pass (perform const folding). 188s Optimizing module top. 188s 188s 2.11.9. Rerunning OPT passes. (Maybe there is more to do..) 188s 188s 2.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 188s Running muxtree optimizer on module \top.. 188s Creating internal representation of mux trees. 188s Evaluating internal representation of mux trees. 188s Analyzing evaluation results. 188s Removed 0 multiplexer ports. 188s 188s 188s 2.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 188s Optimizing cells in module \top. 188s Performed a total of 0 changes. 188s 188s 2.11.12. Executing OPT_MERGE pass (detect identical cells). 188s Finding identical cells in module `\top'. 188s Removed a total of 0 cells. 188s 188s 2.11.13. Executing OPT_DFF pass (perform DFF optimizations). 188s 188s 2.11.14. Executing OPT_CLEAN pass (remove unused cells and wires). 188s Finding unused cells or wires in module \top.. 188s 188s 2.11.15. Executing OPT_EXPR pass (perform const folding). 188s Optimizing module top. 188s 188s 2.11.16. Finished OPT passes. (There is nothing left to do.) 188s 188s 2.12. Executing FSM pass (extract and optimize FSM). 188s 188s 2.12.1. Executing FSM_DETECT pass (finding FSMs in design). 188s 188s 2.12.2. Executing FSM_EXTRACT pass (extracting FSM from design). 188s 188s 2.12.3. Executing FSM_OPT pass (simple optimizations of FSMs). 188s 188s 2.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). 188s Finding unused cells or wires in module \top.. 188s 188s 2.12.5. Executing FSM_OPT pass (simple optimizations of FSMs). 188s 188s 2.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 188s 188s 2.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 188s 188s 2.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 188s 188s 2.13. Executing OPT pass (performing simple optimizations). 188s 188s 2.13.1. Executing OPT_EXPR pass (perform const folding). 188s Optimizing module top. 188s 188s 2.13.2. Executing OPT_MERGE pass (detect identical cells). 188s Finding identical cells in module `\top'. 188s Removed a total of 0 cells. 188s 188s 2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 188s Running muxtree optimizer on module \top.. 188s Creating internal representation of mux trees. 188s Evaluating internal representation of mux trees. 188s Analyzing evaluation results. 188s Removed 0 multiplexer ports. 188s 188s 188s 2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 188s Optimizing cells in module \top. 188s Performed a total of 0 changes. 188s 188s 2.13.5. Executing OPT_MERGE pass (detect identical cells). 188s Finding identical cells in module `\top'. 188s Removed a total of 0 cells. 188s 188s 2.13.6. Executing OPT_DFF pass (perform DFF optimizations). 188s 188s 2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). 188s Finding unused cells or wires in module \top.. 188s 188s 2.13.8. Executing OPT_EXPR pass (perform const folding). 188s Optimizing module top. 188s 188s 2.13.9. Finished OPT passes. (There is nothing left to do.) 188s 188s 2.14. Executing WREDUCE pass (reducing word size of cells). 188s Removed top 31 bits (of 32) from port B of cell top.$add$rgb.v:19$382 ($add). 188s Removed top 30 bits (of 32) from port A of cell top.$mul$rgb.v:35$384 ($mul). 188s Removed top 2 bits (of 12) from port B of cell top.$mul$rgb.v:35$384 ($mul). 188s Removed top 20 bits (of 32) from port Y of cell top.$mul$rgb.v:35$384 ($mul). 188s Removed top 22 bits (of 32) from port A of cell top.$add$rgb.v:35$385 ($add). 188s Removed top 20 bits (of 32) from port B of cell top.$add$rgb.v:35$385 ($add). 188s Removed top 19 bits (of 32) from port Y of cell top.$add$rgb.v:35$385 ($add). 188s Removed top 1 bits (of 2) from port B of cell top.$eq$rgb.v:36$386 ($eq). 188s Removed top 20 bits (of 32) from port A of cell top.$sub$rgb.v:36$387 ($sub). 188s Removed top 19 bits (of 32) from port Y of cell top.$sub$rgb.v:36$387 ($sub). 188s Removed top 22 bits (of 32) from mux cell top.$ternary$rgb.v:37$390 ($mux). 188s Removed top 20 bits (of 32) from mux cell top.$ternary$rgb.v:35$392 ($mux). 188s Removed top 22 bits (of 32) from port A of cell top.$sub$rgb.v:40$394 ($sub). 188s Removed top 2 bits (of 12) from port B of cell top.$sub$rgb.v:40$394 ($sub). 188s Removed top 21 bits (of 32) from port Y of cell top.$sub$rgb.v:40$394 ($sub). 188s Removed top 20 bits (of 32) from mux cell top.$ternary$rgb.v:40$404 ($mux). 188s Removed top 20 bits (of 32) from port A of cell top.$sub$rgb.v:48$410 ($sub). 188s Removed top 20 bits (of 32) from port B of cell top.$sub$rgb.v:48$410 ($sub). 188s Removed top 19 bits (of 32) from port Y of cell top.$sub$rgb.v:48$410 ($sub). 188s Removed top 20 bits (of 32) from mux cell top.$ternary$rgb.v:46$414 ($mux). 188s Removed top 31 bits (of 32) from port B of cell top.$add$rgb.v:57$416 ($add). 188s Removed top 20 bits (of 32) from port Y of cell top.$add$rgb.v:57$416 ($add). 188s Removed top 1 bits (of 13) from port Y of cell top.$add$rgb.v:35$385 ($add). 188s Removed top 20 bits (of 32) from mux cell top.$ternary$rgb.v:36$391 ($mux). 188s Removed top 20 bits (of 32) from mux cell top.$ternary$rgb.v:41$403 ($mux). 188s Removed top 20 bits (of 32) from mux cell top.$ternary$rgb.v:47$413 ($mux). 188s Removed top 20 bits (of 32) from mux cell top.$ternary$rgb.v:42$401 ($mux). 188s Removed top 20 bits (of 32) from mux cell top.$ternary$rgb.v:48$411 ($mux). 188s Removed top 1 bits (of 13) from port Y of cell top.$sub$rgb.v:36$387 ($sub). 188s Removed top 1 bits (of 13) from port Y of cell top.$sub$rgb.v:48$410 ($sub). 188s Removed top 20 bits (of 32) from wire top.$add$rgb.v:35$385_Y. 188s Removed top 20 bits (of 32) from wire top.$mul$rgb.v:35$384_Y. 188s Removed top 20 bits (of 32) from wire top.$sub$rgb.v:36$387_Y. 188s Removed top 20 bits (of 32) from wire top.$sub$rgb.v:48$410_Y. 188s Removed top 20 bits (of 32) from wire top.$ternary$rgb.v:36$391_Y. 188s Removed top 22 bits (of 32) from wire top.$ternary$rgb.v:37$390_Y. 188s Removed top 20 bits (of 32) from wire top.$ternary$rgb.v:41$403_Y. 188s Removed top 20 bits (of 32) from wire top.$ternary$rgb.v:42$401_Y. 188s Removed top 20 bits (of 32) from wire top.$ternary$rgb.v:47$413_Y. 188s Removed top 21 bits (of 32) from wire top.$ternary$rgb.v:48$411_Y. 188s Removed top 2 bits (of 12) from wire top.fade_div4. 188s 188s 2.15. Executing PEEPOPT pass (run peephole optimizers). 188s 188s 2.16. Executing OPT_CLEAN pass (remove unused cells and wires). 188s Finding unused cells or wires in module \top.. 188s Removed 0 unused cells and 15 unused wires. 188s 188s 188s 2.17. Executing SHARE pass (SAT-based resource sharing). 188s 188s 2.18. Executing TECHMAP pass (map to technology primitives). 188s 188s 2.18.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v 188s Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation. 188s Generating RTLIL representation for module `\_90_lut_cmp_'. 188s Successfully finished Verilog frontend. 188s 188s 2.18.2. Continuing TECHMAP pass. 188s No more expansions possible. 188s 188s 188s 2.19. Executing OPT_EXPR pass (perform const folding). 188s Optimizing module top. 188s 188s 2.20. Executing OPT_CLEAN pass (remove unused cells and wires). 188s Finding unused cells or wires in module \top.. 188s 188s 2.21. Executing ALUMACC pass (create $alu and $macc cells). 188s Extracting $alu and $macc cells in module top: 188s creating $macc model for $add$rgb.v:19$382 ($add). 188s creating $macc model for $add$rgb.v:35$385 ($add). 188s creating $macc model for $add$rgb.v:57$416 ($add). 188s creating $macc model for $mul$rgb.v:35$384 ($mul). 188s creating $macc model for $sub$rgb.v:36$387 ($sub). 188s creating $macc model for $sub$rgb.v:40$394 ($sub). 188s creating $macc model for $sub$rgb.v:48$410 ($sub). 188s creating $alu model for $macc $sub$rgb.v:48$410. 188s creating $alu model for $macc $sub$rgb.v:40$394. 188s creating $alu model for $macc $sub$rgb.v:36$387. 188s creating $alu model for $macc $add$rgb.v:57$416. 188s creating $alu model for $macc $add$rgb.v:35$385. 188s creating $alu model for $macc $add$rgb.v:19$382. 188s creating $macc cell for $mul$rgb.v:35$384: $auto$alumacc.cc:365:replace_macc$504 188s creating $alu model for $lt$rgb.v:58$417 ($lt): new $alu 188s creating $alu model for $lt$rgb.v:59$419 ($lt): new $alu 188s creating $alu model for $lt$rgb.v:60$421 ($lt): new $alu 188s creating $alu cell for $lt$rgb.v:60$421: $auto$alumacc.cc:485:replace_alu$508 188s creating $alu cell for $lt$rgb.v:59$419: $auto$alumacc.cc:485:replace_alu$519 188s creating $alu cell for $lt$rgb.v:58$417: $auto$alumacc.cc:485:replace_alu$530 188s creating $alu cell for $add$rgb.v:19$382: $auto$alumacc.cc:485:replace_alu$541 188s creating $alu cell for $add$rgb.v:35$385: $auto$alumacc.cc:485:replace_alu$544 188s creating $alu cell for $add$rgb.v:57$416: $auto$alumacc.cc:485:replace_alu$547 188s creating $alu cell for $sub$rgb.v:36$387: $auto$alumacc.cc:485:replace_alu$550 188s creating $alu cell for $sub$rgb.v:40$394: $auto$alumacc.cc:485:replace_alu$553 188s creating $alu cell for $sub$rgb.v:48$410: $auto$alumacc.cc:485:replace_alu$556 188s created 9 $alu and 1 $macc cells. 188s 188s 2.22. Executing OPT pass (performing simple optimizations). 188s 188s 2.22.1. Executing OPT_EXPR pass (perform const folding). 188s Optimizing module top. 188s 188s 188s 2.22.2. Executing OPT_MERGE pass (detect identical cells). 188s Finding identical cells in module `\top'. 188s Removed a total of 0 cells. 188s 188s 2.22.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 188s Running muxtree optimizer on module \top.. 188s Creating internal representation of mux trees. 188s Evaluating internal representation of mux trees. 188s Analyzing evaluation results. 188s Removed 0 multiplexer ports. 188s 188s 188s 2.22.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 188s Optimizing cells in module \top. 188s Performed a total of 0 changes. 188s 188s 2.22.5. Executing OPT_MERGE pass (detect identical cells). 188s Finding identical cells in module `\top'. 188s Removed a total of 0 cells. 188s 188s 2.22.6. Executing OPT_DFF pass (perform DFF optimizations). 188s 188s 2.22.7. Executing OPT_CLEAN pass (remove unused cells and wires). 188s Finding unused cells or wires in module \top.. 188s Removed 3 unused cells and 6 unused wires. 188s 188s 188s 2.22.8. Executing OPT_EXPR pass (perform const folding). 188s Optimizing module top. 188s 188s 2.22.9. Rerunning OPT passes. (Maybe there is more to do..) 188s 188s 2.22.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 188s Running muxtree optimizer on module \top.. 188s Creating internal representation of mux trees. 188s Evaluating internal representation of mux trees. 188s Analyzing evaluation results. 188s Removed 0 multiplexer ports. 188s 188s 188s 2.22.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 188s Optimizing cells in module \top. 188s Performed a total of 0 changes. 188s 188s 2.22.12. Executing OPT_MERGE pass (detect identical cells). 188s Finding identical cells in module `\top'. 188s Removed a total of 0 cells. 188s 188s 2.22.13. Executing OPT_DFF pass (perform DFF optimizations). 188s 188s 2.22.14. Executing OPT_CLEAN pass (remove unused cells and wires). 188s Finding unused cells or wires in module \top.. 188s 188s 2.22.15. Executing OPT_EXPR pass (perform const folding). 188s Optimizing module top. 188s 188s 2.22.16. Finished OPT passes. (There is nothing left to do.) 188s 188s 2.23. Executing MEMORY pass. 188s 188s 2.23.1. Executing OPT_MEM pass (optimize memories). 188s Performed a total of 0 transformations. 188s 188s 2.23.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). 188s Performed a total of 0 transformations. 188s 188s 2.23.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 188s 188s 2.23.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 188s 188s 2.23.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 188s 188s 2.23.6. Executing OPT_CLEAN pass (remove unused cells and wires). 188s Finding unused cells or wires in module \top.. 188s 188s 2.23.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 188s 188s 2.23.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). 188s Performed a total of 0 transformations. 188s 188s 2.23.9. Executing OPT_CLEAN pass (remove unused cells and wires). 188s Finding unused cells or wires in module \top.. 188s 188s 2.23.10. Executing MEMORY_COLLECT pass (generating $mem cells). 188s 188s 2.24. Executing OPT_CLEAN pass (remove unused cells and wires). 188s Finding unused cells or wires in module \top.. 188s 188s 2.25. Executing MEMORY_LIBMAP pass (mapping memories to cells). 188s 188s 2.26. Executing TECHMAP pass (map to technology primitives). 188s 188s 2.26.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v 188s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation. 188s Generating RTLIL representation for module `\$__ICE40_RAM4K_'. 188s Successfully finished Verilog frontend. 188s 188s 2.26.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/spram_map.v 188s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/spram_map.v' to AST representation. 188s Generating RTLIL representation for module `\$__ICE40_SPRAM_'. 188s Successfully finished Verilog frontend. 188s 188s 2.26.3. Continuing TECHMAP pass. 188s No more expansions possible. 188s 188s 188s 2.27. Executing ICE40_BRAMINIT pass. 188s 188s 2.28. Executing OPT pass (performing simple optimizations). 188s 188s 2.28.1. Executing OPT_EXPR pass (perform const folding). 188s Optimizing module top. 188s 188s 188s 2.28.2. Executing OPT_MERGE pass (detect identical cells). 188s Finding identical cells in module `\top'. 188s 188s Removed a total of 10 cells. 188s 188s 2.28.3. Executing OPT_DFF pass (perform DFF optimizations). 188s 188s 2.28.4. Executing OPT_CLEAN pass (remove unused cells and wires). 188s Finding unused cells or wires in module \top.. 188s Removed 0 unused cells and 22 unused wires. 188s 188s 188s 2.28.5. Finished fast OPT passes. 188s 188s 2.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 188s 188s 2.30. Executing OPT pass (performing simple optimizations). 188s 188s 2.30.1. Executing OPT_EXPR pass (perform const folding). 188s Optimizing module top. 188s 188s 2.30.2. Executing OPT_MERGE pass (detect identical cells). 188s Finding identical cells in module `\top'. 188s Removed a total of 0 cells. 188s 188s 2.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 188s Running muxtree optimizer on module \top.. 188s Creating internal representation of mux trees. 188s Evaluating internal representation of mux trees. 188s Analyzing evaluation results. 188s Removed 0 multiplexer ports. 188s 188s 188s 2.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 188s Optimizing cells in module \top. 188s Performed a total of 0 changes. 188s 188s 2.30.5. Executing OPT_MERGE pass (detect identical cells). 188s Finding identical cells in module `\top'. 188s Removed a total of 0 cells. 188s 188s 2.30.6. Executing OPT_DFF pass (perform DFF optimizations). 188s 188s 2.30.7. Executing OPT_CLEAN pass (remove unused cells and wires). 188s Finding unused cells or wires in module \top.. 188s 188s 2.30.8. Executing OPT_EXPR pass (perform const folding). 188s Optimizing module top. 188s 188s 2.30.9. Finished OPT passes. (There is nothing left to do.) 188s 188s 2.31. Executing ICE40_WRAPCARRY pass (wrap carries). 188s 188s 2.32. Executing TECHMAP pass (map to technology primitives). 188s 188s 2.32.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v 188s Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation. 188s Generating RTLIL representation for module `\_90_simplemap_bool_ops'. 188s Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. 188s Generating RTLIL representation for module `\_90_simplemap_logic_ops'. 188s Generating RTLIL representation for module `\_90_simplemap_compare_ops'. 188s Generating RTLIL representation for module `\_90_simplemap_various'. 188s Generating RTLIL representation for module `\_90_simplemap_registers'. 188s Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. 188s Generating RTLIL representation for module `\_90_shift_shiftx'. 188s Generating RTLIL representation for module `\_90_fa'. 188s Generating RTLIL representation for module `\_90_lcu'. 188s Generating RTLIL representation for module `\_90_alu'. 188s Generating RTLIL representation for module `\_90_macc'. 188s Generating RTLIL representation for module `\_90_alumacc'. 188s Generating RTLIL representation for module `\$__div_mod_u'. 188s Generating RTLIL representation for module `\$__div_mod_trunc'. 188s Generating RTLIL representation for module `\_90_div'. 188s Generating RTLIL representation for module `\_90_mod'. 188s Generating RTLIL representation for module `\$__div_mod_floor'. 188s Generating RTLIL representation for module `\_90_divfloor'. 188s Generating RTLIL representation for module `\_90_modfloor'. 188s Generating RTLIL representation for module `\_90_pow'. 188s Generating RTLIL representation for module `\_90_pmux'. 188s Generating RTLIL representation for module `\_90_demux'. 188s Generating RTLIL representation for module `\_90_lut'. 188s Successfully finished Verilog frontend. 188s 188s 2.32.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v 188s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation. 188s Generating RTLIL representation for module `\_80_ice40_alu'. 188s Successfully finished Verilog frontend. 188s 188s 2.32.3. Continuing TECHMAP pass. 188s Using extmapper simplemap for cells of type $not. 188s Using template $paramod$b40e0f66d01d243904da425c63ff802ae596888e\_80_ice40_alu for cells of type $alu. 188s Using extmapper simplemap for cells of type $logic_not. 188s Using template $paramod$ee3d784672cdb1cb32d9a801a3af776716f16b74\_80_ice40_alu for cells of type $alu. 188s Using template $paramod$8f780356cb6cdb52f6a744190131b65634639c4e\_80_ice40_alu for cells of type $alu. 188s Using extmapper simplemap for cells of type $eq. 188s Using extmapper simplemap for cells of type $or. 188s Using extmapper simplemap for cells of type $mux. 188s Using extmapper maccmap for cells of type $macc. 188s add \ctr [29:20] * 2'11 (10x2 bits, unsigned) 188s Using extmapper simplemap for cells of type $reduce_and. 188s Using template $paramod$6a42b6fefed750f8a1c58eab59479d960557103c\_80_ice40_alu for cells of type $alu. 188s Using extmapper simplemap for cells of type $dff. 188s Using extmapper simplemap for cells of type $and. 188s Using extmapper simplemap for cells of type $xor. 188s Using extmapper simplemap for cells of type $pos. 188s No more expansions possible. 188s 188s 188s 2.33. Executing OPT pass (performing simple optimizations). 188s 188s 2.33.1. Executing OPT_EXPR pass (perform const folding). 188s Optimizing module top. 188s 188s 188s 2.33.2. Executing OPT_MERGE pass (detect identical cells). 188s Finding identical cells in module `\top'. 188s 188s Removed a total of 86 cells. 188s 188s 2.33.3. Executing OPT_DFF pass (perform DFF optimizations). 188s 188s 2.33.4. Executing OPT_CLEAN pass (remove unused cells and wires). 188s Finding unused cells or wires in module \top.. 188s Removed 31 unused cells and 147 unused wires. 188s 188s 188s 2.33.5. Finished fast OPT passes. 188s 188s 2.34. Executing ICE40_OPT pass (performing simple optimizations). 188s 188s 2.34.1. Running ICE40 specific optimizations. 188s Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$541.slice[0].carry: CO=\ctr [0] 188s Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$544.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$544.B [0] 188s Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$547.slice[0].carry: CO=\pwm_ctr [0] 188s Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$830.slice[0].carry: CO=1'0 188s Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$830.slice[11].carry: CO=1'0 188s 188s 2.34.2. Executing OPT_EXPR pass (perform const folding). 188s Optimizing module top. 188s 188s 2.34.3. Executing OPT_MERGE pass (detect identical cells). 188s Finding identical cells in module `\top'. 188s Removed a total of 0 cells. 188s 188s 2.34.4. Executing OPT_DFF pass (perform DFF optimizations). 188s 188s 2.34.5. Executing OPT_CLEAN pass (remove unused cells and wires). 188s Finding unused cells or wires in module \top.. 188s Removed 0 unused cells and 1 unused wires. 188s 188s 188s 2.34.6. Rerunning OPT passes. (Removed registers in this run.) 188s 188s 2.34.7. Running ICE40 specific optimizations. 188s 188s 2.34.8. Executing OPT_EXPR pass (perform const folding). 188s Optimizing module top. 188s 188s 2.34.9. Executing OPT_MERGE pass (detect identical cells). 188s Finding identical cells in module `\top'. 188s Removed a total of 0 cells. 188s 188s 2.34.10. Executing OPT_DFF pass (perform DFF optimizations). 188s 188s 2.34.11. Executing OPT_CLEAN pass (remove unused cells and wires). 188s Finding unused cells or wires in module \top.. 189s 189s 2.34.12. Finished OPT passes. (There is nothing left to do.) 189s 189s 2.35. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 189s 189s 2.36. Executing TECHMAP pass (map to technology primitives). 189s 189s 2.36.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 189s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 189s Generating RTLIL representation for module `\$_DFF_N_'. 189s Generating RTLIL representation for module `\$_DFF_P_'. 189s Generating RTLIL representation for module `\$_DFFE_NP_'. 189s Generating RTLIL representation for module `\$_DFFE_PP_'. 189s Generating RTLIL representation for module `\$_DFF_NP0_'. 189s Generating RTLIL representation for module `\$_DFF_NP1_'. 189s Generating RTLIL representation for module `\$_DFF_PP0_'. 189s Generating RTLIL representation for module `\$_DFF_PP1_'. 189s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 189s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 189s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 189s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 189s Generating RTLIL representation for module `\$_SDFF_NP0_'. 189s Generating RTLIL representation for module `\$_SDFF_NP1_'. 189s Generating RTLIL representation for module `\$_SDFF_PP0_'. 189s Generating RTLIL representation for module `\$_SDFF_PP1_'. 189s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 189s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 189s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 189s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 189s Successfully finished Verilog frontend. 189s 189s 2.36.2. Continuing TECHMAP pass. 189s Using template \$_DFF_P_ for cells of type $_DFF_P_. 189s No more expansions possible. 189s 189s 189s 2.37. Executing OPT_EXPR pass (perform const folding). 189s Optimizing module top. 189s 189s 2.38. Executing SIMPLEMAP pass (map simple cells to gate primitives). 189s Mapping top.$auto$alumacc.cc:485:replace_alu$541.slice[0].carry ($lut). 189s Mapping top.$auto$alumacc.cc:485:replace_alu$544.slice[0].carry ($lut). 189s Mapping top.$auto$alumacc.cc:485:replace_alu$547.slice[0].carry ($lut). 189s Mapping top.$auto$maccmap.cc:240:synth$830.slice[0].carry ($lut). 189s Mapping top.$auto$maccmap.cc:240:synth$830.slice[11].carry ($lut). 189s 189s 2.39. Executing ICE40_OPT pass (performing simple optimizations). 189s 189s 2.39.1. Running ICE40 specific optimizations. 189s 189s 2.39.2. Executing OPT_EXPR pass (perform const folding). 189s Optimizing module top. 189s 189s 189s 2.39.3. Executing OPT_MERGE pass (detect identical cells). 189s Finding identical cells in module `\top'. 189s 189s Removed a total of 5 cells. 189s 189s 2.39.4. Executing OPT_DFF pass (perform DFF optimizations). 189s 189s 2.39.5. Executing OPT_CLEAN pass (remove unused cells and wires). 189s Finding unused cells or wires in module \top.. 189s Removed 0 unused cells and 209 unused wires. 189s 189s 189s 2.39.6. Rerunning OPT passes. (Removed registers in this run.) 189s 189s 2.39.7. Running ICE40 specific optimizations. 189s 189s 2.39.8. Executing OPT_EXPR pass (perform const folding). 189s Optimizing module top. 189s 189s 2.39.9. Executing OPT_MERGE pass (detect identical cells). 189s Finding identical cells in module `\top'. 189s Removed a total of 0 cells. 189s 189s 2.39.10. Executing OPT_DFF pass (perform DFF optimizations). 189s 189s 2.39.11. Executing OPT_CLEAN pass (remove unused cells and wires). 189s Finding unused cells or wires in module \top.. 189s 189s 2.39.12. Finished OPT passes. (There is nothing left to do.) 189s 189s 2.40. Executing TECHMAP pass (map to technology primitives). 189s 189s 2.40.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v 189s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation. 189s Generating RTLIL representation for module `\$_DLATCH_N_'. 189s Generating RTLIL representation for module `\$_DLATCH_P_'. 189s Successfully finished Verilog frontend. 189s 189s 2.40.2. Continuing TECHMAP pass. 189s No more expansions possible. 189s 189s 189s 2.41. Executing ABC pass (technology mapping using ABC). 189s 189s 2.41.1. Extracting gate netlist of module `\top' to `/input.blif'.. 189s Extracted 226 gates and 279 wires to a netlist network with 52 inputs and 52 outputs. 189s 189s 2.41.1.1. Executing ABC. 189s Running ABC command: "berkeley-abc" -s -f /abc.script 2>&1 189s ABC: ABC command line: "source /abc.script". 189s ABC: 189s ABC: + read_blif /input.blif 189s ABC: + read_lut /lutdefs.txt 189s ABC: + strash 189s ABC: + &get -n 189s ABC: + &fraig -x 189s ABC: + &put 189s ABC: + scorr 189s ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). 189s ABC: + dc2 189s ABC: + dretime 189s ABC: + strash 189s ABC: + dch -f 189s ABC: + if 189s ABC: + mfs2 189s ABC: + lutpack -S 1 189s ABC: + dress /input.blif 189s ABC: Total number of equiv classes = 58. 189s ABC: Participating nodes from both networks = 122. 189s ABC: Participating nodes from the first network = 57. ( 63.33 % of nodes) 189s ABC: Participating nodes from the second network = 65. ( 72.22 % of nodes) 189s ABC: Node pairs (any polarity) = 57. ( 63.33 % of names can be moved) 189s ABC: Node pairs (same polarity) = 55. ( 61.11 % of names can be moved) 189s ABC: Total runtime = 0.05 sec 189s ABC: + write_blif /output.blif 189s 189s 2.41.1.2. Re-integrating ABC results. 189s ABC RESULTS: $lut cells: 89 189s ABC RESULTS: internal signals: 175 189s ABC RESULTS: input signals: 52 189s ABC RESULTS: output signals: 52 189s Removing temp directory. 189s 189s 2.42. Executing ICE40_WRAPCARRY pass (wrap carries). 189s 189s 2.43. Executing TECHMAP pass (map to technology primitives). 189s 189s 2.43.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 189s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 189s Generating RTLIL representation for module `\$_DFF_N_'. 189s Generating RTLIL representation for module `\$_DFF_P_'. 189s Generating RTLIL representation for module `\$_DFFE_NP_'. 189s Generating RTLIL representation for module `\$_DFFE_PP_'. 189s Generating RTLIL representation for module `\$_DFF_NP0_'. 189s Generating RTLIL representation for module `\$_DFF_NP1_'. 189s Generating RTLIL representation for module `\$_DFF_PP0_'. 189s Generating RTLIL representation for module `\$_DFF_PP1_'. 189s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 189s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 189s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 189s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 189s Generating RTLIL representation for module `\$_SDFF_NP0_'. 189s Generating RTLIL representation for module `\$_SDFF_NP1_'. 189s Generating RTLIL representation for module `\$_SDFF_PP0_'. 189s Generating RTLIL representation for module `\$_SDFF_PP1_'. 189s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 189s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 189s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 189s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 189s Successfully finished Verilog frontend. 189s 189s 2.43.2. Continuing TECHMAP pass. 189s No more expansions possible. 189s 189s Removed 39 unused cells and 157 unused wires. 189s 189s 2.44. Executing OPT_LUT pass (optimize LUTs). 189s Discovering LUTs. 189s Number of LUTs: 152 189s 1-LUT 13 189s 2-LUT 5 189s 3-LUT 74 189s 4-LUT 60 189s with \SB_CARRY (#0) 60 189s with \SB_CARRY (#1) 62 189s 189s Eliminating LUTs. 189s Number of LUTs: 152 189s 1-LUT 13 189s 2-LUT 5 189s 3-LUT 74 189s 4-LUT 60 189s with \SB_CARRY (#0) 60 189s with \SB_CARRY (#1) 62 189s 189s Combining LUTs. 189s Number of LUTs: 152 189s 1-LUT 13 189s 2-LUT 5 189s 3-LUT 74 189s 4-LUT 60 189s with \SB_CARRY (#0) 60 189s with \SB_CARRY (#1) 62 189s 189s Eliminated 0 LUTs. 189s Combined 0 LUTs. 189s 189s 189s 2.45. Executing TECHMAP pass (map to technology primitives). 189s 189s 2.45.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v 189s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation. 189s Generating RTLIL representation for module `\$lut'. 189s Successfully finished Verilog frontend. 189s 189s 2.45.2. Continuing TECHMAP pass. 189s Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut. 189s Using template $paramod$44f084d3146d098e660e97ec68aa8e73f67e1794\$lut for cells of type $lut. 189s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000010 for cells of type $lut. 189s Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011\$lut for cells of type $lut. 189s Using template $paramod$6382f7860648fdb6f8a8dc690c25a62882cc501b\$lut for cells of type $lut. 189s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. 189s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. 189s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001111 for cells of type $lut. 189s Using template $paramod$99a2a175d178a040bb1ffceb53184fb0f59423c6\$lut for cells of type $lut. 189s Using template $paramod$6dc00590ec1f2f22d7e489e662a8d787a23a0ca2\$lut for cells of type $lut. 189s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut. 189s Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut. 189s Using template $paramod$d9d6d961a139aa8625028a83327b5b5f5f63381a\$lut for cells of type $lut. 189s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut. 189s Using template $paramod$5cdc22d0bd3ca14398fe93d6a434826313da339f\$lut for cells of type $lut. 189s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. 189s Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912\$lut for cells of type $lut. 189s Using template $paramod$7eb00dbc62aefa046649f6bb6faa1ef961d12e98\$lut for cells of type $lut. 189s Using template $paramod$a56d70ffd309b1185b27bc1a5092003d8bf696be\$lut for cells of type $lut. 189s Using template $paramod$4972722c284f07fee673f7cb99e6a36ce4a244f0\$lut for cells of type $lut. 189s Using template $paramod$d750c7e22625d6018716a3d53c182b89ec1b2e44\$lut for cells of type $lut. 189s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut. 189s Using template $paramod$4da6fe9957da309dc16b8f31a6b80b19c05c808d\$lut for cells of type $lut. 189s Using template $paramod$59c595af41d4a5cce2d588c3a5f1342749ce7a77\$lut for cells of type $lut. 189s No more expansions possible. 189s 189s Removed 0 unused cells and 318 unused wires. 189s 189s 2.46. Executing AUTONAME pass. 189s Renamed 3208 objects in module top (23 iterations). 189s 189s 189s 2.47. Executing HIERARCHY pass (managing design hierarchy). 189s 189s 2.47.1. Analyzing design hierarchy.. 189s Top module: \top 189s 189s 2.47.2. Analyzing design hierarchy.. 189s Top module: \top 189s Removed 0 unused modules. 189s 189s 2.48. Printing statistics. 189s 189s === top === 189s 189s Number of wires: 56 189s Number of wire bits: 416 189s Number of public wires: 56 189s Number of public wire bits: 416 189s Number of memories: 0 189s Number of memory bits: 0 189s Number of processes: 0 189s Number of cells: 297 189s SB_CARRY 96 189s SB_DFF 47 189s SB_HFOSC 1 189s SB_LUT4 152 189s SB_RGBA_DRV 1 189s 189s 2.49. Executing CHECK pass (checking for obvious problems). 189s Checking module top... 189s Found and reported 0 problems. 189s 189s 2.50. Executing JSON backend. 189s 189s End of script. Logfile hash: 2abde65be8, CPU: user 1.34s system 0.00s, MEM: 22.00 MB peak 189s Yosys 0.23 (git sha1 7ce5011c24b) 189s Time spent: 46% 13x read_verilog (0 sec), 12% 1x abc (0 sec), ... 189s nextpnr-ice40 --up5k --package sg48 --asc rgb.asc --pcf rgb.pcf --json rgb.json 189s Info: constrained 'RGB0' to bel 'X4/Y31/io0' 189s Info: constrained 'RGB1' to bel 'X5/Y31/io0' 189s Info: constrained 'RGB2' to bel 'X6/Y31/io0' 189s Info: constraining clock net 'clk' to 32.00 MHz 189s 189s Info: Packing constants.. 189s Info: Packing IOs.. 189s Info: RGB2 use by SB_RGBA_DRV/SB_RGB_DRV RGBA_DRIVER, not creating SB_IO 189s Info: RGB1 use by SB_RGBA_DRV/SB_RGB_DRV RGBA_DRIVER, not creating SB_IO 189s Info: RGB0 use by SB_RGBA_DRV/SB_RGB_DRV RGBA_DRIVER, not creating SB_IO 189s Info: Packing LUT-FFs.. 189s Info: 106 LCs used as LUT4 only 189s Info: 46 LCs used as LUT4 and DFF 189s Info: Packing non-LUT FFs.. 189s Info: 1 LCs used as DFF only 189s Info: Packing carries.. 189s Info: 38 LCs used as CARRY only 189s Info: Packing indirect carry+LUT pairs... 189s Info: 13 LUTs merged into carry LCs 189s Info: Packing RAMs.. 189s Info: Placing PLLs.. 189s Info: Packing special functions.. 189s Info: constrained ICESTORM_HFOSC 'inthosc_OSC' to X0/Y31/hfosc_1 189s Warning: Overriding derived constraint of 48.0 MHz on net clk with user-specified constraint of 32.0 MHz. 189s Info: constrained SB_RGBA_DRV 'RGBA_DRIVER' to X0/Y30/rgba_drv_0 189s Info: Packing PLLs.. 189s Info: Promoting globals.. 189s Info: Constraining chains... 189s Info: 4 LCs used to legalise carry chains. 189s Info: Checksum: 0x3278d252 189s 189s Info: Annotating ports with timing budgets for target frequency 12.00 MHz 189s Info: Checksum: 0xa7599e04 189s 189s Info: Device utilisation: 189s Info: ICESTORM_LC: 184/ 5280 3% 189s Info: ICESTORM_RAM: 0/ 30 0% 189s Info: SB_IO: 0/ 96 0% 189s Info: SB_GB: 1/ 8 12% 189s Info: ICESTORM_PLL: 0/ 1 0% 189s Info: SB_WARMBOOT: 0/ 1 0% 189s Info: ICESTORM_DSP: 0/ 8 0% 189s Info: ICESTORM_HFOSC: 1/ 1 100% 189s Info: ICESTORM_LFOSC: 0/ 1 0% 189s Info: SB_I2C: 0/ 2 0% 189s Info: SB_SPI: 0/ 2 0% 189s Info: IO_I3C: 0/ 2 0% 189s Info: SB_LEDDA_IP: 0/ 1 0% 189s Info: SB_RGBA_DRV: 1/ 1 100% 189s Info: ICESTORM_SPRAM: 0/ 4 0% 189s 189s Info: Placed 3 cells based on constraints. 189s Info: Creating initial analytic placement for 84 cells, random placement wirelen = 3936. 189s Info: at initial placer iter 0, wirelen = 54 189s Info: at initial placer iter 1, wirelen = 50 189s Info: at initial placer iter 2, wirelen = 50 189s Info: at initial placer iter 3, wirelen = 50 189s Info: Running main analytical placer, max placement attempts per cell = 10000. 189s Info: at iteration #1, type ICESTORM_LC: wirelen solved = 50, spread = 814, legal = 824; time = 0.00s 189s Info: at iteration #2, type ICESTORM_LC: wirelen solved = 54, spread = 768, legal = 777; time = 0.00s 189s Info: at iteration #3, type ICESTORM_LC: wirelen solved = 69, spread = 767, legal = 792; time = 0.00s 189s Info: at iteration #4, type ICESTORM_LC: wirelen solved = 67, spread = 699, legal = 710; time = 0.01s 189s Info: at iteration #5, type ICESTORM_LC: wirelen solved = 59, spread = 781, legal = 764; time = 0.01s 189s Info: at iteration #6, type ICESTORM_LC: wirelen solved = 128, spread = 688, legal = 703; time = 0.00s 189s Info: at iteration #7, type ICESTORM_LC: wirelen solved = 127, spread = 639, legal = 647; time = 0.01s 189s Info: at iteration #8, type ICESTORM_LC: wirelen solved = 77, spread = 729, legal = 787; time = 0.01s 189s Info: at iteration #9, type ICESTORM_LC: wirelen solved = 117, spread = 585, legal = 626; time = 0.01s 189s Info: at iteration #10, type ICESTORM_LC: wirelen solved = 132, spread = 566, legal = 596; time = 0.00s 189s Info: at iteration #11, type ICESTORM_LC: wirelen solved = 101, spread = 710, legal = 777; time = 0.01s 189s Info: at iteration #12, type ICESTORM_LC: wirelen solved = 96, spread = 577, legal = 635; time = 0.00s 189s Info: at iteration #13, type ICESTORM_LC: wirelen solved = 114, spread = 706, legal = 692; time = 0.01s 189s Info: at iteration #14, type ICESTORM_LC: wirelen solved = 105, spread = 535, legal = 586; time = 0.01s 189s Info: at iteration #15, type ICESTORM_LC: wirelen solved = 142, spread = 672, legal = 718; time = 0.00s 189s Info: at iteration #16, type ICESTORM_LC: wirelen solved = 128, spread = 691, legal = 744; time = 0.00s 189s Info: at iteration #17, type ICESTORM_LC: wirelen solved = 138, spread = 696, legal = 742; time = 0.01s 189s Info: at iteration #18, type ICESTORM_LC: wirelen solved = 145, spread = 698, legal = 753; time = 0.00s 189s Info: at iteration #19, type ICESTORM_LC: wirelen solved = 161, spread = 701, legal = 758; time = 0.01s 189s Info: HeAP Placer Time: 0.13s 189s Info: of which solving equations: 0.10s 189s Info: of which spreading cells: 0.01s 189s Info: of which strict legalisation: 0.00s 189s 189s Info: Running simulated annealing placer for refinement. 189s Info: at iteration #1: temp = 0.000000, timing cost = 136, wirelen = 586 189s Info: at iteration #5: temp = 0.000000, timing cost = 128, wirelen = 465 189s Info: at iteration #10: temp = 0.000000, timing cost = 124, wirelen = 422 189s Info: at iteration #15: temp = 0.000000, timing cost = 128, wirelen = 407 189s Info: at iteration #17: temp = 0.000000, timing cost = 126, wirelen = 407 189s Info: SA placement time 0.12s 189s 189s Info: Max frequency for clock 'clk': 40.17 MHz (PASS at 32.00 MHz) 189s 189s Info: Max delay posedge clk -> : 5.61 ns 189s 189s Info: Slack histogram: 189s Info: legend: * represents 1 endpoint(s) 189s Info: + represents [1,1) endpoint(s) 189s Info: [ 6355, 9944) |***** 189s Info: [ 9944, 13533) |*** 189s Info: [ 13533, 17122) |*** 189s Info: [ 17122, 20711) |************** 189s Info: [ 20711, 24300) |********************* 189s Info: [ 24300, 27889) |**************************************************** 189s Info: [ 27889, 31478) | 189s Info: [ 31478, 35067) | 189s Info: [ 35067, 38656) | 189s Info: [ 38656, 42245) | 189s Info: [ 42245, 45834) | 189s Info: [ 45834, 49423) | 189s Info: [ 49423, 53012) | 189s Info: [ 53012, 56601) | 189s Info: [ 56601, 60190) | 189s Info: [ 60190, 63779) | 189s Info: [ 63779, 67368) | 189s Info: [ 67368, 70957) | 189s Info: [ 70957, 74546) | 189s Info: [ 74546, 78135) |*** 189s Info: Checksum: 0x9fd6acb1 189s 189s Info: Routing.. 189s Info: Setting up routing queue. 189s Info: Routing 632 arcs. 189s Info: | (re-)routed arcs | delta | remaining| time spent | 189s Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| 189s Info: 1000 | 335 581 | 335 581 | 25| 0.13 0.13| 189s Info: 1047 | 349 615 | 14 34 | 0| 0.02 0.15| 189s Info: Routing complete. 189s Info: Router1 time 0.15s 189s Info: Checksum: 0x59611459 189s 189s Info: Critical path report for clock 'clk' (posedge -> posedge): 189s Info: curr total 189s Info: 1.4 1.4 Source ctr_SB_DFF_Q_D_SB_LUT4_O_18_LC.O 189s Info: 2.4 3.8 Net ctr[21] budget 0.000000 ns (1,20) -> (1,22) 189s Info: Sink b_val_SB_LUT4_O_I1_SB_LUT4_O_8_LC.I1 189s Info: Defined in: 189s Info: /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 189s Info: 0.7 4.5 Source b_val_SB_LUT4_O_I1_SB_LUT4_O_8_LC.COUT 189s Info: 0.7 5.1 Net b_val_SB_LUT4_O_I1_SB_LUT4_O_I3[2] budget 0.660000 ns (1,22) -> (1,22) 189s Info: Sink b_val_SB_LUT4_O_I1_SB_LUT4_O_7_LC.I3 189s Info: Defined in: 189s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 189s Info: 0.9 6.0 Source b_val_SB_LUT4_O_I1_SB_LUT4_O_7_LC.O 189s Info: 1.8 7.8 Net b_val_SB_LUT4_O_I1[2] budget 2.349000 ns (1,22) -> (2,22) 189s Info: Sink r_val_SB_LUT4_O_2_I0_SB_LUT4_O_7_LC.I2 189s Info: Defined in: 189s Info: rgb.v:35.31-35.61 189s Info: /usr/bin/../share/yosys/ice40/arith_map.v:31.22-31.23 189s Info: 0.6 8.4 Source r_val_SB_LUT4_O_2_I0_SB_LUT4_O_7_LC.COUT 189s Info: 0.0 8.4 Net r_val_SB_LUT4_O_2_I0_SB_LUT4_O_I3[3] budget 0.000000 ns (2,22) -> (2,22) 189s Info: Sink r_val_SB_LUT4_O_2_I0_SB_LUT4_O_6_LC.CIN 189s Info: Defined in: 189s Info: rgb.v:35.31-35.61 189s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 189s Info: 0.3 8.7 Source r_val_SB_LUT4_O_2_I0_SB_LUT4_O_6_LC.COUT 189s Info: 0.0 8.7 Net r_val_SB_LUT4_O_2_I0_SB_LUT4_O_I3[4] budget 0.000000 ns (2,22) -> (2,22) 189s Info: Sink r_val_SB_LUT4_O_2_I0_SB_LUT4_O_5_LC.CIN 189s Info: Defined in: 189s Info: rgb.v:35.31-35.61 189s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 189s Info: 0.3 8.9 Source r_val_SB_LUT4_O_2_I0_SB_LUT4_O_5_LC.COUT 189s Info: 0.0 8.9 Net r_val_SB_LUT4_O_2_I0_SB_LUT4_O_I3[5] budget 0.000000 ns (2,22) -> (2,22) 189s Info: Sink r_val_SB_LUT4_O_2_I0_SB_LUT4_O_4_LC.CIN 189s Info: Defined in: 189s Info: rgb.v:35.31-35.61 189s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 189s Info: 0.3 9.2 Source r_val_SB_LUT4_O_2_I0_SB_LUT4_O_4_LC.COUT 189s Info: 0.0 9.2 Net r_val_SB_LUT4_O_2_I0_SB_LUT4_O_I3[6] budget 0.000000 ns (2,22) -> (2,22) 189s Info: Sink r_val_SB_LUT4_O_2_I0_SB_LUT4_O_3_LC.CIN 189s Info: Defined in: 189s Info: rgb.v:35.31-35.61 189s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 189s Info: 0.3 9.5 Source r_val_SB_LUT4_O_2_I0_SB_LUT4_O_3_LC.COUT 189s Info: 0.0 9.5 Net r_val_SB_LUT4_O_2_I0_SB_LUT4_O_I3[7] budget 0.000000 ns (2,22) -> (2,22) 189s Info: Sink r_val_SB_LUT4_O_2_I0_SB_LUT4_O_2_LC.CIN 189s Info: Defined in: 189s Info: rgb.v:35.31-35.61 189s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 189s Info: 0.3 9.8 Source r_val_SB_LUT4_O_2_I0_SB_LUT4_O_2_LC.COUT 189s Info: 0.6 10.3 Net r_val_SB_LUT4_O_2_I0_SB_LUT4_O_I3[8] budget 0.560000 ns (2,22) -> (2,23) 189s Info: Sink r_val_SB_LUT4_O_2_I0_SB_LUT4_O_1_LC.CIN 189s Info: Defined in: 189s Info: rgb.v:35.31-35.61 189s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 189s Info: 0.3 10.6 Source r_val_SB_LUT4_O_2_I0_SB_LUT4_O_1_LC.COUT 189s Info: 0.0 10.6 Net r_val_SB_LUT4_O_2_I0_SB_LUT4_O_I3[9] budget 0.000000 ns (2,23) -> (2,23) 189s Info: Sink r_val_SB_LUT4_O_2_I0_SB_LUT4_O_LC.CIN 189s Info: Defined in: 189s Info: rgb.v:35.31-35.61 189s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 189s Info: 0.3 10.9 Source r_val_SB_LUT4_O_2_I0_SB_LUT4_O_LC.COUT 189s Info: 0.7 11.5 Net r_val_SB_LUT4_O_2_I0_SB_LUT4_O_I3[10] budget 0.660000 ns (2,23) -> (2,23) 189s Info: Sink r_val_SB_LUT4_O_2_I0_SB_LUT4_O_10_LC.I3 189s Info: Defined in: 189s Info: rgb.v:35.31-35.61 189s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 189s Info: 0.9 12.4 Source r_val_SB_LUT4_O_2_I0_SB_LUT4_O_10_LC.O 189s Info: 1.8 14.2 Net r_val_SB_LUT4_O_2_I0[10] budget 2.832000 ns (2,23) -> (2,23) 189s Info: Sink r_val_SB_LUT4_O_2_LC.I0 189s Info: Defined in: 189s Info: rgb.v:35.31-35.61 189s Info: /usr/bin/../share/yosys/ice40/arith_map.v:33.26-33.27 189s Info: 1.3 15.5 Source r_val_SB_LUT4_O_2_LC.O 189s Info: 1.8 17.2 Net r_val[10] budget 2.832000 ns (2,23) -> (3,22) 189s Info: Sink r_val_SB_LUT4_O_7_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_O_LC.I3 189s Info: Defined in: 189s Info: rgb.v:32.22-32.27 189s Info: 0.9 18.1 Source r_val_SB_LUT4_O_7_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_O_LC.O 189s Info: 1.8 19.9 Net r_val_SB_LUT4_O_7_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[2] budget 2.831000 ns (3,22) -> (3,22) 189s Info: Sink r_val_SB_LUT4_O_7_I3_SB_LUT4_I2_O_SB_LUT4_O_LC.I3 189s Info: Defined in: 189s Info: /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 189s Info: 0.9 20.7 Source r_val_SB_LUT4_O_7_I3_SB_LUT4_I2_O_SB_LUT4_O_LC.O 189s Info: 1.8 22.5 Net r_val_SB_LUT4_O_7_I3_SB_LUT4_I2_O[2] budget 2.831000 ns (3,22) -> (3,23) 189s Info: Sink r_val_SB_LUT4_O_7_I3_SB_LUT4_I2_O_SB_LUT4_I1_LC.I3 189s Info: Defined in: 189s Info: /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 189s Info: 0.9 23.4 Source r_val_SB_LUT4_O_7_I3_SB_LUT4_I2_O_SB_LUT4_I1_LC.O 189s Info: 1.8 25.1 Net pwm_r_SB_DFF_Q_D_SB_LUT4_O_I0[2] budget 2.831000 ns (3,23) -> (3,22) 189s Info: Sink pwm_r_SB_DFF_Q_D_SB_LUT4_O_LC.I2 189s Info: Defined in: 189s Info: /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 189s Info: 1.2 26.3 Setup pwm_r_SB_DFF_Q_D_SB_LUT4_O_LC.I2 189s Info: 11.4 ns logic, 14.9 ns routing 189s 189s Info: Critical path report for cross-domain path 'posedge clk' -> '': 189s Info: curr total 189s Info: 1.4 1.4 Source pwm_g_SB_DFF_Q_D_SB_LUT4_O_LC.O 189s Info: 4.2 5.6 Net pwm_g budget 81.943001 ns (4,20) -> (0,30) 189s Info: Sink RGBA_DRIVER.RGB0PWM 189s Info: Defined in: 189s Info: rgb.v:53.12-53.17 189s Info: 1.4 ns logic, 4.2 ns routing 189s 189s Info: Max frequency for clock 'clk': 38.05 MHz (PASS at 32.00 MHz) 189s 189s Info: Max delay posedge clk -> : 5.64 ns 189s 189s Info: Slack histogram: 189s Info: legend: * represents 1 endpoint(s) 189s Info: + represents [1,1) endpoint(s) 189s Info: [ 4966, 8635) |***** 189s Info: [ 8635, 12304) |*** 189s Info: [ 12304, 15973) |** 189s Info: [ 15973, 19642) |************** 189s Info: [ 19642, 23311) |**************** 189s Info: [ 23311, 26980) |******************************************************** 189s Info: [ 26980, 30649) |** 189s Info: [ 30649, 34318) | 189s Info: [ 34318, 37987) | 189s Info: [ 37987, 41656) | 189s Info: [ 41656, 45325) | 189s Info: [ 45325, 48994) | 189s Info: [ 48994, 52663) | 189s Info: [ 52663, 56332) | 189s Info: [ 56332, 60001) | 189s Info: [ 60001, 63670) | 189s Info: [ 63670, 67339) | 189s Info: [ 67339, 71008) | 189s Info: [ 71008, 74677) | 189s Info: [ 74677, 78346) |*** 189s 1 warning, 0 errors 189s 189s Info: Program finished normally. 189s icepack rgb.asc rgb.bin 189s make: Leaving directory '/tmp/autopkgtest.DyuG3m/build.kB5/src/examples/up5k_rgb' 190s autopkgtest [00:12:46]: test examples-compile: -----------------------] 191s examples-compile PASS 191s autopkgtest [00:12:47]: test examples-compile: - - - - - - - - - - results - - - - - - - - - - 191s autopkgtest [00:12:47]: @@@@@@@@@@@@@@@@@@@@ summary 191s can-show-help PASS (superficial) 191s examples-compile PASS 208s Creating nova instance adt-noble-ppc64el-fpga-icestorm-20240316-000936-juju-7f2275-prod-proposed-migration-environment-2 from image adt/ubuntu-noble-ppc64el-server-20240315.img (UUID ce913c63-9f6c-46f7-a674-fa2454cb6d6b)...