0s autopkgtest [18:55:02]: starting date and time: 2024-03-19 18:55:02+0000 0s autopkgtest [18:55:02]: git checkout: 4a1cd702 l/adt_testbed: don't blame the testbed for unsolvable build deps 0s autopkgtest [18:55:02]: host juju-7f2275-prod-proposed-migration-environment-2; command line: /home/ubuntu/autopkgtest/runner/autopkgtest --output-dir /tmp/autopkgtest-work.xu0lw1xz/out --timeout-copy=6000 --setup-commands /home/ubuntu/autopkgtest-cloud/worker-config-production/setup-canonical.sh --apt-pocket=proposed=src:yosys,src:readline,src:yosys-plugin-ghdl --apt-upgrade yosys --timeout-short=300 --timeout-copy=20000 --timeout-build=20000 '--env=ADT_TEST_TRIGGERS=yosys/0.33-5build1 readline/8.2-3.1 yosys-plugin-ghdl/0.0~git20230419.5b64ccf-1' -- ssh -s /home/ubuntu/autopkgtest/ssh-setup/nova -- --flavor autopkgtest --security-groups autopkgtest-juju-7f2275-prod-proposed-migration-environment-2@bos01-arm64-45.secgroup --name adt-noble-arm64-yosys-20240319-163541-juju-7f2275-prod-proposed-migration-environment-2 --image adt/ubuntu-noble-arm64-server --keyname testbed-juju-7f2275-prod-proposed-migration-environment-2 --net-id=net_prod-proposed-migration -e TERM=linux -e ''"'"'http_proxy=http://squid.internal:3128'"'"'' -e ''"'"'https_proxy=http://squid.internal:3128'"'"'' -e ''"'"'no_proxy=127.0.0.1,127.0.1.1,login.ubuntu.com,localhost,localdomain,novalocal,internal,archive.ubuntu.com,ports.ubuntu.com,security.ubuntu.com,ddebs.ubuntu.com,changelogs.ubuntu.com,launchpadlibrarian.net,launchpadcontent.net,launchpad.net,10.24.0.0/24,keystone.ps5.canonical.com,objectstorage.prodstack5.canonical.com'"'"'' --mirror=http://us.ports.ubuntu.com/ubuntu-ports/ 151s autopkgtest [18:57:33]: testbed dpkg architecture: arm64 151s autopkgtest [18:57:33]: testbed apt version: 2.7.12 151s autopkgtest [18:57:33]: @@@@@@@@@@@@@@@@@@@@ test bed setup 152s Get:1 http://ftpmaster.internal/ubuntu noble-proposed InRelease [117 kB] 152s Get:2 http://ftpmaster.internal/ubuntu noble-proposed/universe Sources [3789 kB] 153s Get:3 http://ftpmaster.internal/ubuntu noble-proposed/restricted Sources [6540 B] 153s Get:4 http://ftpmaster.internal/ubuntu noble-proposed/main Sources [493 kB] 153s Get:5 http://ftpmaster.internal/ubuntu noble-proposed/multiverse Sources [52.7 kB] 153s Get:6 http://ftpmaster.internal/ubuntu noble-proposed/main arm64 Packages [658 kB] 153s Get:7 http://ftpmaster.internal/ubuntu noble-proposed/main arm64 c-n-f Metadata [3144 B] 153s Get:8 http://ftpmaster.internal/ubuntu noble-proposed/restricted arm64 Packages [33.6 kB] 153s Get:9 http://ftpmaster.internal/ubuntu noble-proposed/restricted arm64 c-n-f Metadata [116 B] 153s Get:10 http://ftpmaster.internal/ubuntu noble-proposed/universe arm64 Packages [4150 kB] 153s Get:11 http://ftpmaster.internal/ubuntu noble-proposed/universe arm64 c-n-f Metadata [8528 B] 153s Get:12 http://ftpmaster.internal/ubuntu noble-proposed/multiverse arm64 Packages [56.7 kB] 153s Get:13 http://ftpmaster.internal/ubuntu noble-proposed/multiverse arm64 c-n-f Metadata [116 B] 155s Fetched 9369 kB in 2s (5474 kB/s) 155s Reading package lists... 158s Reading package lists... 158s Building dependency tree... 158s Reading state information... 158s Calculating upgrade... 159s The following packages will be upgraded: 159s readline-common ubuntu-minimal ubuntu-standard 159s 3 upgraded, 0 newly installed, 0 to remove and 0 not upgraded. 159s Need to get 77.9 kB of archives. 159s After this operation, 0 B of additional disk space will be used. 159s Get:1 http://ftpmaster.internal/ubuntu noble-proposed/main arm64 readline-common all 8.2-3.1 [56.4 kB] 159s Get:2 http://ftpmaster.internal/ubuntu noble/main arm64 ubuntu-minimal arm64 1.536build1 [10.7 kB] 159s Get:3 http://ftpmaster.internal/ubuntu noble/main arm64 ubuntu-standard arm64 1.536build1 [10.7 kB] 159s Fetched 77.9 kB in 0s (210 kB/s) 159s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 75850 files and directories currently installed.) 159s Preparing to unpack .../readline-common_8.2-3.1_all.deb ... 159s Unpacking readline-common (8.2-3.1) over (8.2-3) ... 160s Preparing to unpack .../ubuntu-minimal_1.536build1_arm64.deb ... 160s Unpacking ubuntu-minimal (1.536build1) over (1.536) ... 160s Preparing to unpack .../ubuntu-standard_1.536build1_arm64.deb ... 160s Unpacking ubuntu-standard (1.536build1) over (1.536) ... 160s Setting up ubuntu-minimal (1.536build1) ... 160s Setting up ubuntu-standard (1.536build1) ... 160s Setting up readline-common (8.2-3.1) ... 160s Processing triggers for install-info (7.1-3) ... 160s Processing triggers for man-db (2.12.0-3) ... 160s Reading package lists... 160s Building dependency tree... 160s Reading state information... 161s 0 upgraded, 0 newly installed, 0 to remove and 0 not upgraded. 161s Hit:1 http://ftpmaster.internal/ubuntu noble-proposed InRelease 161s Hit:2 http://ftpmaster.internal/ubuntu noble InRelease 161s Hit:3 http://ftpmaster.internal/ubuntu noble-updates InRelease 161s Hit:4 http://ftpmaster.internal/ubuntu noble-security InRelease 163s Reading package lists... 163s Reading package lists... 163s Building dependency tree... 163s Reading state information... 163s Calculating upgrade... 164s 0 upgraded, 0 newly installed, 0 to remove and 0 not upgraded. 164s Reading package lists... 164s Building dependency tree... 164s Reading state information... 165s 0 upgraded, 0 newly installed, 0 to remove and 0 not upgraded. 168s autopkgtest [18:57:50]: testbed running kernel: Linux 6.8.0-11-generic #11-Ubuntu SMP PREEMPT_DYNAMIC Wed Feb 14 02:53:31 UTC 2024 168s autopkgtest [18:57:50]: @@@@@@@@@@@@@@@@@@@@ apt-source yosys 174s Get:1 http://ftpmaster.internal/ubuntu noble-proposed/universe yosys 0.33-5build1 (dsc) [2990 B] 174s Get:2 http://ftpmaster.internal/ubuntu noble-proposed/universe yosys 0.33-5build1 (tar) [6161 kB] 174s Get:3 http://ftpmaster.internal/ubuntu noble-proposed/universe yosys 0.33-5build1 (tar) [2586 kB] 174s Get:4 http://ftpmaster.internal/ubuntu noble-proposed/universe yosys 0.33-5build1 (diff) [30.2 kB] 174s gpgv: Signature made Fri Mar 15 18:03:30 2024 UTC 174s gpgv: using RSA key 568BF22A66337CBFC9A6B9B72C83DBC8E9BD0E37 174s gpgv: Can't check signature: No public key 174s dpkg-source: warning: cannot verify inline signature for ./yosys_0.33-5build1.dsc: no acceptable signature found 175s autopkgtest [18:57:57]: testing package yosys version 0.33-5build1 175s autopkgtest [18:57:57]: build not needed 186s autopkgtest [18:58:08]: test yosys-testsuite: preparing testbed 190s Reading package lists... 190s Building dependency tree... 190s Reading state information... 191s Starting pkgProblemResolver with broken count: 0 191s Starting 2 pkgProblemResolver with broken count: 0 191s Done 191s The following additional packages will be installed: 191s cpp cpp-13 cpp-13-aarch64-linux-gnu cpp-aarch64-linux-gnu g++ g++-13 191s g++-13-aarch64-linux-gnu g++-aarch64-linux-gnu gcc gcc-13 191s gcc-13-aarch64-linux-gnu gcc-aarch64-linux-gnu iverilog libasan8 libatomic1 191s libc-dev-bin libc6-dev libcc1-0 libcrypt-dev libffi-dev libgcc-13-dev 191s libgomp1 libhwasan0 libisl23 libitm1 liblsan0 libmpc3 libncurses-dev 191s libnsl-dev libpkgconf3 libreadline-dev libreadline8t64 libstdc++-13-dev 191s libtcl8.6 libtirpc-dev libtsan2 libubsan1 linux-libc-dev pkg-config pkgconf 191s pkgconf-bin python3-click python3-colorama rpcsvc-proto tcl tcl-dev tcl8.6 191s tcl8.6-dev yosys yosys-abc yosys-dev zlib1g-dev 191s Suggested packages: 191s cpp-doc gcc-13-locales cpp-13-doc gcc-13-doc gcc-multilib manpages-dev 191s autoconf automake libtool flex bison gdb gcc-doc gdb-aarch64-linux-gnu 191s gtkwave glibc-doc ncurses-doc readline-doc libstdc++-13-doc tcl-doc 191s tcl-tclreadline tcl8.6-doc 191s Recommended packages: 191s manpages manpages-dev libc-devtools xdot 191s The following packages will be REMOVED: 191s libreadline8 191s The following NEW packages will be installed: 191s autopkgtest-satdep cpp cpp-13 cpp-13-aarch64-linux-gnu cpp-aarch64-linux-gnu 191s g++ g++-13 g++-13-aarch64-linux-gnu g++-aarch64-linux-gnu gcc gcc-13 191s gcc-13-aarch64-linux-gnu gcc-aarch64-linux-gnu iverilog libasan8 libatomic1 191s libc-dev-bin libc6-dev libcc1-0 libcrypt-dev libffi-dev libgcc-13-dev 191s libgomp1 libhwasan0 libisl23 libitm1 liblsan0 libmpc3 libncurses-dev 191s libnsl-dev libpkgconf3 libreadline-dev libreadline8t64 libstdc++-13-dev 191s libtcl8.6 libtirpc-dev libtsan2 libubsan1 linux-libc-dev pkg-config pkgconf 191s pkgconf-bin python3-click python3-colorama rpcsvc-proto tcl tcl-dev tcl8.6 191s tcl8.6-dev yosys yosys-abc yosys-dev zlib1g-dev 191s 0 upgraded, 53 newly installed, 1 to remove and 0 not upgraded. 191s Need to get 76.4 MB/76.4 MB of archives. 191s After this operation, 271 MB of additional disk space will be used. 191s Get:1 /tmp/autopkgtest.9XLSHY/1-autopkgtest-satdep.deb autopkgtest-satdep arm64 0 [736 B] 192s Get:2 http://ftpmaster.internal/ubuntu noble-proposed/main arm64 libreadline8t64 arm64 8.2-3.1 [153 kB] 192s Get:3 http://ftpmaster.internal/ubuntu noble/main arm64 libisl23 arm64 0.26-3 [713 kB] 192s Get:4 http://ftpmaster.internal/ubuntu noble/main arm64 libmpc3 arm64 1.3.1-1 [55.3 kB] 192s Get:5 http://ftpmaster.internal/ubuntu noble/main arm64 cpp-13-aarch64-linux-gnu arm64 13.2.0-17ubuntu2 [10.3 MB] 193s Get:6 http://ftpmaster.internal/ubuntu noble/main arm64 cpp-13 arm64 13.2.0-17ubuntu2 [1028 B] 193s Get:7 http://ftpmaster.internal/ubuntu noble/main arm64 cpp-aarch64-linux-gnu arm64 4:13.2.0-7ubuntu1 [5316 B] 193s Get:8 http://ftpmaster.internal/ubuntu noble/main arm64 cpp arm64 4:13.2.0-7ubuntu1 [22.4 kB] 193s Get:9 http://ftpmaster.internal/ubuntu noble/main arm64 libcc1-0 arm64 14-20240303-1ubuntu1 [44.7 kB] 193s Get:10 http://ftpmaster.internal/ubuntu noble/main arm64 libgomp1 arm64 14-20240303-1ubuntu1 [144 kB] 193s Get:11 http://ftpmaster.internal/ubuntu noble/main arm64 libitm1 arm64 14-20240303-1ubuntu1 [27.7 kB] 193s Get:12 http://ftpmaster.internal/ubuntu noble/main arm64 libatomic1 arm64 14-20240303-1ubuntu1 [11.4 kB] 193s Get:13 http://ftpmaster.internal/ubuntu noble/main arm64 libasan8 arm64 14-20240303-1ubuntu1 [2919 kB] 193s Get:14 http://ftpmaster.internal/ubuntu noble/main arm64 liblsan0 arm64 14-20240303-1ubuntu1 [1282 kB] 193s Get:15 http://ftpmaster.internal/ubuntu noble/main arm64 libtsan2 arm64 14-20240303-1ubuntu1 [2687 kB] 194s Get:16 http://ftpmaster.internal/ubuntu noble/main arm64 libubsan1 arm64 14-20240303-1ubuntu1 [1151 kB] 194s Get:17 http://ftpmaster.internal/ubuntu noble/main arm64 libhwasan0 arm64 14-20240303-1ubuntu1 [1597 kB] 194s Get:18 http://ftpmaster.internal/ubuntu noble/main arm64 libgcc-13-dev arm64 13.2.0-17ubuntu2 [2464 kB] 194s Get:19 http://ftpmaster.internal/ubuntu noble/main arm64 gcc-13-aarch64-linux-gnu arm64 13.2.0-17ubuntu2 [20.1 MB] 196s Get:20 http://ftpmaster.internal/ubuntu noble/main arm64 gcc-13 arm64 13.2.0-17ubuntu2 [467 kB] 197s Get:21 http://ftpmaster.internal/ubuntu noble/main arm64 gcc-aarch64-linux-gnu arm64 4:13.2.0-7ubuntu1 [1198 B] 197s Get:22 http://ftpmaster.internal/ubuntu noble/main arm64 gcc arm64 4:13.2.0-7ubuntu1 [5018 B] 197s Get:23 http://ftpmaster.internal/ubuntu noble/main arm64 libc-dev-bin arm64 2.39-0ubuntu2 [19.7 kB] 197s Get:24 http://ftpmaster.internal/ubuntu noble/main arm64 linux-libc-dev arm64 6.8.0-11.11 [1569 kB] 197s Get:25 http://ftpmaster.internal/ubuntu noble/main arm64 libcrypt-dev arm64 1:4.4.36-4 [136 kB] 197s Get:26 http://ftpmaster.internal/ubuntu noble/main arm64 libtirpc-dev arm64 1.3.4+ds-1build1 [232 kB] 197s Get:27 http://ftpmaster.internal/ubuntu noble/main arm64 libnsl-dev arm64 1.3.0-3 [71.9 kB] 197s Get:28 http://ftpmaster.internal/ubuntu noble/main arm64 rpcsvc-proto arm64 1.4.2-0ubuntu6 [65.4 kB] 197s Get:29 http://ftpmaster.internal/ubuntu noble/main arm64 libc6-dev arm64 2.39-0ubuntu2 [1596 kB] 197s Get:30 http://ftpmaster.internal/ubuntu noble/main arm64 libstdc++-13-dev arm64 13.2.0-17ubuntu2 [2322 kB] 197s Get:31 http://ftpmaster.internal/ubuntu noble/main arm64 g++-13-aarch64-linux-gnu arm64 13.2.0-17ubuntu2 [11.7 MB] 199s Get:32 http://ftpmaster.internal/ubuntu noble/main arm64 g++-13 arm64 13.2.0-17ubuntu2 [14.4 kB] 199s Get:33 http://ftpmaster.internal/ubuntu noble/main arm64 g++-aarch64-linux-gnu arm64 4:13.2.0-7ubuntu1 [962 B] 199s Get:34 http://ftpmaster.internal/ubuntu noble/main arm64 g++ arm64 4:13.2.0-7ubuntu1 [1082 B] 199s Get:35 http://ftpmaster.internal/ubuntu noble/universe arm64 iverilog arm64 12.0-2 [2017 kB] 199s Get:36 http://ftpmaster.internal/ubuntu noble/main arm64 libncurses-dev arm64 6.4+20240113-1ubuntu1 [385 kB] 199s Get:37 http://ftpmaster.internal/ubuntu noble/main arm64 libpkgconf3 arm64 1.8.1-2 [31.2 kB] 199s Get:38 http://ftpmaster.internal/ubuntu noble-proposed/main arm64 libreadline-dev arm64 8.2-3.1 [177 kB] 199s Get:39 http://ftpmaster.internal/ubuntu noble/main arm64 libtcl8.6 arm64 8.6.13+dfsg-2 [980 kB] 199s Get:40 http://ftpmaster.internal/ubuntu noble/main arm64 pkgconf-bin arm64 1.8.1-2 [20.4 kB] 199s Get:41 http://ftpmaster.internal/ubuntu noble/main arm64 pkgconf arm64 1.8.1-2 [16.7 kB] 199s Get:42 http://ftpmaster.internal/ubuntu noble/main arm64 pkg-config arm64 1.8.1-2 [7170 B] 199s Get:43 http://ftpmaster.internal/ubuntu noble/main arm64 python3-colorama all 0.4.6-4 [32.1 kB] 199s Get:44 http://ftpmaster.internal/ubuntu noble/main arm64 python3-click all 8.1.6-1 [79.0 kB] 199s Get:45 http://ftpmaster.internal/ubuntu noble/main arm64 tcl8.6 arm64 8.6.13+dfsg-2 [14.6 kB] 199s Get:46 http://ftpmaster.internal/ubuntu noble/main arm64 tcl arm64 8.6.13 [3992 B] 199s Get:47 http://ftpmaster.internal/ubuntu noble/main arm64 zlib1g-dev arm64 1:1.3.dfsg-3ubuntu1 [895 kB] 199s Get:48 http://ftpmaster.internal/ubuntu noble/main arm64 tcl8.6-dev arm64 8.6.13+dfsg-2 [1024 kB] 199s Get:49 http://ftpmaster.internal/ubuntu noble/main arm64 tcl-dev arm64 8.6.13 [5752 B] 199s Get:50 http://ftpmaster.internal/ubuntu noble-proposed/universe arm64 yosys-abc arm64 0.33-5build1 [5594 kB] 200s Get:51 http://ftpmaster.internal/ubuntu noble-proposed/universe arm64 yosys arm64 0.33-5build1 [3098 kB] 200s Get:52 http://ftpmaster.internal/ubuntu noble/main arm64 libffi-dev arm64 3.4.6-1 [59.5 kB] 200s Get:53 http://ftpmaster.internal/ubuntu noble-proposed/universe arm64 yosys-dev arm64 0.33-5build1 [88.4 kB] 201s Fetched 76.4 MB in 9s (8476 kB/s) 201s dpkg: libreadline8:arm64: dependency problems, but removing anyway as you requested: 201s parted depends on libreadline8 (>= 6.0). 201s libpython3.12-stdlib:arm64 depends on libreadline8 (>= 7.0~beta). 201s libpython3.11-stdlib:arm64 depends on libreadline8 (>= 7.0~beta). 201s gpgsm depends on libreadline8 (>= 6.0). 201s gpgconf depends on libreadline8 (>= 6.0). 201s gpg depends on libreadline8 (>= 6.0). 201s gawk depends on libreadline8 (>= 6.0). 201s fdisk depends on libreadline8 (>= 6.0). 201s 201s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 75850 files and directories currently installed.) 201s Removing libreadline8:arm64 (8.2-3) ... 201s Selecting previously unselected package libreadline8t64:arm64. 201s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 75838 files and directories currently installed.) 201s Preparing to unpack .../00-libreadline8t64_8.2-3.1_arm64.deb ... 201s Adding 'diversion of /lib/aarch64-linux-gnu/libhistory.so.8 to /lib/aarch64-linux-gnu/libhistory.so.8.usr-is-merged by libreadline8t64' 201s Adding 'diversion of /lib/aarch64-linux-gnu/libhistory.so.8.2 to /lib/aarch64-linux-gnu/libhistory.so.8.2.usr-is-merged by libreadline8t64' 201s Adding 'diversion of /lib/aarch64-linux-gnu/libreadline.so.8 to /lib/aarch64-linux-gnu/libreadline.so.8.usr-is-merged by libreadline8t64' 201s Adding 'diversion of /lib/aarch64-linux-gnu/libreadline.so.8.2 to /lib/aarch64-linux-gnu/libreadline.so.8.2.usr-is-merged by libreadline8t64' 201s Unpacking libreadline8t64:arm64 (8.2-3.1) ... 201s Selecting previously unselected package libisl23:arm64. 201s Preparing to unpack .../01-libisl23_0.26-3_arm64.deb ... 201s Unpacking libisl23:arm64 (0.26-3) ... 201s Selecting previously unselected package libmpc3:arm64. 201s Preparing to unpack .../02-libmpc3_1.3.1-1_arm64.deb ... 201s Unpacking libmpc3:arm64 (1.3.1-1) ... 201s Selecting previously unselected package cpp-13-aarch64-linux-gnu. 201s Preparing to unpack .../03-cpp-13-aarch64-linux-gnu_13.2.0-17ubuntu2_arm64.deb ... 201s Unpacking cpp-13-aarch64-linux-gnu (13.2.0-17ubuntu2) ... 201s Selecting previously unselected package cpp-13. 201s Preparing to unpack .../04-cpp-13_13.2.0-17ubuntu2_arm64.deb ... 201s Unpacking cpp-13 (13.2.0-17ubuntu2) ... 201s Selecting previously unselected package cpp-aarch64-linux-gnu. 201s Preparing to unpack .../05-cpp-aarch64-linux-gnu_4%3a13.2.0-7ubuntu1_arm64.deb ... 201s Unpacking cpp-aarch64-linux-gnu (4:13.2.0-7ubuntu1) ... 201s Selecting previously unselected package cpp. 201s Preparing to unpack .../06-cpp_4%3a13.2.0-7ubuntu1_arm64.deb ... 201s Unpacking cpp (4:13.2.0-7ubuntu1) ... 201s Selecting previously unselected package libcc1-0:arm64. 201s Preparing to unpack .../07-libcc1-0_14-20240303-1ubuntu1_arm64.deb ... 201s Unpacking libcc1-0:arm64 (14-20240303-1ubuntu1) ... 201s Selecting previously unselected package libgomp1:arm64. 201s Preparing to unpack .../08-libgomp1_14-20240303-1ubuntu1_arm64.deb ... 201s Unpacking libgomp1:arm64 (14-20240303-1ubuntu1) ... 201s Selecting previously unselected package libitm1:arm64. 201s Preparing to unpack .../09-libitm1_14-20240303-1ubuntu1_arm64.deb ... 201s Unpacking libitm1:arm64 (14-20240303-1ubuntu1) ... 201s Selecting previously unselected package libatomic1:arm64. 201s Preparing to unpack .../10-libatomic1_14-20240303-1ubuntu1_arm64.deb ... 201s Unpacking libatomic1:arm64 (14-20240303-1ubuntu1) ... 201s Selecting previously unselected package libasan8:arm64. 201s Preparing to unpack .../11-libasan8_14-20240303-1ubuntu1_arm64.deb ... 201s Unpacking libasan8:arm64 (14-20240303-1ubuntu1) ... 201s Selecting previously unselected package liblsan0:arm64. 201s Preparing to unpack .../12-liblsan0_14-20240303-1ubuntu1_arm64.deb ... 201s Unpacking liblsan0:arm64 (14-20240303-1ubuntu1) ... 202s Selecting previously unselected package libtsan2:arm64. 202s Preparing to unpack .../13-libtsan2_14-20240303-1ubuntu1_arm64.deb ... 202s Unpacking libtsan2:arm64 (14-20240303-1ubuntu1) ... 202s Selecting previously unselected package libubsan1:arm64. 202s Preparing to unpack .../14-libubsan1_14-20240303-1ubuntu1_arm64.deb ... 202s Unpacking libubsan1:arm64 (14-20240303-1ubuntu1) ... 202s Selecting previously unselected package libhwasan0:arm64. 202s Preparing to unpack .../15-libhwasan0_14-20240303-1ubuntu1_arm64.deb ... 202s Unpacking libhwasan0:arm64 (14-20240303-1ubuntu1) ... 202s Selecting previously unselected package libgcc-13-dev:arm64. 202s Preparing to unpack .../16-libgcc-13-dev_13.2.0-17ubuntu2_arm64.deb ... 202s Unpacking libgcc-13-dev:arm64 (13.2.0-17ubuntu2) ... 202s Selecting previously unselected package gcc-13-aarch64-linux-gnu. 202s Preparing to unpack .../17-gcc-13-aarch64-linux-gnu_13.2.0-17ubuntu2_arm64.deb ... 202s Unpacking gcc-13-aarch64-linux-gnu (13.2.0-17ubuntu2) ... 202s Selecting previously unselected package gcc-13. 202s Preparing to unpack .../18-gcc-13_13.2.0-17ubuntu2_arm64.deb ... 202s Unpacking gcc-13 (13.2.0-17ubuntu2) ... 202s Selecting previously unselected package gcc-aarch64-linux-gnu. 202s Preparing to unpack .../19-gcc-aarch64-linux-gnu_4%3a13.2.0-7ubuntu1_arm64.deb ... 202s Unpacking gcc-aarch64-linux-gnu (4:13.2.0-7ubuntu1) ... 202s Selecting previously unselected package gcc. 202s Preparing to unpack .../20-gcc_4%3a13.2.0-7ubuntu1_arm64.deb ... 202s Unpacking gcc (4:13.2.0-7ubuntu1) ... 202s Selecting previously unselected package libc-dev-bin. 202s Preparing to unpack .../21-libc-dev-bin_2.39-0ubuntu2_arm64.deb ... 202s Unpacking libc-dev-bin (2.39-0ubuntu2) ... 202s Selecting previously unselected package linux-libc-dev:arm64. 202s Preparing to unpack .../22-linux-libc-dev_6.8.0-11.11_arm64.deb ... 202s Unpacking linux-libc-dev:arm64 (6.8.0-11.11) ... 203s Selecting previously unselected package libcrypt-dev:arm64. 203s Preparing to unpack .../23-libcrypt-dev_1%3a4.4.36-4_arm64.deb ... 203s Unpacking libcrypt-dev:arm64 (1:4.4.36-4) ... 203s Selecting previously unselected package libtirpc-dev:arm64. 203s Preparing to unpack .../24-libtirpc-dev_1.3.4+ds-1build1_arm64.deb ... 203s Unpacking libtirpc-dev:arm64 (1.3.4+ds-1build1) ... 203s Selecting previously unselected package libnsl-dev:arm64. 203s Preparing to unpack .../25-libnsl-dev_1.3.0-3_arm64.deb ... 203s Unpacking libnsl-dev:arm64 (1.3.0-3) ... 203s Selecting previously unselected package rpcsvc-proto. 203s Preparing to unpack .../26-rpcsvc-proto_1.4.2-0ubuntu6_arm64.deb ... 203s Unpacking rpcsvc-proto (1.4.2-0ubuntu6) ... 203s Selecting previously unselected package libc6-dev:arm64. 203s Preparing to unpack .../27-libc6-dev_2.39-0ubuntu2_arm64.deb ... 203s Unpacking libc6-dev:arm64 (2.39-0ubuntu2) ... 203s Selecting previously unselected package libstdc++-13-dev:arm64. 203s Preparing to unpack .../28-libstdc++-13-dev_13.2.0-17ubuntu2_arm64.deb ... 203s Unpacking libstdc++-13-dev:arm64 (13.2.0-17ubuntu2) ... 203s Selecting previously unselected package g++-13-aarch64-linux-gnu. 203s Preparing to unpack .../29-g++-13-aarch64-linux-gnu_13.2.0-17ubuntu2_arm64.deb ... 203s Unpacking g++-13-aarch64-linux-gnu (13.2.0-17ubuntu2) ... 203s Selecting previously unselected package g++-13. 203s Preparing to unpack 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tcl-dev:arm64. 204s Preparing to unpack .../47-tcl-dev_8.6.13_arm64.deb ... 204s Unpacking tcl-dev:arm64 (8.6.13) ... 204s Selecting previously unselected package yosys-abc. 204s Preparing to unpack .../48-yosys-abc_0.33-5build1_arm64.deb ... 204s Unpacking yosys-abc (0.33-5build1) ... 204s Selecting previously unselected package yosys. 204s Preparing to unpack .../49-yosys_0.33-5build1_arm64.deb ... 204s Unpacking yosys (0.33-5build1) ... 204s Selecting previously unselected package libffi-dev:arm64. 204s Preparing to unpack .../50-libffi-dev_3.4.6-1_arm64.deb ... 204s Unpacking libffi-dev:arm64 (3.4.6-1) ... 204s Selecting previously unselected package yosys-dev. 204s Preparing to unpack .../51-yosys-dev_0.33-5build1_arm64.deb ... 204s Unpacking yosys-dev (0.33-5build1) ... 204s Selecting previously unselected package autopkgtest-satdep. 204s Preparing to unpack .../52-1-autopkgtest-satdep.deb ... 204s Unpacking autopkgtest-satdep (0) ... 204s Setting up python3-colorama (0.4.6-4) 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libreadline-dev:arm64 (8.2-3.1) ... 205s Setting up gcc-13 (13.2.0-17ubuntu2) ... 205s Setting up zlib1g-dev:arm64 (1:1.3.dfsg-3ubuntu1) ... 205s Setting up cpp (4:13.2.0-7ubuntu1) ... 205s Setting up g++-13-aarch64-linux-gnu (13.2.0-17ubuntu2) ... 205s Setting up gcc-aarch64-linux-gnu (4:13.2.0-7ubuntu1) ... 205s Setting up g++-13 (13.2.0-17ubuntu2) ... 205s Setting up tcl8.6-dev:arm64 (8.6.13+dfsg-2) ... 205s Setting up gcc (4:13.2.0-7ubuntu1) ... 205s Setting up tcl-dev:arm64 (8.6.13) ... 205s Setting up g++-aarch64-linux-gnu (4:13.2.0-7ubuntu1) ... 205s Setting up yosys-dev (0.33-5build1) ... 205s Setting up g++ (4:13.2.0-7ubuntu1) ... 205s update-alternatives: using /usr/bin/g++ to provide /usr/bin/c++ (c++) in auto mode 205s Setting up autopkgtest-satdep (0) ... 205s Processing triggers for man-db (2.12.0-3) ... 205s Processing triggers for install-info (7.1-3) ... 205s Processing triggers for libc-bin (2.39-0ubuntu2) ... 209s (Reading database ... 79687 files and directories currently installed.) 209s Removing autopkgtest-satdep (0) ... 210s autopkgtest [18:58:32]: test yosys-testsuite: [----------------------- 210s + [ 1 -ge 1 ] 210s + testdir=. 210s + shift 210s + mkdir -p . 210s + cd . 210s + ln -sf /usr/bin/yosys . 210s + ln -sf /usr/bin/yosys-abc . 210s + ln -sf /usr/bin/yosys-config . 210s + sed -i s/^test:.*/test: $(EXTRA_TARGETS)/ Makefile 210s + make test CONFIG=gcc ABCPULL=0 210s mkdir -p share/include/kernel/ 210s cp "./"/kernel/yosys.h share/include/kernel/yosys.h 210s mkdir -p share/include/kernel/ 210s cp "./"/kernel/hashlib.h share/include/kernel/hashlib.h 210s mkdir -p share/include/kernel/ 210s cp "./"/kernel/log.h share/include/kernel/log.h 210s mkdir -p share/include/kernel/ 210s cp "./"/kernel/rtlil.h share/include/kernel/rtlil.h 210s mkdir -p share/include/kernel/ 210s cp "./"/kernel/binding.h share/include/kernel/binding.h 210s mkdir -p share/include/kernel/ 210s cp "./"/kernel/register.h share/include/kernel/register.h 210s mkdir -p share/include/kernel/ 210s cp "./"/kernel/cellaigs.h share/include/kernel/cellaigs.h 210s mkdir -p share/include/kernel/ 210s cp "./"/kernel/celltypes.h share/include/kernel/celltypes.h 210s mkdir -p share/include/kernel/ 210s cp "./"/kernel/celledges.h share/include/kernel/celledges.h 210s mkdir -p share/include/kernel/ 210s cp "./"/kernel/consteval.h share/include/kernel/consteval.h 210s mkdir -p share/include/kernel/ 210s cp "./"/kernel/constids.inc share/include/kernel/constids.inc 210s mkdir -p share/include/kernel/ 210s cp "./"/kernel/sigtools.h share/include/kernel/sigtools.h 210s mkdir -p share/include/kernel/ 210s cp "./"/kernel/modtools.h share/include/kernel/modtools.h 210s mkdir -p share/include/kernel/ 210s cp "./"/kernel/macc.h share/include/kernel/macc.h 210s mkdir -p share/include/kernel/ 210s cp "./"/kernel/utils.h share/include/kernel/utils.h 210s mkdir -p share/include/kernel/ 210s cp "./"/kernel/satgen.h share/include/kernel/satgen.h 210s mkdir -p share/include/kernel/ 210s cp "./"/kernel/qcsat.h share/include/kernel/qcsat.h 210s mkdir -p share/include/kernel/ 210s cp "./"/kernel/ff.h share/include/kernel/ff.h 210s mkdir -p share/include/kernel/ 210s cp "./"/kernel/ffinit.h share/include/kernel/ffinit.h 210s mkdir -p share/include/kernel/ 210s cp "./"/kernel/fstdata.h share/include/kernel/fstdata.h 210s mkdir -p share/include/kernel/ 210s cp "./"/kernel/mem.h share/include/kernel/mem.h 210s mkdir -p share/include/kernel/ 210s cp "./"/kernel/yw.h share/include/kernel/yw.h 210s mkdir -p share/include/kernel/ 210s cp "./"/kernel/json.h share/include/kernel/json.h 210s mkdir -p share/include/libs/ezsat/ 210s cp "./"/libs/ezsat/ezsat.h share/include/libs/ezsat/ezsat.h 210s mkdir -p share/include/libs/ezsat/ 210s cp "./"/libs/ezsat/ezminisat.h share/include/libs/ezsat/ezminisat.h 210s mkdir -p share/include/libs/fst/ 210s cp "./"/libs/fst/fstapi.h share/include/libs/fst/fstapi.h 210s mkdir -p share/include/libs/sha1/ 210s cp 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share/include/backends/cxxrtl/cxxrtl_vcd.h 210s mkdir -p share/include/backends/cxxrtl/ 210s cp "./"/backends/cxxrtl/cxxrtl_capi.cc share/include/backends/cxxrtl/cxxrtl_capi.cc 210s mkdir -p share/include/backends/cxxrtl/ 210s cp "./"/backends/cxxrtl/cxxrtl_capi.h share/include/backends/cxxrtl/cxxrtl_capi.h 210s mkdir -p share/include/backends/cxxrtl/ 210s cp "./"/backends/cxxrtl/cxxrtl_vcd_capi.cc share/include/backends/cxxrtl/cxxrtl_vcd_capi.cc 210s mkdir -p share/include/backends/cxxrtl/ 210s cp "./"/backends/cxxrtl/cxxrtl_vcd_capi.h share/include/backends/cxxrtl/cxxrtl_vcd_capi.h 210s mkdir -p share/python3 210s cp "./"/backends/smt2/smtio.py share/python3/smtio.py 210s mkdir -p share/python3 210s cp "./"/backends/smt2/ywio.py share/python3/ywio.py 210s mkdir -p share/achronix/speedster22i/ 210s cp "./"/techlibs/achronix/speedster22i/cells_sim.v share/achronix/speedster22i/cells_sim.v 210s mkdir -p share/achronix/speedster22i/ 210s cp "./"/techlibs/achronix/speedster22i/cells_map.v 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cp "./"/techlibs/coolrunner2/cells_latch.v share/coolrunner2/cells_latch.v 211s mkdir -p share/coolrunner2 211s cp "./"/techlibs/coolrunner2/cells_sim.v share/coolrunner2/cells_sim.v 211s mkdir -p share/coolrunner2 211s cp "./"/techlibs/coolrunner2/cells_counter_map.v share/coolrunner2/cells_counter_map.v 211s mkdir -p share/coolrunner2 211s cp "./"/techlibs/coolrunner2/tff_extract.v share/coolrunner2/tff_extract.v 211s mkdir -p share/coolrunner2 211s cp "./"/techlibs/coolrunner2/xc2_dff.lib share/coolrunner2/xc2_dff.lib 211s mkdir -p share/ecp5 211s cp "./"/techlibs/ecp5/cells_ff.vh share/ecp5/cells_ff.vh 211s mkdir -p share/ecp5 211s cp "./"/techlibs/ecp5/cells_io.vh share/ecp5/cells_io.vh 211s mkdir -p share/ecp5 211s cp "./"/techlibs/ecp5/cells_map.v share/ecp5/cells_map.v 211s mkdir -p share/ecp5 211s cp "./"/techlibs/ecp5/cells_sim.v share/ecp5/cells_sim.v 211s mkdir -p share/ecp5 211s cp "./"/techlibs/ecp5/cells_bb.v share/ecp5/cells_bb.v 211s mkdir -p share/ecp5 211s cp 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"./"/techlibs/efinix/gbuf_map.v share/efinix/gbuf_map.v 211s mkdir -p share/efinix 211s cp "./"/techlibs/efinix/brams.txt share/efinix/brams.txt 211s mkdir -p share/fabulous 211s cp "./"/techlibs/fabulous/cells_map.v share/fabulous/cells_map.v 211s mkdir -p share/fabulous 211s cp "./"/techlibs/fabulous/prims.v share/fabulous/prims.v 211s mkdir -p share/fabulous 211s cp "./"/techlibs/fabulous/latches_map.v share/fabulous/latches_map.v 211s mkdir -p share/fabulous 211s cp "./"/techlibs/fabulous/ff_map.v share/fabulous/ff_map.v 211s mkdir -p share/fabulous 211s cp "./"/techlibs/fabulous/ram_regfile.txt share/fabulous/ram_regfile.txt 211s mkdir -p share/fabulous 211s cp "./"/techlibs/fabulous/regfile_map.v share/fabulous/regfile_map.v 211s mkdir -p share/fabulous 211s cp "./"/techlibs/fabulous/io_map.v share/fabulous/io_map.v 211s mkdir -p share/fabulous 211s cp "./"/techlibs/fabulous/arith_map.v share/fabulous/arith_map.v 211s mkdir -p share/gatemate 211s cp "./"/techlibs/gatemate/reg_map.v share/gatemate/reg_map.v 211s mkdir -p share/gatemate 211s cp "./"/techlibs/gatemate/mux_map.v share/gatemate/mux_map.v 211s mkdir -p share/gatemate 211s cp "./"/techlibs/gatemate/lut_map.v share/gatemate/lut_map.v 211s mkdir -p share/gatemate 211s cp "./"/techlibs/gatemate/mul_map.v share/gatemate/mul_map.v 211s mkdir -p share/gatemate 211s cp "./"/techlibs/gatemate/arith_map.v share/gatemate/arith_map.v 211s mkdir -p share/gatemate 211s cp "./"/techlibs/gatemate/cells_sim.v share/gatemate/cells_sim.v 211s mkdir -p share/gatemate 211s cp "./"/techlibs/gatemate/cells_bb.v share/gatemate/cells_bb.v 211s mkdir -p share/gatemate 211s cp "./"/techlibs/gatemate/brams_map.v share/gatemate/brams_map.v 211s mkdir -p share/gatemate 211s cp "./"/techlibs/gatemate/brams.txt share/gatemate/brams.txt 211s mkdir -p share/gatemate 211s cp "./"/techlibs/gatemate/brams_init_20.vh share/gatemate/brams_init_20.vh 211s mkdir -p share/gatemate 211s cp "./"/techlibs/gatemate/brams_init_40.vh share/gatemate/brams_init_40.vh 211s mkdir -p share/gatemate 211s cp "./"/techlibs/gatemate/inv_map.v share/gatemate/inv_map.v 211s mkdir -p techlibs/gatemate 211s python3 techlibs/gatemate/make_lut_tree_lib.py 211s touch techlibs/gatemate/lut_tree_lib.mk 211s mkdir -p share/gatemate 211s cp techlibs/gatemate/lut_tree_cells.genlib share/gatemate/lut_tree_cells.genlib 211s mkdir -p share/gatemate 211s cp techlibs/gatemate/lut_tree_map.v share/gatemate/lut_tree_map.v 211s mkdir -p share/gowin 211s cp "./"/techlibs/gowin/cells_map.v share/gowin/cells_map.v 211s mkdir -p share/gowin 211s cp "./"/techlibs/gowin/cells_sim.v share/gowin/cells_sim.v 211s mkdir -p share/gowin 211s cp "./"/techlibs/gowin/cells_xtra.v share/gowin/cells_xtra.v 211s mkdir -p share/gowin 211s cp "./"/techlibs/gowin/arith_map.v share/gowin/arith_map.v 211s mkdir -p share/gowin 211s cp "./"/techlibs/gowin/brams_map.v share/gowin/brams_map.v 211s mkdir -p share/gowin 211s cp "./"/techlibs/gowin/brams.txt share/gowin/brams.txt 211s mkdir -p share/gowin 211s cp "./"/techlibs/gowin/lutrams_map.v share/gowin/lutrams_map.v 211s mkdir -p share/gowin 211s cp "./"/techlibs/gowin/lutrams.txt share/gowin/lutrams.txt 211s mkdir -p share/greenpak4 211s cp "./"/techlibs/greenpak4/cells_blackbox.v share/greenpak4/cells_blackbox.v 211s mkdir -p share/greenpak4 211s cp "./"/techlibs/greenpak4/cells_latch.v share/greenpak4/cells_latch.v 211s mkdir -p share/greenpak4 211s cp "./"/techlibs/greenpak4/cells_map.v share/greenpak4/cells_map.v 211s mkdir -p share/greenpak4 211s cp "./"/techlibs/greenpak4/cells_sim.v share/greenpak4/cells_sim.v 211s mkdir -p share/greenpak4 211s cp "./"/techlibs/greenpak4/cells_sim_ams.v share/greenpak4/cells_sim_ams.v 211s mkdir -p share/greenpak4 211s cp "./"/techlibs/greenpak4/cells_sim_digital.v share/greenpak4/cells_sim_digital.v 211s mkdir -p share/greenpak4 211s cp "./"/techlibs/greenpak4/cells_sim_wip.v share/greenpak4/cells_sim_wip.v 211s mkdir -p share/greenpak4 211s cp "./"/techlibs/greenpak4/gp_dff.lib share/greenpak4/gp_dff.lib 211s mkdir -p share/ice40 211s cp "./"/techlibs/ice40/arith_map.v share/ice40/arith_map.v 211s mkdir -p share/ice40 211s cp "./"/techlibs/ice40/cells_map.v share/ice40/cells_map.v 211s mkdir -p share/ice40 211s cp "./"/techlibs/ice40/ff_map.v share/ice40/ff_map.v 211s mkdir -p share/ice40 211s cp "./"/techlibs/ice40/cells_sim.v share/ice40/cells_sim.v 211s mkdir -p share/ice40 211s cp "./"/techlibs/ice40/latches_map.v share/ice40/latches_map.v 211s mkdir -p share/ice40 211s cp "./"/techlibs/ice40/brams.txt share/ice40/brams.txt 211s mkdir -p share/ice40 211s cp "./"/techlibs/ice40/brams_map.v share/ice40/brams_map.v 211s mkdir -p share/ice40 211s cp "./"/techlibs/ice40/spram.txt share/ice40/spram.txt 211s mkdir -p share/ice40 211s cp "./"/techlibs/ice40/spram_map.v share/ice40/spram_map.v 211s mkdir -p share/ice40 211s cp "./"/techlibs/ice40/dsp_map.v share/ice40/dsp_map.v 211s mkdir -p share/ice40 211s cp "./"/techlibs/ice40/abc9_model.v share/ice40/abc9_model.v 211s mkdir -p share/intel/common 211s cp "./"/techlibs/intel/common/m9k_bb.v share/intel/common/m9k_bb.v 211s mkdir -p share/intel/common 211s cp "./"/techlibs/intel/common/altpll_bb.v share/intel/common/altpll_bb.v 211s mkdir -p share/intel/common 211s cp "./"/techlibs/intel/common/brams_m9k.txt share/intel/common/brams_m9k.txt 211s mkdir -p share/intel/common 211s cp "./"/techlibs/intel/common/brams_map_m9k.v share/intel/common/brams_map_m9k.v 211s mkdir -p share/intel/common 211s cp "./"/techlibs/intel/common/ff_map.v share/intel/common/ff_map.v 211s mkdir -p share/intel/max10 211s cp "./"/techlibs/intel/max10/cells_sim.v share/intel/max10/cells_sim.v 211s mkdir -p share/intel/cyclone10lp 211s cp "./"/techlibs/intel/cyclone10lp/cells_sim.v share/intel/cyclone10lp/cells_sim.v 211s mkdir -p share/intel/cycloneiv 211s cp "./"/techlibs/intel/cycloneiv/cells_sim.v share/intel/cycloneiv/cells_sim.v 211s mkdir -p share/intel/cycloneive 211s cp "./"/techlibs/intel/cycloneive/cells_sim.v share/intel/cycloneive/cells_sim.v 211s mkdir -p share/intel/max10 211s cp "./"/techlibs/intel/max10/cells_map.v share/intel/max10/cells_map.v 211s mkdir -p share/intel/cyclone10lp 211s cp "./"/techlibs/intel/cyclone10lp/cells_map.v share/intel/cyclone10lp/cells_map.v 211s mkdir -p share/intel/cycloneiv 211s cp "./"/techlibs/intel/cycloneiv/cells_map.v share/intel/cycloneiv/cells_map.v 211s mkdir -p share/intel/cycloneive 211s cp "./"/techlibs/intel/cycloneive/cells_map.v share/intel/cycloneive/cells_map.v 211s mkdir -p share/intel_alm/common 211s cp "./"/techlibs/intel_alm/common/abc9_map.v share/intel_alm/common/abc9_map.v 211s mkdir -p share/intel_alm/common 211s cp "./"/techlibs/intel_alm/common/abc9_unmap.v share/intel_alm/common/abc9_unmap.v 211s mkdir -p share/intel_alm/common 211s cp "./"/techlibs/intel_alm/common/abc9_model.v share/intel_alm/common/abc9_model.v 211s mkdir -p share/intel_alm/common 211s cp "./"/techlibs/intel_alm/common/alm_map.v share/intel_alm/common/alm_map.v 211s mkdir -p share/intel_alm/common 211s cp "./"/techlibs/intel_alm/common/alm_sim.v share/intel_alm/common/alm_sim.v 211s mkdir -p share/intel_alm/common 211s cp "./"/techlibs/intel_alm/common/arith_alm_map.v share/intel_alm/common/arith_alm_map.v 211s mkdir -p share/intel_alm/common 211s cp "./"/techlibs/intel_alm/common/dff_map.v share/intel_alm/common/dff_map.v 211s mkdir -p share/intel_alm/common 211s cp "./"/techlibs/intel_alm/common/dff_sim.v share/intel_alm/common/dff_sim.v 211s mkdir -p share/intel_alm/common 211s cp "./"/techlibs/intel_alm/common/dsp_sim.v share/intel_alm/common/dsp_sim.v 211s mkdir -p share/intel_alm/common 211s cp "./"/techlibs/intel_alm/common/dsp_map.v share/intel_alm/common/dsp_map.v 211s mkdir -p share/intel_alm/common 211s cp "./"/techlibs/intel_alm/common/mem_sim.v share/intel_alm/common/mem_sim.v 211s mkdir -p share/intel_alm/common 211s cp "./"/techlibs/intel_alm/common/misc_sim.v share/intel_alm/common/misc_sim.v 211s mkdir -p share/intel_alm/cyclonev 211s cp "./"/techlibs/intel_alm/cyclonev/cells_sim.v share/intel_alm/cyclonev/cells_sim.v 211s mkdir -p share/intel_alm/common 211s cp "./"/techlibs/intel_alm/common/bram_m10k.txt share/intel_alm/common/bram_m10k.txt 211s mkdir -p share/intel_alm/common 211s cp "./"/techlibs/intel_alm/common/bram_m10k_map.v share/intel_alm/common/bram_m10k_map.v 211s mkdir -p share/intel_alm/common 211s cp "./"/techlibs/intel_alm/common/bram_m20k.txt share/intel_alm/common/bram_m20k.txt 211s mkdir -p share/intel_alm/common 211s cp "./"/techlibs/intel_alm/common/bram_m20k_map.v share/intel_alm/common/bram_m20k_map.v 211s mkdir -p share/intel_alm/common 211s cp "./"/techlibs/intel_alm/common/lutram_mlab.txt share/intel_alm/common/lutram_mlab.txt 211s mkdir -p share/intel_alm/common 211s cp "./"/techlibs/intel_alm/common/megafunction_bb.v share/intel_alm/common/megafunction_bb.v 211s mkdir -p share/intel_alm/common 211s cp "./"/techlibs/intel_alm/common/quartus_rename.v share/intel_alm/common/quartus_rename.v 211s mkdir -p share/lattice 211s cp "./"/techlibs/lattice/cells_ff.vh share/lattice/cells_ff.vh 211s mkdir -p share/lattice 211s cp "./"/techlibs/lattice/cells_io.vh share/lattice/cells_io.vh 211s mkdir -p share/lattice 211s cp "./"/techlibs/lattice/cells_map.v share/lattice/cells_map.v 211s mkdir -p share/lattice 211s cp "./"/techlibs/lattice/common_sim.vh share/lattice/common_sim.vh 211s mkdir -p share/lattice 211s cp "./"/techlibs/lattice/ccu2d_sim.vh share/lattice/ccu2d_sim.vh 211s mkdir -p share/lattice 211s cp "./"/techlibs/lattice/ccu2c_sim.vh share/lattice/ccu2c_sim.vh 211s mkdir -p share/lattice 211s cp "./"/techlibs/lattice/cells_sim_ecp5.v share/lattice/cells_sim_ecp5.v 211s mkdir -p share/lattice 211s cp "./"/techlibs/lattice/cells_sim_xo2.v share/lattice/cells_sim_xo2.v 211s mkdir -p share/lattice 211s cp "./"/techlibs/lattice/cells_sim_xo3.v share/lattice/cells_sim_xo3.v 211s mkdir -p share/lattice 211s cp "./"/techlibs/lattice/cells_sim_xo3d.v share/lattice/cells_sim_xo3d.v 211s mkdir -p share/lattice 211s cp "./"/techlibs/lattice/cells_bb_ecp5.v share/lattice/cells_bb_ecp5.v 211s mkdir -p share/lattice 211s cp "./"/techlibs/lattice/cells_bb_xo2.v share/lattice/cells_bb_xo2.v 211s mkdir -p share/lattice 211s cp "./"/techlibs/lattice/cells_bb_xo3.v share/lattice/cells_bb_xo3.v 211s mkdir -p share/lattice 211s cp "./"/techlibs/lattice/cells_bb_xo3d.v share/lattice/cells_bb_xo3d.v 211s mkdir -p share/lattice 211s cp "./"/techlibs/lattice/lutrams_map.v share/lattice/lutrams_map.v 211s mkdir -p share/lattice 211s cp "./"/techlibs/lattice/lutrams.txt share/lattice/lutrams.txt 211s mkdir -p share/lattice 211s cp "./"/techlibs/lattice/brams_map_16kd.v share/lattice/brams_map_16kd.v 211s mkdir -p share/lattice 211s cp "./"/techlibs/lattice/brams_16kd.txt share/lattice/brams_16kd.txt 211s mkdir -p share/lattice 211s cp "./"/techlibs/lattice/brams_map_8kc.v share/lattice/brams_map_8kc.v 211s mkdir -p share/lattice 211s cp "./"/techlibs/lattice/brams_8kc.txt share/lattice/brams_8kc.txt 211s mkdir -p share/lattice 211s cp "./"/techlibs/lattice/arith_map_ccu2c.v share/lattice/arith_map_ccu2c.v 211s mkdir -p share/lattice 211s cp "./"/techlibs/lattice/arith_map_ccu2d.v share/lattice/arith_map_ccu2d.v 211s mkdir -p share/lattice 211s cp "./"/techlibs/lattice/latches_map.v share/lattice/latches_map.v 211s mkdir -p share/lattice 211s cp "./"/techlibs/lattice/dsp_map_18x18.v share/lattice/dsp_map_18x18.v 211s mkdir -p share/nexus 211s cp "./"/techlibs/nexus/cells_map.v share/nexus/cells_map.v 211s mkdir -p share/nexus 211s cp "./"/techlibs/nexus/cells_sim.v share/nexus/cells_sim.v 211s mkdir -p share/nexus 211s cp "./"/techlibs/nexus/parse_init.vh share/nexus/parse_init.vh 211s mkdir -p share/nexus 211s cp "./"/techlibs/nexus/cells_xtra.v share/nexus/cells_xtra.v 211s mkdir -p share/nexus 211s cp "./"/techlibs/nexus/lutrams_map.v share/nexus/lutrams_map.v 211s mkdir -p share/nexus 211s cp "./"/techlibs/nexus/lutrams.txt share/nexus/lutrams.txt 211s mkdir -p share/nexus 211s cp "./"/techlibs/nexus/brams_map.v share/nexus/brams_map.v 211s mkdir -p share/nexus 211s cp "./"/techlibs/nexus/brams.txt share/nexus/brams.txt 211s mkdir -p share/nexus 211s cp "./"/techlibs/nexus/lrams_map.v share/nexus/lrams_map.v 211s mkdir -p share/nexus 211s cp "./"/techlibs/nexus/lrams.txt share/nexus/lrams.txt 211s mkdir -p share/nexus 211s cp "./"/techlibs/nexus/arith_map.v share/nexus/arith_map.v 211s mkdir -p share/nexus 211s cp "./"/techlibs/nexus/latches_map.v share/nexus/latches_map.v 211s mkdir -p share/nexus 211s cp "./"/techlibs/nexus/dsp_map.v share/nexus/dsp_map.v 211s mkdir -p share/quicklogic 211s cp "./"/techlibs/quicklogic/pp3_ffs_map.v share/quicklogic/pp3_ffs_map.v 211s mkdir -p share/quicklogic 211s cp "./"/techlibs/quicklogic/pp3_lut_map.v share/quicklogic/pp3_lut_map.v 211s mkdir -p share/quicklogic 211s cp "./"/techlibs/quicklogic/pp3_latches_map.v share/quicklogic/pp3_latches_map.v 211s mkdir -p share/quicklogic 211s cp "./"/techlibs/quicklogic/pp3_cells_map.v share/quicklogic/pp3_cells_map.v 211s mkdir -p share/quicklogic 211s cp "./"/techlibs/quicklogic/cells_sim.v share/quicklogic/cells_sim.v 211s mkdir -p share/quicklogic 211s cp "./"/techlibs/quicklogic/lut_sim.v share/quicklogic/lut_sim.v 211s mkdir -p share/quicklogic 211s cp "./"/techlibs/quicklogic/pp3_cells_sim.v share/quicklogic/pp3_cells_sim.v 211s mkdir -p share/quicklogic 211s cp "./"/techlibs/quicklogic/abc9_model.v share/quicklogic/abc9_model.v 211s mkdir -p share/quicklogic 211s cp "./"/techlibs/quicklogic/abc9_map.v share/quicklogic/abc9_map.v 211s mkdir -p share/quicklogic 211s cp "./"/techlibs/quicklogic/abc9_unmap.v share/quicklogic/abc9_unmap.v 211s mkdir -p share/sf2 211s cp "./"/techlibs/sf2/arith_map.v share/sf2/arith_map.v 211s mkdir -p share/sf2 211s cp "./"/techlibs/sf2/cells_map.v share/sf2/cells_map.v 211s mkdir -p share/sf2 211s cp "./"/techlibs/sf2/cells_sim.v share/sf2/cells_sim.v 211s mkdir -p share/xilinx 211s cp "./"/techlibs/xilinx/cells_map.v share/xilinx/cells_map.v 211s mkdir -p share/xilinx 211s cp "./"/techlibs/xilinx/cells_sim.v share/xilinx/cells_sim.v 211s mkdir -p share/xilinx 211s cp "./"/techlibs/xilinx/cells_xtra.v share/xilinx/cells_xtra.v 211s mkdir -p share/xilinx 211s cp "./"/techlibs/xilinx/lutrams_xcv.txt share/xilinx/lutrams_xcv.txt 211s mkdir -p share/xilinx 211s cp "./"/techlibs/xilinx/lutrams_xcv_map.v share/xilinx/lutrams_xcv_map.v 211s mkdir -p share/xilinx 211s cp "./"/techlibs/xilinx/lutrams_xc5v.txt share/xilinx/lutrams_xc5v.txt 211s mkdir -p share/xilinx 211s cp "./"/techlibs/xilinx/lutrams_xcu.txt share/xilinx/lutrams_xcu.txt 211s mkdir -p share/xilinx 211s cp "./"/techlibs/xilinx/lutrams_xc5v_map.v share/xilinx/lutrams_xc5v_map.v 211s mkdir -p share/xilinx 211s cp "./"/techlibs/xilinx/brams_xcv.txt share/xilinx/brams_xcv.txt 211s mkdir -p share/xilinx 211s cp "./"/techlibs/xilinx/brams_xcv_map.v share/xilinx/brams_xcv_map.v 211s mkdir -p share/xilinx 211s cp "./"/techlibs/xilinx/brams_defs.vh share/xilinx/brams_defs.vh 211s mkdir -p share/xilinx 211s cp "./"/techlibs/xilinx/brams_xc2v.txt share/xilinx/brams_xc2v.txt 211s mkdir -p share/xilinx 211s cp "./"/techlibs/xilinx/brams_xc2v_map.v share/xilinx/brams_xc2v_map.v 211s mkdir -p share/xilinx 211s cp "./"/techlibs/xilinx/brams_xc3sda.txt share/xilinx/brams_xc3sda.txt 211s mkdir -p share/xilinx 211s cp "./"/techlibs/xilinx/brams_xc3sda_map.v share/xilinx/brams_xc3sda_map.v 211s mkdir -p share/xilinx 211s cp "./"/techlibs/xilinx/brams_xc4v.txt share/xilinx/brams_xc4v.txt 211s mkdir -p share/xilinx 211s cp "./"/techlibs/xilinx/brams_xc4v_map.v share/xilinx/brams_xc4v_map.v 211s mkdir -p share/xilinx 211s cp "./"/techlibs/xilinx/brams_xc5v_map.v share/xilinx/brams_xc5v_map.v 211s mkdir -p share/xilinx 211s cp "./"/techlibs/xilinx/brams_xc6v_map.v share/xilinx/brams_xc6v_map.v 211s mkdir -p share/xilinx 211s cp "./"/techlibs/xilinx/brams_xcu_map.v share/xilinx/brams_xcu_map.v 211s mkdir -p share/xilinx 211s cp "./"/techlibs/xilinx/urams.txt share/xilinx/urams.txt 211s mkdir -p share/xilinx 211s cp "./"/techlibs/xilinx/urams_map.v share/xilinx/urams_map.v 211s mkdir -p share/xilinx 211s cp "./"/techlibs/xilinx/arith_map.v share/xilinx/arith_map.v 211s mkdir -p share/xilinx 211s cp "./"/techlibs/xilinx/ff_map.v share/xilinx/ff_map.v 211s mkdir -p share/xilinx 211s cp "./"/techlibs/xilinx/lut_map.v share/xilinx/lut_map.v 211s mkdir -p share/xilinx 211s cp "./"/techlibs/xilinx/mux_map.v share/xilinx/mux_map.v 211s mkdir -p share/xilinx 211s cp "./"/techlibs/xilinx/xc3s_mult_map.v share/xilinx/xc3s_mult_map.v 211s mkdir -p share/xilinx 211s cp "./"/techlibs/xilinx/xc3sda_dsp_map.v share/xilinx/xc3sda_dsp_map.v 211s mkdir -p share/xilinx 211s cp "./"/techlibs/xilinx/xc6s_dsp_map.v share/xilinx/xc6s_dsp_map.v 211s mkdir -p share/xilinx 211s cp "./"/techlibs/xilinx/xc4v_dsp_map.v share/xilinx/xc4v_dsp_map.v 211s mkdir -p share/xilinx 211s cp "./"/techlibs/xilinx/xc5v_dsp_map.v share/xilinx/xc5v_dsp_map.v 211s mkdir -p share/xilinx 211s cp "./"/techlibs/xilinx/xc7_dsp_map.v share/xilinx/xc7_dsp_map.v 211s mkdir -p share/xilinx 211s cp "./"/techlibs/xilinx/xcu_dsp_map.v share/xilinx/xcu_dsp_map.v 211s mkdir -p share/xilinx 211s cp "./"/techlibs/xilinx/abc9_model.v share/xilinx/abc9_model.v 211s cd tests/simple && bash run-test.sh "" 211s make[1]: Entering directory '/tmp/autopkgtest.9XLSHY/build.lOV/src/tests/simple' 211s + gcc -Wall -o /tmp/autopkgtest.9XLSHY/build.lOV/src/tests/tools/cmp_tbdata /tmp/autopkgtest.9XLSHY/build.lOV/src/tests/tools/cmp_tbdata.c 212s Test: arrays02 -> ok 214s Test: asgn_binop -> ok 214s Test: case_expr_extend -> ok 214s Test: case_expr_query -> ok 215s Test: defvalue -> ok 215s Test: implicit_ports -> ok 215s Test: lesser_size_cast -> ok 215s Test: local_loop_var -> ok 216s Test: macro_arg_spaces -> ok 216s Test: matching_end_labels -> ok 216s Test: memwr_port_connection -> ok 217s Test: unnamed_block_decl -> ok 217s Test: aes_kexp128 -> ok 217s Test: always01 -> ok 218s Test: always02 -> ok 218s Test: always03 -> ok 218s Test: arraycells -> ok 219s Test: arrays01 -> ok 219s Test: attrib01_module -> ok 219s Test: attrib02_port_decl -> ok 220s Test: attrib03_parameter -> ok 220s Test: attrib04_net_var -> ok 221s Test: attrib06_operator_suffix -> ok 221s Test: attrib08_mod_inst -> ok 222s Test: attrib09_case -> ok 222s Test: carryadd -> ok 222s Test: case_expr_const -> ok 222s Test: case_expr_non_const -> ok 231s Test: case_large -> ok 231s Test: const_branch_finish -> ok 231s Test: const_fold_func -> ok 232s Test: const_func_shadow -> ok 234s Test: constmuldivmod -> ok 234s Test: constpower -> ok 236s Test: dff_different_styles -> ok 236s Test: dff_init -> ok 238s Test: dynslice -> ok 239s Test: fiedler-cooley -> ok 239s Test: forgen01 -> ok 240s Test: forgen02 -> ok 240s Test: forloops -> ok 241s Test: fsm -> ok 241s Test: func_block -> ok 241s Test: func_recurse -> ok 242s Test: func_width_scope -> ok 242s Test: genblk_collide -> ok 242s Test: genblk_dive -> ok 243s Test: genblk_order -> ok 243s Test: genblk_port_shadow -> ok 246s Test: generate -> ok 246s Test: graphtest -> ok 246s Test: hierarchy -> ok 247s Test: hierdefparam -> ok 247s Test: i2c_master_tests -> ok 248s Test: ifdef_1 -> ok 248s Test: ifdef_2 -> ok 248s Test: localparam_attr -> ok 248s Test: loop_prefix_case -> ok 248s Test: loop_var_shadow -> ok 249s Test: loops -> ok 249s Test: macro_arg_surrounding_spaces -> ok 250s Test: macros -> ok 251s Test: mem2reg -> ok 252s Test: mem2reg_bounds_tern -> ok 253s Test: mem_arst -> ok 260s Test: memory -> ok 261s Test: module_scope -> ok 261s Test: module_scope_case -> ok 261s Test: module_scope_func -> ok 262s Test: multiplier -> ok 263s Test: muxtree -> ok 263s Test: named_genblk -> ok 263s Test: nested_genblk_resolve -> ok 263s Test: omsp_dbg_uart -> ok 269s Test: operators -> ok 269s Test: param_attr -> ok 269s Test: paramods -> ok 274s Test: partsel -> ok 275s Test: process -> ok 275s Test: realexpr -> ok 276s Test: repwhile -> ok 276s Test: retime -> ok 281s Test: rotate -> ok 282s Test: scopes -> ok 282s Test: signed_full_slice -> ok 282s Test: signedexpr -> ok 284s Test: sincos -> ok 284s Test: specify -> ok 285s Test: string_format -> ok 285s Test: subbytes -> ok 286s Test: task_func -> ok 287s Test: undef_eqx_nex -> ok 287s Test: usb_phy_tests -> ok 288s Test: values -> ok 288s Test: verilog_primitives -> ok 289s Test: vloghammer -> ok 290s Test: wandwor -> ok 291s Test: wreduce -> ok 291s make[1]: Leaving directory '/tmp/autopkgtest.9XLSHY/build.lOV/src/tests/simple' 291s cd tests/simple_abc9 && bash run-test.sh "" 291s ls: cannot access '*.sv': No such file or directory 291s make[1]: Entering directory '/tmp/autopkgtest.9XLSHY/build.lOV/src/tests/simple_abc9' 293s Test: abc9 -> ok 294s Test: aes_kexp128 -> ok 294s Test: always01 -> ok 294s Test: always02 -> ok 294s Test: always03 -> ok 295s Test: arraycells -> ok 295s Test: arrays01 -> ok 295s Test: attrib01_module -> ok 295s Test: attrib02_port_decl -> ok 296s Test: attrib03_parameter -> ok 296s Test: attrib04_net_var -> ok 296s Test: attrib06_operator_suffix -> ok 297s Test: attrib08_mod_inst -> ok 297s Test: attrib09_case -> ok 297s Test: carryadd -> ok 297s Test: case_expr_const -> ok 297s Test: case_expr_non_const -> ok 314s Test: case_large -> ok 314s Test: const_branch_finish -> ok 314s Test: const_fold_func -> ok 315s Test: const_func_shadow -> ok 317s Test: constmuldivmod -> ok 318s Test: constpower -> ok 318s Test: dff_different_styles -> ok 319s Test: dff_init -> ok 327s Test: dynslice -> ok 327s Test: fiedler-cooley -> ok 328s Test: forgen01 -> ok 328s Test: forgen02 -> ok 328s Test: forloops -> ok 329s Test: fsm -> ok 329s Test: func_block -> ok 329s Test: func_recurse -> ok 329s Test: func_width_scope -> ok 330s Test: genblk_collide -> ok 330s Test: genblk_dive -> ok 330s Test: genblk_order -> ok 330s Test: genblk_port_shadow -> ok 332s Test: generate -> ok 332s Test: graphtest -> ok 333s Test: hierarchy -> ok 333s Test: hierdefparam -> ok 334s Test: i2c_master_tests -> ok 334s Test: ifdef_1 -> ok 334s Test: ifdef_2 -> ok 334s Test: localparam_attr -> ok 334s Test: loop_prefix_case -> ok 335s Test: loop_var_shadow -> ok 335s Test: loops -> ok 335s Test: macro_arg_surrounding_spaces -> ok 336s Test: macros -> ok 337s Test: mem2reg -> ok 337s Test: mem2reg_bounds_tern -> ok 337s Test: mem_arst -> ok 341s Test: memory -> ok 342s Test: module_scope -> ok 342s Test: module_scope_case -> ok 342s Test: module_scope_func -> ok 343s Test: multiplier -> ok 343s Test: muxtree -> ok 343s Test: named_genblk -> ok 344s Test: nested_genblk_resolve -> ok 344s Test: omsp_dbg_uart -> ok 352s Test: operators -> ok 352s Test: param_attr -> ok 353s Test: paramods -> ok 358s Test: partsel -> ok 359s Test: process -> ok 359s Test: realexpr -> ok 360s Test: repwhile -> ok 360s Test: retime -> ok 362s Test: rotate -> ok 362s Test: scopes -> ok 362s Test: signed_full_slice -> ok 363s Test: signedexpr -> ok 366s Test: sincos -> ok 366s Test: string_format -> ok 366s Test: subbytes -> ok 367s Test: task_func -> ok 367s Test: undef_eqx_nex -> ok 367s Test: usb_phy_tests -> ok 368s Test: values -> ok 368s Test: verilog_primitives -> ok 369s Test: vloghammer -> ok 369s Test: wandwor -> ok 371s Test: wreduce -> ok 371s Test: arrays02 -> ok 373s Test: asgn_binop -> ok 373s Test: case_expr_extend -> ok 373s Test: case_expr_query -> ok 374s Test: defvalue -> ok 374s Test: implicit_ports -> ok 374s Test: lesser_size_cast -> ok 374s Test: local_loop_var -> ok 375s Test: macro_arg_spaces -> ok 375s Test: matching_end_labels -> ok 376s Test: memwr_port_connection -> ok 376s Test: unnamed_block_decl -> ok 376s make[1]: Leaving directory '/tmp/autopkgtest.9XLSHY/build.lOV/src/tests/simple_abc9' 376s cd tests/hana && bash run-test.sh "" 376s make[1]: Entering directory '/tmp/autopkgtest.9XLSHY/build.lOV/src/tests/hana' 380s Test: test_intermout -> ok 380s Test: test_parse2synthtrans -> ok 381s Test: test_parser -> ok 382s Test: test_simulation_always -> ok 383s Test: test_simulation_and -> ok 383s Test: test_simulation_buffer -> ok 384s Test: test_simulation_decoder -> ok 385s Test: test_simulation_inc -> ok 386s Test: test_simulation_mux -> ok 387s Test: test_simulation_nand -> ok 387s Test: test_simulation_nor -> ok 388s Test: test_simulation_or -> ok 388s Test: test_simulation_seq -> ok 391s Test: test_simulation_shifter -> ok 392s Test: test_simulation_sop -> ok 393s Test: test_simulation_techmap -> ok 396s Test: test_simulation_techmap_tech -> ok 396s Test: test_simulation_vlib -> ok 396s Test: test_simulation_xnor -> ok 397s Test: test_simulation_xor -> ok 397s make[1]: Leaving directory '/tmp/autopkgtest.9XLSHY/build.lOV/src/tests/hana' 397s cd tests/asicworld && bash run-test.sh "" 397s make[1]: Entering directory '/tmp/autopkgtest.9XLSHY/build.lOV/src/tests/asicworld' 397s Test: code_hdl_models_GrayCounter -> ok 397s Test: code_hdl_models_arbiter -> ok 406s Test: code_hdl_models_cam -> ok 406s Test: code_hdl_models_clk_div -> ok 407s Test: code_hdl_models_clk_div_45 -> ok 407s Test: code_hdl_models_d_ff_gates -> ok 407s Test: code_hdl_models_d_latch_gates -> ok 407s Test: code_hdl_models_decoder_2to4_gates -> ok 408s Test: code_hdl_models_decoder_using_assign -> ok 408s Test: code_hdl_models_decoder_using_case -> ok 408s Test: code_hdl_models_dff_async_reset -> ok 409s Test: code_hdl_models_dff_sync_reset -> ok 409s Test: code_hdl_models_encoder_4to2_gates -> ok 409s Test: code_hdl_models_encoder_using_case -> ok 410s Test: code_hdl_models_encoder_using_if -> ok 410s Test: code_hdl_models_full_adder_gates -> ok 410s Test: code_hdl_models_full_subtracter_gates -> ok 411s Test: code_hdl_models_gray_counter -> ok 411s Test: code_hdl_models_half_adder_gates -> ok 411s Test: code_hdl_models_lfsr -> ok 412s Test: code_hdl_models_lfsr_updown -> ok 412s Test: code_hdl_models_mux_2to1_gates -> ok 412s Test: code_hdl_models_mux_using_assign -> ok 412s Test: code_hdl_models_mux_using_case -> ok 413s Test: code_hdl_models_mux_using_if -> ok 413s Test: code_hdl_models_one_hot_cnt -> ok 413s Test: code_hdl_models_parallel_crc -> ok 414s Test: code_hdl_models_parity_using_assign -> ok 414s Test: code_hdl_models_parity_using_bitwise -> ok 414s Test: code_hdl_models_parity_using_function -> ok 415s Test: code_hdl_models_pri_encoder_using_assign -> ok 415s Test: code_hdl_models_rom_using_case -> ok 415s Test: code_hdl_models_serial_crc -> ok 416s Test: code_hdl_models_tff_async_reset -> ok 416s Test: code_hdl_models_tff_sync_reset -> ok 417s Test: code_hdl_models_uart -> ok 418s Test: code_hdl_models_up_counter -> ok 418s Test: code_hdl_models_up_counter_load -> ok 419s Test: code_hdl_models_up_down_counter -> ok 419s Test: code_specman_switch_fabric -> ok 419s Test: code_tidbits_asyn_reset -> ok 420s Test: code_tidbits_blocking -> ok 420s Test: code_tidbits_fsm_using_always -> ok 420s Test: code_tidbits_fsm_using_function -> ok 421s Test: code_tidbits_fsm_using_single_always -> ok 421s Test: code_tidbits_nonblocking -> ok 421s Test: code_tidbits_reg_combo_example -> ok 422s Test: code_tidbits_reg_seq_example -> ok 422s Test: code_tidbits_syn_reset -> ok 422s Test: code_tidbits_wire_example -> ok 422s Test: code_verilog_tutorial_addbit -> ok 423s Test: code_verilog_tutorial_always_example -> ok 423s Test: code_verilog_tutorial_bus_con -> ok 423s Test: code_verilog_tutorial_comment -> ok 423s Test: code_verilog_tutorial_counter -> ok 424s Test: code_verilog_tutorial_d_ff -> ok 424s Test: code_verilog_tutorial_decoder -> ok 424s Test: code_verilog_tutorial_decoder_always -> ok 424s Test: code_verilog_tutorial_escape_id -> ok 425s Test: code_verilog_tutorial_explicit -> ok 425s Test: code_verilog_tutorial_first_counter -> ok 425s Test: code_verilog_tutorial_flip_flop -> ok 426s Test: code_verilog_tutorial_fsm_full -> ok 426s Test: code_verilog_tutorial_good_code -> ok 426s Test: code_verilog_tutorial_if_else -> ok 426s Test: code_verilog_tutorial_multiply -> ok 427s Test: code_verilog_tutorial_mux_21 -> ok 427s Test: code_verilog_tutorial_n_out_primitive -> ok 427s Test: code_verilog_tutorial_parallel_if -> ok 427s Test: code_verilog_tutorial_parity -> ok 428s Test: code_verilog_tutorial_simple_function -> ok 428s Test: code_verilog_tutorial_simple_if -> ok 428s Test: code_verilog_tutorial_task_global -> ok 428s Test: code_verilog_tutorial_tri_buf -> ok 428s Test: code_verilog_tutorial_v2k_reg -> ok 429s Test: code_verilog_tutorial_which_clock -> ok 429s make[1]: Leaving directory '/tmp/autopkgtest.9XLSHY/build.lOV/src/tests/asicworld' 429s # +cd tests/realmath && bash run-test.sh "" 429s cd tests/share && bash run-test.sh "" 429s generating tests.. 429s running tests.. 432s [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41][42][43][44][45][46][47][48][49][50][51][52][53][54][55][56][57][58][59][60][61][62][63][64][65][66][67][68][69][70][71][72][73][74][75][76][77][78][79][80][81][82][83][84][85][86][87][88][89][90][91][92][93][94][95][96][97][98][99] 432s cd tests/opt_share && bash run-test.sh "" 432s generating tests.. 432s running tests.. 432s make[1]: Entering directory '/tmp/autopkgtest.9XLSHY/build.lOV/src/tests/opt_share' 477s [0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41][42][43][44][45][46][47][48][49][50][51][52][53][54][55][56][57][58][59][60][61][62][63][64][65][66][67][68][69][70][71][72][73][74][75][76][77][78][79][80][81][82][83][84][85][86][87][88][89][90][91][92][93][94][95][96][97][98][99]make[1]: Leaving directory '/tmp/autopkgtest.9XLSHY/build.lOV/src/tests/opt_share' 477s 477s cd tests/fsm && bash run-test.sh "" 477s generating tests.. 477s PRNG seed: 3487291454232357467 477s running tests.. 477s make[1]: Entering directory '/tmp/autopkgtest.9XLSHY/build.lOV/src/tests/fsm' 478s [0]K[1]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 478s Users of state reg look like FSM recoding might result in larger circuit. 478s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 494s K[2]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 494s Users of state reg look like FSM recoding might result in larger circuit. 494s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 497s K[3]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 497s Users of state reg look like FSM recoding might result in larger circuit. 497s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 509s K[4]K[5]K[6]K[7]K[8]K[9]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 509s Users of state reg look like FSM recoding might result in larger circuit. 509s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 516s K[10]K[11]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 516s Users of state reg look like FSM recoding might result in larger circuit. 516s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 522s K[12]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 522s Users of state reg look like FSM recoding might result in larger circuit. 522s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 526s K[13]K[14]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 526s Users of state reg look like FSM recoding might result in larger circuit. 526s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 534s K[15]K[16]K[17]K[18]K[19]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 534s Users of state reg look like FSM recoding might result in larger circuit. 534s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 541s K[20]K[21]K[22]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 541s Users of state reg look like FSM recoding might result in larger circuit. 541s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 541s K[23]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 541s Users of state reg look like FSM recoding might result in larger circuit. 541s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 545s K[24]K[25]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 545s Users of state reg look like FSM recoding might result in larger circuit. 545s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 547s K[26]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 547s Users of state reg look like FSM recoding might result in larger circuit. 547s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 552s K[27]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 552s Users of state reg look like FSM recoding might result in larger circuit. 552s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 552s K[28]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 552s Users of state reg look like FSM recoding might result in larger circuit. 552s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 554s K[29]K[30]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 554s Users of state reg look like FSM recoding might result in larger circuit. 554s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 560s K[31]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 560s Users of state reg look like FSM recoding might result in larger circuit. 560s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 568s K[32]K[33]K[34]K[35]K[36]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 568s Users of state reg look like FSM recoding might result in larger circuit. 568s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 572s K[37]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 572s Users of state reg look like FSM recoding might result in larger circuit. 572s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 574s K[38]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 574s Users of state reg look like FSM recoding might result in larger circuit. 574s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 575s K[39]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 575s Users of state reg look like FSM recoding might result in larger circuit. 575s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 577s K[40]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 577s Users of state reg look like FSM recoding might result in larger circuit. 577s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 581s K[41]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 581s Users of state reg look like FSM recoding might result in larger circuit. 581s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 586s K[42]K[43]K[44]K[45]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 586s Users of state reg look like FSM recoding might result in larger circuit. 586s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 594s K[46]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 594s Users of state reg look like FSM recoding might result in larger circuit. 594s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 602s K[47]K[48]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 602s Users of state reg look like FSM recoding might result in larger circuit. 602s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 602s K[49]Warning: Regarding the user-specified fsm_encoding attribute on gate.state: 602s Users of state reg look like FSM recoding might result in larger circuit. 602s Doesn't look like a proper FSM. Possible simulation-synthesis mismatch! 604s K 604s make[1]: Leaving directory '/tmp/autopkgtest.9XLSHY/build.lOV/src/tests/fsm' 604s cd tests/techmap && bash run-test.sh 604s make[1]: Entering directory '/tmp/autopkgtest.9XLSHY/build.lOV/src/tests/techmap' 605s Passed abc9.ys 605s Warning: wire '\Q' is assigned in a block at < ok 616s Test: firrtl_938 -> ok 617s Test: implicit_en -> ok 619s Test: issue00335 -> ok 621s Test: issue00710 -> ok 621s Test: no_implicit_en -> ok 622s Test: read_arst -> ok 623s Test: read_two_mux -> ok 624s Test: shared_ports -> ok 624s Test: simple_sram_byte_en -> ok 627s Test: trans_addr_enable -> ok 627s Test: trans_sdp -> ok 628s Test: trans_sp -> ok 629s Test: wide_all -> ok 630s Test: wide_read_async -> ok 631s Test: wide_read_mixed -> ok 632s Test: wide_read_sync -> ok 633s Test: wide_read_trans -> ok 633s Test: wide_thru_priority -> ok 634s Test: wide_write -> ok 634s make[1]: Leaving directory '/tmp/autopkgtest.9XLSHY/build.lOV/src/tests/memories' 635s Testing expectations for amber23_sram_byte_en.v .. ok. 635s Testing expectations for implicit_en.v .. ok. 635s Testing expectations for issue00335.v .. ok. 635s Testing expectations for issue00710.v .. ok. 635s Testing expectations for no_implicit_en.v .. ok. 635s Testing expectations for read_arst.v .. ok. 635s Testing expectations for read_two_mux.v .. ok. 635s Testing expectations for shared_ports.v .. ok. 635s Testing expectations for simple_sram_byte_en.v .. ok. 635s Testing expectations for trans_addr_enable.v .. ok. 635s Testing expectations for trans_sdp.v .. ok. 635s Testing expectations for trans_sp.v .. ok. 635s Testing expectations for wide_all.v .. ok. 635s Testing expectations for wide_read_async.v .. ok. 635s Testing expectations for wide_read_mixed.v .. ok. 635s Testing expectations for wide_read_sync.v .. ok. 636s Testing expectations for wide_read_trans.v .. ok. 636s Testing expectations for wide_thru_priority.v .. ok. 636s Testing expectations for wide_write.v .. ok. 636s cd tests/memlib && bash run-test.sh "" 636s make[1]: Entering directory '/tmp/autopkgtest.9XLSHY/build.lOV/src/tests/memlib' 637s Test: t_async_big -> ok 640s Test: t_async_big_block -> ok 640s Test: t_async_small -> ok 641s Test: t_async_small_block -> ok 641s Test: t_sync_big -> ok 641s Test: t_sync_big_sdp -> ok 642s Test: t_sync_big_lut -> ok 643s Test: t_sync_small -> ok 643s Test: t_sync_small_block -> ok 643s Test: t_sync_small_block_attr -> ok 643s Test: t_init_lut_zeros_zero -> ok 643s Test: t_init_lut_zeros_any -> ok 643s Test: t_init_lut_val_zero -> ok 644s Test: t_init_lut_val_any -> ok 644s Test: t_init_lut_val_no_undef -> ok 644s Test: t_init_lut_val2_any -> ok 644s Test: t_init_lut_val2_no_undef -> ok 644s Test: t_init_lut_x_none -> ok 644s Test: t_init_lut_x_zero -> ok 645s Test: t_init_lut_x_any -> ok 645s Test: t_init_lut_x_no_undef -> ok 645s Test: t_ram_18b2B -> ok 645s Test: t_ram_9b1B -> ok 645s Test: t_ram_4b1B -> ok 645s Test: t_ram_2b1B -> ok 646s Test: t_ram_1b1B -> ok 646s Test: t_init_9b1B_zeros_zero -> ok 646s Test: t_init_9b1B_zeros_any -> ok 646s Test: t_init_9b1B_val_zero -> ok 646s Test: t_init_9b1B_val_any -> ok 646s Test: t_init_9b1B_val_no_undef -> ok 647s Test: t_init_13b2B_val_any -> ok 647s Test: t_init_18b2B_val_any -> ok 647s Test: t_init_18b2B_val_no_undef -> ok 647s Test: t_init_4b1B_x_none -> ok 647s Test: t_init_4b1B_x_zero -> ok 647s Test: t_init_4b1B_x_any -> ok 648s Test: t_init_4b1B_x_no_undef -> ok 648s Test: t_clock_a4_wANYrANYsFalse -> ok 648s Test: t_clock_a4_wANYrNEGsFalse -> ok 648s Test: t_clock_a4_wANYrPOSsFalse -> ok 648s Test: t_clock_a4_wNEGrANYsFalse -> ok 648s Test: t_clock_a4_wNEGrPOSsFalse -> ok 648s Test: t_clock_a4_wNEGrNEGsFalse -> ok 649s Test: t_clock_a4_wPOSrANYsFalse -> ok 649s Test: t_clock_a4_wPOSrNEGsFalse -> ok 649s Test: t_clock_a4_wPOSrPOSsFalse -> ok 649s Test: t_clock_a4_wANYrANYsTrue -> ok 649s Test: t_clock_a4_wNEGrPOSsTrue -> ok 649s Test: t_clock_a4_wNEGrNEGsTrue -> ok 650s Test: t_clock_a4_wPOSrNEGsTrue -> ok 650s Test: t_clock_a4_wPOSrPOSsTrue -> ok 650s Test: t_unmixed -> ok 650s Test: t_mixed_9_18 -> ok 650s Test: t_mixed_18_9 -> ok 650s Test: t_mixed_36_9 -> ok 651s Test: t_mixed_4_2 -> ok 651s Test: t_tdp -> ok 651s Test: t_sync_2clk -> ok 651s Test: t_sync_shared -> ok 651s Test: t_sync_2clk_shared -> ok 651s Test: t_sync_trans_old_old -> ok 652s Test: t_sync_trans_old_new -> ok 652s Test: t_sync_trans_old_none -> ok 652s Test: t_sync_trans_new_old -> ok 652s Test: t_sync_trans_new_new -> ok 652s Test: t_sync_trans_new_none -> ok 652s Test: t_sp_nc_none -> ok 653s Test: t_sp_new_none -> ok 653s Test: t_sp_old_none -> ok 653s Test: t_sp_nc_nc -> ok 653s Test: t_sp_new_nc -> ok 653s Test: t_sp_old_nc -> ok 653s Test: t_sp_nc_new -> ok 653s Test: t_sp_new_new -> ok 654s Test: t_sp_old_new -> ok 654s Test: t_sp_nc_old -> ok 654s Test: t_sp_new_old -> ok 654s Test: t_sp_old_old -> ok 654s Test: t_sp_nc_new_only -> ok 654s Test: t_sp_new_new_only -> ok 654s Test: t_sp_old_new_only -> ok 655s Test: t_sp_nc_new_only_be -> ok 655s Test: t_sp_new_new_only_be -> ok 655s Test: t_sp_old_new_only_be -> ok 655s Test: t_sp_nc_new_be -> ok 655s Test: t_sp_new_new_be -> ok 655s Test: t_sp_old_new_be -> ok 656s Test: t_sp_nc_old_be -> ok 656s Test: t_sp_new_old_be -> ok 656s Test: t_sp_old_old_be -> ok 656s Test: t_sp_nc_nc_be -> ok 656s Test: t_sp_new_nc_be -> ok 656s Test: t_sp_old_nc_be -> ok 657s Test: t_sp_nc_auto -> ok 657s Test: t_sp_new_auto -> ok 657s Test: t_sp_old_auto -> ok 657s Test: t_sp_nc_auto_be -> ok 657s Test: t_sp_new_auto_be -> ok 657s Test: t_sp_old_auto_be -> ok 658s Test: t_sp_init_x_x -> ok 658s Test: t_sp_init_x_x_re -> ok 658s Test: t_sp_init_x_x_ce -> ok 658s Test: t_sp_init_0_x -> ok 658s Test: t_sp_init_0_x_re -> ok 658s Test: t_sp_init_0_0 -> ok 658s Test: t_sp_init_0_0_re -> ok 659s Test: t_sp_init_0_any -> ok 659s Test: t_sp_init_0_any_re -> ok 659s Test: t_sp_init_v_x -> ok 659s Test: t_sp_init_v_x_re -> ok 659s Test: t_sp_init_v_0 -> ok 659s Test: t_sp_init_v_0_re -> ok 660s Test: t_sp_init_v_any -> ok 660s Test: t_sp_init_v_any_re -> ok 660s Test: t_sp_arst_x_x -> ok 660s Test: t_sp_arst_x_x_re -> ok 660s Test: t_sp_arst_0_x -> ok 660s Test: t_sp_arst_0_x_re -> ok 660s Test: t_sp_arst_0_0 -> ok 661s Test: t_sp_arst_0_0_re -> ok 661s Test: t_sp_arst_0_any -> ok 661s Test: t_sp_arst_0_any_re -> ok 661s Test: t_sp_arst_0_init -> ok 661s Test: t_sp_arst_0_init_re -> ok 661s Test: t_sp_arst_v_x -> ok 662s Test: t_sp_arst_v_x_re -> ok 662s Test: t_sp_arst_v_0 -> ok 662s Test: t_sp_arst_v_0_re -> ok 662s Test: t_sp_arst_v_any -> ok 662s Test: t_sp_arst_v_any_re -> ok 662s Test: t_sp_arst_v_init -> ok 662s Test: t_sp_arst_v_init_re -> ok 663s Test: t_sp_arst_e_x -> ok 663s Test: t_sp_arst_e_x_re -> ok 663s Test: t_sp_arst_e_0 -> ok 663s Test: t_sp_arst_e_0_re -> ok 663s Test: t_sp_arst_e_any -> ok 663s Test: t_sp_arst_e_any_re -> ok 664s Test: t_sp_arst_e_init -> ok 664s Test: t_sp_arst_e_init_re -> ok 664s Test: t_sp_arst_n_x -> ok 664s Test: t_sp_arst_n_x_re -> ok 664s Test: t_sp_arst_n_0 -> ok 664s Test: t_sp_arst_n_0_re -> ok 664s Test: t_sp_arst_n_any -> ok 665s Test: t_sp_arst_n_any_re -> ok 665s Test: t_sp_arst_n_init -> ok 666s Test: t_sp_arst_n_init_re -> ok 666s Test: t_sp_srst_x_x -> ok 666s Test: t_sp_srst_x_x_re -> ok 666s Test: t_sp_srst_0_x -> ok 666s Test: t_sp_srst_0_x_re -> ok 666s Test: t_sp_srst_0_0 -> ok 666s Test: t_sp_srst_0_0_re -> ok 666s Test: t_sp_srst_0_any -> ok 666s Test: t_sp_srst_0_any_re -> ok 666s Test: t_sp_srst_0_init -> ok 667s Test: t_sp_srst_0_init_re -> ok 667s Test: t_sp_srst_v_x -> ok 667s Test: t_sp_srst_v_x_re -> ok 667s Test: t_sp_srst_v_0 -> ok 667s Test: t_sp_srst_v_0_re -> ok 667s Test: t_sp_srst_v_any -> ok 668s Test: t_sp_srst_v_any_re -> ok 668s Test: t_sp_srst_v_any_re_gated -> ok 668s Test: t_sp_srst_v_any_ce -> ok 668s Test: t_sp_srst_v_any_ce_gated -> ok 668s Test: t_sp_srst_v_init -> ok 668s Test: t_sp_srst_v_init_re -> ok 668s Test: t_sp_srst_e_x -> ok 669s Test: t_sp_srst_e_x_re -> ok 669s Test: t_sp_srst_e_0 -> ok 669s Test: t_sp_srst_e_0_re -> ok 669s Test: t_sp_srst_e_any -> ok 669s Test: t_sp_srst_e_any_re -> ok 669s Test: t_sp_srst_e_init -> ok 670s Test: t_sp_srst_e_init_re -> ok 670s Test: t_sp_srst_n_x -> ok 670s Test: t_sp_srst_n_x_re -> ok 670s Test: t_sp_srst_n_0 -> ok 670s Test: t_sp_srst_n_0_re -> ok 670s Test: t_sp_srst_n_any -> ok 671s Test: t_sp_srst_n_any_re -> ok 671s Test: t_sp_srst_n_init -> ok 671s Test: t_sp_srst_n_init_re -> ok 671s Test: t_sp_srst_gv_x -> ok 671s Test: t_sp_srst_gv_x_re -> ok 671s Test: t_sp_srst_gv_0 -> ok 672s Test: t_sp_srst_gv_0_re -> ok 672s Test: t_sp_srst_gv_any -> ok 672s Test: t_sp_srst_gv_any_re -> ok 672s Test: t_sp_srst_gv_any_re_gated -> ok 672s Test: t_sp_srst_gv_any_ce -> ok 672s Test: t_sp_srst_gv_any_ce_gated -> ok 673s Test: t_sp_srst_gv_init -> ok 673s Test: t_sp_srst_gv_init_re -> ok 673s Test: t_wren_a4d4_NO_BYTE -> ok 673s Test: t_wren_a5d4_NO_BYTE -> ok 673s Test: t_wren_a6d4_NO_BYTE -> ok 673s Test: t_wren_a3d8_NO_BYTE -> ok 673s Test: t_wren_a4d8_NO_BYTE -> ok 674s Test: t_wren_a4d4_W4_B4 -> ok 674s Test: t_wren_a4d8_W4_B4_separate -> ok 674s Test: t_wren_a4d8_W8_B4 -> ok 674s Test: t_wren_a4d8_W8_B4_separate -> ok 674s Test: t_wren_a4d8_W8_B8 -> ok 674s Test: t_wren_a4d8_W8_B8_separate -> ok 674s Test: t_wren_a4d2w8_W16_B4 -> ok 675s Test: t_wren_a4d2w8_W16_B4_separate -> ok 675s Test: t_wren_a4d4w4_W16_B4 -> ok 675s Test: t_wren_a4d4w4_W16_B4_separate -> ok 675s Test: t_wren_a5d4w2_W16_B4 -> ok 675s Test: t_wren_a5d4w2_W16_B4_separate -> ok 676s Test: t_wren_a5d4w4_W16_B4 -> ok 676s Test: t_wren_a5d4w4_W16_B4_separate -> ok 676s Test: t_wren_a4d8w2_W16_B4 -> ok 676s Test: t_wren_a4d8w2_W16_B4_separate -> ok 676s Test: t_wren_a5d8w1_W16_B4 -> ok 676s Test: t_wren_a5d8w1_W16_B4_separate -> ok 676s Test: t_wren_a5d8w2_W16_B4 -> ok 677s Test: t_wren_a5d8w2_W16_B4_separate -> ok 677s Test: t_wren_a4d16w1_W16_B4 -> ok 677s Test: t_wren_a4d16w1_W16_B4_separate -> ok 677s Test: t_wren_a4d4w2_W8_B8 -> ok 677s Test: t_wren_a4d4w2_W8_B8_separate -> ok 677s Test: t_wren_a4d4w1_W8_B8 -> ok 678s Test: t_wren_a4d4w1_W8_B8_separate -> ok 678s Test: t_wren_a4d8w2_W8_B8 -> ok 678s Test: t_wren_a4d8w2_W8_B8_separate -> ok 678s Test: t_wren_a3d8w2_W8_B8 -> ok 678s Test: t_wren_a3d8w2_W8_B8_separate -> ok 678s Test: t_wren_a4d4w2_W8_B4 -> ok 679s Test: t_wren_a4d4w2_W8_B4_separate -> ok 679s Test: t_wren_a4d2w4_W8_B4 -> ok 679s Test: t_wren_a4d2w4_W8_B4_separate -> ok 679s Test: t_wren_a4d4w4_W8_B4 -> ok 679s Test: t_wren_a4d4w4_W8_B4_separate -> ok 679s Test: t_wren_a4d4w4_W4_B4 -> ok 680s Test: t_wren_a4d4w4_W4_B4_separate -> ok 680s Test: t_wren_a4d4w5_W4_B4 -> ok 680s Test: t_wren_a4d4w5_W4_B4_separate -> ok 680s Test: t_geom_a4d64_wren -> ok 680s Test: t_geom_a5d32_wren -> ok 680s Test: t_geom_a5d64_wren -> ok 681s Test: t_geom_a6d16_wren -> ok 681s Test: t_geom_a6d30_wren -> ok 681s Test: t_geom_a6d64_wren -> ok 681s Test: t_geom_a7d4_wren -> ok 681s Test: t_geom_a7d6_wren -> ok 681s Test: t_geom_a7d8_wren -> ok 682s Test: t_geom_a7d17_wren -> ok 682s Test: t_geom_a8d4_wren -> ok 682s Test: t_geom_a8d6_wren -> ok 682s Test: t_geom_a9d4_wren -> ok 682s Test: t_geom_a9d8_wren -> ok 682s Test: t_geom_a9d5_wren -> ok 683s Test: t_geom_a9d6_wren -> ok 683s Test: t_geom_a3d18_9b1B -> ok 683s Test: t_geom_a4d4_9b1B -> ok 683s Test: t_geom_a4d18_9b1B -> ok 683s Test: t_geom_a5d32_9b1B -> ok 683s Test: t_geom_a6d4_9b1B -> ok 684s Test: t_geom_a7d11_9b1B -> ok 684s Test: t_geom_a7d18_9b1B -> ok 684s Test: t_geom_a11d1_9b1B -> ok 684s Test: t_wide_sdp_a6r1w1b1x1 -> ok 684s Test: t_wide_sdp_a7r1w1b1x1 -> ok 684s Test: t_wide_sdp_a8r1w1b1x1 -> ok 685s Test: t_wide_sdp_a6r0w0b0x0 -> ok 685s Test: t_wide_sdp_a6r1w0b0x0 -> ok 685s Test: t_wide_sdp_a6r2w0b0x0 -> ok 685s Test: t_wide_sdp_a6r3w0b0x0 -> ok 685s Test: t_wide_sdp_a6r4w0b0x0 -> ok 686s Test: t_wide_sdp_a6r5w0b0x0 -> ok 686s Test: t_wide_sdp_a6r0w1b0x0 -> ok 686s Test: t_wide_sdp_a6r0w1b1x0 -> ok 686s Test: t_wide_sdp_a6r0w2b0x0 -> ok 686s Test: t_wide_sdp_a6r0w2b2x0 -> ok 687s Test: t_wide_sdp_a6r0w3b2x0 -> ok 687s Test: t_wide_sdp_a6r0w4b2x0 -> ok 687s Test: t_wide_sdp_a6r0w5b2x0 -> ok 687s Test: t_wide_sdp_a7r0w0b0x0 -> ok 687s Test: t_wide_sdp_a7r1w0b0x0 -> ok 688s Test: t_wide_sdp_a7r2w0b0x0 -> ok 688s Test: t_wide_sdp_a7r3w0b0x0 -> ok 688s Test: t_wide_sdp_a7r4w0b0x0 -> ok 688s Test: t_wide_sdp_a7r5w0b0x0 -> ok 688s Test: t_wide_sdp_a7r0w1b0x0 -> ok 689s Test: t_wide_sdp_a7r0w1b1x0 -> ok 689s Test: t_wide_sdp_a7r0w2b0x0 -> ok 689s Test: t_wide_sdp_a7r0w2b2x0 -> ok 689s Test: t_wide_sdp_a7r0w3b2x0 -> ok 689s Test: t_wide_sdp_a7r0w4b2x0 -> ok 690s Test: t_wide_sdp_a7r0w5b2x0 -> ok 690s Test: t_wide_sp_mix_a6r1w1b1 -> ok 690s Test: t_wide_sp_mix_a7r1w1b1 -> ok 690s Test: t_wide_sp_mix_a8r1w1b1 -> ok 691s Test: t_wide_sp_mix_a6r0w0b0 -> ok 691s Test: t_wide_sp_mix_a6r1w0b0 -> ok 691s Test: t_wide_sp_mix_a6r2w0b0 -> ok 691s Test: t_wide_sp_mix_a6r3w0b0 -> ok 691s Test: t_wide_sp_mix_a6r4w0b0 -> ok 691s Test: t_wide_sp_mix_a6r5w0b0 -> ok 692s Test: t_wide_sp_mix_a6r0w1b0 -> ok 692s Test: t_wide_sp_mix_a6r0w1b1 -> ok 692s Test: t_wide_sp_mix_a6r0w2b0 -> ok 692s Test: t_wide_sp_mix_a6r0w2b2 -> ok 692s Test: t_wide_sp_mix_a6r0w3b2 -> ok 693s Test: t_wide_sp_mix_a6r0w4b2 -> ok 693s Test: t_wide_sp_mix_a6r0w5b2 -> ok 693s Test: t_wide_sp_mix_a7r0w0b0 -> ok 693s Test: t_wide_sp_mix_a7r1w0b0 -> ok 693s Test: t_wide_sp_mix_a7r2w0b0 -> ok 694s Test: t_wide_sp_mix_a7r3w0b0 -> ok 694s Test: t_wide_sp_mix_a7r4w0b0 -> ok 694s Test: t_wide_sp_mix_a7r5w0b0 -> ok 694s Test: t_wide_sp_mix_a7r0w1b0 -> ok 694s Test: t_wide_sp_mix_a7r0w1b1 -> ok 695s Test: t_wide_sp_mix_a7r0w2b0 -> ok 695s Test: t_wide_sp_mix_a7r0w2b2 -> ok 695s Test: t_wide_sp_mix_a7r0w3b2 -> ok 695s Test: t_wide_sp_mix_a7r0w4b2 -> ok 695s Test: t_wide_sp_mix_a7r0w5b2 -> ok 696s Test: t_wide_sp_tied_a6r1w1b1 -> ok 696s Test: t_wide_sp_tied_a7r1w1b1 -> ok 696s Test: t_wide_sp_tied_a8r1w1b1 -> ok 696s Test: t_wide_sp_tied_a6r0w0b0 -> ok 696s Test: t_wide_sp_tied_a6r1w0b0 -> ok 696s Test: t_wide_sp_tied_a6r2w0b0 -> ok 697s Test: t_wide_sp_tied_a6r3w0b0 -> ok 697s Test: t_wide_sp_tied_a6r4w0b0 -> ok 697s Test: t_wide_sp_tied_a6r5w0b0 -> ok 697s Test: t_wide_sp_tied_a6r0w1b0 -> ok 697s Test: t_wide_sp_tied_a6r0w1b1 -> ok 698s Test: t_wide_sp_tied_a6r0w2b0 -> ok 698s Test: t_wide_sp_tied_a6r0w2b2 -> ok 698s Test: t_wide_sp_tied_a6r0w3b2 -> ok 698s Test: t_wide_sp_tied_a6r0w4b2 -> ok 699s Test: t_wide_sp_tied_a6r0w5b2 -> ok 699s Test: t_wide_sp_tied_a7r0w0b0 -> ok 699s Test: t_wide_sp_tied_a7r1w0b0 -> ok 699s Test: t_wide_sp_tied_a7r2w0b0 -> ok 699s Test: t_wide_sp_tied_a7r3w0b0 -> ok 699s Test: t_wide_sp_tied_a7r4w0b0 -> ok 700s Test: t_wide_sp_tied_a7r5w0b0 -> ok 700s Test: t_wide_sp_tied_a7r0w1b0 -> ok 700s Test: t_wide_sp_tied_a7r0w1b1 -> ok 700s Test: t_wide_sp_tied_a7r0w2b0 -> ok 700s Test: t_wide_sp_tied_a7r0w2b2 -> ok 701s Test: t_wide_sp_tied_a7r0w3b2 -> ok 701s Test: t_wide_sp_tied_a7r0w4b2 -> ok 701s Test: t_wide_sp_tied_a7r0w5b2 -> ok 701s Test: t_wide_read_a6r1w1b1 -> ok 702s Test: t_wide_write_a6r1w1b1 -> ok 702s Test: t_wide_read_a7r1w1b1 -> ok 702s Test: t_wide_write_a7r1w1b1 -> ok 702s Test: t_wide_read_a8r1w1b1 -> ok 702s Test: t_wide_write_a8r1w1b1 -> ok 702s Test: t_wide_read_a6r0w0b0 -> ok 702s Test: t_wide_write_a6r0w0b0 -> ok 703s Test: t_wide_read_a6r1w0b0 -> ok 703s Test: t_wide_write_a6r1w0b0 -> ok 703s Test: t_wide_read_a6r2w0b0 -> ok 703s Test: t_wide_write_a6r2w0b0 -> ok 703s Test: t_wide_read_a6r3w0b0 -> ok 703s Test: t_wide_write_a6r3w0b0 -> ok 704s Test: t_wide_read_a6r4w0b0 -> ok 704s Test: t_wide_write_a6r4w0b0 -> ok 704s Test: t_wide_read_a6r5w0b0 -> ok 704s Test: t_wide_write_a6r5w0b0 -> ok 705s Test: t_wide_read_a6r0w1b0 -> ok 705s Test: t_wide_write_a6r0w1b0 -> ok 705s Test: t_wide_read_a6r0w1b1 -> ok 705s Test: t_wide_write_a6r0w1b1 -> ok 705s Test: t_wide_read_a6r0w2b0 -> ok 705s Test: t_wide_write_a6r0w2b0 -> ok 706s Test: t_wide_read_a6r0w2b2 -> ok 706s Test: t_wide_write_a6r0w2b2 -> ok 706s Test: t_wide_read_a6r0w3b2 -> ok 706s Test: t_wide_write_a6r0w3b2 -> ok 706s Test: t_wide_read_a6r0w4b2 -> ok 707s Test: t_wide_write_a6r0w4b2 -> ok 707s Test: t_wide_read_a6r0w5b2 -> ok 707s Test: t_wide_write_a6r0w5b2 -> ok 707s Test: t_wide_read_a7r0w0b0 -> ok 708s Test: t_wide_write_a7r0w0b0 -> ok 708s Test: t_wide_read_a7r1w0b0 -> ok 708s Test: t_wide_write_a7r1w0b0 -> ok 708s Test: t_wide_read_a7r2w0b0 -> ok 708s Test: t_wide_write_a7r2w0b0 -> ok 708s Test: t_wide_read_a7r3w0b0 -> ok 709s Test: t_wide_write_a7r3w0b0 -> ok 709s Test: t_wide_read_a7r4w0b0 -> ok 709s Test: t_wide_write_a7r4w0b0 -> ok 710s Test: t_wide_read_a7r5w0b0 -> ok 710s Test: t_wide_write_a7r5w0b0 -> ok 710s Test: t_wide_read_a7r0w1b0 -> ok 710s Test: t_wide_write_a7r0w1b0 -> ok 710s Test: t_wide_read_a7r0w1b1 -> ok 710s Test: t_wide_write_a7r0w1b1 -> ok 710s Test: t_wide_read_a7r0w2b0 -> ok 711s Test: t_wide_write_a7r0w2b0 -> ok 711s Test: t_wide_read_a7r0w2b2 -> ok 711s Test: t_wide_write_a7r0w2b2 -> ok 711s Test: t_wide_read_a7r0w3b2 -> ok 711s Test: t_wide_write_a7r0w3b2 -> ok 711s Test: t_wide_read_a7r0w4b2 -> ok 712s Test: t_wide_write_a7r0w4b2 -> ok 712s Test: t_wide_read_a7r0w5b2 -> ok 712s Test: t_wide_write_a7r0w5b2 -> ok 713s Test: t_quad_port_a2d2 -> ok 713s Test: t_quad_port_a4d2 -> ok 713s Test: t_quad_port_a5d2 -> ok 713s Test: t_quad_port_a4d4 -> ok 713s Test: t_quad_port_a6d2 -> ok 713s Test: t_quad_port_a4d8 -> ok 714s Test: t_wide_quad_a4w2r1 -> ok 714s Test: t_wide_oct_a4w2r1 -> ok 714s Test: t_wide_quad_a4w2r2 -> ok 714s Test: t_wide_oct_a4w2r2 -> ok 714s Test: t_wide_quad_a4w2r3 -> ok 714s Test: t_wide_oct_a4w2r3 -> ok 714s Test: t_wide_quad_a4w2r4 -> ok 715s Test: t_wide_oct_a4w2r4 -> ok 715s Test: t_wide_quad_a4w2r5 -> ok 715s Test: t_wide_oct_a4w2r5 -> ok 715s Test: t_wide_quad_a4w2r6 -> ok 715s Test: t_wide_oct_a4w2r6 -> ok 715s Test: t_wide_quad_a4w2r7 -> ok 716s Test: t_wide_oct_a4w2r7 -> ok 716s Test: t_wide_quad_a4w2r8 -> ok 716s Test: t_wide_oct_a4w2r8 -> ok 716s Test: t_wide_quad_a4w2r9 -> ok 716s Test: t_wide_oct_a4w2r9 -> ok 716s Test: t_wide_quad_a4w4r1 -> ok 717s Test: t_wide_oct_a4w4r1 -> ok 717s Test: t_wide_quad_a4w4r4 -> ok 717s Test: t_wide_oct_a4w4r4 -> ok 717s Test: t_wide_quad_a4w4r6 -> ok 717s Test: t_wide_oct_a4w4r6 -> ok 717s Test: t_wide_quad_a4w4r9 -> ok 718s Test: t_wide_oct_a4w4r9 -> ok 718s Test: t_wide_quad_a5w2r1 -> ok 718s Test: t_wide_oct_a5w2r1 -> ok 718s Test: t_wide_quad_a5w2r4 -> ok 718s Test: t_wide_oct_a5w2r4 -> ok 718s Test: t_wide_quad_a5w2r9 -> ok 719s Test: t_wide_oct_a5w2r9 -> ok 719s Test: t_no_reset -> ok 719s Test: t_gclken -> ok 719s Test: t_ungated -> ok 719s Test: t_gclken_ce -> ok 719s Test: t_grden -> ok 720s Test: t_grden_ce -> ok 720s Test: t_exclwr -> ok 720s Test: t_excl_rst -> ok 720s Test: t_transwr -> ok 720s Test: t_trans_rst -> ok 721s Test: t_wr_byte -> ok 721s Test: t_trans_byte -> ok 721s Test: t_wr_rst_byte -> ok 721s Test: t_rst_wr_byte -> ok 721s Test: t_rdenrst_wr_byte -> ok 721s make[1]: Leaving directory '/tmp/autopkgtest.9XLSHY/build.lOV/src/tests/memlib' 721s cd tests/bram && bash run-test.sh "" 721s generating tests.. 721s PRNG seed: 951932 721s running tests.. 721s make[1]: Entering directory '/tmp/autopkgtest.9XLSHY/build.lOV/src/tests/bram' 722s Passed memory_bram test 00_01. 723s Passed memory_bram test 00_02. 724s Passed memory_bram test 00_03. 725s Passed memory_bram test 00_04. 726s Passed memory_bram test 01_00. 727s Passed memory_bram test 01_02. 728s Passed memory_bram test 01_03. 730s Passed memory_bram test 01_04. 730s Passed memory_bram test 02_00. 731s Passed memory_bram test 02_01. 731s Passed memory_bram test 02_03. 732s Passed memory_bram test 02_04. 732s Passed memory_bram test 03_00. 733s Passed memory_bram test 03_01. 735s Passed memory_bram test 03_02. 736s Passed memory_bram test 03_04. 736s Passed memory_bram test 04_00. 737s Passed memory_bram test 04_01. 737s Passed memory_bram test 04_02. 738s Passed memory_bram test 04_03. 738s make[1]: Leaving directory '/tmp/autopkgtest.9XLSHY/build.lOV/src/tests/bram' 738s cd tests/various && bash run-test.sh 738s make[1]: Entering directory '/tmp/autopkgtest.9XLSHY/build.lOV/src/tests/various' 738s Warning: Wire abc9_test027.$abc$91$o is used but has no driver. 739s Passed abc9.ys 739s Passed aiger_dff.ys 739s Passed attrib05_port_conn.ys 739s Passed attrib07_func_call.ys 739s Passed autoname.ys 739s Passed blackbox_wb.ys 739s Passed bug1496.ys 739s Passed bug1531.ys 739s Passed bug1614.ys 739s Passed bug1710.ys 739s Passed bug1745.ys 739s Warning: Yosys has only limited support for tri-state logic at the moment. (< svinterface1_tb.v:50: $finish called at 420000 (10ps) 801s svinterface1_tb.v:50: $finish called at 420000 (10ps) 801s ok 801s Test: svinterface_at_top -> svinterface_at_top_tb.v:61: $finish called at 420000 (10ps) 801s svinterface_at_top_tb_wrapper.v:61: $finish called at 420000 (10ps) 801s ERROR! 801s Test: load_and_derive ->ok 801s Test: resolve_types ->ok 801s cd tests/svtypes && bash run-test.sh "" 801s make[1]: Entering directory '/tmp/autopkgtest.9XLSHY/build.lOV/src/tests/svtypes' 801s Passed enum_simple.ys 802s Passed logic_rom.ys 802s < ok 815s Test ../../techlibs/anlogic/cells_sim.v -> ok 815s Test ../../techlibs/coolrunner2/cells_sim.v -> ok 815s Test ../../techlibs/ecp5/cells_sim.v -> ok 815s Test ../../techlibs/efinix/cells_sim.v -> ok 815s Test ../../techlibs/gatemate/cells_sim.v -> ok 815s Test ../../techlibs/gowin/cells_sim.v -> ok 815s Test ../../techlibs/greenpak4/cells_sim.v -> ok 815s Test ../../techlibs/ice40/cells_sim.v -DICE40_HX ->../../techlibs/ice40/cells_sim.v:2231: warning: Choosing typ expression. 815s ../../techlibs/ice40/cells_sim.v:2231: warning: Choosing typ expression. 815s ../../techlibs/ice40/cells_sim.v:2233: warning: Choosing typ expression. 815s ../../techlibs/ice40/cells_sim.v:2233: warning: Choosing typ expression. 815s ../../techlibs/ice40/cells_sim.v:2235: warning: Choosing typ expression. 815s ../../techlibs/ice40/cells_sim.v:2235: warning: Choosing typ expression. 815s ../../techlibs/ice40/cells_sim.v:2237: warning: Choosing typ expression. 815s ../../techlibs/ice40/cells_sim.v:2237: warning: Choosing typ expression. 815s ../../techlibs/ice40/cells_sim.v:2239: warning: Choosing typ expression. 815s ../../techlibs/ice40/cells_sim.v:2239: warning: Choosing typ expression. 815s ok 815s Test ../../techlibs/ice40/cells_sim.v -DICE40_LP ->../../techlibs/ice40/cells_sim.v:2295: warning: Choosing typ expression. 815s ../../techlibs/ice40/cells_sim.v:2295: warning: Choosing typ expression. 815s ../../techlibs/ice40/cells_sim.v:2297: warning: Choosing typ expression. 815s ../../techlibs/ice40/cells_sim.v:2297: warning: Choosing typ expression. 815s ../../techlibs/ice40/cells_sim.v:2299: warning: Choosing typ expression. 815s ../../techlibs/ice40/cells_sim.v:2299: warning: Choosing typ expression. 815s ../../techlibs/ice40/cells_sim.v:2301: warning: Choosing typ expression. 815s ../../techlibs/ice40/cells_sim.v:2301: warning: Choosing typ expression. 815s ../../techlibs/ice40/cells_sim.v:2303: warning: Choosing typ expression. 815s ../../techlibs/ice40/cells_sim.v:2303: warning: Choosing typ expression. 815s ok 815s Test ../../techlibs/ice40/cells_sim.v -DICE40_U -> ok 815s ../../techlibs/ice40/cells_sim.v:2359: warning: Choosing typ expression. 815s ../../techlibs/ice40/cells_sim.v:2359: warning: Choosing typ expression. 815s ../../techlibs/ice40/cells_sim.v:2361: warning: Choosing typ expression. 815s ../../techlibs/ice40/cells_sim.v:2361: warning: Choosing typ expression. 815s ../../techlibs/ice40/cells_sim.v:2363: warning: Choosing typ expression. 815s ../../techlibs/ice40/cells_sim.v:2363: warning: Choosing typ expression. 815s ../../techlibs/ice40/cells_sim.v:2365: warning: Choosing typ expression. 815s ../../techlibs/ice40/cells_sim.v:2365: warning: Choosing typ expression. 815s ../../techlibs/ice40/cells_sim.v:2367: warning: Choosing typ expression. 815s ../../techlibs/ice40/cells_sim.v:2367: warning: Choosing typ expression. 815s Test ../../techlibs/intel/cycloneiv/cells_sim.v -> ok 815s Test ../../techlibs/intel/cycloneive/cells_sim.v -> ok 815s Test ../../techlibs/intel/cyclone10lp/cells_sim.v -> ok 815s Test ../../techlibs/intel/max10/cells_sim.v -> ok 815s Test ../../techlibs/intel_alm/cyclonev/cells_sim.v -> ok 815s Test ../../techlibs/nexus/cells_sim.v -> ok 815s Test ../../techlibs/quicklogic/cells_sim.v -> ok 815s Test ../../techlibs/sf2/cells_sim.v -> ok 815s Test ../../techlibs/xilinx/cells_sim.v -> ok 815s Test ../../techlibs/common/simcells.v -> ok 815s Test ../../techlibs/common/simlib.v -> ok 815s cd tests/arch/ice40 && bash run-test.sh "" 815s make[1]: Entering directory '/tmp/autopkgtest.9XLSHY/build.lOV/src/tests/arch/ice40' 816s Passed add_sub.ys 820s Passed adffs.ys 820s Warning: Resizing cell port SSCounter6o.l0.I3 from 32 bits to 1 bits. 820s Warning: Resizing cell port SSCounter6o.c0.CI from 32 bits to 1 bits. 820s Warning: Resizing cell port SSCounter6o.lien.I0 from 32 bits to 1 bits. 820s Warning: Resizing cell port SSCounter6o.lien.I1 from 32 bits to 1 bits. 820s Passed bug1597.ys 821s Passed bug1598.ys 822s Passed bug1626.ys 837s Passed bug1644.ys 839s Passed bug2061.ys 839s Passed counter.ys 840s Passed dffs.ys 849s Passed dpram.ys 851s Passed fsm.ys 851s Passed ice40_dsp.ys 851s Passed ice40_opt.ys 851s Passed ice40_wrapcarry.ys 854s Passed latches.ys 855s Passed logic.ys 860s Passed macc.ys 912s Passed memories.ys 913s Passed mul.ys 916s Passed mux.ys 916s Warning: wire '\data' is assigned in a block at rom.v:10.5-10.15. 916s Warning: wire '\data' is assigned in a block at rom.v:11.5-11.15. 916s Warning: wire '\data' is assigned in a block at rom.v:12.5-12.15. 916s Warning: wire '\data' is assigned in a block at rom.v:13.6-13.16. 916s Warning: wire '\data' is assigned in a block at rom.v:14.6-14.16. 916s Warning: wire '\data' is assigned in a block at rom.v:15.6-15.16. 916s Warning: wire '\data' is assigned in a block at rom.v:16.11-16.21. 917s Passed rom.ys 918s Passed shifter.ys 918s Warning: wire '\read_data' is assigned in a block at spram.v:19.3-19.25. 919s Passed spram.ys 920s Passed tribuf.ys 920s make[1]: Leaving directory '/tmp/autopkgtest.9XLSHY/build.lOV/src/tests/arch/ice40' 920s cd tests/arch/xilinx && bash run-test.sh "" 920s make[1]: Entering directory '/tmp/autopkgtest.9XLSHY/build.lOV/src/tests/arch/xilinx' 935s Warning: Whitebox '$paramod\FDRE\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. 935s Warning: Whitebox 'FDSE' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. 935s Warning: Whitebox '$paramod\FDRE_1\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. 935s Warning: Whitebox '$paramod\FDSE_1\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox. 959s Passed abc9_dff.ys 963s Warning: Shift register inference not yet supported for family xc3s. 966s Passed add_sub.ys 985s Passed adffs.ys 990s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DIADI from 64 bits to 16 bits. 990s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOADO from 64 bits to 16 bits. 990s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOBDO from 64 bits to 16 bits. 990s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOPADOP from 8 bits to 2 bits. 990s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOPBDOP from 8 bits to 2 bits. 990s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.WEA from 4 bits to 2 bits. 998s Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.WEBWE from 1 bits to 4 bits. 1003s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DIADI from 64 bits to 16 bits. 1003s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOADO from 64 bits to 16 bits. 1003s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOBDO from 64 bits to 16 bits. 1003s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOPADOP from 8 bits to 2 bits. 1003s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOPBDOP from 8 bits to 2 bits. 1003s Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.WEA from 4 bits to 2 bits. 1003s Warning: Selection "asym_ram_sdp_read_wider" did not match any module. 1016s Passed asym_ram_sdp.ys 1021s Warning: Resizing cell port block_ram.memory.0.0.DIADI from 64 bits to 16 bits. 1021s Warning: Resizing cell port block_ram.memory.0.0.DOADO from 64 bits to 16 bits. 1021s Warning: Resizing cell port block_ram.memory.0.0.DOBDO from 64 bits to 16 bits. 1021s Warning: Resizing cell port block_ram.memory.0.0.DOPADOP from 8 bits to 2 bits. 1021s Warning: Resizing cell port block_ram.memory.0.0.DOPBDOP from 8 bits to 2 bits. 1021s Warning: Resizing cell port block_ram.memory.0.0.WEA from 4 bits to 2 bits. 1044s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DIADI from 64 bits to 16 bits. 1044s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOADO from 64 bits to 16 bits. 1044s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOBDO from 64 bits to 16 bits. 1044s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOPADOP from 8 bits to 2 bits. 1044s Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOPBDOP from 8 bits to 2 bits. 1044s Warning: Resizing cell port distributed_ram_manual.memory.0.0.WEA from 4 bits to 2 bits. 1044s Passed attributes_test.ys 1049s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIADI from 64 bits to 16 bits. 1049s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOADO from 64 bits to 16 bits. 1049s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOBDO from 64 bits to 16 bits. 1049s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPADOP from 8 bits to 2 bits. 1049s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPBDOP from 8 bits to 2 bits. 1049s Warning: Resizing cell port sync_ram_sdp.memory.0.0.WEA from 4 bits to 2 bits. 1053s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIPADIP from 8 bits to 2 bits. 1070s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIADI from 64 bits to 32 bits. 1070s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIPADIP from 8 bits to 4 bits. 1070s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOADO from 64 bits to 32 bits. 1070s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOBDO from 64 bits to 32 bits. 1070s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPADOP from 8 bits to 4 bits. 1070s Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPBDOP from 8 bits to 4 bits. 1099s Passed blockram.ys 1103s Passed bug1460.ys 1107s Passed bug1462.ys 1111s Passed bug1480.ys 1116s Passed bug1598.ys 1117s Warning: Wire top.\t is used but has no driver. 1117s Warning: Wire top.\in is used but has no driver. 1120s Passed bug1605.ys 1120s Passed bug3670.ys 1125s Passed counter.ys 1144s Passed dffs.ys 1159s Passed dsp_abc9.ys 1171s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef. 1171s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef. 1220s Passed dsp_cascade.ys 1224s Passed dsp_fastfir.ys 1230s Passed dsp_simd.ys 1235s Warning: Shift register inference not yet supported for family xc3se. 1238s Passed fsm.ys 1251s Passed latches.ys 1255s Passed logic.ys 1296s Warning: Shift register inference not yet supported for family xc3s. 1299s Passed lutram.ys 1310s Passed macc.ys 1317s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef. 1317s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef. 1319s Passed mul.ys 1319s Warning: Replacing memory \M with list of registers. See mul_unsigned.v:25 1329s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef. 1329s /usr/bin/../share/yosys/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef. 1333s Passed mul_unsigned.ys 1351s Passed mux.ys 1351s Warning: Shift register inference not yet supported for family xc3se. 1364s Passed mux_lut4.ys 1372s Passed nosrl.ys 1373s Passed opt_lut_ins.ys 1385s Passed pmgen_xilinx_srl.ys 1390s Warning: Resizing cell port priority_memory.mem.0.0.ADDRARDADDR from 16 bits to 15 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.0.ADDRBWRADDR from 16 bits to 15 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.0.DINADIN from 64 bits to 32 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.0.DINBDIN from 64 bits to 32 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.0.DINPADINP from 8 bits to 4 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.0.DINPBDINP from 8 bits to 4 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.0.DOUTADOUT from 64 bits to 32 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.0.DOUTBDOUT from 64 bits to 32 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.0.DOUTPADOUTP from 8 bits to 4 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.0.DOUTPBDOUTP from 8 bits to 4 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.0.WEBWE from 4 bits to 8 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.1.ADDRARDADDR from 16 bits to 15 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.1.ADDRBWRADDR from 16 bits to 15 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.1.DINADIN from 64 bits to 32 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.1.DINBDIN from 64 bits to 32 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.1.DINPADINP from 8 bits to 4 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.1.DINPBDINP from 8 bits to 4 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.1.DOUTADOUT from 64 bits to 32 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.1.DOUTBDOUT from 64 bits to 32 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.1.DOUTPADOUTP from 8 bits to 4 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.1.DOUTPBDOUTP from 8 bits to 4 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.1.WEBWE from 4 bits to 8 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.2.ADDRARDADDR from 16 bits to 15 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.2.ADDRBWRADDR from 16 bits to 15 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.2.DINADIN from 64 bits to 32 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.2.DINBDIN from 64 bits to 32 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.2.DINPADINP from 8 bits to 4 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.2.DINPBDINP from 8 bits to 4 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.2.DOUTADOUT from 64 bits to 32 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.2.DOUTBDOUT from 64 bits to 32 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.2.DOUTPADOUTP from 8 bits to 4 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.2.DOUTPBDOUTP from 8 bits to 4 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.2.WEBWE from 4 bits to 8 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.3.ADDRARDADDR from 16 bits to 15 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.3.ADDRBWRADDR from 16 bits to 15 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.3.DINADIN from 64 bits to 32 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.3.DINBDIN from 64 bits to 32 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.3.DINPADINP from 8 bits to 4 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.3.DINPBDINP from 8 bits to 4 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.3.DOUTADOUT from 64 bits to 32 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.3.DOUTBDOUT from 64 bits to 32 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.3.DOUTPADOUTP from 8 bits to 4 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.3.DOUTPBDOUTP from 8 bits to 4 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.3.WEBWE from 4 bits to 8 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.4.ADDRARDADDR from 16 bits to 15 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.4.ADDRBWRADDR from 16 bits to 15 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.4.DINADIN from 64 bits to 32 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.4.DINBDIN from 64 bits to 32 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.4.DINPADINP from 8 bits to 4 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.4.DINPBDINP from 8 bits to 4 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.4.DOUTADOUT from 64 bits to 32 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.4.DOUTBDOUT from 64 bits to 32 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.4.DOUTPADOUTP from 8 bits to 4 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.4.DOUTPBDOUTP from 8 bits to 4 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.4.WEBWE from 4 bits to 8 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.5.ADDRARDADDR from 16 bits to 15 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.5.ADDRBWRADDR from 16 bits to 15 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.5.DINADIN from 64 bits to 32 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.5.DINBDIN from 64 bits to 32 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.5.DINPADINP from 8 bits to 4 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.5.DINPBDINP from 8 bits to 4 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.5.DOUTADOUT from 64 bits to 32 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.5.DOUTBDOUT from 64 bits to 32 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.5.DOUTPADOUTP from 8 bits to 4 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.5.DOUTPBDOUTP from 8 bits to 4 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.5.WEBWE from 4 bits to 8 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.6.ADDRARDADDR from 16 bits to 15 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.6.ADDRBWRADDR from 16 bits to 15 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.6.DINADIN from 64 bits to 32 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.6.DINBDIN from 64 bits to 32 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.6.DINPADINP from 8 bits to 4 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.6.DINPBDINP from 8 bits to 4 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.6.DOUTADOUT from 64 bits to 32 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.6.DOUTBDOUT from 64 bits to 32 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.6.DOUTPADOUTP from 8 bits to 4 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.6.DOUTPBDOUTP from 8 bits to 4 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.6.WEBWE from 4 bits to 8 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.7.ADDRARDADDR from 16 bits to 15 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.7.ADDRBWRADDR from 16 bits to 15 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.7.DINADIN from 64 bits to 32 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.7.DINBDIN from 64 bits to 32 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.7.DINPADINP from 8 bits to 4 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.7.DINPBDINP from 8 bits to 4 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.7.DOUTADOUT from 64 bits to 32 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.7.DOUTBDOUT from 64 bits to 32 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.7.DOUTPADOUTP from 8 bits to 4 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.7.DOUTPBDOUTP from 8 bits to 4 bits. 1390s Warning: Resizing cell port priority_memory.mem.0.7.WEBWE from 4 bits to 8 bits. 1394s Warning: Resizing cell port priority_memory.mem.0.0.BWE_A from 8 bits to 9 bits. 1394s Warning: Resizing cell port priority_memory.mem.0.0.BWE_B from 8 bits to 9 bits. 1406s Warning: Resizing cell port sp_write_first.mem.0.0.BWE_A from 8 bits to 9 bits. 1410s Warning: Resizing cell port sp_read_first.mem.0.0.BWE_B from 8 bits to 9 bits. 1410s Passed priority_memory.ys 1414s Passed shifter.ys 1419s Passed tribuf.ys 1422s Passed xilinx_dffopt.ys 1422s Passed xilinx_dsp.ys 1423s Passed xilinx_srl.ys 1431s Passed macc.sh 1439s Passed tribuf.sh 1439s make[1]: Leaving directory '/tmp/autopkgtest.9XLSHY/build.lOV/src/tests/arch/xilinx' 1439s cd tests/arch/ecp5 && bash run-test.sh "" 1439s make[1]: Entering directory '/tmp/autopkgtest.9XLSHY/build.lOV/src/tests/arch/ecp5' 1440s Passed add_sub.ys 1442s Passed adffs.ys 1443s Passed bug1459.ys 1444s Passed bug1598.ys 1444s Passed bug1630.ys 1444s Warning: Literal has a width of 16 bit, but value requires 184 bit. (<>>/,/<<>>/ {print $0}' 1886s + iverilog -o iverilog-initial_display initial_display.v 1886s + ./iverilog-initial_display 1886s + diff yosys-initial_display.log iverilog-initial_display.log 1886s + test_always_display clk -DEVENT_CLK 1886s + local subtest=clk 1886s + shift 1886s + ../../yosys -p 'read_verilog -DEVENT_CLK always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk-1.v 1886s + ../../yosys -p 'read_verilog yosys-always_display-clk-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk-2.v 1886s + diff yosys-always_display-clk-1.v yosys-always_display-clk-2.v 1886s + test_always_display clk_rst -DEVENT_CLK_RST 1886s + local subtest=clk_rst 1886s + shift 1886s + ../../yosys -p 'read_verilog -DEVENT_CLK_RST always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst-1.v 1886s 1886s /----------------------------------------------------------------------------\ 1886s | | 1886s | yosys -- Yosys Open SYnthesis Suite | 1886s | | 1886s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1886s | | 1886s | Permission to use, copy, modify, and/or distribute this software for any | 1886s | purpose with or without fee is hereby granted, provided that the above | 1886s | copyright notice and this permission notice appear in all copies. | 1886s | | 1886s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1886s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1886s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1886s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1886s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1886s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1886s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1886s | | 1886s \----------------------------------------------------------------------------/ 1886s 1886s Yosys 0.33 (git sha1 2584903a060) 1886s 1886s 1886s -- Running command `read_verilog -DEVENT_CLK always_display.v; proc; opt_expr -mux_bool; clean' -- 1886s 1886s 1. Executing Verilog-2005 frontend: always_display.v 1886s Parsing Verilog input from `always_display.v' to AST representation. 1886s Generating RTLIL representation for module `\m'. 1886s Successfully finished Verilog frontend. 1886s 1886s 2. Executing PROC pass (convert processes to netlists). 1886s 1886s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Cleaned up 0 empty switches. 1886s 1886s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1886s Removed a total of 0 dead cases. 1886s 1886s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1886s Removed 1 redundant assignment. 1886s Promoted 1 assignment to connection. 1886s 1886s 2.4. Executing PROC_INIT pass (extract init attributes). 1886s 1886s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1886s 1886s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1886s Converted 0 switches. 1886s 1886s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1886s Creating decoders for process `\m.$proc$always_display.v:4$1'. 1886s 1886s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1886s 1886s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1886s 1886s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1886s 1886s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Removing empty process `m.$proc$always_display.v:4$1'. 1886s Cleaned up 0 empty switches. 1886s 1886s 2.12. Executing OPT_EXPR pass (perform const folding). 1886s Optimizing module m. 1886s 1886s 3. Executing OPT_EXPR pass (perform const folding). 1886s Optimizing module m. 1886s Removed 0 unused cells and 1 unused wires. 1886s 1886s -- Writing to `yosys-always_display-clk-1.v' using backend `verilog' -- 1886s 1886s 4. Executing Verilog backend. 1886s 1886s 4.1. Executing BMUXMAP pass. 1886s 1886s 4.2. Executing DEMUXMAP pass. 1886s Dumping module `\m'. 1886s 1886s End of script. Logfile hash: 0de35d2746, CPU: user 0.01s system 0.00s, MEM: 9.50 MB peak 1886s Yosys 0.33 (git sha1 2584903a060) 1886s Time spent: 35% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ... 1886s 1886s /----------------------------------------------------------------------------\ 1886s | | 1886s | yosys -- Yosys Open SYnthesis Suite | 1886s | | 1886s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1886s | | 1886s | Permission to use, copy, modify, and/or distribute this software for any | 1886s | purpose with or without fee is hereby granted, provided that the above | 1886s | copyright notice and this permission notice appear in all copies. | 1886s | | 1886s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1886s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1886s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1886s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1886s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1886s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1886s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1886s | | 1886s \----------------------------------------------------------------------------/ 1886s 1886s Yosys 0.33 (git sha1 2584903a060) 1886s 1886s 1886s -- Running command `read_verilog yosys-always_display-clk-1.v; proc; opt_expr -mux_bool; clean' -- 1886s 1886s 1. Executing Verilog-2005 frontend: yosys-always_display-clk-1.v 1886s Parsing Verilog input from `yosys-always_display-clk-1.v' to AST representation. 1886s Generating RTLIL representation for module `\m'. 1886s Successfully finished Verilog frontend. 1886s 1886s 2. Executing PROC pass (convert processes to netlists). 1886s 1886s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk-1.v:18$1'. 1886s Cleaned up 1 empty switch. 1886s 1886s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1886s Removed a total of 0 dead cases. 1886s 1886s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1886s Removed 1 redundant assignment. 1886s Promoted 1 assignment to connection. 1886s 1886s 2.4. Executing PROC_INIT pass (extract init attributes). 1886s 1886s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1886s 1886s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1886s Converted 0 switches. 1886s 1886s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1886s Creating decoders for process `\m.$proc$yosys-always_display-clk-1.v:18$1'. 1886s 1886s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1886s 1886s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1886s 1886s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1886s 1886s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Removing empty process `m.$proc$yosys-always_display-clk-1.v:18$1'. 1886s Cleaned up 0 empty switches. 1886s 1886s 2.12. Executing OPT_EXPR pass (perform const folding). 1886s Optimizing module m. 1886s 1886s 3. Executing OPT_EXPR pass (perform const folding). 1886s Optimizing module m. 1886s Removed 0 unused cells and 1 unused wires. 1886s 1886s -- Writing to `yosys-always_display-clk-2.v' using backend `verilog' -- 1886s 1886s 4. Executing Verilog backend. 1886s 1886s 4.1. Executing BMUXMAP pass. 1886s 1886s 4.2. Executing DEMUXMAP pass. 1886s Dumping module `\m'. 1886s 1886s End of script. Logfile hash: e35e8bb689, CPU: user 0.00s system 0.00s, MEM: 9.50 MB peak 1886s Yosys 0.33 (git sha1 2584903a060) 1886s Time spent: 35% 2x opt_expr (0 sec), 23% 1x clean (0 sec), ... 1886s 1886s /----------------------------------------------------------------------------\ 1886s | | 1886s | yosys -- Yosys Open SYnthesis Suite | 1886s | | 1886s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1886s | | 1886s | Permission to use, copy, modify, and/or distribute this software for any | 1886s | purpose with or without fee is hereby granted, provided that the above | 1886s | copyright notice and this permission notice appear in all copies. | 1886s | | 1886s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1886s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1886s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1886s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1886s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1886s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1886s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1886s | | 1886s \----------------------------------------------------------------------------/ 1886s 1886s Yosys 0.33 (git sha1 2584903a060) 1886s 1886s 1886s -- Running command `read_verilog -DEVENT_CLK_RST always_display.v; proc; opt_expr -mux_bool; clean' -- 1886s 1886s 1. Executing Verilog-2005 frontend: always_display.v 1886s Parsing Verilog input from `always_display.v' to AST representation. 1886s Generating RTLIL representation for module `\m'. 1886s Successfully finished Verilog frontend. 1886s 1886s 2. Executing PROC pass (convert processes to netlists). 1886s 1886s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Cleaned up 0 empty switches. 1886s 1886s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1886s Removed a total of 0 dead cases. 1886s 1886s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1886s Removed 1 redundant assignment. 1886s Promoted 1 assignment to connection. 1886s 1886s 2.4. Executing PROC_INIT pass (extract init attributes). 1886s 1886s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1886s 1886s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1886s Converted 0 switches. 1886s 1886s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1886s Creating decoders for process `\m.$proc$always_display.v:7$1'. 1886s 1886s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1886s 1886s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1886s 1886s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1886s 1886s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Removing empty process `m.$proc$always_display.v:7$1'. 1886s Cleaned up 0 empty switches. 1886s 1886s 2.12. Executing OPT_EXPR pass (perform const folding). 1886s Optimizing module m. 1886s 1886s 3. Executing OPT_EXPR pass (perform const folding). 1886s Optimizing module m. 1886s Removed 0 unused cells and 1 unused wires. 1886s 1886s -- Writing to `yosys-always_display-clk_rst-1.v' using backend `verilog' -- 1886s 1886s 4. Executing Verilog backend. 1886s 1886s 4.1. Executing BMUXMAP pass. 1886s 1886s 4.2. Executing DEMUXMAP pass. 1886s Dumping module `\m'. 1886s 1886s End of script. Logfile hash: c95608ddf0, CPU: user 0.01s system 0.00s, MEM: 9.50 MB peak 1886s Yosys 0.33 (git sha1 2584903a060) 1886s Time spent: 38% 2x opt_expr (0 sec), 23% 1x clean (0 sec), ... 1886s 1886s /----------------------------------------------------------------------------\ 1886s | | 1886s | yosys -- Yosys Open SYnthesis Suite | 1886s | | 1886s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1886s | | 1886s | Permission to use, copy, modify, and/or distribute this software for any | 1886s | purpose with or without fee is hereby granted, provided that the above | 1886s | copyright notice and this permission notice appear in all copies. | 1886s | | 1886s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1886s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1886s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1886s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1886s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1886s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1886s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1886s | | 1886s \----------------------------------------------------------------------------/ 1886s 1886s Yosys 0.33 (git sha1 2584903a060) 1886s 1886s 1886s -- Running command `read_verilog yosys-always_display-clk_rst-1.v; proc; opt_expr -mux_bool; clean' -- 1886s 1886s 1. Executing Verilog-2005 frontend: yosys-always_display-clk_rst-1.v 1886s Parsing Verilog input from `yosys-always_display-clk_rst-1.v' to AST representation. 1886s Generating RTLIL representation for module `\m'. 1886s Successfully finished Verilog frontend. 1886s 1886s 2. Executing PROC pass (convert processes to netlists). 1886s 1886s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_rst-1.v:18$1'. 1886s Cleaned up 1 empty switch. 1886s 1886s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1886s Removed a total of 0 dead cases. 1886s 1886s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1886s Removed 1 redundant assignment. 1886s Promoted 1 assignment to connection. 1886s 1886s 2.4. Executing PROC_INIT pass (extract init attributes). 1886s 1886s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1886s 1886s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1886s Converted 0 switches. 1886s 1886s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1886s Creating decoders for process `\m.$proc$yosys-always_display-clk_rst-1.v:18$1'. 1886s 1886s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1886s 1886s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1886s 1886s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1886s 1886s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Removing empty process `m.$proc$yosys-always_display-clk_rst-1.v:18$1'. 1886s Cleaned up 0 empty switches. 1886s 1886s 2.12. Executing OPT_EXPR pass (perform const folding). 1886s Optimizing module m. 1886s 1886s 3. Executing OPT_EXPR pass (perform const folding). 1886s Optimizing module m. 1886s Removed 0 unused cells and 1 unused wires. 1886s 1886s -- Writing to `yosys-always_display-clk_rst-2.v' using backend `verilog' -- 1886s 1886s 4. Executing Verilog backend. 1886s 1886s 4.1. Executing BMUXMAP pass. 1886s 1886s 4.2. Executing DEMUXMAP pass. 1886s Dumping module `\m'. 1886s 1886s End of script. Logfile hash: faf50513c3, CPU: user 0.00s system 0.00s, MEM: 9.50 MB peak 1886s Yosys 0.33 (git sha1 2584903a060) 1886s Time spent: 35% 2x opt_expr (0 sec), 24% 1x clean (0 sec), ... 1886s + ../../yosys -p 'read_verilog yosys-always_display-clk_rst-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst-2.v 1886s + diff yosys-always_display-clk_rst-1.v yosys-always_display-clk_rst-2.v 1886s + test_always_display star -DEVENT_STAR 1886s + local subtest=star 1886s + shift 1886s + ../../yosys -p 'read_verilog -DEVENT_STAR always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star-1.v 1886s 1886s /----------------------------------------------------------------------------\ 1886s | | 1886s | yosys -- Yosys Open SYnthesis Suite | 1886s | | 1886s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1886s | | 1886s | Permission to use, copy, modify, and/or distribute this software for any | 1886s | purpose with or without fee is hereby granted, provided that the above | 1886s | copyright notice and this permission notice appear in all copies. | 1886s | | 1886s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1886s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1886s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1886s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1886s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1886s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1886s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1886s | | 1886s \----------------------------------------------------------------------------/ 1886s 1886s Yosys 0.33 (git sha1 2584903a060) 1886s 1886s 1886s -- Running command `read_verilog -DEVENT_STAR always_display.v; proc; opt_expr -mux_bool; clean' -- 1886s 1886s 1. Executing Verilog-2005 frontend: always_display.v 1886s Parsing Verilog input from `always_display.v' to AST representation. 1886s Generating RTLIL representation for module `\m'. 1886s Successfully finished Verilog frontend. 1886s 1886s 2. Executing PROC pass (convert processes to netlists). 1886s 1886s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Cleaned up 0 empty switches. 1886s 1886s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1886s Removed a total of 0 dead cases. 1886s 1886s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1886s Removed 1 redundant assignment. 1886s Promoted 1 assignment to connection. 1886s 1886s 2.4. Executing PROC_INIT pass (extract init attributes). 1886s 1886s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1886s 1886s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1886s Converted 0 switches. 1886s 1886s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1886s Creating decoders for process `\m.$proc$always_display.v:10$1'. 1886s 1886s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1886s 1886s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1886s 1886s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1886s 1886s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Removing empty process `m.$proc$always_display.v:10$1'. 1886s Cleaned up 0 empty switches. 1886s 1886s 2.12. Executing OPT_EXPR pass (perform const folding). 1886s Optimizing module m. 1886s 1886s 3. Executing OPT_EXPR pass (perform const folding). 1886s Optimizing module m. 1886s Removed 0 unused cells and 1 unused wires. 1886s 1886s -- Writing to `yosys-always_display-star-1.v' using backend `verilog' -- 1886s 1886s 4. Executing Verilog backend. 1886s 1886s 4.1. Executing BMUXMAP pass. 1886s 1886s 4.2. Executing DEMUXMAP pass. 1886s Dumping module `\m'. 1886s 1886s End of script. Logfile hash: 7b2c5274a5, CPU: user 0.01s system 0.00s, MEM: 9.50 MB peak 1886s Yosys 0.33 (git sha1 2584903a060) 1886s Time spent: 37% 2x opt_expr (0 sec), 23% 1x clean (0 sec), ... 1886s + ../../yosys -p 'read_verilog yosys-always_display-star-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star-2.v 1886s 1886s /----------------------------------------------------------------------------\ 1886s | | 1886s | yosys -- Yosys Open SYnthesis Suite | 1886s | | 1886s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1886s | | 1886s | Permission to use, copy, modify, and/or distribute this software for any | 1886s | purpose with or without fee is hereby granted, provided that the above | 1886s | copyright notice and this permission notice appear in all copies. | 1886s | | 1886s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1886s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1886s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1886s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1886s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1886s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1886s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1886s | | 1886s \----------------------------------------------------------------------------/ 1886s 1886s Yosys 0.33 (git sha1 2584903a060) 1886s 1886s 1886s -- Running command `read_verilog yosys-always_display-star-1.v; proc; opt_expr -mux_bool; clean' -- 1886s 1886s 1. Executing Verilog-2005 frontend: yosys-always_display-star-1.v 1886s Parsing Verilog input from `yosys-always_display-star-1.v' to AST representation. 1886s Generating RTLIL representation for module `\m'. 1886s Successfully finished Verilog frontend. 1886s 1886s 2. Executing PROC pass (convert processes to netlists). 1886s 1886s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-star-1.v:18$1'. 1886s Cleaned up 1 empty switch. 1886s 1886s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1886s Removed a total of 0 dead cases. 1886s 1886s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1886s Removed 1 redundant assignment. 1886s Promoted 1 assignment to connection. 1886s 1886s 2.4. Executing PROC_INIT pass (extract init attributes). 1886s 1886s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1886s 1886s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1886s Converted 0 switches. 1886s 1886s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1886s Creating decoders for process `\m.$proc$yosys-always_display-star-1.v:18$1'. 1886s 1886s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1886s 1886s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1886s + diff yosys-always_display-star-1.v yosys-always_display-star-2.v 1886s + test_always_display clk_en -DEVENT_CLK -DCOND_EN 1886s + local subtest=clk_en 1886s + shift 1886s + ../../yosys -p 'read_verilog -DEVENT_CLK -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_en-1.v 1886s 1886s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1886s 1886s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Removing empty process `m.$proc$yosys-always_display-star-1.v:18$1'. 1886s Cleaned up 0 empty switches. 1886s 1886s 2.12. Executing OPT_EXPR pass (perform const folding). 1886s Optimizing module m. 1886s 1886s 3. Executing OPT_EXPR pass (perform const folding). 1886s Optimizing module m. 1886s Removed 0 unused cells and 1 unused wires. 1886s 1886s -- Writing to `yosys-always_display-star-2.v' using backend `verilog' -- 1886s 1886s 4. Executing Verilog backend. 1886s 1886s 4.1. Executing BMUXMAP pass. 1886s 1886s 4.2. Executing DEMUXMAP pass. 1886s Dumping module `\m'. 1886s 1886s End of script. Logfile hash: 8979c5de0b, CPU: user 0.01s system 0.00s, MEM: 9.50 MB peak 1886s Yosys 0.33 (git sha1 2584903a060) 1886s Time spent: 35% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ... 1886s 1886s /----------------------------------------------------------------------------\ 1886s | | 1886s | yosys -- Yosys Open SYnthesis Suite | 1886s | | 1886s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1886s | | 1886s | Permission to use, copy, modify, and/or distribute this software for any | 1886s | purpose with or without fee is hereby granted, provided that the above | 1886s | copyright notice and this permission notice appear in all copies. | 1886s | | 1886s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1886s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1886s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1886s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1886s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1886s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1886s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1886s | | 1886s \----------------------------------------------------------------------------/ 1886s 1886s Yosys 0.33 (git sha1 2584903a060) 1886s 1886s 1886s -- Running command `read_verilog -DEVENT_CLK -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -- 1886s 1886s 1. Executing Verilog-2005 frontend: always_display.v 1886s Parsing Verilog input from `always_display.v' to AST representation. 1886s Generating RTLIL representation for module `\m'. 1886s Successfully finished Verilog frontend. 1886s 1886s 2. Executing PROC pass (convert processes to netlists). 1886s 1886s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Cleaned up 0 empty switches. 1886s 1886s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1886s Removed a total of 0 dead cases. 1886s 1886s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1886s Removed 0 redundant assignments. 1886s Promoted 0 assignments to connections. 1886s 1886s 2.4. Executing PROC_INIT pass (extract init attributes). 1886s 1886s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1886s 1886s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1886s Converted 0 switches. 1886s 1886s 1886s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1886s Creating decoders for process `\m.$proc$always_display.v:4$1'. 1886s 1/1: $display$always_display.v:15$2_EN 1886s 1886s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1886s 1886s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1886s 1886s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1886s 1886s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:4$1'. 1886s Removing empty process `m.$proc$always_display.v:4$1'. 1886s Cleaned up 1 empty switch. 1886s 1886s 2.12. Executing OPT_EXPR pass (perform const folding). 1886s Optimizing module m. 1886s 1886s 3. Executing OPT_EXPR pass (perform const folding). 1886s Optimizing module m. 1886s 1886s + ../../yosys -p 'read_verilog yosys-always_display-clk_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_en-2.v 1886s + diff yosys-always_display-clk_en-1.v yosys-always_display-clk_en-2.v 1886s + test_always_display clk_rst_en -DEVENT_CLK_RST -DCOND_EN 1886s + local subtest=clk_rst_en 1886s + shift 1886s + ../../yosys -p 'read_verilog -DEVENT_CLK_RST -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst_en-1.v 1886s + ../../yosys -p 'read_verilog yosys-always_display-clk_rst_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst_en-2.v 1886s + diff yosys-always_display-clk_rst_en-1.v yosys-always_display-clk_rst_en-2.v 1886s + test_always_display star_en -DEVENT_STAR -DCOND_EN 1886s + local subtest=star_en 1886s + shift 1886s + ../../yosys -p 'read_verilog -DEVENT_STAR -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star_en-1.v 1886s + ../../yosys -p 'read_verilog yosys-always_display-star_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star_en-2.v 1886s Removed 0 unused cells and 3 unused wires. 1886s 1886s -- Writing to `yosys-always_display-clk_en-1.v' using backend `verilog' -- 1886s 1886s 4. Executing Verilog backend. 1886s 1886s 4.1. Executing BMUXMAP pass. 1886s 1886s 4.2. Executing DEMUXMAP pass. 1886s Dumping module `\m'. 1886s 1886s End of script. Logfile hash: 4f8a3b339c, CPU: user 0.01s system 0.00s, MEM: 9.62 MB peak 1886s Yosys 0.33 (git sha1 2584903a060) 1886s Time spent: 39% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ... 1886s 1886s /----------------------------------------------------------------------------\ 1886s | | 1886s | yosys -- Yosys Open SYnthesis Suite | 1886s | | 1886s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1886s | | 1886s | Permission to use, copy, modify, and/or distribute this software for any | 1886s | purpose with or without fee is hereby granted, provided that the above | 1886s | copyright notice and this permission notice appear in all copies. | 1886s | | 1886s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1886s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1886s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1886s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1886s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1886s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1886s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1886s | | 1886s \----------------------------------------------------------------------------/ 1886s 1886s Yosys 0.33 (git sha1 2584903a060) 1886s 1886s 1886s -- Running command `read_verilog yosys-always_display-clk_en-1.v; proc; opt_expr -mux_bool; clean' -- 1886s 1886s 1. Executing Verilog-2005 frontend: yosys-always_display-clk_en-1.v 1886s Parsing Verilog input from `yosys-always_display-clk_en-1.v' to AST representation. 1886s Generating RTLIL representation for module `\m'. 1886s Successfully finished Verilog frontend. 1886s 1886s 2. Executing PROC pass (convert processes to netlists). 1886s 1886s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Cleaned up 0 empty switches. 1886s 1886s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1886s Removed a total of 0 dead cases. 1886s 1886s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1886s Removed 0 redundant assignments. 1886s Promoted 0 assignments to connections. 1886s 1886s 2.4. Executing PROC_INIT pass (extract init attributes). 1886s 1886s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1886s 1886s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1886s Converted 0 switches. 1886s 1886s 1886s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1886s Creating decoders for process `\m.$proc$yosys-always_display-clk_en-1.v:18$1'. 1886s 1/1: $write$yosys-always_display-clk_en-1.v:20$2_EN 1886s 1886s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1886s 1886s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1886s 1886s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1886s 1886s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_en-1.v:18$1'. 1886s Removing empty process `m.$proc$yosys-always_display-clk_en-1.v:18$1'. 1886s Cleaned up 1 empty switch. 1886s 1886s 2.12. Executing OPT_EXPR pass (perform const folding). 1886s Optimizing module m. 1886s 1886s 3. Executing OPT_EXPR pass (perform const folding). 1886s Optimizing module m. 1886s 1886s Removed 0 unused cells and 3 unused wires. 1886s 1886s -- Writing to `yosys-always_display-clk_en-2.v' using backend `verilog' -- 1886s 1886s 4. Executing Verilog backend. 1886s 1886s 4.1. Executing BMUXMAP pass. 1886s 1886s 4.2. Executing DEMUXMAP pass. 1886s Dumping module `\m'. 1886s 1886s End of script. Logfile hash: 51e7fa3902, CPU: user 0.01s system 0.00s, MEM: 9.62 MB peak 1886s Yosys 0.33 (git sha1 2584903a060) 1886s Time spent: 38% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ... 1886s 1886s /----------------------------------------------------------------------------\ 1886s | | 1886s | yosys -- Yosys Open SYnthesis Suite | 1886s | | 1886s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1886s | | 1886s | Permission to use, copy, modify, and/or distribute this software for any | 1886s | purpose with or without fee is hereby granted, provided that the above | 1886s | copyright notice and this permission notice appear in all copies. | 1886s | | 1886s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1886s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1886s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1886s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1886s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1886s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1886s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1886s | | 1886s \----------------------------------------------------------------------------/ 1886s 1886s Yosys 0.33 (git sha1 2584903a060) 1886s 1886s 1886s -- Running command `read_verilog -DEVENT_CLK_RST -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -- 1886s 1886s 1. Executing Verilog-2005 frontend: always_display.v 1886s Parsing Verilog input from `always_display.v' to AST representation. 1886s Generating RTLIL representation for module `\m'. 1886s Successfully finished Verilog frontend. 1886s 1886s 2. Executing PROC pass (convert processes to netlists). 1886s 1886s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Cleaned up 0 empty switches. 1886s 1886s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1886s Removed a total of 0 dead cases. 1886s 1886s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1886s Removed 0 redundant assignments. 1886s Promoted 0 assignments to connections. 1886s 1886s 2.4. Executing PROC_INIT pass (extract init attributes). 1886s 1886s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1886s 1886s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1886s Converted 0 switches. 1886s 1886s 1886s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1886s Creating decoders for process `\m.$proc$always_display.v:7$1'. 1886s 1/1: $display$always_display.v:15$2_EN 1886s 1886s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1886s 1886s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1886s 1886s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1886s 1886s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:7$1'. 1886s Removing empty process `m.$proc$always_display.v:7$1'. 1886s Cleaned up 1 empty switch. 1886s 1886s 2.12. Executing OPT_EXPR pass (perform const folding). 1886s Optimizing module m. 1886s 1886s 3. Executing OPT_EXPR pass (perform const folding). 1886s Optimizing module m. 1886s 1886s Removed 0 unused cells and 3 unused wires. 1886s 1886s -- Writing to `yosys-always_display-clk_rst_en-1.v' using backend `verilog' -- 1886s 1886s 4. Executing Verilog backend. 1886s 1886s 4.1. Executing BMUXMAP pass. 1886s 1886s 4.2. Executing DEMUXMAP pass. 1886s Dumping module `\m'. 1886s 1886s End of script. Logfile hash: f9b4876f33, CPU: user 0.00s system 0.00s, MEM: 9.62 MB peak 1886s Yosys 0.33 (git sha1 2584903a060) 1886s Time spent: 37% 2x opt_expr (0 sec), 21% 1x clean (0 sec), ... 1886s 1886s /----------------------------------------------------------------------------\ 1886s | | 1886s | yosys -- Yosys Open SYnthesis Suite | 1886s | | 1886s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1886s | | 1886s | Permission to use, copy, modify, and/or distribute this software for any | 1886s | purpose with or without fee is hereby granted, provided that the above | 1886s | copyright notice and this permission notice appear in all copies. | 1886s | | 1886s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1886s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1886s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1886s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1886s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1886s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1886s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1886s | | 1886s \----------------------------------------------------------------------------/ 1886s 1886s Yosys 0.33 (git sha1 2584903a060) 1886s 1886s 1886s -- Running command `read_verilog yosys-always_display-clk_rst_en-1.v; proc; opt_expr -mux_bool; clean' -- 1886s 1886s 1. Executing Verilog-2005 frontend: yosys-always_display-clk_rst_en-1.v 1886s Parsing Verilog input from `yosys-always_display-clk_rst_en-1.v' to AST representation. 1886s Generating RTLIL representation for module `\m'. 1886s Successfully finished Verilog frontend. 1886s 1886s 2. Executing PROC pass (convert processes to netlists). 1886s 1886s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Cleaned up 0 empty switches. 1886s 1886s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1886s Removed a total of 0 dead cases. 1886s 1886s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1886s Removed 0 redundant assignments. 1886s Promoted 0 assignments to connections. 1886s 1886s 2.4. Executing PROC_INIT pass (extract init attributes). 1886s 1886s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1886s 1886s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1886s Converted 0 switches. 1886s 1886s 1886s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1886s Creating decoders for process `\m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'. 1886s 1/1: $write$yosys-always_display-clk_rst_en-1.v:20$2_EN 1886s 1886s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1886s 1886s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1886s 1886s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1886s 1886s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'. 1886s Removing empty process `m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'. 1886s Cleaned up 1 empty switch. 1886s 1886s 2.12. Executing OPT_EXPR pass (perform const folding). 1886s Optimizing module m. 1886s 1886s 3. Executing OPT_EXPR pass (perform const folding). 1886s Optimizing module m. 1886s 1886s Removed 0 unused cells and 3 unused wires. 1886s 1886s -- Writing to `yosys-always_display-clk_rst_en-2.v' using backend `verilog' -- 1886s 1886s 4. Executing Verilog backend. 1886s 1886s 4.1. Executing BMUXMAP pass. 1886s 1886s 4.2. Executing DEMUXMAP pass. 1886s Dumping module `\m'. 1886s 1886s End of script. Logfile hash: 0c4b4eaa9c, CPU: user 0.01s system 0.00s, MEM: 9.62 MB peak 1886s Yosys 0.33 (git sha1 2584903a060) 1886s Time spent: 38% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ... 1886s 1886s /----------------------------------------------------------------------------\ 1886s | | 1886s | yosys -- Yosys Open SYnthesis Suite | 1886s | | 1886s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1886s | | 1886s | Permission to use, copy, modify, and/or distribute this software for any | 1886s | purpose with or without fee is hereby granted, provided that the above | 1886s | copyright notice and this permission notice appear in all copies. | 1886s | | 1886s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1886s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1886s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1886s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1886s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1886s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1886s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1886s | | 1886s \----------------------------------------------------------------------------/ 1886s 1886s Yosys 0.33 (git sha1 2584903a060) 1886s 1886s 1886s -- Running command `read_verilog -DEVENT_STAR -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -- 1886s 1886s 1. Executing Verilog-2005 frontend: always_display.v 1886s Parsing Verilog input from `always_display.v' to AST representation. 1886s Generating RTLIL representation for module `\m'. 1886s Successfully finished Verilog frontend. 1886s 1886s 2. Executing PROC pass (convert processes to netlists). 1886s 1886s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Cleaned up 0 empty switches. 1886s 1886s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1886s Removed a total of 0 dead cases. 1886s 1886s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1886s Removed 0 redundant assignments. 1886s Promoted 0 assignments to connections. 1886s 1886s 2.4. Executing PROC_INIT pass (extract init attributes). 1886s 1886s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1886s 1886s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1886s Converted 0 switches. 1886s 1886s 1886s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1886s Creating decoders for process `\m.$proc$always_display.v:10$1'. 1886s 1/1: $display$always_display.v:15$2_EN 1886s 1886s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1886s 1886s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1886s 1886s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1886s 1886s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:10$1'. 1886s Removing empty process `m.$proc$always_display.v:10$1'. 1886s Cleaned up 1 empty switch. 1886s 1886s 2.12. Executing OPT_EXPR pass (perform const folding). 1886s Optimizing module m. 1886s 1886s 3. Executing OPT_EXPR pass (perform const folding). 1886s Optimizing module m. 1886s 1886s Removed 0 unused cells and 3 unused wires. 1886s 1886s -- Writing to `yosys-always_display-star_en-1.v' using backend `verilog' -- 1886s 1886s 4. Executing Verilog backend. 1886s 1886s 4.1. Executing BMUXMAP pass. 1886s 1886s 4.2. Executing DEMUXMAP pass. 1886s Dumping module `\m'. 1886s 1886s End of script. Logfile hash: d6a7335726, CPU: user 0.00s system 0.00s, MEM: 9.50 MB peak 1886s Yosys 0.33 (git sha1 2584903a060) 1886s Time spent: 38% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ... 1886s 1886s /----------------------------------------------------------------------------\ 1886s | | 1886s | yosys -- Yosys Open SYnthesis Suite | 1886s | | 1886s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1886s | | 1886s | Permission to use, copy, modify, and/or distribute this software for any | 1886s | purpose with or without fee is hereby granted, provided that the above | 1886s | copyright notice and this permission notice appear in all copies. | 1886s | | 1886s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1886s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1886s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1886s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1886s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1886s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1886s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1886s | | 1886s \----------------------------------------------------------------------------/ 1886s 1886s Yosys 0.33 (git sha1 2584903a060) 1886s 1886s 1886s -- Running command `read_verilog yosys-always_display-star_en-1.v; proc; opt_expr -mux_bool; clean' -- 1886s 1886s 1. Executing Verilog-2005 frontend: yosys-always_display-star_en-1.v 1886s Parsing Verilog input from `yosys-always_display-star_en-1.v' to AST representation. 1886s Generating RTLIL representation for module `\m'. 1886s Successfully finished Verilog frontend. 1886s 1886s 2. Executing PROC pass (convert processes to netlists). 1886s 1886s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Cleaned up 0 empty switches. 1886s 1886s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1886s Removed a total of 0 dead cases. 1886s 1886s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1886s Removed 0 redundant assignments. 1886s Promoted 0 assignments to connections. 1886s 1886s 2.4. Executing PROC_INIT pass (extract init attributes). 1886s 1886s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1886s 1886s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1886s Converted 0 switches. 1886s 1886s 1886s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1886s Creating decoders for process `\m.$proc$yosys-always_display-star_en-1.v:18$1'. 1886s 1/1: $write$yosys-always_display-star_en-1.v:20$2_EN 1886s 1886s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1886s 1886s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1886s 1886s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1886s 1886s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-star_en-1.v:18$1'. 1886s Removing empty process `m.$proc$yosys-always_display-star_en-1.v:18$1'. 1886s Cleaned up 1 empty switch. 1886s 1886s 2.12. Executing OPT_EXPR pass (perform const folding). 1886s Optimizing module m. 1886s 1886s 3. Executing OPT_EXPR pass (perform const folding). 1886s Optimizing module m. 1886s 1886s Removed 0 unused cells and 3 unused wires. 1886s 1886s -- Writing to `yosys-always_display-star_en-2.v' using backend `verilog' -- 1886s 1886s 4. Executing Verilog backend. 1886s 1886s 4.1. Executing BMUXMAP pass. 1886s 1886s 4.2. Executing DEMUXMAP pass. 1886s Dumping module `\m'. 1886s 1886s End of script. Logfile hash: 18895a2046, CPU: user 0.01s system 0.00s, MEM: 9.50 MB peak 1886s Yosys 0.33 (git sha1 2584903a060) 1886s Time spent: 38% 2x opt_expr (0 sec), 21% 1x clean (0 sec), ... 1886s + diff yosys-always_display-star_en-1.v yosys-always_display-star_en-2.v 1886s + test_roundtrip dec_unsigned -DBASE_DEC -DSIGN= 1886s + local subtest=dec_unsigned 1886s + shift 1886s + ../../yosys -p 'read_verilog -DBASE_DEC -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-dec_unsigned-1.v 1886s 1886s /----------------------------------------------------------------------------\ 1886s | | 1886s | yosys -- Yosys Open SYnthesis Suite | 1886s | | 1886s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1886s | | 1886s | Permission to use, copy, modify, and/or distribute this software for any | 1886s | purpose with or without fee is hereby granted, provided that the above | 1886s | copyright notice and this permission notice appear in all copies. | 1886s | | 1886s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1886s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1886s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1886s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1886s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1886s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1886s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1886s | | 1886s \----------------------------------------------------------------------------/ 1886s 1886s Yosys 0.33 (git sha1 2584903a060) 1886s 1886s 1886s -- Running command `read_verilog -DBASE_DEC -DSIGN= roundtrip.v; proc; clean' -- 1886s 1886s 1. Executing Verilog-2005 frontend: roundtrip.v 1886s Parsing Verilog input from `roundtrip.v' to AST representation. 1886s Generating RTLIL representation for module `\m'. 1886s Successfully finished Verilog frontend. 1886s 1886s 2. Executing PROC pass (convert processes to netlists). 1886s 1886s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Cleaned up 0 empty switches. 1886s 1886s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1886s Removed a total of 0 dead cases. 1886s 1886s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1886s Removed 1 redundant assignment. 1886s Promoted 1 assignment to connection. 1886s 1886s 2.4. Executing PROC_INIT pass (extract init attributes). 1886s 1886s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1886s 1886s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1886s Converted 0 switches. 1886s 1886s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1886s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 1886s 1886s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1886s 1886s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1886s 1886s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1886s 1886s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Removing empty process `m.$proc$roundtrip.v:3$1'. 1886s Cleaned up 0 empty switches. 1886s 1886s 2.12. Executing OPT_EXPR pass (perform const folding). 1886s Optimizing module m. 1886s Removed 0 unused cells and 1 unused wires. 1886s 1886s -- Writing to `yosys-roundtrip-dec_unsigned-1.v' using backend `verilog' -- 1886s 1886s 3. Executing Verilog backend. 1886s 1886s 3.1. Executing BMUXMAP pass. 1886s 1886s 3.2. Executing DEMUXMAP pass. 1886s Dumping module `\m'. 1886s 1886s End of script. Logfile hash: bfb187b86d, CPU: user 0.01s system 0.00s, MEM: 9.50 MB peak 1886s Yosys 0.33 (git sha1 2584903a060) 1886s Time spent: 29% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ... 1886s 1886s /----------------------------------------------------------------------------\ 1886s | | 1886s | yosys -- Yosys Open SYnthesis Suite | 1886s | | 1886s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1886s | | 1886s | Permission to use, copy, modify, and/or distribute this software for any | 1886s | purpose with or without fee is hereby granted, provided that the above | 1886s | copyright notice and this permission notice appear in all copies. | 1886s | | 1886s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1886s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1886s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1886s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1886s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1886s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1886s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1886s | | 1886s \----------------------------------------------------------------------------/ 1886s 1886s Yosys 0.33 (git sha1 2584903a060) 1886s 1886s 1886s -- Running command `read_verilog yosys-roundtrip-dec_unsigned-1.v; proc; clean' -- 1886s 1886s 1. Executing Verilog-2005 frontend: yosys-roundtrip-dec_unsigned-1.v 1886s Parsing Verilog input from `yosys-roundtrip-dec_unsigned-1.v' to AST representation. 1886s Generating RTLIL representation for module `\m'. 1886s Successfully finished Verilog frontend. 1886s 1886s 2. Executing PROC pass (convert processes to netlists). 1886s 1886s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'. 1886s Cleaned up 1 empty switch. 1886s 1886s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1886s Removed a total of 0 dead cases. 1886s 1886s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1886s Removed 1 redundant assignment. 1886s Promoted 1 assignment to connection. 1886s 1886s 2.4. Executing PROC_INIT pass (extract init attributes). 1886s 1886s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1886s 1886s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1886s Converted 0 switches. 1886s 1886s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1886s Creating decoders for process `\m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'. 1886s 1886s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1886s 1886s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1886s 1886s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1886s 1886s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Removing empty process `m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'. 1886s Cleaned up 0 empty switches. 1886s 1886s 2.12. Executing OPT_EXPR pass (perform const folding). 1886s Optimizing module m. 1886s Removed 0 unused cells and 1 unused wires. 1886s 1886s -- Writing to `yosys-roundtrip-dec_unsigned-2.v' using backend `verilog' -- 1886s 1886s 3. Executing Verilog backend. 1886s 1886s 3.1. Executing BMUXMAP pass. 1886s 1886s 3.2. Executing DEMUXMAP pass. 1886s Dumping module `\m'. 1886s 1886s End of script. Logfile hash: 4be9539e85, CPU: user 0.01s system 0.00s, MEM: 9.50 MB peak 1886s Yosys 0.33 (git sha1 2584903a060) 1886s Time spent: 28% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 1886s + ../../yosys -p 'read_verilog yosys-roundtrip-dec_unsigned-1.v; proc; clean' -o yosys-roundtrip-dec_unsigned-2.v 1886s + diff yosys-roundtrip-dec_unsigned-1.v yosys-roundtrip-dec_unsigned-2.v 1886s + iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned roundtrip.v roundtrip_tb.v 1886s + ./iverilog-roundtrip-dec_unsigned 1886s + iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned-1 yosys-roundtrip-dec_unsigned-1.v roundtrip_tb.v 1886s + ./iverilog-roundtrip-dec_unsigned-1 1886s + iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned-2 yosys-roundtrip-dec_unsigned-2.v roundtrip_tb.v 1886s + ./iverilog-roundtrip-dec_unsigned-1 1886s + diff iverilog-roundtrip-dec_unsigned.log iverilog-roundtrip-dec_unsigned-1.log 1886s 1886s /----------------------------------------------------------------------------\ 1886s | | 1886s | yosys -- Yosys Open SYnthesis Suite | 1886s | | 1886s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1886s | | 1886s | Permission to use, copy, modify, and/or distribute this software for any | 1886s | purpose with or without fee is hereby granted, provided that the above | 1886s | copyright notice and this permission notice appear in all copies. | 1886s | | 1886s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1886s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1886s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1886s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1886s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1886s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1886s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1886s | | 1886s \----------------------------------------------------------------------------/ 1886s 1886s Yosys 0.33 (git sha1 2584903a060) 1886s 1886s 1886s -- Running command `read_verilog -DBASE_DEC -DSIGN=signed roundtrip.v; proc; clean' -- 1886s 1886s 1. Executing Verilog-2005 frontend: roundtrip.v 1886s Parsing Verilog input from `roundtrip.v' to AST representation. 1886s Generating RTLIL representation for module `\m'. 1886s Successfully finished Verilog frontend. 1886s 1886s 2. Executing PROC pass (convert processes to netlists). 1886s 1886s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Cleaned up 0 empty switches. 1886s 1886s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1886s Removed a total of 0 dead cases. 1886s 1886s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1886s Removed 1 redundant assignment. 1886s Promoted 1 assignment to connection. 1886s 1886s 2.4. Executing PROC_INIT pass (extract init attributes). 1886s 1886s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1886s 1886s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1886s Converted 0 switches. 1886s 1886s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1886s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 1886s 1886s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1886s 1886s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1886s 1886s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1886s 1886s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Removing empty process `m.$proc$roundtrip.v:3$1'. 1886s Cleaned up 0 empty switches. 1886s 1886s 2.12. Executing OPT_EXPR pass (perform const folding). 1886s Optimizing module m. 1886s Removed 0 unused cells and 1 unused wires. 1886s 1886s -- Writing to `yosys-roundtrip-dec_signed-1.v' using backend `verilog' -- 1886s 1886s 3. Executing Verilog backend. 1886s 1886s 3.1. Executing BMUXMAP pass. 1886s 1886s 3.2. Executing DEMUXMAP pass. 1886s Dumping module `\m'. 1886s 1886s End of script. Logfile hash: bbdfa5ca92, CPU: user 0.01s system 0.00s, MEM: 9.50 MB peak 1886s Yosys 0.33 (git sha1 2584903a060) 1886s Time spent: 28% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 1886s + diff iverilog-roundtrip-dec_unsigned-1.log iverilog-roundtrip-dec_unsigned-2.log 1886s + test_roundtrip dec_signed -DBASE_DEC -DSIGN=signed 1886s + local subtest=dec_signed 1886s + shift 1886s + ../../yosys -p 'read_verilog -DBASE_DEC -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-dec_signed-1.v 1886s + ../../yosys -p 'read_verilog yosys-roundtrip-dec_signed-1.v; proc; clean' -o yosys-roundtrip-dec_signed-2.v 1886s 1886s /----------------------------------------------------------------------------\ 1886s | | 1886s | yosys -- Yosys Open SYnthesis Suite | 1886s | | 1886s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1886s | | 1886s | Permission to use, copy, modify, and/or distribute this software for any | 1886s | purpose with or without fee is hereby granted, provided that the above | 1886s | copyright notice and this permission notice appear in all copies. | 1886s | | 1886s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1886s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1886s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1886s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1886s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1886s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1886s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1886s | | 1886s \----------------------------------------------------------------------------/ 1886s 1886s Yosys 0.33 (git sha1 2584903a060) 1886s 1886s 1886s -- Running command `read_verilog yosys-roundtrip-dec_signed-1.v; proc; clean' -- 1886s 1886s 1. Executing Verilog-2005 frontend: yosys-roundtrip-dec_signed-1.v 1886s Parsing Verilog input from `yosys-roundtrip-dec_signed-1.v' to AST representation. 1886s Generating RTLIL representation for module `\m'. 1886s Successfully finished Verilog frontend. 1886s 1886s 2. Executing PROC pass (convert processes to netlists). 1886s 1886s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'. 1886s Cleaned up 1 empty switch. 1886s 1886s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1886s Removed a total of 0 dead cases. 1886s 1886s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1886s Removed 1 redundant assignment. 1886s Promoted 1 assignment to connection. 1886s 1886s 2.4. Executing PROC_INIT pass (extract init attributes). 1886s 1886s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1886s 1886s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1886s Converted 0 switches. 1886s 1886s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1886s Creating decoders for process `\m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'. 1886s 1886s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1886s 1886s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1886s 1886s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1886s 1886s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Removing empty process `m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'. 1886s Cleaned up 0 empty switches. 1886s 1886s 2.12. Executing OPT_EXPR pass (perform const folding). 1886s Optimizing module m. 1886s Removed 0 unused cells and 1 unused wires. 1886s 1886s -- Writing to `yosys-roundtrip-dec_signed-2.v' using backend `verilog' -- 1886s 1886s 3. Executing Verilog backend. 1886s 1886s 3.1. Executing BMUXMAP pass. 1886s 1886s 3.2. Executing DEMUXMAP pass. 1886s Dumping module `\m'. 1886s 1886s End of script. Logfile hash: b233de92a6, CPU: user 0.01s system 0.00s, MEM: 9.50 MB peak 1886s Yosys 0.33 (git sha1 2584903a060) 1886s Time spent: 28% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 1886s + diff yosys-roundtrip-dec_signed-1.v yosys-roundtrip-dec_signed-2.v 1886s + iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed roundtrip.v roundtrip_tb.v 1886s + ./iverilog-roundtrip-dec_signed 1886s + iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed-1 yosys-roundtrip-dec_signed-1.v roundtrip_tb.v 1886s + ./iverilog-roundtrip-dec_signed-1 1886s + iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed-2 yosys-roundtrip-dec_signed-2.v roundtrip_tb.v 1886s + ./iverilog-roundtrip-dec_signed-1 1886s + diff iverilog-roundtrip-dec_signed.log iverilog-roundtrip-dec_signed-1.log 1886s + diff iverilog-roundtrip-dec_signed-1.log iverilog-roundtrip-dec_signed-2.log 1886s + test_roundtrip hex_unsigned -DBASE_HEX -DSIGN= 1886s + local subtest=hex_unsigned 1886s + shift 1886s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-hex_unsigned-1.v 1886s 1886s /----------------------------------------------------------------------------\ 1886s | | 1886s | yosys -- Yosys Open SYnthesis Suite | 1886s | | 1886s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1886s | | 1886s | Permission to use, copy, modify, and/or distribute this software for any | 1886s | purpose with or without fee is hereby granted, provided that the above | 1886s | copyright notice and this permission notice appear in all copies. | 1886s | | 1886s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1886s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1886s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1886s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1886s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1886s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1886s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1886s | | 1886s \----------------------------------------------------------------------------/ 1886s 1886s Yosys 0.33 (git sha1 2584903a060) 1886s 1886s 1886s -- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -- 1886s 1886s 1. Executing Verilog-2005 frontend: roundtrip.v 1886s Parsing Verilog input from `roundtrip.v' to AST representation. 1886s Generating RTLIL representation for module `\m'. 1886s Successfully finished Verilog frontend. 1886s 1886s 2. Executing PROC pass (convert processes to netlists). 1886s 1886s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Cleaned up 0 empty switches. 1886s 1886s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1886s Removed a total of 0 dead cases. 1886s 1886s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1886s Removed 1 redundant assignment. 1886s Promoted 1 assignment to connection. 1886s 1886s 2.4. Executing PROC_INIT pass (extract init attributes). 1886s 1886s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1886s 1886s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1886s Converted 0 switches. 1886s 1886s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1886s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 1886s 1886s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1886s 1886s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1886s 1886s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1886s 1886s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Removing empty process `m.$proc$roundtrip.v:3$1'. 1886s Cleaned up 0 empty switches. 1886s 1886s 2.12. Executing OPT_EXPR pass (perform const folding). 1886s Optimizing module m. 1886s Removed 0 unused cells and 1 unused wires. 1886s 1886s -- Writing to `yosys-roundtrip-hex_unsigned-1.v' using backend `verilog' -- 1886s 1886s 3. Executing Verilog backend. 1886s 1886s 3.1. Executing BMUXMAP pass. 1886s 1886s 3.2. Executing DEMUXMAP pass. 1886s Dumping module `\m'. 1886s 1886s End of script. Logfile hash: 2377f2e106, CPU: user 0.00s system 0.00s, MEM: 9.50 MB peak 1886s Yosys 0.33 (git sha1 2584903a060) 1886s Time spent: 29% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... 1886s 1886s /----------------------------------------------------------------------------\ 1886s | | 1886s | yosys -- Yosys Open SYnthesis Suite | 1886s | | 1886s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1886s | | 1886s | Permission to use, copy, modify, and/or distribute this software for any | 1886s | purpose with or without fee is hereby granted, provided that the above | 1886s | copyright notice and this permission notice appear in all copies. | 1886s | | 1886s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1886s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1886s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1886s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1886s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1886s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1886s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1886s | | 1886s \----------------------------------------------------------------------------/ 1886s 1886s Yosys 0.33 (git sha1 2584903a060) 1886s 1886s 1886s -- Running command `read_verilog yosys-roundtrip-hex_unsigned-1.v; proc; clean' -- 1886s 1886s 1. Executing Verilog-2005 frontend: yosys-roundtrip-hex_unsigned-1.v 1886s Parsing Verilog input from `yosys-roundtrip-hex_unsigned-1.v' to AST representation. 1886s Generating RTLIL representation for module `\m'. 1886s Successfully finished Verilog frontend. 1886s 1886s 2. Executing PROC pass (convert processes to netlists). 1886s 1886s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'. 1886s Cleaned up 1 empty switch. 1886s 1886s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1886s Removed a total of 0 dead cases. 1886s 1886s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1886s Removed 1 redundant assignment. 1886s Promoted 1 assignment to connection. 1886s 1886s 2.4. Executing PROC_INIT pass (extract init attributes). 1886s 1886s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1886s 1886s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1886s + ../../yosys -p 'read_verilog yosys-roundtrip-hex_unsigned-1.v; proc; clean' -o yosys-roundtrip-hex_unsigned-2.v 1886s + diff yosys-roundtrip-hex_unsigned-1.v yosys-roundtrip-hex_unsigned-2.v 1886s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned roundtrip.v roundtrip_tb.v 1886s + ./iverilog-roundtrip-hex_unsigned 1886s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned-1 yosys-roundtrip-hex_unsigned-1.v roundtrip_tb.v 1886s Converted 0 switches. 1886s 1886s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1886s Creating decoders for process `\m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'. 1886s 1886s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1886s 1886s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1886s 1886s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1886s 1886s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Removing empty process `m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'. 1886s Cleaned up 0 empty switches. 1886s 1886s 2.12. Executing OPT_EXPR pass (perform const folding). 1886s Optimizing module m. 1886s Removed 0 unused cells and 1 unused wires. 1886s 1886s -- Writing to `yosys-roundtrip-hex_unsigned-2.v' using backend `verilog' -- 1886s 1886s 3. Executing Verilog backend. 1886s 1886s 3.1. Executing BMUXMAP pass. 1886s 1886s 3.2. Executing DEMUXMAP pass. 1886s Dumping module `\m'. 1886s 1886s End of script. Logfile hash: 06bfea69c8, CPU: user 0.00s system 0.00s, MEM: 9.50 MB peak 1886s Yosys 0.33 (git sha1 2584903a060) 1886s Time spent: 29% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 1886s + ./iverilog-roundtrip-hex_unsigned-1 1886s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned-2 yosys-roundtrip-hex_unsigned-2.v roundtrip_tb.v 1886s + ./iverilog-roundtrip-hex_unsigned-1 1886s + diff iverilog-roundtrip-hex_unsigned.log iverilog-roundtrip-hex_unsigned-1.log 1886s + diff iverilog-roundtrip-hex_unsigned-1.log iverilog-roundtrip-hex_unsigned-2.log 1886s + test_roundtrip hex_signed -DBASE_HEX -DSIGN=signed 1886s + local subtest=hex_signed 1886s + shift 1886s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-hex_signed-1.v 1886s 1886s /----------------------------------------------------------------------------\ 1886s | | 1886s | yosys -- Yosys Open SYnthesis Suite | 1886s | | 1886s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1886s | | 1886s | Permission to use, copy, modify, and/or distribute this software for any | 1886s | purpose with or without fee is hereby granted, provided that the above | 1886s | copyright notice and this permission notice appear in all copies. | 1886s | | 1886s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1886s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1886s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1886s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1886s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1886s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1886s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1886s | | 1886s \----------------------------------------------------------------------------/ 1886s 1886s Yosys 0.33 (git sha1 2584903a060) 1886s 1886s 1886s -- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -- 1886s 1886s 1. Executing Verilog-2005 frontend: roundtrip.v 1886s Parsing Verilog input from `roundtrip.v' to AST representation. 1886s Generating RTLIL representation for module `\m'. 1886s Successfully finished Verilog frontend. 1886s 1886s 2. Executing PROC pass (convert processes to netlists). 1886s 1886s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Cleaned up 0 empty switches. 1886s 1886s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1886s Removed a total of 0 dead cases. 1886s 1886s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1886s Removed 1 redundant assignment. 1886s Promoted 1 assignment to connection. 1886s 1886s 2.4. Executing PROC_INIT pass (extract init attributes). 1886s 1886s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1886s 1886s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1886s Converted 0 switches. 1886s 1886s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1886s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 1886s 1886s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1886s 1886s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1886s 1886s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1886s 1886s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Removing empty process `m.$proc$roundtrip.v:3$1'. 1886s Cleaned up 0 empty switches. 1886s 1886s 2.12. Executing OPT_EXPR pass (perform const folding). 1886s Optimizing module m. 1886s Removed 0 unused cells and 1 unused wires. 1886s 1886s -- Writing to `yosys-roundtrip-hex_signed-1.v' using backend `verilog' -- 1886s 1886s 3. Executing Verilog backend. 1886s 1886s 3.1. Executing BMUXMAP pass. 1886s 1886s 3.2. Executing DEMUXMAP pass. 1886s Dumping module `\m'. 1886s 1886s End of script. Logfile hash: 824c3b1e65, CPU: user 0.01s system 0.00s, MEM: 9.50 MB peak 1886s Yosys 0.33 (git sha1 2584903a060) 1886s Time spent: 30% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 1886s + ../../yosys -p 'read_verilog yosys-roundtrip-hex_signed-1.v; proc; clean' -o yosys-roundtrip-hex_signed-2.v 1886s 1886s /----------------------------------------------------------------------------\ 1886s | | 1886s | yosys -- Yosys Open SYnthesis Suite | 1886s | | 1886s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1886s | | 1886s | Permission to use, copy, modify, and/or distribute this software for any | 1886s | purpose with or without fee is hereby granted, provided that the above | 1886s | copyright notice and this permission notice appear in all copies. | 1886s | | 1886s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1886s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1886s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1886s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1886s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1886s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1886s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1886s | | 1886s \----------------------------------------------------------------------------/ 1886s 1886s Yosys 0.33 (git sha1 2584903a060) 1886s 1886s 1886s -- Running command `read_verilog yosys-roundtrip-hex_signed-1.v; proc; clean' -- 1886s 1886s 1. Executing Verilog-2005 frontend: yosys-roundtrip-hex_signed-1.v 1886s Parsing Verilog input from `yosys-roundtrip-hex_signed-1.v' to AST representation. 1886s Generating RTLIL representation for module `\m'. 1886s Successfully finished Verilog frontend. 1886s 1886s 2. Executing PROC pass (convert processes to netlists). 1886s 1886s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'. 1886s Cleaned up 1 empty switch. 1886s 1886s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1886s Removed a total of 0 dead cases. 1886s 1886s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1886s Removed 1 redundant assignment. 1886s Promoted 1 assignment to connection. 1886s 1886s 2.4. Executing PROC_INIT pass (extract init attributes). 1886s 1886s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1886s 1886s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1886s Converted 0 switches. 1886s 1886s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1886s Creating decoders for process `\m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'. 1886s 1886s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1886s 1886s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1886s 1886s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1886s 1886s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Removing empty process `m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'. 1886s Cleaned up 0 empty switches. 1886s 1886s 2.12. Executing OPT_EXPR pass (perform const folding). 1886s Optimizing module m. 1886s Removed 0 unused cells and 1 unused wires. 1886s 1886s -- Writing to `yosys-roundtrip-hex_signed-2.v' using backend `verilog' -- 1886s 1886s 3. Executing Verilog backend. 1886s 1886s 3.1. Executing BMUXMAP pass. 1886s 1886s 3.2. Executing DEMUXMAP pass. 1886s Dumping module `\m'. 1886s 1886s End of script. Logfile hash: f18b3fa15b, CPU: user 0.01s system 0.00s, MEM: 9.50 MB peak 1886s Yosys 0.33 (git sha1 2584903a060) 1886s Time spent: 28% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... 1886s + diff yosys-roundtrip-hex_signed-1.v yosys-roundtrip-hex_signed-2.v 1886s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed roundtrip.v roundtrip_tb.v 1886s + ./iverilog-roundtrip-hex_signed 1886s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed-1 yosys-roundtrip-hex_signed-1.v roundtrip_tb.v 1886s + ./iverilog-roundtrip-hex_signed-1 1886s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed-2 yosys-roundtrip-hex_signed-2.v roundtrip_tb.v 1886s + ./iverilog-roundtrip-hex_signed-1 1886s + diff iverilog-roundtrip-hex_signed.log iverilog-roundtrip-hex_signed-1.log 1886s + diff iverilog-roundtrip-hex_signed-1.log iverilog-roundtrip-hex_signed-2.log 1886s + test_roundtrip oct_unsigned -DBASE_HEX -DSIGN= 1886s 1886s /----------------------------------------------------------------------------\ 1886s | | 1886s | yosys -- Yosys Open SYnthesis Suite | 1886s | | 1886s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1886s | | 1886s | Permission to use, copy, modify, and/or distribute this software for any | 1886s | purpose with or without fee is hereby granted, provided that the above | 1886s | copyright notice and this permission notice appear in all copies. | 1886s | | 1886s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1886s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1886s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1886s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1886s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1886s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1886s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1886s | | 1886s \----------------------------------------------------------------------------/ 1886s 1886s Yosys 0.33 (git sha1 2584903a060) 1886s 1886s 1886s -- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -- 1886s 1886s 1. Executing Verilog-2005 frontend: roundtrip.v 1886s + local subtest=oct_unsigned 1886s + shift 1886s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-oct_unsigned-1.v 1886s Parsing Verilog input from `roundtrip.v' to AST representation. 1886s Generating RTLIL representation for module `\m'. 1886s Successfully finished Verilog frontend. 1886s 1886s 2. Executing PROC pass (convert processes to netlists). 1886s 1886s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Cleaned up 0 empty switches. 1886s 1886s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1886s Removed a total of 0 dead cases. 1886s 1886s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1886s Removed 1 redundant assignment. 1886s Promoted 1 assignment to connection. 1886s 1886s 2.4. Executing PROC_INIT pass (extract init attributes). 1886s 1886s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1886s 1886s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1886s Converted 0 switches. 1886s 1886s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1886s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 1886s 1886s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1886s 1886s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1886s + ../../yosys -p 'read_verilog yosys-roundtrip-oct_unsigned-1.v; proc; clean' -o yosys-roundtrip-oct_unsigned-2.v 1886s 1886s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1886s 1886s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Removing empty process `m.$proc$roundtrip.v:3$1'. 1886s Cleaned up 0 empty switches. 1886s 1886s 2.12. Executing OPT_EXPR pass (perform const folding). 1886s Optimizing module m. 1886s Removed 0 unused cells and 1 unused wires. 1886s 1886s -- Writing to `yosys-roundtrip-oct_unsigned-1.v' using backend `verilog' -- 1886s 1886s 3. Executing Verilog backend. 1886s 1886s 3.1. Executing BMUXMAP pass. 1886s 1886s 3.2. Executing DEMUXMAP pass. 1886s Dumping module `\m'. 1886s 1886s End of script. Logfile hash: b768358a65, CPU: user 0.00s system 0.00s, MEM: 9.50 MB peak 1886s Yosys 0.33 (git sha1 2584903a060) 1886s Time spent: 28% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 1886s 1886s /----------------------------------------------------------------------------\ 1886s | | 1886s | yosys -- Yosys Open SYnthesis Suite | 1886s | | 1886s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1886s | | 1886s | Permission to use, copy, modify, and/or distribute this software for any | 1886s | purpose with or without fee is hereby granted, provided that the above | 1886s | copyright notice and this permission notice appear in all copies. | 1886s | | 1886s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1886s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1886s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1886s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1886s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1886s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1886s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1886s | | 1886s \----------------------------------------------------------------------------/ 1886s 1886s Yosys 0.33 (git sha1 2584903a060) 1886s 1886s 1886s -- Running command `read_verilog yosys-roundtrip-oct_unsigned-1.v; proc; clean' -- 1886s 1886s 1. Executing Verilog-2005 frontend: yosys-roundtrip-oct_unsigned-1.v 1886s Parsing Verilog input from `yosys-roundtrip-oct_unsigned-1.v' to AST representation. 1886s Generating RTLIL representation for module `\m'. 1886s Successfully finished Verilog frontend. 1886s 1886s 2. Executing PROC pass (convert processes to netlists). 1886s 1886s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'. 1886s Cleaned up 1 empty switch. 1886s 1886s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1886s Removed a total of 0 dead cases. 1886s 1886s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1886s Removed 1 redundant assignment. 1886s Promoted 1 assignment to connection. 1886s 1886s 2.4. Executing PROC_INIT pass (extract init attributes). 1886s 1886s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1886s 1886s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1886s Converted 0 switches. 1886s 1886s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1886s Creating decoders for process `\m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'. 1886s 1886s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1886s 1886s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1886s 1886s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1886s 1886s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Removing empty process `m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'. 1886s Cleaned up 0 empty switches. 1886s 1886s 2.12. Executing OPT_EXPR pass (perform const folding). 1886s Optimizing module m. 1886s Removed 0 unused cells and 1 unused wires. 1886s 1886s -- Writing to `yosys-roundtrip-oct_unsigned-2.v' using backend `verilog' -- 1886s 1886s 3. Executing Verilog backend. 1886s 1886s 3.1. Executing BMUXMAP pass. 1886s 1886s 3.2. Executing DEMUXMAP pass. 1886s Dumping module `\m'. 1886s 1886s End of script. Logfile hash: 762621cd95, CPU: user 0.00s system 0.00s, MEM: 9.50 MB peak 1886s Yosys 0.33 (git sha1 2584903a060) 1886s Time spent: 28% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 1886s + diff yosys-roundtrip-oct_unsigned-1.v yosys-roundtrip-oct_unsigned-2.v 1886s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned roundtrip.v roundtrip_tb.v 1886s + ./iverilog-roundtrip-oct_unsigned 1886s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned-1 yosys-roundtrip-oct_unsigned-1.v roundtrip_tb.v 1886s + ./iverilog-roundtrip-oct_unsigned-1 1886s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned-2 yosys-roundtrip-oct_unsigned-2.v roundtrip_tb.v 1886s + ./iverilog-roundtrip-oct_unsigned-1 1886s + diff iverilog-roundtrip-oct_unsigned.log iverilog-roundtrip-oct_unsigned-1.log 1886s + diff iverilog-roundtrip-oct_unsigned-1.log iverilog-roundtrip-oct_unsigned-2.log 1886s + test_roundtrip oct_signed -DBASE_HEX -DSIGN=signed 1886s + local subtest=oct_signed 1886s + shift 1886s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-oct_signed-1.v 1886s 1886s /----------------------------------------------------------------------------\ 1886s | | 1886s | yosys -- Yosys Open SYnthesis Suite | 1886s | | 1886s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1886s | | 1886s | Permission to use, copy, modify, and/or distribute this software for any | 1886s | purpose with or without fee is hereby granted, provided that the above | 1886s | copyright notice and this permission notice appear in all copies. | 1886s | | 1886s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1886s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1886s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1886s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1886s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1886s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1886s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1886s | | 1886s \----------------------------------------------------------------------------/ 1886s 1886s Yosys 0.33 (git sha1 2584903a060) 1886s 1886s 1886s -- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -- 1886s 1886s 1. Executing Verilog-2005 frontend: roundtrip.v 1886s Parsing Verilog input from `roundtrip.v' to AST representation. 1886s Generating RTLIL representation for module `\m'. 1886s Successfully finished Verilog frontend. 1886s 1886s 2. Executing PROC pass (convert processes to netlists). 1886s 1886s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Cleaned up 0 empty switches. 1886s 1886s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1886s Removed a total of 0 dead cases. 1886s 1886s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1886s Removed 1 redundant assignment. 1886s Promoted 1 assignment to connection. 1886s 1886s 2.4. Executing PROC_INIT pass (extract init attributes). 1886s 1886s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1886s 1886s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1886s Converted 0 switches. 1886s 1886s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1886s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 1886s 1886s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1886s 1886s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1886s 1886s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1886s 1886s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Removing empty process `m.$proc$roundtrip.v:3$1'. 1886s Cleaned up 0 empty switches. 1886s 1886s 2.12. Executing OPT_EXPR pass (perform const folding). 1886s Optimizing module m. 1886s Removed 0 unused cells and 1 unused wires. 1886s 1886s -- Writing to `yosys-roundtrip-oct_signed-1.v' using backend `verilog' -- 1886s 1886s 3. Executing Verilog backend. 1886s 1886s 3.1. Executing BMUXMAP pass. 1886s 1886s 3.2. Executing DEMUXMAP pass. 1886s Dumping module `\m'. 1886s 1886s End of script. Logfile hash: 7ec82b15e3, CPU: user 0.01s system 0.00s, MEM: 9.50 MB peak 1886s Yosys 0.33 (git sha1 2584903a060) 1886s Time spent: 29% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 1886s + ../../yosys -p 'read_verilog yosys-roundtrip-oct_signed-1.v; proc; clean' -o yosys-roundtrip-oct_signed-2.v 1886s 1886s /----------------------------------------------------------------------------\ 1886s | | 1886s | yosys -- Yosys Open SYnthesis Suite | 1886s | | 1886s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1886s | | 1886s | Permission to use, copy, modify, and/or distribute this software for any | 1886s | purpose with or without fee is hereby granted, provided that the above | 1886s | copyright notice and this permission notice appear in all copies. | 1886s | | 1886s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1886s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1886s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1886s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1886s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1886s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1886s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1886s | | 1886s \----------------------------------------------------------------------------/ 1886s 1886s Yosys 0.33 (git sha1 2584903a060) 1886s 1886s 1886s -- Running command `read_verilog yosys-roundtrip-oct_signed-1.v; proc; clean' -- 1886s 1886s 1. Executing Verilog-2005 frontend: yosys-roundtrip-oct_signed-1.v 1886s Parsing Verilog input from `yosys-roundtrip-oct_signed-1.v' to AST representation. 1886s Generating RTLIL representation for module `\m'. 1886s Successfully finished Verilog frontend. 1886s 1886s 2. Executing PROC pass (convert processes to netlists). 1886s 1886s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'. 1886s Cleaned up 1 empty switch. 1886s 1886s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1886s Removed a total of 0 dead cases. 1886s 1886s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1886s Removed 1 redundant assignment. 1886s Promoted 1 assignment to connection. 1886s 1886s 2.4. Executing PROC_INIT pass (extract init attributes). 1886s 1886s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1886s 1886s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1886s Converted 0 switches. 1886s 1886s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1886s Creating decoders for process `\m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'. 1886s 1886s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1886s 1886s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1886s 1886s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1886s 1886s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Removing empty process `m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'. 1886s Cleaned up 0 empty switches. 1886s 1886s 2.12. Executing OPT_EXPR pass (perform const folding). 1886s Optimizing module m. 1886s Removed 0 unused cells and 1 unused wires. 1886s 1886s -- Writing to `yosys-roundtrip-oct_signed-2.v' using backend `verilog' -- 1886s 1886s 3. Executing Verilog backend. 1886s 1886s 3.1. Executing BMUXMAP pass. 1886s 1886s 3.2. Executing DEMUXMAP pass. 1886s Dumping module `\m'. 1886s 1886s End of script. Logfile hash: a747b9bd4f, CPU: user 0.01s system 0.00s, MEM: 9.50 MB peak 1886s Yosys 0.33 (git sha1 2584903a060) 1886s Time spent: 29% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 1886s + diff yosys-roundtrip-oct_signed-1.v yosys-roundtrip-oct_signed-2.v 1886s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed roundtrip.v roundtrip_tb.v 1886s + ./iverilog-roundtrip-oct_signed 1886s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed-1 yosys-roundtrip-oct_signed-1.v roundtrip_tb.v 1886s + ./iverilog-roundtrip-oct_signed-1 1886s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed-2 yosys-roundtrip-oct_signed-2.v roundtrip_tb.v 1886s + ./iverilog-roundtrip-oct_signed-1 1886s + diff iverilog-roundtrip-oct_signed.log iverilog-roundtrip-oct_signed-1.log 1886s + diff iverilog-roundtrip-oct_signed-1.log iverilog-roundtrip-oct_signed-2.log 1886s + test_roundtrip bin_unsigned -DBASE_HEX -DSIGN= 1886s + local subtest=bin_unsigned 1886s + shift 1886s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-bin_unsigned-1.v 1886s 1886s /----------------------------------------------------------------------------\ 1886s | | 1886s | yosys -- Yosys Open SYnthesis Suite | 1886s | | 1886s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1886s | | 1886s | Permission to use, copy, modify, and/or distribute this software for any | 1886s | purpose with or without fee is hereby granted, provided that the above | 1886s | copyright notice and this permission notice appear in all copies. | 1886s | | 1886s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1886s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1886s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1886s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1886s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1886s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1886s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1886s | | 1886s \----------------------------------------------------------------------------/ 1886s 1886s Yosys 0.33 (git sha1 2584903a060) 1886s 1886s 1886s -- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -- 1886s 1886s 1. Executing Verilog-2005 frontend: roundtrip.v 1886s Parsing Verilog input from `roundtrip.v' to AST representation. 1886s Generating RTLIL representation for module `\m'. 1886s Successfully finished Verilog frontend. 1886s 1886s 2. Executing PROC pass (convert processes to netlists). 1886s 1886s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Cleaned up 0 empty switches. 1886s 1886s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1886s Removed a total of 0 dead cases. 1886s 1886s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1886s Removed 1 redundant assignment. 1886s Promoted 1 assignment to connection. 1886s 1886s 2.4. Executing PROC_INIT pass (extract init attributes). 1886s 1886s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1886s 1886s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1886s Converted 0 switches. 1886s 1886s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1886s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 1886s 1886s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1886s 1886s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1886s 1886s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1886s 1886s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Removing empty process `m.$proc$roundtrip.v:3$1'. 1886s Cleaned up 0 empty switches. 1886s 1886s 2.12. Executing OPT_EXPR pass (perform const folding). 1886s Optimizing module m. 1886s Removed 0 unused cells and 1 unused wires. 1886s 1886s -- Writing to `yosys-roundtrip-bin_unsigned-1.v' using backend `verilog' -- 1886s 1886s 3. Executing Verilog backend. 1886s 1886s 3.1. Executing BMUXMAP pass. 1886s + ../../yosys -p 'read_verilog yosys-roundtrip-bin_unsigned-1.v; proc; clean' -o yosys-roundtrip-bin_unsigned-2.v 1886s 1886s 3.2. Executing DEMUXMAP pass. 1886s Dumping module `\m'. 1886s 1886s End of script. Logfile hash: 270b564880, CPU: user 0.00s system 0.00s, MEM: 9.50 MB peak 1886s Yosys 0.33 (git sha1 2584903a060) 1886s Time spent: 29% 1x clean (0 sec), 23% 1x opt_expr (0 sec), ... 1886s 1886s /----------------------------------------------------------------------------\ 1886s | | 1886s | yosys -- Yosys Open SYnthesis Suite | 1886s | | 1886s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1886s | | 1886s | Permission to use, copy, modify, and/or distribute this software for any | 1886s | purpose with or without fee is hereby granted, provided that the above | 1886s | copyright notice and this permission notice appear in all copies. | 1886s | | 1886s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1886s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1886s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1886s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1886s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1886s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1886s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1886s | | 1886s \----------------------------------------------------------------------------/ 1886s 1886s Yosys 0.33 (git sha1 2584903a060) 1886s 1886s 1886s -- Running command `read_verilog yosys-roundtrip-bin_unsigned-1.v; proc; clean' -- 1886s 1886s 1. Executing Verilog-2005 frontend: yosys-roundtrip-bin_unsigned-1.v 1886s Parsing Verilog input from `yosys-roundtrip-bin_unsigned-1.v' to AST representation. 1886s Generating RTLIL representation for module `\m'. 1886s Successfully finished Verilog frontend. 1886s 1886s 2. Executing PROC pass (convert processes to netlists). 1886s 1886s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s + diff yosys-roundtrip-bin_unsigned-1.v yosys-roundtrip-bin_unsigned-2.v 1886s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned roundtrip.v roundtrip_tb.v 1886s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'. 1886s Cleaned up 1 empty switch. 1886s 1886s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1886s Removed a total of 0 dead cases. 1886s 1886s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1886s Removed 1 redundant assignment. 1886s Promoted 1 assignment to connection. 1886s 1886s 2.4. Executing PROC_INIT pass (extract init attributes). 1886s 1886s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1886s 1886s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1886s Converted 0 switches. 1886s 1886s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1886s Creating decoders for process `\m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'. 1886s 1886s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1886s 1886s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1886s 1886s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1886s 1886s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Removing empty process `m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'. 1886s Cleaned up 0 empty switches. 1886s 1886s 2.12. Executing OPT_EXPR pass (perform const folding). 1886s Optimizing module m. 1886s Removed 0 unused cells and 1 unused wires. 1886s 1886s -- Writing to `yosys-roundtrip-bin_unsigned-2.v' using backend `verilog' -- 1886s 1886s 3. Executing Verilog backend. 1886s 1886s 3.1. Executing BMUXMAP pass. 1886s 1886s 3.2. Executing DEMUXMAP pass. 1886s Dumping module `\m'. 1886s 1886s End of script. Logfile hash: dc9f56cb10, CPU: user 0.01s system 0.00s, MEM: 9.50 MB peak 1886s Yosys 0.33 (git sha1 2584903a060) 1886s Time spent: 29% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ... 1886s + ./iverilog-roundtrip-bin_unsigned 1886s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned-1 yosys-roundtrip-bin_unsigned-1.v roundtrip_tb.v 1886s + ./iverilog-roundtrip-bin_unsigned-1 1886s + iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned-2 yosys-roundtrip-bin_unsigned-2.v roundtrip_tb.v 1886s + ./iverilog-roundtrip-bin_unsigned-1 1886s + diff iverilog-roundtrip-bin_unsigned.log iverilog-roundtrip-bin_unsigned-1.log 1886s + diff iverilog-roundtrip-bin_unsigned-1.log iverilog-roundtrip-bin_unsigned-2.log 1886s + test_roundtrip bin_signed -DBASE_HEX -DSIGN=signed 1886s + local subtest=bin_signed 1886s + shift 1886s + ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-bin_signed-1.v 1886s 1886s /----------------------------------------------------------------------------\ 1886s | | 1886s | yosys -- Yosys Open SYnthesis Suite | 1886s | | 1886s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1886s | | 1886s | Permission to use, copy, modify, and/or distribute this software for any | 1886s | purpose with or without fee is hereby granted, provided that the above | 1886s | copyright notice and this permission notice appear in all copies. | 1886s | | 1886s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1886s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1886s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1886s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1886s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1886s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1886s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1886s | | 1886s \----------------------------------------------------------------------------/ 1886s 1886s Yosys 0.33 (git sha1 2584903a060) 1886s 1886s 1886s -- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -- 1886s 1886s 1. Executing Verilog-2005 frontend: roundtrip.v 1886s Parsing Verilog input from `roundtrip.v' to AST representation. 1886s Generating RTLIL representation for module `\m'. 1886s Successfully finished Verilog frontend. 1886s 1886s 2. Executing PROC pass (convert processes to netlists). 1886s 1886s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Cleaned up 0 empty switches. 1886s 1886s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1886s Removed a total of 0 dead cases. 1886s 1886s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1886s Removed 1 redundant assignment. 1886s Promoted 1 assignment to connection. 1886s 1886s 2.4. Executing PROC_INIT pass (extract init attributes). 1886s 1886s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1886s 1886s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1886s Converted 0 switches. 1886s 1886s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1886s Creating decoders for process `\m.$proc$roundtrip.v:3$1'. 1886s 1886s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1886s 1886s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1886s 1886s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1886s 1886s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Removing empty process `m.$proc$roundtrip.v:3$1'. 1886s Cleaned up 0 empty switches. 1886s 1886s 2.12. Executing OPT_EXPR pass (perform const folding). 1886s Optimizing module m. 1886s Removed 0 unused cells and 1 unused wires. 1886s 1886s -- Writing to `yosys-roundtrip-bin_signed-1.v' using backend `verilog' -- 1886s 1886s 3. Executing Verilog backend. 1886s 1886s 3.1. Executing BMUXMAP pass. 1886s 1886s 3.2. Executing DEMUXMAP pass. 1886s Dumping module `\m'. 1886s 1886s End of script. Logfile hash: 7709253822, CPU: user 0.00s system 0.00s, MEM: 9.50 MB peak 1886s Yosys 0.33 (git sha1 2584903a060) 1886s Time spent: 28% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 1886s + ../../yosys -p 'read_verilog yosys-roundtrip-bin_signed-1.v; proc; clean' -o yosys-roundtrip-bin_signed-2.v 1886s 1886s /----------------------------------------------------------------------------\ 1886s | | 1886s | yosys -- Yosys Open SYnthesis Suite | 1886s | | 1886s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1886s | | 1886s | Permission to use, copy, modify, and/or distribute this software for any | 1886s | purpose with or without fee is hereby granted, provided that the above | 1886s | copyright notice and this permission notice appear in all copies. | 1886s | | 1886s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1886s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1886s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1886s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1886s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1886s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1886s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1886s | | 1886s \----------------------------------------------------------------------------/ 1886s 1886s Yosys 0.33 (git sha1 2584903a060) 1886s 1886s 1886s -- Running command `read_verilog yosys-roundtrip-bin_signed-1.v; proc; clean' -- 1886s 1886s 1. Executing Verilog-2005 frontend: yosys-roundtrip-bin_signed-1.v 1886s Parsing Verilog input from `yosys-roundtrip-bin_signed-1.v' to AST representation. 1886s Generating RTLIL representation for module `\m'. 1886s Successfully finished Verilog frontend. 1886s 1886s 2. Executing PROC pass (convert processes to netlists). 1886s 1886s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'. 1886s Cleaned up 1 empty switch. 1886s 1886s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1886s Removed a total of 0 dead cases. 1886s 1886s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1886s Removed 1 redundant assignment. 1886s Promoted 1 assignment to connection. 1886s 1886s 2.4. Executing PROC_INIT pass (extract init attributes). 1886s 1886s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1886s 1886s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1886s Converted 0 switches. 1886s 1886s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1886s Creating decoders for process `\m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'. 1886s 1886s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1886s 1886s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1886s 1886s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1886s 1886s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Removing empty process `m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'. 1886s Cleaned up 0 empty switches. 1886s 1886s 2.12. Executing OPT_EXPR pass (perform const folding). 1886s Optimizing module m. 1886s Removed 0 unused cells and 1 unused wires. 1886s 1886s -- Writing to `yosys-roundtrip-bin_signed-2.v' using backend `verilog' -- 1886s 1886s 3. Executing Verilog backend. 1886s 1886s 3.1. Executing BMUXMAP pass. 1886s 1886s 3.2. Executing DEMUXMAP pass. 1886s Dumping module `\m'. 1886s 1886s End of script. Logfile hash: 7e2d8271c4, CPU: user 0.01s system 0.00s, MEM: 9.50 MB peak 1886s Yosys 0.33 (git sha1 2584903a060) 1886s Time spent: 28% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ... 1886s + diff yosys-roundtrip-bin_signed-1.v yosys-roundtrip-bin_signed-2.v 1886s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed roundtrip.v roundtrip_tb.v 1886s + ./iverilog-roundtrip-bin_signed 1886s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed-1 yosys-roundtrip-bin_signed-1.v roundtrip_tb.v 1886s + ./iverilog-roundtrip-bin_signed-1 1886s + iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed-2 yosys-roundtrip-bin_signed-2.v roundtrip_tb.v 1886s + ./iverilog-roundtrip-bin_signed-1 1886s + diff iverilog-roundtrip-bin_signed.log iverilog-roundtrip-bin_signed-1.log 1886s + diff iverilog-roundtrip-bin_signed-1.log iverilog-roundtrip-bin_signed-2.log 1886s + test_cxxrtl always_full 1886s + local subtest=always_full 1886s + shift 1886s + ../../yosys -p 'read_verilog always_full.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_full.cc' 1886s 1886s /----------------------------------------------------------------------------\ 1886s | | 1886s | yosys -- Yosys Open SYnthesis Suite | 1886s | | 1886s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1886s | | 1886s | Permission to use, copy, modify, and/or distribute this software for any | 1886s | purpose with or without fee is hereby granted, provided that the above | 1886s | copyright notice and this permission notice appear in all copies. | 1886s | | 1886s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1886s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1886s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1886s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1886s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1886s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1886s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1886s | | 1886s \----------------------------------------------------------------------------/ 1886s 1886s Yosys 0.33 (git sha1 2584903a060) 1886s 1886s 1886s -- Running command `read_verilog always_full.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_full.cc' -- 1886s 1886s 1. Executing Verilog-2005 frontend: always_full.v 1886s Parsing Verilog input from `always_full.v' to AST representation. 1886s Generating RTLIL representation for module `\always_full'. 1886s Successfully finished Verilog frontend. 1886s 1886s 2. Executing PROC pass (convert processes to netlists). 1886s 1886s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Cleaned up 0 empty switches. 1886s 1886s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1886s Removed a total of 0 dead cases. 1886s 1886s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1886s Removed 207 redundant assignments. 1886s Promoted 207 assignments to connections. 1886s 1886s 2.4. Executing PROC_INIT pass (extract init attributes). 1886s 1886s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1886s 1886s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1886s Converted 0 switches. 1886s 1886s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1886s Creating decoders for process `\always_full.$proc$always_full.v:3$1'. 1886s 1886s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1886s 1886s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1886s 1886s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1886s 1886s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Removing empty process `always_full.$proc$always_full.v:3$1'. 1886s Cleaned up 0 empty switches. 1886s 1886s 2.12. Executing OPT_EXPR pass (perform const folding). 1886s Optimizing module always_full. 1886s Removed 0 unused cells and 207 unused wires. 1886s 1886s 3. Executing CXXRTL backend. 1886s 1886s 3.1. Executing HIERARCHY pass (managing design hierarchy). 1886s 1886s 3.1.1. Finding top of design hierarchy.. 1886s root of 0 design levels: always_full 1886s Automatically selected always_full as design top module. 1886s 1886s 3.1.2. Analyzing design hierarchy.. 1886s Top module: \always_full 1886s 1886s 3.1.3. Analyzing design hierarchy.. 1886s Top module: \always_full 1886s Removed 0 unused modules. 1886s 1886s 3.2. Executing FLATTEN pass (flatten design). 1886s 1886s 3.3. Executing PROC pass (convert processes to netlists). 1886s 1886s 3.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Cleaned up 0 empty switches. 1886s 1886s 3.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1886s Removed a total of 0 dead cases. 1886s 1886s 3.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1886s Removed 0 redundant assignments. 1886s Promoted 0 assignments to connections. 1886s 1886s 3.3.4. Executing PROC_INIT pass (extract init attributes). 1886s 1886s 3.3.5. Executing PROC_ARST pass (detect async resets in processes). 1886s 1886s 3.3.6. Executing PROC_ROM pass (convert switches to ROMs). 1886s Converted 0 switches. 1886s 1886s 3.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1886s 1886s 3.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1886s 1886s 3.3.9. Executing PROC_DFF pass (convert process syncs to FFs). 1886s 1886s 3.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1886s 1886s 3.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1886s Cleaned up 0 empty switches. 1886s 1886s 3.3.12. Executing OPT_EXPR pass (perform const folding). 1886s Optimizing module always_full. 1886s 1886s 1886s 1886s End of script. Logfile hash: 6abd135c0a, CPU: user 0.03s system 0.01s, MEM: 10.75 MB peak 1886s Yosys 0.33 (git sha1 2584903a060) 1886s Time spent: 49% 2x write_cxxrtl (0 sec), 15% 2x read_verilog (0 sec), ... 1886s + gcc -std=c++11 -o yosys-always_full -I../.. always_full_tb.cc -lstdc++ 1888s + ./yosys-always_full 1888s + iverilog -o iverilog-always_full always_full.v always_full_tb.v 1888s + ./iverilog-always_full 1888s + grep -v '\$finish called' 1888s + diff iverilog-always_full.log yosys-always_full.log 1888s + test_cxxrtl always_comb 1888s 1888s /----------------------------------------------------------------------------\ 1888s | | 1888s | yosys -- Yosys Open SYnthesis Suite | 1888s | | 1888s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1888s | | 1888s | Permission to use, copy, modify, and/or distribute this software for any | 1888s | purpose with or without fee is hereby granted, provided that the above | 1888s | copyright notice and this permission notice appear in all copies. | 1888s | | 1888s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1888s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1888s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1888s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1888s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1888s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1888s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1888s | | 1888s \----------------------------------------------------------------------------/ 1888s 1888s Yosys 0.33 (git sha1 2584903a060) 1888s 1888s 1888s -- Running command `read_verilog always_comb.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_comb.cc' -- 1888s 1888s 1. Executing Verilog-2005 frontend: always_comb.v 1888s + local subtest=always_comb 1888s + shift 1888s + ../../yosys -p 'read_verilog always_comb.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_comb.cc' 1888s Parsing Verilog input from `always_comb.v' to AST representation. 1888s Generating RTLIL representation for module `\top'. 1888s Generating RTLIL representation for module `\sub'. 1888s Successfully finished Verilog frontend. 1888s 1888s 2. Executing PROC pass (convert processes to netlists). 1888s 1888s 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1888s Cleaned up 0 empty switches. 1888s 1888s 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1888s Removed a total of 0 dead cases. 1888s 1888s 2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1888s Removed 0 redundant assignments. 1888s Promoted 4 assignments to connections. 1888s 1888s 2.4. Executing PROC_INIT pass (extract init attributes). 1888s Found init rule in `\top.$proc$always_comb.v:3$13'. 1888s Set init value: \b = 1'0 1888s Found init rule in `\top.$proc$always_comb.v:2$12'. 1888s Set init value: \a = 1'0 1888s 1888s 2.5. Executing PROC_ARST pass (detect async resets in processes). 1888s 1888s 2.6. Executing PROC_ROM pass (convert switches to ROMs). 1888s Converted 0 switches. 1888s 1888s 1888s 2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1888s Creating decoders for process `\sub.$proc$always_comb.v:23$15'. 1888s 1/1: $display$always_comb.v:23$19_EN 1888s Creating decoders for process `\top.$proc$always_comb.v:3$13'. 1888s Creating decoders for process `\top.$proc$always_comb.v:2$12'. 1888s Creating decoders for process `\top.$proc$always_comb.v:8$1'. 1888s 1888s 2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1888s 1888s 2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1888s Creating register for signal `\top.\a' using process `\top.$proc$always_comb.v:8$1'. 1888s created $dff cell `$procdff$22' with positive edge clock. 1888s Creating register for signal `\top.\b' using process `\top.$proc$always_comb.v:8$1'. 1888s created $dff cell `$procdff$23' with positive edge clock. 1888s 1888s 2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1888s 1888s 2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1888s Found and cleaned up 1 empty switch in `\sub.$proc$always_comb.v:23$15'. 1888s Removing empty process `sub.$proc$always_comb.v:23$15'. 1888s Removing empty process `top.$proc$always_comb.v:3$13'. 1888s Removing empty process `top.$proc$always_comb.v:2$12'. 1888s Removing empty process `top.$proc$always_comb.v:8$1'. 1888s Cleaned up 1 empty switch. 1888s 1888s 2.12. Executing OPT_EXPR pass (perform const folding). 1888s Optimizing module sub. 1888s Optimizing module top. 1888s Removed 0 unused cells and 7 unused wires. 1888s 1888s 3. Executing CXXRTL backend. 1888s 1888s 3.1. Executing HIERARCHY pass (managing design hierarchy). 1888s 1888s 3.1.1. Finding top of design hierarchy.. 1888s root of 0 design levels: sub 1888s root of 1 design levels: top 1888s Automatically selected top as design top module. 1888s 1888s 3.1.2. Analyzing design hierarchy.. 1888s Top module: \top 1888s Used module: \sub 1888s 1888s 3.1.3. Analyzing design hierarchy.. 1888s Top module: \top 1888s Used module: \sub 1888s Removed 0 unused modules. 1888s 1888s 3.2. Executing FLATTEN pass (flatten design). 1888s Deleting now unused module sub. 1888s 1888s 1888s 3.3. Executing PROC pass (convert processes to netlists). 1888s 1888s 3.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1888s Cleaned up 0 empty switches. 1888s 1888s 3.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1888s Removed a total of 0 dead cases. 1888s 1888s 3.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1888s Removed 0 redundant assignments. 1888s Promoted 0 assignments to connections. 1888s 1888s 3.3.4. Executing PROC_INIT pass (extract init attributes). 1888s 1888s 3.3.5. Executing PROC_ARST pass (detect async resets in processes). 1888s 1888s 3.3.6. Executing PROC_ROM pass (convert switches to ROMs). 1888s Converted 0 switches. 1888s 1888s 3.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1888s 1888s 3.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1888s 1888s 3.3.9. Executing PROC_DFF pass (convert process syncs to FFs). 1888s 1888s 3.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1888s 1888s 3.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1888s Cleaned up 0 empty switches. 1888s 1888s 3.3.12. Executing OPT_EXPR pass (perform const folding). 1888s Optimizing module top. 1888s + gcc -std=c++11 -o yosys-always_comb -I../.. always_comb_tb.cc -lstdc++ 1888s 1888s 1888s 1888s End of script. Logfile hash: 03fe26efda, CPU: user 0.01s system 0.00s, MEM: 10.00 MB peak 1888s Yosys 0.33 (git sha1 2584903a060) 1888s Time spent: 29% 2x opt_expr (0 sec), 19% 1x clean (0 sec), ... 1889s + ./yosys-always_comb 1889s + iverilog -o iverilog-always_comb always_comb.v always_comb_tb.v 1889s + ./iverilog-always_comb 1889s + grep -v '\$finish called' 1889s + diff iverilog-always_comb.log yosys-always_comb.log 1889s + ../../yosys -p 'read_verilog always_full.v; prep; clean' -o yosys-always_full-1.v 1889s 1889s /----------------------------------------------------------------------------\ 1889s | | 1889s | yosys -- Yosys Open SYnthesis Suite | 1889s | | 1889s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1889s | | 1889s | Permission to use, copy, modify, and/or distribute this software for any | 1889s | purpose with or without fee is hereby granted, provided that the above | 1889s | copyright notice and this permission notice appear in all copies. | 1889s | | 1889s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1889s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1889s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1889s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1889s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1889s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1889s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1889s | | 1889s \----------------------------------------------------------------------------/ 1889s 1889s Yosys 0.33 (git sha1 2584903a060) 1889s 1889s 1889s -- Running command `read_verilog always_full.v; prep; clean' -- 1889s 1889s 1. Executing Verilog-2005 frontend: always_full.v 1889s Parsing Verilog input from `always_full.v' to AST representation. 1889s Generating RTLIL representation for module `\always_full'. 1889s Successfully finished Verilog frontend. 1889s 1889s 2. Executing PREP pass. 1889s 1889s 2.1. Executing HIERARCHY pass (managing design hierarchy). 1889s 1889s 2.2. Executing PROC pass (convert processes to netlists). 1889s 1889s 2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1889s Cleaned up 0 empty switches. 1889s 1889s 2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1889s Removed a total of 0 dead cases. 1889s 1889s 2.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1889s Removed 207 redundant assignments. 1889s Promoted 207 assignments to connections. 1889s 1889s 2.2.4. Executing PROC_INIT pass (extract init attributes). 1889s 1889s 2.2.5. Executing PROC_ARST pass (detect async resets in processes). 1889s 1889s 2.2.6. Executing PROC_ROM pass (convert switches to ROMs). 1889s Converted 0 switches. 1889s 1889s 2.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1889s Creating decoders for process `\always_full.$proc$always_full.v:3$1'. 1889s 1889s 2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1889s 1889s 2.2.9. Executing PROC_DFF pass (convert process syncs to FFs). 1889s 1889s 2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1889s 1889s 2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1889s Removing empty process `always_full.$proc$always_full.v:3$1'. 1889s Cleaned up 0 empty switches. 1889s 1889s 2.2.12. Executing OPT_EXPR pass (perform const folding). 1889s Optimizing module always_full. 1889s 1889s 2.3. Executing OPT_EXPR pass (perform const folding). 1889s Optimizing module always_full. 1889s 1889s 2.4. Executing OPT_CLEAN pass (remove unused cells and wires). 1889s Finding unused cells or wires in module \always_full.. 1889s Removed 0 unused cells and 207 unused wires. 1889s 1889s 1889s 2.5. Executing CHECK pass (checking for obvious problems). 1889s Checking module always_full... 1889s Found and reported 0 problems. 1889s 1889s 2.6. Executing OPT pass (performing simple optimizations). 1889s 1889s 2.6.1. Executing OPT_EXPR pass (perform const folding). 1889s Optimizing module always_full. 1889s 1889s 2.6.2. Executing OPT_MERGE pass (detect identical cells). 1889s Finding identical cells in module `\always_full'. 1889s Removed a total of 0 cells. 1889s 1889s 2.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 1889s Running muxtree optimizer on module \always_full.. 1889s Creating internal representation of mux trees. 1889s No muxes found in this module. 1889s Removed 0 multiplexer ports. 1889s 1889s 2.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 1889s Optimizing cells in module \always_full. 1889s Performed a total of 0 changes. 1889s 1889s 2.6.5. Executing OPT_MERGE pass (detect identical cells). 1889s Finding identical cells in module `\always_full'. 1889s Removed a total of 0 cells. 1889s 1889s 2.6.6. Executing OPT_CLEAN pass (remove unused cells and wires). 1889s Finding unused cells or wires in module \always_full.. 1889s 1889s 2.6.7. Executing OPT_EXPR pass (perform const folding). 1889s Optimizing module always_full. 1889s 1889s 2.6.8. Finished OPT passes. (There is nothing left to do.) 1889s 1889s 2.7. Executing WREDUCE pass (reducing word size of cells). 1889s 1889s 2.8. Executing OPT_CLEAN pass (remove unused cells and wires). 1889s Finding unused cells or wires in module \always_full.. 1889s 1889s 2.9. Executing MEMORY_COLLECT pass (generating $mem cells). 1889s 1889s 2.10. Executing OPT pass (performing simple optimizations). 1889s 1889s 2.10.1. Executing OPT_EXPR pass (perform const folding). 1889s Optimizing module always_full. 1889s 1889s 2.10.2. Executing OPT_MERGE pass (detect identical cells). 1889s Finding identical cells in module `\always_full'. 1889s Removed a total of 0 cells. 1889s 1889s 2.10.3. Executing OPT_CLEAN pass (remove unused cells and wires). 1889s Finding unused cells or wires in module \always_full.. 1889s 1889s 2.10.4. Finished fast OPT passes. 1889s 1889s 2.11. Printing statistics. 1889s + iverilog -o iverilog-always_full-1 yosys-always_full-1.v always_full_tb.v 1889s + ./iverilog-always_full-1 1889s + grep -v '\$finish called' 1889s 1889s === always_full === 1889s 1889s Number of wires: 1 1889s Number of wire bits: 1 1889s Number of public wires: 1 1889s Number of public wire bits: 1 1889s Number of memories: 0 1889s Number of memory bits: 0 1889s Number of processes: 0 1889s Number of cells: 207 1889s $print 207 1889s 1889s 2.12. Executing CHECK pass (checking for obvious problems). 1889s Checking module always_full... 1889s Found and reported 0 problems. 1889s 1889s -- Writing to `yosys-always_full-1.v' using backend `verilog' -- 1889s 1889s 3. Executing Verilog backend. 1889s 1889s 3.1. Executing BMUXMAP pass. 1889s 1889s 3.2. Executing DEMUXMAP pass. 1889s Dumping module `\always_full'. 1889s 1889s End of script. Logfile hash: cfd5b76053, CPU: user 0.06s system 0.00s, MEM: 10.88 MB peak 1889s Yosys 0.33 (git sha1 2584903a060) 1889s Time spent: 21% 5x opt_expr (0 sec), 20% 4x opt_clean (0 sec), ... 1889s + diff iverilog-always_full.log iverilog-always_full-1.log 1889s + ../../yosys -p 'read_verilog display_lm.v' 1889s + ../../yosys -p 'read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc' 1889s 1889s /----------------------------------------------------------------------------\ 1889s | | 1889s | yosys -- Yosys Open SYnthesis Suite | 1889s | | 1889s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 1889s | | 1889s | Permission to use, copy, modify, and/or distribute this software for any | 1889s | purpose with or without fee is hereby granted, provided that the above | 1889s | copyright notice and this permission notice appear in all copies. | 1889s | | 1889s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 1889s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 1889s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 1889s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 1889s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 1889s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 1889s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 1889s | | 1889s \----------------------------------------------------------------------------/ 1889s 1889s Yosys 0.33 (git sha1 2584903a060) 1889s 1889s 1889s -- Running command `read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc' -- 1889s 1889s 1. Executing Verilog-2005 frontend: display_lm.v 1889s Parsing Verilog input from `display_lm.v' to AST representation. 1889s Generating RTLIL representation for module `\top'. 1889s Generating RTLIL representation for module `\mid'. 1889s Generating RTLIL representation for module `\bot'. 1889s %l: \bot 1889s %m: \bot 1889s Successfully finished Verilog frontend. 1889s 1889s 2. Executing CXXRTL backend. 1889s 1889s 2.1. Executing HIERARCHY pass (managing design hierarchy). 1889s 1889s 2.1.1. Finding top of design hierarchy.. 1889s root of 0 design levels: bot 1889s root of 1 design levels: mid 1889s root of 2 design levels: top 1889s Automatically selected top as design top module. 1889s 1889s 2.1.2. Analyzing design hierarchy.. 1889s Top module: \top 1889s Used module: \mid 1889s Used module: \bot 1889s 1889s 2.1.3. Analyzing design hierarchy.. 1889s Top module: \top 1889s Used module: \mid 1889s Used module: \bot 1889s Removed 0 unused modules. 1889s 1889s 2.2. Executing FLATTEN pass (flatten design). 1889s Deleting now unused module bot. 1889s Deleting now unused module mid. 1889s + gcc -std=c++11 -o yosys-display_lm_cc -I../.. display_lm_tb.cc -lstdc++ 1889s 1889s 1889s 2.3. Executing PROC pass (convert processes to netlists). 1889s 1889s 2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1889s Removing empty process `top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:0$3'. 1889s Cleaned up 0 empty switches. 1889s 1889s 2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 1889s Removed a total of 0 dead cases. 1889s 1889s 2.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 1889s Removed 1 redundant assignment. 1889s Promoted 1 assignment to connection. 1889s 1889s 2.3.4. Executing PROC_INIT pass (extract init attributes). 1889s 1889s 2.3.5. Executing PROC_ARST pass (detect async resets in processes). 1889s 1889s 2.3.6. Executing PROC_ROM pass (convert switches to ROMs). 1889s Converted 0 switches. 1889s 1889s 2.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 1889s Creating decoders for process `\top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:11$1'. 1889s 1889s 2.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 1889s 1889s 2.3.9. Executing PROC_DFF pass (convert process syncs to FFs). 1889s 1889s 2.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 1889s 1889s 2.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 1889s Removing empty process `top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:11$1'. 1889s Cleaned up 0 empty switches. 1889s 1889s 2.3.12. Executing OPT_EXPR pass (perform const folding). 1889s Optimizing module top. 1889s 1889s 1889s 1889s End of script. Logfile hash: 1b689717a7, CPU: user 0.01s system 0.00s, MEM: 9.62 MB peak 1889s Yosys 0.33 (git sha1 2584903a060) 1889s Time spent: 35% 1x opt_expr (0 sec), 14% 2x read_verilog (0 sec), ... 1889s + ./yosys-display_lm_cc 1889s + for log in yosys-display_lm.log yosys-display_lm_cc.log 1889s + grep '^%l: \\bot$' yosys-display_lm.log 1889s + grep '^%m: \\bot$' yosys-display_lm.log 1889s + for log in yosys-display_lm.log yosys-display_lm_cc.log 1889s + grep '^%l: \\bot$' yosys-display_lm_cc.log 1889s + grep '^%m: \\bot$' yosys-display_lm_cc.log 1889s %l: \bot 1889s %m: \bot 1889s %l: \bot 1889s %m: \bot 1889s 1889s Passed "make test". 1889s 1890s autopkgtest [19:26:32]: test yosys-testsuite: -----------------------] 1891s yosys-testsuite PASS 1891s autopkgtest [19:26:33]: test yosys-testsuite: - - - - - - - - - - results - - - - - - - - - - 1891s autopkgtest [19:26:33]: test ice: preparing testbed 2025s autopkgtest [19:28:47]: testbed dpkg architecture: arm64 2025s autopkgtest [19:28:47]: testbed apt version: 2.7.12 2025s autopkgtest [19:28:47]: @@@@@@@@@@@@@@@@@@@@ test bed setup 2027s Get:1 http://ftpmaster.internal/ubuntu noble-proposed InRelease [117 kB] 2027s Get:2 http://ftpmaster.internal/ubuntu noble-proposed/restricted Sources [6540 B] 2027s Get:3 http://ftpmaster.internal/ubuntu noble-proposed/main Sources [493 kB] 2027s Get:4 http://ftpmaster.internal/ubuntu noble-proposed/multiverse Sources [52.7 kB] 2027s Get:5 http://ftpmaster.internal/ubuntu noble-proposed/universe Sources [3757 kB] 2028s Get:6 http://ftpmaster.internal/ubuntu noble-proposed/main arm64 Packages [659 kB] 2028s Get:7 http://ftpmaster.internal/ubuntu noble-proposed/main arm64 c-n-f Metadata [3144 B] 2028s Get:8 http://ftpmaster.internal/ubuntu noble-proposed/restricted arm64 Packages [33.6 kB] 2028s Get:9 http://ftpmaster.internal/ubuntu noble-proposed/restricted arm64 c-n-f Metadata [116 B] 2028s Get:10 http://ftpmaster.internal/ubuntu noble-proposed/universe arm64 Packages [4157 kB] 2028s Get:11 http://ftpmaster.internal/ubuntu noble-proposed/universe arm64 c-n-f Metadata [8528 B] 2028s Get:12 http://ftpmaster.internal/ubuntu noble-proposed/multiverse arm64 Packages [56.7 kB] 2028s Get:13 http://ftpmaster.internal/ubuntu noble-proposed/multiverse arm64 c-n-f Metadata [116 B] 2030s Fetched 9345 kB in 2s (4469 kB/s) 2030s Reading package lists... 2035s Reading package lists... 2035s Building dependency tree... 2035s Reading state information... 2035s Calculating upgrade... 2035s The following packages will be upgraded: 2035s readline-common ubuntu-minimal ubuntu-standard 2035s 3 upgraded, 0 newly installed, 0 to remove and 0 not upgraded. 2035s Need to get 77.9 kB of archives. 2035s After this operation, 0 B of additional disk space will be used. 2035s Get:1 http://ftpmaster.internal/ubuntu noble-proposed/main arm64 readline-common all 8.2-3.1 [56.4 kB] 2035s Get:2 http://ftpmaster.internal/ubuntu noble/main arm64 ubuntu-minimal arm64 1.536build1 [10.7 kB] 2035s Get:3 http://ftpmaster.internal/ubuntu noble/main arm64 ubuntu-standard arm64 1.536build1 [10.7 kB] 2035s Fetched 77.9 kB in 0s (159 kB/s) 2035s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 75850 files and directories currently installed.) 2035s Preparing to unpack .../readline-common_8.2-3.1_all.deb ... 2035s Unpacking readline-common (8.2-3.1) over (8.2-3) ... 2035s Preparing to unpack .../ubuntu-minimal_1.536build1_arm64.deb ... 2035s Unpacking ubuntu-minimal (1.536build1) over (1.536) ... 2035s Preparing to unpack .../ubuntu-standard_1.536build1_arm64.deb ... 2035s Unpacking ubuntu-standard (1.536build1) over (1.536) ... 2035s Setting up ubuntu-minimal (1.536build1) ... 2035s Setting up ubuntu-standard (1.536build1) ... 2035s Setting up readline-common (8.2-3.1) ... 2035s Processing triggers for install-info (7.1-3) ... 2035s Processing triggers for man-db (2.12.0-3) ... 2035s Reading package lists... 2035s Building dependency tree... 2035s Reading state information... 2036s 0 upgraded, 0 newly installed, 0 to remove and 0 not upgraded. 2036s Hit:1 http://ftpmaster.internal/ubuntu noble-proposed InRelease 2038s Hit:2 http://ftpmaster.internal/ubuntu noble InRelease 2038s Hit:3 http://ftpmaster.internal/ubuntu noble-updates InRelease 2038s Hit:4 http://ftpmaster.internal/ubuntu noble-security InRelease 2038s Reading package lists... 2038s Reading package lists... 2038s Building dependency tree... 2038s Reading state information... 2039s Calculating upgrade... 2039s 0 upgraded, 0 newly installed, 0 to remove and 0 not upgraded. 2039s Reading package lists... 2039s Building dependency tree... 2039s Reading state information... 2040s 0 upgraded, 0 newly installed, 0 to remove and 0 not upgraded. 2049s Reading package lists... 2049s Building dependency tree... 2049s Reading state information... 2050s Starting pkgProblemResolver with broken count: 0 2050s Starting 2 pkgProblemResolver with broken count: 0 2050s Done 2050s The following additional packages will be installed: 2050s libreadline8t64 libtcl8.6 python3-click python3-colorama yosys yosys-abc 2050s Suggested packages: 2050s tcl8.6 2050s Recommended packages: 2050s xdot 2051s The following packages will be REMOVED: 2051s libreadline8 2051s The following NEW packages will be installed: 2051s autopkgtest-satdep libreadline8t64 libtcl8.6 python3-click python3-colorama 2051s yosys yosys-abc 2051s 0 upgraded, 7 newly installed, 1 to remove and 0 not upgraded. 2051s Need to get 9935 kB/9936 kB of archives. 2051s After this operation, 32.4 MB of additional disk space will be used. 2051s Get:1 /tmp/autopkgtest.9XLSHY/2-autopkgtest-satdep.deb autopkgtest-satdep arm64 0 [700 B] 2051s Get:2 http://ftpmaster.internal/ubuntu noble-proposed/main arm64 libreadline8t64 arm64 8.2-3.1 [153 kB] 2051s Get:3 http://ftpmaster.internal/ubuntu noble/main arm64 libtcl8.6 arm64 8.6.13+dfsg-2 [980 kB] 2052s Get:4 http://ftpmaster.internal/ubuntu noble/main arm64 python3-colorama all 0.4.6-4 [32.1 kB] 2052s Get:5 http://ftpmaster.internal/ubuntu noble/main arm64 python3-click all 8.1.6-1 [79.0 kB] 2052s Get:6 http://ftpmaster.internal/ubuntu noble-proposed/universe arm64 yosys-abc arm64 0.33-5build1 [5594 kB] 2054s Get:7 http://ftpmaster.internal/ubuntu noble-proposed/universe arm64 yosys arm64 0.33-5build1 [3098 kB] 2057s Fetched 9935 kB in 6s (1694 kB/s) 2057s dpkg: libreadline8:arm64: dependency problems, but removing anyway as you requested: 2057s parted depends on libreadline8 (>= 6.0). 2057s libpython3.12-stdlib:arm64 depends on libreadline8 (>= 7.0~beta). 2057s libpython3.11-stdlib:arm64 depends on libreadline8 (>= 7.0~beta). 2057s gpgsm depends on libreadline8 (>= 6.0). 2057s gpgconf depends on libreadline8 (>= 6.0). 2057s gpg depends on libreadline8 (>= 6.0). 2057s gawk depends on libreadline8 (>= 6.0). 2057s fdisk depends on libreadline8 (>= 6.0). 2057s 2057s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 75850 files and directories currently installed.) 2057s Removing libreadline8:arm64 (8.2-3) ... 2057s Selecting previously unselected package libreadline8t64:arm64. 2057s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 75838 files and directories currently installed.) 2057s Preparing to unpack .../0-libreadline8t64_8.2-3.1_arm64.deb ... 2057s Adding 'diversion of /lib/aarch64-linux-gnu/libhistory.so.8 to /lib/aarch64-linux-gnu/libhistory.so.8.usr-is-merged by libreadline8t64' 2057s Adding 'diversion of /lib/aarch64-linux-gnu/libhistory.so.8.2 to /lib/aarch64-linux-gnu/libhistory.so.8.2.usr-is-merged by libreadline8t64' 2057s Adding 'diversion of /lib/aarch64-linux-gnu/libreadline.so.8 to /lib/aarch64-linux-gnu/libreadline.so.8.usr-is-merged by libreadline8t64' 2057s Adding 'diversion of /lib/aarch64-linux-gnu/libreadline.so.8.2 to /lib/aarch64-linux-gnu/libreadline.so.8.2.usr-is-merged by libreadline8t64' 2057s Unpacking libreadline8t64:arm64 (8.2-3.1) ... 2057s Selecting previously unselected package libtcl8.6:arm64. 2057s Preparing to unpack .../1-libtcl8.6_8.6.13+dfsg-2_arm64.deb ... 2057s Unpacking libtcl8.6:arm64 (8.6.13+dfsg-2) ... 2058s Selecting previously unselected package python3-colorama. 2058s Preparing to unpack .../2-python3-colorama_0.4.6-4_all.deb ... 2058s Unpacking python3-colorama (0.4.6-4) ... 2058s Selecting previously unselected package python3-click. 2058s Preparing to unpack .../3-python3-click_8.1.6-1_all.deb ... 2058s Unpacking python3-click (8.1.6-1) ... 2058s Selecting previously unselected package yosys-abc. 2058s Preparing to unpack .../4-yosys-abc_0.33-5build1_arm64.deb ... 2058s Unpacking yosys-abc (0.33-5build1) ... 2058s Selecting previously unselected package yosys. 2058s Preparing to unpack .../5-yosys_0.33-5build1_arm64.deb ... 2058s Unpacking yosys (0.33-5build1) ... 2058s Selecting previously unselected package autopkgtest-satdep. 2058s Preparing to unpack .../6-2-autopkgtest-satdep.deb ... 2058s Unpacking autopkgtest-satdep (0) ... 2058s Setting up python3-colorama (0.4.6-4) ... 2058s Setting up python3-click (8.1.6-1) ... 2058s Setting up libtcl8.6:arm64 (8.6.13+dfsg-2) ... 2058s Setting up libreadline8t64:arm64 (8.2-3.1) ... 2058s Setting up yosys-abc (0.33-5build1) ... 2058s Setting up yosys (0.33-5build1) ... 2058s Setting up autopkgtest-satdep (0) ... 2058s Processing triggers for man-db (2.12.0-3) ... 2058s Processing triggers for libc-bin (2.39-0ubuntu2) ... 2062s (Reading database ... 76422 files and directories currently installed.) 2062s Removing autopkgtest-satdep (0) ... 2115s autopkgtest [19:30:17]: test ice: [----------------------- 2116s 2116s /----------------------------------------------------------------------------\ 2116s | | 2116s | yosys -- Yosys Open SYnthesis Suite | 2116s | | 2116s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 2116s | | 2116s | Permission to use, copy, modify, and/or distribute this software for any | 2116s | purpose with or without fee is hereby granted, provided that the above | 2116s | copyright notice and this permission notice appear in all copies. | 2116s | | 2116s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 2116s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 2116s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 2116s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 2116s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 2116s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 2116s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 2116s | | 2116s \----------------------------------------------------------------------------/ 2116s 2116s Yosys 0.33 (git sha1 2584903a060) 2116s 2116s 2116s -- Running command `read_verilog debian/tests/design_ice.v; synth_ice40 -blif /tmp/autopkgtest.9XLSHY/autopkgtest_tmp/design_ice.blif' -- 2116s 2116s 1. Executing Verilog-2005 frontend: debian/tests/design_ice.v 2116s Parsing Verilog input from `debian/tests/design_ice.v' to AST representation. 2116s Generating RTLIL representation for module `\design_ice'. 2116s Successfully finished Verilog frontend. 2116s 2116s 2. Executing SYNTH_ICE40 pass. 2116s 2116s 2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v 2116s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation. 2116s Generating RTLIL representation for module `\SB_IO'. 2116s Generating RTLIL representation for module `\SB_GB_IO'. 2116s Generating RTLIL representation for module `\SB_GB'. 2116s Generating RTLIL representation for module `\SB_LUT4'. 2116s Generating RTLIL representation for module `\SB_CARRY'. 2116s Generating RTLIL representation for module `\SB_DFF'. 2116s Generating RTLIL representation for module `\SB_DFFE'. 2116s Generating RTLIL representation for module `\SB_DFFSR'. 2116s Generating RTLIL representation for module `\SB_DFFR'. 2116s Generating RTLIL representation for module `\SB_DFFSS'. 2116s Generating RTLIL representation for module `\SB_DFFS'. 2116s Generating RTLIL representation for module `\SB_DFFESR'. 2116s Generating RTLIL representation for module `\SB_DFFER'. 2116s Generating RTLIL representation for module `\SB_DFFESS'. 2116s Generating RTLIL representation for module `\SB_DFFES'. 2116s Generating RTLIL representation for module `\SB_DFFN'. 2116s Generating RTLIL representation for module `\SB_DFFNE'. 2116s Generating RTLIL representation for module `\SB_DFFNSR'. 2116s Generating RTLIL representation for module `\SB_DFFNR'. 2116s Generating RTLIL representation for module `\SB_DFFNSS'. 2116s Generating RTLIL representation for module `\SB_DFFNS'. 2116s Generating RTLIL representation for module `\SB_DFFNESR'. 2116s Generating RTLIL representation for module `\SB_DFFNER'. 2116s Generating RTLIL representation for module `\SB_DFFNESS'. 2116s Generating RTLIL representation for module `\SB_DFFNES'. 2116s Generating RTLIL representation for module `\SB_RAM40_4K'. 2116s Generating RTLIL representation for module `\SB_RAM40_4KNR'. 2116s Generating RTLIL representation for module `\SB_RAM40_4KNW'. 2116s Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. 2116s Generating RTLIL representation for module `\ICESTORM_LC'. 2116s Generating RTLIL representation for module `\SB_PLL40_CORE'. 2116s Generating RTLIL representation for module `\SB_PLL40_PAD'. 2116s Generating RTLIL representation for module `\SB_PLL40_2_PAD'. 2116s Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. 2116s Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. 2116s Generating RTLIL representation for module `\SB_WARMBOOT'. 2116s Generating RTLIL representation for module `\SB_SPRAM256KA'. 2116s Generating RTLIL representation for module `\SB_HFOSC'. 2116s Generating RTLIL representation for module `\SB_LFOSC'. 2116s Generating RTLIL representation for module `\SB_RGBA_DRV'. 2116s Generating RTLIL representation for module `\SB_LED_DRV_CUR'. 2116s Generating RTLIL representation for module `\SB_RGB_DRV'. 2116s Generating RTLIL representation for module `\SB_I2C'. 2116s Generating RTLIL representation for module `\SB_SPI'. 2116s Generating RTLIL representation for module `\SB_LEDDA_IP'. 2116s Generating RTLIL representation for module `\SB_FILTER_50NS'. 2116s Generating RTLIL representation for module `\SB_IO_I3C'. 2116s Generating RTLIL representation for module `\SB_IO_OD'. 2116s Generating RTLIL representation for module `\SB_MAC16'. 2116s Generating RTLIL representation for module `\ICESTORM_RAM'. 2116s Successfully finished Verilog frontend. 2116s 2116s 2.2. Executing HIERARCHY pass (managing design hierarchy). 2116s 2116s 2.2.1. Finding top of design hierarchy.. 2116s root of 0 design levels: design_ice 2116s Automatically selected design_ice as design top module. 2116s 2116s 2.2.2. Analyzing design hierarchy.. 2116s Top module: \design_ice 2116s 2116s 2.2.3. Analyzing design hierarchy.. 2116s Top module: \design_ice 2116s Removed 0 unused modules. 2116s 2116s 2.3. Executing PROC pass (convert processes to netlists). 2116s 2116s 2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2116s Cleaned up 0 empty switches. 2116s 2116s 2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 2116s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243 in module SB_DFFNES. 2116s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236 in module SB_DFFNESS. 2116s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232 in module SB_DFFNER. 2116s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225 in module SB_DFFNESR. 2116s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222 in module SB_DFFNS. 2116s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219 in module SB_DFFNSS. 2116s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216 in module SB_DFFNR. 2116s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213 in module SB_DFFNSR. 2116s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205 in module SB_DFFES. 2116s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198 in module SB_DFFESS. 2116s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194 in module SB_DFFER. 2116s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187 in module SB_DFFESR. 2116s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184 in module SB_DFFS. 2116s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181 in module SB_DFFSS. 2116s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178 in module SB_DFFR. 2116s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175 in module SB_DFFSR. 2116s Marked 1 switch rules as full_case in process $proc$debian/tests/design_ice.v:6$1 in module design_ice. 2116s Removed a total of 0 dead cases. 2116s 2116s 2.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 2116s Removed 8 redundant assignments. 2116s Promoted 23 assignments to connections. 2116s 2116s 2.3.4. Executing PROC_INIT pass (extract init attributes). 2116s Found init rule in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$246'. 2116s Set init value: \Q = 1'0 2116s Found init rule in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$242'. 2116s Set init value: \Q = 1'0 2116s Found init rule in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$235'. 2116s Set init value: \Q = 1'0 2116s Found init rule in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$231'. 2116s Set init value: \Q = 1'0 2116s Found init rule in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$224'. 2116s Set init value: \Q = 1'0 2116s Found init rule in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$221'. 2116s Set init value: \Q = 1'0 2116s Found init rule in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$218'. 2116s Set init value: \Q = 1'0 2116s Found init rule in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$215'. 2116s Set init value: \Q = 1'0 2116s Found init rule in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$212'. 2116s Set init value: \Q = 1'0 2116s Found init rule in `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 2116s Set init value: \Q = 1'0 2116s Found init rule in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 2116s Set init value: \Q = 1'0 2116s Found init rule in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$204'. 2116s Set init value: \Q = 1'0 2116s Found init rule in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$197'. 2116s Set init value: \Q = 1'0 2116s Found init rule in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$193'. 2116s Set init value: \Q = 1'0 2116s Found init rule in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$186'. 2116s Set init value: \Q = 1'0 2116s Found init rule in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$183'. 2116s Set init value: \Q = 1'0 2116s Found init rule in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$180'. 2116s Set init value: \Q = 1'0 2116s Found init rule in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$177'. 2116s Set init value: \Q = 1'0 2116s Found init rule in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$174'. 2116s Set init value: \Q = 1'0 2116s Found init rule in `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 2116s Set init value: \Q = 1'0 2116s Found init rule in `\design_ice.$proc$debian/tests/design_ice.v:3$2'. 2116s Set init value: \ready = 1'0 2116s 2116s 2.3.5. Executing PROC_ARST pass (detect async resets in processes). 2116s Found async reset \S in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'. 2116s Found async reset \R in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'. 2116s Found async reset \S in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222'. 2116s Found async reset \R in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216'. 2116s Found async reset \S in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'. 2116s Found async reset \R in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'. 2116s Found async reset \S in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184'. 2116s Found async reset \R in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178'. 2116s 2116s 2.3.6. Executing PROC_ROM pass (convert switches to ROMs). 2116s Converted 0 switches. 2116s 2116s 2116s 2.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 2116s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$246'. 2116s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'. 2116s 1/1: $0\Q[0:0] 2116s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$242'. 2116s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236'. 2116s 1/1: $0\Q[0:0] 2116s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$235'. 2116s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'. 2116s 1/1: $0\Q[0:0] 2116s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$231'. 2116s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225'. 2116s 1/1: $0\Q[0:0] 2116s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$224'. 2116s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222'. 2116s 1/1: $0\Q[0:0] 2116s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$221'. 2116s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219'. 2116s 1/1: $0\Q[0:0] 2116s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$218'. 2116s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216'. 2116s 1/1: $0\Q[0:0] 2116s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$215'. 2116s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213'. 2116s 1/1: $0\Q[0:0] 2116s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$212'. 2116s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$211'. 2116s 1/1: $0\Q[0:0] 2116s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 2116s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$209'. 2116s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 2116s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'. 2116s 1/1: $0\Q[0:0] 2116s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$204'. 2116s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198'. 2116s 1/1: $0\Q[0:0] 2116s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$197'. 2116s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'. 2116s 1/1: $0\Q[0:0] 2116s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$193'. 2116s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187'. 2116s 1/1: $0\Q[0:0] 2116s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$186'. 2116s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184'. 2116s 1/1: $0\Q[0:0] 2116s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$183'. 2116s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181'. 2116s 1/1: $0\Q[0:0] 2116s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$180'. 2116s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178'. 2116s 1/1: $0\Q[0:0] 2116s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$177'. 2116s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175'. 2116s 1/1: $0\Q[0:0] 2116s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$174'. 2116s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$173'. 2116s 1/1: $0\Q[0:0] 2116s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 2116s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$171'. 2116s Creating decoders for process `\design_ice.$proc$debian/tests/design_ice.v:3$2'. 2116s Creating decoders for process `\design_ice.$proc$debian/tests/design_ice.v:6$1'. 2116s 1/2: $0\value[0:0] 2116s 2/2: $0\ready[0:0] 2116s 2116s 2.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 2116s 2116s 2.3.9. Executing PROC_DFF pass (convert process syncs to FFs). 2116s Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'. 2116s created $adff cell `$procdff$433' with negative edge clock and positive level reset. 2116s Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236'. 2116s created $dff cell `$procdff$434' with negative edge clock. 2116s Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'. 2116s created $adff cell `$procdff$435' with negative edge clock and positive level reset. 2116s Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225'. 2116s created $dff cell `$procdff$436' with negative edge clock. 2116s Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222'. 2116s created $adff cell `$procdff$437' with negative edge clock and positive level reset. 2116s Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219'. 2116s created $dff cell `$procdff$438' with negative edge clock. 2116s Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216'. 2116s created $adff cell `$procdff$439' with negative edge clock and positive level reset. 2116s Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213'. 2116s created $dff cell `$procdff$440' with negative edge clock. 2116s Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$211'. 2116s created $dff cell `$procdff$441' with negative edge clock. 2116s Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$209'. 2116s created $dff cell `$procdff$442' with negative edge clock. 2116s Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'. 2116s created $adff cell `$procdff$443' with positive edge clock and positive level reset. 2116s Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198'. 2116s created $dff cell `$procdff$444' with positive edge clock. 2116s Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'. 2116s created $adff cell `$procdff$445' with positive edge clock and positive level reset. 2116s Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187'. 2116s created $dff cell `$procdff$446' with positive edge clock. 2116s Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184'. 2116s created $adff cell `$procdff$447' with positive edge clock and positive level reset. 2116s Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181'. 2116s created $dff cell `$procdff$448' with positive edge clock. 2116s Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178'. 2116s created $adff cell `$procdff$449' with positive edge clock and positive level reset. 2116s Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175'. 2116s created $dff cell `$procdff$450' with positive edge clock. 2116s Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$173'. 2116s created $dff cell `$procdff$451' with positive edge clock. 2116s Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$171'. 2116s created $dff cell `$procdff$452' with positive edge clock. 2116s Creating register for signal `\design_ice.\ready' using process `\design_ice.$proc$debian/tests/design_ice.v:6$1'. 2116s created $dff cell `$procdff$453' with positive edge clock. 2116s Creating register for signal `\design_ice.\value' using process `\design_ice.$proc$debian/tests/design_ice.v:6$1'. 2116s created $dff cell `$procdff$454' with positive edge clock. 2116s 2116s 2.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 2116s 2116s 2.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 2116s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$246'. 2116s Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'. 2116s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$243'. 2116s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$242'. 2116s Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236'. 2116s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$236'. 2116s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$235'. 2116s Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'. 2116s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$232'. 2116s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$231'. 2116s Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225'. 2116s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$225'. 2116s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$224'. 2116s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$222'. 2116s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$221'. 2116s Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219'. 2116s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$219'. 2116s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$218'. 2116s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$216'. 2116s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$215'. 2116s Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213'. 2116s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$213'. 2116s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$212'. 2116s Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$211'. 2116s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$211'. 2116s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 2116s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$209'. 2116s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 2116s Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'. 2116s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$205'. 2116s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$204'. 2116s Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198'. 2116s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$198'. 2116s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$197'. 2116s Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'. 2116s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$194'. 2116s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$193'. 2116s Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187'. 2116s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$187'. 2116s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$186'. 2116s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$184'. 2116s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$183'. 2116s Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181'. 2116s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$181'. 2116s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$180'. 2116s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$178'. 2116s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$177'. 2116s Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175'. 2116s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$175'. 2116s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$174'. 2116s Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$173'. 2116s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$173'. 2116s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 2116s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$171'. 2116s Removing empty process `design_ice.$proc$debian/tests/design_ice.v:3$2'. 2116s Found and cleaned up 1 empty switch in `\design_ice.$proc$debian/tests/design_ice.v:6$1'. 2116s Removing empty process `design_ice.$proc$debian/tests/design_ice.v:6$1'. 2116s Cleaned up 19 empty switches. 2116s 2116s 2.3.12. Executing OPT_EXPR pass (perform const folding). 2116s Optimizing module design_ice. 2116s 2116s 2.4. Executing FLATTEN pass (flatten design). 2116s 2116s 2.5. Executing TRIBUF pass. 2116s 2116s 2.6. Executing DEMINOUT pass (demote inout ports to input or output). 2116s 2116s 2.7. Executing OPT_EXPR pass (perform const folding). 2116s Optimizing module design_ice. 2116s 2116s 2.8. Executing OPT_CLEAN pass (remove unused cells and wires). 2116s Finding unused cells or wires in module \design_ice.. 2116s Removed 0 unused cells and 5 unused wires. 2116s 2116s 2116s 2.9. Executing CHECK pass (checking for obvious problems). 2116s Checking module design_ice... 2116s Found and reported 0 problems. 2116s 2116s 2.10. Executing OPT pass (performing simple optimizations). 2116s 2116s 2.10.1. Executing OPT_EXPR pass (perform const folding). 2116s Optimizing module design_ice. 2116s 2116s 2.10.2. Executing OPT_MERGE pass (detect identical cells). 2116s Finding identical cells in module `\design_ice'. 2116s Removed a total of 0 cells. 2116s 2116s 2.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 2116s Running muxtree optimizer on module \design_ice.. 2116s Creating internal representation of mux trees. 2116s Evaluating internal representation of mux trees. 2116s Replacing known input bits on port B of cell $procmux$431: \ready -> 1'1 2116s Analyzing evaluation results. 2116s Removed 0 multiplexer ports. 2116s 2116s 2116s 2.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 2116s Optimizing cells in module \design_ice. 2116s Optimizing cells in module \design_ice. 2116s Performed a total of 1 changes. 2116s 2116s 2.10.5. Executing OPT_MERGE pass (detect identical cells). 2116s Finding identical cells in module `\design_ice'. 2116s Removed a total of 0 cells. 2116s 2116s 2.10.6. Executing OPT_DFF pass (perform DFF optimizations). 2116s 2116s 2.10.7. Executing OPT_CLEAN pass (remove unused cells and wires). 2116s Finding unused cells or wires in module \design_ice.. 2116s Removed 0 unused cells and 1 unused wires. 2116s 2116s 2116s 2.10.8. Executing OPT_EXPR pass (perform const folding). 2116s Optimizing module design_ice. 2116s 2116s 2.10.9. Rerunning OPT passes. (Maybe there is more to do..) 2116s 2116s 2.10.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 2116s Running muxtree optimizer on module \design_ice.. 2116s Creating internal representation of mux trees. 2116s Evaluating internal representation of mux trees. 2116s Analyzing evaluation results. 2116s Removed 0 multiplexer ports. 2116s 2116s 2116s 2.10.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 2116s Optimizing cells in module \design_ice. 2116s Performed a total of 0 changes. 2116s 2116s 2.10.12. Executing OPT_MERGE pass (detect identical cells). 2116s Finding identical cells in module `\design_ice'. 2116s Removed a total of 0 cells. 2116s 2116s 2.10.13. Executing OPT_DFF pass (perform DFF optimizations). 2116s 2116s 2.10.14. Executing OPT_CLEAN pass (remove unused cells and wires). 2116s Finding unused cells or wires in module \design_ice.. 2116s 2116s 2.10.15. Executing OPT_EXPR pass (perform const folding). 2116s Optimizing module design_ice. 2116s 2116s 2.10.16. Finished OPT passes. (There is nothing left to do.) 2116s 2116s 2.11. Executing FSM pass (extract and optimize FSM). 2116s 2116s 2.11.1. Executing FSM_DETECT pass (finding FSMs in design). 2116s 2116s 2.11.2. Executing FSM_EXTRACT pass (extracting FSM from design). 2116s 2116s 2.11.3. Executing FSM_OPT pass (simple optimizations of FSMs). 2116s 2116s 2.11.4. Executing OPT_CLEAN pass (remove unused cells and wires). 2116s Finding unused cells or wires in module \design_ice.. 2116s 2116s 2.11.5. Executing FSM_OPT pass (simple optimizations of FSMs). 2116s 2116s 2.11.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 2116s 2116s 2.11.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 2116s 2116s 2.11.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 2116s 2116s 2.12. Executing OPT pass (performing simple optimizations). 2116s 2116s 2.12.1. Executing OPT_EXPR pass (perform const folding). 2116s Optimizing module design_ice. 2116s 2116s 2.12.2. Executing OPT_MERGE pass (detect identical cells). 2116s Finding identical cells in module `\design_ice'. 2116s Removed a total of 0 cells. 2116s 2116s 2.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 2116s Running muxtree optimizer on module \design_ice.. 2116s Creating internal representation of mux trees. 2116s Evaluating internal representation of mux trees. 2116s Analyzing evaluation results. 2116s Removed 0 multiplexer ports. 2116s 2116s 2116s 2.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 2116s Optimizing cells in module \design_ice. 2116s Performed a total of 0 changes. 2116s 2116s 2.12.5. Executing OPT_MERGE pass (detect identical cells). 2116s Finding identical cells in module `\design_ice'. 2116s Removed a total of 0 cells. 2116s 2116s 2.12.6. Executing OPT_DFF pass (perform DFF optimizations). 2116s Adding EN signal on $procdff$454 ($dff) from module design_ice (D = \I1, Q = \value). 2116s 2116s 2.12.7. Executing OPT_CLEAN pass (remove unused cells and wires). 2116s Finding unused cells or wires in module \design_ice.. 2116s Removed 1 unused cells and 1 unused wires. 2116s 2116s 2116s 2.12.8. Executing OPT_EXPR pass (perform const folding). 2116s Optimizing module design_ice. 2116s 2116s 2.12.9. Rerunning OPT passes. (Maybe there is more to do..) 2116s 2116s 2.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 2116s Running muxtree optimizer on module \design_ice.. 2116s Creating internal representation of mux trees. 2116s No muxes found in this module. 2116s Removed 0 multiplexer ports. 2116s 2116s 2.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 2116s Optimizing cells in module \design_ice. 2116s Performed a total of 0 changes. 2116s 2116s 2.12.12. Executing OPT_MERGE pass (detect identical cells). 2116s Finding identical cells in module `\design_ice'. 2116s Removed a total of 0 cells. 2116s 2116s 2.12.13. Executing OPT_DFF pass (perform DFF optimizations). 2116s 2116s 2.12.14. Executing OPT_CLEAN pass (remove unused cells and wires). 2116s Finding unused cells or wires in module \design_ice.. 2116s 2116s 2.12.15. Executing OPT_EXPR pass (perform const folding). 2116s Optimizing module design_ice. 2116s 2116s 2.12.16. Finished OPT passes. (There is nothing left to do.) 2116s 2116s 2.13. Executing WREDUCE pass (reducing word size of cells). 2116s 2116s 2.14. Executing PEEPOPT pass (run peephole optimizers). 2116s 2116s 2.15. Executing OPT_CLEAN pass (remove unused cells and wires). 2116s Finding unused cells or wires in module \design_ice.. 2116s 2116s 2.16. Executing SHARE pass (SAT-based resource sharing). 2116s 2116s 2.17. Executing TECHMAP pass (map to technology primitives). 2116s 2116s 2.17.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v 2116s Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation. 2116s Generating RTLIL representation for module `\_90_lut_cmp_'. 2116s Successfully finished Verilog frontend. 2116s 2116s 2.17.2. Continuing TECHMAP pass. 2116s No more expansions possible. 2116s 2116s 2116s 2.18. Executing OPT_EXPR pass (perform const folding). 2116s Optimizing module design_ice. 2116s 2116s 2.19. Executing OPT_CLEAN pass (remove unused cells and wires). 2116s Finding unused cells or wires in module \design_ice.. 2116s 2116s 2.20. Executing ALUMACC pass (create $alu and $macc cells). 2116s Extracting $alu and $macc cells in module design_ice: 2116s created 0 $alu and 0 $macc cells. 2116s 2116s 2.21. Executing OPT pass (performing simple optimizations). 2116s 2116s 2.21.1. Executing OPT_EXPR pass (perform const folding). 2116s Optimizing module design_ice. 2116s 2116s 2.21.2. Executing OPT_MERGE pass (detect identical cells). 2116s Finding identical cells in module `\design_ice'. 2116s Removed a total of 0 cells. 2116s 2116s 2.21.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 2116s Running muxtree optimizer on module \design_ice.. 2116s Creating internal representation of mux trees. 2116s No muxes found in this module. 2116s Removed 0 multiplexer ports. 2116s 2116s 2.21.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 2116s Optimizing cells in module \design_ice. 2116s Performed a total of 0 changes. 2116s 2116s 2.21.5. Executing OPT_MERGE pass (detect identical cells). 2116s Finding identical cells in module `\design_ice'. 2116s Removed a total of 0 cells. 2116s 2116s 2.21.6. Executing OPT_DFF pass (perform DFF optimizations). 2116s 2116s 2.21.7. Executing OPT_CLEAN pass (remove unused cells and wires). 2116s Finding unused cells or wires in module \design_ice.. 2116s 2116s 2.21.8. Executing OPT_EXPR pass (perform const folding). 2116s Optimizing module design_ice. 2116s 2116s 2.21.9. Finished OPT passes. (There is nothing left to do.) 2116s 2116s 2.22. Executing MEMORY pass. 2116s 2116s 2.22.1. Executing OPT_MEM pass (optimize memories). 2116s Performed a total of 0 transformations. 2116s 2116s 2.22.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). 2116s Performed a total of 0 transformations. 2116s 2116s 2.22.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 2116s 2116s 2.22.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 2116s 2116s 2.22.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 2116s 2116s 2.22.6. Executing OPT_CLEAN pass (remove unused cells and wires). 2116s Finding unused cells or wires in module \design_ice.. 2116s 2116s 2.22.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 2116s 2116s 2.22.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). 2116s Performed a total of 0 transformations. 2116s 2116s 2.22.9. Executing OPT_CLEAN pass (remove unused cells and wires). 2116s Finding unused cells or wires in module \design_ice.. 2116s 2116s 2.22.10. Executing MEMORY_COLLECT pass (generating $mem cells). 2116s 2116s 2.23. Executing OPT_CLEAN pass (remove unused cells and wires). 2116s Finding unused cells or wires in module \design_ice.. 2116s 2116s 2.24. Executing MEMORY_LIBMAP pass (mapping memories to cells). 2116s 2116s 2.25. Executing TECHMAP pass (map to technology primitives). 2116s 2116s 2.25.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v 2116s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation. 2116s Generating RTLIL representation for module `\$__ICE40_RAM4K_'. 2116s Successfully finished Verilog frontend. 2116s 2116s 2.25.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/spram_map.v 2116s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/spram_map.v' to AST representation. 2116s Generating RTLIL representation for module `\$__ICE40_SPRAM_'. 2116s Successfully finished Verilog frontend. 2116s 2116s 2.25.3. Continuing TECHMAP pass. 2116s No more expansions possible. 2116s 2116s 2116s 2.26. Executing ICE40_BRAMINIT pass. 2116s 2116s 2.27. Executing OPT pass (performing simple optimizations). 2116s 2116s 2.27.1. Executing OPT_EXPR pass (perform const folding). 2116s Optimizing module design_ice. 2116s 2116s 2.27.2. Executing OPT_MERGE pass (detect identical cells). 2116s Finding identical cells in module `\design_ice'. 2116s Removed a total of 0 cells. 2116s 2116s 2.27.3. Executing OPT_DFF pass (perform DFF optimizations). 2116s 2116s 2.27.4. Executing OPT_CLEAN pass (remove unused cells and wires). 2116s Finding unused cells or wires in module \design_ice.. 2116s 2116s 2.27.5. Finished fast OPT passes. 2116s 2116s 2.28. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 2116s 2116s 2.29. Executing OPT pass (performing simple optimizations). 2116s 2116s 2.29.1. Executing OPT_EXPR pass (perform const folding). 2116s Optimizing module design_ice. 2116s 2116s 2.29.2. Executing OPT_MERGE pass (detect identical cells). 2116s Finding identical cells in module `\design_ice'. 2116s Removed a total of 0 cells. 2116s 2116s 2.29.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 2116s Running muxtree optimizer on module \design_ice.. 2116s Creating internal representation of mux trees. 2116s No muxes found in this module. 2116s Removed 0 multiplexer ports. 2116s 2116s 2.29.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 2116s Optimizing cells in module \design_ice. 2116s Performed a total of 0 changes. 2116s 2116s 2.29.5. Executing OPT_MERGE pass (detect identical cells). 2116s Finding identical cells in module `\design_ice'. 2116s Removed a total of 0 cells. 2116s 2116s 2.29.6. Executing OPT_DFF pass (perform DFF optimizations). 2116s 2116s 2.29.7. Executing OPT_CLEAN pass (remove unused cells and wires). 2116s Finding unused cells or wires in module \design_ice.. 2116s 2116s 2.29.8. Executing OPT_EXPR pass (perform const folding). 2116s Optimizing module design_ice. 2116s 2116s 2.29.9. Finished OPT passes. (There is nothing left to do.) 2116s 2116s 2.30. Executing ICE40_WRAPCARRY pass (wrap carries). 2116s 2116s 2.31. Executing TECHMAP pass (map to technology primitives). 2116s 2116s 2.31.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v 2116s Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation. 2116s Generating RTLIL representation for module `\_90_simplemap_bool_ops'. 2116s Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. 2116s Generating RTLIL representation for module `\_90_simplemap_logic_ops'. 2116s Generating RTLIL representation for module `\_90_simplemap_compare_ops'. 2116s Generating RTLIL representation for module `\_90_simplemap_various'. 2116s Generating RTLIL representation for module `\_90_simplemap_registers'. 2116s Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. 2116s Generating RTLIL representation for module `\_90_shift_shiftx'. 2116s Generating RTLIL representation for module `\_90_fa'. 2116s Generating RTLIL representation for module `\_90_lcu'. 2116s Generating RTLIL representation for module `\_90_alu'. 2116s Generating RTLIL representation for module `\_90_macc'. 2116s Generating RTLIL representation for module `\_90_alumacc'. 2116s Generating RTLIL representation for module `\$__div_mod_u'. 2116s Generating RTLIL representation for module `\$__div_mod_trunc'. 2116s Generating RTLIL representation for module `\_90_div'. 2116s Generating RTLIL representation for module `\_90_mod'. 2116s Generating RTLIL representation for module `\$__div_mod_floor'. 2116s Generating RTLIL representation for module `\_90_divfloor'. 2116s Generating RTLIL representation for module `\_90_modfloor'. 2116s Generating RTLIL representation for module `\_90_pow'. 2116s Generating RTLIL representation for module `\_90_pmux'. 2116s Generating RTLIL representation for module `\_90_demux'. 2116s Generating RTLIL representation for module `\_90_lut'. 2116s Successfully finished Verilog frontend. 2116s 2116s 2.31.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v 2116s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation. 2116s Generating RTLIL representation for module `\_80_ice40_alu'. 2116s Successfully finished Verilog frontend. 2116s 2116s 2.31.3. Continuing TECHMAP pass. 2116s Using extmapper simplemap for cells of type $dffe. 2116s Using extmapper simplemap for cells of type $dff. 2116s No more expansions possible. 2116s 2116s 2116s 2.32. Executing OPT pass (performing simple optimizations). 2116s 2116s 2.32.1. Executing OPT_EXPR pass (perform const folding). 2116s Optimizing module design_ice. 2116s 2116s 2.32.2. Executing OPT_MERGE pass (detect identical cells). 2116s Finding identical cells in module `\design_ice'. 2116s Removed a total of 0 cells. 2116s 2116s 2.32.3. Executing OPT_DFF pass (perform DFF optimizations). 2116s 2116s 2.32.4. Executing OPT_CLEAN pass (remove unused cells and wires). 2116s Finding unused cells or wires in module \design_ice.. 2116s 2116s 2.32.5. Finished fast OPT passes. 2116s 2116s 2.33. Executing ICE40_OPT pass (performing simple optimizations). 2116s 2116s 2.33.1. Running ICE40 specific optimizations. 2116s 2116s 2.33.2. Executing OPT_EXPR pass (perform const folding). 2116s Optimizing module design_ice. 2116s 2116s 2.33.3. Executing OPT_MERGE pass (detect identical cells). 2116s Finding identical cells in module `\design_ice'. 2116s Removed a total of 0 cells. 2116s 2116s 2.33.4. Executing OPT_DFF pass (perform DFF optimizations). 2116s 2116s 2.33.5. Executing OPT_CLEAN pass (remove unused cells and wires). 2116s Finding unused cells or wires in module \design_ice.. 2116s 2116s 2.33.6. Finished OPT passes. (There is nothing left to do.) 2116s 2116s 2.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 2116s 2116s 2.35. Executing TECHMAP pass (map to technology primitives). 2116s 2116s 2.35.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 2116s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 2116s Generating RTLIL representation for module `\$_DFF_N_'. 2116s Generating RTLIL representation for module `\$_DFF_P_'. 2116s Generating RTLIL representation for module `\$_DFFE_NP_'. 2116s Generating RTLIL representation for module `\$_DFFE_PP_'. 2116s Generating RTLIL representation for module `\$_DFF_NP0_'. 2116s Generating RTLIL representation for module `\$_DFF_NP1_'. 2116s Generating RTLIL representation for module `\$_DFF_PP0_'. 2116s Generating RTLIL representation for module `\$_DFF_PP1_'. 2116s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 2116s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 2116s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 2116s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 2116s Generating RTLIL representation for module `\$_SDFF_NP0_'. 2116s Generating RTLIL representation for module `\$_SDFF_NP1_'. 2116s Generating RTLIL representation for module `\$_SDFF_PP0_'. 2116s Generating RTLIL representation for module `\$_SDFF_PP1_'. 2116s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 2116s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 2116s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 2116s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 2116s Successfully finished Verilog frontend. 2116s 2116s 2.35.2. Continuing TECHMAP pass. 2116s Using template \$_DFF_P_ for cells of type $_DFF_P_. 2116s Using template \$_DFFE_PP_ for cells of type $_DFFE_PP_. 2116s No more expansions possible. 2116s 2116s 2116s 2.36. Executing OPT_EXPR pass (perform const folding). 2116s Optimizing module design_ice. 2116s 2116s 2.37. Executing SIMPLEMAP pass (map simple cells to gate primitives). 2116s 2116s 2.38. Executing ICE40_OPT pass (performing simple optimizations). 2116s 2116s 2.38.1. Running ICE40 specific optimizations. 2116s 2116s 2.38.2. Executing OPT_EXPR pass (perform const folding). 2116s Optimizing module design_ice. 2116s 2116s 2.38.3. Executing OPT_MERGE pass (detect identical cells). 2116s Finding identical cells in module `\design_ice'. 2116s Removed a total of 0 cells. 2116s 2116s 2.38.4. Executing OPT_DFF pass (perform DFF optimizations). 2116s 2116s 2.38.5. Executing OPT_CLEAN pass (remove unused cells and wires). 2116s Finding unused cells or wires in module \design_ice.. 2116s Removed 0 unused cells and 9 unused wires. 2116s 2116s 2116s 2.38.6. Rerunning OPT passes. (Removed registers in this run.) 2116s 2116s 2.38.7. Running ICE40 specific optimizations. 2116s 2116s 2.38.8. Executing OPT_EXPR pass (perform const folding). 2116s Optimizing module design_ice. 2116s 2116s 2.38.9. Executing OPT_MERGE pass (detect identical cells). 2116s Finding identical cells in module `\design_ice'. 2116s Removed a total of 0 cells. 2116s 2116s 2.38.10. Executing OPT_DFF pass (perform DFF optimizations). 2116s 2116s 2.38.11. Executing OPT_CLEAN pass (remove unused cells and wires). 2116s Finding unused cells or wires in module \design_ice.. 2116s 2116s 2.38.12. Finished OPT passes. (There is nothing left to do.) 2116s 2116s 2.39. Executing TECHMAP pass (map to technology primitives). 2116s 2116s 2.39.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v 2116s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation. 2116s Generating RTLIL representation for module `\$_DLATCH_N_'. 2116s Generating RTLIL representation for module `\$_DLATCH_P_'. 2116s Successfully finished Verilog frontend. 2116s 2116s 2.39.2. Continuing TECHMAP pass. 2116s No more expansions possible. 2116s 2116s 2116s 2.40. Executing ABC pass (technology mapping using ABC). 2116s 2116s 2.40.1. Extracting gate netlist of module `\design_ice' to `/input.blif'.. 2116s Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs. 2116s Don't call ABC as there is nothing to map. 2116s Removing temp directory. 2116s 2116s 2.41. Executing ICE40_WRAPCARRY pass (wrap carries). 2116s 2116s 2.42. Executing TECHMAP pass (map to technology primitives). 2116s 2116s 2.42.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 2116s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 2116s Generating RTLIL representation for module `\$_DFF_N_'. 2116s Generating RTLIL representation for module `\$_DFF_P_'. 2116s Generating RTLIL representation for module `\$_DFFE_NP_'. 2116s Generating RTLIL representation for module `\$_DFFE_PP_'. 2116s Generating RTLIL representation for module `\$_DFF_NP0_'. 2116s Generating RTLIL representation for module `\$_DFF_NP1_'. 2116s Generating RTLIL representation for module `\$_DFF_PP0_'. 2116s Generating RTLIL representation for module `\$_DFF_PP1_'. 2116s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 2116s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 2116s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 2116s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 2116s Generating RTLIL representation for module `\$_SDFF_NP0_'. 2116s Generating RTLIL representation for module `\$_SDFF_NP1_'. 2116s Generating RTLIL representation for module `\$_SDFF_PP0_'. 2116s Generating RTLIL representation for module `\$_SDFF_PP1_'. 2116s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 2116s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 2116s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 2116s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 2116s Successfully finished Verilog frontend. 2116s 2116s 2.42.2. Continuing TECHMAP pass. 2116s No more expansions possible. 2116s 2116s 2116s 2.43. Executing OPT_LUT pass (optimize LUTs). 2116s Discovering LUTs. 2116s Number of LUTs: 0 2116s with \SB_CARRY (#0) 0 2116s with \SB_CARRY (#1) 0 2116s 2116s Eliminating LUTs. 2116s Number of LUTs: 0 2116s with \SB_CARRY (#0) 0 2116s with \SB_CARRY (#1) 0 2116s 2116s Combining LUTs. 2116s Number of LUTs: 0 2116s with \SB_CARRY (#0) 0 2116s with \SB_CARRY (#1) 0 2116s 2116s Eliminated 0 LUTs. 2116s Combined 0 LUTs. 2116s 2116s 2.44. Executing TECHMAP pass (map to technology primitives). 2116s 2116s 2.44.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v 2116s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation. 2116s Generating RTLIL representation for module `\$lut'. 2116s Successfully finished Verilog frontend. 2116s 2116s 2.44.2. Continuing TECHMAP pass. 2116s No more expansions possible. 2116s 2116s 2116s 2.45. Executing AUTONAME pass. 2116s Renamed 2 objects in module design_ice (2 iterations). 2116s 2116s 2116s 2.46. Executing HIERARCHY pass (managing design hierarchy). 2116s 2116s 2.46.1. Analyzing design hierarchy.. 2116s Top module: \design_ice 2116s 2116s 2.46.2. Analyzing design hierarchy.. 2116s Top module: \design_ice 2116s Removed 0 unused modules. 2116s 2116s 2.47. Printing statistics. 2116s 2116s === design_ice === 2116s 2116s Number of wires: 5 2116s Number of wire bits: 5 2116s Number of public wires: 5 2116s Number of public wire bits: 5 2116s Number of memories: 0 2116s Number of memory bits: 0 2116s Number of processes: 0 2116s Number of cells: 2 2116s SB_DFF 1 2116s SB_DFFE 1 2116s 2116s 2.48. Executing CHECK pass (checking for obvious problems). 2116s Checking module design_ice... 2116s Found and reported 0 problems. 2116s 2116s 2.49. Executing BLIF backend. 2116s 2116s End of script. Logfile hash: a59fdb3b14, CPU: user 0.66s system 0.02s, MEM: 18.88 MB peak 2116s Yosys 0.33 (git sha1 2584903a060) 2116s Time spent: 69% 13x read_verilog (0 sec), 8% 1x synth_ice40 (0 sec), ... 2117s autopkgtest [19:30:19]: test ice: -----------------------] 2118s ice PASS 2118s autopkgtest [19:30:20]: test ice: - - - - - - - - - - results - - - - - - - - - - 2119s autopkgtest [19:30:21]: test smtbc: preparing testbed 2123s Reading package lists... 2124s Building dependency tree... 2124s Reading state information... 2124s Starting pkgProblemResolver with broken count: 0 2124s Starting 2 pkgProblemResolver with broken count: 0 2124s Done 2126s The following NEW packages will be installed: 2126s autopkgtest-satdep 2126s 0 upgraded, 1 newly installed, 0 to remove and 0 not upgraded. 2126s Need to get 0 B/700 B of archives. 2126s After this operation, 0 B of additional disk space will be used. 2126s Get:1 /tmp/autopkgtest.9XLSHY/3-autopkgtest-satdep.deb autopkgtest-satdep arm64 0 [700 B] 2126s Selecting previously unselected package autopkgtest-satdep. 2126s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 76422 files and directories currently installed.) 2126s Preparing to unpack .../3-autopkgtest-satdep.deb ... 2126s Unpacking autopkgtest-satdep (0) ... 2126s Setting up autopkgtest-satdep (0) ... 2128s (Reading database ... 76422 files and directories currently installed.) 2128s Removing autopkgtest-satdep (0) ... 2130s autopkgtest [19:30:32]: test smtbc: [----------------------- 2131s autopkgtest [19:30:33]: test smtbc: -----------------------] 2131s autopkgtest [19:30:33]: test smtbc: - - - - - - - - - - results - - - - - - - - - - 2131s smtbc PASS 2132s autopkgtest [19:30:34]: @@@@@@@@@@@@@@@@@@@@ summary 2132s yosys-testsuite PASS 2132s ice PASS 2132s smtbc PASS 2159s Creating nova instance adt-noble-arm64-yosys-20240319-163541-juju-7f2275-prod-proposed-migration-environment-2 from image adt/ubuntu-noble-arm64-server-20240319.img (UUID bd25b89b-8264-4402-95d9-d9c88f21f275)... 2159s Creating nova instance adt-noble-arm64-yosys-20240319-163541-juju-7f2275-prod-proposed-migration-environment-2 from image adt/ubuntu-noble-arm64-server-20240319.img (UUID bd25b89b-8264-4402-95d9-d9c88f21f275)...