0s autopkgtest [12:25:49]: starting date and time: 2024-03-15 12:25:49+0000 0s autopkgtest [12:25:49]: git checkout: b506e79c ssh-setup/nova: fix ARCH having two lines of data 0s autopkgtest [12:25:49]: host juju-7f2275-prod-proposed-migration-environment-2; command line: /home/ubuntu/autopkgtest/runner/autopkgtest --output-dir /tmp/autopkgtest-work.1kx39mv0/out --timeout-copy=6000 --setup-commands /home/ubuntu/autopkgtest-cloud/worker-config-production/setup-canonical.sh --apt-pocket=proposed=src:nextpnr,src:db5.3,src:glib2.0,src:libpng1.6,src:mtdev,src:openssl,src:python3.12,src:qtbase-opensource-src,src:readline,src:wp2latex --apt-upgrade fpga-icestorm --timeout-short=300 --timeout-copy=20000 --timeout-build=20000 '--env=ADT_TEST_TRIGGERS=nextpnr/0.6-3build4 db5.3/5.3.28+dfsg2-5build1 glib2.0/2.79.3-3ubuntu5 libpng1.6/1.6.43-3 mtdev/1.1.6-1.1 openssl/3.0.13-0ubuntu1 python3.12/3.12.2-4build2 qtbase-opensource-src/5.15.12+dfsg-3ubuntu5 readline/8.2-3.1 wp2latex/4.4~ds-1build1' -- ssh -s /home/ubuntu/autopkgtest/ssh-setup/nova -- --flavor autopkgtest --security-groups autopkgtest-juju-7f2275-prod-proposed-migration-environment-2@bos03-arm64-19.secgroup --name adt-noble-arm64-fpga-icestorm-20240315-122548-juju-7f2275-prod-proposed-migration-environment-2 --image adt/ubuntu-noble-arm64-server --keyname testbed-juju-7f2275-prod-proposed-migration-environment-2 --net-id=net_prod-proposed-migration -e TERM=linux -e ''"'"'http_proxy=http://squid.internal:3128'"'"'' -e ''"'"'https_proxy=http://squid.internal:3128'"'"'' -e ''"'"'no_proxy=127.0.0.1,127.0.1.1,login.ubuntu.com,localhost,localdomain,novalocal,internal,archive.ubuntu.com,ports.ubuntu.com,security.ubuntu.com,ddebs.ubuntu.com,changelogs.ubuntu.com,launchpadlibrarian.net,launchpadcontent.net,launchpad.net,10.24.0.0/24,keystone.ps5.canonical.com,objectstorage.prodstack5.canonical.com'"'"'' --mirror=http://ftpmaster.internal/ubuntu/ 91s autopkgtest [12:27:20]: testbed dpkg architecture: arm64 92s autopkgtest [12:27:21]: testbed apt version: 2.7.12 92s autopkgtest [12:27:21]: @@@@@@@@@@@@@@@@@@@@ test bed setup 92s Get:1 http://ftpmaster.internal/ubuntu noble-proposed InRelease [117 kB] 92s Get:2 http://ftpmaster.internal/ubuntu noble-proposed/universe Sources [3614 kB] 93s Get:3 http://ftpmaster.internal/ubuntu noble-proposed/main Sources [453 kB] 93s Get:4 http://ftpmaster.internal/ubuntu noble-proposed/restricted Sources [4812 B] 93s Get:5 http://ftpmaster.internal/ubuntu noble-proposed/multiverse Sources [49.0 kB] 93s Get:6 http://ftpmaster.internal/ubuntu noble-proposed/main arm64 Packages [611 kB] 93s Get:7 http://ftpmaster.internal/ubuntu noble-proposed/main arm64 c-n-f Metadata [3144 B] 93s Get:8 http://ftpmaster.internal/ubuntu noble-proposed/restricted arm64 Packages [20.3 kB] 93s Get:9 http://ftpmaster.internal/ubuntu noble-proposed/restricted arm64 c-n-f Metadata [116 B] 93s Get:10 http://ftpmaster.internal/ubuntu noble-proposed/universe arm64 Packages [3819 kB] 93s Get:11 http://ftpmaster.internal/ubuntu noble-proposed/universe arm64 c-n-f Metadata [8528 B] 93s Get:12 http://ftpmaster.internal/ubuntu noble-proposed/multiverse arm64 Packages [53.5 kB] 93s Get:13 http://ftpmaster.internal/ubuntu noble-proposed/multiverse arm64 c-n-f Metadata [116 B] 95s Fetched 8755 kB in 2s (4774 kB/s) 95s Reading package lists... 98s Reading package lists... 99s Building dependency tree... 99s Reading state information... 99s Calculating upgrade... 100s The following packages will be REMOVED: 100s libglib2.0-0 libreadline8 libssl3 100s The following NEW packages will be installed: 100s libglib2.0-0t64 libreadline8t64 libssl3t64 xdg-user-dirs 100s The following packages have been kept back: 100s libpython3.12-minimal libpython3.12-stdlib python3.12 python3.12-minimal 100s The following packages will be upgraded: 100s gir1.2-glib-2.0 libglib2.0-data openssl readline-common 100s 4 upgraded, 4 newly installed, 3 to remove and 4 not upgraded. 100s Need to get 4737 kB of archives. 100s After this operation, 279 kB of additional disk space will be used. 100s Get:1 http://ftpmaster.internal/ubuntu noble-proposed/main arm64 gir1.2-glib-2.0 arm64 2.79.3-3ubuntu5 [182 kB] 100s Get:2 http://ftpmaster.internal/ubuntu noble-proposed/main arm64 libglib2.0-0t64 arm64 2.79.3-3ubuntu5 [1527 kB] 101s Get:3 http://ftpmaster.internal/ubuntu noble-proposed/main arm64 readline-common all 8.2-3.1 [56.4 kB] 101s Get:4 http://ftpmaster.internal/ubuntu noble-proposed/main arm64 libreadline8t64 arm64 8.2-3.1 [153 kB] 101s Get:5 http://ftpmaster.internal/ubuntu noble-proposed/main arm64 openssl arm64 3.0.13-0ubuntu1 [983 kB] 101s Get:6 http://ftpmaster.internal/ubuntu noble-proposed/main arm64 libssl3t64 arm64 3.0.13-0ubuntu1 [1770 kB] 101s Get:7 http://ftpmaster.internal/ubuntu noble-proposed/main arm64 libglib2.0-data all 2.79.3-3ubuntu5 [46.6 kB] 101s Get:8 http://ftpmaster.internal/ubuntu noble/main arm64 xdg-user-dirs arm64 0.18-1 [18.1 kB] 101s Fetched 4737 kB in 1s (6605 kB/s) 102s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 74758 files and directories currently installed.) 102s Preparing to unpack .../gir1.2-glib-2.0_2.79.3-3ubuntu5_arm64.deb ... 102s Unpacking gir1.2-glib-2.0:arm64 (2.79.3-3ubuntu5) over (2.79.2-1~ubuntu1) ... 102s dpkg: libglib2.0-0:arm64: dependency problems, but removing anyway as you requested: 102s udisks2 depends on libglib2.0-0 (>= 2.77.0). 102s shared-mime-info depends on libglib2.0-0 (>= 2.75.3). 102s python3-gi depends on libglib2.0-0 (>= 2.77.0). 102s python3-dbus depends on libglib2.0-0 (>= 2.16.0). 102s netplan.io depends on libglib2.0-0 (>= 2.70.0). 102s netplan-generator depends on libglib2.0-0 (>= 2.70.0). 102s libxmlb2:arm64 depends on libglib2.0-0 (>= 2.54.0). 102s libvolume-key1:arm64 depends on libglib2.0-0 (>= 2.18.0). 102s libudisks2-0:arm64 depends on libglib2.0-0 (>= 2.75.3). 102s libqrtr-glib0:arm64 depends on libglib2.0-0 (>= 2.56). 102s libqmi-proxy depends on libglib2.0-0 (>= 2.30.0). 102s libqmi-glib5:arm64 depends on libglib2.0-0 (>= 2.54.0). 102s libpolkit-gobject-1-0:arm64 depends on libglib2.0-0 (>= 2.38.0). 102s libpolkit-agent-1-0:arm64 depends on libglib2.0-0 (>= 2.38.0). 102s libnetplan0:arm64 depends on libglib2.0-0 (>= 2.75.3). 102s libmm-glib0:arm64 depends on libglib2.0-0 (>= 2.62.0). 102s libmbim-proxy depends on libglib2.0-0 (>= 2.56). 102s libmbim-glib4:arm64 depends on libglib2.0-0 (>= 2.56). 102s libjson-glib-1.0-0:arm64 depends on libglib2.0-0 (>= 2.75.3). 102s libjcat1:arm64 depends on libglib2.0-0 (>= 2.75.3). 102s libgusb2:arm64 depends on libglib2.0-0 (>= 2.75.3). 102s libgudev-1.0-0:arm64 depends on libglib2.0-0 (>= 2.38.0). 102s libgirepository-1.0-1:arm64 depends on libglib2.0-0 (>= 2.79.0). 102s libfwupd2:arm64 depends on libglib2.0-0 (>= 2.79.0). 102s libblockdev3:arm64 depends on libglib2.0-0 (>= 2.42.2). 102s libblockdev-utils3:arm64 depends on libglib2.0-0 (>= 2.75.3). 102s libblockdev-swap3:arm64 depends on libglib2.0-0 (>= 2.42.2). 102s libblockdev-part3:arm64 depends on libglib2.0-0 (>= 2.42.2). 102s libblockdev-nvme3:arm64 depends on libglib2.0-0 (>= 2.42.2). 102s libblockdev-mdraid3:arm64 depends on libglib2.0-0 (>= 2.42.2). 102s libblockdev-loop3:arm64 depends on libglib2.0-0 (>= 2.42.2). 102s libblockdev-fs3:arm64 depends on libglib2.0-0 (>= 2.42.2). 102s libblockdev-crypto3:arm64 depends on libglib2.0-0 (>= 2.42.2). 102s fwupd depends on libglib2.0-0 (>= 2.79.0). 102s bolt depends on libglib2.0-0 (>= 2.56.0). 102s 102s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 74758 files and directories currently installed.) 102s Removing libglib2.0-0:arm64 (2.79.2-1~ubuntu1) ... 102s Selecting previously unselected package libglib2.0-0t64:arm64. 102s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 74733 files and directories currently installed.) 102s Preparing to unpack .../libglib2.0-0t64_2.79.3-3ubuntu5_arm64.deb ... 102s libglib2.0-0t64.preinst: Removing /var/lib/dpkg/info/libglib2.0-0:arm64.postrm to avoid loss of /usr/share/glib-2.0/schemas/gschemas.compiled... 102s removed '/var/lib/dpkg/info/libglib2.0-0:arm64.postrm' 102s Unpacking libglib2.0-0t64:arm64 (2.79.3-3ubuntu5) ... 102s Preparing to unpack .../readline-common_8.2-3.1_all.deb ... 102s Unpacking readline-common (8.2-3.1) over (8.2-3) ... 102s dpkg: libreadline8:arm64: dependency problems, but removing anyway as you requested: 102s parted depends on libreadline8 (>= 6.0). 102s libpython3.12-stdlib:arm64 depends on libreadline8 (>= 7.0~beta). 102s gpgsm depends on libreadline8 (>= 6.0). 102s gpgconf depends on libreadline8 (>= 6.0). 102s gpg depends on libreadline8 (>= 6.0). 102s gawk depends on libreadline8 (>= 6.0). 102s fdisk depends on libreadline8 (>= 6.0). 102s 102s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 74758 files and directories currently installed.) 102s Removing libreadline8:arm64 (8.2-3) ... 102s Selecting previously unselected package libreadline8t64:arm64. 102s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 74746 files and directories currently installed.) 102s Preparing to unpack .../libreadline8t64_8.2-3.1_arm64.deb ... 102s Adding 'diversion of /lib/aarch64-linux-gnu/libhistory.so.8 to /lib/aarch64-linux-gnu/libhistory.so.8.usr-is-merged by libreadline8t64' 102s Adding 'diversion of /lib/aarch64-linux-gnu/libhistory.so.8.2 to /lib/aarch64-linux-gnu/libhistory.so.8.2.usr-is-merged by libreadline8t64' 102s Adding 'diversion of /lib/aarch64-linux-gnu/libreadline.so.8 to /lib/aarch64-linux-gnu/libreadline.so.8.usr-is-merged by libreadline8t64' 102s Adding 'diversion of /lib/aarch64-linux-gnu/libreadline.so.8.2 to /lib/aarch64-linux-gnu/libreadline.so.8.2.usr-is-merged by libreadline8t64' 102s Unpacking libreadline8t64:arm64 (8.2-3.1) ... 103s Preparing to unpack .../openssl_3.0.13-0ubuntu1_arm64.deb ... 103s Unpacking openssl (3.0.13-0ubuntu1) over (3.0.10-1ubuntu4) ... 103s dpkg: libssl3:arm64: dependency problems, but removing anyway as you requested: 103s wget depends on libssl3 (>= 3.0.0). 103s u-boot-tools depends on libssl3 (>= 3.0.0). 103s tnftp depends on libssl3 (>= 3.0.0). 103s tcpdump depends on libssl3 (>= 3.0.0). 103s systemd-resolved depends on libssl3 (>= 3.0.0). 103s systemd depends on libssl3 (>= 3.0.0). 103s sudo depends on libssl3 (>= 3.0.0). 103s sbsigntool depends on libssl3 (>= 3.0.0). 103s rsync depends on libssl3 (>= 3.0.0). 103s python3-cryptography depends on libssl3 (>= 3.0.0). 103s openssh-server depends on libssl3 (>= 3.0.10). 103s openssh-client depends on libssl3 (>= 3.0.10). 103s mtd-utils depends on libssl3 (>= 3.0.0). 103s mokutil depends on libssl3 (>= 3.0.0). 103s linux-headers-6.8.0-11-generic depends on libssl3 (>= 3.0.0). 103s libsystemd-shared:arm64 depends on libssl3 (>= 3.0.0). 103s libssh-4:arm64 depends on libssl3 (>= 3.0.0). 103s libsasl2-modules:arm64 depends on libssl3 (>= 3.0.0). 103s libsasl2-2:arm64 depends on libssl3 (>= 3.0.0). 103s libpython3.12-minimal:arm64 depends on libssl3 (>= 3.0.0). 103s libnvme1 depends on libssl3 (>= 3.0.0). 103s libkrb5-3:arm64 depends on libssl3 (>= 3.0.0). 103s libkmod2:arm64 depends on libssl3 (>= 3.0.0). 103s libfido2-1:arm64 depends on libssl3 (>= 3.0.0). 103s libcurl4:arm64 depends on libssl3 (>= 3.0.0). 103s libcryptsetup12:arm64 depends on libssl3 (>= 3.0.0). 103s kmod depends on libssl3 (>= 3.0.0). 103s dhcpcd-base depends on libssl3 (>= 3.0.0). 103s bind9-libs:arm64 depends on libssl3 (>= 3.0.0). 103s 103s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 74766 files and directories currently installed.) 103s Removing libssl3:arm64 (3.0.10-1ubuntu4) ... 103s Selecting previously unselected package libssl3t64:arm64. 103s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 74755 files and directories currently installed.) 103s Preparing to unpack .../libssl3t64_3.0.13-0ubuntu1_arm64.deb ... 103s Unpacking libssl3t64:arm64 (3.0.13-0ubuntu1) ... 103s Preparing to unpack .../libglib2.0-data_2.79.3-3ubuntu5_all.deb ... 103s Unpacking libglib2.0-data (2.79.3-3ubuntu5) over (2.79.2-1~ubuntu1) ... 103s Selecting previously unselected package xdg-user-dirs. 103s Preparing to unpack .../xdg-user-dirs_0.18-1_arm64.deb ... 103s Unpacking xdg-user-dirs (0.18-1) ... 103s Setting up xdg-user-dirs (0.18-1) ... 103s Setting up libssl3t64:arm64 (3.0.13-0ubuntu1) ... 103s Setting up libglib2.0-0t64:arm64 (2.79.3-3ubuntu5) ... 103s No schema files found: doing nothing. 103s Setting up libglib2.0-data (2.79.3-3ubuntu5) ... 103s Setting up gir1.2-glib-2.0:arm64 (2.79.3-3ubuntu5) ... 103s Setting up openssl (3.0.13-0ubuntu1) ... 103s Setting up readline-common (8.2-3.1) ... 103s Setting up libreadline8t64:arm64 (8.2-3.1) ... 103s Processing triggers for libc-bin (2.39-0ubuntu2) ... 103s Processing triggers for man-db (2.12.0-3) ... 104s Processing triggers for install-info (7.1-3) ... 104s Reading package lists... 105s Building dependency tree... 105s Reading state information... 105s 0 upgraded, 0 newly installed, 0 to remove and 4 not upgraded. 106s Hit:1 http://ftpmaster.internal/ubuntu noble InRelease 106s Hit:2 http://ftpmaster.internal/ubuntu noble-updates InRelease 107s Hit:3 http://ftpmaster.internal/ubuntu noble-security InRelease 107s Hit:4 http://ftpmaster.internal/ubuntu noble-proposed InRelease 109s Reading package lists... 109s Reading package lists... 109s Building dependency tree... 109s Reading state information... 110s Calculating upgrade... 110s The following packages have been kept back: 110s libpython3.12-minimal libpython3.12-stdlib python3.12 python3.12-minimal 110s 0 upgraded, 0 newly installed, 0 to remove and 4 not upgraded. 111s Reading package lists... 111s Building dependency tree... 111s Reading state information... 111s 0 upgraded, 0 newly installed, 0 to remove and 4 not upgraded. 114s autopkgtest [12:27:43]: testbed running kernel: Linux 6.8.0-11-generic #11-Ubuntu SMP PREEMPT_DYNAMIC Wed Feb 14 02:53:31 UTC 2024 115s autopkgtest [12:27:44]: @@@@@@@@@@@@@@@@@@@@ apt-source fpga-icestorm 117s Get:1 http://ftpmaster.internal/ubuntu noble/universe fpga-icestorm 0~20230218gitd20a5e9-1 (dsc) [2329 B] 117s Get:2 http://ftpmaster.internal/ubuntu noble/universe fpga-icestorm 0~20230218gitd20a5e9-1 (tar) [432 kB] 117s Get:3 http://ftpmaster.internal/ubuntu noble/universe fpga-icestorm 0~20230218gitd20a5e9-1 (diff) [10.3 kB] 117s gpgv: Signature made Wed Jun 14 23:39:20 2023 UTC 117s gpgv: using RSA key 57A1BF15B4F6F99B89EDB29FD39481AE1E79ACF7 117s gpgv: Can't check signature: No public key 117s dpkg-source: warning: cannot verify inline signature for ./fpga-icestorm_0~20230218gitd20a5e9-1.dsc: no acceptable signature found 118s autopkgtest [12:27:47]: testing package fpga-icestorm version 0~20230218gitd20a5e9-1 118s autopkgtest [12:27:47]: build not needed 119s autopkgtest [12:27:48]: test can-show-help: preparing testbed 121s Reading package lists... 121s Building dependency tree... 121s Reading state information... 121s Starting pkgProblemResolver with broken count: 0 121s Starting 2 pkgProblemResolver with broken count: 0 121s Done 122s The following additional packages will be installed: 122s fpga-icestorm fpga-icestorm-chipdb libftdi1 libusb-0.1-4 122s Suggested packages: 122s nextpnr-ice40 | nextpnr-ice40-qt 122s Recommended packages: 122s yosys 122s The following NEW packages will be installed: 122s autopkgtest-satdep fpga-icestorm fpga-icestorm-chipdb libftdi1 libusb-0.1-4 123s 0 upgraded, 5 newly installed, 0 to remove and 4 not upgraded. 123s Need to get 10.8 MB/10.8 MB of archives. 123s After this operation, 116 MB of additional disk space will be used. 123s Get:1 /tmp/autopkgtest.rlxjW8/1-autopkgtest-satdep.deb autopkgtest-satdep arm64 0 [716 B] 123s Get:2 http://ftpmaster.internal/ubuntu noble/main arm64 libusb-0.1-4 arm64 2:0.1.12-35 [19.7 kB] 123s Get:3 http://ftpmaster.internal/ubuntu noble/universe arm64 libftdi1 arm64 0.20-4ubuntu2 [15.0 kB] 123s Get:4 http://ftpmaster.internal/ubuntu noble/universe arm64 fpga-icestorm arm64 0~20230218gitd20a5e9-1 [424 kB] 123s Get:5 http://ftpmaster.internal/ubuntu noble/universe arm64 fpga-icestorm-chipdb all 0~20230218gitd20a5e9-1 [10.3 MB] 124s Fetched 10.8 MB in 1s (10.2 MB/s) 124s Selecting previously unselected package libusb-0.1-4:arm64. 124s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 74782 files and directories currently installed.) 124s Preparing to unpack .../libusb-0.1-4_2%3a0.1.12-35_arm64.deb ... 124s Unpacking libusb-0.1-4:arm64 (2:0.1.12-35) ... 124s Selecting previously unselected package libftdi1:arm64. 125s Preparing to unpack .../libftdi1_0.20-4ubuntu2_arm64.deb ... 125s Unpacking libftdi1:arm64 (0.20-4ubuntu2) ... 125s Selecting previously unselected package fpga-icestorm. 125s Preparing to unpack .../fpga-icestorm_0~20230218gitd20a5e9-1_arm64.deb ... 125s Unpacking fpga-icestorm (0~20230218gitd20a5e9-1) ... 125s Selecting previously unselected package fpga-icestorm-chipdb. 125s Preparing to unpack .../fpga-icestorm-chipdb_0~20230218gitd20a5e9-1_all.deb ... 125s Unpacking fpga-icestorm-chipdb (0~20230218gitd20a5e9-1) ... 125s Selecting previously unselected package autopkgtest-satdep. 125s Preparing to unpack .../1-autopkgtest-satdep.deb ... 125s Unpacking autopkgtest-satdep (0) ... 125s Setting up libusb-0.1-4:arm64 (2:0.1.12-35) ... 125s Setting up fpga-icestorm-chipdb (0~20230218gitd20a5e9-1) ... 125s Setting up libftdi1:arm64 (0.20-4ubuntu2) ... 125s Setting up fpga-icestorm (0~20230218gitd20a5e9-1) ... 125s Setting up autopkgtest-satdep (0) ... 125s Processing triggers for man-db (2.12.0-3) ... 125s Processing triggers for libc-bin (2.39-0ubuntu2) ... 130s (Reading database ... 74873 files and directories currently installed.) 130s Removing autopkgtest-satdep (0) ... 131s autopkgtest [12:28:00]: test can-show-help: [----------------------- 132s Simple programming tool for FTDI-based Lattice iCE programmers. 132s Usage: iceprog [-b|-n|-c] 132s iceprog -r|-R 132s iceprog -S 132s iceprog -t 132s 132s General options: 132s -d use the specified USB device [default: i:0x0403:0x6010 or i:0x0403:0x6014] 132s d: (e.g. d:002/005) 132s i:: (e.g. i:0x0403:0x6010) 132s i::: (e.g. i:0x0403:0x6010:0) 132s s::: 132s -I [ABCD] connect to the specified interface on the FTDI chip 132s [default: A] 132s -o start address for read/write [default: 0] 132s (append 'k' to the argument for size in kilobytes, 132s or 'M' for size in megabytes) 132s -s slow SPI (50 kHz instead of 6 MHz) 132s -k keep flash in powered up state (i.e. skip power down command) 132s -v verbose output 132s -i [4,32,64] select erase block size [default: 64k] 132s 132s Mode of operation: 132s [default] write file contents to flash, then verify 132s -X write file contents to flash only 132s -r read first 256 kB from flash and write to file 132s -R read the specified number of bytes from flash 132s (append 'k' to the argument for size in kilobytes, 132s or 'M' for size in megabytes) 132s -c do not write flash, only verify (`check') 132s -S perform SRAM programming 132s -t just read the flash ID sequence 132s -Q just set the flash QE=1 bit 132s 132s Erase mode (only meaningful in default mode): 132s [default] erase aligned chunks of 64kB in write mode 132s This means that some data after the written data (or 132s even before when -o is used) may be erased as well. 132s -b bulk erase entire flash before writing 132s -e erase flash as if we were writing that number of bytes 132s -n do not erase flash before writing 132s -p disable write protection before erasing or writing 132s This can be useful if flash memory appears to be 132s bricked and won't respond to erasing or programming. 132s 132s Miscellaneous options: 132s --help display this help and exit 132s -- treat all remaining arguments as filenames 132s 132s Exit status: 132s 0 on success, 132s 1 if a non-hardware error occurred (e.g., failure to read from or 132s write to a file, or invoked with invalid options), 132s 2 if communication with the hardware failed (e.g., cannot find the 132s iCE FTDI USB device), 132s 3 if verification of the data failed. 132s 132s Notes for iCEstick (iCE40HX-1k devel board): 132s An unmodified iCEstick can only be programmed via the serial flash. 132s Direct programming of the SRAM is not supported. For direct SRAM 132s programming the flash chip and one zero ohm resistor must be desoldered 132s and the FT2232H SI pin must be connected to the iCE SPI_SI pin, as shown 132s in this picture: 132s http://www.clifford.at/gallery/2014-elektronik/IMG_20141115_183838 132s 132s Notes for the iCE40-HX8K Breakout Board: 132s Make sure that the jumper settings on the board match the selected 132s mode (SRAM or FLASH). See the iCE40-HX8K user manual for details. 132s 132s If you have a bug report, please file an issue on github: 132s https://github.com/cliffordwolf/icestorm/issues 132s autopkgtest [12:28:01]: test can-show-help: -----------------------] 133s autopkgtest [12:28:02]: test can-show-help: - - - - - - - - - - results - - - - - - - - - - 133s can-show-help PASS (superficial) 133s autopkgtest [12:28:02]: test examples-compile: preparing testbed 135s Reading package lists... 135s Building dependency tree... 135s Reading state information... 135s Starting pkgProblemResolver with broken count: 0 136s Starting 2 pkgProblemResolver with broken count: 0 136s Done 136s The following additional packages will be installed: 136s adwaita-icon-theme at-spi2-common berkeley-abc dconf-gsettings-backend 136s dconf-service fontconfig fontconfig-config fonts-dejavu-core 136s fonts-dejavu-mono gir1.2-atk-1.0 gir1.2-freedesktop gir1.2-gdkpixbuf-2.0 136s gir1.2-gtk-3.0 gir1.2-harfbuzz-0.0 gir1.2-pango-1.0 graphviz 136s gtk-update-icon-cache hicolor-icon-theme humanity-icon-theme libann0 136s libatk-bridge2.0-0 libatk1.0-0 libatspi2.0-0 libavahi-client3 136s libavahi-common-data libavahi-common3 libblas3 libboost-filesystem1.83.0 136s libboost-iostreams1.83.0 libboost-program-options1.83.0 136s libboost-thread1.83.0 libcairo-gobject2 libcairo2 libcdt5 libcgraph6 136s libcolord2 libcups2 libdatrie1 libdb5.3t64 libdconf1 libdeflate0 libepoxy0 136s libfontconfig1 libgd3 libgdk-pixbuf-2.0-0 libgdk-pixbuf2.0-common 136s libgfortran5 libgraphite2-3 libgtk-3-0 libgtk-3-common libgts-0.7-5 libgvc6 136s libgvpr2 libharfbuzz-gobject0 libharfbuzz0b libice6 libjbig0 libjpeg-turbo8 136s libjpeg8 liblab-gamut1 liblapack3 liblcms2-2 liblerc4 libltdl7 136s libpango-1.0-0 libpangocairo-1.0-0 libpangoft2-1.0-0 libpangoxft-1.0-0 136s libpathplan4 libpixman-1-0 libpython3.11-minimal libpython3.11-stdlib 136s libpython3.12-minimal libpython3.12-stdlib libpython3.12t64 libsharpyuv0 136s libsm6 libtcl8.6 libthai-data libthai0 libtiff6 libwayland-client0 136s libwayland-cursor0 libwayland-egl1 libwebp7 libxaw7 libxcb-render0 136s libxcb-shm0 libxcomposite1 libxcursor1 libxdamage1 libxfixes3 libxft2 libxi6 136s libxinerama1 libxmu6 libxpm4 libxrandr2 libxrender1 libxt6 nextpnr-ice40 136s nextpnr-ice40-chipdb python3-cairo python3-click python3-colorama 136s python3-gi-cairo python3-numpy python3.11 python3.11-minimal python3.12 136s python3.12-minimal ubuntu-mono x11-common xdot yosys 136s Suggested packages: 136s gsfonts graphviz-doc colord cups-common libgd-tools gvfs liblcms2-utils 136s tcl8.6 gcc gfortran python3-dev python3-pytest python3.11-venv 136s python3.11-doc binfmt-support python3.12-venv python3.12-doc 136s Recommended packages: 136s librsvg2-common fonts-liberation2 at-spi2-core libgdk-pixbuf2.0-bin 136s libgtk-3-bin libgts-bin 136s The following packages will be REMOVED: 136s libdb5.3 136s The following NEW packages will be installed: 136s adwaita-icon-theme at-spi2-common autopkgtest-satdep berkeley-abc 136s dconf-gsettings-backend dconf-service fontconfig fontconfig-config 136s fonts-dejavu-core fonts-dejavu-mono gir1.2-atk-1.0 gir1.2-freedesktop 136s gir1.2-gdkpixbuf-2.0 gir1.2-gtk-3.0 gir1.2-harfbuzz-0.0 gir1.2-pango-1.0 136s graphviz gtk-update-icon-cache hicolor-icon-theme humanity-icon-theme 136s libann0 libatk-bridge2.0-0 libatk1.0-0 libatspi2.0-0 libavahi-client3 136s libavahi-common-data libavahi-common3 libblas3 libboost-filesystem1.83.0 136s libboost-iostreams1.83.0 libboost-program-options1.83.0 136s libboost-thread1.83.0 libcairo-gobject2 libcairo2 libcdt5 libcgraph6 136s libcolord2 libcups2 libdatrie1 libdb5.3t64 libdconf1 libdeflate0 libepoxy0 136s libfontconfig1 libgd3 libgdk-pixbuf-2.0-0 libgdk-pixbuf2.0-common 136s libgfortran5 libgraphite2-3 libgtk-3-0 libgtk-3-common libgts-0.7-5 libgvc6 136s libgvpr2 libharfbuzz-gobject0 libharfbuzz0b libice6 libjbig0 libjpeg-turbo8 136s libjpeg8 liblab-gamut1 liblapack3 liblcms2-2 liblerc4 libltdl7 136s libpango-1.0-0 libpangocairo-1.0-0 libpangoft2-1.0-0 libpangoxft-1.0-0 136s libpathplan4 libpixman-1-0 libpython3.11-minimal libpython3.11-stdlib 136s libpython3.12t64 libsharpyuv0 libsm6 libtcl8.6 libthai-data libthai0 136s libtiff6 libwayland-client0 libwayland-cursor0 libwayland-egl1 libwebp7 136s libxaw7 libxcb-render0 libxcb-shm0 libxcomposite1 libxcursor1 libxdamage1 136s libxfixes3 libxft2 libxi6 libxinerama1 libxmu6 libxpm4 libxrandr2 136s libxrender1 libxt6 nextpnr-ice40 nextpnr-ice40-chipdb python3-cairo 136s python3-click python3-colorama python3-gi-cairo python3-numpy python3.11 136s python3.11-minimal ubuntu-mono x11-common xdot yosys 136s The following packages will be upgraded: 136s libpython3.12-minimal libpython3.12-stdlib python3.12 python3.12-minimal 136s 4 upgraded, 112 newly installed, 1 to remove and 0 not upgraded. 136s Need to get 97.3 MB/97.3 MB of archives. 136s After this operation, 429 MB of additional disk space will be used. 136s Get:1 /tmp/autopkgtest.rlxjW8/2-autopkgtest-satdep.deb autopkgtest-satdep arm64 0 [732 B] 136s Get:2 http://ftpmaster.internal/ubuntu noble-proposed/main arm64 python3.12 arm64 3.12.2-4build2 [645 kB] 137s Get:3 http://ftpmaster.internal/ubuntu noble-proposed/main arm64 python3.12-minimal arm64 3.12.2-4build2 [2189 kB] 137s Get:4 http://ftpmaster.internal/ubuntu noble-proposed/main arm64 libpython3.12-minimal arm64 3.12.2-4build2 [829 kB] 137s Get:5 http://ftpmaster.internal/ubuntu noble-proposed/main arm64 libpython3.12-stdlib arm64 3.12.2-4build2 [2002 kB] 137s Get:6 http://ftpmaster.internal/ubuntu noble-proposed/main arm64 libdb5.3t64 arm64 5.3.28+dfsg2-5build1 [719 kB] 137s Get:7 http://ftpmaster.internal/ubuntu noble/main arm64 libpython3.11-minimal arm64 3.11.8-1 [837 kB] 137s Get:8 http://ftpmaster.internal/ubuntu noble/main arm64 python3.11-minimal arm64 3.11.8-1 [2150 kB] 137s Get:9 http://ftpmaster.internal/ubuntu noble/main arm64 libpython3.11-stdlib arm64 3.11.8-1 [1913 kB] 137s Get:10 http://ftpmaster.internal/ubuntu noble/main arm64 python3.11 arm64 3.11.8-1 [589 kB] 137s Get:11 http://ftpmaster.internal/ubuntu noble/main arm64 libgdk-pixbuf2.0-common all 2.42.10+dfsg-3 [7624 B] 137s Get:12 http://ftpmaster.internal/ubuntu noble/main arm64 libjpeg-turbo8 arm64 2.1.5-2ubuntu1 [160 kB] 137s Get:13 http://ftpmaster.internal/ubuntu noble/main arm64 libjpeg8 arm64 8c-2ubuntu11 [2148 B] 137s Get:14 http://ftpmaster.internal/ubuntu noble/main arm64 libdeflate0 arm64 1.19-1 [43.4 kB] 137s Get:15 http://ftpmaster.internal/ubuntu noble/main arm64 libjbig0 arm64 2.1-6.1ubuntu1 [28.9 kB] 137s Get:16 http://ftpmaster.internal/ubuntu noble/main arm64 liblerc4 arm64 4.0.0+ds-4ubuntu1 [153 kB] 137s Get:17 http://ftpmaster.internal/ubuntu noble/main arm64 libsharpyuv0 arm64 1.3.2-0.4 [14.4 kB] 137s Get:18 http://ftpmaster.internal/ubuntu noble/main arm64 libwebp7 arm64 1.3.2-0.4 [191 kB] 137s Get:19 http://ftpmaster.internal/ubuntu noble/main arm64 libtiff6 arm64 4.5.1+git230720-3ubuntu1 [226 kB] 137s Get:20 http://ftpmaster.internal/ubuntu noble/main arm64 libgdk-pixbuf-2.0-0 arm64 2.42.10+dfsg-3 [144 kB] 137s Get:21 http://ftpmaster.internal/ubuntu noble/main arm64 gtk-update-icon-cache arm64 3.24.40-2ubuntu1 [50.5 kB] 137s Get:22 http://ftpmaster.internal/ubuntu noble/main arm64 hicolor-icon-theme all 0.17-2 [9976 B] 137s Get:23 http://ftpmaster.internal/ubuntu noble/main arm64 humanity-icon-theme all 0.6.16 [1282 kB] 137s Get:24 http://ftpmaster.internal/ubuntu noble/main arm64 ubuntu-mono all 24.04-0ubuntu1 [151 kB] 137s Get:25 http://ftpmaster.internal/ubuntu noble/main arm64 adwaita-icon-theme all 46~rc-1 [723 kB] 137s Get:26 http://ftpmaster.internal/ubuntu noble/main arm64 at-spi2-common all 2.50.0-1 [7864 B] 137s Get:27 http://ftpmaster.internal/ubuntu noble/universe arm64 berkeley-abc arm64 1.01+20230625git01b1bd1+dfsg-3 [4306 kB] 137s Get:28 http://ftpmaster.internal/ubuntu noble/main arm64 libdconf1 arm64 0.40.0-4 [39.2 kB] 137s Get:29 http://ftpmaster.internal/ubuntu noble/main arm64 dconf-service arm64 0.40.0-4 [26.1 kB] 137s Get:30 http://ftpmaster.internal/ubuntu noble/main arm64 dconf-gsettings-backend arm64 0.40.0-4 [21.6 kB] 137s Get:31 http://ftpmaster.internal/ubuntu noble/main arm64 fonts-dejavu-mono all 2.37-8 [502 kB] 137s Get:32 http://ftpmaster.internal/ubuntu noble/main arm64 fonts-dejavu-core all 2.37-8 [835 kB] 137s Get:33 http://ftpmaster.internal/ubuntu noble/main arm64 fontconfig-config arm64 2.15.0-1ubuntu1 [37.0 kB] 137s Get:34 http://ftpmaster.internal/ubuntu noble/main arm64 libfontconfig1 arm64 2.15.0-1ubuntu1 [142 kB] 137s Get:35 http://ftpmaster.internal/ubuntu noble/main arm64 fontconfig arm64 2.15.0-1ubuntu1 [190 kB] 137s Get:36 http://ftpmaster.internal/ubuntu noble/main arm64 libatk1.0-0 arm64 2.50.0-1 [53.8 kB] 137s Get:37 http://ftpmaster.internal/ubuntu noble/main arm64 gir1.2-atk-1.0 arm64 2.50.0-1 [22.9 kB] 137s Get:38 http://ftpmaster.internal/ubuntu noble/main arm64 libpixman-1-0 arm64 0.42.2-1 [193 kB] 137s Get:39 http://ftpmaster.internal/ubuntu noble/main arm64 libxcb-render0 arm64 1.15-1 [16.1 kB] 137s Get:40 http://ftpmaster.internal/ubuntu noble/main arm64 libxcb-shm0 arm64 1.15-1 [5780 B] 138s Get:41 http://ftpmaster.internal/ubuntu noble/main arm64 libxrender1 arm64 1:0.9.10-1.1 [19.1 kB] 138s Get:42 http://ftpmaster.internal/ubuntu noble/main arm64 libcairo2 arm64 1.18.0-1 [550 kB] 138s Get:43 http://ftpmaster.internal/ubuntu noble/main arm64 libcairo-gobject2 arm64 1.18.0-1 [127 kB] 138s Get:44 http://ftpmaster.internal/ubuntu noble/main arm64 gir1.2-freedesktop arm64 1.79.1-1 [48.5 kB] 138s Get:45 http://ftpmaster.internal/ubuntu noble/main arm64 gir1.2-gdkpixbuf-2.0 arm64 2.42.10+dfsg-3 [9474 B] 138s Get:46 http://ftpmaster.internal/ubuntu noble/main arm64 libgraphite2-3 arm64 1.3.14-2 [81.5 kB] 138s Get:47 http://ftpmaster.internal/ubuntu noble/main arm64 libharfbuzz0b arm64 8.3.0-2 [463 kB] 138s Get:48 http://ftpmaster.internal/ubuntu noble/main arm64 libharfbuzz-gobject0 arm64 8.3.0-2 [32.8 kB] 138s Get:49 http://ftpmaster.internal/ubuntu noble/main arm64 gir1.2-harfbuzz-0.0 arm64 8.3.0-2 [44.5 kB] 138s Get:50 http://ftpmaster.internal/ubuntu noble/main arm64 libthai-data all 0.1.29-2 [158 kB] 138s Get:51 http://ftpmaster.internal/ubuntu noble/main arm64 libdatrie1 arm64 0.2.13-3 [21.7 kB] 138s Get:52 http://ftpmaster.internal/ubuntu noble/main arm64 libthai0 arm64 0.1.29-2 [18.1 kB] 138s Get:53 http://ftpmaster.internal/ubuntu noble/main arm64 libpango-1.0-0 arm64 1.51.0+ds-4 [226 kB] 138s Get:54 http://ftpmaster.internal/ubuntu noble/main arm64 libpangoft2-1.0-0 arm64 1.51.0+ds-4 [41.2 kB] 138s Get:55 http://ftpmaster.internal/ubuntu noble/main arm64 libpangocairo-1.0-0 arm64 1.51.0+ds-4 [27.6 kB] 138s Get:56 http://ftpmaster.internal/ubuntu noble/main arm64 libxft2 arm64 2.3.6-1 [43.3 kB] 138s Get:57 http://ftpmaster.internal/ubuntu noble/main arm64 libpangoxft-1.0-0 arm64 1.51.0+ds-4 [20.3 kB] 138s Get:58 http://ftpmaster.internal/ubuntu noble/main arm64 gir1.2-pango-1.0 arm64 1.51.0+ds-4 [34.9 kB] 138s Get:59 http://ftpmaster.internal/ubuntu noble/main arm64 libxi6 arm64 2:1.8.1-1 [31.9 kB] 138s Get:60 http://ftpmaster.internal/ubuntu noble/main arm64 libatspi2.0-0 arm64 2.50.0-1 [78.5 kB] 138s Get:61 http://ftpmaster.internal/ubuntu noble/main arm64 libatk-bridge2.0-0 arm64 2.50.0-1 [65.0 kB] 138s Get:62 http://ftpmaster.internal/ubuntu noble/main arm64 liblcms2-2 arm64 2.14-2 [159 kB] 138s Get:63 http://ftpmaster.internal/ubuntu noble/main arm64 libcolord2 arm64 1.4.7-1 [148 kB] 138s Get:64 http://ftpmaster.internal/ubuntu noble/main arm64 libavahi-common-data arm64 0.8-13ubuntu2 [29.5 kB] 138s Get:65 http://ftpmaster.internal/ubuntu noble/main arm64 libavahi-common3 arm64 0.8-13ubuntu2 [23.2 kB] 138s Get:66 http://ftpmaster.internal/ubuntu noble/main arm64 libavahi-client3 arm64 0.8-13ubuntu2 [27.3 kB] 138s Get:67 http://ftpmaster.internal/ubuntu noble/main arm64 libcups2 arm64 2.4.6-0ubuntu3 [270 kB] 138s Get:68 http://ftpmaster.internal/ubuntu noble/main arm64 libepoxy0 arm64 1.5.10-1 [247 kB] 138s Get:69 http://ftpmaster.internal/ubuntu noble/main arm64 libwayland-client0 arm64 1.22.0-2.1 [25.6 kB] 138s Get:70 http://ftpmaster.internal/ubuntu noble/main arm64 libwayland-cursor0 arm64 1.22.0-2.1 [10.2 kB] 138s Get:71 http://ftpmaster.internal/ubuntu noble/main arm64 libwayland-egl1 arm64 1.22.0-2.1 [5498 B] 138s Get:72 http://ftpmaster.internal/ubuntu noble/main arm64 libxcomposite1 arm64 1:0.4.5-1build2 [7080 B] 138s Get:73 http://ftpmaster.internal/ubuntu noble/main arm64 libxfixes3 arm64 1:6.0.0-2 [11.0 kB] 138s Get:74 http://ftpmaster.internal/ubuntu noble/main arm64 libxcursor1 arm64 1:1.2.1-1 [21.3 kB] 138s Get:75 http://ftpmaster.internal/ubuntu noble/main arm64 libxdamage1 arm64 1:1.1.6-1 [6032 B] 138s Get:76 http://ftpmaster.internal/ubuntu noble/main arm64 libxinerama1 arm64 2:1.1.4-3 [7056 B] 138s Get:77 http://ftpmaster.internal/ubuntu noble/main arm64 libxrandr2 arm64 2:1.5.2-2 [19.6 kB] 138s Get:78 http://ftpmaster.internal/ubuntu noble/main arm64 libgtk-3-common all 3.24.40-2ubuntu1 [1200 kB] 138s Get:79 http://ftpmaster.internal/ubuntu noble/main arm64 libgtk-3-0 arm64 3.24.40-2ubuntu1 [2867 kB] 138s Get:80 http://ftpmaster.internal/ubuntu noble/main arm64 gir1.2-gtk-3.0 arm64 3.24.40-2ubuntu1 [245 kB] 138s Get:81 http://ftpmaster.internal/ubuntu noble/universe arm64 libann0 arm64 1.1.2+doc-9 [25.1 kB] 138s Get:82 http://ftpmaster.internal/ubuntu noble/universe arm64 libcdt5 arm64 2.42.2-8build1 [20.3 kB] 138s Get:83 http://ftpmaster.internal/ubuntu noble/universe arm64 libcgraph6 arm64 2.42.2-8build1 [44.8 kB] 138s Get:84 http://ftpmaster.internal/ubuntu noble/main arm64 libxpm4 arm64 1:3.5.17-1 [34.5 kB] 138s Get:85 http://ftpmaster.internal/ubuntu noble/main arm64 libgd3 arm64 2.3.3-9ubuntu1 [119 kB] 138s Get:86 http://ftpmaster.internal/ubuntu noble/universe arm64 libgts-0.7-5 arm64 0.7.6+darcs121130-5 [157 kB] 138s Get:87 http://ftpmaster.internal/ubuntu noble/main arm64 libltdl7 arm64 2.4.7-7 [40.3 kB] 138s Get:88 http://ftpmaster.internal/ubuntu noble/universe arm64 libpathplan4 arm64 2.42.2-8build1 [22.6 kB] 138s Get:89 http://ftpmaster.internal/ubuntu noble/universe arm64 libgvc6 arm64 2.42.2-8build1 [692 kB] 138s Get:90 http://ftpmaster.internal/ubuntu noble/universe arm64 libgvpr2 arm64 2.42.2-8build1 [187 kB] 138s Get:91 http://ftpmaster.internal/ubuntu noble/universe arm64 liblab-gamut1 arm64 2.42.2-8build1 [1860 kB] 138s Get:92 http://ftpmaster.internal/ubuntu noble/main arm64 x11-common all 1:7.7+23ubuntu2 [23.4 kB] 138s Get:93 http://ftpmaster.internal/ubuntu noble/main arm64 libice6 arm64 2:1.0.10-1build2 [41.7 kB] 138s Get:94 http://ftpmaster.internal/ubuntu noble/main arm64 libsm6 arm64 2:1.2.3-1build2 [16.1 kB] 138s Get:95 http://ftpmaster.internal/ubuntu noble/main arm64 libxt6 arm64 1:1.2.1-1.1 [167 kB] 138s Get:96 http://ftpmaster.internal/ubuntu noble/main arm64 libxmu6 arm64 2:1.1.3-3 [48.9 kB] 138s Get:97 http://ftpmaster.internal/ubuntu noble/main arm64 libxaw7 arm64 2:1.0.14-1 [184 kB] 138s Get:98 http://ftpmaster.internal/ubuntu noble/universe arm64 graphviz arm64 2.42.2-8build1 [613 kB] 138s Get:99 http://ftpmaster.internal/ubuntu noble/main arm64 libblas3 arm64 3.12.0-3 [143 kB] 138s Get:100 http://ftpmaster.internal/ubuntu noble/main arm64 libboost-filesystem1.83.0 arm64 1.83.0-2ubuntu1 [366 kB] 138s Get:101 http://ftpmaster.internal/ubuntu noble/main arm64 libboost-iostreams1.83.0 arm64 1.83.0-2ubuntu1 [339 kB] 138s Get:102 http://ftpmaster.internal/ubuntu noble/main arm64 libboost-program-options1.83.0 arm64 1.83.0-2ubuntu1 [410 kB] 138s Get:103 http://ftpmaster.internal/ubuntu noble/main arm64 libboost-thread1.83.0 arm64 1.83.0-2ubuntu1 [358 kB] 139s Get:104 http://ftpmaster.internal/ubuntu noble/main arm64 libgfortran5 arm64 14-20240303-1ubuntu1 [444 kB] 139s Get:105 http://ftpmaster.internal/ubuntu noble/main arm64 liblapack3 arm64 3.12.0-3 [2241 kB] 139s Get:106 http://ftpmaster.internal/ubuntu noble-proposed/main arm64 libpython3.12t64 arm64 3.12.2-4build2 [2279 kB] 139s Get:107 http://ftpmaster.internal/ubuntu noble/main arm64 libtcl8.6 arm64 8.6.13+dfsg-2 [980 kB] 139s Get:108 http://ftpmaster.internal/ubuntu noble-proposed/universe arm64 nextpnr-ice40-chipdb arm64 0.6-3build4 [47.6 MB] 141s Get:109 http://ftpmaster.internal/ubuntu noble-proposed/universe arm64 nextpnr-ice40 arm64 0.6-3build4 [743 kB] 141s Get:110 http://ftpmaster.internal/ubuntu noble/main arm64 python3-cairo arm64 1.25.1-2 [153 kB] 141s Get:111 http://ftpmaster.internal/ubuntu noble/main arm64 python3-colorama all 0.4.6-4 [32.1 kB] 141s Get:112 http://ftpmaster.internal/ubuntu noble/main arm64 python3-click all 8.1.6-1 [79.0 kB] 141s Get:113 http://ftpmaster.internal/ubuntu noble/main arm64 python3-gi-cairo arm64 3.47.0-3 [9250 B] 141s Get:114 http://ftpmaster.internal/ubuntu noble/main arm64 python3-numpy arm64 1:1.24.2-2 [4525 kB] 141s Get:115 http://ftpmaster.internal/ubuntu noble/universe arm64 xdot all 1.3-1 [30.3 kB] 141s Get:116 http://ftpmaster.internal/ubuntu noble/universe arm64 yosys arm64 0.23-6 [3314 kB] 142s Fetched 97.3 MB in 5s (20.1 MB/s) 142s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 74873 files and directories currently installed.) 142s Preparing to unpack .../python3.12_3.12.2-4build2_arm64.deb ... 143s Unpacking python3.12 (3.12.2-4build2) over (3.12.2-1) ... 143s Preparing to unpack .../python3.12-minimal_3.12.2-4build2_arm64.deb ... 143s Unpacking python3.12-minimal (3.12.2-4build2) over (3.12.2-1) ... 143s Preparing to unpack .../libpython3.12-minimal_3.12.2-4build2_arm64.deb ... 143s Unpacking libpython3.12-minimal:arm64 (3.12.2-4build2) over (3.12.2-1) ... 143s Preparing to unpack .../libpython3.12-stdlib_3.12.2-4build2_arm64.deb ... 143s Unpacking libpython3.12-stdlib:arm64 (3.12.2-4build2) over (3.12.2-1) ... 143s dpkg: libdb5.3:arm64: dependency problems, but removing anyway as you requested: 143s libsasl2-modules-db:arm64 depends on libdb5.3. 143s libperl5.38:arm64 depends on libdb5.3. 143s libpam-modules:arm64 depends on libdb5.3. 143s iproute2 depends on libdb5.3. 143s apt-utils depends on libdb5.3. 143s 143s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 74871 files and directories currently installed.) 143s Removing libdb5.3:arm64 (5.3.28+dfsg2-4) ... 144s Selecting previously unselected package libdb5.3t64:arm64. 144s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 74865 files and directories currently installed.) 144s Preparing to unpack .../libdb5.3t64_5.3.28+dfsg2-5build1_arm64.deb ... 144s Unpacking libdb5.3t64:arm64 (5.3.28+dfsg2-5build1) ... 144s Setting up libdb5.3t64:arm64 (5.3.28+dfsg2-5build1) ... 144s Selecting previously unselected package libpython3.11-minimal:arm64. 144s (Reading database ... (Reading database ... 5% (Reading database ... 10% (Reading database ... 15% (Reading database ... 20% (Reading database ... 25% (Reading database ... 30% (Reading database ... 35% (Reading database ... 40% (Reading database ... 45% (Reading database ... 50% (Reading database ... 55% (Reading database ... 60% (Reading database ... 65% (Reading database ... 70% (Reading database ... 75% (Reading database ... 80% (Reading database ... 85% (Reading database ... 90% (Reading database ... 95% (Reading database ... 100% (Reading database ... 74871 files and directories currently installed.) 144s Preparing to unpack .../000-libpython3.11-minimal_3.11.8-1_arm64.deb ... 144s Unpacking libpython3.11-minimal:arm64 (3.11.8-1) ... 144s Selecting previously unselected package python3.11-minimal. 144s Preparing to unpack .../001-python3.11-minimal_3.11.8-1_arm64.deb ... 144s Unpacking python3.11-minimal (3.11.8-1) ... 144s Selecting previously unselected package libpython3.11-stdlib:arm64. 144s Preparing to unpack .../002-libpython3.11-stdlib_3.11.8-1_arm64.deb ... 144s Unpacking libpython3.11-stdlib:arm64 (3.11.8-1) ... 144s Selecting previously unselected package python3.11. 144s Preparing to unpack .../003-python3.11_3.11.8-1_arm64.deb ... 144s Unpacking python3.11 (3.11.8-1) ... 144s Selecting previously unselected package libgdk-pixbuf2.0-common. 144s Preparing to unpack .../004-libgdk-pixbuf2.0-common_2.42.10+dfsg-3_all.deb ... 144s Unpacking libgdk-pixbuf2.0-common (2.42.10+dfsg-3) ... 144s Selecting previously unselected package libjpeg-turbo8:arm64. 144s Preparing to unpack .../005-libjpeg-turbo8_2.1.5-2ubuntu1_arm64.deb ... 144s Unpacking libjpeg-turbo8:arm64 (2.1.5-2ubuntu1) ... 144s Selecting previously unselected package libjpeg8:arm64. 144s Preparing to unpack .../006-libjpeg8_8c-2ubuntu11_arm64.deb ... 144s Unpacking libjpeg8:arm64 (8c-2ubuntu11) ... 145s Selecting previously unselected package libdeflate0:arm64. 145s Preparing to unpack .../007-libdeflate0_1.19-1_arm64.deb ... 145s Unpacking libdeflate0:arm64 (1.19-1) ... 145s Selecting previously unselected package libjbig0:arm64. 145s Preparing to unpack .../008-libjbig0_2.1-6.1ubuntu1_arm64.deb ... 145s Unpacking libjbig0:arm64 (2.1-6.1ubuntu1) ... 145s Selecting previously unselected package liblerc4:arm64. 145s Preparing to unpack .../009-liblerc4_4.0.0+ds-4ubuntu1_arm64.deb ... 145s Unpacking liblerc4:arm64 (4.0.0+ds-4ubuntu1) ... 145s Selecting previously unselected package libsharpyuv0:arm64. 145s Preparing to unpack .../010-libsharpyuv0_1.3.2-0.4_arm64.deb ... 145s Unpacking libsharpyuv0:arm64 (1.3.2-0.4) ... 145s Selecting previously unselected package libwebp7:arm64. 145s Preparing to unpack .../011-libwebp7_1.3.2-0.4_arm64.deb ... 145s Unpacking libwebp7:arm64 (1.3.2-0.4) ... 145s Selecting previously unselected package libtiff6:arm64. 145s Preparing to unpack .../012-libtiff6_4.5.1+git230720-3ubuntu1_arm64.deb ... 145s Unpacking libtiff6:arm64 (4.5.1+git230720-3ubuntu1) ... 145s Selecting previously unselected package libgdk-pixbuf-2.0-0:arm64. 145s Preparing to unpack .../013-libgdk-pixbuf-2.0-0_2.42.10+dfsg-3_arm64.deb ... 145s Unpacking libgdk-pixbuf-2.0-0:arm64 (2.42.10+dfsg-3) ... 145s Selecting previously unselected package gtk-update-icon-cache. 146s Preparing to unpack .../014-gtk-update-icon-cache_3.24.40-2ubuntu1_arm64.deb ... 146s Unpacking gtk-update-icon-cache (3.24.40-2ubuntu1) ... 146s Selecting previously unselected package hicolor-icon-theme. 146s Preparing to unpack .../015-hicolor-icon-theme_0.17-2_all.deb ... 146s Unpacking hicolor-icon-theme (0.17-2) ... 146s Selecting previously unselected package humanity-icon-theme. 146s Preparing to unpack .../016-humanity-icon-theme_0.6.16_all.deb ... 146s Unpacking humanity-icon-theme (0.6.16) ... 146s Selecting previously unselected package ubuntu-mono. 147s Preparing to unpack .../017-ubuntu-mono_24.04-0ubuntu1_all.deb ... 147s Unpacking ubuntu-mono (24.04-0ubuntu1) ... 147s Selecting previously unselected package adwaita-icon-theme. 147s Preparing to unpack .../018-adwaita-icon-theme_46~rc-1_all.deb ... 147s Unpacking adwaita-icon-theme (46~rc-1) ... 147s Selecting previously unselected package at-spi2-common. 147s Preparing to unpack .../019-at-spi2-common_2.50.0-1_all.deb ... 147s Unpacking at-spi2-common (2.50.0-1) ... 147s Selecting previously unselected package berkeley-abc. 147s Preparing to unpack .../020-berkeley-abc_1.01+20230625git01b1bd1+dfsg-3_arm64.deb ... 147s Unpacking berkeley-abc (1.01+20230625git01b1bd1+dfsg-3) ... 147s Selecting previously unselected package libdconf1:arm64. 147s Preparing to unpack .../021-libdconf1_0.40.0-4_arm64.deb ... 147s Unpacking libdconf1:arm64 (0.40.0-4) ... 147s Selecting previously unselected package dconf-service. 147s Preparing to unpack .../022-dconf-service_0.40.0-4_arm64.deb ... 147s Unpacking dconf-service (0.40.0-4) ... 147s Selecting previously unselected package dconf-gsettings-backend:arm64. 147s Preparing to unpack .../023-dconf-gsettings-backend_0.40.0-4_arm64.deb ... 147s Unpacking dconf-gsettings-backend:arm64 (0.40.0-4) ... 147s Selecting previously unselected package fonts-dejavu-mono. 148s Preparing to unpack .../024-fonts-dejavu-mono_2.37-8_all.deb ... 148s Unpacking fonts-dejavu-mono (2.37-8) ... 148s Selecting previously unselected package fonts-dejavu-core. 148s Preparing to unpack .../025-fonts-dejavu-core_2.37-8_all.deb ... 148s Unpacking fonts-dejavu-core (2.37-8) ... 148s Selecting previously unselected package fontconfig-config. 148s Preparing to unpack .../026-fontconfig-config_2.15.0-1ubuntu1_arm64.deb ... 148s Unpacking fontconfig-config (2.15.0-1ubuntu1) ... 148s Selecting previously unselected package libfontconfig1:arm64. 148s Preparing to unpack .../027-libfontconfig1_2.15.0-1ubuntu1_arm64.deb ... 148s Unpacking libfontconfig1:arm64 (2.15.0-1ubuntu1) ... 148s Selecting previously unselected package fontconfig. 148s Preparing to unpack .../028-fontconfig_2.15.0-1ubuntu1_arm64.deb ... 148s Unpacking fontconfig (2.15.0-1ubuntu1) ... 148s Selecting previously unselected package libatk1.0-0:arm64. 148s Preparing to unpack .../029-libatk1.0-0_2.50.0-1_arm64.deb ... 148s Unpacking libatk1.0-0:arm64 (2.50.0-1) ... 148s Selecting previously unselected package gir1.2-atk-1.0:arm64. 148s Preparing to unpack .../030-gir1.2-atk-1.0_2.50.0-1_arm64.deb ... 148s Unpacking gir1.2-atk-1.0:arm64 (2.50.0-1) ... 148s Selecting previously unselected package libpixman-1-0:arm64. 148s Preparing to unpack .../031-libpixman-1-0_0.42.2-1_arm64.deb ... 148s Unpacking libpixman-1-0:arm64 (0.42.2-1) ... 148s Selecting previously unselected package libxcb-render0:arm64. 148s Preparing to unpack .../032-libxcb-render0_1.15-1_arm64.deb ... 148s Unpacking libxcb-render0:arm64 (1.15-1) ... 148s Selecting previously unselected package libxcb-shm0:arm64. 148s Preparing to unpack .../033-libxcb-shm0_1.15-1_arm64.deb ... 148s Unpacking libxcb-shm0:arm64 (1.15-1) ... 148s Selecting previously unselected package libxrender1:arm64. 148s Preparing to unpack .../034-libxrender1_1%3a0.9.10-1.1_arm64.deb ... 148s Unpacking libxrender1:arm64 (1:0.9.10-1.1) ... 149s Selecting previously unselected package libcairo2:arm64. 149s Preparing to unpack .../035-libcairo2_1.18.0-1_arm64.deb ... 149s Unpacking libcairo2:arm64 (1.18.0-1) ... 149s Selecting previously unselected package libcairo-gobject2:arm64. 149s Preparing to unpack .../036-libcairo-gobject2_1.18.0-1_arm64.deb ... 149s Unpacking libcairo-gobject2:arm64 (1.18.0-1) ... 149s Selecting previously unselected package gir1.2-freedesktop:arm64. 149s Preparing to unpack .../037-gir1.2-freedesktop_1.79.1-1_arm64.deb ... 149s Unpacking gir1.2-freedesktop:arm64 (1.79.1-1) ... 149s Selecting previously unselected package gir1.2-gdkpixbuf-2.0:arm64. 149s Preparing to unpack .../038-gir1.2-gdkpixbuf-2.0_2.42.10+dfsg-3_arm64.deb ... 149s Unpacking gir1.2-gdkpixbuf-2.0:arm64 (2.42.10+dfsg-3) ... 149s Selecting previously unselected package libgraphite2-3:arm64. 149s Preparing to unpack .../039-libgraphite2-3_1.3.14-2_arm64.deb ... 149s Unpacking libgraphite2-3:arm64 (1.3.14-2) ... 149s Selecting previously unselected package libharfbuzz0b:arm64. 149s Preparing to unpack .../040-libharfbuzz0b_8.3.0-2_arm64.deb ... 149s Unpacking libharfbuzz0b:arm64 (8.3.0-2) ... 149s Selecting previously unselected package libharfbuzz-gobject0:arm64. 149s Preparing to unpack .../041-libharfbuzz-gobject0_8.3.0-2_arm64.deb ... 149s Unpacking libharfbuzz-gobject0:arm64 (8.3.0-2) ... 149s Selecting previously unselected package gir1.2-harfbuzz-0.0:arm64. 149s Preparing to unpack .../042-gir1.2-harfbuzz-0.0_8.3.0-2_arm64.deb ... 149s Unpacking gir1.2-harfbuzz-0.0:arm64 (8.3.0-2) ... 149s Selecting previously unselected package libthai-data. 149s Preparing to unpack .../043-libthai-data_0.1.29-2_all.deb ... 149s Unpacking libthai-data (0.1.29-2) ... 149s Selecting previously unselected package libdatrie1:arm64. 149s Preparing to unpack .../044-libdatrie1_0.2.13-3_arm64.deb ... 149s Unpacking libdatrie1:arm64 (0.2.13-3) ... 149s Selecting previously unselected package libthai0:arm64. 149s Preparing to unpack .../045-libthai0_0.1.29-2_arm64.deb ... 149s Unpacking libthai0:arm64 (0.1.29-2) ... 149s Selecting previously unselected package libpango-1.0-0:arm64. 149s Preparing to unpack .../046-libpango-1.0-0_1.51.0+ds-4_arm64.deb ... 149s Unpacking libpango-1.0-0:arm64 (1.51.0+ds-4) ... 149s Selecting previously unselected package libpangoft2-1.0-0:arm64. 149s Preparing to unpack .../047-libpangoft2-1.0-0_1.51.0+ds-4_arm64.deb ... 149s Unpacking libpangoft2-1.0-0:arm64 (1.51.0+ds-4) ... 149s Selecting previously unselected package libpangocairo-1.0-0:arm64. 149s Preparing to unpack .../048-libpangocairo-1.0-0_1.51.0+ds-4_arm64.deb ... 149s Unpacking libpangocairo-1.0-0:arm64 (1.51.0+ds-4) ... 149s Selecting previously unselected package libxft2:arm64. 149s Preparing to unpack .../049-libxft2_2.3.6-1_arm64.deb ... 149s Unpacking libxft2:arm64 (2.3.6-1) ... 149s Selecting previously unselected package libpangoxft-1.0-0:arm64. 149s Preparing to unpack .../050-libpangoxft-1.0-0_1.51.0+ds-4_arm64.deb ... 149s Unpacking libpangoxft-1.0-0:arm64 (1.51.0+ds-4) ... 149s Selecting previously unselected package gir1.2-pango-1.0:arm64. 149s Preparing to unpack .../051-gir1.2-pango-1.0_1.51.0+ds-4_arm64.deb ... 149s Unpacking gir1.2-pango-1.0:arm64 (1.51.0+ds-4) ... 149s Selecting previously unselected package libxi6:arm64. 149s Preparing to unpack .../052-libxi6_2%3a1.8.1-1_arm64.deb ... 149s Unpacking libxi6:arm64 (2:1.8.1-1) ... 149s Selecting previously unselected package libatspi2.0-0:arm64. 149s Preparing to unpack .../053-libatspi2.0-0_2.50.0-1_arm64.deb ... 149s Unpacking libatspi2.0-0:arm64 (2.50.0-1) ... 149s Selecting previously unselected package libatk-bridge2.0-0:arm64. 149s Preparing to unpack .../054-libatk-bridge2.0-0_2.50.0-1_arm64.deb ... 149s Unpacking libatk-bridge2.0-0:arm64 (2.50.0-1) ... 149s Selecting previously unselected package liblcms2-2:arm64. 149s Preparing to unpack .../055-liblcms2-2_2.14-2_arm64.deb ... 149s Unpacking liblcms2-2:arm64 (2.14-2) ... 149s Selecting previously unselected package libcolord2:arm64. 149s Preparing to unpack .../056-libcolord2_1.4.7-1_arm64.deb ... 149s Unpacking libcolord2:arm64 (1.4.7-1) ... 149s Selecting previously unselected package libavahi-common-data:arm64. 149s Preparing to unpack .../057-libavahi-common-data_0.8-13ubuntu2_arm64.deb ... 149s Unpacking libavahi-common-data:arm64 (0.8-13ubuntu2) ... 149s Selecting previously unselected package libavahi-common3:arm64. 149s Preparing to unpack .../058-libavahi-common3_0.8-13ubuntu2_arm64.deb ... 149s Unpacking libavahi-common3:arm64 (0.8-13ubuntu2) ... 149s Selecting previously unselected package libavahi-client3:arm64. 149s Preparing to unpack .../059-libavahi-client3_0.8-13ubuntu2_arm64.deb ... 149s Unpacking libavahi-client3:arm64 (0.8-13ubuntu2) ... 149s Selecting previously unselected package libcups2:arm64. 149s Preparing to unpack .../060-libcups2_2.4.6-0ubuntu3_arm64.deb ... 149s Unpacking libcups2:arm64 (2.4.6-0ubuntu3) ... 149s Selecting previously unselected package libepoxy0:arm64. 150s Preparing to unpack .../061-libepoxy0_1.5.10-1_arm64.deb ... 150s Unpacking libepoxy0:arm64 (1.5.10-1) ... 150s Selecting previously unselected package libwayland-client0:arm64. 150s Preparing to unpack .../062-libwayland-client0_1.22.0-2.1_arm64.deb ... 150s Unpacking libwayland-client0:arm64 (1.22.0-2.1) ... 150s Selecting previously unselected package libwayland-cursor0:arm64. 150s Preparing to unpack .../063-libwayland-cursor0_1.22.0-2.1_arm64.deb ... 150s Unpacking libwayland-cursor0:arm64 (1.22.0-2.1) ... 150s Selecting previously unselected package libwayland-egl1:arm64. 150s Preparing to unpack .../064-libwayland-egl1_1.22.0-2.1_arm64.deb ... 150s Unpacking libwayland-egl1:arm64 (1.22.0-2.1) ... 150s Selecting previously unselected package libxcomposite1:arm64. 150s Preparing to unpack .../065-libxcomposite1_1%3a0.4.5-1build2_arm64.deb ... 150s Unpacking libxcomposite1:arm64 (1:0.4.5-1build2) ... 150s Selecting previously unselected package libxfixes3:arm64. 150s Preparing to unpack .../066-libxfixes3_1%3a6.0.0-2_arm64.deb ... 150s Unpacking libxfixes3:arm64 (1:6.0.0-2) ... 150s Selecting previously unselected package libxcursor1:arm64. 150s Preparing to unpack .../067-libxcursor1_1%3a1.2.1-1_arm64.deb ... 150s Unpacking libxcursor1:arm64 (1:1.2.1-1) ... 150s Selecting previously unselected package libxdamage1:arm64. 150s Preparing to unpack .../068-libxdamage1_1%3a1.1.6-1_arm64.deb ... 150s Unpacking libxdamage1:arm64 (1:1.1.6-1) ... 150s Selecting previously unselected package libxinerama1:arm64. 150s Preparing to unpack .../069-libxinerama1_2%3a1.1.4-3_arm64.deb ... 150s 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previously unselected package libcdt5:arm64. 150s Preparing to unpack .../075-libcdt5_2.42.2-8build1_arm64.deb ... 150s Unpacking libcdt5:arm64 (2.42.2-8build1) ... 150s Selecting previously unselected package libcgraph6:arm64. 151s Preparing to unpack .../076-libcgraph6_2.42.2-8build1_arm64.deb ... 151s Unpacking libcgraph6:arm64 (2.42.2-8build1) ... 151s Selecting previously unselected package libxpm4:arm64. 151s Preparing to unpack .../077-libxpm4_1%3a3.5.17-1_arm64.deb ... 151s Unpacking libxpm4:arm64 (1:3.5.17-1) ... 151s Selecting previously unselected package libgd3:arm64. 151s Preparing to unpack .../078-libgd3_2.3.3-9ubuntu1_arm64.deb ... 151s Unpacking libgd3:arm64 (2.3.3-9ubuntu1) ... 151s Selecting previously unselected package libgts-0.7-5:arm64. 151s Preparing to unpack .../079-libgts-0.7-5_0.7.6+darcs121130-5_arm64.deb ... 151s Unpacking libgts-0.7-5:arm64 (0.7.6+darcs121130-5) ... 151s Selecting previously unselected package libltdl7:arm64. 151s Preparing to unpack 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previously unselected package libboost-thread1.83.0:arm64. 152s Preparing to unpack .../096-libboost-thread1.83.0_1.83.0-2ubuntu1_arm64.deb ... 152s Unpacking libboost-thread1.83.0:arm64 (1.83.0-2ubuntu1) ... 152s Selecting previously unselected package libgfortran5:arm64. 152s Preparing to unpack .../097-libgfortran5_14-20240303-1ubuntu1_arm64.deb ... 152s Unpacking libgfortran5:arm64 (14-20240303-1ubuntu1) ... 152s Selecting previously unselected package liblapack3:arm64. 152s Preparing to unpack .../098-liblapack3_3.12.0-3_arm64.deb ... 152s Unpacking liblapack3:arm64 (3.12.0-3) ... 152s Selecting previously unselected package libpython3.12t64:arm64. 152s Preparing to unpack .../099-libpython3.12t64_3.12.2-4build2_arm64.deb ... 152s Unpacking libpython3.12t64:arm64 (3.12.2-4build2) ... 152s Selecting previously unselected package libtcl8.6:arm64. 153s Preparing to unpack .../100-libtcl8.6_8.6.13+dfsg-2_arm64.deb ... 153s Unpacking libtcl8.6:arm64 (8.6.13+dfsg-2) ... 153s Selecting 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(1.83.0-2ubuntu1) ... 156s Setting up python3-click (8.1.6-1) ... 157s Setting up libjbig0:arm64 (2.1-6.1ubuntu1) ... 157s Setting up libcolord2:arm64 (1.4.7-1) ... 157s Setting up berkeley-abc (1.01+20230625git01b1bd1+dfsg-3) ... 157s Setting up libdconf1:arm64 (0.40.0-4) ... 157s Setting up libgts-0.7-5:arm64 (0.7.6+darcs121130-5) ... 157s Setting up libblas3:arm64 (3.12.0-3) ... 157s update-alternatives: using /usr/lib/aarch64-linux-gnu/blas/libblas.so.3 to provide /usr/lib/aarch64-linux-gnu/libblas.so.3 (libblas.so.3-aarch64-linux-gnu) in auto mode 157s Setting up libepoxy0:arm64 (1.5.10-1) ... 157s Setting up libxfixes3:arm64 (1:6.0.0-2) ... 157s Setting up libboost-iostreams1.83.0:arm64 (1.83.0-2ubuntu1) ... 157s Setting up libpathplan4:arm64 (2.42.2-8build1) ... 157s Setting up libavahi-common-data:arm64 (0.8-13ubuntu2) ... 157s Setting up libann0 (1.1.2+doc-9) ... 157s Setting up libxinerama1:arm64 (2:1.1.4-3) ... 157s Setting up fonts-dejavu-mono (2.37-8) ... 157s Setting up libxrandr2:arm64 (2:1.5.2-2) ... 157s Setting up libtcl8.6:arm64 (8.6.13+dfsg-2) ... 157s Setting up fonts-dejavu-core (2.37-8) ... 157s Setting up libjpeg-turbo8:arm64 (2.1.5-2ubuntu1) ... 157s Setting up libltdl7:arm64 (2.4.7-7) ... 157s Setting up libgfortran5:arm64 (14-20240303-1ubuntu1) ... 157s Setting up libwebp7:arm64 (1.3.2-0.4) ... 157s Setting up at-spi2-common (2.50.0-1) ... 157s Setting up libharfbuzz0b:arm64 (8.3.0-2) ... 157s Setting up libthai-data (0.1.29-2) ... 157s Setting up libcdt5:arm64 (2.42.2-8build1) ... 157s Setting up libatk1.0-0:arm64 (2.50.0-1) ... 157s Setting up libcgraph6:arm64 (2.42.2-8build1) ... 157s Setting up libpython3.11-minimal:arm64 (3.11.8-1) ... 157s Setting up libwayland-egl1:arm64 (1.22.0-2.1) ... 157s Setting up libxcomposite1:arm64 (1:0.4.5-1build2) ... 157s Setting up libwayland-client0:arm64 (1.22.0-2.1) ... 157s Setting up libjpeg8:arm64 (8c-2ubuntu11) ... 157s Setting up python3.11-minimal (3.11.8-1) ... 157s Setting up python3.12-minimal (3.12.2-4build2) ... 158s Setting up libice6:arm64 (2:1.0.10-1build2) ... 158s Setting up liblapack3:arm64 (3.12.0-3) ... 159s update-alternatives: using /usr/lib/aarch64-linux-gnu/lapack/liblapack.so.3 to provide /usr/lib/aarch64-linux-gnu/liblapack.so.3 (liblapack.so.3-aarch64-linux-gnu) in auto mode 159s Setting up libpython3.12-stdlib:arm64 (3.12.2-4build2) ... 159s Setting up gir1.2-atk-1.0:arm64 (2.50.0-1) ... 159s Setting up fontconfig-config (2.15.0-1ubuntu1) ... 159s Setting up libpython3.11-stdlib:arm64 (3.11.8-1) ... 159s Setting up python3.12 (3.12.2-4build2) ... 160s Setting up libxcursor1:arm64 (1:1.2.1-1) ... 160s Setting up libavahi-common3:arm64 (0.8-13ubuntu2) ... 160s Setting up dconf-service (0.40.0-4) ... 160s Setting up libharfbuzz-gobject0:arm64 (8.3.0-2) ... 160s Setting up libpython3.12t64:arm64 (3.12.2-4build2) ... 160s Setting up libatk-bridge2.0-0:arm64 (2.50.0-1) ... 160s Setting up libthai0:arm64 (0.1.29-2) ... 160s Setting up nextpnr-ice40 (0.6-3build4) ... 160s Setting up libgvpr2:arm64 (2.42.2-8build1) ... 160s Setting up libtiff6:arm64 (4.5.1+git230720-3ubuntu1) ... 160s Setting up libwayland-cursor0:arm64 (1.22.0-2.1) ... 160s Setting up libgdk-pixbuf-2.0-0:arm64 (2.42.10+dfsg-3) ... 160s Setting up libfontconfig1:arm64 (2.15.0-1ubuntu1) ... 160s Setting up libsm6:arm64 (2:1.2.3-1build2) ... 160s Setting up libavahi-client3:arm64 (0.8-13ubuntu2) ... 160s Setting up gtk-update-icon-cache (3.24.40-2ubuntu1) ... 160s Setting up python3.11 (3.11.8-1) ... 161s Setting up fontconfig (2.15.0-1ubuntu1) ... 163s Regenerating fonts cache... done. 163s Setting up libxft2:arm64 (2.3.6-1) ... 163s Setting up dconf-gsettings-backend:arm64 (0.40.0-4) ... 163s Setting up gir1.2-gdkpixbuf-2.0:arm64 (2.42.10+dfsg-3) ... 163s Setting up libpango-1.0-0:arm64 (1.51.0+ds-4) ... 163s Setting up libcairo2:arm64 (1.18.0-1) ... 163s Setting up libgd3:arm64 (2.3.3-9ubuntu1) ... 163s Setting up libxt6:arm64 (1:1.2.1-1.1) ... 163s Setting up python3-numpy (1:1.24.2-2) ... 165s Setting up libcups2:arm64 (2.4.6-0ubuntu3) ... 165s Setting up libcairo-gobject2:arm64 (1.18.0-1) ... 165s Setting up libpangoft2-1.0-0:arm64 (1.51.0+ds-4) ... 165s Setting up libgtk-3-common (3.24.40-2ubuntu1) ... 165s Setting up libpangocairo-1.0-0:arm64 (1.51.0+ds-4) ... 165s Setting up libxmu6:arm64 (2:1.1.3-3) ... 165s Setting up gir1.2-freedesktop:arm64 (1.79.1-1) ... 165s Setting up python3-cairo (1.25.1-2) ... 165s Setting up libpangoxft-1.0-0:arm64 (1.51.0+ds-4) ... 165s Setting up libxaw7:arm64 (2:1.0.14-1) ... 165s Setting up gir1.2-harfbuzz-0.0:arm64 (8.3.0-2) ... 165s Setting up gir1.2-pango-1.0:arm64 (1.51.0+ds-4) ... 165s Setting up libgvc6 (2.42.2-8build1) ... 165s Setting up python3-gi-cairo (3.47.0-3) ... 165s Setting up graphviz (2.42.2-8build1) ... 165s Setting up adwaita-icon-theme (46~rc-1) ... 165s update-alternatives: using /usr/share/icons/Adwaita/cursor.theme to provide /usr/share/icons/default/index.theme (x-cursor-theme) in auto mode 165s Setting up humanity-icon-theme (0.6.16) ... 165s Setting up ubuntu-mono (24.04-0ubuntu1) ... 165s Processing triggers for systemd (255.2-3ubuntu2) ... 165s Processing triggers for man-db (2.12.0-3) ... 166s Processing triggers for libglib2.0-0t64:arm64 (2.79.3-3ubuntu5) ... 166s Setting up libgtk-3-0:arm64 (3.24.40-2ubuntu1) ... 166s Processing triggers for libc-bin (2.39-0ubuntu2) ... 166s Setting up gir1.2-gtk-3.0:arm64 (3.24.40-2ubuntu1) ... 166s Setting up xdot (1.3-1) ... 166s Setting up yosys (0.23-6) ... 166s /usr/share/yosys/smtio.py:771: SyntaxWarning: invalid escape sequence '\|' 166s s = "/-\|" 166s /usr/share/yosys/smtio.py:1174: SyntaxWarning: invalid escape sequence '\[' 166s if re.match("[\[\]]", name) and name[0] != "\\": 166s Setting up autopkgtest-satdep (0) ... 169s (Reading database ... 90659 files and directories currently installed.) 169s Removing autopkgtest-satdep (0) ... 170s autopkgtest [12:28:39]: test examples-compile: [----------------------- 170s make: Entering directory '/tmp/autopkgtest.rlxjW8/build.dCN/src/examples/hx8kboard' 170s yosys -p 'synth_ice40 -top top -json example.json' example.v 170s 170s /----------------------------------------------------------------------------\ 170s | | 170s | yosys -- Yosys Open SYnthesis Suite | 170s | | 170s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 170s | | 170s | Permission to use, copy, modify, and/or distribute this software for any | 170s | purpose with or without fee is hereby granted, provided that the above | 170s | copyright notice and this permission notice appear in all copies. | 170s | | 170s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 170s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 170s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 170s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 170s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 170s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 170s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 170s | | 170s \----------------------------------------------------------------------------/ 170s 170s Yosys 0.23 (git sha1 7ce5011c24b) 170s 170s 170s -- Parsing `example.v' using frontend ` -vlog2k' -- 170s 170s 1. Executing Verilog-2005 frontend: example.v 170s Parsing Verilog input from `example.v' to AST representation. 170s Storing AST representation for module `$abstract\top'. 170s Successfully finished Verilog frontend. 170s 170s -- Running command `synth_ice40 -top top -json example.json' -- 170s 170s 2. Executing SYNTH_ICE40 pass. 170s 170s 2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v 170s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation. 170s Generating RTLIL representation for module `\SB_IO'. 170s Generating RTLIL representation for module `\SB_GB_IO'. 170s Generating RTLIL representation for module `\SB_GB'. 170s Generating RTLIL representation for module `\SB_LUT4'. 170s Generating RTLIL representation for module `\SB_CARRY'. 170s Generating RTLIL representation for module `\SB_DFF'. 170s Generating RTLIL representation for module `\SB_DFFE'. 170s Generating RTLIL representation for module `\SB_DFFSR'. 170s Generating RTLIL representation for module `\SB_DFFR'. 170s Generating RTLIL representation for module `\SB_DFFSS'. 170s Generating RTLIL representation for module `\SB_DFFS'. 170s Generating RTLIL representation for module `\SB_DFFESR'. 170s Generating RTLIL representation for module `\SB_DFFER'. 170s Generating RTLIL representation for module `\SB_DFFESS'. 170s Generating RTLIL representation for module `\SB_DFFES'. 170s Generating RTLIL representation for module `\SB_DFFN'. 170s Generating RTLIL representation for module `\SB_DFFNE'. 170s Generating RTLIL representation for module `\SB_DFFNSR'. 170s Generating RTLIL representation for module `\SB_DFFNR'. 170s Generating RTLIL representation for module `\SB_DFFNSS'. 170s Generating RTLIL representation for module `\SB_DFFNS'. 170s Generating RTLIL representation for module `\SB_DFFNESR'. 170s Generating RTLIL representation for module `\SB_DFFNER'. 170s Generating RTLIL representation for module `\SB_DFFNESS'. 170s Generating RTLIL representation for module `\SB_DFFNES'. 170s Generating RTLIL representation for module `\SB_RAM40_4K'. 170s Generating RTLIL representation for module `\SB_RAM40_4KNR'. 170s Generating RTLIL representation for module `\SB_RAM40_4KNW'. 170s Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. 170s Generating RTLIL representation for module `\ICESTORM_LC'. 170s Generating RTLIL representation for module `\SB_PLL40_CORE'. 170s Generating RTLIL representation for module `\SB_PLL40_PAD'. 170s Generating RTLIL representation for module `\SB_PLL40_2_PAD'. 170s Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. 170s Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. 170s Generating RTLIL representation for module `\SB_WARMBOOT'. 170s Generating RTLIL representation for module `\SB_SPRAM256KA'. 170s Generating RTLIL representation for module `\SB_HFOSC'. 170s Generating RTLIL representation for module `\SB_LFOSC'. 170s Generating RTLIL representation for module `\SB_RGBA_DRV'. 170s Generating RTLIL representation for module `\SB_LED_DRV_CUR'. 170s Generating RTLIL representation for module `\SB_RGB_DRV'. 170s Generating RTLIL representation for module `\SB_I2C'. 170s Generating RTLIL representation for module `\SB_SPI'. 170s Generating RTLIL representation for module `\SB_LEDDA_IP'. 170s Generating RTLIL representation for module `\SB_FILTER_50NS'. 170s Generating RTLIL representation for module `\SB_IO_I3C'. 170s Generating RTLIL representation for module `\SB_IO_OD'. 170s Generating RTLIL representation for module `\SB_MAC16'. 170s Generating RTLIL representation for module `\ICESTORM_RAM'. 170s Successfully finished Verilog frontend. 170s 170s 2.2. Executing HIERARCHY pass (managing design hierarchy). 170s 170s 2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\top'. 170s Generating RTLIL representation for module `\top'. 170s 170s 2.3.1. Analyzing design hierarchy.. 170s Top module: \top 170s 170s 2.3.2. Analyzing design hierarchy.. 170s Top module: \top 170s Removing unused module `$abstract\top'. 170s Removed 1 unused modules. 170s 170s 2.4. Executing PROC pass (convert processes to netlists). 170s 170s 2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 170s Cleaned up 0 empty switches. 170s 170s 2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 170s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241 in module SB_DFFNES. 170s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234 in module SB_DFFNESS. 170s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230 in module SB_DFFNER. 170s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223 in module SB_DFFNESR. 170s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220 in module SB_DFFNS. 170s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217 in module SB_DFFNSS. 170s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214 in module SB_DFFNR. 170s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211 in module SB_DFFNSR. 170s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203 in module SB_DFFES. 170s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196 in module SB_DFFESS. 170s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192 in module SB_DFFER. 170s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185 in module SB_DFFESR. 170s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182 in module SB_DFFS. 170s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179 in module SB_DFFSS. 170s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176 in module SB_DFFR. 170s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173 in module SB_DFFSR. 170s Removed a total of 0 dead cases. 170s 170s 2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 170s Removed 8 redundant assignments. 170s Promoted 25 assignments to connections. 170s 170s 2.4.4. Executing PROC_INIT pass (extract init attributes). 170s Found init rule in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 170s Set init value: \Q = 1'0 170s Found init rule in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 170s Set init value: \Q = 1'0 170s Found init rule in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 170s Set init value: \Q = 1'0 170s Found init rule in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 170s Set init value: \Q = 1'0 170s Found init rule in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 170s Set init value: \Q = 1'0 170s Found init rule in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 170s Set init value: \Q = 1'0 170s Found init rule in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 170s Set init value: \Q = 1'0 170s Found init rule in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 170s Set init value: \Q = 1'0 170s Found init rule in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 170s Set init value: \Q = 1'0 170s Found init rule in `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 170s Set init value: \Q = 1'0 170s Found init rule in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 170s Set init value: \Q = 1'0 170s Found init rule in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 170s Set init value: \Q = 1'0 170s Found init rule in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 170s Set init value: \Q = 1'0 170s Found init rule in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 170s Set init value: \Q = 1'0 170s Found init rule in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 170s Set init value: \Q = 1'0 170s Found init rule in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 170s Set init value: \Q = 1'0 170s Found init rule in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 170s Set init value: \Q = 1'0 170s Found init rule in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 170s Set init value: \Q = 1'0 170s Found init rule in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 170s Set init value: \Q = 1'0 170s Found init rule in `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 170s Set init value: \Q = 1'0 170s Found init rule in `\top.$proc$example.v:16$386'. 170s Set init value: \counter = 30'000000000000000000000000000000 170s 170s 2.4.5. Executing PROC_ARST pass (detect async resets in processes). 170s Found async reset \S in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 170s Found async reset \R in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 170s Found async reset \S in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 170s Found async reset \R in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 170s Found async reset \S in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 170s Found async reset \R in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 170s Found async reset \S in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 170s Found async reset \R in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 170s 170s 2.4.6. Executing PROC_ROM pass (convert switches to ROMs). 170s Converted 0 switches. 170s 170s 170s 2.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 170s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 170s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 170s 1/1: $0\Q[0:0] 170s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 170s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 170s 1/1: $0\Q[0:0] 170s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 170s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 170s 1/1: $0\Q[0:0] 170s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 170s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 170s 1/1: $0\Q[0:0] 170s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 170s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 170s 1/1: $0\Q[0:0] 170s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 170s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 170s 1/1: $0\Q[0:0] 170s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 170s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 170s 1/1: $0\Q[0:0] 170s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 170s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 170s 1/1: $0\Q[0:0] 170s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 170s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 170s 1/1: $0\Q[0:0] 170s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 170s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 170s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 170s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 170s 1/1: $0\Q[0:0] 170s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 170s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 170s 1/1: $0\Q[0:0] 170s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 170s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 170s 1/1: $0\Q[0:0] 170s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 170s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 170s 1/1: $0\Q[0:0] 170s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 170s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 170s 1/1: $0\Q[0:0] 170s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 170s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 170s 1/1: $0\Q[0:0] 170s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 170s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 170s 1/1: $0\Q[0:0] 170s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 170s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 170s 1/1: $0\Q[0:0] 170s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 170s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 170s 1/1: $0\Q[0:0] 170s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 170s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 170s Creating decoders for process `\top.$proc$example.v:16$386'. 170s Creating decoders for process `\top.$proc$example.v:19$381'. 170s 170s 2.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). 170s 170s 2.4.9. Executing PROC_DFF pass (convert process syncs to FFs). 170s Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 170s created $adff cell `$procdff$431' with negative edge clock and positive level reset. 170s Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 170s created $dff cell `$procdff$432' with negative edge clock. 170s Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 170s created $adff cell `$procdff$433' with negative edge clock and positive level reset. 170s Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 170s created $dff cell `$procdff$434' with negative edge clock. 170s Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 170s created $adff cell `$procdff$435' with negative edge clock and positive level reset. 170s Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 170s created $dff cell `$procdff$436' with negative edge clock. 170s Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 170s created $adff cell `$procdff$437' with negative edge clock and positive level reset. 170s Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 170s created $dff cell `$procdff$438' with negative edge clock. 170s Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 170s created $dff cell `$procdff$439' with negative edge clock. 170s Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 170s created $dff cell `$procdff$440' with negative edge clock. 170s Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 170s created $adff cell `$procdff$441' with positive edge clock and positive level reset. 170s Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 170s created $dff cell `$procdff$442' with positive edge clock. 170s Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 170s created $adff cell `$procdff$443' with positive edge clock and positive level reset. 170s Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 170s created $dff cell `$procdff$444' with positive edge clock. 170s Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 170s created $adff cell `$procdff$445' with positive edge clock and positive level reset. 170s Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 170s created $dff cell `$procdff$446' with positive edge clock. 170s Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 170s created $adff cell `$procdff$447' with positive edge clock and positive level reset. 170s Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 170s created $dff cell `$procdff$448' with positive edge clock. 170s Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 170s created $dff cell `$procdff$449' with positive edge clock. 170s Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 170s created $dff cell `$procdff$450' with positive edge clock. 170s Creating register for signal `\top.\counter' using process `\top.$proc$example.v:19$381'. 170s created $dff cell `$procdff$451' with positive edge clock. 170s Creating register for signal `\top.\outcnt' using process `\top.$proc$example.v:19$381'. 170s created $dff cell `$procdff$452' with positive edge clock. 170s 170s 2.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 170s 170s 2.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 170s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 170s Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 170s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 170s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 170s Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 170s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 170s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 170s Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 170s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 170s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 170s Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 170s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 170s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 170s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 170s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 170s Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 170s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 170s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 170s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 170s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 170s Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 170s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 170s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 170s Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 170s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 170s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 170s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 170s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 170s Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 170s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 170s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 170s Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 170s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 170s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 170s Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 170s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 170s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 170s Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 170s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 170s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 170s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 170s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 170s Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 170s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 170s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 170s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 170s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 170s Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 170s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 170s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 170s Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 170s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 170s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 170s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 170s Removing empty process `top.$proc$example.v:16$386'. 170s Removing empty process `top.$proc$example.v:19$381'. 170s Cleaned up 18 empty switches. 170s 170s 2.4.12. Executing OPT_EXPR pass (perform const folding). 170s Optimizing module top. 170s 170s 170s 2.5. Executing FLATTEN pass (flatten design). 170s 170s 2.6. Executing TRIBUF pass. 170s 170s 2.7. Executing DEMINOUT pass (demote inout ports to input or output). 170s 170s 2.8. Executing OPT_EXPR pass (perform const folding). 170s Optimizing module top. 170s 170s 2.9. Executing OPT_CLEAN pass (remove unused cells and wires). 170s Finding unused cells or wires in module \top.. 170s Removed 0 unused cells and 5 unused wires. 170s 170s 170s 2.10. Executing CHECK pass (checking for obvious problems). 170s Checking module top... 170s Found and reported 0 problems. 170s 170s 2.11. Executing OPT pass (performing simple optimizations). 170s 170s 2.11.1. Executing OPT_EXPR pass (perform const folding). 170s Optimizing module top. 170s 170s 2.11.2. Executing OPT_MERGE pass (detect identical cells). 170s Finding identical cells in module `\top'. 170s Removed a total of 0 cells. 170s 170s 2.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 170s Running muxtree optimizer on module \top.. 170s Creating internal representation of mux trees. 170s No muxes found in this module. 170s Removed 0 multiplexer ports. 170s 170s 2.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 170s Optimizing cells in module \top. 170s Performed a total of 0 changes. 170s 170s 2.11.5. Executing OPT_MERGE pass (detect identical cells). 170s Finding identical cells in module `\top'. 170s Removed a total of 0 cells. 170s 170s 2.11.6. Executing OPT_DFF pass (perform DFF optimizations). 170s 170s 2.11.7. Executing OPT_CLEAN pass (remove unused cells and wires). 170s Finding unused cells or wires in module \top.. 170s 170s 2.11.8. Executing OPT_EXPR pass (perform const folding). 170s Optimizing module top. 170s 170s 2.11.9. Finished OPT passes. (There is nothing left to do.) 170s 170s 2.12. Executing FSM pass (extract and optimize FSM). 170s 170s 2.12.1. Executing FSM_DETECT pass (finding FSMs in design). 170s 170s 2.12.2. Executing FSM_EXTRACT pass (extracting FSM from design). 170s 170s 2.12.3. Executing FSM_OPT pass (simple optimizations of FSMs). 170s 170s 2.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). 170s Finding unused cells or wires in module \top.. 170s 170s 2.12.5. Executing FSM_OPT pass (simple optimizations of FSMs). 170s 170s 2.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 170s 170s 2.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 170s 170s 2.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 170s 170s 2.13. Executing OPT pass (performing simple optimizations). 170s 170s 2.13.1. Executing OPT_EXPR pass (perform const folding). 170s Optimizing module top. 170s 170s 2.13.2. Executing OPT_MERGE pass (detect identical cells). 170s Finding identical cells in module `\top'. 170s Removed a total of 0 cells. 170s 170s 2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 170s Running muxtree optimizer on module \top.. 170s Creating internal representation of mux trees. 170s No muxes found in this module. 170s Removed 0 multiplexer ports. 170s 170s 2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 170s Optimizing cells in module \top. 170s Performed a total of 0 changes. 170s 170s 2.13.5. Executing OPT_MERGE pass (detect identical cells). 170s Finding identical cells in module `\top'. 170s Removed a total of 0 cells. 170s 170s 2.13.6. Executing OPT_DFF pass (perform DFF optimizations). 170s 170s 2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). 170s Finding unused cells or wires in module \top.. 170s 170s 2.13.8. Executing OPT_EXPR pass (perform const folding). 170s Optimizing module top. 170s 170s 2.13.9. Finished OPT passes. (There is nothing left to do.) 170s 170s 2.14. Executing WREDUCE pass (reducing word size of cells). 170s Removed top 31 bits (of 32) from port B of cell top.$add$example.v:20$382 ($add). 170s Removed top 2 bits (of 32) from port Y of cell top.$add$example.v:20$382 ($add). 170s Removed top 1 bits (of 8) from port B of cell top.$xor$example.v:24$385 ($xor). 170s 170s 2.15. Executing PEEPOPT pass (run peephole optimizers). 170s 170s 2.16. Executing OPT_CLEAN pass (remove unused cells and wires). 170s Finding unused cells or wires in module \top.. 170s Removed 0 unused cells and 1 unused wires. 170s 170s 170s 2.17. Executing SHARE pass (SAT-based resource sharing). 170s 170s 2.18. Executing TECHMAP pass (map to technology primitives). 170s 170s 2.18.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v 170s Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation. 170s Generating RTLIL representation for module `\_90_lut_cmp_'. 170s Successfully finished Verilog frontend. 170s 170s 2.18.2. Continuing TECHMAP pass. 170s No more expansions possible. 170s 170s 170s 2.19. Executing OPT_EXPR pass (perform const folding). 170s Optimizing module top. 170s 170s 2.20. Executing OPT_CLEAN pass (remove unused cells and wires). 170s Finding unused cells or wires in module \top.. 170s 170s 2.21. Executing ALUMACC pass (create $alu and $macc cells). 170s Extracting $alu and $macc cells in module top: 170s creating $macc model for $add$example.v:20$382 ($add). 170s creating $alu model for $macc $add$example.v:20$382. 170s creating $alu cell for $add$example.v:20$382: $auto$alumacc.cc:485:replace_alu$454 170s created 1 $alu and 0 $macc cells. 170s 170s 2.22. Executing OPT pass (performing simple optimizations). 170s 170s 2.22.1. Executing OPT_EXPR pass (perform const folding). 170s Optimizing module top. 170s 170s 2.22.2. Executing OPT_MERGE pass (detect identical cells). 170s Finding identical cells in module `\top'. 170s Removed a total of 0 cells. 170s 170s 2.22.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 170s Running muxtree optimizer on module \top.. 170s Creating internal representation of mux trees. 170s No muxes found in this module. 170s Removed 0 multiplexer ports. 170s 170s 2.22.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 170s Optimizing cells in module \top. 170s Performed a total of 0 changes. 170s 170s 2.22.5. Executing OPT_MERGE pass (detect identical cells). 170s Finding identical cells in module `\top'. 170s Removed a total of 0 cells. 170s 170s 2.22.6. Executing OPT_DFF pass (perform DFF optimizations). 170s 170s 2.22.7. Executing OPT_CLEAN pass (remove unused cells and wires). 170s Finding unused cells or wires in module \top.. 170s 170s 2.22.8. Executing OPT_EXPR pass (perform const folding). 170s Optimizing module top. 170s 170s 2.22.9. Finished OPT passes. (There is nothing left to do.) 170s 170s 2.23. Executing MEMORY pass. 170s 170s 2.23.1. Executing OPT_MEM pass (optimize memories). 170s Performed a total of 0 transformations. 170s 170s 2.23.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). 170s Performed a total of 0 transformations. 170s 170s 2.23.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 170s 170s 2.23.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 170s 170s 2.23.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 170s 170s 2.23.6. Executing OPT_CLEAN pass (remove unused cells and wires). 170s Finding unused cells or wires in module \top.. 170s 170s 2.23.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 170s 170s 2.23.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). 170s Performed a total of 0 transformations. 170s 170s 2.23.9. Executing OPT_CLEAN pass (remove unused cells and wires). 170s Finding unused cells or wires in module \top.. 170s 170s 2.23.10. Executing MEMORY_COLLECT pass (generating $mem cells). 170s 170s 2.24. Executing OPT_CLEAN pass (remove unused cells and wires). 170s Finding unused cells or wires in module \top.. 170s 170s 2.25. Executing MEMORY_LIBMAP pass (mapping memories to cells). 170s 170s 2.26. Executing TECHMAP pass (map to technology primitives). 170s 170s 2.26.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v 171s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation. 171s Generating RTLIL representation for module `\$__ICE40_RAM4K_'. 171s Successfully finished Verilog frontend. 171s 171s 2.26.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/spram_map.v 171s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/spram_map.v' to AST representation. 171s Generating RTLIL representation for module `\$__ICE40_SPRAM_'. 171s Successfully finished Verilog frontend. 171s 171s 2.26.3. Continuing TECHMAP pass. 171s No more expansions possible. 171s 171s 171s 2.27. Executing ICE40_BRAMINIT pass. 171s 171s 2.28. Executing OPT pass (performing simple optimizations). 171s 171s 2.28.1. Executing OPT_EXPR pass (perform const folding). 171s Optimizing module top. 171s 171s 171s 2.28.2. Executing OPT_MERGE pass (detect identical cells). 171s Finding identical cells in module `\top'. 171s Removed a total of 0 cells. 171s 171s 2.28.3. Executing OPT_DFF pass (perform DFF optimizations). 171s 171s 2.28.4. Executing OPT_CLEAN pass (remove unused cells and wires). 171s Finding unused cells or wires in module \top.. 171s Removed 0 unused cells and 2 unused wires. 171s 171s 171s 2.28.5. Finished fast OPT passes. 171s 171s 2.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 171s 171s 2.30. Executing OPT pass (performing simple optimizations). 171s 171s 2.30.1. Executing OPT_EXPR pass (perform const folding). 171s Optimizing module top. 171s 171s 2.30.2. Executing OPT_MERGE pass (detect identical cells). 171s Finding identical cells in module `\top'. 171s Removed a total of 0 cells. 171s 171s 2.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 171s Running muxtree optimizer on module \top.. 171s Creating internal representation of mux trees. 171s No muxes found in this module. 171s Removed 0 multiplexer ports. 171s 171s 2.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 171s Optimizing cells in module \top. 171s Performed a total of 0 changes. 171s 171s 2.30.5. Executing OPT_MERGE pass (detect identical cells). 171s Finding identical cells in module `\top'. 171s Removed a total of 0 cells. 171s 171s 2.30.6. Executing OPT_DFF pass (perform DFF optimizations). 171s 171s 2.30.7. Executing OPT_CLEAN pass (remove unused cells and wires). 171s Finding unused cells or wires in module \top.. 171s 171s 2.30.8. Executing OPT_EXPR pass (perform const folding). 171s Optimizing module top. 171s 171s 2.30.9. Finished OPT passes. (There is nothing left to do.) 171s 171s 2.31. Executing ICE40_WRAPCARRY pass (wrap carries). 171s 171s 2.32. Executing TECHMAP pass (map to technology primitives). 171s 171s 2.32.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v 171s Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation. 171s Generating RTLIL representation for module `\_90_simplemap_bool_ops'. 171s Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. 171s Generating RTLIL representation for module `\_90_simplemap_logic_ops'. 171s Generating RTLIL representation for module `\_90_simplemap_compare_ops'. 171s Generating RTLIL representation for module `\_90_simplemap_various'. 171s Generating RTLIL representation for module `\_90_simplemap_registers'. 171s Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. 171s Generating RTLIL representation for module `\_90_shift_shiftx'. 171s Generating RTLIL representation for module `\_90_fa'. 171s Generating RTLIL representation for module `\_90_lcu'. 171s Generating RTLIL representation for module `\_90_alu'. 171s Generating RTLIL representation for module `\_90_macc'. 171s Generating RTLIL representation for module `\_90_alumacc'. 171s Generating RTLIL representation for module `\$__div_mod_u'. 171s Generating RTLIL representation for module `\$__div_mod_trunc'. 171s Generating RTLIL representation for module `\_90_div'. 171s Generating RTLIL representation for module `\_90_mod'. 171s Generating RTLIL representation for module `\$__div_mod_floor'. 171s Generating RTLIL representation for module `\_90_divfloor'. 171s Generating RTLIL representation for module `\_90_modfloor'. 171s Generating RTLIL representation for module `\_90_pow'. 171s Generating RTLIL representation for module `\_90_pmux'. 171s Generating RTLIL representation for module `\_90_demux'. 171s Generating RTLIL representation for module `\_90_lut'. 171s Successfully finished Verilog frontend. 171s 171s 2.32.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v 171s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation. 171s Generating RTLIL representation for module `\_80_ice40_alu'. 171s Successfully finished Verilog frontend. 171s 171s 2.32.3. Continuing TECHMAP pass. 171s Using template $paramod$44a13d10af618e7fbe7b9aad2f6151ffcee1e2fa\_80_ice40_alu for cells of type $alu. 171s Using extmapper simplemap for cells of type $xor. 171s Using extmapper simplemap for cells of type $dff. 171s Using extmapper simplemap for cells of type $mux. 171s Using extmapper simplemap for cells of type $not. 171s Using extmapper simplemap for cells of type $pos. 171s No more expansions possible. 171s 171s 171s 2.33. Executing OPT pass (performing simple optimizations). 171s 171s 2.33.1. Executing OPT_EXPR pass (perform const folding). 171s Optimizing module top. 171s 171s 171s 2.33.2. Executing OPT_MERGE pass (detect identical cells). 171s Finding identical cells in module `\top'. 171s 171s Removed a total of 1 cells. 171s 171s 2.33.3. Executing OPT_DFF pass (perform DFF optimizations). 171s 171s 2.33.4. Executing OPT_CLEAN pass (remove unused cells and wires). 171s Finding unused cells or wires in module \top.. 171s Removed 30 unused cells and 17 unused wires. 171s 171s 171s 2.33.5. Finished fast OPT passes. 171s 171s 2.34. Executing ICE40_OPT pass (performing simple optimizations). 171s 171s 2.34.1. Running ICE40 specific optimizations. 171s Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$454.slice[0].carry: CO=\counter [0] 171s 171s 2.34.2. Executing OPT_EXPR pass (perform const folding). 171s Optimizing module top. 171s 171s 2.34.3. Executing OPT_MERGE pass (detect identical cells). 171s Finding identical cells in module `\top'. 171s Removed a total of 0 cells. 171s 171s 2.34.4. Executing OPT_DFF pass (perform DFF optimizations). 171s 171s 2.34.5. Executing OPT_CLEAN pass (remove unused cells and wires). 171s Finding unused cells or wires in module \top.. 171s 171s 2.34.6. Rerunning OPT passes. (Removed registers in this run.) 171s 171s 2.34.7. Running ICE40 specific optimizations. 171s 171s 2.34.8. Executing OPT_EXPR pass (perform const folding). 171s Optimizing module top. 171s 171s 2.34.9. Executing OPT_MERGE pass (detect identical cells). 171s Finding identical cells in module `\top'. 171s Removed a total of 0 cells. 171s 171s 2.34.10. Executing OPT_DFF pass (perform DFF optimizations). 171s 171s 2.34.11. Executing OPT_CLEAN pass (remove unused cells and wires). 171s Finding unused cells or wires in module \top.. 171s 171s 2.34.12. Finished OPT passes. (There is nothing left to do.) 171s 171s 2.35. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 171s 171s 2.36. Executing TECHMAP pass (map to technology primitives). 171s 171s 2.36.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 171s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 171s Generating RTLIL representation for module `\$_DFF_N_'. 171s Generating RTLIL representation for module `\$_DFF_P_'. 171s Generating RTLIL representation for module `\$_DFFE_NP_'. 171s Generating RTLIL representation for module `\$_DFFE_PP_'. 171s Generating RTLIL representation for module `\$_DFF_NP0_'. 171s Generating RTLIL representation for module `\$_DFF_NP1_'. 171s Generating RTLIL representation for module `\$_DFF_PP0_'. 171s Generating RTLIL representation for module `\$_DFF_PP1_'. 171s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 171s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 171s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 171s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 171s Generating RTLIL representation for module `\$_SDFF_NP0_'. 171s Generating RTLIL representation for module `\$_SDFF_NP1_'. 171s Generating RTLIL representation for module `\$_SDFF_PP0_'. 171s Generating RTLIL representation for module `\$_SDFF_PP1_'. 171s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 171s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 171s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 171s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 171s Successfully finished Verilog frontend. 171s 171s 2.36.2. Continuing TECHMAP pass. 171s Using template \$_DFF_P_ for cells of type $_DFF_P_. 171s No more expansions possible. 171s 171s 171s 2.37. Executing OPT_EXPR pass (perform const folding). 171s Optimizing module top. 171s 171s 2.38. Executing SIMPLEMAP pass (map simple cells to gate primitives). 171s Mapping top.$auto$alumacc.cc:485:replace_alu$454.slice[0].carry ($lut). 171s 171s 2.39. Executing ICE40_OPT pass (performing simple optimizations). 171s 171s 2.39.1. Running ICE40 specific optimizations. 171s 171s 2.39.2. Executing OPT_EXPR pass (perform const folding). 171s Optimizing module top. 171s 171s 171s 2.39.3. Executing OPT_MERGE pass (detect identical cells). 171s Finding identical cells in module `\top'. 171s Removed a total of 0 cells. 171s 171s 2.39.4. Executing OPT_DFF pass (perform DFF optimizations). 171s 171s 2.39.5. Executing OPT_CLEAN pass (remove unused cells and wires). 171s Finding unused cells or wires in module \top.. 171s Removed 0 unused cells and 156 unused wires. 171s 171s 171s 2.39.6. Rerunning OPT passes. (Removed registers in this run.) 171s 171s 2.39.7. Running ICE40 specific optimizations. 171s 171s 2.39.8. Executing OPT_EXPR pass (perform const folding). 171s Optimizing module top. 171s 171s 2.39.9. Executing OPT_MERGE pass (detect identical cells). 171s Finding identical cells in module `\top'. 171s Removed a total of 0 cells. 171s 171s 2.39.10. Executing OPT_DFF pass (perform DFF optimizations). 171s 171s 2.39.11. Executing OPT_CLEAN pass (remove unused cells and wires). 171s Finding unused cells or wires in module \top.. 171s 171s 2.39.12. Finished OPT passes. (There is nothing left to do.) 171s 171s 2.40. Executing TECHMAP pass (map to technology primitives). 171s 171s 2.40.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v 171s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation. 171s Generating RTLIL representation for module `\$_DLATCH_N_'. 171s Generating RTLIL representation for module `\$_DLATCH_P_'. 171s Successfully finished Verilog frontend. 171s 171s 2.40.2. Continuing TECHMAP pass. 171s No more expansions possible. 171s 171s 171s 2.41. Executing ABC pass (technology mapping using ABC). 171s 171s 2.41.1. Extracting gate netlist of module `\top' to `/input.blif'.. 171s Extracted 8 gates and 17 wires to a netlist network with 9 inputs and 8 outputs. 171s 171s 2.41.1.1. Executing ABC. 171s Running ABC command: "berkeley-abc" -s -f /abc.script 2>&1 171s ABC: ABC command line: "source /abc.script". 171s ABC: 171s ABC: + read_blif /input.blif 171s ABC: + read_lut /lutdefs.txt 171s ABC: + strash 171s ABC: + &get -n 171s ABC: + &fraig -x 171s ABC: + &put 171s ABC: + scorr 171s ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). 171s ABC: + dc2 171s ABC: + dretime 171s ABC: + strash 171s ABC: + dch -f 171s ABC: + if 171s ABC: + mfs2 171s ABC: + lutpack -S 1 171s ABC: + dress /input.blif 171s ABC: Total number of equiv classes = 9. 171s ABC: Participating nodes from both networks = 16. 171s ABC: Participating nodes from the first network = 8. ( 88.89 % of nodes) 171s ABC: Participating nodes from the second network = 8. ( 88.89 % of nodes) 171s ABC: Node pairs (any polarity) = 8. ( 88.89 % of names can be moved) 171s ABC: Node pairs (same polarity) = 8. ( 88.89 % of names can be moved) 171s ABC: Total runtime = 0.00 sec 171s ABC: + write_blif /output.blif 171s 171s 2.41.1.2. Re-integrating ABC results. 171s ABC RESULTS: $lut cells: 8 171s ABC RESULTS: internal signals: 0 171s ABC RESULTS: input signals: 9 171s ABC RESULTS: output signals: 8 171s Removing temp directory. 171s 171s 2.42. Executing ICE40_WRAPCARRY pass (wrap carries). 171s 171s 2.43. Executing TECHMAP pass (map to technology primitives). 171s 171s 2.43.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 171s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 171s Generating RTLIL representation for module `\$_DFF_N_'. 171s Generating RTLIL representation for module `\$_DFF_P_'. 171s Generating RTLIL representation for module `\$_DFFE_NP_'. 171s Generating RTLIL representation for module `\$_DFFE_PP_'. 171s Generating RTLIL representation for module `\$_DFF_NP0_'. 171s Generating RTLIL representation for module `\$_DFF_NP1_'. 171s Generating RTLIL representation for module `\$_DFF_PP0_'. 171s Generating RTLIL representation for module `\$_DFF_PP1_'. 171s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 171s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 171s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 171s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 171s Generating RTLIL representation for module `\$_SDFF_NP0_'. 171s Generating RTLIL representation for module `\$_SDFF_NP1_'. 171s Generating RTLIL representation for module `\$_SDFF_PP0_'. 171s Generating RTLIL representation for module `\$_SDFF_PP1_'. 171s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 171s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 171s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 171s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 171s Successfully finished Verilog frontend. 171s 171s 2.43.2. Continuing TECHMAP pass. 171s No more expansions possible. 171s 171s Removed 1 unused cells and 18 unused wires. 171s 171s 2.44. Executing OPT_LUT pass (optimize LUTs). 171s Discovering LUTs. 171s Number of LUTs: 37 171s 1-LUT 1 171s 2-LUT 8 171s 3-LUT 28 171s with \SB_CARRY (#0) 28 171s with \SB_CARRY (#1) 28 171s 171s Eliminating LUTs. 171s Number of LUTs: 37 171s 1-LUT 1 171s 2-LUT 8 171s 3-LUT 28 171s with \SB_CARRY (#0) 28 171s with \SB_CARRY (#1) 28 171s 171s Combining LUTs. 171s Number of LUTs: 37 171s 1-LUT 1 171s 2-LUT 8 171s 3-LUT 28 171s with \SB_CARRY (#0) 28 171s with \SB_CARRY (#1) 28 171s 171s Eliminated 0 LUTs. 171s Combined 0 LUTs. 171s 171s 171s 2.45. Executing TECHMAP pass (map to technology primitives). 171s 171s 2.45.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v 171s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation. 171s Generating RTLIL representation for module `\$lut'. 171s Successfully finished Verilog frontend. 171s 171s 2.45.2. Continuing TECHMAP pass. 171s Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut. 171s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut. 171s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. 171s No more expansions possible. 171s 171s Removed 0 unused cells and 74 unused wires. 171s 171s 2.46. Executing AUTONAME pass. 171s Renamed 163 objects in module top (4 iterations). 171s 171s 171s 2.47. Executing HIERARCHY pass (managing design hierarchy). 171s 171s 2.47.1. Analyzing design hierarchy.. 171s Top module: \top 171s 171s 2.47.2. Analyzing design hierarchy.. 171s Top module: \top 171s Removed 0 unused modules. 171s 171s 2.48. Printing statistics. 171s 171s === top === 171s 171s Number of wires: 13 171s Number of wire bits: 107 171s Number of public wires: 13 171s Number of public wire bits: 107 171s Number of memories: 0 171s Number of memory bits: 0 171s Number of processes: 0 171s Number of cells: 103 171s SB_CARRY 28 171s SB_DFF 38 171s SB_LUT4 37 171s 171s 2.49. Executing CHECK pass (checking for obvious problems). 171s Checking module top... 171s Found and reported 0 problems. 171s 171s 2.50. Executing JSON backend. 171s 171s End of script. Logfile hash: a82be2095c, CPU: user 0.73s system 0.03s, MEM: 20.00 MB peak 171s Yosys 0.23 (git sha1 7ce5011c24b) 171s Time spent: 57% 13x read_verilog (0 sec), 17% 1x abc (0 sec), ... 171s nextpnr-ice40 --hx8k --package ct256 --asc example.asc --pcf hx8kboard.pcf --json example.json 171s Info: constrained 'LED0' to bel 'X7/Y33/io1' 171s Info: constrained 'LED1' to bel 'X6/Y33/io1' 171s Info: constrained 'LED2' to bel 'X5/Y33/io1' 171s Info: constrained 'LED3' to bel 'X4/Y33/io1' 171s Info: constrained 'LED4' to bel 'X4/Y33/io0' 171s Info: constrained 'LED5' to bel 'X3/Y33/io1' 171s Info: constrained 'LED6' to bel 'X3/Y33/io0' 171s Info: constrained 'LED7' to bel 'X1/Y33/io0' 171s Info: constrained 'clk' to bel 'X0/Y16/io1' 171s 171s Info: Packing constants.. 171s Info: Packing IOs.. 171s Info: Packing LUT-FFs.. 171s Info: 7 LCs used as LUT4 only 171s Info: 30 LCs used as LUT4 and DFF 171s Info: Packing non-LUT FFs.. 171s Info: 8 LCs used as DFF only 171s Info: Packing carries.. 171s Info: 0 LCs used as CARRY only 171s Info: Packing indirect carry+LUT pairs... 171s Info: 0 LUTs merged into carry LCs 171s Info: Packing RAMs.. 171s Info: Placing PLLs.. 171s Info: Packing special functions.. 171s Info: Packing PLLs.. 171s Info: Promoting globals.. 171s Info: promoting clk$SB_IO_IN (fanout 38) 171s Info: Constraining chains... 171s Info: 1 LCs used to legalise carry chains. 171s Info: Checksum: 0x74fa9ee4 171s 171s Info: Annotating ports with timing budgets for target frequency 12.00 MHz 171s Info: Checksum: 0x4df74e96 171s 171s Info: Device utilisation: 171s Info: ICESTORM_LC: 48/ 7680 0% 171s Info: ICESTORM_RAM: 0/ 32 0% 171s Info: SB_IO: 9/ 256 3% 171s Info: SB_GB: 1/ 8 12% 171s Info: ICESTORM_PLL: 0/ 2 0% 171s Info: SB_WARMBOOT: 0/ 1 0% 171s 171s Info: Placed 9 cells based on constraints. 171s Info: Creating initial analytic placement for 18 cells, random placement wirelen = 571. 171s Info: at initial placer iter 0, wirelen = 26 171s Info: at initial placer iter 1, wirelen = 21 171s Info: at initial placer iter 2, wirelen = 20 171s Info: at initial placer iter 3, wirelen = 21 171s Info: Running main analytical placer, max placement attempts per cell = 10000. 171s Info: at iteration #1, type ICESTORM_LC: wirelen solved = 20, spread = 50, legal = 50; time = 0.00s 171s Info: at iteration #1, type SB_GB: wirelen solved = 50, spread = 50, legal = 50; time = 0.00s 171s Info: at iteration #1, type ALL: wirelen solved = 20, spread = 45, legal = 49; time = 0.00s 171s Info: at iteration #2, type ICESTORM_LC: wirelen solved = 32, spread = 47, legal = 51; time = 0.00s 171s Info: at iteration #2, type SB_GB: wirelen solved = 51, spread = 51, legal = 51; time = 0.00s 171s Info: at iteration #2, type ALL: wirelen solved = 31, spread = 44, legal = 48; time = 0.00s 171s Info: at iteration #3, type ICESTORM_LC: wirelen solved = 29, spread = 58, legal = 62; time = 0.00s 171s Info: at iteration #3, type SB_GB: wirelen solved = 62, spread = 62, legal = 62; time = 0.00s 171s Info: at iteration #3, type ALL: wirelen solved = 27, spread = 60, legal = 62; time = 0.00s 171s Info: at iteration #4, type ICESTORM_LC: wirelen solved = 29, spread = 52, legal = 64; time = 0.00s 171s Info: at iteration #4, type SB_GB: wirelen solved = 64, spread = 64, legal = 64; time = 0.00s 171s Info: at iteration #4, type ALL: wirelen solved = 29, spread = 52, legal = 62; time = 0.00s 171s Info: at iteration #5, type ICESTORM_LC: wirelen solved = 30, spread = 53, legal = 60; time = 0.00s 171s Info: at iteration #5, type SB_GB: wirelen solved = 60, spread = 60, legal = 60; time = 0.00s 171s Info: at iteration #5, type ALL: wirelen solved = 30, spread = 53, legal = 57; time = 0.00s 171s Info: at iteration #6, type ICESTORM_LC: wirelen solved = 34, spread = 44, legal = 57; time = 0.00s 171s Info: at iteration #6, type SB_GB: wirelen solved = 57, spread = 57, legal = 57; time = 0.00s 171s Info: at iteration #6, type ALL: wirelen solved = 34, spread = 44, legal = 61; time = 0.00s 171s Info: at iteration #7, type ICESTORM_LC: wirelen solved = 34, spread = 44, legal = 59; time = 0.00s 171s Info: at iteration #7, type SB_GB: wirelen solved = 59, spread = 59, legal = 59; time = 0.00s 171s Info: at iteration #7, type ALL: wirelen solved = 34, spread = 44, legal = 57; time = 0.00s 171s Info: HeAP Placer Time: 0.03s 171s Info: of which solving equations: 0.03s 171s Info: of which spreading cells: 0.00s 171s Info: of which strict legalisation: 0.00s 171s 171s Info: Running simulated annealing placer for refinement. 171s Info: at iteration #1: temp = 0.000000, timing cost = 3, wirelen = 48 171s Info: at iteration #5: temp = 0.000000, timing cost = 4, wirelen = 33 171s Info: at iteration #10: temp = 0.000000, timing cost = 4, wirelen = 32 171s Info: at iteration #11: temp = 0.000000, timing cost = 4, wirelen = 32 171s Info: SA placement time 0.01s 171s 171s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 159.74 MHz (PASS at 12.00 MHz) 171s 171s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> : 2.72 ns 171s 171s Info: Slack histogram: 171s Info: legend: * represents 1 endpoint(s) 171s Info: + represents [1,1) endpoint(s) 171s Info: [ 77073, 77313) |** 171s Info: [ 77313, 77553) |** 171s Info: [ 77553, 77793) |** 171s Info: [ 77793, 78033) | 171s Info: [ 78033, 78273) |** 171s Info: [ 78273, 78513) |** 171s Info: [ 78513, 78753) |** 171s Info: [ 78753, 78993) |** 171s Info: [ 78993, 79233) | 171s Info: [ 79233, 79473) |** 171s Info: [ 79473, 79713) |* 171s Info: [ 79713, 79953) |** 171s Info: [ 79953, 80193) |*** 171s Info: [ 80193, 80433) | 171s Info: [ 80433, 80673) |** 171s Info: [ 80673, 80913) |*** 171s Info: [ 80913, 81153) |** 171s Info: [ 81153, 81393) |****** 171s Info: [ 81393, 81633) |* 171s Info: [ 81633, 81873) |*************************************** 171s Info: Checksum: 0xa7a876a4 171s 171s Info: Routing.. 171s Info: Setting up routing queue. 171s Info: Routing 126 arcs. 171s Info: | (re-)routed arcs | delta | remaining| time spent | 171s Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| 171s Info: 126 | 0 101 | 0 101 | 0| 0.01 0.01| 171s Info: Routing complete. 171s Info: Router1 time 0.01s 171s Info: Checksum: 0x3ab1ef41 171s 171s Info: Critical path report for clock 'clk$SB_IO_IN_$glb_clk' (posedge -> posedge): 171s Info: curr total 171s Info: 0.5 0.5 Source counter_SB_LUT4_I3_LC.O 171s Info: 0.6 1.1 Net counter[0] budget 78.411003 ns (2,29) -> (3,29) 171s Info: Sink $nextpnr_ICESTORM_LC_0.I1 171s Info: Defined in: 171s Info: example.v:20.14-20.25 171s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 171s Info: 0.3 1.4 Source $nextpnr_ICESTORM_LC_0.COUT 171s Info: 0.0 1.4 Net $nextpnr_ICESTORM_LC_0$O budget 0.000000 ns (3,29) -> (3,29) 171s Info: Sink counter_SB_LUT4_I2_26_LC.CIN 171s Info: 0.1 1.5 Source counter_SB_LUT4_I2_26_LC.COUT 171s Info: 0.0 1.5 Net counter_SB_CARRY_CI_CO[2] budget 0.000000 ns (3,29) -> (3,29) 171s Info: Sink counter_SB_LUT4_I2_15_LC.CIN 171s Info: Defined in: 171s Info: example.v:20.14-20.25 171s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 171s Info: 0.1 1.6 Source counter_SB_LUT4_I2_15_LC.COUT 171s Info: 0.0 1.6 Net counter_SB_CARRY_CI_CO[3] budget 0.000000 ns (3,29) -> (3,29) 171s Info: Sink counter_SB_LUT4_I2_14_LC.CIN 171s Info: Defined in: 171s Info: example.v:20.14-20.25 171s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 171s Info: 0.1 1.8 Source counter_SB_LUT4_I2_14_LC.COUT 171s Info: 0.0 1.8 Net counter_SB_CARRY_CI_CO[4] budget 0.000000 ns (3,29) -> (3,29) 171s Info: Sink counter_SB_LUT4_I2_13_LC.CIN 171s Info: Defined in: 171s Info: example.v:20.14-20.25 171s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 171s Info: 0.1 1.9 Source counter_SB_LUT4_I2_13_LC.COUT 171s Info: 0.0 1.9 Net counter_SB_CARRY_CI_CO[5] budget 0.000000 ns (3,29) -> (3,29) 171s Info: Sink counter_SB_LUT4_I2_12_LC.CIN 171s Info: Defined in: 171s Info: example.v:20.14-20.25 171s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 171s Info: 0.1 2.0 Source counter_SB_LUT4_I2_12_LC.COUT 171s Info: 0.0 2.0 Net counter_SB_CARRY_CI_CO[6] budget 0.000000 ns (3,29) -> (3,29) 171s Info: Sink counter_SB_LUT4_I2_11_LC.CIN 171s Info: Defined in: 171s Info: example.v:20.14-20.25 171s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 171s Info: 0.1 2.1 Source counter_SB_LUT4_I2_11_LC.COUT 171s Info: 0.0 2.1 Net counter_SB_CARRY_CI_CO[7] budget 0.000000 ns (3,29) -> (3,29) 171s Info: Sink counter_SB_LUT4_I2_10_LC.CIN 171s Info: Defined in: 171s Info: example.v:20.14-20.25 171s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 171s Info: 0.1 2.3 Source counter_SB_LUT4_I2_10_LC.COUT 171s Info: 0.2 2.5 Net counter_SB_CARRY_CI_CO[8] budget 0.190000 ns (3,29) -> (3,30) 171s Info: Sink counter_SB_LUT4_I2_9_LC.CIN 171s Info: Defined in: 171s Info: example.v:20.14-20.25 171s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 171s Info: 0.1 2.6 Source counter_SB_LUT4_I2_9_LC.COUT 171s Info: 0.0 2.6 Net counter_SB_CARRY_CI_CO[9] budget 0.000000 ns (3,30) -> (3,30) 171s Info: Sink counter_SB_LUT4_I2_8_LC.CIN 171s Info: Defined in: 171s Info: example.v:20.14-20.25 171s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 171s Info: 0.1 2.7 Source counter_SB_LUT4_I2_8_LC.COUT 171s Info: 0.0 2.7 Net counter_SB_CARRY_CI_CO[10] budget 0.000000 ns (3,30) -> (3,30) 171s Info: Sink counter_SB_LUT4_I2_7_LC.CIN 171s Info: Defined in: 171s Info: example.v:20.14-20.25 171s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 171s Info: 0.1 2.8 Source counter_SB_LUT4_I2_7_LC.COUT 171s Info: 0.0 2.8 Net counter_SB_CARRY_CI_CO[11] budget 0.000000 ns (3,30) -> (3,30) 171s Info: Sink counter_SB_LUT4_I2_6_LC.CIN 171s Info: Defined in: 171s Info: example.v:20.14-20.25 171s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 171s Info: 0.1 3.0 Source counter_SB_LUT4_I2_6_LC.COUT 171s Info: 0.0 3.0 Net counter_SB_CARRY_CI_CO[12] budget 0.000000 ns (3,30) -> (3,30) 171s Info: Sink counter_SB_LUT4_I2_5_LC.CIN 171s Info: Defined in: 171s Info: example.v:20.14-20.25 171s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 171s Info: 0.1 3.1 Source counter_SB_LUT4_I2_5_LC.COUT 171s Info: 0.0 3.1 Net counter_SB_CARRY_CI_CO[13] budget 0.000000 ns (3,30) -> (3,30) 171s Info: Sink counter_SB_LUT4_I2_4_LC.CIN 171s Info: Defined in: 171s Info: example.v:20.14-20.25 171s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 171s Info: 0.1 3.2 Source counter_SB_LUT4_I2_4_LC.COUT 171s Info: 0.0 3.2 Net counter_SB_CARRY_CI_CO[14] budget 0.000000 ns (3,30) -> (3,30) 171s Info: Sink counter_SB_LUT4_I2_3_LC.CIN 171s Info: Defined in: 171s Info: example.v:20.14-20.25 171s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 171s Info: 0.1 3.3 Source counter_SB_LUT4_I2_3_LC.COUT 171s Info: 0.0 3.3 Net counter_SB_CARRY_CI_CO[15] budget 0.000000 ns (3,30) -> (3,30) 171s Info: Sink counter_SB_LUT4_I2_2_LC.CIN 171s Info: Defined in: 171s Info: example.v:20.14-20.25 171s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 171s Info: 0.1 3.5 Source counter_SB_LUT4_I2_2_LC.COUT 171s Info: 0.2 3.7 Net counter_SB_CARRY_CI_CO[16] budget 0.190000 ns (3,30) -> (3,31) 171s Info: Sink counter_SB_LUT4_I2_1_LC.CIN 171s Info: Defined in: 171s Info: example.v:20.14-20.25 171s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 171s Info: 0.1 3.8 Source counter_SB_LUT4_I2_1_LC.COUT 171s Info: 0.0 3.8 Net counter_SB_CARRY_CI_CO[17] budget 0.000000 ns (3,31) -> (3,31) 171s Info: Sink counter_SB_LUT4_I2_LC.CIN 171s Info: Defined in: 171s Info: example.v:20.14-20.25 171s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 171s Info: 0.1 3.9 Source counter_SB_LUT4_I2_LC.COUT 171s Info: 0.0 3.9 Net counter_SB_CARRY_CI_CO[18] budget 0.000000 ns (3,31) -> (3,31) 171s Info: Sink counter_SB_LUT4_I2_28_LC.CIN 171s Info: Defined in: 171s Info: example.v:20.14-20.25 171s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 171s Info: 0.1 4.0 Source counter_SB_LUT4_I2_28_LC.COUT 171s Info: 0.0 4.0 Net counter_SB_CARRY_CI_CO[19] budget 0.000000 ns (3,31) -> (3,31) 171s Info: Sink counter_SB_LUT4_I2_27_LC.CIN 171s Info: Defined in: 171s Info: example.v:20.14-20.25 171s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 171s Info: 0.1 4.2 Source counter_SB_LUT4_I2_27_LC.COUT 171s Info: 0.0 4.2 Net counter_SB_CARRY_CI_CO[20] budget 0.000000 ns (3,31) -> (3,31) 171s Info: Sink counter_SB_LUT4_I2_25_LC.CIN 171s Info: Defined in: 171s Info: example.v:20.14-20.25 171s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 171s Info: 0.1 4.3 Source counter_SB_LUT4_I2_25_LC.COUT 171s Info: 0.0 4.3 Net counter_SB_CARRY_CI_CO[21] budget 0.000000 ns (3,31) -> (3,31) 171s Info: Sink counter_SB_LUT4_I2_24_LC.CIN 171s Info: Defined in: 171s Info: example.v:20.14-20.25 171s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 171s Info: 0.1 4.4 Source counter_SB_LUT4_I2_24_LC.COUT 171s Info: 0.0 4.4 Net counter_SB_CARRY_CI_CO[22] budget 0.000000 ns (3,31) -> (3,31) 171s Info: Sink counter_SB_LUT4_I2_23_LC.CIN 171s Info: Defined in: 171s Info: example.v:20.14-20.25 171s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 171s Info: 0.1 4.6 Source counter_SB_LUT4_I2_23_LC.COUT 171s Info: 0.0 4.6 Net counter_SB_CARRY_CI_CO[23] budget 0.000000 ns (3,31) -> (3,31) 171s Info: Sink counter_SB_LUT4_I2_22_LC.CIN 171s Info: Defined in: 171s Info: example.v:20.14-20.25 171s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 171s Info: 0.1 4.7 Source counter_SB_LUT4_I2_22_LC.COUT 171s Info: 0.2 4.9 Net counter_SB_CARRY_CI_CO[24] budget 0.190000 ns (3,31) -> (3,32) 171s Info: Sink counter_SB_LUT4_I2_21_LC.CIN 171s Info: Defined in: 171s Info: example.v:20.14-20.25 171s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 171s Info: 0.1 5.0 Source counter_SB_LUT4_I2_21_LC.COUT 171s Info: 0.0 5.0 Net counter_SB_CARRY_CI_CO[25] budget 0.000000 ns (3,32) -> (3,32) 171s Info: Sink counter_SB_LUT4_I2_20_LC.CIN 171s Info: Defined in: 171s Info: example.v:20.14-20.25 171s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 171s Info: 0.1 5.1 Source counter_SB_LUT4_I2_20_LC.COUT 171s Info: 0.0 5.1 Net counter_SB_CARRY_CI_CO[26] budget 0.000000 ns (3,32) -> (3,32) 171s Info: Sink counter_SB_LUT4_I2_19_LC.CIN 171s Info: Defined in: 171s Info: example.v:20.14-20.25 171s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 171s Info: 0.1 5.3 Source counter_SB_LUT4_I2_19_LC.COUT 171s Info: 0.0 5.3 Net counter_SB_CARRY_CI_CO[27] budget 0.000000 ns (3,32) -> (3,32) 171s Info: Sink counter_SB_LUT4_I2_18_LC.CIN 171s Info: Defined in: 171s Info: example.v:20.14-20.25 171s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 171s Info: 0.1 5.4 Source counter_SB_LUT4_I2_18_LC.COUT 171s Info: 0.0 5.4 Net counter_SB_CARRY_CI_CO[28] budget 0.000000 ns (3,32) -> (3,32) 171s Info: Sink counter_SB_LUT4_I2_17_LC.CIN 171s Info: Defined in: 171s Info: example.v:20.14-20.25 171s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 171s Info: 0.1 5.5 Source counter_SB_LUT4_I2_17_LC.COUT 171s Info: 0.3 5.8 Net counter_SB_CARRY_CI_CO[29] budget 0.260000 ns (3,32) -> (3,32) 171s Info: Sink counter_SB_LUT4_I2_16_LC.I3 171s Info: Defined in: 171s Info: example.v:20.14-20.25 171s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 171s Info: 0.3 6.1 Setup counter_SB_LUT4_I2_16_LC.I3 171s Info: 4.7 ns logic, 1.4 ns routing 171s 171s Info: Critical path report for cross-domain path 'posedge clk$SB_IO_IN_$glb_clk' -> '': 171s Info: curr total 171s Info: 0.5 0.5 Source outcnt_SB_DFF_Q_DFFLC.O 171s Info: 1.2 1.8 Net outcnt[6] budget 41.208000 ns (3,32) -> (6,32) 171s Info: Sink LED1_SB_LUT4_O_LC.I2 171s Info: Defined in: 171s Info: example.v:17.17-17.23 171s Info: 0.4 2.1 Source LED1_SB_LUT4_O_LC.O 171s Info: 0.6 2.7 Net LED1$SB_IO_OUT budget 41.207001 ns (6,32) -> (6,33) 171s Info: Sink LED1$sb_io.D_OUT_0 171s Info: Defined in: 171s Info: example.v:4.9-4.13 171s Info: 0.9 ns logic, 1.8 ns routing 171s 171s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 163.99 MHz (PASS at 12.00 MHz) 171s 171s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> : 2.72 ns 171s 171s Info: Slack histogram: 171s Info: legend: * represents 1 endpoint(s) 171s Info: + represents [1,1) endpoint(s) 171s Info: [ 77235, 77467) |** 171s Info: [ 77467, 77699) |** 171s Info: [ 77699, 77931) |** 171s Info: [ 77931, 78163) | 171s Info: [ 78163, 78395) |** 171s Info: [ 78395, 78627) |** 171s Info: [ 78627, 78859) |** 171s Info: [ 78859, 79091) |** 171s Info: [ 79091, 79323) | 171s Info: [ 79323, 79555) |** 171s Info: [ 79555, 79787) |** 171s Info: [ 79787, 80019) |* 171s Info: [ 80019, 80251) |*** 171s Info: [ 80251, 80483) | 171s Info: [ 80483, 80715) |** 171s Info: [ 80715, 80947) |** 171s Info: [ 80947, 81179) |*** 171s Info: [ 81179, 81411) |****** 171s Info: [ 81411, 81643) |* 171s Info: [ 81643, 81875) |*************************************** 171s 171s Info: Program finished normally. 171s icetime -d hx8k -mtr example.rpt example.asc 171s // Reading input .asc file.. 171s // Reading 8k chipdb file.. 173s // Creating timing netlist.. 173s // Timing estimate: 6.09 ns (164.22 MHz) 173s icepack example.asc example.bin 173s make: Leaving directory '/tmp/autopkgtest.rlxjW8/build.dCN/src/examples/hx8kboard' 173s make: Entering directory '/tmp/autopkgtest.rlxjW8/build.dCN/src/examples/iceblink' 173s yosys -p 'synth_ice40 -top top -json example.json' example.v 173s 173s /----------------------------------------------------------------------------\ 173s | | 173s | yosys -- Yosys Open SYnthesis Suite | 173s | | 173s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 173s | | 173s | Permission to use, copy, modify, and/or distribute this software for any | 173s | purpose with or without fee is hereby granted, provided that the above | 173s | copyright notice and this permission notice appear in all copies. | 173s | | 173s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 173s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 173s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 173s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 173s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 173s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 173s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 173s | | 173s \----------------------------------------------------------------------------/ 173s 173s Yosys 0.23 (git sha1 7ce5011c24b) 173s 173s 173s -- Parsing `example.v' using frontend ` -vlog2k' -- 173s 173s 1. Executing Verilog-2005 frontend: example.v 173s Parsing Verilog input from `example.v' to AST representation. 173s Storing AST representation for module `$abstract\top'. 173s Successfully finished Verilog frontend. 173s 173s -- Running command `synth_ice40 -top top -json example.json' -- 173s 173s 2. Executing SYNTH_ICE40 pass. 173s 173s 2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v 173s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation. 173s Generating RTLIL representation for module `\SB_IO'. 173s Generating RTLIL representation for module `\SB_GB_IO'. 173s Generating RTLIL representation for module `\SB_GB'. 173s Generating RTLIL representation for module `\SB_LUT4'. 173s Generating RTLIL representation for module `\SB_CARRY'. 173s Generating RTLIL representation for module `\SB_DFF'. 173s Generating RTLIL representation for module `\SB_DFFE'. 173s Generating RTLIL representation for module `\SB_DFFSR'. 173s Generating RTLIL representation for module `\SB_DFFR'. 173s Generating RTLIL representation for module `\SB_DFFSS'. 173s Generating RTLIL representation for module `\SB_DFFS'. 173s Generating RTLIL representation for module `\SB_DFFESR'. 173s Generating RTLIL representation for module `\SB_DFFER'. 173s Generating RTLIL representation for module `\SB_DFFESS'. 173s Generating RTLIL representation for module `\SB_DFFES'. 173s Generating RTLIL representation for module `\SB_DFFN'. 173s Generating RTLIL representation for module `\SB_DFFNE'. 173s Generating RTLIL representation for module `\SB_DFFNSR'. 173s Generating RTLIL representation for module `\SB_DFFNR'. 173s Generating RTLIL representation for module `\SB_DFFNSS'. 173s Generating RTLIL representation for module `\SB_DFFNS'. 173s Generating RTLIL representation for module `\SB_DFFNESR'. 173s Generating RTLIL representation for module `\SB_DFFNER'. 173s Generating RTLIL representation for module `\SB_DFFNESS'. 173s Generating RTLIL representation for module `\SB_DFFNES'. 173s Generating RTLIL representation for module `\SB_RAM40_4K'. 173s Generating RTLIL representation for module `\SB_RAM40_4KNR'. 173s Generating RTLIL representation for module `\SB_RAM40_4KNW'. 173s Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. 173s Generating RTLIL representation for module `\ICESTORM_LC'. 173s Generating RTLIL representation for module `\SB_PLL40_CORE'. 173s Generating RTLIL representation for module `\SB_PLL40_PAD'. 173s Generating RTLIL representation for module `\SB_PLL40_2_PAD'. 173s Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. 173s Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. 173s Generating RTLIL representation for module `\SB_WARMBOOT'. 173s Generating RTLIL representation for module `\SB_SPRAM256KA'. 173s Generating RTLIL representation for module `\SB_HFOSC'. 173s Generating RTLIL representation for module `\SB_LFOSC'. 173s Generating RTLIL representation for module `\SB_RGBA_DRV'. 173s Generating RTLIL representation for module `\SB_LED_DRV_CUR'. 173s Generating RTLIL representation for module `\SB_RGB_DRV'. 173s Generating RTLIL representation for module `\SB_I2C'. 173s Generating RTLIL representation for module `\SB_SPI'. 173s Generating RTLIL representation for module `\SB_LEDDA_IP'. 173s Generating RTLIL representation for module `\SB_FILTER_50NS'. 173s Generating RTLIL representation for module `\SB_IO_I3C'. 173s Generating RTLIL representation for module `\SB_IO_OD'. 173s Generating RTLIL representation for module `\SB_MAC16'. 173s Generating RTLIL representation for module `\ICESTORM_RAM'. 173s Successfully finished Verilog frontend. 173s 173s 2.2. Executing HIERARCHY pass (managing design hierarchy). 173s 173s 2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\top'. 173s Generating RTLIL representation for module `\top'. 173s 173s 2.3.1. Analyzing design hierarchy.. 173s Top module: \top 173s 173s 2.3.2. Analyzing design hierarchy.. 173s Top module: \top 173s Removing unused module `$abstract\top'. 173s Removed 1 unused modules. 173s 173s 2.4. Executing PROC pass (convert processes to netlists). 173s 173s 2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 173s Cleaned up 0 empty switches. 173s 173s 2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 173s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241 in module SB_DFFNES. 173s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234 in module SB_DFFNESS. 173s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230 in module SB_DFFNER. 173s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223 in module SB_DFFNESR. 173s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220 in module SB_DFFNS. 173s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217 in module SB_DFFNSS. 173s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214 in module SB_DFFNR. 173s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211 in module SB_DFFNSR. 173s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203 in module SB_DFFES. 173s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196 in module SB_DFFESS. 173s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192 in module SB_DFFER. 173s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185 in module SB_DFFESR. 173s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182 in module SB_DFFS. 173s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179 in module SB_DFFSS. 173s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176 in module SB_DFFR. 173s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173 in module SB_DFFSR. 173s Removed a total of 0 dead cases. 173s 173s 2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 173s Removed 8 redundant assignments. 173s Promoted 25 assignments to connections. 173s 173s 2.4.4. Executing PROC_INIT pass (extract init attributes). 173s Found init rule in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 173s Set init value: \Q = 1'0 173s Found init rule in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 173s Set init value: \Q = 1'0 173s Found init rule in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 173s Set init value: \Q = 1'0 173s Found init rule in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 173s Set init value: \Q = 1'0 173s Found init rule in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 173s Set init value: \Q = 1'0 173s Found init rule in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 173s Set init value: \Q = 1'0 173s Found init rule in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 173s Set init value: \Q = 1'0 173s Found init rule in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 173s Set init value: \Q = 1'0 173s Found init rule in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 173s Set init value: \Q = 1'0 173s Found init rule in `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 173s Set init value: \Q = 1'0 173s Found init rule in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 173s Set init value: \Q = 1'0 173s Found init rule in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 173s Set init value: \Q = 1'0 173s Found init rule in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 173s Set init value: \Q = 1'0 173s Found init rule in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 173s Set init value: \Q = 1'0 173s Found init rule in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 173s Set init value: \Q = 1'0 173s Found init rule in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 173s Set init value: \Q = 1'0 173s Found init rule in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 173s Set init value: \Q = 1'0 173s Found init rule in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 173s Set init value: \Q = 1'0 173s Found init rule in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 173s Set init value: \Q = 1'0 173s Found init rule in `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 173s Set init value: \Q = 1'0 173s Found init rule in `\top.$proc$example.v:15$384'. 173s Set init value: \counter = 26'00000000000000000000000000 173s 173s 2.4.5. Executing PROC_ARST pass (detect async resets in processes). 173s Found async reset \S in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 173s Found async reset \R in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 173s Found async reset \S in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 173s Found async reset \R in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 173s Found async reset \S in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 173s Found async reset \R in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 173s Found async reset \S in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 173s Found async reset \R in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 173s 173s 2.4.6. Executing PROC_ROM pass (convert switches to ROMs). 173s Converted 0 switches. 173s 173s 173s 2.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 173s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 173s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 173s 1/1: $0\Q[0:0] 173s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 173s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 173s 1/1: $0\Q[0:0] 173s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 173s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 173s 1/1: $0\Q[0:0] 173s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 173s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 173s 1/1: $0\Q[0:0] 173s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 173s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 173s 1/1: $0\Q[0:0] 173s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 173s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 173s 1/1: $0\Q[0:0] 173s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 173s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 173s 1/1: $0\Q[0:0] 173s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 173s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 173s 1/1: $0\Q[0:0] 173s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 173s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 173s 1/1: $0\Q[0:0] 173s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 173s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 173s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 173s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 173s 1/1: $0\Q[0:0] 173s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 173s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 173s 1/1: $0\Q[0:0] 173s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 173s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 173s 1/1: $0\Q[0:0] 173s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 173s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 173s 1/1: $0\Q[0:0] 173s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 173s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 173s 1/1: $0\Q[0:0] 173s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 173s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 173s 1/1: $0\Q[0:0] 173s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 173s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 173s 1/1: $0\Q[0:0] 173s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 173s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 173s 1/1: $0\Q[0:0] 173s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 173s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 173s 1/1: $0\Q[0:0] 173s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 173s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 173s Creating decoders for process `\top.$proc$example.v:15$384'. 173s Creating decoders for process `\top.$proc$example.v:18$381'. 173s 173s 2.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). 173s 173s 2.4.9. Executing PROC_DFF pass (convert process syncs to FFs). 173s Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 173s created $adff cell `$procdff$429' with negative edge clock and positive level reset. 173s Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 173s created $dff cell `$procdff$430' with negative edge clock. 173s Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 173s created $adff cell `$procdff$431' with negative edge clock and positive level reset. 173s Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 173s created $dff cell `$procdff$432' with negative edge clock. 173s Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 173s created $adff cell `$procdff$433' with negative edge clock and positive level reset. 173s Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 173s created $dff cell `$procdff$434' with negative edge clock. 173s Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 173s created $adff cell `$procdff$435' with negative edge clock and positive level reset. 173s Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 173s created $dff cell `$procdff$436' with negative edge clock. 173s Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 173s created $dff cell `$procdff$437' with negative edge clock. 173s Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 173s created $dff cell `$procdff$438' with negative edge clock. 173s Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 173s created $adff cell `$procdff$439' with positive edge clock and positive level reset. 173s Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 173s created $dff cell `$procdff$440' with positive edge clock. 173s Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 173s created $adff cell `$procdff$441' with positive edge clock and positive level reset. 173s Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 173s created $dff cell `$procdff$442' with positive edge clock. 173s Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 173s created $adff cell `$procdff$443' with positive edge clock and positive level reset. 173s Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 173s created $dff cell `$procdff$444' with positive edge clock. 173s Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 173s created $adff cell `$procdff$445' with positive edge clock and positive level reset. 173s Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 173s created $dff cell `$procdff$446' with positive edge clock. 173s Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 173s created $dff cell `$procdff$447' with positive edge clock. 173s Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 173s created $dff cell `$procdff$448' with positive edge clock. 173s Creating register for signal `\top.\counter' using process `\top.$proc$example.v:18$381'. 173s created $dff cell `$procdff$449' with positive edge clock. 173s Creating register for signal `\top.\outcnt' using process `\top.$proc$example.v:18$381'. 173s created $dff cell `$procdff$450' with positive edge clock. 173s 173s 2.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 173s 173s 2.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 173s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 173s Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 173s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 173s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 173s Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 173s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 173s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 173s Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 173s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 173s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 173s Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 173s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 173s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 173s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 173s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 173s Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 173s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 173s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 173s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 173s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 173s Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 173s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 173s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 173s Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 173s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 173s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 173s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 173s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 173s Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 173s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 173s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 173s Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 173s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 173s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 173s Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 173s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 173s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 173s Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 173s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 173s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 173s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 173s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 173s Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 173s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 173s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 173s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 173s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 173s Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 173s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 173s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 173s Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 173s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 173s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 173s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 173s Removing empty process `top.$proc$example.v:15$384'. 173s Removing empty process `top.$proc$example.v:18$381'. 173s Cleaned up 18 empty switches. 173s 173s 2.4.12. Executing OPT_EXPR pass (perform const folding). 173s Optimizing module top. 173s 173s 173s 2.5. Executing FLATTEN pass (flatten design). 173s 173s 2.6. Executing TRIBUF pass. 173s 173s 2.7. Executing DEMINOUT pass (demote inout ports to input or output). 173s 173s 2.8. Executing OPT_EXPR pass (perform const folding). 173s Optimizing module top. 173s 173s 2.9. Executing OPT_CLEAN pass (remove unused cells and wires). 173s Finding unused cells or wires in module \top.. 173s Removed 0 unused cells and 3 unused wires. 173s 173s 173s 2.10. Executing CHECK pass (checking for obvious problems). 173s Checking module top... 173s Found and reported 0 problems. 173s 173s 2.11. Executing OPT pass (performing simple optimizations). 173s 173s 2.11.1. Executing OPT_EXPR pass (perform const folding). 173s Optimizing module top. 173s 173s 2.11.2. Executing OPT_MERGE pass (detect identical cells). 173s Finding identical cells in module `\top'. 173s Removed a total of 0 cells. 173s 173s 2.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 173s Running muxtree optimizer on module \top.. 173s Creating internal representation of mux trees. 173s No muxes found in this module. 173s Removed 0 multiplexer ports. 173s 173s 2.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 173s Optimizing cells in module \top. 173s Performed a total of 0 changes. 173s 173s 2.11.5. Executing OPT_MERGE pass (detect identical cells). 173s Finding identical cells in module `\top'. 173s Removed a total of 0 cells. 173s 173s 2.11.6. Executing OPT_DFF pass (perform DFF optimizations). 173s 173s 2.11.7. Executing OPT_CLEAN pass (remove unused cells and wires). 173s Finding unused cells or wires in module \top.. 173s 173s 2.11.8. Executing OPT_EXPR pass (perform const folding). 173s Optimizing module top. 173s 173s 2.11.9. Finished OPT passes. (There is nothing left to do.) 173s 173s 2.12. Executing FSM pass (extract and optimize FSM). 173s 173s 2.12.1. Executing FSM_DETECT pass (finding FSMs in design). 173s 173s 2.12.2. Executing FSM_EXTRACT pass (extracting FSM from design). 173s 173s 2.12.3. Executing FSM_OPT pass (simple optimizations of FSMs). 173s 173s 2.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). 173s Finding unused cells or wires in module \top.. 173s 173s 2.12.5. Executing FSM_OPT pass (simple optimizations of FSMs). 173s 173s 2.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 173s 173s 2.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 173s 173s 2.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 173s 173s 2.13. Executing OPT pass (performing simple optimizations). 173s 173s 2.13.1. Executing OPT_EXPR pass (perform const folding). 173s Optimizing module top. 173s 173s 2.13.2. Executing OPT_MERGE pass (detect identical cells). 173s Finding identical cells in module `\top'. 173s Removed a total of 0 cells. 173s 173s 2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 173s Running muxtree optimizer on module \top.. 173s Creating internal representation of mux trees. 173s No muxes found in this module. 173s Removed 0 multiplexer ports. 173s 173s 2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 173s Optimizing cells in module \top. 173s Performed a total of 0 changes. 173s 173s 2.13.5. Executing OPT_MERGE pass (detect identical cells). 173s Finding identical cells in module `\top'. 173s Removed a total of 0 cells. 173s 173s 2.13.6. Executing OPT_DFF pass (perform DFF optimizations). 173s 173s 2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). 173s Finding unused cells or wires in module \top.. 173s 173s 2.13.8. Executing OPT_EXPR pass (perform const folding). 173s Optimizing module top. 173s 173s 2.13.9. Finished OPT passes. (There is nothing left to do.) 173s 173s 2.14. Executing WREDUCE pass (reducing word size of cells). 173s Removed top 31 bits (of 32) from port B of cell top.$add$example.v:19$382 ($add). 173s Removed top 6 bits (of 32) from port Y of cell top.$add$example.v:19$382 ($add). 173s 173s 2.15. Executing PEEPOPT pass (run peephole optimizers). 173s 173s 2.16. Executing OPT_CLEAN pass (remove unused cells and wires). 173s Finding unused cells or wires in module \top.. 173s Removed 0 unused cells and 1 unused wires. 173s 173s 173s 2.17. Executing SHARE pass (SAT-based resource sharing). 173s 173s 2.18. Executing TECHMAP pass (map to technology primitives). 173s 173s 2.18.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v 173s Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation. 173s Generating RTLIL representation for module `\_90_lut_cmp_'. 173s Successfully finished Verilog frontend. 173s 173s 2.18.2. Continuing TECHMAP pass. 173s No more expansions possible. 173s 173s 173s 2.19. Executing OPT_EXPR pass (perform const folding). 173s Optimizing module top. 173s 173s 2.20. Executing OPT_CLEAN pass (remove unused cells and wires). 173s Finding unused cells or wires in module \top.. 173s 173s 2.21. Executing ALUMACC pass (create $alu and $macc cells). 173s Extracting $alu and $macc cells in module top: 173s creating $macc model for $add$example.v:19$382 ($add). 173s creating $alu model for $macc $add$example.v:19$382. 173s creating $alu cell for $add$example.v:19$382: $auto$alumacc.cc:485:replace_alu$452 173s created 1 $alu and 0 $macc cells. 173s 173s 2.22. Executing OPT pass (performing simple optimizations). 173s 173s 2.22.1. Executing OPT_EXPR pass (perform const folding). 173s Optimizing module top. 173s 173s 2.22.2. Executing OPT_MERGE pass (detect identical cells). 173s Finding identical cells in module `\top'. 173s Removed a total of 0 cells. 173s 173s 2.22.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 173s Running muxtree optimizer on module \top.. 173s Creating internal representation of mux trees. 173s No muxes found in this module. 173s Removed 0 multiplexer ports. 173s 173s 2.22.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 173s Optimizing cells in module \top. 173s Performed a total of 0 changes. 173s 173s 2.22.5. Executing OPT_MERGE pass (detect identical cells). 173s Finding identical cells in module `\top'. 173s Removed a total of 0 cells. 173s 173s 2.22.6. Executing OPT_DFF pass (perform DFF optimizations). 173s 173s 2.22.7. Executing OPT_CLEAN pass (remove unused cells and wires). 173s Finding unused cells or wires in module \top.. 173s 173s 2.22.8. Executing OPT_EXPR pass (perform const folding). 173s Optimizing module top. 173s 173s 2.22.9. Finished OPT passes. (There is nothing left to do.) 173s 173s 2.23. Executing MEMORY pass. 173s 173s 2.23.1. Executing OPT_MEM pass (optimize memories). 173s Performed a total of 0 transformations. 173s 173s 2.23.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). 173s Performed a total of 0 transformations. 173s 173s 2.23.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 173s 173s 2.23.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 173s 173s 2.23.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 173s 173s 2.23.6. Executing OPT_CLEAN pass (remove unused cells and wires). 173s Finding unused cells or wires in module \top.. 173s 173s 2.23.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 173s 173s 2.23.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). 173s Performed a total of 0 transformations. 173s 173s 2.23.9. Executing OPT_CLEAN pass (remove unused cells and wires). 173s Finding unused cells or wires in module \top.. 173s 173s 2.23.10. Executing MEMORY_COLLECT pass (generating $mem cells). 173s 173s 2.24. Executing OPT_CLEAN pass (remove unused cells and wires). 173s Finding unused cells or wires in module \top.. 173s 173s 2.25. Executing MEMORY_LIBMAP pass (mapping memories to cells). 173s 173s 2.26. Executing TECHMAP pass (map to technology primitives). 173s 173s 2.26.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v 173s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation. 173s Generating RTLIL representation for module `\$__ICE40_RAM4K_'. 173s Successfully finished Verilog frontend. 173s 173s 2.26.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/spram_map.v 173s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/spram_map.v' to AST representation. 173s Generating RTLIL representation for module `\$__ICE40_SPRAM_'. 173s Successfully finished Verilog frontend. 173s 173s 2.26.3. Continuing TECHMAP pass. 173s No more expansions possible. 173s 173s 173s 2.27. Executing ICE40_BRAMINIT pass. 173s 173s 2.28. Executing OPT pass (performing simple optimizations). 173s 173s 2.28.1. Executing OPT_EXPR pass (perform const folding). 173s Optimizing module top. 173s 173s 2.28.2. Executing OPT_MERGE pass (detect identical cells). 173s Finding identical cells in module `\top'. 173s Removed a total of 0 cells. 173s 173s 2.28.3. Executing OPT_DFF pass (perform DFF optimizations). 173s 173s 2.28.4. Executing OPT_CLEAN pass (remove unused cells and wires). 173s Finding unused cells or wires in module \top.. 173s 173s 2.28.5. Finished fast OPT passes. 173s 173s 2.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 173s 173s 2.30. Executing OPT pass (performing simple optimizations). 173s 173s 2.30.1. Executing OPT_EXPR pass (perform const folding). 173s Optimizing module top. 173s 173s 2.30.2. Executing OPT_MERGE pass (detect identical cells). 173s Finding identical cells in module `\top'. 173s Removed a total of 0 cells. 173s 173s 2.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 173s Running muxtree optimizer on module \top.. 173s Creating internal representation of mux trees. 173s No muxes found in this module. 173s Removed 0 multiplexer ports. 173s 173s 2.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 173s Optimizing cells in module \top. 173s Performed a total of 0 changes. 173s 173s 2.30.5. Executing OPT_MERGE pass (detect identical cells). 173s Finding identical cells in module `\top'. 173s Removed a total of 0 cells. 173s 173s 2.30.6. Executing OPT_DFF pass (perform DFF optimizations). 173s 173s 2.30.7. Executing OPT_CLEAN pass (remove unused cells and wires). 173s Finding unused cells or wires in module \top.. 173s 173s 2.30.8. Executing OPT_EXPR pass (perform const folding). 173s Optimizing module top. 173s 173s 2.30.9. Finished OPT passes. (There is nothing left to do.) 173s 173s 2.31. Executing ICE40_WRAPCARRY pass (wrap carries). 173s 173s 2.32. Executing TECHMAP pass (map to technology primitives). 173s 173s 2.32.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v 173s Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation. 173s Generating RTLIL representation for module `\_90_simplemap_bool_ops'. 173s Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. 173s Generating RTLIL representation for module `\_90_simplemap_logic_ops'. 173s Generating RTLIL representation for module `\_90_simplemap_compare_ops'. 173s Generating RTLIL representation for module `\_90_simplemap_various'. 173s Generating RTLIL representation for module `\_90_simplemap_registers'. 173s Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. 173s Generating RTLIL representation for module `\_90_shift_shiftx'. 173s Generating RTLIL representation for module `\_90_fa'. 173s Generating RTLIL representation for module `\_90_lcu'. 173s Generating RTLIL representation for module `\_90_alu'. 173s Generating RTLIL representation for module `\_90_macc'. 173s Generating RTLIL representation for module `\_90_alumacc'. 173s Generating RTLIL representation for module `\$__div_mod_u'. 173s Generating RTLIL representation for module `\$__div_mod_trunc'. 173s Generating RTLIL representation for module `\_90_div'. 173s Generating RTLIL representation for module `\_90_mod'. 173s Generating RTLIL representation for module `\$__div_mod_floor'. 173s Generating RTLIL representation for module `\_90_divfloor'. 173s Generating RTLIL representation for module `\_90_modfloor'. 173s Generating RTLIL representation for module `\_90_pow'. 173s Generating RTLIL representation for module `\_90_pmux'. 173s Generating RTLIL representation for module `\_90_demux'. 173s Generating RTLIL representation for module `\_90_lut'. 173s Successfully finished Verilog frontend. 173s 173s 2.32.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v 173s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation. 173s Generating RTLIL representation for module `\_80_ice40_alu'. 173s Successfully finished Verilog frontend. 173s 173s 2.32.3. Continuing TECHMAP pass. 173s Using template $paramod$a8151eed7df109f18d5adf1169b40bb7b9e884a8\_80_ice40_alu for cells of type $alu. 173s Using extmapper simplemap for cells of type $dff. 173s Using extmapper simplemap for cells of type $xor. 173s Using extmapper simplemap for cells of type $mux. 173s Using extmapper simplemap for cells of type $not. 173s Using extmapper simplemap for cells of type $pos. 173s No more expansions possible. 173s 173s 173s 2.33. Executing OPT pass (performing simple optimizations). 173s 173s 2.33.1. Executing OPT_EXPR pass (perform const folding). 173s Optimizing module top. 173s 173s 173s 2.33.2. Executing OPT_MERGE pass (detect identical cells). 173s Finding identical cells in module `\top'. 173s 173s Removed a total of 1 cells. 173s 173s 2.33.3. Executing OPT_DFF pass (perform DFF optimizations). 173s 173s 2.33.4. Executing OPT_CLEAN pass (remove unused cells and wires). 173s Finding unused cells or wires in module \top.. 173s Removed 26 unused cells and 17 unused wires. 173s 173s 173s 2.33.5. Finished fast OPT passes. 173s 173s 2.34. Executing ICE40_OPT pass (performing simple optimizations). 173s 173s 2.34.1. Running ICE40 specific optimizations. 173s Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$452.slice[0].carry: CO=\counter [0] 173s 173s 2.34.2. Executing OPT_EXPR pass (perform const folding). 173s Optimizing module top. 173s 173s 2.34.3. Executing OPT_MERGE pass (detect identical cells). 173s Finding identical cells in module `\top'. 173s Removed a total of 0 cells. 173s 173s 2.34.4. Executing OPT_DFF pass (perform DFF optimizations). 173s 173s 2.34.5. Executing OPT_CLEAN pass (remove unused cells and wires). 173s Finding unused cells or wires in module \top.. 173s 173s 2.34.6. Rerunning OPT passes. (Removed registers in this run.) 173s 173s 2.34.7. Running ICE40 specific optimizations. 173s 173s 2.34.8. Executing OPT_EXPR pass (perform const folding). 173s Optimizing module top. 173s 173s 2.34.9. Executing OPT_MERGE pass (detect identical cells). 173s Finding identical cells in module `\top'. 173s Removed a total of 0 cells. 173s 173s 2.34.10. Executing OPT_DFF pass (perform DFF optimizations). 173s 173s 2.34.11. Executing OPT_CLEAN pass (remove unused cells and wires). 173s Finding unused cells or wires in module \top.. 173s 173s 2.34.12. Finished OPT passes. (There is nothing left to do.) 173s 173s 2.35. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 173s 173s 2.36. Executing TECHMAP pass (map to technology primitives). 173s 173s 2.36.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 173s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 173s Generating RTLIL representation for module `\$_DFF_N_'. 173s Generating RTLIL representation for module `\$_DFF_P_'. 173s Generating RTLIL representation for module `\$_DFFE_NP_'. 173s Generating RTLIL representation for module `\$_DFFE_PP_'. 173s Generating RTLIL representation for module `\$_DFF_NP0_'. 173s Generating RTLIL representation for module `\$_DFF_NP1_'. 173s Generating RTLIL representation for module `\$_DFF_PP0_'. 173s Generating RTLIL representation for module `\$_DFF_PP1_'. 173s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 173s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 173s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 173s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 173s Generating RTLIL representation for module `\$_SDFF_NP0_'. 173s Generating RTLIL representation for module `\$_SDFF_NP1_'. 173s Generating RTLIL representation for module `\$_SDFF_PP0_'. 173s Generating RTLIL representation for module `\$_SDFF_PP1_'. 173s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 173s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 173s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 173s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 173s Successfully finished Verilog frontend. 173s 173s 2.36.2. Continuing TECHMAP pass. 173s Using template \$_DFF_P_ for cells of type $_DFF_P_. 173s No more expansions possible. 173s 173s 173s 2.37. Executing OPT_EXPR pass (perform const folding). 173s Optimizing module top. 173s 173s 2.38. Executing SIMPLEMAP pass (map simple cells to gate primitives). 173s Mapping top.$auto$alumacc.cc:485:replace_alu$452.slice[0].carry ($lut). 173s 173s 2.39. Executing ICE40_OPT pass (performing simple optimizations). 173s 173s 2.39.1. Running ICE40 specific optimizations. 173s 173s 2.39.2. Executing OPT_EXPR pass (perform const folding). 173s Optimizing module top. 173s 173s 173s 2.39.3. Executing OPT_MERGE pass (detect identical cells). 173s Finding identical cells in module `\top'. 173s Removed a total of 0 cells. 173s 173s 2.39.4. Executing OPT_DFF pass (perform DFF optimizations). 173s 173s 2.39.5. Executing OPT_CLEAN pass (remove unused cells and wires). 173s Finding unused cells or wires in module \top.. 173s Removed 0 unused cells and 124 unused wires. 173s 173s 173s 2.39.6. Rerunning OPT passes. (Removed registers in this run.) 173s 173s 2.39.7. Running ICE40 specific optimizations. 173s 173s 2.39.8. Executing OPT_EXPR pass (perform const folding). 173s Optimizing module top. 173s 173s 2.39.9. Executing OPT_MERGE pass (detect identical cells). 173s Finding identical cells in module `\top'. 173s Removed a total of 0 cells. 173s 173s 2.39.10. Executing OPT_DFF pass (perform DFF optimizations). 173s 173s 2.39.11. Executing OPT_CLEAN pass (remove unused cells and wires). 173s Finding unused cells or wires in module \top.. 173s 173s 2.39.12. Finished OPT passes. (There is nothing left to do.) 173s 173s 2.40. Executing TECHMAP pass (map to technology primitives). 173s 173s 2.40.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v 173s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation. 173s Generating RTLIL representation for module `\$_DLATCH_N_'. 173s Generating RTLIL representation for module `\$_DLATCH_P_'. 173s Successfully finished Verilog frontend. 173s 173s 2.40.2. Continuing TECHMAP pass. 173s No more expansions possible. 173s 173s 173s 2.41. Executing ABC pass (technology mapping using ABC). 173s 173s 2.41.1. Extracting gate netlist of module `\top' to `/input.blif'.. 173s Extracted 1 gates and 2 wires to a netlist network with 1 inputs and 1 outputs. 173s 173s 2.41.1.1. Executing ABC. 173s Running ABC command: "berkeley-abc" -s -f /abc.script 2>&1 173s ABC: ABC command line: "source /abc.script". 173s ABC: 173s ABC: + read_blif /input.blif 173s ABC: + read_lut /lutdefs.txt 173s ABC: + strash 173s ABC: + &get -n 173s ABC: + &fraig -x 173s ABC: + &put 173s ABC: + scorr 173s ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). 173s ABC: + dc2 173s ABC: + dretime 173s ABC: + strash 173s ABC: + dch -f 173s ABC: + if 173s ABC: + mfs2 173s ABC: + lutpack -S 1 173s ABC: + dress /input.blif 173s ABC: Total number of equiv classes = 2. 173s ABC: Participating nodes from both networks = 2. 173s ABC: Participating nodes from the first network = 1. ( 50.00 % of nodes) 173s ABC: Participating nodes from the second network = 1. ( 50.00 % of nodes) 173s ABC: Node pairs (any polarity) = 1. ( 50.00 % of names can be moved) 173s ABC: Node pairs (same polarity) = 1. ( 50.00 % of names can be moved) 173s ABC: Total runtime = 0.00 sec 173s ABC: + write_blif /output.blif 173s 173s 2.41.1.2. Re-integrating ABC results. 173s ABC RESULTS: $lut cells: 1 173s ABC RESULTS: internal signals: 0 173s ABC RESULTS: input signals: 1 173s ABC RESULTS: output signals: 1 173s Removing temp directory. 173s 173s 2.42. Executing ICE40_WRAPCARRY pass (wrap carries). 173s 173s 2.43. Executing TECHMAP pass (map to technology primitives). 173s 173s 2.43.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 173s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 173s Generating RTLIL representation for module `\$_DFF_N_'. 173s Generating RTLIL representation for module `\$_DFF_P_'. 173s Generating RTLIL representation for module `\$_DFFE_NP_'. 173s Generating RTLIL representation for module `\$_DFFE_PP_'. 173s Generating RTLIL representation for module `\$_DFF_NP0_'. 173s Generating RTLIL representation for module `\$_DFF_NP1_'. 173s Generating RTLIL representation for module `\$_DFF_PP0_'. 173s Generating RTLIL representation for module `\$_DFF_PP1_'. 173s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 173s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 173s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 173s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 173s Generating RTLIL representation for module `\$_SDFF_NP0_'. 173s Generating RTLIL representation for module `\$_SDFF_NP1_'. 173s Generating RTLIL representation for module `\$_SDFF_PP0_'. 173s Generating RTLIL representation for module `\$_SDFF_PP1_'. 173s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 173s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 173s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 173s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 173s Successfully finished Verilog frontend. 173s 173s 2.43.2. Continuing TECHMAP pass. 173s No more expansions possible. 173s 173s Removed 1 unused cells and 3 unused wires. 173s 173s 2.44. Executing OPT_LUT pass (optimize LUTs). 173s Discovering LUTs. 173s Number of LUTs: 26 173s 1-LUT 1 173s 2-LUT 1 173s 3-LUT 24 173s with \SB_CARRY (#0) 24 173s with \SB_CARRY (#1) 24 173s 173s Eliminating LUTs. 173s Number of LUTs: 26 173s 1-LUT 1 173s 2-LUT 1 173s 3-LUT 24 173s with \SB_CARRY (#0) 24 173s with \SB_CARRY (#1) 24 173s 173s Combining LUTs. 173s Number of LUTs: 26 173s 1-LUT 1 173s 2-LUT 1 173s 3-LUT 24 173s with \SB_CARRY (#0) 24 173s with \SB_CARRY (#1) 24 173s 173s Eliminated 0 LUTs. 173s Combined 0 LUTs. 173s 173s 173s 2.45. Executing TECHMAP pass (map to technology primitives). 173s 173s 2.45.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v 173s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation. 173s Generating RTLIL representation for module `\$lut'. 173s Successfully finished Verilog frontend. 173s 173s 2.45.2. Continuing TECHMAP pass. 173s Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut. 173s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. 173s No more expansions possible. 173s 173s Removed 0 unused cells and 52 unused wires. 173s 173s 2.46. Executing AUTONAME pass. 173s Renamed 132 objects in module top (4 iterations). 173s 173s 173s 2.47. Executing HIERARCHY pass (managing design hierarchy). 173s 173s 2.47.1. Analyzing design hierarchy.. 173s Top module: \top 173s 173s 2.47.2. Analyzing design hierarchy.. 173s Top module: \top 173s Removed 0 unused modules. 173s 173s 2.48. Printing statistics. 173s 173s === top === 173s 173s Number of wires: 9 173s Number of wire bits: 87 173s Number of public wires: 9 173s Number of public wire bits: 87 173s Number of memories: 0 173s Number of memory bits: 0 173s Number of processes: 0 173s Number of cells: 80 173s SB_CARRY 24 173s SB_DFF 30 173s SB_LUT4 26 173s 173s 2.49. Executing CHECK pass (checking for obvious problems). 173s Checking module top... 173s Found and reported 0 problems. 173s 173s 2.50. Executing JSON backend. 173s 173s End of script. Logfile hash: 7602206948, CPU: user 0.66s system 0.02s, MEM: 20.00 MB peak 173s Yosys 0.23 (git sha1 7ce5011c24b) 173s Time spent: 62% 13x read_verilog (0 sec), 8% 1x abc (0 sec), ... 173s nextpnr-ice40 --hx1k --package vq100 --asc example.asc --pcf iceblink.pcf --json example.json 173s Info: constrained 'LED2' to bel 'X13/Y7/io1' 173s Info: constrained 'LED3' to bel 'X13/Y6/io1' 173s Info: constrained 'LED4' to bel 'X13/Y4/io1' 173s Info: constrained 'LED5' to bel 'X13/Y3/io1' 173s Info: constrained 'clk' to bel 'X0/Y9/io0' 173s 173s Info: Packing constants.. 173s Info: Packing IOs.. 173s Info: Packing LUT-FFs.. 173s Info: 0 LCs used as LUT4 only 173s Info: 26 LCs used as LUT4 and DFF 173s Info: Packing non-LUT FFs.. 173s Info: 4 LCs used as DFF only 173s Info: Packing carries.. 173s Info: 0 LCs used as CARRY only 173s Info: Packing indirect carry+LUT pairs... 173s Info: 0 LUTs merged into carry LCs 173s Info: Packing RAMs.. 173s Info: Placing PLLs.. 173s Info: Packing special functions.. 173s Info: Packing PLLs.. 173s Info: Promoting globals.. 173s Info: promoting clk$SB_IO_IN (fanout 30) 173s Info: Constraining chains... 173s Info: 1 LCs used to legalise carry chains. 173s Info: Checksum: 0xabd25caf 173s 173s Info: Annotating ports with timing budgets for target frequency 12.00 MHz 173s Info: Checksum: 0x8546a4a1 173s 173s Info: Device utilisation: 173s Info: ICESTORM_LC: 33/ 1280 2% 173s Info: ICESTORM_RAM: 0/ 16 0% 173s Info: SB_IO: 5/ 112 4% 173s Info: SB_GB: 1/ 8 12% 173s Info: ICESTORM_PLL: 0/ 1 0% 173s Info: SB_WARMBOOT: 0/ 1 0% 173s 173s Info: Placed 5 cells based on constraints. 173s Info: Creating initial analytic placement for 7 cells, random placement wirelen = 81. 173s Info: at initial placer iter 0, wirelen = 7 173s Info: at initial placer iter 1, wirelen = 7 173s Info: at initial placer iter 2, wirelen = 7 173s Info: at initial placer iter 3, wirelen = 7 173s Info: Running main analytical placer, max placement attempts per cell = 10000. 173s Info: at iteration #1, type ICESTORM_LC: wirelen solved = 7, spread = 16, legal = 25; time = 0.00s 173s Info: at iteration #1, type SB_GB: wirelen solved = 25, spread = 25, legal = 25; time = 0.00s 173s Info: at iteration #1, type ALL: wirelen solved = 7, spread = 16, legal = 20; time = 0.00s 173s Info: at iteration #2, type ICESTORM_LC: wirelen solved = 11, spread = 27, legal = 27; time = 0.00s 173s Info: at iteration #2, type SB_GB: wirelen solved = 27, spread = 27, legal = 27; time = 0.00s 173s Info: at iteration #2, type ALL: wirelen solved = 11, spread = 27, legal = 27; time = 0.00s 173s Info: at iteration #3, type ICESTORM_LC: wirelen solved = 11, spread = 27, legal = 27; time = 0.00s 173s Info: at iteration #3, type SB_GB: wirelen solved = 27, spread = 27, legal = 27; time = 0.00s 173s Info: at iteration #3, type ALL: wirelen solved = 11, spread = 27, legal = 27; time = 0.00s 173s Info: at iteration #4, type ICESTORM_LC: wirelen solved = 11, spread = 27, legal = 27; time = 0.00s 173s Info: at iteration #4, type SB_GB: wirelen solved = 27, spread = 27, legal = 27; time = 0.00s 173s Info: at iteration #4, type ALL: wirelen solved = 11, spread = 27, legal = 27; time = 0.00s 173s Info: at iteration #5, type ICESTORM_LC: wirelen solved = 13, spread = 27, legal = 27; time = 0.00s 173s Info: at iteration #5, type SB_GB: wirelen solved = 27, spread = 27, legal = 27; time = 0.00s 173s Info: at iteration #5, type ALL: wirelen solved = 13, spread = 27, legal = 27; time = 0.00s 173s Info: at iteration #6, type ICESTORM_LC: wirelen solved = 13, spread = 27, legal = 27; time = 0.00s 173s Info: at iteration #6, type SB_GB: wirelen solved = 27, spread = 27, legal = 27; time = 0.00s 173s Info: at iteration #6, type ALL: wirelen solved = 13, spread = 27, legal = 27; time = 0.00s 173s Info: HeAP Placer Time: 0.01s 173s Info: of which solving equations: 0.01s 173s Info: of which spreading cells: 0.00s 173s Info: of which strict legalisation: 0.00s 173s 173s Info: Running simulated annealing placer for refinement. 173s Info: at iteration #1: temp = 0.000000, timing cost = 3, wirelen = 20 173s Info: at iteration #5: temp = 0.000000, timing cost = 4, wirelen = 16 173s Info: at iteration #6: temp = 0.000000, timing cost = 4, wirelen = 16 173s Info: SA placement time 0.00s 173s 173s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 173.73 MHz (PASS at 12.00 MHz) 173s 173s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> : 1.82 ns 173s 173s Info: Slack histogram: 173s Info: legend: * represents 1 endpoint(s) 173s Info: + represents [1,1) endpoint(s) 173s Info: [ 77577, 77809) |** 173s Info: [ 77809, 78041) | 173s Info: [ 78041, 78273) |** 173s Info: [ 78273, 78505) |** 173s Info: [ 78505, 78737) |** 173s Info: [ 78737, 78969) |** 173s Info: [ 78969, 79201) | 173s Info: [ 79201, 79433) |* 173s Info: [ 79433, 79665) |** 173s Info: [ 79665, 79897) |** 173s Info: [ 79897, 80129) |** 173s Info: [ 80129, 80361) |* 173s Info: [ 80361, 80593) | 173s Info: [ 80593, 80825) |** 173s Info: [ 80825, 81057) |** 173s Info: [ 81057, 81289) |** 173s Info: [ 81289, 81521) |* 173s Info: [ 81521, 81753) |**** 173s Info: [ 81753, 81985) |*************************** 173s Info: [ 81985, 82217) |*** 173s Info: Checksum: 0xb91a5d6b 173s 173s Info: Routing.. 173s Info: Setting up routing queue. 173s Info: Routing 93 arcs. 173s Info: | (re-)routed arcs | delta | remaining| time spent | 173s Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| 173s Info: 94 | 1 72 | 1 72 | 0| 0.00 0.00| 173s Info: Routing complete. 173s Info: Router1 time 0.00s 173s Info: Checksum: 0x96bc9a66 173s 173s Info: Critical path report for clock 'clk$SB_IO_IN_$glb_clk' (posedge -> posedge): 173s Info: curr total 173s Info: 0.5 0.5 Source counter_SB_LUT4_I3_LC.O 173s Info: 0.6 1.1 Net counter[0] budget 78.740997 ns (12,2) -> (11,2) 173s Info: Sink $nextpnr_ICESTORM_LC_0.I1 173s Info: Defined in: 173s Info: example.v:19.14-19.25 173s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 173s Info: 0.3 1.4 Source $nextpnr_ICESTORM_LC_0.COUT 173s Info: 0.0 1.4 Net $nextpnr_ICESTORM_LC_0$O budget 0.000000 ns (11,2) -> (11,2) 173s Info: Sink counter_SB_LUT4_I2_15_LC.CIN 173s Info: 0.1 1.5 Source counter_SB_LUT4_I2_15_LC.COUT 173s Info: 0.0 1.5 Net counter_SB_CARRY_CI_CO[2] budget 0.000000 ns (11,2) -> (11,2) 173s Info: Sink counter_SB_LUT4_I2_8_LC.CIN 173s Info: Defined in: 173s Info: example.v:19.14-19.25 173s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 173s Info: 0.1 1.6 Source counter_SB_LUT4_I2_8_LC.COUT 173s Info: 0.0 1.6 Net counter_SB_CARRY_CI_CO[3] budget 0.000000 ns (11,2) -> (11,2) 173s Info: Sink counter_SB_LUT4_I2_7_LC.CIN 173s Info: Defined in: 173s Info: example.v:19.14-19.25 173s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 173s Info: 0.1 1.8 Source counter_SB_LUT4_I2_7_LC.COUT 173s Info: 0.0 1.8 Net counter_SB_CARRY_CI_CO[4] budget 0.000000 ns (11,2) -> (11,2) 173s Info: Sink counter_SB_LUT4_I2_6_LC.CIN 173s Info: Defined in: 173s Info: example.v:19.14-19.25 173s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 173s Info: 0.1 1.9 Source counter_SB_LUT4_I2_6_LC.COUT 173s Info: 0.0 1.9 Net counter_SB_CARRY_CI_CO[5] budget 0.000000 ns (11,2) -> (11,2) 173s Info: Sink counter_SB_LUT4_I2_5_LC.CIN 173s Info: Defined in: 173s Info: example.v:19.14-19.25 173s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 173s Info: 0.1 2.0 Source counter_SB_LUT4_I2_5_LC.COUT 173s Info: 0.0 2.0 Net counter_SB_CARRY_CI_CO[6] budget 0.000000 ns (11,2) -> (11,2) 173s Info: Sink counter_SB_LUT4_I2_4_LC.CIN 173s Info: Defined in: 173s Info: example.v:19.14-19.25 173s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 173s Info: 0.1 2.1 Source counter_SB_LUT4_I2_4_LC.COUT 173s Info: 0.0 2.1 Net counter_SB_CARRY_CI_CO[7] budget 0.000000 ns (11,2) -> (11,2) 173s Info: Sink counter_SB_LUT4_I2_3_LC.CIN 173s Info: Defined in: 173s Info: example.v:19.14-19.25 173s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 173s Info: 0.1 2.3 Source counter_SB_LUT4_I2_3_LC.COUT 173s Info: 0.2 2.5 Net counter_SB_CARRY_CI_CO[8] budget 0.190000 ns (11,2) -> (11,3) 173s Info: Sink counter_SB_LUT4_I2_2_LC.CIN 173s Info: Defined in: 173s Info: example.v:19.14-19.25 173s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 173s Info: 0.1 2.6 Source counter_SB_LUT4_I2_2_LC.COUT 173s Info: 0.0 2.6 Net counter_SB_CARRY_CI_CO[9] budget 0.000000 ns (11,3) -> (11,3) 173s Info: Sink counter_SB_LUT4_I2_1_LC.CIN 173s Info: Defined in: 173s Info: example.v:19.14-19.25 173s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 173s Info: 0.1 2.7 Source counter_SB_LUT4_I2_1_LC.COUT 173s Info: 0.0 2.7 Net counter_SB_CARRY_CI_CO[10] budget 0.000000 ns (11,3) -> (11,3) 173s Info: Sink counter_SB_LUT4_I2_LC.CIN 173s Info: Defined in: 173s Info: example.v:19.14-19.25 173s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 173s Info: 0.1 2.8 Source counter_SB_LUT4_I2_LC.COUT 173s Info: 0.0 2.8 Net counter_SB_CARRY_CI_CO[11] budget 0.000000 ns (11,3) -> (11,3) 173s Info: Sink counter_SB_LUT4_I2_24_LC.CIN 173s Info: Defined in: 173s Info: example.v:19.14-19.25 173s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 173s Info: 0.1 3.0 Source counter_SB_LUT4_I2_24_LC.COUT 173s Info: 0.0 3.0 Net counter_SB_CARRY_CI_CO[12] budget 0.000000 ns (11,3) -> (11,3) 173s Info: Sink counter_SB_LUT4_I2_23_LC.CIN 173s Info: Defined in: 173s Info: example.v:19.14-19.25 173s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 173s Info: 0.1 3.1 Source counter_SB_LUT4_I2_23_LC.COUT 173s Info: 0.0 3.1 Net counter_SB_CARRY_CI_CO[13] budget 0.000000 ns (11,3) -> (11,3) 173s Info: Sink counter_SB_LUT4_I2_22_LC.CIN 173s Info: Defined in: 173s Info: example.v:19.14-19.25 173s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 173s Info: 0.1 3.2 Source counter_SB_LUT4_I2_22_LC.COUT 174s Info: 0.0 3.2 Net counter_SB_CARRY_CI_CO[14] budget 0.000000 ns (11,3) -> (11,3) 174s Info: Sink counter_SB_LUT4_I2_21_LC.CIN 174s Info: Defined in: 174s Info: example.v:19.14-19.25 174s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 174s Info: 0.1 3.3 Source counter_SB_LUT4_I2_21_LC.COUT 174s Info: 0.0 3.3 Net counter_SB_CARRY_CI_CO[15] budget 0.000000 ns (11,3) -> (11,3) 174s Info: Sink counter_SB_LUT4_I2_20_LC.CIN 174s Info: Defined in: 174s Info: example.v:19.14-19.25 174s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 174s Info: 0.1 3.5 Source counter_SB_LUT4_I2_20_LC.COUT 174s Info: 0.2 3.7 Net counter_SB_CARRY_CI_CO[16] budget 0.190000 ns (11,3) -> (11,4) 174s Info: Sink counter_SB_LUT4_I2_19_LC.CIN 174s Info: Defined in: 174s Info: example.v:19.14-19.25 174s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 174s Info: 0.1 3.8 Source counter_SB_LUT4_I2_19_LC.COUT 174s Info: 0.0 3.8 Net counter_SB_CARRY_CI_CO[17] budget 0.000000 ns (11,4) -> (11,4) 174s Info: Sink counter_SB_LUT4_I2_18_LC.CIN 174s Info: Defined in: 174s Info: example.v:19.14-19.25 174s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 174s Info: 0.1 3.9 Source counter_SB_LUT4_I2_18_LC.COUT 174s Info: 0.0 3.9 Net counter_SB_CARRY_CI_CO[18] budget 0.000000 ns (11,4) -> (11,4) 174s Info: Sink counter_SB_LUT4_I2_17_LC.CIN 174s Info: Defined in: 174s Info: example.v:19.14-19.25 174s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 174s Info: 0.1 4.0 Source counter_SB_LUT4_I2_17_LC.COUT 174s Info: 0.0 4.0 Net counter_SB_CARRY_CI_CO[19] budget 0.000000 ns (11,4) -> (11,4) 174s Info: Sink counter_SB_LUT4_I2_16_LC.CIN 174s Info: Defined in: 174s Info: example.v:19.14-19.25 174s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 174s Info: 0.1 4.2 Source counter_SB_LUT4_I2_16_LC.COUT 174s Info: 0.0 4.2 Net counter_SB_CARRY_CI_CO[20] budget 0.000000 ns (11,4) -> (11,4) 174s Info: Sink counter_SB_LUT4_I2_14_LC.CIN 174s Info: Defined in: 174s Info: example.v:19.14-19.25 174s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 174s Info: 0.1 4.3 Source counter_SB_LUT4_I2_14_LC.COUT 174s Info: 0.0 4.3 Net counter_SB_CARRY_CI_CO[21] budget 0.000000 ns (11,4) -> (11,4) 174s Info: Sink counter_SB_LUT4_I2_13_LC.CIN 174s Info: Defined in: 174s Info: example.v:19.14-19.25 174s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 174s Info: 0.1 4.4 Source counter_SB_LUT4_I2_13_LC.COUT 174s Info: 0.0 4.4 Net counter_SB_CARRY_CI_CO[22] budget 0.000000 ns (11,4) -> (11,4) 174s Info: Sink counter_SB_LUT4_I2_12_LC.CIN 174s Info: Defined in: 174s Info: example.v:19.14-19.25 174s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 174s Info: 0.1 4.6 Source counter_SB_LUT4_I2_12_LC.COUT 174s Info: 0.0 4.6 Net counter_SB_CARRY_CI_CO[23] budget 0.000000 ns (11,4) -> (11,4) 174s Info: Sink counter_SB_LUT4_I2_11_LC.CIN 174s Info: Defined in: 174s Info: example.v:19.14-19.25 174s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 174s Info: 0.1 4.7 Source counter_SB_LUT4_I2_11_LC.COUT 174s Info: 0.2 4.9 Net counter_SB_CARRY_CI_CO[24] budget 0.190000 ns (11,4) -> (11,5) 174s Info: Sink counter_SB_LUT4_I2_10_LC.CIN 174s Info: Defined in: 174s Info: example.v:19.14-19.25 174s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 174s Info: 0.1 5.0 Source counter_SB_LUT4_I2_10_LC.COUT 174s Info: 0.3 5.3 Net counter_SB_CARRY_CI_CO[25] budget 0.260000 ns (11,5) -> (11,5) 174s Info: Sink counter_SB_LUT4_I2_9_LC.I3 174s Info: Defined in: 174s Info: example.v:19.14-19.25 174s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 174s Info: 0.3 5.6 Setup counter_SB_LUT4_I2_9_LC.I3 174s Info: 4.2 ns logic, 1.4 ns routing 174s 174s Info: Critical path report for cross-domain path 'posedge clk$SB_IO_IN_$glb_clk' -> '': 174s Info: curr total 174s Info: 0.5 0.5 Source LED2_SB_DFF_Q_DFFLC.O 174s Info: 1.3 1.8 Net LED2$SB_IO_OUT budget 82.792999 ns (11,5) -> (13,7) 174s Info: Sink LED2$sb_io.D_OUT_0 174s Info: Defined in: 174s Info: example.v:16.17-16.23 174s Info: 0.5 ns logic, 1.3 ns routing 174s 174s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 178.76 MHz (PASS at 12.00 MHz) 174s 174s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> : 1.81 ns 174s 174s Info: Slack histogram: 174s Info: legend: * represents 1 endpoint(s) 174s Info: + represents [1,1) endpoint(s) 174s Info: [ 77739, 77963) |** 174s Info: [ 77963, 78187) | 174s Info: [ 78187, 78411) |** 174s Info: [ 78411, 78635) |** 174s Info: [ 78635, 78859) |** 174s Info: [ 78859, 79083) |** 174s Info: [ 79083, 79307) | 174s Info: [ 79307, 79531) |** 174s Info: [ 79531, 79755) |* 174s Info: [ 79755, 79979) |** 174s Info: [ 79979, 80203) |*** 174s Info: [ 80203, 80427) | 174s Info: [ 80427, 80651) |* 174s Info: [ 80651, 80875) |** 174s Info: [ 80875, 81099) |* 174s Info: [ 81099, 81323) |** 174s Info: [ 81323, 81547) |* 174s Info: [ 81547, 81771) |**** 174s Info: [ 81771, 81995) |*************************** 174s Info: [ 81995, 82219) |*** 174s 174s Info: Program finished normally. 174s icetime -d hx1k -mtr example.rpt example.asc 174s // Reading input .asc file.. 174s // Reading 1k chipdb file.. 174s // Creating timing netlist.. 174s // Timing estimate: 5.58 ns (179.07 MHz) 174s icepack example.asc example.bin 174s rm example.asc example.json 174s make: Leaving directory '/tmp/autopkgtest.rlxjW8/build.dCN/src/examples/iceblink' 174s make: Entering directory '/tmp/autopkgtest.rlxjW8/build.dCN/src/examples/icebreaker' 174s yosys -p 'synth_ice40 -top top -json example.json' example.v 174s 174s /----------------------------------------------------------------------------\ 174s | | 174s | yosys -- Yosys Open SYnthesis Suite | 174s | | 174s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 174s | | 174s | Permission to use, copy, modify, and/or distribute this software for any | 174s | purpose with or without fee is hereby granted, provided that the above | 174s | copyright notice and this permission notice appear in all copies. | 174s | | 174s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 174s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 174s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 174s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 174s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 174s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 174s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 174s | | 174s \----------------------------------------------------------------------------/ 174s 174s Yosys 0.23 (git sha1 7ce5011c24b) 174s 174s 174s -- Parsing `example.v' using frontend ` -vlog2k' -- 174s 174s 1. Executing Verilog-2005 frontend: example.v 174s Parsing Verilog input from `example.v' to AST representation. 174s Storing AST representation for module `$abstract\top'. 174s Successfully finished Verilog frontend. 174s 174s -- Running command `synth_ice40 -top top -json example.json' -- 174s 174s 2. Executing SYNTH_ICE40 pass. 174s 174s 2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v 174s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation. 174s Generating RTLIL representation for module `\SB_IO'. 174s Generating RTLIL representation for module `\SB_GB_IO'. 174s Generating RTLIL representation for module `\SB_GB'. 174s Generating RTLIL representation for module `\SB_LUT4'. 174s Generating RTLIL representation for module `\SB_CARRY'. 174s Generating RTLIL representation for module `\SB_DFF'. 174s Generating RTLIL representation for module `\SB_DFFE'. 174s Generating RTLIL representation for module `\SB_DFFSR'. 174s Generating RTLIL representation for module `\SB_DFFR'. 174s Generating RTLIL representation for module `\SB_DFFSS'. 174s Generating RTLIL representation for module `\SB_DFFS'. 174s Generating RTLIL representation for module `\SB_DFFESR'. 174s Generating RTLIL representation for module `\SB_DFFER'. 174s Generating RTLIL representation for module `\SB_DFFESS'. 174s Generating RTLIL representation for module `\SB_DFFES'. 174s Generating RTLIL representation for module `\SB_DFFN'. 174s Generating RTLIL representation for module `\SB_DFFNE'. 174s Generating RTLIL representation for module `\SB_DFFNSR'. 174s Generating RTLIL representation for module `\SB_DFFNR'. 174s Generating RTLIL representation for module `\SB_DFFNSS'. 174s Generating RTLIL representation for module `\SB_DFFNS'. 174s Generating RTLIL representation for module `\SB_DFFNESR'. 174s Generating RTLIL representation for module `\SB_DFFNER'. 174s Generating RTLIL representation for module `\SB_DFFNESS'. 174s Generating RTLIL representation for module `\SB_DFFNES'. 174s Generating RTLIL representation for module `\SB_RAM40_4K'. 174s Generating RTLIL representation for module `\SB_RAM40_4KNR'. 174s Generating RTLIL representation for module `\SB_RAM40_4KNW'. 174s Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. 174s Generating RTLIL representation for module `\ICESTORM_LC'. 174s Generating RTLIL representation for module `\SB_PLL40_CORE'. 174s Generating RTLIL representation for module `\SB_PLL40_PAD'. 174s Generating RTLIL representation for module `\SB_PLL40_2_PAD'. 174s Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. 174s Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. 174s Generating RTLIL representation for module `\SB_WARMBOOT'. 174s Generating RTLIL representation for module `\SB_SPRAM256KA'. 174s Generating RTLIL representation for module `\SB_HFOSC'. 174s Generating RTLIL representation for module `\SB_LFOSC'. 174s Generating RTLIL representation for module `\SB_RGBA_DRV'. 174s Generating RTLIL representation for module `\SB_LED_DRV_CUR'. 174s Generating RTLIL representation for module `\SB_RGB_DRV'. 174s Generating RTLIL representation for module `\SB_I2C'. 174s Generating RTLIL representation for module `\SB_SPI'. 174s Generating RTLIL representation for module `\SB_LEDDA_IP'. 174s Generating RTLIL representation for module `\SB_FILTER_50NS'. 174s Generating RTLIL representation for module `\SB_IO_I3C'. 174s Generating RTLIL representation for module `\SB_IO_OD'. 174s Generating RTLIL representation for module `\SB_MAC16'. 174s Generating RTLIL representation for module `\ICESTORM_RAM'. 174s Successfully finished Verilog frontend. 174s 174s 2.2. Executing HIERARCHY pass (managing design hierarchy). 174s 174s 2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\top'. 174s Generating RTLIL representation for module `\top'. 174s 174s 2.3.1. Analyzing design hierarchy.. 174s Top module: \top 174s 174s 2.3.2. Analyzing design hierarchy.. 174s Top module: \top 174s Removing unused module `$abstract\top'. 174s Removed 1 unused modules. 174s 174s 2.4. Executing PROC pass (convert processes to netlists). 174s 174s 2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 174s Cleaned up 0 empty switches. 174s 174s 2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 174s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241 in module SB_DFFNES. 174s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234 in module SB_DFFNESS. 174s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230 in module SB_DFFNER. 174s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223 in module SB_DFFNESR. 174s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220 in module SB_DFFNS. 174s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217 in module SB_DFFNSS. 174s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214 in module SB_DFFNR. 174s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211 in module SB_DFFNSR. 174s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203 in module SB_DFFES. 174s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196 in module SB_DFFESS. 174s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192 in module SB_DFFER. 174s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185 in module SB_DFFESR. 174s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182 in module SB_DFFS. 174s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179 in module SB_DFFSS. 174s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176 in module SB_DFFR. 174s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173 in module SB_DFFSR. 174s Removed a total of 0 dead cases. 174s 174s 2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 174s Removed 8 redundant assignments. 174s Promoted 25 assignments to connections. 174s 174s 2.4.4. Executing PROC_INIT pass (extract init attributes). 174s Found init rule in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 174s Set init value: \Q = 1'0 174s Found init rule in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 174s Set init value: \Q = 1'0 174s Found init rule in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 174s Set init value: \Q = 1'0 174s Found init rule in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 174s Set init value: \Q = 1'0 174s Found init rule in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 174s Set init value: \Q = 1'0 174s Found init rule in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 174s Set init value: \Q = 1'0 174s Found init rule in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 174s Set init value: \Q = 1'0 174s Found init rule in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 174s Set init value: \Q = 1'0 174s Found init rule in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 174s Set init value: \Q = 1'0 174s Found init rule in `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 174s Set init value: \Q = 1'0 174s Found init rule in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 174s Set init value: \Q = 1'0 174s Found init rule in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 174s Set init value: \Q = 1'0 174s Found init rule in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 174s Set init value: \Q = 1'0 174s Found init rule in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 174s Set init value: \Q = 1'0 174s Found init rule in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 174s Set init value: \Q = 1'0 174s Found init rule in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 174s Set init value: \Q = 1'0 174s Found init rule in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 174s Set init value: \Q = 1'0 174s Found init rule in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 174s Set init value: \Q = 1'0 174s Found init rule in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 174s Set init value: \Q = 1'0 174s Found init rule in `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 174s Set init value: \Q = 1'0 174s Found init rule in `\top.$proc$example.v:25$393'. 174s Set init value: \counter = 27'000000000000000000000000000 174s 174s 2.4.5. Executing PROC_ARST pass (detect async resets in processes). 174s Found async reset \S in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 174s Found async reset \R in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 174s Found async reset \S in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 174s Found async reset \R in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 174s Found async reset \S in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 174s Found async reset \R in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 174s Found async reset \S in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 174s Found async reset \R in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 174s 174s 2.4.6. Executing PROC_ROM pass (convert switches to ROMs). 174s Converted 0 switches. 174s 174s 174s 2.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 174s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 174s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 174s 1/1: $0\Q[0:0] 174s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 174s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 174s 1/1: $0\Q[0:0] 174s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 174s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 174s 1/1: $0\Q[0:0] 174s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 174s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 174s 1/1: $0\Q[0:0] 174s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 174s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 174s 1/1: $0\Q[0:0] 174s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 174s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 174s 1/1: $0\Q[0:0] 174s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 174s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 174s 1/1: $0\Q[0:0] 174s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 174s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 174s 1/1: $0\Q[0:0] 174s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 174s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 174s 1/1: $0\Q[0:0] 174s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 174s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 174s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 174s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 174s 1/1: $0\Q[0:0] 174s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 174s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 174s 1/1: $0\Q[0:0] 174s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 174s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 174s 1/1: $0\Q[0:0] 174s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 174s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 174s 1/1: $0\Q[0:0] 174s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 174s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 174s 1/1: $0\Q[0:0] 174s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 174s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 174s 1/1: $0\Q[0:0] 174s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 174s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 174s 1/1: $0\Q[0:0] 174s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 174s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 174s 1/1: $0\Q[0:0] 174s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 174s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 174s 1/1: $0\Q[0:0] 174s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 174s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 174s Creating decoders for process `\top.$proc$example.v:25$393'. 174s Creating decoders for process `\top.$proc$example.v:28$381'. 174s 174s 2.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). 174s 174s 2.4.9. Executing PROC_DFF pass (convert process syncs to FFs). 174s Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 174s created $adff cell `$procdff$438' with negative edge clock and positive level reset. 174s Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 174s created $dff cell `$procdff$439' with negative edge clock. 174s Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 174s created $adff cell `$procdff$440' with negative edge clock and positive level reset. 174s Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 174s created $dff cell `$procdff$441' with negative edge clock. 174s Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 174s created $adff cell `$procdff$442' with negative edge clock and positive level reset. 174s Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 174s created $dff cell `$procdff$443' with negative edge clock. 174s Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 174s created $adff cell `$procdff$444' with negative edge clock and positive level reset. 174s Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 174s created $dff cell `$procdff$445' with negative edge clock. 174s Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 174s created $dff cell `$procdff$446' with negative edge clock. 174s Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 174s created $dff cell `$procdff$447' with negative edge clock. 174s Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 174s created $adff cell `$procdff$448' with positive edge clock and positive level reset. 174s Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 174s created $dff cell `$procdff$449' with positive edge clock. 174s Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 174s created $adff cell `$procdff$450' with positive edge clock and positive level reset. 174s Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 174s created $dff cell `$procdff$451' with positive edge clock. 174s Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 174s created $adff cell `$procdff$452' with positive edge clock and positive level reset. 174s Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 174s created $dff cell `$procdff$453' with positive edge clock. 174s Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 174s created $adff cell `$procdff$454' with positive edge clock and positive level reset. 174s Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 174s created $dff cell `$procdff$455' with positive edge clock. 174s Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 174s created $dff cell `$procdff$456' with positive edge clock. 174s Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 174s created $dff cell `$procdff$457' with positive edge clock. 174s Creating register for signal `\top.\counter' using process `\top.$proc$example.v:28$381'. 174s created $dff cell `$procdff$458' with positive edge clock. 174s Creating register for signal `\top.\outcnt' using process `\top.$proc$example.v:28$381'. 174s created $dff cell `$procdff$459' with positive edge clock. 174s 174s 2.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 174s 174s 2.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 174s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 174s Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 174s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 174s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 174s Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 174s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 174s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 174s Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 174s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 174s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 174s Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 174s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 174s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 174s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 174s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 174s Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 174s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 174s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 174s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 174s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 174s Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 174s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 174s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 174s Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 174s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 174s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 174s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 174s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 174s Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 174s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 174s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 174s Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 174s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 174s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 174s Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 174s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 174s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 174s Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 174s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 174s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 174s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 174s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 174s Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 174s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 174s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 174s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 174s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 174s Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 174s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 174s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 174s Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 174s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 174s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 174s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 174s Removing empty process `top.$proc$example.v:25$393'. 174s Removing empty process `top.$proc$example.v:28$381'. 174s Cleaned up 18 empty switches. 174s 174s 2.4.12. Executing OPT_EXPR pass (perform const folding). 174s Optimizing module top. 174s 174s 174s 2.5. Executing FLATTEN pass (flatten design). 174s 174s 2.6. Executing TRIBUF pass. 174s 174s 2.7. Executing DEMINOUT pass (demote inout ports to input or output). 174s 174s 2.8. Executing OPT_EXPR pass (perform const folding). 174s Optimizing module top. 174s 174s 2.9. Executing OPT_CLEAN pass (remove unused cells and wires). 174s Finding unused cells or wires in module \top.. 174s Removed 0 unused cells and 6 unused wires. 174s 174s 174s 2.10. Executing CHECK pass (checking for obvious problems). 174s Checking module top... 174s Found and reported 0 problems. 174s 174s 2.11. Executing OPT pass (performing simple optimizations). 174s 174s 2.11.1. Executing OPT_EXPR pass (perform const folding). 174s Optimizing module top. 174s 174s 2.11.2. Executing OPT_MERGE pass (detect identical cells). 174s Finding identical cells in module `\top'. 174s Removed a total of 0 cells. 174s 174s 2.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 174s Running muxtree optimizer on module \top.. 174s Creating internal representation of mux trees. 174s No muxes found in this module. 174s Removed 0 multiplexer ports. 174s 174s 2.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 174s Optimizing cells in module \top. 174s Performed a total of 0 changes. 174s 174s 2.11.5. Executing OPT_MERGE pass (detect identical cells). 174s Finding identical cells in module `\top'. 174s Removed a total of 0 cells. 174s 174s 2.11.6. Executing OPT_DFF pass (perform DFF optimizations). 174s 174s 2.11.7. Executing OPT_CLEAN pass (remove unused cells and wires). 174s Finding unused cells or wires in module \top.. 174s 174s 2.11.8. Executing OPT_EXPR pass (perform const folding). 174s Optimizing module top. 174s 174s 2.11.9. Finished OPT passes. (There is nothing left to do.) 174s 174s 2.12. Executing FSM pass (extract and optimize FSM). 174s 174s 2.12.1. Executing FSM_DETECT pass (finding FSMs in design). 174s 174s 2.12.2. Executing FSM_EXTRACT pass (extracting FSM from design). 174s 174s 2.12.3. Executing FSM_OPT pass (simple optimizations of FSMs). 174s 174s 2.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). 174s Finding unused cells or wires in module \top.. 174s 174s 2.12.5. Executing FSM_OPT pass (simple optimizations of FSMs). 174s 174s 2.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 174s 174s 2.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 174s 174s 2.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 174s 174s 2.13. Executing OPT pass (performing simple optimizations). 174s 174s 2.13.1. Executing OPT_EXPR pass (perform const folding). 174s Optimizing module top. 174s 174s 2.13.2. Executing OPT_MERGE pass (detect identical cells). 174s Finding identical cells in module `\top'. 174s Removed a total of 0 cells. 174s 174s 2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 174s Running muxtree optimizer on module \top.. 174s Creating internal representation of mux trees. 174s No muxes found in this module. 174s Removed 0 multiplexer ports. 174s 174s 2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 174s Optimizing cells in module \top. 174s Performed a total of 0 changes. 174s 174s 2.13.5. Executing OPT_MERGE pass (detect identical cells). 174s Finding identical cells in module `\top'. 174s Removed a total of 0 cells. 174s 174s 2.13.6. Executing OPT_DFF pass (perform DFF optimizations). 174s 174s 2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). 174s Finding unused cells or wires in module \top.. 174s 174s 2.13.8. Executing OPT_EXPR pass (perform const folding). 174s Optimizing module top. 174s 174s 2.13.9. Finished OPT passes. (There is nothing left to do.) 174s 174s 2.14. Executing WREDUCE pass (reducing word size of cells). 174s Removed top 31 bits (of 32) from port B of cell top.$add$example.v:29$382 ($add). 174s Removed top 5 bits (of 32) from port Y of cell top.$add$example.v:29$382 ($add). 174s Removed top 1 bits (of 5) from port B of cell top.$xor$example.v:33$385 ($xor). 174s Removed top 1 bits (of 2) from port A of cell top.$add$example.v:35$387 ($add). 174s Removed top 28 bits (of 32) from port B of cell top.$and$example.v:38$391 ($and). 174s Removed top 27 bits (of 32) from port Y of cell top.$and$example.v:38$391 ($and). 174s Removed top 30 bits (of 32) from port A of cell top.$shl$example.v:38$392 ($shl). 174s Removed top 27 bits (of 32) from port B of cell top.$shl$example.v:38$392 ($shl). 174s Removed top 16 bits (of 32) from port Y of cell top.$shl$example.v:38$392 ($shl). 174s Removed top 27 bits (of 32) from wire top.$and$example.v:38$391_Y. 174s Removed top 1 bits (of 2) from wire top.$logic_not$example.v:35$386_Y. 174s Removed top 16 bits (of 32) from wire top.$shl$example.v:38$392_Y. 174s 174s 2.15. Executing PEEPOPT pass (run peephole optimizers). 174s 174s 2.16. Executing OPT_CLEAN pass (remove unused cells and wires). 174s Finding unused cells or wires in module \top.. 174s Removed 0 unused cells and 5 unused wires. 174s 174s 174s 2.17. Executing SHARE pass (SAT-based resource sharing). 174s 174s 2.18. Executing TECHMAP pass (map to technology primitives). 174s 174s 2.18.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v 174s Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation. 174s Generating RTLIL representation for module `\_90_lut_cmp_'. 174s Successfully finished Verilog frontend. 174s 174s 2.18.2. Continuing TECHMAP pass. 174s No more expansions possible. 174s 174s 174s 2.19. Executing OPT_EXPR pass (perform const folding). 174s Optimizing module top. 174s 174s 2.20. Executing OPT_CLEAN pass (remove unused cells and wires). 174s Finding unused cells or wires in module \top.. 174s 174s 2.21. Executing ALUMACC pass (create $alu and $macc cells). 174s Extracting $alu and $macc cells in module top: 174s creating $macc model for $add$example.v:29$382 ($add). 174s creating $macc model for $add$example.v:35$387 ($add). 174s creating $macc model for $add$example.v:35$388 ($add). 174s creating $macc model for $add$example.v:35$389 ($add). 174s merging $macc model for $add$example.v:35$388 into $add$example.v:35$389. 174s merging $macc model for $add$example.v:35$387 into $add$example.v:35$389. 174s creating $alu model for $macc $add$example.v:29$382. 174s creating $macc cell for $add$example.v:35$389: $auto$alumacc.cc:365:replace_macc$464 174s creating $alu cell for $add$example.v:29$382: $auto$alumacc.cc:485:replace_alu$465 174s created 1 $alu and 1 $macc cells. 174s 174s 2.22. Executing OPT pass (performing simple optimizations). 174s 174s 2.22.1. Executing OPT_EXPR pass (perform const folding). 174s Optimizing module top. 174s 174s 2.22.2. Executing OPT_MERGE pass (detect identical cells). 174s Finding identical cells in module `\top'. 174s Removed a total of 0 cells. 174s 174s 2.22.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 174s Running muxtree optimizer on module \top.. 174s Creating internal representation of mux trees. 174s No muxes found in this module. 174s Removed 0 multiplexer ports. 174s 174s 2.22.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 174s Optimizing cells in module \top. 174s Performed a total of 0 changes. 174s 174s 2.22.5. Executing OPT_MERGE pass (detect identical cells). 174s Finding identical cells in module `\top'. 174s Removed a total of 0 cells. 174s 174s 2.22.6. Executing OPT_DFF pass (perform DFF optimizations). 174s 174s 2.22.7. Executing OPT_CLEAN pass (remove unused cells and wires). 174s Finding unused cells or wires in module \top.. 174s Removed 2 unused cells and 2 unused wires. 174s 174s 174s 2.22.8. Executing OPT_EXPR pass (perform const folding). 174s Optimizing module top. 174s 174s 2.22.9. Rerunning OPT passes. (Maybe there is more to do..) 174s 174s 2.22.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 174s Running muxtree optimizer on module \top.. 174s Creating internal representation of mux trees. 174s No muxes found in this module. 174s Removed 0 multiplexer ports. 174s 174s 2.22.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 174s Optimizing cells in module \top. 174s Performed a total of 0 changes. 174s 174s 2.22.12. Executing OPT_MERGE pass (detect identical cells). 174s Finding identical cells in module `\top'. 174s Removed a total of 0 cells. 174s 174s 2.22.13. Executing OPT_DFF pass (perform DFF optimizations). 174s 174s 2.22.14. Executing OPT_CLEAN pass (remove unused cells and wires). 174s Finding unused cells or wires in module \top.. 174s 174s 2.22.15. Executing OPT_EXPR pass (perform const folding). 174s Optimizing module top. 174s 174s 2.22.16. Finished OPT passes. (There is nothing left to do.) 174s 174s 2.23. Executing MEMORY pass. 174s 174s 2.23.1. Executing OPT_MEM pass (optimize memories). 174s Performed a total of 0 transformations. 174s 174s 2.23.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). 174s Performed a total of 0 transformations. 174s 174s 2.23.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 174s 174s 2.23.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 174s 174s 2.23.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 174s 174s 2.23.6. Executing OPT_CLEAN pass (remove unused cells and wires). 174s Finding unused cells or wires in module \top.. 174s 174s 2.23.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 174s 174s 2.23.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). 174s Performed a total of 0 transformations. 174s 174s 2.23.9. Executing OPT_CLEAN pass (remove unused cells and wires). 174s Finding unused cells or wires in module \top.. 174s 174s 2.23.10. Executing MEMORY_COLLECT pass (generating $mem cells). 174s 174s 2.24. Executing OPT_CLEAN pass (remove unused cells and wires). 174s Finding unused cells or wires in module \top.. 174s 174s 2.25. Executing MEMORY_LIBMAP pass (mapping memories to cells). 174s 174s 2.26. Executing TECHMAP pass (map to technology primitives). 174s 174s 2.26.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v 174s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation. 174s Generating RTLIL representation for module `\$__ICE40_RAM4K_'. 174s Successfully finished Verilog frontend. 174s 174s 2.26.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/spram_map.v 174s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/spram_map.v' to AST representation. 174s Generating RTLIL representation for module `\$__ICE40_SPRAM_'. 174s Successfully finished Verilog frontend. 174s 174s 2.26.3. Continuing TECHMAP pass. 174s No more expansions possible. 174s 174s 174s 2.27. Executing ICE40_BRAMINIT pass. 174s 174s 2.28. Executing OPT pass (performing simple optimizations). 174s 174s 2.28.1. Executing OPT_EXPR pass (perform const folding). 174s Optimizing module top. 174s 174s 174s 2.28.2. Executing OPT_MERGE pass (detect identical cells). 174s Finding identical cells in module `\top'. 174s Removed a total of 0 cells. 174s 174s 2.28.3. Executing OPT_DFF pass (perform DFF optimizations). 174s 174s 2.28.4. Executing OPT_CLEAN pass (remove unused cells and wires). 174s Finding unused cells or wires in module \top.. 174s Removed 0 unused cells and 5 unused wires. 174s 174s 174s 2.28.5. Finished fast OPT passes. 174s 174s 2.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 174s 174s 2.30. Executing OPT pass (performing simple optimizations). 174s 174s 2.30.1. Executing OPT_EXPR pass (perform const folding). 174s Optimizing module top. 174s 174s 2.30.2. Executing OPT_MERGE pass (detect identical cells). 174s Finding identical cells in module `\top'. 174s Removed a total of 0 cells. 174s 174s 2.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 174s Running muxtree optimizer on module \top.. 174s Creating internal representation of mux trees. 174s No muxes found in this module. 174s Removed 0 multiplexer ports. 174s 174s 2.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 174s Optimizing cells in module \top. 174s Performed a total of 0 changes. 174s 174s 2.30.5. Executing OPT_MERGE pass (detect identical cells). 174s Finding identical cells in module `\top'. 174s Removed a total of 0 cells. 174s 174s 2.30.6. Executing OPT_DFF pass (perform DFF optimizations). 174s 174s 2.30.7. Executing OPT_CLEAN pass (remove unused cells and wires). 174s Finding unused cells or wires in module \top.. 174s 174s 2.30.8. Executing OPT_EXPR pass (perform const folding). 174s Optimizing module top. 174s 174s 2.30.9. Finished OPT passes. (There is nothing left to do.) 174s 174s 2.31. Executing ICE40_WRAPCARRY pass (wrap carries). 174s 174s 2.32. Executing TECHMAP pass (map to technology primitives). 174s 174s 2.32.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v 174s Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation. 174s Generating RTLIL representation for module `\_90_simplemap_bool_ops'. 174s Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. 174s Generating RTLIL representation for module `\_90_simplemap_logic_ops'. 174s Generating RTLIL representation for module `\_90_simplemap_compare_ops'. 174s Generating RTLIL representation for module `\_90_simplemap_various'. 174s Generating RTLIL representation for module `\_90_simplemap_registers'. 174s Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. 174s Generating RTLIL representation for module `\_90_shift_shiftx'. 174s Generating RTLIL representation for module `\_90_fa'. 174s Generating RTLIL representation for module `\_90_lcu'. 174s Generating RTLIL representation for module `\_90_alu'. 174s Generating RTLIL representation for module `\_90_macc'. 174s Generating RTLIL representation for module `\_90_alumacc'. 174s Generating RTLIL representation for module `\$__div_mod_u'. 174s Generating RTLIL representation for module `\$__div_mod_trunc'. 174s Generating RTLIL representation for module `\_90_div'. 174s Generating RTLIL representation for module `\_90_mod'. 174s Generating RTLIL representation for module `\$__div_mod_floor'. 174s Generating RTLIL representation for module `\_90_divfloor'. 174s Generating RTLIL representation for module `\_90_modfloor'. 174s Generating RTLIL representation for module `\_90_pow'. 174s Generating RTLIL representation for module `\_90_pmux'. 174s Generating RTLIL representation for module `\_90_demux'. 174s Generating RTLIL representation for module `\_90_lut'. 174s Successfully finished Verilog frontend. 174s 174s 2.32.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v 174s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation. 174s Generating RTLIL representation for module `\_80_ice40_alu'. 174s Successfully finished Verilog frontend. 174s 174s 2.32.3. Continuing TECHMAP pass. 174s Using extmapper simplemap for cells of type $logic_not. 174s Using extmapper simplemap for cells of type $xor. 174s Using template $paramod$956e79e8f8c5e64be7438155ae50a966e615cb04\_80_ice40_alu for cells of type $alu. 174s Using extmapper simplemap for cells of type $not. 174s Using template $paramod$constmap:9b90168b0f8ca06b2b949f1a9c9bc3e813ea8531$paramod$288516fc4f16924f26258e65716d87e1f82fa03e\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. 174s Using extmapper maccmap for cells of type $macc. 174s add bits { \BTN1 \BTN2 \BTN3 $auto$wreduce.cc:455:run$461 [0] } (4 bits) 174s packed 1 (1) bits / 1 words into adder tree 174s Using extmapper simplemap for cells of type $dff. 174s Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000001 for cells of type $fa. 174s Using template $paramod$7e708ae28ab761f11d0fb59d3ffc72f6a4baf5d9\_90_alu for cells of type $alu. 174s Using extmapper simplemap for cells of type $pos. 174s Using extmapper simplemap for cells of type $or. 174s Using extmapper simplemap for cells of type $and. 174s Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu. 174s No more expansions possible. 174s 174s 174s 2.33. Executing OPT pass (performing simple optimizations). 174s 174s 2.33.1. Executing OPT_EXPR pass (perform const folding). 174s Optimizing module top. 174s 174s 174s 2.33.2. Executing OPT_MERGE pass (detect identical cells). 174s Finding identical cells in module `\top'. 174s 174s Removed a total of 1 cells. 174s 174s 2.33.3. Executing OPT_DFF pass (perform DFF optimizations). 174s 174s 2.33.4. Executing OPT_CLEAN pass (remove unused cells and wires). 174s Finding unused cells or wires in module \top.. 174s Removed 30 unused cells and 60 unused wires. 174s 174s 174s 2.33.5. Finished fast OPT passes. 174s 174s 2.34. Executing ICE40_OPT pass (performing simple optimizations). 174s 174s 2.34.1. Running ICE40 specific optimizations. 174s Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$465.slice[0].carry: CO=\counter [0] 174s 174s 2.34.2. Executing OPT_EXPR pass (perform const folding). 174s Optimizing module top. 174s 174s 2.34.3. Executing OPT_MERGE pass (detect identical cells). 174s Finding identical cells in module `\top'. 174s Removed a total of 0 cells. 174s 174s 2.34.4. Executing OPT_DFF pass (perform DFF optimizations). 174s 174s 2.34.5. Executing OPT_CLEAN pass (remove unused cells and wires). 174s Finding unused cells or wires in module \top.. 174s 174s 2.34.6. Rerunning OPT passes. (Removed registers in this run.) 174s 174s 2.34.7. Running ICE40 specific optimizations. 174s 174s 2.34.8. Executing OPT_EXPR pass (perform const folding). 174s Optimizing module top. 174s 174s 2.34.9. Executing OPT_MERGE pass (detect identical cells). 174s Finding identical cells in module `\top'. 174s Removed a total of 0 cells. 174s 174s 2.34.10. Executing OPT_DFF pass (perform DFF optimizations). 174s 174s 2.34.11. Executing OPT_CLEAN pass (remove unused cells and wires). 174s Finding unused cells or wires in module \top.. 174s 174s 2.34.12. Finished OPT passes. (There is nothing left to do.) 174s 174s 2.35. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 174s 174s 2.36. Executing TECHMAP pass (map to technology primitives). 174s 174s 2.36.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 174s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 174s Generating RTLIL representation for module `\$_DFF_N_'. 174s Generating RTLIL representation for module `\$_DFF_P_'. 174s Generating RTLIL representation for module `\$_DFFE_NP_'. 174s Generating RTLIL representation for module `\$_DFFE_PP_'. 174s Generating RTLIL representation for module `\$_DFF_NP0_'. 174s Generating RTLIL representation for module `\$_DFF_NP1_'. 174s Generating RTLIL representation for module `\$_DFF_PP0_'. 174s Generating RTLIL representation for module `\$_DFF_PP1_'. 174s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 174s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 174s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 174s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 174s Generating RTLIL representation for module `\$_SDFF_NP0_'. 174s Generating RTLIL representation for module `\$_SDFF_NP1_'. 174s Generating RTLIL representation for module `\$_SDFF_PP0_'. 174s Generating RTLIL representation for module `\$_SDFF_PP1_'. 174s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 174s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 174s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 174s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 174s Successfully finished Verilog frontend. 174s 174s 2.36.2. Continuing TECHMAP pass. 174s Using template \$_DFF_P_ for cells of type $_DFF_P_. 174s No more expansions possible. 174s 174s 174s 2.37. Executing OPT_EXPR pass (perform const folding). 174s Optimizing module top. 174s 174s 2.38. Executing SIMPLEMAP pass (map simple cells to gate primitives). 174s Mapping top.$auto$alumacc.cc:485:replace_alu$465.slice[0].carry ($lut). 174s 174s 2.39. Executing ICE40_OPT pass (performing simple optimizations). 174s 174s 2.39.1. Running ICE40 specific optimizations. 174s 174s 2.39.2. Executing OPT_EXPR pass (perform const folding). 174s Optimizing module top. 174s 174s 174s 2.39.3. Executing OPT_MERGE pass (detect identical cells). 174s Finding identical cells in module `\top'. 174s Removed a total of 0 cells. 174s 174s 2.39.4. Executing OPT_DFF pass (perform DFF optimizations). 174s 174s 2.39.5. Executing OPT_CLEAN pass (remove unused cells and wires). 174s Finding unused cells or wires in module \top.. 174s Removed 0 unused cells and 132 unused wires. 174s 174s 174s 2.39.6. Rerunning OPT passes. (Removed registers in this run.) 174s 174s 2.39.7. Running ICE40 specific optimizations. 174s 174s 2.39.8. Executing OPT_EXPR pass (perform const folding). 174s Optimizing module top. 175s 175s 2.39.9. Executing OPT_MERGE pass (detect identical cells). 175s Finding identical cells in module `\top'. 175s Removed a total of 0 cells. 175s 175s 2.39.10. Executing OPT_DFF pass (perform DFF optimizations). 175s 175s 2.39.11. Executing OPT_CLEAN pass (remove unused cells and wires). 175s Finding unused cells or wires in module \top.. 175s 175s 2.39.12. Finished OPT passes. (There is nothing left to do.) 175s 175s 2.40. Executing TECHMAP pass (map to technology primitives). 175s 175s 2.40.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v 175s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation. 175s Generating RTLIL representation for module `\$_DLATCH_N_'. 175s Generating RTLIL representation for module `\$_DLATCH_P_'. 175s Successfully finished Verilog frontend. 175s 175s 2.40.2. Continuing TECHMAP pass. 175s No more expansions possible. 175s 175s 175s 2.41. Executing ABC pass (technology mapping using ABC). 175s 175s 2.41.1. Extracting gate netlist of module `\top' to `/input.blif'.. 175s Extracted 45 gates and 56 wires to a netlist network with 10 inputs and 23 outputs. 175s 175s 2.41.1.1. Executing ABC. 175s Running ABC command: "berkeley-abc" -s -f /abc.script 2>&1 175s ABC: ABC command line: "source /abc.script". 175s ABC: 175s ABC: + read_blif /input.blif 175s ABC: + read_lut /lutdefs.txt 175s ABC: + strash 175s ABC: + &get -n 175s ABC: + &fraig -x 175s ABC: + &put 175s ABC: + scorr 175s ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). 175s ABC: + dc2 175s ABC: + dretime 175s ABC: + strash 175s ABC: + dch -f 175s ABC: + if 175s ABC: + mfs2 175s ABC: + lutpack -S 1 175s ABC: + dress /input.blif 175s ABC: Total number of equiv classes = 24. 175s ABC: Participating nodes from both networks = 49. 175s ABC: Participating nodes from the first network = 23. ( 95.83 % of nodes) 175s ABC: Participating nodes from the second network = 26. ( 108.33 % of nodes) 175s ABC: Node pairs (any polarity) = 23. ( 95.83 % of names can be moved) 175s ABC: Node pairs (same polarity) = 23. ( 95.83 % of names can be moved) 175s ABC: Total runtime = 0.01 sec 175s ABC: + write_blif /output.blif 175s 175s 2.41.1.2. Re-integrating ABC results. 175s ABC RESULTS: $lut cells: 23 175s ABC RESULTS: internal signals: 23 175s ABC RESULTS: input signals: 10 175s ABC RESULTS: output signals: 23 175s Removing temp directory. 175s 175s 2.42. Executing ICE40_WRAPCARRY pass (wrap carries). 175s 175s 2.43. Executing TECHMAP pass (map to technology primitives). 175s 175s 2.43.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 175s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 175s Generating RTLIL representation for module `\$_DFF_N_'. 175s Generating RTLIL representation for module `\$_DFF_P_'. 175s Generating RTLIL representation for module `\$_DFFE_NP_'. 175s Generating RTLIL representation for module `\$_DFFE_PP_'. 175s Generating RTLIL representation for module `\$_DFF_NP0_'. 175s Generating RTLIL representation for module `\$_DFF_NP1_'. 175s Generating RTLIL representation for module `\$_DFF_PP0_'. 175s Generating RTLIL representation for module `\$_DFF_PP1_'. 175s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 175s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 175s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 175s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 175s Generating RTLIL representation for module `\$_SDFF_NP0_'. 175s Generating RTLIL representation for module `\$_SDFF_NP1_'. 175s Generating RTLIL representation for module `\$_SDFF_PP0_'. 175s Generating RTLIL representation for module `\$_SDFF_PP1_'. 175s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 175s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 175s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 175s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 175s Successfully finished Verilog frontend. 175s 175s 2.43.2. Continuing TECHMAP pass. 175s No more expansions possible. 175s 175s Removed 1 unused cells and 46 unused wires. 175s 175s 2.44. Executing OPT_LUT pass (optimize LUTs). 175s Discovering LUTs. 175s Number of LUTs: 49 175s 1-LUT 1 175s 2-LUT 5 175s 3-LUT 25 175s 4-LUT 18 175s with \SB_CARRY (#0) 25 175s with \SB_CARRY (#1) 25 175s 175s Eliminating LUTs. 175s Number of LUTs: 49 175s 1-LUT 1 175s 2-LUT 5 175s 3-LUT 25 175s 4-LUT 18 175s with \SB_CARRY (#0) 25 175s with \SB_CARRY (#1) 25 175s 175s Combining LUTs. 175s Number of LUTs: 49 175s 1-LUT 1 175s 2-LUT 5 175s 3-LUT 25 175s 4-LUT 18 175s with \SB_CARRY (#0) 25 175s with \SB_CARRY (#1) 25 175s 175s Eliminated 0 LUTs. 175s Combined 0 LUTs. 175s 175s 175s 2.45. Executing TECHMAP pass (map to technology primitives). 175s 175s 2.45.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v 175s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation. 175s Generating RTLIL representation for module `\$lut'. 175s Successfully finished Verilog frontend. 175s 175s 2.45.2. Continuing TECHMAP pass. 175s Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut. 175s Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut. 175s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut. 175s Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut. 175s Using template $paramod$38524f19a670105a447163ca7c0fbdcb0f76b0d7\$lut for cells of type $lut. 175s Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut. 175s Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut. 175s Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut. 175s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. 175s No more expansions possible. 175s 175s Removed 0 unused cells and 98 unused wires. 175s 175s 2.46. Executing AUTONAME pass. 175s Renamed 160 objects in module top (4 iterations). 175s 175s 175s 2.47. Executing HIERARCHY pass (managing design hierarchy). 175s 175s 2.47.1. Analyzing design hierarchy.. 175s Top module: \top 175s 175s 2.47.2. Analyzing design hierarchy.. 175s Top module: \top 175s Removed 0 unused modules. 175s 175s 2.48. Printing statistics. 175s 175s === top === 175s 175s Number of wires: 32 175s Number of wire bits: 114 175s Number of public wires: 32 175s Number of public wire bits: 114 175s Number of memories: 0 175s Number of memory bits: 0 175s Number of processes: 0 175s Number of cells: 106 175s SB_CARRY 25 175s SB_DFF 32 175s SB_LUT4 49 175s 175s 2.49. Executing CHECK pass (checking for obvious problems). 175s Checking module top... 175s Found and reported 0 problems. 175s 175s 2.50. Executing JSON backend. 175s 175s End of script. Logfile hash: 5e0858e2ba, CPU: user 0.76s system 0.01s, MEM: 20.12 MB peak 175s Yosys 0.23 (git sha1 7ce5011c24b) 175s Time spent: 54% 13x read_verilog (0 sec), 12% 1x abc (0 sec), ... 175s nextpnr-ice40 --up5k --package sg48 --asc example.asc --pcf icebreaker.pcf --json example.json 175s Info: constrained 'CLK' to bel 'X12/Y31/io1' 175s Info: constrained 'BTN_N' to bel 'X16/Y0/io0' 175s Info: constrained 'LEDR_N' to bel 'X17/Y0/io0' 175s Info: constrained 'LEDG_N' to bel 'X13/Y31/io0' 175s Info: constrained 'P1A1' to bel 'X9/Y0/io0' 175s Info: constrained 'P1A2' to bel 'X8/Y0/io0' 175s Info: constrained 'P1A3' to bel 'X6/Y0/io0' 175s Info: constrained 'P1A4' to bel 'X7/Y0/io1' 175s Info: constrained 'P1A7' to bel 'X9/Y0/io1' 175s Info: constrained 'P1A8' to bel 'X7/Y0/io0' 175s Info: constrained 'P1A9' to bel 'X5/Y0/io0' 175s Info: constrained 'P1A10' to bel 'X6/Y0/io1' 175s Info: constrained 'P1B1' to bel 'X9/Y31/io0' 175s Info: constrained 'P1B2' to bel 'X8/Y31/io1' 175s Info: constrained 'P1B3' to bel 'X13/Y31/io1' 175s Info: constrained 'P1B4' to bel 'X16/Y31/io1' 175s Info: constrained 'P1B7' to bel 'X8/Y31/io0' 175s Info: constrained 'P1B8' to bel 'X9/Y31/io1' 175s Info: constrained 'P1B9' to bel 'X16/Y31/io0' 175s Info: constrained 'P1B10' to bel 'X17/Y31/io0' 175s Info: constrained 'LED1' to bel 'X18/Y31/io1' 175s Info: constrained 'LED2' to bel 'X19/Y31/io1' 175s Info: constrained 'LED3' to bel 'X18/Y0/io1' 175s Info: constrained 'BTN2' to bel 'X21/Y0/io1' 175s Info: constrained 'LED5' to bel 'X18/Y31/io0' 175s Info: constrained 'LED4' to bel 'X19/Y31/io0' 175s Info: constrained 'BTN1' to bel 'X19/Y0/io1' 175s Info: constrained 'BTN3' to bel 'X22/Y0/io1' 175s 175s Info: Packing constants.. 175s Info: Packing IOs.. 175s Info: Packing LUT-FFs.. 175s Info: 22 LCs used as LUT4 only 175s Info: 27 LCs used as LUT4 and DFF 175s Info: Packing non-LUT FFs.. 175s Info: 5 LCs used as DFF only 175s Info: Packing carries.. 175s Info: 0 LCs used as CARRY only 175s Info: Packing indirect carry+LUT pairs... 175s Info: 0 LUTs merged into carry LCs 175s Info: Packing RAMs.. 175s Info: Placing PLLs.. 175s Info: Packing special functions.. 175s Info: Packing PLLs.. 175s Info: Promoting globals.. 175s Info: promoting CLK$SB_IO_IN (fanout 32) 175s Info: Constraining chains... 175s Info: 1 LCs used to legalise carry chains. 175s Info: Checksum: 0xb7f7ed8b 175s 175s Info: Annotating ports with timing budgets for target frequency 12.00 MHz 175s Info: Checksum: 0xed88872c 175s 175s Info: Device utilisation: 175s Info: ICESTORM_LC: 57/ 5280 1% 175s Info: ICESTORM_RAM: 0/ 30 0% 175s Info: SB_IO: 28/ 96 29% 175s Info: SB_GB: 1/ 8 12% 175s Info: ICESTORM_PLL: 0/ 1 0% 175s Info: SB_WARMBOOT: 0/ 1 0% 175s Info: ICESTORM_DSP: 0/ 8 0% 175s Info: ICESTORM_HFOSC: 0/ 1 0% 175s Info: ICESTORM_LFOSC: 0/ 1 0% 175s Info: SB_I2C: 0/ 2 0% 175s Info: SB_SPI: 0/ 2 0% 175s Info: IO_I3C: 0/ 2 0% 175s Info: SB_LEDDA_IP: 0/ 1 0% 175s Info: SB_RGBA_DRV: 0/ 1 0% 175s Info: ICESTORM_SPRAM: 0/ 4 0% 175s 175s Info: Placed 28 cells based on constraints. 175s Info: Creating initial analytic placement for 30 cells, random placement wirelen = 1117. 175s Info: at initial placer iter 0, wirelen = 243 175s Info: at initial placer iter 1, wirelen = 245 175s Info: at initial placer iter 2, wirelen = 242 175s Info: at initial placer iter 3, wirelen = 245 175s Info: Running main analytical placer, max placement attempts per cell = 10000. 175s Info: at iteration #1, type ICESTORM_LC: wirelen solved = 242, spread = 260, legal = 288; time = 0.00s 175s Info: at iteration #1, type SB_GB: wirelen solved = 288, spread = 288, legal = 288; time = 0.00s 175s Info: at iteration #1, type ALL: wirelen solved = 245, spread = 265, legal = 299; time = 0.00s 175s Info: HeAP Placer Time: 0.01s 175s Info: of which solving equations: 0.00s 175s Info: of which spreading cells: 0.00s 175s Info: of which strict legalisation: 0.00s 175s 175s Info: Running simulated annealing placer for refinement. 175s Info: at iteration #1: temp = 0.000000, timing cost = 10, wirelen = 299 175s Info: at iteration #5: temp = 0.000000, timing cost = 10, wirelen = 252 175s Info: at iteration #10: temp = 0.000000, timing cost = 10, wirelen = 250 175s Info: at iteration #11: temp = 0.000000, timing cost = 10, wirelen = 248 175s Info: SA placement time 0.01s 175s 175s Info: Max frequency for clock 'CLK$SB_IO_IN_$glb_clk': 76.86 MHz (PASS at 12.00 MHz) 175s 175s Info: Max delay -> : 11.07 ns 175s Info: Max delay posedge CLK$SB_IO_IN_$glb_clk -> : 12.54 ns 175s 175s Info: Slack histogram: 175s Info: legend: * represents 1 endpoint(s) 175s Info: + represents [1,1) endpoint(s) 175s Info: [ 70323, 70775) |*** 175s Info: [ 70775, 71227) |* 175s Info: [ 71227, 71679) |* 175s Info: [ 71679, 72131) |********* 175s Info: [ 72131, 72583) |*** 175s Info: [ 72583, 73035) |** 175s Info: [ 73035, 73487) |** 175s Info: [ 73487, 73939) |* 175s Info: [ 73939, 74391) |* 175s Info: [ 74391, 74843) |** 175s Info: [ 74843, 75295) |****** 175s Info: [ 75295, 75747) |**** 175s Info: [ 75747, 76199) |*** 175s Info: [ 76199, 76651) |**** 175s Info: [ 76651, 77103) |* 175s Info: [ 77103, 77555) |*** 175s Info: [ 77555, 78007) |* 175s Info: [ 78007, 78459) | 175s Info: [ 78459, 78911) | 175s Info: [ 78911, 79363) |********************************** 175s Info: Checksum: 0xa7f4dfe8 175s 175s Info: Routing.. 175s Info: Setting up routing queue. 175s Info: Routing 194 arcs. 175s Info: | (re-)routed arcs | delta | remaining| time spent | 175s Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| 175s Info: 194 | 0 172 | 0 172 | 0| 0.24 0.24| 175s Info: Routing complete. 175s Info: Router1 time 0.24s 175s Info: Checksum: 0x5b3eaafc 175s 175s Info: Critical path report for clock 'CLK$SB_IO_IN_$glb_clk' (posedge -> posedge): 175s Info: curr total 175s Info: 1.4 1.4 Source counter_SB_LUT4_I3_LC.O 175s Info: 1.8 3.2 Net counter[0] budget 72.830002 ns (15,25) -> (16,25) 175s Info: Sink $nextpnr_ICESTORM_LC_0.I1 175s Info: Defined in: 175s Info: example.v:29.14-29.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.7 3.8 Source $nextpnr_ICESTORM_LC_0.COUT 175s Info: 0.0 3.8 Net $nextpnr_ICESTORM_LC_0$O budget 0.000000 ns (16,25) -> (16,25) 175s Info: Sink counter_SB_LUT4_I2_15_LC.CIN 175s Info: 0.3 4.1 Source counter_SB_LUT4_I2_15_LC.COUT 175s Info: 0.0 4.1 Net counter_SB_CARRY_CI_CO[2] budget 0.000000 ns (16,25) -> (16,25) 175s Info: Sink counter_SB_LUT4_I2_7_LC.CIN 175s Info: Defined in: 175s Info: example.v:29.14-29.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.3 4.4 Source counter_SB_LUT4_I2_7_LC.COUT 175s Info: 0.0 4.4 Net counter_SB_CARRY_CI_CO[3] budget 0.000000 ns (16,25) -> (16,25) 175s Info: Sink counter_SB_LUT4_I2_6_LC.CIN 175s Info: Defined in: 175s Info: example.v:29.14-29.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.3 4.7 Source counter_SB_LUT4_I2_6_LC.COUT 175s Info: 0.0 4.7 Net counter_SB_CARRY_CI_CO[4] budget 0.000000 ns (16,25) -> (16,25) 175s Info: Sink counter_SB_LUT4_I2_5_LC.CIN 175s Info: Defined in: 175s Info: example.v:29.14-29.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.3 4.9 Source counter_SB_LUT4_I2_5_LC.COUT 175s Info: 0.0 4.9 Net counter_SB_CARRY_CI_CO[5] budget 0.000000 ns (16,25) -> (16,25) 175s Info: Sink counter_SB_LUT4_I2_4_LC.CIN 175s Info: Defined in: 175s Info: example.v:29.14-29.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.3 5.2 Source counter_SB_LUT4_I2_4_LC.COUT 175s Info: 0.0 5.2 Net counter_SB_CARRY_CI_CO[6] budget 0.000000 ns (16,25) -> (16,25) 175s Info: Sink counter_SB_LUT4_I2_3_LC.CIN 175s Info: Defined in: 175s Info: example.v:29.14-29.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.3 5.5 Source counter_SB_LUT4_I2_3_LC.COUT 175s Info: 0.0 5.5 Net counter_SB_CARRY_CI_CO[7] budget 0.000000 ns (16,25) -> (16,25) 175s Info: Sink counter_SB_LUT4_I2_2_LC.CIN 175s Info: Defined in: 175s Info: example.v:29.14-29.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.3 5.8 Source counter_SB_LUT4_I2_2_LC.COUT 175s Info: 0.6 6.3 Net counter_SB_CARRY_CI_CO[8] budget 0.560000 ns (16,25) -> (16,26) 175s Info: Sink counter_SB_LUT4_I2_1_LC.CIN 175s Info: Defined in: 175s Info: example.v:29.14-29.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.3 6.6 Source counter_SB_LUT4_I2_1_LC.COUT 175s Info: 0.0 6.6 Net counter_SB_CARRY_CI_CO[9] budget 0.000000 ns (16,26) -> (16,26) 175s Info: Sink counter_SB_LUT4_I2_LC.CIN 175s Info: Defined in: 175s Info: example.v:29.14-29.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.3 6.9 Source counter_SB_LUT4_I2_LC.COUT 175s Info: 0.0 6.9 Net counter_SB_CARRY_CI_CO[10] budget 0.000000 ns (16,26) -> (16,26) 175s Info: Sink counter_SB_LUT4_I2_25_LC.CIN 175s Info: Defined in: 175s Info: example.v:29.14-29.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.3 7.2 Source counter_SB_LUT4_I2_25_LC.COUT 175s Info: 0.0 7.2 Net counter_SB_CARRY_CI_CO[11] budget 0.000000 ns (16,26) -> (16,26) 175s Info: Sink counter_SB_LUT4_I2_24_LC.CIN 175s Info: Defined in: 175s Info: example.v:29.14-29.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.3 7.4 Source counter_SB_LUT4_I2_24_LC.COUT 175s Info: 0.0 7.4 Net counter_SB_CARRY_CI_CO[12] budget 0.000000 ns (16,26) -> (16,26) 175s Info: Sink counter_SB_LUT4_I2_23_LC.CIN 175s Info: Defined in: 175s Info: example.v:29.14-29.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.3 7.7 Source counter_SB_LUT4_I2_23_LC.COUT 175s Info: 0.0 7.7 Net counter_SB_CARRY_CI_CO[13] budget 0.000000 ns (16,26) -> (16,26) 175s Info: Sink counter_SB_LUT4_I2_22_LC.CIN 175s Info: Defined in: 175s Info: example.v:29.14-29.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.3 8.0 Source counter_SB_LUT4_I2_22_LC.COUT 175s Info: 0.0 8.0 Net counter_SB_CARRY_CI_CO[14] budget 0.000000 ns (16,26) -> (16,26) 175s Info: Sink counter_SB_LUT4_I2_21_LC.CIN 175s Info: Defined in: 175s Info: example.v:29.14-29.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.3 8.3 Source counter_SB_LUT4_I2_21_LC.COUT 175s Info: 0.0 8.3 Net counter_SB_CARRY_CI_CO[15] budget 0.000000 ns (16,26) -> (16,26) 175s Info: Sink counter_SB_LUT4_I2_20_LC.CIN 175s Info: Defined in: 175s Info: example.v:29.14-29.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.3 8.6 Source counter_SB_LUT4_I2_20_LC.COUT 175s Info: 0.6 9.1 Net counter_SB_CARRY_CI_CO[16] budget 0.560000 ns (16,26) -> (16,27) 175s Info: Sink counter_SB_LUT4_I2_19_LC.CIN 175s Info: Defined in: 175s Info: example.v:29.14-29.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.3 9.4 Source counter_SB_LUT4_I2_19_LC.COUT 175s Info: 0.0 9.4 Net counter_SB_CARRY_CI_CO[17] budget 0.000000 ns (16,27) -> (16,27) 175s Info: Sink counter_SB_LUT4_I2_18_LC.CIN 175s Info: Defined in: 175s Info: example.v:29.14-29.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.3 9.7 Source counter_SB_LUT4_I2_18_LC.COUT 175s Info: 0.0 9.7 Net counter_SB_CARRY_CI_CO[18] budget 0.000000 ns (16,27) -> (16,27) 175s Info: Sink counter_SB_LUT4_I2_17_LC.CIN 175s Info: Defined in: 175s Info: example.v:29.14-29.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.3 9.9 Source counter_SB_LUT4_I2_17_LC.COUT 175s Info: 0.0 9.9 Net counter_SB_CARRY_CI_CO[19] budget 0.000000 ns (16,27) -> (16,27) 175s Info: Sink counter_SB_LUT4_I2_16_LC.CIN 175s Info: Defined in: 175s Info: example.v:29.14-29.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.3 10.2 Source counter_SB_LUT4_I2_16_LC.COUT 175s Info: 0.0 10.2 Net counter_SB_CARRY_CI_CO[20] budget 0.000000 ns (16,27) -> (16,27) 175s Info: Sink counter_SB_LUT4_I2_14_LC.CIN 175s Info: Defined in: 175s Info: example.v:29.14-29.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.3 10.5 Source counter_SB_LUT4_I2_14_LC.COUT 175s Info: 0.0 10.5 Net counter_SB_CARRY_CI_CO[21] budget 0.000000 ns (16,27) -> (16,27) 175s Info: Sink counter_SB_LUT4_I2_13_LC.CIN 175s Info: Defined in: 175s Info: example.v:29.14-29.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.3 10.8 Source counter_SB_LUT4_I2_13_LC.COUT 175s Info: 0.0 10.8 Net counter_SB_CARRY_CI_CO[22] budget 0.000000 ns (16,27) -> (16,27) 175s Info: Sink counter_SB_LUT4_I2_12_LC.CIN 175s Info: Defined in: 175s Info: example.v:29.14-29.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.3 11.1 Source counter_SB_LUT4_I2_12_LC.COUT 175s Info: 0.0 11.1 Net counter_SB_CARRY_CI_CO[23] budget 0.000000 ns (16,27) -> (16,27) 175s Info: Sink counter_SB_LUT4_I2_11_LC.CIN 175s Info: Defined in: 175s Info: example.v:29.14-29.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.3 11.3 Source counter_SB_LUT4_I2_11_LC.COUT 175s Info: 0.6 11.9 Net counter_SB_CARRY_CI_CO[24] budget 0.560000 ns (16,27) -> (16,28) 175s Info: Sink counter_SB_LUT4_I2_10_LC.CIN 175s Info: Defined in: 175s Info: example.v:29.14-29.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.3 12.2 Source counter_SB_LUT4_I2_10_LC.COUT 175s Info: 0.0 12.2 Net counter_SB_CARRY_CI_CO[25] budget 0.000000 ns (16,28) -> (16,28) 175s Info: Sink counter_SB_LUT4_I2_9_LC.CIN 175s Info: Defined in: 175s Info: example.v:29.14-29.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.3 12.4 Source counter_SB_LUT4_I2_9_LC.COUT 175s Info: 0.7 13.1 Net counter_SB_CARRY_CI_CO[26] budget 0.660000 ns (16,28) -> (16,28) 175s Info: Sink counter_SB_LUT4_I2_8_LC.I3 175s Info: Defined in: 175s Info: example.v:29.14-29.25 175s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 175s Info: 0.8 13.9 Setup counter_SB_LUT4_I2_8_LC.I3 175s Info: 9.8 ns logic, 4.1 ns routing 175s 175s Info: Critical path report for cross-domain path '' -> '': 175s Info: curr total 175s Info: 0.0 0.0 Source BTN3$sb_io.D_IN_0 175s Info: 3.6 3.6 Net BTN3$SB_IO_IN budget 41.025002 ns (22,0) -> (17,1) 175s Info: Sink LEDG_N_SB_LUT4_O_LC.I3 175s Info: Defined in: 175s Info: example.v:13.8-13.12 175s Info: 0.9 4.5 Source LEDG_N_SB_LUT4_O_LC.O 175s Info: 7.0 11.5 Net LEDG_N$SB_IO_OUT budget 41.023998 ns (17,1) -> (13,31) 175s Info: Sink LEDG_N$sb_io.D_OUT_0 175s Info: Defined in: 175s Info: example.v:16.9-16.15 175s Info: 0.9 ns logic, 10.6 ns routing 175s 175s Info: Critical path report for cross-domain path 'posedge CLK$SB_IO_IN_$glb_clk' -> '': 175s Info: curr total 175s Info: 1.4 1.4 Source outcnt_SB_DFF_Q_1_DFFLC.O 175s Info: 7.5 8.9 Net outcnt[2] budget 40.330002 ns (16,28) -> (7,1) 175s Info: Sink P1A9_SB_LUT4_O_LC.I1 175s Info: Defined in: 175s Info: example.v:26.17-26.23 175s Info: 1.2 10.1 Source P1A9_SB_LUT4_O_LC.O 175s Info: 3.1 13.2 Net P1A9$SB_IO_OUT budget 40.328999 ns (7,1) -> (5,0) 175s Info: Sink P1A9$sb_io.D_OUT_0 175s Info: Defined in: 175s Info: example.v:18.45-18.49 175s Info: 2.6 ns logic, 10.5 ns routing 175s 175s Info: Max frequency for clock 'CLK$SB_IO_IN_$glb_clk': 71.80 MHz (PASS at 12.00 MHz) 175s 175s Info: Max delay -> : 11.52 ns 175s Info: Max delay posedge CLK$SB_IO_IN_$glb_clk -> : 13.17 ns 175s 175s Info: Slack histogram: 175s Info: legend: * represents 1 endpoint(s) 175s Info: + represents [1,1) endpoint(s) 175s Info: [ 69405, 69903) |** 175s Info: [ 69903, 70401) |** 175s Info: [ 70401, 70899) |* 175s Info: [ 70899, 71397) |*** 175s Info: [ 71397, 71895) |******** 175s Info: [ 71895, 72393) |** 175s Info: [ 72393, 72891) |*** 175s Info: [ 72891, 73389) | 175s Info: [ 73389, 73887) |** 175s Info: [ 73887, 74385) |* 175s Info: [ 74385, 74883) |** 175s Info: [ 74883, 75381) |**** 175s Info: [ 75381, 75879) |***** 175s Info: [ 75879, 76377) |** 175s Info: [ 76377, 76875) |***** 175s Info: [ 76875, 77373) |*** 175s Info: [ 77373, 77871) |** 175s Info: [ 77871, 78369) | 175s Info: [ 78369, 78867) | 175s Info: [ 78867, 79365) |********************************** 175s 175s Info: Program finished normally. 175s icetime -d up5k -mtr example.rpt example.asc 175s // Reading input .asc file.. 175s // Reading 5k chipdb file.. 176s // Creating timing netlist.. 176s // Timing estimate: 13.73 ns (72.84 MHz) 176s icepack example.asc example.bin 176s make: Leaving directory '/tmp/autopkgtest.rlxjW8/build.dCN/src/examples/icebreaker' 176s make: Entering directory '/tmp/autopkgtest.rlxjW8/build.dCN/src/examples/icemulti' 176s yosys -p "synth_ice40 -top top -json app0.json" app0.v 176s 176s /----------------------------------------------------------------------------\ 176s | | 176s | yosys -- Yosys Open SYnthesis Suite | 176s | | 176s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 176s | | 176s | Permission to use, copy, modify, and/or distribute this software for any | 176s | purpose with or without fee is hereby granted, provided that the above | 176s | copyright notice and this permission notice appear in all copies. | 176s | | 176s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 176s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 176s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 176s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 176s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 176s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 176s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 176s | | 176s \----------------------------------------------------------------------------/ 176s 176s Yosys 0.23 (git sha1 7ce5011c24b) 176s 176s 176s -- Parsing `app0.v' using frontend ` -vlog2k' -- 176s 176s 1. Executing Verilog-2005 frontend: app0.v 176s Parsing Verilog input from `app0.v' to AST representation. 176s Storing AST representation for module `$abstract\top'. 176s Successfully finished Verilog frontend. 176s 176s -- Running command `synth_ice40 -top top -json app0.json' -- 176s 176s 2. Executing SYNTH_ICE40 pass. 176s 176s 2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v 176s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation. 176s Generating RTLIL representation for module `\SB_IO'. 176s Generating RTLIL representation for module `\SB_GB_IO'. 176s Generating RTLIL representation for module `\SB_GB'. 176s Generating RTLIL representation for module `\SB_LUT4'. 176s Generating RTLIL representation for module `\SB_CARRY'. 176s Generating RTLIL representation for module `\SB_DFF'. 176s Generating RTLIL representation for module `\SB_DFFE'. 176s Generating RTLIL representation for module `\SB_DFFSR'. 176s Generating RTLIL representation for module `\SB_DFFR'. 176s Generating RTLIL representation for module `\SB_DFFSS'. 176s Generating RTLIL representation for module `\SB_DFFS'. 176s Generating RTLIL representation for module `\SB_DFFESR'. 176s Generating RTLIL representation for module `\SB_DFFER'. 176s Generating RTLIL representation for module `\SB_DFFESS'. 176s Generating RTLIL representation for module `\SB_DFFES'. 176s Generating RTLIL representation for module `\SB_DFFN'. 176s Generating RTLIL representation for module `\SB_DFFNE'. 176s Generating RTLIL representation for module `\SB_DFFNSR'. 176s Generating RTLIL representation for module `\SB_DFFNR'. 176s Generating RTLIL representation for module `\SB_DFFNSS'. 176s Generating RTLIL representation for module `\SB_DFFNS'. 176s Generating RTLIL representation for module `\SB_DFFNESR'. 176s Generating RTLIL representation for module `\SB_DFFNER'. 176s Generating RTLIL representation for module `\SB_DFFNESS'. 176s Generating RTLIL representation for module `\SB_DFFNES'. 176s Generating RTLIL representation for module `\SB_RAM40_4K'. 176s Generating RTLIL representation for module `\SB_RAM40_4KNR'. 176s Generating RTLIL representation for module `\SB_RAM40_4KNW'. 176s Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. 176s Generating RTLIL representation for module `\ICESTORM_LC'. 176s Generating RTLIL representation for module `\SB_PLL40_CORE'. 176s Generating RTLIL representation for module `\SB_PLL40_PAD'. 176s Generating RTLIL representation for module `\SB_PLL40_2_PAD'. 176s Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. 176s Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. 176s Generating RTLIL representation for module `\SB_WARMBOOT'. 176s Generating RTLIL representation for module `\SB_SPRAM256KA'. 176s Generating RTLIL representation for module `\SB_HFOSC'. 176s Generating RTLIL representation for module `\SB_LFOSC'. 176s Generating RTLIL representation for module `\SB_RGBA_DRV'. 176s Generating RTLIL representation for module `\SB_LED_DRV_CUR'. 176s Generating RTLIL representation for module `\SB_RGB_DRV'. 176s Generating RTLIL representation for module `\SB_I2C'. 176s Generating RTLIL representation for module `\SB_SPI'. 176s Generating RTLIL representation for module `\SB_LEDDA_IP'. 176s Generating RTLIL representation for module `\SB_FILTER_50NS'. 176s Generating RTLIL representation for module `\SB_IO_I3C'. 176s Generating RTLIL representation for module `\SB_IO_OD'. 176s Generating RTLIL representation for module `\SB_MAC16'. 176s Generating RTLIL representation for module `\ICESTORM_RAM'. 176s Successfully finished Verilog frontend. 176s 176s 2.2. Executing HIERARCHY pass (managing design hierarchy). 176s 176s 2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\top'. 176s Generating RTLIL representation for module `\top'. 176s 176s 2.3.1. Analyzing design hierarchy.. 176s Top module: \top 176s 176s 2.3.2. Analyzing design hierarchy.. 176s Top module: \top 176s Removing unused module `$abstract\top'. 176s Removed 1 unused modules. 176s 176s 2.4. Executing PROC pass (convert processes to netlists). 176s 176s 2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 176s Cleaned up 0 empty switches. 176s 176s 2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 176s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241 in module SB_DFFNES. 176s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234 in module SB_DFFNESS. 176s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230 in module SB_DFFNER. 176s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223 in module SB_DFFNESR. 176s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220 in module SB_DFFNS. 176s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217 in module SB_DFFNSS. 176s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214 in module SB_DFFNR. 176s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211 in module SB_DFFNSR. 176s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203 in module SB_DFFES. 176s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196 in module SB_DFFESS. 176s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192 in module SB_DFFER. 176s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185 in module SB_DFFESR. 176s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182 in module SB_DFFS. 176s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179 in module SB_DFFSS. 176s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176 in module SB_DFFR. 176s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173 in module SB_DFFSR. 176s Removed a total of 0 dead cases. 176s 176s 2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 176s Removed 8 redundant assignments. 176s Promoted 28 assignments to connections. 176s 176s 2.4.4. Executing PROC_INIT pass (extract init attributes). 176s Found init rule in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 176s Set init value: \Q = 1'0 176s Found init rule in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 176s Set init value: \Q = 1'0 176s Found init rule in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 176s Set init value: \Q = 1'0 176s Found init rule in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 176s Set init value: \Q = 1'0 176s Found init rule in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 176s Set init value: \Q = 1'0 176s Found init rule in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 176s Set init value: \Q = 1'0 176s Found init rule in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 176s Set init value: \Q = 1'0 176s Found init rule in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 176s Set init value: \Q = 1'0 176s Found init rule in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 176s Set init value: \Q = 1'0 176s Found init rule in `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 176s Set init value: \Q = 1'0 176s Found init rule in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 176s Set init value: \Q = 1'0 176s Found init rule in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 176s Set init value: \Q = 1'0 176s Found init rule in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 176s Set init value: \Q = 1'0 176s Found init rule in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 176s Set init value: \Q = 1'0 176s Found init rule in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 176s Set init value: \Q = 1'0 176s Found init rule in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 176s Set init value: \Q = 1'0 176s Found init rule in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 176s Set init value: \Q = 1'0 176s Found init rule in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 176s Set init value: \Q = 1'0 176s Found init rule in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 176s Set init value: \Q = 1'0 176s Found init rule in `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 176s Set init value: \Q = 1'0 176s Found init rule in `\top.$proc$app0.v:9$390'. 176s Set init value: \state = 1'0 176s Found init rule in `\top.$proc$app0.v:8$389'. 176s Set init value: \counter2 = 4'0000 176s Found init rule in `\top.$proc$app0.v:7$388'. 176s Set init value: \counter = 22'0000000000000000000000 176s 176s 2.4.5. Executing PROC_ARST pass (detect async resets in processes). 176s Found async reset \S in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 176s Found async reset \R in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 176s Found async reset \S in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 176s Found async reset \R in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 176s Found async reset \S in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 176s Found async reset \R in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 176s Found async reset \S in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 176s Found async reset \R in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 176s 176s 2.4.6. Executing PROC_ROM pass (convert switches to ROMs). 176s Converted 0 switches. 176s 176s 176s 2.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 176s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 176s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 176s 1/1: $0\Q[0:0] 176s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 176s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 176s 1/1: $0\Q[0:0] 176s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 176s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 176s 1/1: $0\Q[0:0] 176s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 176s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 176s 1/1: $0\Q[0:0] 176s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 176s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 176s 1/1: $0\Q[0:0] 176s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 176s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 176s 1/1: $0\Q[0:0] 176s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 176s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 176s 1/1: $0\Q[0:0] 176s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 176s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 176s 1/1: $0\Q[0:0] 176s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 176s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 176s 1/1: $0\Q[0:0] 176s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 176s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 176s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 176s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 176s 1/1: $0\Q[0:0] 176s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 176s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 176s 1/1: $0\Q[0:0] 176s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 176s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 176s 1/1: $0\Q[0:0] 176s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 176s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 176s 1/1: $0\Q[0:0] 176s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 176s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 176s 1/1: $0\Q[0:0] 176s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 176s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 176s 1/1: $0\Q[0:0] 176s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 176s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 176s 1/1: $0\Q[0:0] 176s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 176s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 176s 1/1: $0\Q[0:0] 176s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 176s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 176s 1/1: $0\Q[0:0] 176s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 176s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 176s Creating decoders for process `\top.$proc$app0.v:9$390'. 176s Creating decoders for process `\top.$proc$app0.v:8$389'. 176s Creating decoders for process `\top.$proc$app0.v:7$388'. 176s Creating decoders for process `\top.$proc$app0.v:11$381'. 176s 176s 2.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). 176s 176s 2.4.9. Executing PROC_DFF pass (convert process syncs to FFs). 176s Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 176s created $adff cell `$procdff$435' with negative edge clock and positive level reset. 176s Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 176s created $dff cell `$procdff$436' with negative edge clock. 176s Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 176s created $adff cell `$procdff$437' with negative edge clock and positive level reset. 176s Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 176s created $dff cell `$procdff$438' with negative edge clock. 176s Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 176s created $adff cell `$procdff$439' with negative edge clock and positive level reset. 176s Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 176s created $dff cell `$procdff$440' with negative edge clock. 176s Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 176s created $adff cell `$procdff$441' with negative edge clock and positive level reset. 176s Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 176s created $dff cell `$procdff$442' with negative edge clock. 176s Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 176s created $dff cell `$procdff$443' with negative edge clock. 176s Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 176s created $dff cell `$procdff$444' with negative edge clock. 176s Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 176s created $adff cell `$procdff$445' with positive edge clock and positive level reset. 176s Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 176s created $dff cell `$procdff$446' with positive edge clock. 176s Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 176s created $adff cell `$procdff$447' with positive edge clock and positive level reset. 176s Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 176s created $dff cell `$procdff$448' with positive edge clock. 176s Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 176s created $adff cell `$procdff$449' with positive edge clock and positive level reset. 176s Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 176s created $dff cell `$procdff$450' with positive edge clock. 176s Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 176s created $adff cell `$procdff$451' with positive edge clock and positive level reset. 176s Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 176s created $dff cell `$procdff$452' with positive edge clock. 176s Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 176s created $dff cell `$procdff$453' with positive edge clock. 176s Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 176s created $dff cell `$procdff$454' with positive edge clock. 176s Creating register for signal `\top.\counter' using process `\top.$proc$app0.v:11$381'. 176s created $dff cell `$procdff$455' with positive edge clock. 176s Creating register for signal `\top.\counter2' using process `\top.$proc$app0.v:11$381'. 176s created $dff cell `$procdff$456' with positive edge clock. 176s Creating register for signal `\top.\state' using process `\top.$proc$app0.v:11$381'. 176s created $dff cell `$procdff$457' with positive edge clock. 176s 176s 2.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 176s 176s 2.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 176s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 176s Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 176s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 176s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 176s Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 176s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 176s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 176s Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 176s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 176s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 176s Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 176s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 176s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 176s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 176s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 176s Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 176s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 176s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 176s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 176s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 176s Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 176s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 176s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 176s Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 176s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 176s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 176s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 176s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 176s Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 176s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 176s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 176s Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 176s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 176s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 176s Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 176s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 176s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 176s Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 176s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 176s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 176s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 176s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 176s Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 176s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 176s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 176s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 176s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 176s Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 176s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 176s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 176s Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 176s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 176s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 176s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 176s Removing empty process `top.$proc$app0.v:9$390'. 176s Removing empty process `top.$proc$app0.v:8$389'. 176s Removing empty process `top.$proc$app0.v:7$388'. 176s Removing empty process `top.$proc$app0.v:11$381'. 176s Cleaned up 18 empty switches. 176s 176s 2.4.12. Executing OPT_EXPR pass (perform const folding). 176s Optimizing module top. 176s 176s 2.5. Executing FLATTEN pass (flatten design). 176s 176s 2.6. Executing TRIBUF pass. 176s 176s 2.7. Executing DEMINOUT pass (demote inout ports to input or output). 176s 176s 2.8. Executing OPT_EXPR pass (perform const folding). 176s Optimizing module top. 176s 176s 2.9. Executing OPT_CLEAN pass (remove unused cells and wires). 176s Finding unused cells or wires in module \top.. 176s Removed 0 unused cells and 5 unused wires. 176s 176s 176s 2.10. Executing CHECK pass (checking for obvious problems). 176s Checking module top... 176s Found and reported 0 problems. 176s 176s 2.11. Executing OPT pass (performing simple optimizations). 176s 176s 2.11.1. Executing OPT_EXPR pass (perform const folding). 176s Optimizing module top. 176s 176s 2.11.2. Executing OPT_MERGE pass (detect identical cells). 176s Finding identical cells in module `\top'. 176s Removed a total of 0 cells. 176s 176s 2.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 176s Running muxtree optimizer on module \top.. 176s Creating internal representation of mux trees. 176s No muxes found in this module. 176s Removed 0 multiplexer ports. 176s 176s 2.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 176s Optimizing cells in module \top. 176s Performed a total of 0 changes. 176s 176s 2.11.5. Executing OPT_MERGE pass (detect identical cells). 176s Finding identical cells in module `\top'. 176s Removed a total of 0 cells. 176s 176s 2.11.6. Executing OPT_DFF pass (perform DFF optimizations). 176s 176s 2.11.7. Executing OPT_CLEAN pass (remove unused cells and wires). 176s Finding unused cells or wires in module \top.. 176s 176s 2.11.8. Executing OPT_EXPR pass (perform const folding). 176s Optimizing module top. 176s 176s 2.11.9. Finished OPT passes. (There is nothing left to do.) 176s 176s 2.12. Executing FSM pass (extract and optimize FSM). 176s 176s 2.12.1. Executing FSM_DETECT pass (finding FSMs in design). 176s 176s 2.12.2. Executing FSM_EXTRACT pass (extracting FSM from design). 176s 176s 2.12.3. Executing FSM_OPT pass (simple optimizations of FSMs). 176s 176s 2.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). 176s Finding unused cells or wires in module \top.. 176s 176s 2.12.5. Executing FSM_OPT pass (simple optimizations of FSMs). 176s 176s 2.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 176s 176s 2.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 176s 176s 2.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 176s 176s 2.13. Executing OPT pass (performing simple optimizations). 176s 176s 2.13.1. Executing OPT_EXPR pass (perform const folding). 176s Optimizing module top. 176s 176s 2.13.2. Executing OPT_MERGE pass (detect identical cells). 176s Finding identical cells in module `\top'. 176s Removed a total of 0 cells. 176s 176s 2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 176s Running muxtree optimizer on module \top.. 176s Creating internal representation of mux trees. 176s No muxes found in this module. 176s Removed 0 multiplexer ports. 176s 176s 2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 176s Optimizing cells in module \top. 176s Performed a total of 0 changes. 176s 176s 2.13.5. Executing OPT_MERGE pass (detect identical cells). 176s Finding identical cells in module `\top'. 176s Removed a total of 0 cells. 176s 176s 2.13.6. Executing OPT_DFF pass (perform DFF optimizations). 176s 176s 2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). 176s Finding unused cells or wires in module \top.. 176s 176s 2.13.8. Executing OPT_EXPR pass (perform const folding). 176s Optimizing module top. 176s 176s 2.13.9. Finished OPT passes. (There is nothing left to do.) 176s 176s 2.14. Executing WREDUCE pass (reducing word size of cells). 176s Removed top 31 bits (of 32) from port B of cell top.$add$app0.v:12$382 ($add). 176s Removed top 10 bits (of 32) from port Y of cell top.$add$app0.v:12$382 ($add). 176s Removed top 3 bits (of 4) from port B of cell top.$add$app0.v:13$384 ($add). 176s Removed top 3 bits (of 4) from wire top.$logic_not$app0.v:13$383_Y. 176s 176s 2.15. Executing PEEPOPT pass (run peephole optimizers). 176s 176s 2.16. Executing OPT_CLEAN pass (remove unused cells and wires). 176s Finding unused cells or wires in module \top.. 176s Removed 0 unused cells and 2 unused wires. 176s 176s 176s 2.17. Executing SHARE pass (SAT-based resource sharing). 176s 176s 2.18. Executing TECHMAP pass (map to technology primitives). 176s 176s 2.18.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v 176s Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation. 176s Generating RTLIL representation for module `\_90_lut_cmp_'. 176s Successfully finished Verilog frontend. 176s 176s 2.18.2. Continuing TECHMAP pass. 176s No more expansions possible. 176s 176s 176s 2.19. Executing OPT_EXPR pass (perform const folding). 176s Optimizing module top. 176s 176s 2.20. Executing OPT_CLEAN pass (remove unused cells and wires). 176s Finding unused cells or wires in module \top.. 176s 176s 2.21. Executing ALUMACC pass (create $alu and $macc cells). 176s Extracting $alu and $macc cells in module top: 176s creating $macc model for $add$app0.v:12$382 ($add). 176s creating $macc model for $add$app0.v:13$384 ($add). 176s creating $alu model for $macc $add$app0.v:13$384. 176s creating $alu model for $macc $add$app0.v:12$382. 176s creating $alu cell for $add$app0.v:12$382: $auto$alumacc.cc:485:replace_alu$460 176s creating $alu cell for $add$app0.v:13$384: $auto$alumacc.cc:485:replace_alu$463 176s created 2 $alu and 0 $macc cells. 176s 176s 2.22. Executing OPT pass (performing simple optimizations). 176s 176s 2.22.1. Executing OPT_EXPR pass (perform const folding). 176s Optimizing module top. 176s 176s 2.22.2. Executing OPT_MERGE pass (detect identical cells). 176s Finding identical cells in module `\top'. 176s 176s Removed a total of 1 cells. 176s 176s 2.22.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 176s Running muxtree optimizer on module \top.. 176s Creating internal representation of mux trees. 176s No muxes found in this module. 176s Removed 0 multiplexer ports. 176s 176s 2.22.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 176s Optimizing cells in module \top. 176s Performed a total of 0 changes. 176s 176s 2.22.5. Executing OPT_MERGE pass (detect identical cells). 176s Finding identical cells in module `\top'. 176s Removed a total of 0 cells. 176s 176s 2.22.6. Executing OPT_DFF pass (perform DFF optimizations). 176s 176s 2.22.7. Executing OPT_CLEAN pass (remove unused cells and wires). 176s Finding unused cells or wires in module \top.. 176s Removed 0 unused cells and 1 unused wires. 176s 176s 176s 2.22.8. Executing OPT_EXPR pass (perform const folding). 176s Optimizing module top. 176s 176s 2.22.9. Rerunning OPT passes. (Maybe there is more to do..) 176s 176s 2.22.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 176s Running muxtree optimizer on module \top.. 176s Creating internal representation of mux trees. 176s No muxes found in this module. 176s Removed 0 multiplexer ports. 176s 176s 2.22.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 176s Optimizing cells in module \top. 176s Performed a total of 0 changes. 176s 176s 2.22.12. Executing OPT_MERGE pass (detect identical cells). 176s Finding identical cells in module `\top'. 176s Removed a total of 0 cells. 176s 176s 2.22.13. Executing OPT_DFF pass (perform DFF optimizations). 176s 176s 2.22.14. Executing OPT_CLEAN pass (remove unused cells and wires). 176s Finding unused cells or wires in module \top.. 176s 176s 2.22.15. Executing OPT_EXPR pass (perform const folding). 176s Optimizing module top. 176s 176s 2.22.16. Finished OPT passes. (There is nothing left to do.) 176s 176s 2.23. Executing MEMORY pass. 176s 176s 2.23.1. Executing OPT_MEM pass (optimize memories). 176s Performed a total of 0 transformations. 176s 176s 2.23.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). 176s Performed a total of 0 transformations. 176s 176s 2.23.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 176s 176s 2.23.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 176s 176s 2.23.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 176s 176s 2.23.6. Executing OPT_CLEAN pass (remove unused cells and wires). 176s Finding unused cells or wires in module \top.. 176s 176s 2.23.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 176s 176s 2.23.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). 176s Performed a total of 0 transformations. 176s 176s 2.23.9. Executing OPT_CLEAN pass (remove unused cells and wires). 176s Finding unused cells or wires in module \top.. 176s 176s 2.23.10. Executing MEMORY_COLLECT pass (generating $mem cells). 176s 176s 2.24. Executing OPT_CLEAN pass (remove unused cells and wires). 176s Finding unused cells or wires in module \top.. 176s 176s 2.25. Executing MEMORY_LIBMAP pass (mapping memories to cells). 176s 176s 2.26. Executing TECHMAP pass (map to technology primitives). 176s 176s 2.26.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v 177s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation. 177s Generating RTLIL representation for module `\$__ICE40_RAM4K_'. 177s Successfully finished Verilog frontend. 177s 177s 2.26.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/spram_map.v 177s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/spram_map.v' to AST representation. 177s Generating RTLIL representation for module `\$__ICE40_SPRAM_'. 177s Successfully finished Verilog frontend. 177s 177s 2.26.3. Continuing TECHMAP pass. 177s No more expansions possible. 177s 177s 177s 2.27. Executing ICE40_BRAMINIT pass. 177s 177s 2.28. Executing OPT pass (performing simple optimizations). 177s 177s 2.28.1. Executing OPT_EXPR pass (perform const folding). 177s Optimizing module top. 177s 177s 2.28.2. Executing OPT_MERGE pass (detect identical cells). 177s Finding identical cells in module `\top'. 177s Removed a total of 0 cells. 177s 177s 2.28.3. Executing OPT_DFF pass (perform DFF optimizations). 177s 177s 2.28.4. Executing OPT_CLEAN pass (remove unused cells and wires). 177s Finding unused cells or wires in module \top.. 177s 177s 2.28.5. Finished fast OPT passes. 177s 177s 2.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 177s 177s 2.30. Executing OPT pass (performing simple optimizations). 177s 177s 2.30.1. Executing OPT_EXPR pass (perform const folding). 177s Optimizing module top. 177s 177s 2.30.2. Executing OPT_MERGE pass (detect identical cells). 177s Finding identical cells in module `\top'. 177s Removed a total of 0 cells. 177s 177s 2.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 177s Running muxtree optimizer on module \top.. 177s Creating internal representation of mux trees. 177s No muxes found in this module. 177s Removed 0 multiplexer ports. 177s 177s 2.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 177s Optimizing cells in module \top. 177s Performed a total of 0 changes. 177s 177s 2.30.5. Executing OPT_MERGE pass (detect identical cells). 177s Finding identical cells in module `\top'. 177s Removed a total of 0 cells. 177s 177s 2.30.6. Executing OPT_DFF pass (perform DFF optimizations). 177s 177s 2.30.7. Executing OPT_CLEAN pass (remove unused cells and wires). 177s Finding unused cells or wires in module \top.. 177s 177s 2.30.8. Executing OPT_EXPR pass (perform const folding). 177s Optimizing module top. 177s 177s 2.30.9. Finished OPT passes. (There is nothing left to do.) 177s 177s 2.31. Executing ICE40_WRAPCARRY pass (wrap carries). 177s 177s 2.32. Executing TECHMAP pass (map to technology primitives). 177s 177s 2.32.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v 177s Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation. 177s Generating RTLIL representation for module `\_90_simplemap_bool_ops'. 177s Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. 177s Generating RTLIL representation for module `\_90_simplemap_logic_ops'. 177s Generating RTLIL representation for module `\_90_simplemap_compare_ops'. 177s Generating RTLIL representation for module `\_90_simplemap_various'. 177s Generating RTLIL representation for module `\_90_simplemap_registers'. 177s Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. 177s Generating RTLIL representation for module `\_90_shift_shiftx'. 177s Generating RTLIL representation for module `\_90_fa'. 177s Generating RTLIL representation for module `\_90_lcu'. 177s Generating RTLIL representation for module `\_90_alu'. 177s Generating RTLIL representation for module `\_90_macc'. 177s Generating RTLIL representation for module `\_90_alumacc'. 177s Generating RTLIL representation for module `\$__div_mod_u'. 177s Generating RTLIL representation for module `\$__div_mod_trunc'. 177s Generating RTLIL representation for module `\_90_div'. 177s Generating RTLIL representation for module `\_90_mod'. 177s Generating RTLIL representation for module `\$__div_mod_floor'. 177s Generating RTLIL representation for module `\_90_divfloor'. 177s Generating RTLIL representation for module `\_90_modfloor'. 177s Generating RTLIL representation for module `\_90_pow'. 177s Generating RTLIL representation for module `\_90_pmux'. 177s Generating RTLIL representation for module `\_90_demux'. 177s Generating RTLIL representation for module `\_90_lut'. 177s Successfully finished Verilog frontend. 177s 177s 2.32.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v 177s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation. 177s Generating RTLIL representation for module `\_80_ice40_alu'. 177s Successfully finished Verilog frontend. 177s 177s 2.32.3. Continuing TECHMAP pass. 177s Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_80_ice40_alu for cells of type $alu. 177s Using extmapper simplemap for cells of type $logic_not. 177s Using template $paramod$080e6a70eb8bfa1ccf22d9718e795074645029a4\_80_ice40_alu for cells of type $alu. 177s Using extmapper simplemap for cells of type $xor. 177s Using extmapper simplemap for cells of type $reduce_and. 177s Using extmapper simplemap for cells of type $dff. 177s Using extmapper simplemap for cells of type $mux. 177s Using extmapper simplemap for cells of type $not. 177s Using extmapper simplemap for cells of type $pos. 177s No more expansions possible. 177s 177s 177s 2.33. Executing OPT pass (performing simple optimizations). 177s 177s 2.33.1. Executing OPT_EXPR pass (perform const folding). 177s Optimizing module top. 177s 177s 177s 2.33.2. Executing OPT_MERGE pass (detect identical cells). 177s Finding identical cells in module `\top'. 177s 177s Removed a total of 1 cells. 177s 177s 2.33.3. Executing OPT_DFF pass (perform DFF optimizations). 177s 177s 2.33.4. Executing OPT_CLEAN pass (remove unused cells and wires). 177s Finding unused cells or wires in module \top.. 177s Removed 27 unused cells and 34 unused wires. 177s 177s 177s 2.33.5. Finished fast OPT passes. 177s 177s 2.34. Executing ICE40_OPT pass (performing simple optimizations). 177s 177s 2.34.1. Running ICE40 specific optimizations. 177s Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$460.slice[0].carry: CO=\counter [0] 177s 177s 2.34.2. Executing OPT_EXPR pass (perform const folding). 177s Optimizing module top. 177s 177s 2.34.3. Executing OPT_MERGE pass (detect identical cells). 177s Finding identical cells in module `\top'. 177s Removed a total of 0 cells. 177s 177s 2.34.4. Executing OPT_DFF pass (perform DFF optimizations). 177s 177s 2.34.5. Executing OPT_CLEAN pass (remove unused cells and wires). 177s Finding unused cells or wires in module \top.. 177s 177s 2.34.6. Rerunning OPT passes. (Removed registers in this run.) 177s 177s 2.34.7. Running ICE40 specific optimizations. 177s 177s 2.34.8. Executing OPT_EXPR pass (perform const folding). 177s Optimizing module top. 177s 177s 2.34.9. Executing OPT_MERGE pass (detect identical cells). 177s Finding identical cells in module `\top'. 177s Removed a total of 0 cells. 177s 177s 2.34.10. Executing OPT_DFF pass (perform DFF optimizations). 177s 177s 2.34.11. Executing OPT_CLEAN pass (remove unused cells and wires). 177s Finding unused cells or wires in module \top.. 177s 177s 2.34.12. Finished OPT passes. (There is nothing left to do.) 177s 177s 2.35. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 177s 177s 2.36. Executing TECHMAP pass (map to technology primitives). 177s 177s 2.36.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 177s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 177s Generating RTLIL representation for module `\$_DFF_N_'. 177s Generating RTLIL representation for module `\$_DFF_P_'. 177s Generating RTLIL representation for module `\$_DFFE_NP_'. 177s Generating RTLIL representation for module `\$_DFFE_PP_'. 177s Generating RTLIL representation for module `\$_DFF_NP0_'. 177s Generating RTLIL representation for module `\$_DFF_NP1_'. 177s Generating RTLIL representation for module `\$_DFF_PP0_'. 177s Generating RTLIL representation for module `\$_DFF_PP1_'. 177s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 177s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 177s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 177s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 177s Generating RTLIL representation for module `\$_SDFF_NP0_'. 177s Generating RTLIL representation for module `\$_SDFF_NP1_'. 177s Generating RTLIL representation for module `\$_SDFF_PP0_'. 177s Generating RTLIL representation for module `\$_SDFF_PP1_'. 177s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 177s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 177s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 177s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 177s Successfully finished Verilog frontend. 177s 177s 2.36.2. Continuing TECHMAP pass. 177s Using template \$_DFF_P_ for cells of type $_DFF_P_. 177s No more expansions possible. 177s 177s 177s 2.37. Executing OPT_EXPR pass (perform const folding). 177s Optimizing module top. 177s 177s 2.38. Executing SIMPLEMAP pass (map simple cells to gate primitives). 177s Mapping top.$auto$alumacc.cc:485:replace_alu$460.slice[0].carry ($lut). 177s 177s 2.39. Executing ICE40_OPT pass (performing simple optimizations). 177s 177s 2.39.1. Running ICE40 specific optimizations. 177s 177s 2.39.2. Executing OPT_EXPR pass (perform const folding). 177s Optimizing module top. 177s 177s 177s 2.39.3. Executing OPT_MERGE pass (detect identical cells). 177s Finding identical cells in module `\top'. 177s Removed a total of 0 cells. 177s 177s 2.39.4. Executing OPT_DFF pass (perform DFF optimizations). 177s 177s 2.39.5. Executing OPT_CLEAN pass (remove unused cells and wires). 177s Finding unused cells or wires in module \top.. 177s Removed 0 unused cells and 112 unused wires. 177s 177s 177s 2.39.6. Rerunning OPT passes. (Removed registers in this run.) 177s 177s 2.39.7. Running ICE40 specific optimizations. 177s 177s 2.39.8. Executing OPT_EXPR pass (perform const folding). 177s Optimizing module top. 177s 177s 2.39.9. Executing OPT_MERGE pass (detect identical cells). 177s Finding identical cells in module `\top'. 177s Removed a total of 0 cells. 177s 177s 2.39.10. Executing OPT_DFF pass (perform DFF optimizations). 177s 177s 2.39.11. Executing OPT_CLEAN pass (remove unused cells and wires). 177s Finding unused cells or wires in module \top.. 177s 177s 2.39.12. Finished OPT passes. (There is nothing left to do.) 177s 177s 2.40. Executing TECHMAP pass (map to technology primitives). 177s 177s 2.40.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v 177s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation. 177s Generating RTLIL representation for module `\$_DLATCH_N_'. 177s Generating RTLIL representation for module `\$_DLATCH_P_'. 177s Successfully finished Verilog frontend. 177s 177s 2.40.2. Continuing TECHMAP pass. 177s No more expansions possible. 177s 177s 177s 2.41. Executing ABC pass (technology mapping using ABC). 177s 177s 2.41.1. Extracting gate netlist of module `\top' to `/input.blif'.. 177s Extracted 27 gates and 54 wires to a netlist network with 27 inputs and 4 outputs. 177s 177s 2.41.1.1. Executing ABC. 177s Running ABC command: "berkeley-abc" -s -f /abc.script 2>&1 177s ABC: ABC command line: "source /abc.script". 177s ABC: 177s ABC: + read_blif /input.blif 177s ABC: + read_lut /lutdefs.txt 177s ABC: + strash 177s ABC: + &get -n 177s ABC: + &fraig -x 177s ABC: + &put 177s ABC: + scorr 177s ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). 177s ABC: + dc2 177s ABC: + dretime 177s ABC: + strash 177s ABC: + dch -f 177s ABC: + if 177s ABC: + mfs2 177s ABC: + lutpack -S 1 177s ABC: + dress /input.blif 177s ABC: Total number of equiv classes = 5. 177s ABC: Participating nodes from both networks = 9. 177s ABC: Participating nodes from the first network = 4. ( 30.77 % of nodes) 177s ABC: Participating nodes from the second network = 5. ( 38.46 % of nodes) 177s ABC: Node pairs (any polarity) = 4. ( 30.77 % of names can be moved) 177s ABC: Node pairs (same polarity) = 4. ( 30.77 % of names can be moved) 177s ABC: Total runtime = 0.06 sec 177s ABC: + write_blif /output.blif 177s 177s 2.41.1.2. Re-integrating ABC results. 177s ABC RESULTS: $lut cells: 12 177s ABC RESULTS: internal signals: 23 177s ABC RESULTS: input signals: 27 177s ABC RESULTS: output signals: 4 177s Removing temp directory. 177s 177s 2.42. Executing ICE40_WRAPCARRY pass (wrap carries). 177s 177s 2.43. Executing TECHMAP pass (map to technology primitives). 177s 177s 2.43.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 177s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 177s Generating RTLIL representation for module `\$_DFF_N_'. 177s Generating RTLIL representation for module `\$_DFF_P_'. 177s Generating RTLIL representation for module `\$_DFFE_NP_'. 177s Generating RTLIL representation for module `\$_DFFE_PP_'. 177s Generating RTLIL representation for module `\$_DFF_NP0_'. 177s Generating RTLIL representation for module `\$_DFF_NP1_'. 177s Generating RTLIL representation for module `\$_DFF_PP0_'. 177s Generating RTLIL representation for module `\$_DFF_PP1_'. 177s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 177s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 177s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 177s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 177s Generating RTLIL representation for module `\$_SDFF_NP0_'. 177s Generating RTLIL representation for module `\$_SDFF_NP1_'. 177s Generating RTLIL representation for module `\$_SDFF_PP0_'. 177s Generating RTLIL representation for module `\$_SDFF_PP1_'. 177s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 177s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 177s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 177s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 177s Successfully finished Verilog frontend. 177s 177s 2.43.2. Continuing TECHMAP pass. 177s No more expansions possible. 177s 177s Removed 2 unused cells and 39 unused wires. 177s 177s 2.44. Executing OPT_LUT pass (optimize LUTs). 177s Discovering LUTs. 177s Number of LUTs: 37 177s 1-LUT 1 177s 2-LUT 4 177s 3-LUT 25 177s 4-LUT 7 177s with \SB_CARRY (#0) 23 177s with \SB_CARRY (#1) 23 177s 177s Eliminating LUTs. 177s Number of LUTs: 37 177s 1-LUT 1 177s 2-LUT 4 177s 3-LUT 25 177s 4-LUT 7 177s with \SB_CARRY (#0) 23 177s with \SB_CARRY (#1) 23 177s 177s Combining LUTs. 177s Number of LUTs: 37 177s 1-LUT 1 177s 2-LUT 4 177s 3-LUT 25 177s 4-LUT 7 177s with \SB_CARRY (#0) 23 177s with \SB_CARRY (#1) 23 177s 177s Eliminated 0 LUTs. 177s Combined 0 LUTs. 177s 177s 177s 2.45. Executing TECHMAP pass (map to technology primitives). 177s 177s 2.45.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v 177s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation. 177s Generating RTLIL representation for module `\$lut'. 177s Successfully finished Verilog frontend. 177s 177s 2.45.2. Continuing TECHMAP pass. 177s Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut. 177s Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut. 177s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut. 177s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. 177s Using template $paramod$415b9dd3a15783ae56c103f189fd8e182f997441\$lut for cells of type $lut. 177s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. 177s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. 177s Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut. 177s No more expansions possible. 177s 177s Removed 0 unused cells and 78 unused wires. 177s 177s 2.46. Executing AUTONAME pass. 177s Renamed 463 objects in module top (10 iterations). 177s 177s 177s 2.47. Executing HIERARCHY pass (managing design hierarchy). 177s 177s 2.47.1. Analyzing design hierarchy.. 177s Top module: \top 177s 177s 2.47.2. Analyzing design hierarchy.. 177s Top module: \top 177s Removed 0 unused modules. 177s 177s 2.48. Printing statistics. 177s 177s === top === 177s 177s Number of wires: 20 177s Number of wire bits: 99 177s Number of public wires: 20 177s Number of public wire bits: 99 177s Number of memories: 0 177s Number of memory bits: 0 177s Number of processes: 0 177s Number of cells: 88 177s SB_CARRY 23 177s SB_DFF 27 177s SB_LUT4 37 177s SB_WARMBOOT 1 177s 177s 2.49. Executing CHECK pass (checking for obvious problems). 177s Checking module top... 177s Found and reported 0 problems. 177s 177s 2.50. Executing JSON backend. 177s 177s End of script. Logfile hash: b99a73dca2, CPU: user 0.68s system 0.01s, MEM: 19.88 MB peak 177s Yosys 0.23 (git sha1 7ce5011c24b) 177s Time spent: 54% 13x read_verilog (0 sec), 19% 1x abc (0 sec), ... 177s nextpnr-ice40 --hx1k --package tq144 --asc app0.asc --pcf icestick.pcf --json app0.json 177s Warning: unmatched constraint 'RX' (on line 4) 177s Warning: unmatched constraint 'TX' (on line 5) 177s Info: constrained 'LED1' to bel 'X13/Y12/io1' 177s Info: constrained 'LED2' to bel 'X13/Y12/io0' 177s Info: constrained 'LED3' to bel 'X13/Y11/io1' 177s Info: constrained 'LED4' to bel 'X13/Y11/io0' 177s Info: constrained 'LED5' to bel 'X13/Y9/io1' 177s Info: constrained 'clk' to bel 'X0/Y8/io1' 177s 177s Info: Packing constants.. 177s Info: Packing IOs.. 177s Info: Packing LUT-FFs.. 177s Info: 10 LCs used as LUT4 only 177s Info: 27 LCs used as LUT4 and DFF 177s Info: Packing non-LUT FFs.. 177s Info: 0 LCs used as DFF only 177s Info: Packing carries.. 177s Info: 0 LCs used as CARRY only 177s Info: Packing indirect carry+LUT pairs... 177s Info: 0 LUTs merged into carry LCs 177s Info: Packing RAMs.. 177s Info: Placing PLLs.. 177s Info: Packing special functions.. 177s Info: Packing PLLs.. 177s Info: Promoting globals.. 177s Info: promoting clk$SB_IO_IN (fanout 27) 177s Info: Constraining chains... 177s Info: 1 LCs used to legalise carry chains. 177s Info: Checksum: 0x431c6341 177s 177s Info: Annotating ports with timing budgets for target frequency 12.00 MHz 177s Info: Checksum: 0x82f7d2ce 177s 177s Info: Device utilisation: 177s Info: ICESTORM_LC: 40/ 1280 3% 177s Info: ICESTORM_RAM: 0/ 16 0% 177s Info: SB_IO: 6/ 112 5% 177s Info: SB_GB: 1/ 8 12% 177s Info: ICESTORM_PLL: 0/ 1 0% 177s Info: SB_WARMBOOT: 1/ 1 100% 177s 177s Info: Placed 6 cells based on constraints. 177s Info: Creating initial analytic placement for 18 cells, random placement wirelen = 358. 177s Info: at initial placer iter 0, wirelen = 38 177s Info: at initial placer iter 1, wirelen = 14 177s Info: at initial placer iter 2, wirelen = 14 177s Info: at initial placer iter 3, wirelen = 14 177s Info: Running main analytical placer, max placement attempts per cell = 10000. 177s Info: at iteration #1, type ICESTORM_LC: wirelen solved = 16, spread = 61, legal = 87; time = 0.00s 177s Info: at iteration #1, type SB_GB: wirelen solved = 87, spread = 87, legal = 87; time = 0.00s 177s Info: at iteration #1, type SB_WARMBOOT: wirelen solved = 87, spread = 87, legal = 147; time = 0.00s 177s Info: at iteration #1, type ALL: wirelen solved = 39, spread = 112, legal = 170; time = 0.00s 177s Info: at iteration #2, type ICESTORM_LC: wirelen solved = 91, spread = 119, legal = 145; time = 0.00s 177s Info: at iteration #2, type SB_GB: wirelen solved = 145, spread = 145, legal = 145; time = 0.00s 177s Info: at iteration #2, type SB_WARMBOOT: wirelen solved = 93, spread = 93, legal = 145; time = 0.00s 177s Info: at iteration #2, type ALL: wirelen solved = 19, spread = 60, legal = 121; time = 0.00s 177s Info: at iteration #3, type ICESTORM_LC: wirelen solved = 84, spread = 121, legal = 124; time = 0.00s 177s Info: at iteration #3, type SB_GB: wirelen solved = 124, spread = 124, legal = 124; time = 0.00s 177s Info: at iteration #3, type SB_WARMBOOT: wirelen solved = 68, spread = 68, legal = 124; time = 0.00s 177s Info: at iteration #3, type ALL: wirelen solved = 24, spread = 62, legal = 121; time = 0.00s 177s Info: at iteration #4, type ICESTORM_LC: wirelen solved = 84, spread = 127, legal = 132; time = 0.00s 177s Info: at iteration #4, type SB_GB: wirelen solved = 132, spread = 132, legal = 132; time = 0.00s 177s Info: at iteration #4, type SB_WARMBOOT: wirelen solved = 76, spread = 76, legal = 132; time = 0.00s 177s Info: at iteration #4, type ALL: wirelen solved = 21, spread = 61, legal = 121; time = 0.00s 177s Info: at iteration #5, type ICESTORM_LC: wirelen solved = 84, spread = 127, legal = 130; time = 0.00s 177s Info: at iteration #5, type SB_GB: wirelen solved = 130, spread = 130, legal = 130; time = 0.00s 177s Info: at iteration #5, type SB_WARMBOOT: wirelen solved = 74, spread = 74, legal = 130; time = 0.00s 177s Info: at iteration #5, type ALL: wirelen solved = 33, spread = 61, legal = 121; time = 0.00s 177s Info: at iteration #6, type ICESTORM_LC: wirelen solved = 86, spread = 127, legal = 130; time = 0.00s 177s Info: at iteration #6, type SB_GB: wirelen solved = 130, spread = 130, legal = 130; time = 0.00s 177s Info: at iteration #6, type SB_WARMBOOT: wirelen solved = 74, spread = 74, legal = 130; time = 0.00s 177s Info: at iteration #6, type ALL: wirelen solved = 30, spread = 61, legal = 121; time = 0.00s 177s Info: at iteration #7, type ICESTORM_LC: wirelen solved = 85, spread = 125, legal = 133; time = 0.00s 177s Info: at iteration #7, type SB_GB: wirelen solved = 133, spread = 133, legal = 133; time = 0.00s 177s Info: at iteration #7, type SB_WARMBOOT: wirelen solved = 77, spread = 77, legal = 133; time = 0.00s 177s Info: at iteration #7, type ALL: wirelen solved = 28, spread = 64, legal = 121; time = 0.00s 177s Info: HeAP Placer Time: 0.02s 177s Info: of which solving equations: 0.01s 177s Info: of which spreading cells: 0.00s 177s Info: of which strict legalisation: 0.00s 177s 177s Info: Running simulated annealing placer for refinement. 177s Info: at iteration #1: temp = 0.000000, timing cost = 16, wirelen = 121 177s Info: at iteration #5: temp = 0.000000, timing cost = 17, wirelen = 103 177s Info: at iteration #8: temp = 0.000000, timing cost = 17, wirelen = 103 177s Info: SA placement time 0.01s 177s 177s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 192.23 MHz (PASS at 12.00 MHz) 177s 177s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> : 3.94 ns 177s 177s Info: Slack histogram: 177s Info: legend: * represents 1 endpoint(s) 177s Info: + represents [1,1) endpoint(s) 177s Info: [ 78131, 78318) |** 177s Info: [ 78318, 78505) |*** 177s Info: [ 78505, 78692) |* 177s Info: [ 78692, 78879) |*** 177s Info: [ 78879, 79066) |* 177s Info: [ 79066, 79253) | 177s Info: [ 79253, 79440) |** 177s Info: [ 79440, 79627) |** 177s Info: [ 79627, 79814) |**** 177s Info: [ 79814, 80001) |** 177s Info: [ 80001, 80188) |** 177s Info: [ 80188, 80375) | 177s Info: [ 80375, 80562) | 177s Info: [ 80562, 80749) |** 177s Info: [ 80749, 80936) |* 177s Info: [ 80936, 81123) |** 177s Info: [ 81123, 81310) |* 177s Info: [ 81310, 81497) | 177s Info: [ 81497, 81684) |* 177s Info: [ 81684, 81871) |**************************** 177s Info: Checksum: 0xe16e8e03 177s 177s Info: Routing.. 177s Info: Setting up routing queue. 177s Info: Routing 127 arcs. 177s Info: | (re-)routed arcs | delta | remaining| time spent | 177s Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| 177s Info: 127 | 0 107 | 0 107 | 0| 0.01 0.01| 177s Info: Routing complete. 177s Info: Router1 time 0.01s 177s Info: Checksum: 0xe8a7aef0 177s 177s Info: Critical path report for clock 'clk$SB_IO_IN_$glb_clk' (posedge -> posedge): 177s Info: curr total 177s Info: 0.5 0.5 Source counter_SB_LUT4_I2_3_LC.O 177s Info: 0.6 1.1 Net counter[6] budget 20.292999 ns (12,10) -> (11,11) 177s Info: Sink state_SB_LUT4_I3_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_LC.I0 177s Info: Defined in: 177s Info: app0.v:7.22-7.29 177s Info: 0.4 1.6 Source state_SB_LUT4_I3_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_LC.O 177s Info: 0.6 2.2 Net state_SB_LUT4_I3_I0_SB_LUT4_O_1_I2[0] budget 20.292999 ns (11,11) -> (11,11) 177s Info: Sink state_SB_LUT4_I3_I0_SB_LUT4_O_1_LC.I2 177s Info: Defined in: 177s Info: /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 177s Info: 0.4 2.5 Source state_SB_LUT4_I3_I0_SB_LUT4_O_1_LC.O 177s Info: 0.6 3.1 Net state_SB_LUT4_I3_I0[1] budget 20.292000 ns (11,11) -> (11,10) 177s Info: Sink counter2_SB_LUT4_I2_3_I1_SB_LUT4_O_LC.I2 177s Info: Defined in: 177s Info: /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 177s Info: 0.4 3.5 Source counter2_SB_LUT4_I2_3_I1_SB_LUT4_O_LC.O 177s Info: 0.6 4.1 Net counter2_SB_LUT4_I2_3_I1 budget 20.292000 ns (11,10) -> (11,9) 177s Info: Sink counter2_SB_LUT4_I2_3_LC.I1 177s Info: Defined in: 177s Info: app0.v:13.15-13.34 177s Info: /usr/bin/../share/yosys/ice40/arith_map.v:29.22-29.23 177s Info: 0.3 4.4 Source counter2_SB_LUT4_I2_3_LC.COUT 177s Info: 0.0 4.4 Net counter2_SB_CARRY_I1_CO[1] budget 0.000000 ns (11,9) -> (11,9) 177s Info: Sink counter2_SB_LUT4_I2_2_LC.CIN 177s Info: Defined in: 177s Info: app0.v:13.15-13.34 177s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 177s Info: 0.1 4.5 Source counter2_SB_LUT4_I2_2_LC.COUT 177s Info: 0.0 4.5 Net counter2_SB_CARRY_I1_CO[2] budget 0.000000 ns (11,9) -> (11,9) 177s Info: Sink counter2_SB_LUT4_I2_1_LC.CIN 177s Info: Defined in: 177s Info: app0.v:13.15-13.34 177s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 177s Info: 0.1 4.6 Source counter2_SB_LUT4_I2_1_LC.COUT 177s Info: 0.3 4.9 Net counter2_SB_CARRY_I1_CO[3] budget 0.260000 ns (11,9) -> (11,9) 177s Info: Sink counter2_SB_LUT4_I2_LC.I3 177s Info: Defined in: 177s Info: app0.v:13.15-13.34 177s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 177s Info: 0.3 5.2 Setup counter2_SB_LUT4_I2_LC.I3 177s Info: 2.6 ns logic, 2.6 ns routing 177s 177s Info: Critical path report for cross-domain path 'posedge clk$SB_IO_IN_$glb_clk' -> '': 177s Info: curr total 177s Info: 0.5 0.5 Source counter2_SB_LUT4_I2_3_LC.O 177s Info: 0.6 1.1 Net counter2[0] budget 41.173000 ns (11,9) -> (11,9) 177s Info: Sink WB_BOOT_SB_LUT4_O_LC.I0 177s Info: Defined in: 177s Info: app0.v:8.12-8.20 177s Info: 0.4 1.6 Source WB_BOOT_SB_LUT4_O_LC.O 177s Info: 1.4 3.0 Net WB_BOOT budget 41.172001 ns (11,9) -> (0,0) 177s Info: Sink WB.BOOT 177s Info: Defined in: 177s Info: app0.v:24.9-24.18 177s Info: 1.0 ns logic, 2.0 ns routing 177s 177s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 192.23 MHz (PASS at 12.00 MHz) 177s 177s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> : 3.02 ns 177s 177s Info: Slack histogram: 177s Info: legend: * represents 1 endpoint(s) 177s Info: + represents [1,1) endpoint(s) 177s Info: [ 78131, 78318) |** 177s Info: [ 78318, 78505) |** 177s Info: [ 78505, 78692) |** 177s Info: [ 78692, 78879) |** 177s Info: [ 78879, 79066) |** 177s Info: [ 79066, 79253) | 177s Info: [ 79253, 79440) |* 177s Info: [ 79440, 79627) |* 177s Info: [ 79627, 79814) |***** 177s Info: [ 79814, 80001) |* 177s Info: [ 80001, 80188) |*** 177s Info: [ 80188, 80375) |* 177s Info: [ 80375, 80562) | 177s Info: [ 80562, 80749) |** 177s Info: [ 80749, 80936) |* 177s Info: [ 80936, 81123) |** 177s Info: [ 81123, 81310) |* 177s Info: [ 81310, 81497) | 177s Info: [ 81497, 81684) |* 177s Info: [ 81684, 81871) |**************************** 177s 2 warnings, 0 errors 177s 177s Info: Program finished normally. 177s icetime -d hx1k -c 25 app0.asc 177s // Reading input .asc file.. 177s // Reading 1k chipdb file.. 177s // Creating timing netlist.. 177s // Timing estimate: 5.28 ns (189.29 MHz) 177s // Checking 40.00 ns (25.00 MHz) clock constraint: PASSED. 177s icepack app0.asc app0.bin 177s yosys -p "synth_ice40 -top top -json app1.json" app1.v 177s 177s /----------------------------------------------------------------------------\ 177s | | 177s | yosys -- Yosys Open SYnthesis Suite | 177s | | 177s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 177s | | 177s | Permission to use, copy, modify, and/or distribute this software for any | 177s | purpose with or without fee is hereby granted, provided that the above | 177s | copyright notice and this permission notice appear in all copies. | 177s | | 177s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 177s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 177s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 177s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 177s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 177s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 177s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 177s | | 177s \----------------------------------------------------------------------------/ 177s 177s Yosys 0.23 (git sha1 7ce5011c24b) 177s 177s 177s -- Parsing `app1.v' using frontend ` -vlog2k' -- 177s 177s 1. Executing Verilog-2005 frontend: app1.v 177s Parsing Verilog input from `app1.v' to AST representation. 177s Storing AST representation for module `$abstract\top'. 177s Successfully finished Verilog frontend. 177s 177s -- Running command `synth_ice40 -top top -json app1.json' -- 177s 177s 2. Executing SYNTH_ICE40 pass. 177s 177s 2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v 177s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation. 177s Generating RTLIL representation for module `\SB_IO'. 177s Generating RTLIL representation for module `\SB_GB_IO'. 177s Generating RTLIL representation for module `\SB_GB'. 177s Generating RTLIL representation for module `\SB_LUT4'. 177s Generating RTLIL representation for module `\SB_CARRY'. 177s Generating RTLIL representation for module `\SB_DFF'. 177s Generating RTLIL representation for module `\SB_DFFE'. 177s Generating RTLIL representation for module `\SB_DFFSR'. 177s Generating RTLIL representation for module `\SB_DFFR'. 177s Generating RTLIL representation for module `\SB_DFFSS'. 177s Generating RTLIL representation for module `\SB_DFFS'. 177s Generating RTLIL representation for module `\SB_DFFESR'. 177s Generating RTLIL representation for module `\SB_DFFER'. 177s Generating RTLIL representation for module `\SB_DFFESS'. 177s Generating RTLIL representation for module `\SB_DFFES'. 177s Generating RTLIL representation for module `\SB_DFFN'. 177s Generating RTLIL representation for module `\SB_DFFNE'. 177s Generating RTLIL representation for module `\SB_DFFNSR'. 177s Generating RTLIL representation for module `\SB_DFFNR'. 177s Generating RTLIL representation for module `\SB_DFFNSS'. 177s Generating RTLIL representation for module `\SB_DFFNS'. 177s Generating RTLIL representation for module `\SB_DFFNESR'. 177s Generating RTLIL representation for module `\SB_DFFNER'. 177s Generating RTLIL representation for module `\SB_DFFNESS'. 177s Generating RTLIL representation for module `\SB_DFFNES'. 177s Generating RTLIL representation for module `\SB_RAM40_4K'. 177s Generating RTLIL representation for module `\SB_RAM40_4KNR'. 177s Generating RTLIL representation for module `\SB_RAM40_4KNW'. 177s Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. 177s Generating RTLIL representation for module `\ICESTORM_LC'. 177s Generating RTLIL representation for module `\SB_PLL40_CORE'. 177s Generating RTLIL representation for module `\SB_PLL40_PAD'. 177s Generating RTLIL representation for module `\SB_PLL40_2_PAD'. 177s Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. 177s Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. 177s Generating RTLIL representation for module `\SB_WARMBOOT'. 177s Generating RTLIL representation for module `\SB_SPRAM256KA'. 177s Generating RTLIL representation for module `\SB_HFOSC'. 177s Generating RTLIL representation for module `\SB_LFOSC'. 177s Generating RTLIL representation for module `\SB_RGBA_DRV'. 177s Generating RTLIL representation for module `\SB_LED_DRV_CUR'. 177s Generating RTLIL representation for module `\SB_RGB_DRV'. 177s Generating RTLIL representation for module `\SB_I2C'. 177s Generating RTLIL representation for module `\SB_SPI'. 177s Generating RTLIL representation for module `\SB_LEDDA_IP'. 177s Generating RTLIL representation for module `\SB_FILTER_50NS'. 177s Generating RTLIL representation for module `\SB_IO_I3C'. 177s Generating RTLIL representation for module `\SB_IO_OD'. 177s Generating RTLIL representation for module `\SB_MAC16'. 177s Generating RTLIL representation for module `\ICESTORM_RAM'. 177s Successfully finished Verilog frontend. 177s 177s 2.2. Executing HIERARCHY pass (managing design hierarchy). 177s 177s 2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\top'. 177s Generating RTLIL representation for module `\top'. 177s 177s 2.3.1. Analyzing design hierarchy.. 177s Top module: \top 177s 177s 2.3.2. Analyzing design hierarchy.. 177s Top module: \top 177s Removing unused module `$abstract\top'. 177s Removed 1 unused modules. 177s 177s 2.4. Executing PROC pass (convert processes to netlists). 177s 177s 2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 177s Cleaned up 0 empty switches. 177s 177s 2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 177s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241 in module SB_DFFNES. 177s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234 in module SB_DFFNESS. 177s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230 in module SB_DFFNER. 177s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223 in module SB_DFFNESR. 177s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220 in module SB_DFFNS. 177s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217 in module SB_DFFNSS. 177s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214 in module SB_DFFNR. 177s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211 in module SB_DFFNSR. 177s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203 in module SB_DFFES. 177s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196 in module SB_DFFESS. 177s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192 in module SB_DFFER. 177s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185 in module SB_DFFESR. 177s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182 in module SB_DFFS. 177s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179 in module SB_DFFSS. 177s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176 in module SB_DFFR. 177s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173 in module SB_DFFSR. 177s Removed a total of 0 dead cases. 177s 177s 2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 177s Removed 8 redundant assignments. 177s Promoted 28 assignments to connections. 177s 177s 2.4.4. Executing PROC_INIT pass (extract init attributes). 177s Found init rule in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 177s Set init value: \Q = 1'0 177s Found init rule in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 177s Set init value: \Q = 1'0 177s Found init rule in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 177s Set init value: \Q = 1'0 177s Found init rule in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 177s Set init value: \Q = 1'0 177s Found init rule in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 177s Set init value: \Q = 1'0 177s Found init rule in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 177s Set init value: \Q = 1'0 177s Found init rule in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 177s Set init value: \Q = 1'0 177s Found init rule in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 177s Set init value: \Q = 1'0 177s Found init rule in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 177s Set init value: \Q = 1'0 177s Found init rule in `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 177s Set init value: \Q = 1'0 177s Found init rule in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 177s Set init value: \Q = 1'0 177s Found init rule in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 177s Set init value: \Q = 1'0 177s Found init rule in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 177s Set init value: \Q = 1'0 177s Found init rule in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 177s Set init value: \Q = 1'0 177s Found init rule in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 177s Set init value: \Q = 1'0 177s Found init rule in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 177s Set init value: \Q = 1'0 177s Found init rule in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 177s Set init value: \Q = 1'0 177s Found init rule in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 177s Set init value: \Q = 1'0 177s Found init rule in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 177s Set init value: \Q = 1'0 177s Found init rule in `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 177s Set init value: \Q = 1'0 177s Found init rule in `\top.$proc$app1.v:9$390'. 177s Set init value: \state = 1'0 177s Found init rule in `\top.$proc$app1.v:8$389'. 177s Set init value: \counter2 = 4'0000 177s Found init rule in `\top.$proc$app1.v:7$388'. 177s Set init value: \counter = 22'0000000000000000000000 177s 177s 2.4.5. Executing PROC_ARST pass (detect async resets in processes). 177s Found async reset \S in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 177s Found async reset \R in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 177s Found async reset \S in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 177s Found async reset \R in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 177s Found async reset \S in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 177s Found async reset \R in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 177s Found async reset \S in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 177s Found async reset \R in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 177s 177s 2.4.6. Executing PROC_ROM pass (convert switches to ROMs). 177s Converted 0 switches. 177s 177s 177s 2.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 177s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 177s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 177s 1/1: $0\Q[0:0] 177s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 177s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 177s 1/1: $0\Q[0:0] 177s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 177s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 177s 1/1: $0\Q[0:0] 177s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 177s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 177s 1/1: $0\Q[0:0] 177s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 177s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 177s 1/1: $0\Q[0:0] 177s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 177s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 177s 1/1: $0\Q[0:0] 177s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 177s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 177s 1/1: $0\Q[0:0] 177s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 177s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 177s 1/1: $0\Q[0:0] 177s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 177s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 177s 1/1: $0\Q[0:0] 177s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 177s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 177s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 177s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 177s 1/1: $0\Q[0:0] 177s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 177s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 177s 1/1: $0\Q[0:0] 177s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 177s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 177s 1/1: $0\Q[0:0] 177s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 177s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 177s 1/1: $0\Q[0:0] 177s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 177s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 177s 1/1: $0\Q[0:0] 177s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 177s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 177s 1/1: $0\Q[0:0] 177s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 177s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 177s 1/1: $0\Q[0:0] 177s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 177s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 177s 1/1: $0\Q[0:0] 177s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 177s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 177s 1/1: $0\Q[0:0] 177s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 177s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 177s Creating decoders for process `\top.$proc$app1.v:9$390'. 177s Creating decoders for process `\top.$proc$app1.v:8$389'. 177s Creating decoders for process `\top.$proc$app1.v:7$388'. 177s Creating decoders for process `\top.$proc$app1.v:11$381'. 177s 177s 2.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). 177s 177s 2.4.9. Executing PROC_DFF pass (convert process syncs to FFs). 177s Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 177s created $adff cell `$procdff$435' with negative edge clock and positive level reset. 177s Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 177s created $dff cell `$procdff$436' with negative edge clock. 177s Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 177s created $adff cell `$procdff$437' with negative edge clock and positive level reset. 177s Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 177s created $dff cell `$procdff$438' with negative edge clock. 177s Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 177s created $adff cell `$procdff$439' with negative edge clock and positive level reset. 177s Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 177s created $dff cell `$procdff$440' with negative edge clock. 177s Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 177s created $adff cell `$procdff$441' with negative edge clock and positive level reset. 177s Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 177s created $dff cell `$procdff$442' with negative edge clock. 177s Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 177s created $dff cell `$procdff$443' with negative edge clock. 177s Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 177s created $dff cell `$procdff$444' with negative edge clock. 177s Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 177s created $adff cell `$procdff$445' with positive edge clock and positive level reset. 177s Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 177s created $dff cell `$procdff$446' with positive edge clock. 177s Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 177s created $adff cell `$procdff$447' with positive edge clock and positive level reset. 177s Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 177s created $dff cell `$procdff$448' with positive edge clock. 177s Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 177s created $adff cell `$procdff$449' with positive edge clock and positive level reset. 177s Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 177s created $dff cell `$procdff$450' with positive edge clock. 177s Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 177s created $adff cell `$procdff$451' with positive edge clock and positive level reset. 177s Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 177s created $dff cell `$procdff$452' with positive edge clock. 177s Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 177s created $dff cell `$procdff$453' with positive edge clock. 177s Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 177s created $dff cell `$procdff$454' with positive edge clock. 177s Creating register for signal `\top.\counter' using process `\top.$proc$app1.v:11$381'. 177s created $dff cell `$procdff$455' with positive edge clock. 177s Creating register for signal `\top.\counter2' using process `\top.$proc$app1.v:11$381'. 177s created $dff cell `$procdff$456' with positive edge clock. 177s Creating register for signal `\top.\state' using process `\top.$proc$app1.v:11$381'. 177s created $dff cell `$procdff$457' with positive edge clock. 177s 177s 2.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 177s 177s 2.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 177s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 177s Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 177s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 177s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 177s Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 177s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 177s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 177s Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 177s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 177s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 177s Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 177s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 177s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 177s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 177s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 177s Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 177s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 177s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 177s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 177s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 177s Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 177s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 177s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 177s Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 177s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 177s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 177s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 177s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 177s Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 177s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 177s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 177s Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 177s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 177s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 177s Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 177s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 177s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 177s Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 177s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 177s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 177s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 177s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 177s Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 177s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 177s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 177s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 177s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 177s Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 177s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 177s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 177s Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 177s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 177s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 177s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 177s Removing empty process `top.$proc$app1.v:9$390'. 177s Removing empty process `top.$proc$app1.v:8$389'. 177s Removing empty process `top.$proc$app1.v:7$388'. 177s Removing empty process `top.$proc$app1.v:11$381'. 177s Cleaned up 18 empty switches. 177s 177s 2.4.12. Executing OPT_EXPR pass (perform const folding). 177s Optimizing module top. 177s 177s 2.5. Executing FLATTEN pass (flatten design). 177s 177s 2.6. Executing TRIBUF pass. 177s 177s 2.7. Executing DEMINOUT pass (demote inout ports to input or output). 177s 177s 2.8. Executing OPT_EXPR pass (perform const folding). 177s Optimizing module top. 177s 177s 2.9. Executing OPT_CLEAN pass (remove unused cells and wires). 177s Finding unused cells or wires in module \top.. 177s Removed 0 unused cells and 5 unused wires. 177s 177s 177s 2.10. Executing CHECK pass (checking for obvious problems). 177s Checking module top... 177s Found and reported 0 problems. 177s 177s 2.11. Executing OPT pass (performing simple optimizations). 177s 177s 2.11.1. Executing OPT_EXPR pass (perform const folding). 177s Optimizing module top. 177s 177s 2.11.2. Executing OPT_MERGE pass (detect identical cells). 177s Finding identical cells in module `\top'. 177s Removed a total of 0 cells. 177s 177s 2.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 177s Running muxtree optimizer on module \top.. 177s Creating internal representation of mux trees. 177s No muxes found in this module. 177s Removed 0 multiplexer ports. 177s 177s 2.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 177s Optimizing cells in module \top. 177s Performed a total of 0 changes. 177s 177s 2.11.5. Executing OPT_MERGE pass (detect identical cells). 177s Finding identical cells in module `\top'. 177s Removed a total of 0 cells. 177s 177s 2.11.6. Executing OPT_DFF pass (perform DFF optimizations). 177s 177s 2.11.7. Executing OPT_CLEAN pass (remove unused cells and wires). 177s Finding unused cells or wires in module \top.. 177s 177s 2.11.8. Executing OPT_EXPR pass (perform const folding). 177s Optimizing module top. 177s 177s 2.11.9. Finished OPT passes. (There is nothing left to do.) 177s 177s 2.12. Executing FSM pass (extract and optimize FSM). 177s 177s 2.12.1. Executing FSM_DETECT pass (finding FSMs in design). 177s 177s 2.12.2. Executing FSM_EXTRACT pass (extracting FSM from design). 177s 177s 2.12.3. Executing FSM_OPT pass (simple optimizations of FSMs). 177s 177s 2.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). 177s Finding unused cells or wires in module \top.. 177s 177s 2.12.5. Executing FSM_OPT pass (simple optimizations of FSMs). 177s 177s 2.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 177s 177s 2.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 177s 177s 2.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 177s 177s 2.13. Executing OPT pass (performing simple optimizations). 177s 177s 2.13.1. Executing OPT_EXPR pass (perform const folding). 177s Optimizing module top. 177s 177s 2.13.2. Executing OPT_MERGE pass (detect identical cells). 177s Finding identical cells in module `\top'. 177s Removed a total of 0 cells. 177s 177s 2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 177s Running muxtree optimizer on module \top.. 177s Creating internal representation of mux trees. 177s No muxes found in this module. 177s Removed 0 multiplexer ports. 177s 177s 2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 177s Optimizing cells in module \top. 177s Performed a total of 0 changes. 177s 177s 2.13.5. Executing OPT_MERGE pass (detect identical cells). 177s Finding identical cells in module `\top'. 177s Removed a total of 0 cells. 177s 177s 2.13.6. Executing OPT_DFF pass (perform DFF optimizations). 177s 177s 2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). 177s Finding unused cells or wires in module \top.. 177s 177s 2.13.8. Executing OPT_EXPR pass (perform const folding). 177s Optimizing module top. 177s 177s 2.13.9. Finished OPT passes. (There is nothing left to do.) 177s 177s 2.14. Executing WREDUCE pass (reducing word size of cells). 177s Removed top 31 bits (of 32) from port B of cell top.$add$app1.v:12$382 ($add). 177s Removed top 10 bits (of 32) from port Y of cell top.$add$app1.v:12$382 ($add). 177s Removed top 3 bits (of 4) from port B of cell top.$add$app1.v:13$384 ($add). 177s Removed top 3 bits (of 4) from wire top.$logic_not$app1.v:13$383_Y. 177s 177s 2.15. Executing PEEPOPT pass (run peephole optimizers). 177s 177s 2.16. Executing OPT_CLEAN pass (remove unused cells and wires). 177s Finding unused cells or wires in module \top.. 177s Removed 0 unused cells and 2 unused wires. 177s 177s 177s 2.17. Executing SHARE pass (SAT-based resource sharing). 177s 177s 2.18. Executing TECHMAP pass (map to technology primitives). 177s 177s 2.18.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v 177s Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation. 177s Generating RTLIL representation for module `\_90_lut_cmp_'. 177s Successfully finished Verilog frontend. 177s 177s 2.18.2. Continuing TECHMAP pass. 177s No more expansions possible. 177s 177s 177s 2.19. Executing OPT_EXPR pass (perform const folding). 177s Optimizing module top. 177s 177s 2.20. Executing OPT_CLEAN pass (remove unused cells and wires). 177s Finding unused cells or wires in module \top.. 177s 177s 2.21. Executing ALUMACC pass (create $alu and $macc cells). 177s Extracting $alu and $macc cells in module top: 177s creating $macc model for $add$app1.v:12$382 ($add). 177s creating $macc model for $add$app1.v:13$384 ($add). 177s creating $alu model for $macc $add$app1.v:13$384. 177s creating $alu model for $macc $add$app1.v:12$382. 177s creating $alu cell for $add$app1.v:12$382: $auto$alumacc.cc:485:replace_alu$460 177s creating $alu cell for $add$app1.v:13$384: $auto$alumacc.cc:485:replace_alu$463 177s created 2 $alu and 0 $macc cells. 177s 177s 2.22. Executing OPT pass (performing simple optimizations). 177s 177s 2.22.1. Executing OPT_EXPR pass (perform const folding). 177s Optimizing module top. 177s 177s 2.22.2. Executing OPT_MERGE pass (detect identical cells). 177s Finding identical cells in module `\top'. 177s 177s Removed a total of 1 cells. 177s 177s 2.22.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 177s Running muxtree optimizer on module \top.. 177s Creating internal representation of mux trees. 177s No muxes found in this module. 177s Removed 0 multiplexer ports. 177s 177s 2.22.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 177s Optimizing cells in module \top. 177s Performed a total of 0 changes. 177s 177s 2.22.5. Executing OPT_MERGE pass (detect identical cells). 177s Finding identical cells in module `\top'. 177s Removed a total of 0 cells. 177s 177s 2.22.6. Executing OPT_DFF pass (perform DFF optimizations). 177s 177s 2.22.7. Executing OPT_CLEAN pass (remove unused cells and wires). 177s Finding unused cells or wires in module \top.. 177s Removed 0 unused cells and 1 unused wires. 177s 177s 177s 2.22.8. Executing OPT_EXPR pass (perform const folding). 177s Optimizing module top. 177s 177s 2.22.9. Rerunning OPT passes. (Maybe there is more to do..) 177s 177s 2.22.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 177s Running muxtree optimizer on module \top.. 177s Creating internal representation of mux trees. 177s No muxes found in this module. 177s Removed 0 multiplexer ports. 177s 177s 2.22.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 177s Optimizing cells in module \top. 177s Performed a total of 0 changes. 177s 177s 2.22.12. Executing OPT_MERGE pass (detect identical cells). 177s Finding identical cells in module `\top'. 177s Removed a total of 0 cells. 177s 177s 2.22.13. Executing OPT_DFF pass (perform DFF optimizations). 177s 177s 2.22.14. Executing OPT_CLEAN pass (remove unused cells and wires). 177s Finding unused cells or wires in module \top.. 177s 177s 2.22.15. Executing OPT_EXPR pass (perform const folding). 177s Optimizing module top. 177s 177s 2.22.16. Finished OPT passes. (There is nothing left to do.) 177s 177s 2.23. Executing MEMORY pass. 177s 177s 2.23.1. Executing OPT_MEM pass (optimize memories). 177s Performed a total of 0 transformations. 177s 177s 2.23.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). 177s Performed a total of 0 transformations. 177s 177s 2.23.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 177s 177s 2.23.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 177s 177s 2.23.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 177s 177s 2.23.6. Executing OPT_CLEAN pass (remove unused cells and wires). 177s Finding unused cells or wires in module \top.. 177s 177s 2.23.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 177s 177s 2.23.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). 177s Performed a total of 0 transformations. 177s 177s 2.23.9. Executing OPT_CLEAN pass (remove unused cells and wires). 177s Finding unused cells or wires in module \top.. 177s 177s 2.23.10. Executing MEMORY_COLLECT pass (generating $mem cells). 177s 177s 2.24. Executing OPT_CLEAN pass (remove unused cells and wires). 177s Finding unused cells or wires in module \top.. 177s 177s 2.25. Executing MEMORY_LIBMAP pass (mapping memories to cells). 177s 177s 2.26. Executing TECHMAP pass (map to technology primitives). 177s 177s 2.26.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v 178s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation. 178s Generating RTLIL representation for module `\$__ICE40_RAM4K_'. 178s Successfully finished Verilog frontend. 178s 178s 2.26.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/spram_map.v 178s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/spram_map.v' to AST representation. 178s Generating RTLIL representation for module `\$__ICE40_SPRAM_'. 178s Successfully finished Verilog frontend. 178s 178s 2.26.3. Continuing TECHMAP pass. 178s No more expansions possible. 178s 178s 178s 2.27. Executing ICE40_BRAMINIT pass. 178s 178s 2.28. Executing OPT pass (performing simple optimizations). 178s 178s 2.28.1. Executing OPT_EXPR pass (perform const folding). 178s Optimizing module top. 178s 178s 2.28.2. Executing OPT_MERGE pass (detect identical cells). 178s Finding identical cells in module `\top'. 178s Removed a total of 0 cells. 178s 178s 2.28.3. Executing OPT_DFF pass (perform DFF optimizations). 178s 178s 2.28.4. Executing OPT_CLEAN pass (remove unused cells and wires). 178s Finding unused cells or wires in module \top.. 178s 178s 2.28.5. Finished fast OPT passes. 178s 178s 2.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 178s 178s 2.30. Executing OPT pass (performing simple optimizations). 178s 178s 2.30.1. Executing OPT_EXPR pass (perform const folding). 178s Optimizing module top. 178s 178s 2.30.2. Executing OPT_MERGE pass (detect identical cells). 178s Finding identical cells in module `\top'. 178s Removed a total of 0 cells. 178s 178s 2.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 178s Running muxtree optimizer on module \top.. 178s Creating internal representation of mux trees. 178s No muxes found in this module. 178s Removed 0 multiplexer ports. 178s 178s 2.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 178s Optimizing cells in module \top. 178s Performed a total of 0 changes. 178s 178s 2.30.5. Executing OPT_MERGE pass (detect identical cells). 178s Finding identical cells in module `\top'. 178s Removed a total of 0 cells. 178s 178s 2.30.6. Executing OPT_DFF pass (perform DFF optimizations). 178s 178s 2.30.7. Executing OPT_CLEAN pass (remove unused cells and wires). 178s Finding unused cells or wires in module \top.. 178s 178s 2.30.8. Executing OPT_EXPR pass (perform const folding). 178s Optimizing module top. 178s 178s 2.30.9. Finished OPT passes. (There is nothing left to do.) 178s 178s 2.31. Executing ICE40_WRAPCARRY pass (wrap carries). 178s 178s 2.32. Executing TECHMAP pass (map to technology primitives). 178s 178s 2.32.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v 178s Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation. 178s Generating RTLIL representation for module `\_90_simplemap_bool_ops'. 178s Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. 178s Generating RTLIL representation for module `\_90_simplemap_logic_ops'. 178s Generating RTLIL representation for module `\_90_simplemap_compare_ops'. 178s Generating RTLIL representation for module `\_90_simplemap_various'. 178s Generating RTLIL representation for module `\_90_simplemap_registers'. 178s Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. 178s Generating RTLIL representation for module `\_90_shift_shiftx'. 178s Generating RTLIL representation for module `\_90_fa'. 178s Generating RTLIL representation for module `\_90_lcu'. 178s Generating RTLIL representation for module `\_90_alu'. 178s Generating RTLIL representation for module `\_90_macc'. 178s Generating RTLIL representation for module `\_90_alumacc'. 178s Generating RTLIL representation for module `\$__div_mod_u'. 178s Generating RTLIL representation for module `\$__div_mod_trunc'. 178s Generating RTLIL representation for module `\_90_div'. 178s Generating RTLIL representation for module `\_90_mod'. 178s Generating RTLIL representation for module `\$__div_mod_floor'. 178s Generating RTLIL representation for module `\_90_divfloor'. 178s Generating RTLIL representation for module `\_90_modfloor'. 178s Generating RTLIL representation for module `\_90_pow'. 178s Generating RTLIL representation for module `\_90_pmux'. 178s Generating RTLIL representation for module `\_90_demux'. 178s Generating RTLIL representation for module `\_90_lut'. 178s Successfully finished Verilog frontend. 178s 178s 2.32.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v 178s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation. 178s Generating RTLIL representation for module `\_80_ice40_alu'. 178s Successfully finished Verilog frontend. 178s 178s 2.32.3. Continuing TECHMAP pass. 178s Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_80_ice40_alu for cells of type $alu. 178s Using extmapper simplemap for cells of type $logic_not. 178s Using template $paramod$080e6a70eb8bfa1ccf22d9718e795074645029a4\_80_ice40_alu for cells of type $alu. 178s Using extmapper simplemap for cells of type $xor. 178s Using extmapper simplemap for cells of type $reduce_and. 178s Using extmapper simplemap for cells of type $dff. 178s Using extmapper simplemap for cells of type $mux. 178s Using extmapper simplemap for cells of type $not. 178s Using extmapper simplemap for cells of type $pos. 178s No more expansions possible. 178s 178s 178s 2.33. Executing OPT pass (performing simple optimizations). 178s 178s 2.33.1. Executing OPT_EXPR pass (perform const folding). 178s Optimizing module top. 178s 178s 178s 2.33.2. Executing OPT_MERGE pass (detect identical cells). 178s Finding identical cells in module `\top'. 178s 178s Removed a total of 1 cells. 178s 178s 2.33.3. Executing OPT_DFF pass (perform DFF optimizations). 178s 178s 2.33.4. Executing OPT_CLEAN pass (remove unused cells and wires). 178s Finding unused cells or wires in module \top.. 178s Removed 27 unused cells and 34 unused wires. 178s 178s 178s 2.33.5. Finished fast OPT passes. 178s 178s 2.34. Executing ICE40_OPT pass (performing simple optimizations). 178s 178s 2.34.1. Running ICE40 specific optimizations. 178s Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$460.slice[0].carry: CO=\counter [0] 178s 178s 2.34.2. Executing OPT_EXPR pass (perform const folding). 178s Optimizing module top. 178s 178s 2.34.3. Executing OPT_MERGE pass (detect identical cells). 178s Finding identical cells in module `\top'. 178s Removed a total of 0 cells. 178s 178s 2.34.4. Executing OPT_DFF pass (perform DFF optimizations). 178s 178s 2.34.5. Executing OPT_CLEAN pass (remove unused cells and wires). 178s Finding unused cells or wires in module \top.. 178s 178s 2.34.6. Rerunning OPT passes. (Removed registers in this run.) 178s 178s 2.34.7. Running ICE40 specific optimizations. 178s 178s 2.34.8. Executing OPT_EXPR pass (perform const folding). 178s Optimizing module top. 178s 178s 2.34.9. Executing OPT_MERGE pass (detect identical cells). 178s Finding identical cells in module `\top'. 178s Removed a total of 0 cells. 178s 178s 2.34.10. Executing OPT_DFF pass (perform DFF optimizations). 178s 178s 2.34.11. Executing OPT_CLEAN pass (remove unused cells and wires). 178s Finding unused cells or wires in module \top.. 178s 178s 2.34.12. Finished OPT passes. (There is nothing left to do.) 178s 178s 2.35. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 178s 178s 2.36. Executing TECHMAP pass (map to technology primitives). 178s 178s 2.36.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 178s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 178s Generating RTLIL representation for module `\$_DFF_N_'. 178s Generating RTLIL representation for module `\$_DFF_P_'. 178s Generating RTLIL representation for module `\$_DFFE_NP_'. 178s Generating RTLIL representation for module `\$_DFFE_PP_'. 178s Generating RTLIL representation for module `\$_DFF_NP0_'. 178s Generating RTLIL representation for module `\$_DFF_NP1_'. 178s Generating RTLIL representation for module `\$_DFF_PP0_'. 178s Generating RTLIL representation for module `\$_DFF_PP1_'. 178s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 178s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 178s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 178s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 178s Generating RTLIL representation for module `\$_SDFF_NP0_'. 178s Generating RTLIL representation for module `\$_SDFF_NP1_'. 178s Generating RTLIL representation for module `\$_SDFF_PP0_'. 178s Generating RTLIL representation for module `\$_SDFF_PP1_'. 178s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 178s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 178s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 178s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 178s Successfully finished Verilog frontend. 178s 178s 2.36.2. Continuing TECHMAP pass. 178s Using template \$_DFF_P_ for cells of type $_DFF_P_. 178s No more expansions possible. 178s 178s 178s 2.37. Executing OPT_EXPR pass (perform const folding). 178s Optimizing module top. 178s 178s 2.38. Executing SIMPLEMAP pass (map simple cells to gate primitives). 178s Mapping top.$auto$alumacc.cc:485:replace_alu$460.slice[0].carry ($lut). 178s 178s 2.39. Executing ICE40_OPT pass (performing simple optimizations). 178s 178s 2.39.1. Running ICE40 specific optimizations. 178s 178s 2.39.2. Executing OPT_EXPR pass (perform const folding). 178s Optimizing module top. 178s 178s 178s 2.39.3. Executing OPT_MERGE pass (detect identical cells). 178s Finding identical cells in module `\top'. 178s Removed a total of 0 cells. 178s 178s 2.39.4. Executing OPT_DFF pass (perform DFF optimizations). 178s 178s 2.39.5. Executing OPT_CLEAN pass (remove unused cells and wires). 178s Finding unused cells or wires in module \top.. 178s Removed 0 unused cells and 112 unused wires. 178s 178s 178s 2.39.6. Rerunning OPT passes. (Removed registers in this run.) 178s 178s 2.39.7. Running ICE40 specific optimizations. 178s 178s 2.39.8. Executing OPT_EXPR pass (perform const folding). 178s Optimizing module top. 178s 178s 2.39.9. Executing OPT_MERGE pass (detect identical cells). 178s Finding identical cells in module `\top'. 178s Removed a total of 0 cells. 178s 178s 2.39.10. Executing OPT_DFF pass (perform DFF optimizations). 178s 178s 2.39.11. Executing OPT_CLEAN pass (remove unused cells and wires). 178s Finding unused cells or wires in module \top.. 178s 178s 2.39.12. Finished OPT passes. (There is nothing left to do.) 178s 178s 2.40. Executing TECHMAP pass (map to technology primitives). 178s 178s 2.40.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v 178s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation. 178s Generating RTLIL representation for module `\$_DLATCH_N_'. 178s Generating RTLIL representation for module `\$_DLATCH_P_'. 178s Successfully finished Verilog frontend. 178s 178s 2.40.2. Continuing TECHMAP pass. 178s No more expansions possible. 178s 178s 178s 2.41. Executing ABC pass (technology mapping using ABC). 178s 178s 2.41.1. Extracting gate netlist of module `\top' to `/input.blif'.. 178s Extracted 27 gates and 54 wires to a netlist network with 27 inputs and 4 outputs. 178s 178s 2.41.1.1. Executing ABC. 178s Running ABC command: "berkeley-abc" -s -f /abc.script 2>&1 178s ABC: ABC command line: "source /abc.script". 178s ABC: 178s ABC: + read_blif /input.blif 178s ABC: + read_lut /lutdefs.txt 178s ABC: + strash 178s ABC: + &get -n 178s ABC: + &fraig -x 178s ABC: + &put 178s ABC: + scorr 178s ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). 178s ABC: + dc2 178s ABC: + dretime 178s ABC: + strash 178s ABC: + dch -f 178s ABC: + if 178s ABC: + mfs2 178s ABC: + lutpack -S 1 178s ABC: + dress /input.blif 178s ABC: Total number of equiv classes = 5. 178s ABC: Participating nodes from both networks = 9. 178s ABC: Participating nodes from the first network = 4. ( 30.77 % of nodes) 178s ABC: Participating nodes from the second network = 5. ( 38.46 % of nodes) 178s ABC: Node pairs (any polarity) = 4. ( 30.77 % of names can be moved) 178s ABC: Node pairs (same polarity) = 4. ( 30.77 % of names can be moved) 178s ABC: Total runtime = 0.06 sec 178s ABC: + write_blif /output.blif 178s 178s 2.41.1.2. Re-integrating ABC results. 178s ABC RESULTS: $lut cells: 12 178s ABC RESULTS: internal signals: 23 178s ABC RESULTS: input signals: 27 178s ABC RESULTS: output signals: 4 178s Removing temp directory. 178s 178s 2.42. Executing ICE40_WRAPCARRY pass (wrap carries). 178s 178s 2.43. Executing TECHMAP pass (map to technology primitives). 178s 178s 2.43.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 178s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 178s Generating RTLIL representation for module `\$_DFF_N_'. 178s Generating RTLIL representation for module `\$_DFF_P_'. 178s Generating RTLIL representation for module `\$_DFFE_NP_'. 178s Generating RTLIL representation for module `\$_DFFE_PP_'. 178s Generating RTLIL representation for module `\$_DFF_NP0_'. 178s Generating RTLIL representation for module `\$_DFF_NP1_'. 178s Generating RTLIL representation for module `\$_DFF_PP0_'. 178s Generating RTLIL representation for module `\$_DFF_PP1_'. 178s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 178s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 178s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 178s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 178s Generating RTLIL representation for module `\$_SDFF_NP0_'. 178s Generating RTLIL representation for module `\$_SDFF_NP1_'. 178s Generating RTLIL representation for module `\$_SDFF_PP0_'. 178s Generating RTLIL representation for module `\$_SDFF_PP1_'. 178s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 178s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 178s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 178s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 178s Successfully finished Verilog frontend. 178s 178s 2.43.2. Continuing TECHMAP pass. 178s No more expansions possible. 178s 178s Removed 2 unused cells and 39 unused wires. 178s 178s 2.44. Executing OPT_LUT pass (optimize LUTs). 178s Discovering LUTs. 178s Number of LUTs: 37 178s 1-LUT 1 178s 2-LUT 4 178s 3-LUT 25 178s 4-LUT 7 178s with \SB_CARRY (#0) 23 178s with \SB_CARRY (#1) 23 178s 178s Eliminating LUTs. 178s Number of LUTs: 37 178s 1-LUT 1 178s 2-LUT 4 178s 3-LUT 25 178s 4-LUT 7 178s with \SB_CARRY (#0) 23 178s with \SB_CARRY (#1) 23 178s 178s Combining LUTs. 178s Number of LUTs: 37 178s 1-LUT 1 178s 2-LUT 4 178s 3-LUT 25 178s 4-LUT 7 178s with \SB_CARRY (#0) 23 178s with \SB_CARRY (#1) 23 178s 178s Eliminated 0 LUTs. 178s Combined 0 LUTs. 178s 178s 178s 2.45. Executing TECHMAP pass (map to technology primitives). 178s 178s 2.45.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v 178s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation. 178s Generating RTLIL representation for module `\$lut'. 178s Successfully finished Verilog frontend. 178s 178s 2.45.2. Continuing TECHMAP pass. 178s Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut. 178s Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut. 178s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut. 178s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. 178s Using template $paramod$415b9dd3a15783ae56c103f189fd8e182f997441\$lut for cells of type $lut. 178s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. 178s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. 178s Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut. 178s No more expansions possible. 178s 178s Removed 0 unused cells and 78 unused wires. 178s 178s 2.46. Executing AUTONAME pass. 178s Renamed 463 objects in module top (10 iterations). 178s 178s 178s 2.47. Executing HIERARCHY pass (managing design hierarchy). 178s 178s 2.47.1. Analyzing design hierarchy.. 178s Top module: \top 178s 178s 2.47.2. Analyzing design hierarchy.. 178s Top module: \top 178s Removed 0 unused modules. 178s 178s 2.48. Printing statistics. 178s 178s === top === 178s 178s Number of wires: 20 178s Number of wire bits: 99 178s Number of public wires: 20 178s Number of public wire bits: 99 178s Number of memories: 0 178s Number of memory bits: 0 178s Number of processes: 0 178s Number of cells: 88 178s SB_CARRY 23 178s SB_DFF 27 178s SB_LUT4 37 178s SB_WARMBOOT 1 178s 178s 2.49. Executing CHECK pass (checking for obvious problems). 178s Checking module top... 178s Found and reported 0 problems. 178s 178s 2.50. Executing JSON backend. 178s 178s End of script. Logfile hash: 5ef4382c4c, CPU: user 0.68s system 0.01s, MEM: 20.00 MB peak 178s Yosys 0.23 (git sha1 7ce5011c24b) 178s Time spent: 54% 13x read_verilog (0 sec), 19% 1x abc (0 sec), ... 178s nextpnr-ice40 --hx1k --package tq144 --asc app1.asc --pcf icestick.pcf --json app1.json 178s Warning: unmatched constraint 'RX' (on line 4) 178s Warning: unmatched constraint 'TX' (on line 5) 178s Info: constrained 'LED1' to bel 'X13/Y12/io1' 178s Info: constrained 'LED2' to bel 'X13/Y12/io0' 178s Info: constrained 'LED3' to bel 'X13/Y11/io1' 178s Info: constrained 'LED4' to bel 'X13/Y11/io0' 178s Info: constrained 'LED5' to bel 'X13/Y9/io1' 178s Info: constrained 'clk' to bel 'X0/Y8/io1' 178s 178s Info: Packing constants.. 178s Info: Packing IOs.. 178s Info: Packing LUT-FFs.. 178s Info: 10 LCs used as LUT4 only 178s Info: 27 LCs used as LUT4 and DFF 178s Info: Packing non-LUT FFs.. 178s Info: 0 LCs used as DFF only 178s Info: Packing carries.. 178s Info: 0 LCs used as CARRY only 178s Info: Packing indirect carry+LUT pairs... 178s Info: 0 LUTs merged into carry LCs 178s Info: Packing RAMs.. 178s Info: Placing PLLs.. 178s Info: Packing special functions.. 178s Info: Packing PLLs.. 178s Info: Promoting globals.. 178s Info: promoting clk$SB_IO_IN (fanout 27) 178s Info: Constraining chains... 178s Info: 1 LCs used to legalise carry chains. 178s Info: Checksum: 0xb506605d 178s 178s Info: Annotating ports with timing budgets for target frequency 12.00 MHz 178s Info: Checksum: 0x14b02b09 178s 178s Info: Device utilisation: 178s Info: ICESTORM_LC: 40/ 1280 3% 178s Info: ICESTORM_RAM: 0/ 16 0% 178s Info: SB_IO: 6/ 112 5% 178s Info: SB_GB: 1/ 8 12% 178s Info: ICESTORM_PLL: 0/ 1 0% 178s Info: SB_WARMBOOT: 1/ 1 100% 178s 178s Info: Placed 6 cells based on constraints. 178s Info: Creating initial analytic placement for 18 cells, random placement wirelen = 358. 178s Info: at initial placer iter 0, wirelen = 38 178s Info: at initial placer iter 1, wirelen = 14 178s Info: at initial placer iter 2, wirelen = 14 178s Info: at initial placer iter 3, wirelen = 14 178s Info: Running main analytical placer, max placement attempts per cell = 10000. 178s Info: at iteration #1, type ICESTORM_LC: wirelen solved = 16, spread = 61, legal = 87; time = 0.00s 178s Info: at iteration #1, type SB_GB: wirelen solved = 87, spread = 87, legal = 87; time = 0.00s 178s Info: at iteration #1, type SB_WARMBOOT: wirelen solved = 87, spread = 87, legal = 147; time = 0.00s 178s Info: at iteration #1, type ALL: wirelen solved = 39, spread = 112, legal = 170; time = 0.00s 178s Info: at iteration #2, type ICESTORM_LC: wirelen solved = 91, spread = 119, legal = 145; time = 0.00s 178s Info: at iteration #2, type SB_GB: wirelen solved = 145, spread = 145, legal = 145; time = 0.00s 178s Info: at iteration #2, type SB_WARMBOOT: wirelen solved = 93, spread = 93, legal = 145; time = 0.00s 178s Info: at iteration #2, type ALL: wirelen solved = 19, spread = 60, legal = 121; time = 0.00s 178s Info: at iteration #3, type ICESTORM_LC: wirelen solved = 84, spread = 121, legal = 124; time = 0.00s 178s Info: at iteration #3, type SB_GB: wirelen solved = 124, spread = 124, legal = 124; time = 0.00s 178s Info: at iteration #3, type SB_WARMBOOT: wirelen solved = 68, spread = 68, legal = 124; time = 0.00s 178s Info: at iteration #3, type ALL: wirelen solved = 24, spread = 62, legal = 121; time = 0.00s 178s Info: at iteration #4, type ICESTORM_LC: wirelen solved = 84, spread = 127, legal = 132; time = 0.00s 178s Info: at iteration #4, type SB_GB: wirelen solved = 132, spread = 132, legal = 132; time = 0.00s 178s Info: at iteration #4, type SB_WARMBOOT: wirelen solved = 76, spread = 76, legal = 132; time = 0.00s 178s Info: at iteration #4, type ALL: wirelen solved = 21, spread = 61, legal = 121; time = 0.00s 178s Info: at iteration #5, type ICESTORM_LC: wirelen solved = 84, spread = 127, legal = 130; time = 0.00s 178s Info: at iteration #5, type SB_GB: wirelen solved = 130, spread = 130, legal = 130; time = 0.00s 178s Info: at iteration #5, type SB_WARMBOOT: wirelen solved = 74, spread = 74, legal = 130; time = 0.00s 178s Info: at iteration #5, type ALL: wirelen solved = 33, spread = 61, legal = 121; time = 0.00s 178s Info: at iteration #6, type ICESTORM_LC: wirelen solved = 86, spread = 127, legal = 130; time = 0.00s 178s Info: at iteration #6, type SB_GB: wirelen solved = 130, spread = 130, legal = 130; time = 0.00s 178s Info: at iteration #6, type SB_WARMBOOT: wirelen solved = 74, spread = 74, legal = 130; time = 0.00s 178s Info: at iteration #6, type ALL: wirelen solved = 30, spread = 61, legal = 121; time = 0.00s 178s Info: at iteration #7, type ICESTORM_LC: wirelen solved = 85, spread = 125, legal = 133; time = 0.00s 178s Info: at iteration #7, type SB_GB: wirelen solved = 133, spread = 133, legal = 133; time = 0.00s 178s Info: at iteration #7, type SB_WARMBOOT: wirelen solved = 77, spread = 77, legal = 133; time = 0.00s 178s Info: at iteration #7, type ALL: wirelen solved = 28, spread = 64, legal = 121; time = 0.00s 178s Info: HeAP Placer Time: 0.02s 178s Info: of which solving equations: 0.01s 178s Info: of which spreading cells: 0.00s 178s Info: of which strict legalisation: 0.00s 178s 178s Info: Running simulated annealing placer for refinement. 178s Info: at iteration #1: temp = 0.000000, timing cost = 16, wirelen = 121 178s Info: at iteration #5: temp = 0.000000, timing cost = 17, wirelen = 103 178s Info: at iteration #8: temp = 0.000000, timing cost = 17, wirelen = 103 178s Info: SA placement time 0.01s 178s 178s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 192.23 MHz (PASS at 12.00 MHz) 178s 178s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> : 3.94 ns 178s 178s Info: Slack histogram: 178s Info: legend: * represents 1 endpoint(s) 178s Info: + represents [1,1) endpoint(s) 178s Info: [ 78131, 78318) |** 178s Info: [ 78318, 78505) |*** 178s Info: [ 78505, 78692) |* 178s Info: [ 78692, 78879) |*** 178s Info: [ 78879, 79066) |* 178s Info: [ 79066, 79253) | 178s Info: [ 79253, 79440) |** 178s Info: [ 79440, 79627) |** 178s Info: [ 79627, 79814) |**** 178s Info: [ 79814, 80001) |** 178s Info: [ 80001, 80188) |** 178s Info: [ 80188, 80375) | 178s Info: [ 80375, 80562) | 178s Info: [ 80562, 80749) |** 178s Info: [ 80749, 80936) |* 178s Info: [ 80936, 81123) |** 178s Info: [ 81123, 81310) |* 178s Info: [ 81310, 81497) | 178s Info: [ 81497, 81684) |* 178s Info: [ 81684, 81871) |**************************** 178s Info: Checksum: 0xcc9786c2 178s 178s Info: Routing.. 178s Info: Setting up routing queue. 178s Info: Routing 127 arcs. 178s Info: | (re-)routed arcs | delta | remaining| time spent | 178s Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| 178s Info: 127 | 0 107 | 0 107 | 0| 0.01 0.01| 178s Info: Routing complete. 178s Info: Router1 time 0.01s 178s Info: Checksum: 0xb20a0be1 178s 178s Info: Critical path report for clock 'clk$SB_IO_IN_$glb_clk' (posedge -> posedge): 178s Info: curr total 178s Info: 0.5 0.5 Source counter_SB_LUT4_I2_3_LC.O 178s Info: 0.6 1.1 Net counter[6] budget 20.292999 ns (12,10) -> (11,11) 178s Info: Sink state_SB_LUT4_I3_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_LC.I0 178s Info: Defined in: 178s Info: app1.v:7.22-7.29 178s Info: 0.4 1.6 Source state_SB_LUT4_I3_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_LC.O 178s Info: 0.6 2.2 Net state_SB_LUT4_I3_I0_SB_LUT4_O_1_I2[0] budget 20.292999 ns (11,11) -> (11,11) 178s Info: Sink state_SB_LUT4_I3_I0_SB_LUT4_O_1_LC.I2 178s Info: Defined in: 178s Info: /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 178s Info: 0.4 2.5 Source state_SB_LUT4_I3_I0_SB_LUT4_O_1_LC.O 178s Info: 0.6 3.1 Net state_SB_LUT4_I3_I0[1] budget 20.292000 ns (11,11) -> (11,10) 178s Info: Sink counter2_SB_LUT4_I2_3_I1_SB_LUT4_O_LC.I2 178s Info: Defined in: 178s Info: /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 178s Info: 0.4 3.5 Source counter2_SB_LUT4_I2_3_I1_SB_LUT4_O_LC.O 178s Info: 0.6 4.1 Net counter2_SB_LUT4_I2_3_I1 budget 20.292000 ns (11,10) -> (11,9) 178s Info: Sink counter2_SB_LUT4_I2_3_LC.I1 178s Info: Defined in: 178s Info: app1.v:13.15-13.34 178s Info: /usr/bin/../share/yosys/ice40/arith_map.v:29.22-29.23 178s Info: 0.3 4.4 Source counter2_SB_LUT4_I2_3_LC.COUT 178s Info: 0.0 4.4 Net counter2_SB_CARRY_I1_CO[1] budget 0.000000 ns (11,9) -> (11,9) 178s Info: Sink counter2_SB_LUT4_I2_2_LC.CIN 178s Info: Defined in: 178s Info: app1.v:13.15-13.34 178s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 178s Info: 0.1 4.5 Source counter2_SB_LUT4_I2_2_LC.COUT 178s Info: 0.0 4.5 Net counter2_SB_CARRY_I1_CO[2] budget 0.000000 ns (11,9) -> (11,9) 178s Info: Sink counter2_SB_LUT4_I2_1_LC.CIN 178s Info: Defined in: 178s Info: app1.v:13.15-13.34 178s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 178s Info: 0.1 4.6 Source counter2_SB_LUT4_I2_1_LC.COUT 178s Info: 0.3 4.9 Net counter2_SB_CARRY_I1_CO[3] budget 0.260000 ns (11,9) -> (11,9) 178s Info: Sink counter2_SB_LUT4_I2_LC.I3 178s Info: Defined in: 178s Info: app1.v:13.15-13.34 178s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 178s Info: 0.3 5.2 Setup counter2_SB_LUT4_I2_LC.I3 178s Info: 2.6 ns logic, 2.6 ns routing 178s 178s Info: Critical path report for cross-domain path 'posedge clk$SB_IO_IN_$glb_clk' -> '': 178s Info: curr total 178s Info: 0.5 0.5 Source counter2_SB_LUT4_I2_3_LC.O 178s Info: 0.6 1.1 Net counter2[0] budget 41.173000 ns (11,9) -> (11,9) 178s Info: Sink WB_BOOT_SB_LUT4_O_LC.I0 178s Info: Defined in: 178s Info: app1.v:8.12-8.20 178s Info: 0.4 1.6 Source WB_BOOT_SB_LUT4_O_LC.O 178s Info: 1.4 3.0 Net WB_BOOT budget 41.172001 ns (11,9) -> (0,0) 178s Info: Sink WB.BOOT 178s Info: Defined in: 178s Info: app1.v:24.9-24.18 178s Info: 1.0 ns logic, 2.0 ns routing 178s 178s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 192.23 MHz (PASS at 12.00 MHz) 178s 178s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> : 3.02 ns 178s 178s Info: Slack histogram: 178s Info: legend: * represents 1 endpoint(s) 178s Info: + represents [1,1) endpoint(s) 178s Info: [ 78131, 78318) |** 178s Info: [ 78318, 78505) |** 178s Info: [ 78505, 78692) |** 178s Info: [ 78692, 78879) |** 178s Info: [ 78879, 79066) |** 178s Info: [ 79066, 79253) | 178s Info: [ 79253, 79440) |* 178s Info: [ 79440, 79627) |* 178s icetime -d hx1k -c 25 app1.asc 178s // Reading input .asc file.. 178s // Reading 1k chipdb file.. 178s Info: [ 79627, 79814) |***** 178s Info: [ 79814, 80001) |* 178s Info: [ 80001, 80188) |*** 178s Info: [ 80188, 80375) |* 178s Info: [ 80375, 80562) | 178s Info: [ 80562, 80749) |** 178s Info: [ 80749, 80936) |* 178s Info: [ 80936, 81123) |** 178s Info: [ 81123, 81310) |* 178s Info: [ 81310, 81497) | 178s Info: [ 81497, 81684) |* 178s Info: [ 81684, 81871) |**************************** 178s 2 warnings, 0 errors 178s 178s Info: Program finished normally. 178s // Creating timing netlist.. 178s // Timing estimate: 5.28 ns (189.29 MHz) 178s // Checking 40.00 ns (25.00 MHz) clock constraint: PASSED. 178s icepack app1.asc app1.bin 178s yosys -p "synth_ice40 -top top -json app2.json" app2.v 178s 178s /----------------------------------------------------------------------------\ 178s | | 178s | yosys -- Yosys Open SYnthesis Suite | 178s | | 178s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 178s | | 178s | Permission to use, copy, modify, and/or distribute this software for any | 178s | purpose with or without fee is hereby granted, provided that the above | 178s | copyright notice and this permission notice appear in all copies. | 178s | | 178s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 178s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 178s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 178s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 178s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 178s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 178s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 178s | | 178s \----------------------------------------------------------------------------/ 178s 178s Yosys 0.23 (git sha1 7ce5011c24b) 178s 178s 178s -- Parsing `app2.v' using frontend ` -vlog2k' -- 178s 178s 1. Executing Verilog-2005 frontend: app2.v 178s Parsing Verilog input from `app2.v' to AST representation. 178s Storing AST representation for module `$abstract\top'. 178s Successfully finished Verilog frontend. 178s 178s -- Running command `synth_ice40 -top top -json app2.json' -- 178s 178s 2. Executing SYNTH_ICE40 pass. 178s 178s 2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v 178s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation. 178s Generating RTLIL representation for module `\SB_IO'. 178s Generating RTLIL representation for module `\SB_GB_IO'. 178s Generating RTLIL representation for module `\SB_GB'. 178s Generating RTLIL representation for module `\SB_LUT4'. 178s Generating RTLIL representation for module `\SB_CARRY'. 178s Generating RTLIL representation for module `\SB_DFF'. 178s Generating RTLIL representation for module `\SB_DFFE'. 178s Generating RTLIL representation for module `\SB_DFFSR'. 178s Generating RTLIL representation for module `\SB_DFFR'. 178s Generating RTLIL representation for module `\SB_DFFSS'. 178s Generating RTLIL representation for module `\SB_DFFS'. 178s Generating RTLIL representation for module `\SB_DFFESR'. 178s Generating RTLIL representation for module `\SB_DFFER'. 178s Generating RTLIL representation for module `\SB_DFFESS'. 178s Generating RTLIL representation for module `\SB_DFFES'. 178s Generating RTLIL representation for module `\SB_DFFN'. 178s Generating RTLIL representation for module `\SB_DFFNE'. 178s Generating RTLIL representation for module `\SB_DFFNSR'. 178s Generating RTLIL representation for module `\SB_DFFNR'. 178s Generating RTLIL representation for module `\SB_DFFNSS'. 178s Generating RTLIL representation for module `\SB_DFFNS'. 178s Generating RTLIL representation for module `\SB_DFFNESR'. 178s Generating RTLIL representation for module `\SB_DFFNER'. 178s Generating RTLIL representation for module `\SB_DFFNESS'. 178s Generating RTLIL representation for module `\SB_DFFNES'. 178s Generating RTLIL representation for module `\SB_RAM40_4K'. 178s Generating RTLIL representation for module `\SB_RAM40_4KNR'. 178s Generating RTLIL representation for module `\SB_RAM40_4KNW'. 178s Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. 178s Generating RTLIL representation for module `\ICESTORM_LC'. 178s Generating RTLIL representation for module `\SB_PLL40_CORE'. 178s Generating RTLIL representation for module `\SB_PLL40_PAD'. 178s Generating RTLIL representation for module `\SB_PLL40_2_PAD'. 178s Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. 178s Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. 178s Generating RTLIL representation for module `\SB_WARMBOOT'. 178s Generating RTLIL representation for module `\SB_SPRAM256KA'. 178s Generating RTLIL representation for module `\SB_HFOSC'. 178s Generating RTLIL representation for module `\SB_LFOSC'. 178s Generating RTLIL representation for module `\SB_RGBA_DRV'. 178s Generating RTLIL representation for module `\SB_LED_DRV_CUR'. 178s Generating RTLIL representation for module `\SB_RGB_DRV'. 178s Generating RTLIL representation for module `\SB_I2C'. 178s Generating RTLIL representation for module `\SB_SPI'. 178s Generating RTLIL representation for module `\SB_LEDDA_IP'. 178s Generating RTLIL representation for module `\SB_FILTER_50NS'. 178s Generating RTLIL representation for module `\SB_IO_I3C'. 178s Generating RTLIL representation for module `\SB_IO_OD'. 178s Generating RTLIL representation for module `\SB_MAC16'. 178s Generating RTLIL representation for module `\ICESTORM_RAM'. 178s Successfully finished Verilog frontend. 178s 178s 2.2. Executing HIERARCHY pass (managing design hierarchy). 178s 178s 2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\top'. 178s Generating RTLIL representation for module `\top'. 178s 178s 2.3.1. Analyzing design hierarchy.. 178s Top module: \top 178s 178s 2.3.2. Analyzing design hierarchy.. 178s Top module: \top 178s Removing unused module `$abstract\top'. 178s Removed 1 unused modules. 178s 178s 2.4. Executing PROC pass (convert processes to netlists). 178s 178s 2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 178s Cleaned up 0 empty switches. 178s 178s 2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 178s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241 in module SB_DFFNES. 178s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234 in module SB_DFFNESS. 178s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230 in module SB_DFFNER. 178s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223 in module SB_DFFNESR. 178s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220 in module SB_DFFNS. 178s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217 in module SB_DFFNSS. 178s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214 in module SB_DFFNR. 178s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211 in module SB_DFFNSR. 178s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203 in module SB_DFFES. 178s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196 in module SB_DFFESS. 178s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192 in module SB_DFFER. 178s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185 in module SB_DFFESR. 178s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182 in module SB_DFFS. 178s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179 in module SB_DFFSS. 178s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176 in module SB_DFFR. 178s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173 in module SB_DFFSR. 178s Removed a total of 0 dead cases. 178s 178s 2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 178s Removed 8 redundant assignments. 178s Promoted 28 assignments to connections. 178s 178s 2.4.4. Executing PROC_INIT pass (extract init attributes). 178s Found init rule in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 178s Set init value: \Q = 1'0 178s Found init rule in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 178s Set init value: \Q = 1'0 178s Found init rule in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 178s Set init value: \Q = 1'0 178s Found init rule in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 178s Set init value: \Q = 1'0 178s Found init rule in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 178s Set init value: \Q = 1'0 178s Found init rule in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 178s Set init value: \Q = 1'0 178s Found init rule in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 178s Set init value: \Q = 1'0 178s Found init rule in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 178s Set init value: \Q = 1'0 178s Found init rule in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 178s Set init value: \Q = 1'0 178s Found init rule in `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 178s Set init value: \Q = 1'0 178s Found init rule in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 178s Set init value: \Q = 1'0 178s Found init rule in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 178s Set init value: \Q = 1'0 178s Found init rule in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 178s Set init value: \Q = 1'0 178s Found init rule in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 178s Set init value: \Q = 1'0 178s Found init rule in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 178s Set init value: \Q = 1'0 178s Found init rule in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 178s Set init value: \Q = 1'0 178s Found init rule in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 178s Set init value: \Q = 1'0 178s Found init rule in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 178s Set init value: \Q = 1'0 178s Found init rule in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 178s Set init value: \Q = 1'0 178s Found init rule in `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 178s Set init value: \Q = 1'0 178s Found init rule in `\top.$proc$app2.v:9$390'. 178s Set init value: \state = 1'0 178s Found init rule in `\top.$proc$app2.v:8$389'. 178s Set init value: \counter2 = 4'0000 178s Found init rule in `\top.$proc$app2.v:7$388'. 178s Set init value: \counter = 22'0000000000000000000000 178s 178s 2.4.5. Executing PROC_ARST pass (detect async resets in processes). 178s Found async reset \S in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 178s Found async reset \R in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 178s Found async reset \S in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 178s Found async reset \R in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 178s Found async reset \S in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 178s Found async reset \R in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 178s Found async reset \S in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 178s Found async reset \R in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 178s 178s 2.4.6. Executing PROC_ROM pass (convert switches to ROMs). 178s Converted 0 switches. 178s 178s 178s 2.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 178s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 178s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 178s 1/1: $0\Q[0:0] 178s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 178s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 178s 1/1: $0\Q[0:0] 178s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 178s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 178s 1/1: $0\Q[0:0] 178s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 178s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 178s 1/1: $0\Q[0:0] 178s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 178s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 178s 1/1: $0\Q[0:0] 178s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 178s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 178s 1/1: $0\Q[0:0] 178s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 178s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 178s 1/1: $0\Q[0:0] 178s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 178s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 178s 1/1: $0\Q[0:0] 178s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 178s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 178s 1/1: $0\Q[0:0] 178s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 178s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 178s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 178s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 178s 1/1: $0\Q[0:0] 178s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 178s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 178s 1/1: $0\Q[0:0] 178s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 178s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 178s 1/1: $0\Q[0:0] 178s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 178s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 178s 1/1: $0\Q[0:0] 178s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 178s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 178s 1/1: $0\Q[0:0] 178s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 178s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 178s 1/1: $0\Q[0:0] 178s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 178s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 178s 1/1: $0\Q[0:0] 178s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 178s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 178s 1/1: $0\Q[0:0] 178s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 178s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 178s 1/1: $0\Q[0:0] 178s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 178s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 178s Creating decoders for process `\top.$proc$app2.v:9$390'. 178s Creating decoders for process `\top.$proc$app2.v:8$389'. 178s Creating decoders for process `\top.$proc$app2.v:7$388'. 178s Creating decoders for process `\top.$proc$app2.v:11$381'. 178s 178s 2.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). 178s 178s 2.4.9. Executing PROC_DFF pass (convert process syncs to FFs). 178s Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 178s created $adff cell `$procdff$435' with negative edge clock and positive level reset. 178s Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 178s created $dff cell `$procdff$436' with negative edge clock. 178s Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 178s created $adff cell `$procdff$437' with negative edge clock and positive level reset. 178s Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 178s created $dff cell `$procdff$438' with negative edge clock. 178s Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 178s created $adff cell `$procdff$439' with negative edge clock and positive level reset. 178s Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 178s created $dff cell `$procdff$440' with negative edge clock. 178s Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 178s created $adff cell `$procdff$441' with negative edge clock and positive level reset. 178s Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 178s created $dff cell `$procdff$442' with negative edge clock. 178s Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 178s created $dff cell `$procdff$443' with negative edge clock. 178s Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 178s created $dff cell `$procdff$444' with negative edge clock. 178s Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 178s created $adff cell `$procdff$445' with positive edge clock and positive level reset. 178s Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 178s created $dff cell `$procdff$446' with positive edge clock. 178s Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 178s created $adff cell `$procdff$447' with positive edge clock and positive level reset. 178s Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 178s created $dff cell `$procdff$448' with positive edge clock. 178s Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 178s created $adff cell `$procdff$449' with positive edge clock and positive level reset. 178s Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 178s created $dff cell `$procdff$450' with positive edge clock. 178s Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 178s created $adff cell `$procdff$451' with positive edge clock and positive level reset. 178s Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 178s created $dff cell `$procdff$452' with positive edge clock. 178s Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 178s created $dff cell `$procdff$453' with positive edge clock. 178s Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 178s created $dff cell `$procdff$454' with positive edge clock. 178s Creating register for signal `\top.\counter' using process `\top.$proc$app2.v:11$381'. 178s created $dff cell `$procdff$455' with positive edge clock. 178s Creating register for signal `\top.\counter2' using process `\top.$proc$app2.v:11$381'. 178s created $dff cell `$procdff$456' with positive edge clock. 178s Creating register for signal `\top.\state' using process `\top.$proc$app2.v:11$381'. 178s created $dff cell `$procdff$457' with positive edge clock. 178s 178s 2.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 178s 178s 2.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 178s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 178s Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 178s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 178s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 178s Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 178s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 178s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 178s Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 178s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 178s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 178s Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 178s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 178s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 178s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 178s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 178s Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 178s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 178s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 178s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 178s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 178s Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 178s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 178s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 178s Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 178s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 178s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 178s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 178s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 178s Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 178s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 178s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 178s Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 178s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 178s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 178s Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 178s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 178s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 178s Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 178s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 178s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 178s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 178s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 178s Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 178s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 178s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 178s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 178s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 178s Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 178s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 178s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 178s Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 178s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 178s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 178s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 178s Removing empty process `top.$proc$app2.v:9$390'. 178s Removing empty process `top.$proc$app2.v:8$389'. 178s Removing empty process `top.$proc$app2.v:7$388'. 178s Removing empty process `top.$proc$app2.v:11$381'. 178s Cleaned up 18 empty switches. 178s 178s 2.4.12. Executing OPT_EXPR pass (perform const folding). 178s Optimizing module top. 178s 178s 2.5. Executing FLATTEN pass (flatten design). 178s 178s 2.6. Executing TRIBUF pass. 178s 178s 2.7. Executing DEMINOUT pass (demote inout ports to input or output). 178s 178s 2.8. Executing OPT_EXPR pass (perform const folding). 178s Optimizing module top. 178s 178s 2.9. Executing OPT_CLEAN pass (remove unused cells and wires). 178s Finding unused cells or wires in module \top.. 178s Removed 0 unused cells and 5 unused wires. 178s 178s 178s 2.10. Executing CHECK pass (checking for obvious problems). 178s Checking module top... 178s Found and reported 0 problems. 178s 178s 2.11. Executing OPT pass (performing simple optimizations). 178s 178s 2.11.1. Executing OPT_EXPR pass (perform const folding). 179s Optimizing module top. 179s 179s 2.11.2. Executing OPT_MERGE pass (detect identical cells). 179s Finding identical cells in module `\top'. 179s Removed a total of 0 cells. 179s 179s 2.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 179s Running muxtree optimizer on module \top.. 179s Creating internal representation of mux trees. 179s No muxes found in this module. 179s Removed 0 multiplexer ports. 179s 179s 2.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 179s Optimizing cells in module \top. 179s Performed a total of 0 changes. 179s 179s 2.11.5. Executing OPT_MERGE pass (detect identical cells). 179s Finding identical cells in module `\top'. 179s Removed a total of 0 cells. 179s 179s 2.11.6. Executing OPT_DFF pass (perform DFF optimizations). 179s 179s 2.11.7. Executing OPT_CLEAN pass (remove unused cells and wires). 179s Finding unused cells or wires in module \top.. 179s 179s 2.11.8. Executing OPT_EXPR pass (perform const folding). 179s Optimizing module top. 179s 179s 2.11.9. Finished OPT passes. (There is nothing left to do.) 179s 179s 2.12. Executing FSM pass (extract and optimize FSM). 179s 179s 2.12.1. Executing FSM_DETECT pass (finding FSMs in design). 179s 179s 2.12.2. Executing FSM_EXTRACT pass (extracting FSM from design). 179s 179s 2.12.3. Executing FSM_OPT pass (simple optimizations of FSMs). 179s 179s 2.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). 179s Finding unused cells or wires in module \top.. 179s 179s 2.12.5. Executing FSM_OPT pass (simple optimizations of FSMs). 179s 179s 2.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 179s 179s 2.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 179s 179s 2.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 179s 179s 2.13. Executing OPT pass (performing simple optimizations). 179s 179s 2.13.1. Executing OPT_EXPR pass (perform const folding). 179s Optimizing module top. 179s 179s 2.13.2. Executing OPT_MERGE pass (detect identical cells). 179s Finding identical cells in module `\top'. 179s Removed a total of 0 cells. 179s 179s 2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 179s Running muxtree optimizer on module \top.. 179s Creating internal representation of mux trees. 179s No muxes found in this module. 179s Removed 0 multiplexer ports. 179s 179s 2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 179s Optimizing cells in module \top. 179s Performed a total of 0 changes. 179s 179s 2.13.5. Executing OPT_MERGE pass (detect identical cells). 179s Finding identical cells in module `\top'. 179s Removed a total of 0 cells. 179s 179s 2.13.6. Executing OPT_DFF pass (perform DFF optimizations). 179s 179s 2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). 179s Finding unused cells or wires in module \top.. 179s 179s 2.13.8. Executing OPT_EXPR pass (perform const folding). 179s Optimizing module top. 179s 179s 2.13.9. Finished OPT passes. (There is nothing left to do.) 179s 179s 2.14. Executing WREDUCE pass (reducing word size of cells). 179s Removed top 31 bits (of 32) from port B of cell top.$add$app2.v:12$382 ($add). 179s Removed top 10 bits (of 32) from port Y of cell top.$add$app2.v:12$382 ($add). 179s Removed top 3 bits (of 4) from port B of cell top.$add$app2.v:13$384 ($add). 179s Removed top 3 bits (of 4) from wire top.$logic_not$app2.v:13$383_Y. 179s 179s 2.15. Executing PEEPOPT pass (run peephole optimizers). 179s 179s 2.16. Executing OPT_CLEAN pass (remove unused cells and wires). 179s Finding unused cells or wires in module \top.. 179s Removed 0 unused cells and 2 unused wires. 179s 179s 179s 2.17. Executing SHARE pass (SAT-based resource sharing). 179s 179s 2.18. Executing TECHMAP pass (map to technology primitives). 179s 179s 2.18.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v 179s Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation. 179s Generating RTLIL representation for module `\_90_lut_cmp_'. 179s Successfully finished Verilog frontend. 179s 179s 2.18.2. Continuing TECHMAP pass. 179s No more expansions possible. 179s 179s 179s 2.19. Executing OPT_EXPR pass (perform const folding). 179s Optimizing module top. 179s 179s 2.20. Executing OPT_CLEAN pass (remove unused cells and wires). 179s Finding unused cells or wires in module \top.. 179s 179s 2.21. Executing ALUMACC pass (create $alu and $macc cells). 179s Extracting $alu and $macc cells in module top: 179s creating $macc model for $add$app2.v:12$382 ($add). 179s creating $macc model for $add$app2.v:13$384 ($add). 179s creating $alu model for $macc $add$app2.v:13$384. 179s creating $alu model for $macc $add$app2.v:12$382. 179s creating $alu cell for $add$app2.v:12$382: $auto$alumacc.cc:485:replace_alu$460 179s creating $alu cell for $add$app2.v:13$384: $auto$alumacc.cc:485:replace_alu$463 179s created 2 $alu and 0 $macc cells. 179s 179s 2.22. Executing OPT pass (performing simple optimizations). 179s 179s 2.22.1. Executing OPT_EXPR pass (perform const folding). 179s Optimizing module top. 179s 179s 2.22.2. Executing OPT_MERGE pass (detect identical cells). 179s Finding identical cells in module `\top'. 179s 179s Removed a total of 1 cells. 179s 179s 2.22.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 179s Running muxtree optimizer on module \top.. 179s Creating internal representation of mux trees. 179s No muxes found in this module. 179s Removed 0 multiplexer ports. 179s 179s 2.22.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 179s Optimizing cells in module \top. 179s Performed a total of 0 changes. 179s 179s 2.22.5. Executing OPT_MERGE pass (detect identical cells). 179s Finding identical cells in module `\top'. 179s Removed a total of 0 cells. 179s 179s 2.22.6. Executing OPT_DFF pass (perform DFF optimizations). 179s 179s 2.22.7. Executing OPT_CLEAN pass (remove unused cells and wires). 179s Finding unused cells or wires in module \top.. 179s Removed 0 unused cells and 1 unused wires. 179s 179s 179s 2.22.8. Executing OPT_EXPR pass (perform const folding). 179s Optimizing module top. 179s 179s 2.22.9. Rerunning OPT passes. (Maybe there is more to do..) 179s 179s 2.22.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 179s Running muxtree optimizer on module \top.. 179s Creating internal representation of mux trees. 179s No muxes found in this module. 179s Removed 0 multiplexer ports. 179s 179s 2.22.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 179s Optimizing cells in module \top. 179s Performed a total of 0 changes. 179s 179s 2.22.12. Executing OPT_MERGE pass (detect identical cells). 179s Finding identical cells in module `\top'. 179s Removed a total of 0 cells. 179s 179s 2.22.13. Executing OPT_DFF pass (perform DFF optimizations). 179s 179s 2.22.14. Executing OPT_CLEAN pass (remove unused cells and wires). 179s Finding unused cells or wires in module \top.. 179s 179s 2.22.15. Executing OPT_EXPR pass (perform const folding). 179s Optimizing module top. 179s 179s 2.22.16. Finished OPT passes. (There is nothing left to do.) 179s 179s 2.23. Executing MEMORY pass. 179s 179s 2.23.1. Executing OPT_MEM pass (optimize memories). 179s Performed a total of 0 transformations. 179s 179s 2.23.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). 179s Performed a total of 0 transformations. 179s 179s 2.23.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 179s 179s 2.23.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 179s 179s 2.23.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 179s 179s 2.23.6. Executing OPT_CLEAN pass (remove unused cells and wires). 179s Finding unused cells or wires in module \top.. 179s 179s 2.23.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 179s 179s 2.23.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). 179s Performed a total of 0 transformations. 179s 179s 2.23.9. Executing OPT_CLEAN pass (remove unused cells and wires). 179s Finding unused cells or wires in module \top.. 179s 179s 2.23.10. Executing MEMORY_COLLECT pass (generating $mem cells). 179s 179s 2.24. Executing OPT_CLEAN pass (remove unused cells and wires). 179s Finding unused cells or wires in module \top.. 179s 179s 2.25. Executing MEMORY_LIBMAP pass (mapping memories to cells). 179s 179s 2.26. Executing TECHMAP pass (map to technology primitives). 179s 179s 2.26.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v 179s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation. 179s Generating RTLIL representation for module `\$__ICE40_RAM4K_'. 179s Successfully finished Verilog frontend. 179s 179s 2.26.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/spram_map.v 179s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/spram_map.v' to AST representation. 179s Generating RTLIL representation for module `\$__ICE40_SPRAM_'. 179s Successfully finished Verilog frontend. 179s 179s 2.26.3. Continuing TECHMAP pass. 179s No more expansions possible. 179s 179s 179s 2.27. Executing ICE40_BRAMINIT pass. 179s 179s 2.28. Executing OPT pass (performing simple optimizations). 179s 179s 2.28.1. Executing OPT_EXPR pass (perform const folding). 179s Optimizing module top. 179s 179s 2.28.2. Executing OPT_MERGE pass (detect identical cells). 179s Finding identical cells in module `\top'. 179s Removed a total of 0 cells. 179s 179s 2.28.3. Executing OPT_DFF pass (perform DFF optimizations). 179s 179s 2.28.4. Executing OPT_CLEAN pass (remove unused cells and wires). 179s Finding unused cells or wires in module \top.. 179s 179s 2.28.5. Finished fast OPT passes. 179s 179s 2.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 179s 179s 2.30. Executing OPT pass (performing simple optimizations). 179s 179s 2.30.1. Executing OPT_EXPR pass (perform const folding). 179s Optimizing module top. 179s 179s 2.30.2. Executing OPT_MERGE pass (detect identical cells). 179s Finding identical cells in module `\top'. 179s Removed a total of 0 cells. 179s 179s 2.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 179s Running muxtree optimizer on module \top.. 179s Creating internal representation of mux trees. 179s No muxes found in this module. 179s Removed 0 multiplexer ports. 179s 179s 2.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 179s Optimizing cells in module \top. 179s Performed a total of 0 changes. 179s 179s 2.30.5. Executing OPT_MERGE pass (detect identical cells). 179s Finding identical cells in module `\top'. 179s Removed a total of 0 cells. 179s 179s 2.30.6. Executing OPT_DFF pass (perform DFF optimizations). 179s 179s 2.30.7. Executing OPT_CLEAN pass (remove unused cells and wires). 179s Finding unused cells or wires in module \top.. 179s 179s 2.30.8. Executing OPT_EXPR pass (perform const folding). 179s Optimizing module top. 179s 179s 2.30.9. Finished OPT passes. (There is nothing left to do.) 179s 179s 2.31. Executing ICE40_WRAPCARRY pass (wrap carries). 179s 179s 2.32. Executing TECHMAP pass (map to technology primitives). 179s 179s 2.32.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v 179s Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation. 179s Generating RTLIL representation for module `\_90_simplemap_bool_ops'. 179s Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. 179s Generating RTLIL representation for module `\_90_simplemap_logic_ops'. 179s Generating RTLIL representation for module `\_90_simplemap_compare_ops'. 179s Generating RTLIL representation for module `\_90_simplemap_various'. 179s Generating RTLIL representation for module `\_90_simplemap_registers'. 179s Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. 179s Generating RTLIL representation for module `\_90_shift_shiftx'. 179s Generating RTLIL representation for module `\_90_fa'. 179s Generating RTLIL representation for module `\_90_lcu'. 179s Generating RTLIL representation for module `\_90_alu'. 179s Generating RTLIL representation for module `\_90_macc'. 179s Generating RTLIL representation for module `\_90_alumacc'. 179s Generating RTLIL representation for module `\$__div_mod_u'. 179s Generating RTLIL representation for module `\$__div_mod_trunc'. 179s Generating RTLIL representation for module `\_90_div'. 179s Generating RTLIL representation for module `\_90_mod'. 179s Generating RTLIL representation for module `\$__div_mod_floor'. 179s Generating RTLIL representation for module `\_90_divfloor'. 179s Generating RTLIL representation for module `\_90_modfloor'. 179s Generating RTLIL representation for module `\_90_pow'. 179s Generating RTLIL representation for module `\_90_pmux'. 179s Generating RTLIL representation for module `\_90_demux'. 179s Generating RTLIL representation for module `\_90_lut'. 179s Successfully finished Verilog frontend. 179s 179s 2.32.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v 179s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation. 179s Generating RTLIL representation for module `\_80_ice40_alu'. 179s Successfully finished Verilog frontend. 179s 179s 2.32.3. Continuing TECHMAP pass. 179s Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_80_ice40_alu for cells of type $alu. 179s Using extmapper simplemap for cells of type $logic_not. 179s Using template $paramod$080e6a70eb8bfa1ccf22d9718e795074645029a4\_80_ice40_alu for cells of type $alu. 179s Using extmapper simplemap for cells of type $xor. 179s Using extmapper simplemap for cells of type $reduce_and. 179s Using extmapper simplemap for cells of type $dff. 179s Using extmapper simplemap for cells of type $mux. 179s Using extmapper simplemap for cells of type $not. 179s Using extmapper simplemap for cells of type $pos. 179s No more expansions possible. 179s 179s 179s 2.33. Executing OPT pass (performing simple optimizations). 179s 179s 2.33.1. Executing OPT_EXPR pass (perform const folding). 179s Optimizing module top. 179s 179s 179s 2.33.2. Executing OPT_MERGE pass (detect identical cells). 179s Finding identical cells in module `\top'. 179s 179s Removed a total of 1 cells. 179s 179s 2.33.3. Executing OPT_DFF pass (perform DFF optimizations). 179s 179s 2.33.4. Executing OPT_CLEAN pass (remove unused cells and wires). 179s Finding unused cells or wires in module \top.. 179s Removed 27 unused cells and 34 unused wires. 179s 179s 179s 2.33.5. Finished fast OPT passes. 179s 179s 2.34. Executing ICE40_OPT pass (performing simple optimizations). 179s 179s 2.34.1. Running ICE40 specific optimizations. 179s Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$460.slice[0].carry: CO=\counter [0] 179s 179s 2.34.2. Executing OPT_EXPR pass (perform const folding). 179s Optimizing module top. 179s 179s 2.34.3. Executing OPT_MERGE pass (detect identical cells). 179s Finding identical cells in module `\top'. 179s Removed a total of 0 cells. 179s 179s 2.34.4. Executing OPT_DFF pass (perform DFF optimizations). 179s 179s 2.34.5. Executing OPT_CLEAN pass (remove unused cells and wires). 179s Finding unused cells or wires in module \top.. 179s 179s 2.34.6. Rerunning OPT passes. (Removed registers in this run.) 179s 179s 2.34.7. Running ICE40 specific optimizations. 179s 179s 2.34.8. Executing OPT_EXPR pass (perform const folding). 179s Optimizing module top. 179s 179s 2.34.9. Executing OPT_MERGE pass (detect identical cells). 179s Finding identical cells in module `\top'. 179s Removed a total of 0 cells. 179s 179s 2.34.10. Executing OPT_DFF pass (perform DFF optimizations). 179s 179s 2.34.11. Executing OPT_CLEAN pass (remove unused cells and wires). 179s Finding unused cells or wires in module \top.. 179s 179s 2.34.12. Finished OPT passes. (There is nothing left to do.) 179s 179s 2.35. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 179s 179s 2.36. Executing TECHMAP pass (map to technology primitives). 179s 179s 2.36.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 179s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 179s Generating RTLIL representation for module `\$_DFF_N_'. 179s Generating RTLIL representation for module `\$_DFF_P_'. 179s Generating RTLIL representation for module `\$_DFFE_NP_'. 179s Generating RTLIL representation for module `\$_DFFE_PP_'. 179s Generating RTLIL representation for module `\$_DFF_NP0_'. 179s Generating RTLIL representation for module `\$_DFF_NP1_'. 179s Generating RTLIL representation for module `\$_DFF_PP0_'. 179s Generating RTLIL representation for module `\$_DFF_PP1_'. 179s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 179s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 179s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 179s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 179s Generating RTLIL representation for module `\$_SDFF_NP0_'. 179s Generating RTLIL representation for module `\$_SDFF_NP1_'. 179s Generating RTLIL representation for module `\$_SDFF_PP0_'. 179s Generating RTLIL representation for module `\$_SDFF_PP1_'. 179s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 179s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 179s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 179s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 179s Successfully finished Verilog frontend. 179s 179s 2.36.2. Continuing TECHMAP pass. 179s Using template \$_DFF_P_ for cells of type $_DFF_P_. 179s No more expansions possible. 179s 179s 179s 2.37. Executing OPT_EXPR pass (perform const folding). 179s Optimizing module top. 179s 179s 2.38. Executing SIMPLEMAP pass (map simple cells to gate primitives). 179s Mapping top.$auto$alumacc.cc:485:replace_alu$460.slice[0].carry ($lut). 179s 179s 2.39. Executing ICE40_OPT pass (performing simple optimizations). 179s 179s 2.39.1. Running ICE40 specific optimizations. 179s 179s 2.39.2. Executing OPT_EXPR pass (perform const folding). 179s Optimizing module top. 179s 179s 179s 2.39.3. Executing OPT_MERGE pass (detect identical cells). 179s Finding identical cells in module `\top'. 179s Removed a total of 0 cells. 179s 179s 2.39.4. Executing OPT_DFF pass (perform DFF optimizations). 179s 179s 2.39.5. Executing OPT_CLEAN pass (remove unused cells and wires). 179s Finding unused cells or wires in module \top.. 179s Removed 0 unused cells and 112 unused wires. 179s 179s 179s 2.39.6. Rerunning OPT passes. (Removed registers in this run.) 179s 179s 2.39.7. Running ICE40 specific optimizations. 179s 179s 2.39.8. Executing OPT_EXPR pass (perform const folding). 179s Optimizing module top. 179s 179s 2.39.9. Executing OPT_MERGE pass (detect identical cells). 179s Finding identical cells in module `\top'. 179s Removed a total of 0 cells. 179s 179s 2.39.10. Executing OPT_DFF pass (perform DFF optimizations). 179s 179s 2.39.11. Executing OPT_CLEAN pass (remove unused cells and wires). 179s Finding unused cells or wires in module \top.. 179s 179s 2.39.12. Finished OPT passes. (There is nothing left to do.) 179s 179s 2.40. Executing TECHMAP pass (map to technology primitives). 179s 179s 2.40.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v 179s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation. 179s Generating RTLIL representation for module `\$_DLATCH_N_'. 179s Generating RTLIL representation for module `\$_DLATCH_P_'. 179s Successfully finished Verilog frontend. 179s 179s 2.40.2. Continuing TECHMAP pass. 179s No more expansions possible. 179s 179s 179s 2.41. Executing ABC pass (technology mapping using ABC). 179s 179s 2.41.1. Extracting gate netlist of module `\top' to `/input.blif'.. 179s Extracted 27 gates and 54 wires to a netlist network with 27 inputs and 4 outputs. 179s 179s 2.41.1.1. Executing ABC. 179s Running ABC command: "berkeley-abc" -s -f /abc.script 2>&1 179s ABC: ABC command line: "source /abc.script". 179s ABC: 179s ABC: + read_blif /input.blif 179s ABC: + read_lut /lutdefs.txt 179s ABC: + strash 179s ABC: + &get -n 179s ABC: + &fraig -x 179s ABC: + &put 179s ABC: + scorr 179s ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). 179s ABC: + dc2 179s ABC: + dretime 179s ABC: + strash 179s ABC: + dch -f 179s ABC: + if 179s ABC: + mfs2 179s ABC: + lutpack -S 1 179s ABC: + dress /input.blif 179s ABC: Total number of equiv classes = 5. 179s ABC: Participating nodes from both networks = 9. 179s ABC: Participating nodes from the first network = 4. ( 30.77 % of nodes) 179s ABC: Participating nodes from the second network = 5. ( 38.46 % of nodes) 179s ABC: Node pairs (any polarity) = 4. ( 30.77 % of names can be moved) 179s ABC: Node pairs (same polarity) = 4. ( 30.77 % of names can be moved) 179s ABC: Total runtime = 0.06 sec 179s ABC: + write_blif /output.blif 179s 179s 2.41.1.2. Re-integrating ABC results. 179s ABC RESULTS: $lut cells: 12 179s ABC RESULTS: internal signals: 23 179s ABC RESULTS: input signals: 27 179s ABC RESULTS: output signals: 4 179s Removing temp directory. 179s 179s 2.42. Executing ICE40_WRAPCARRY pass (wrap carries). 179s 179s 2.43. Executing TECHMAP pass (map to technology primitives). 179s 179s 2.43.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 179s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 179s Generating RTLIL representation for module `\$_DFF_N_'. 179s Generating RTLIL representation for module `\$_DFF_P_'. 179s Generating RTLIL representation for module `\$_DFFE_NP_'. 179s Generating RTLIL representation for module `\$_DFFE_PP_'. 179s Generating RTLIL representation for module `\$_DFF_NP0_'. 179s Generating RTLIL representation for module `\$_DFF_NP1_'. 179s Generating RTLIL representation for module `\$_DFF_PP0_'. 179s Generating RTLIL representation for module `\$_DFF_PP1_'. 179s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 179s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 179s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 179s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 179s Generating RTLIL representation for module `\$_SDFF_NP0_'. 179s Generating RTLIL representation for module `\$_SDFF_NP1_'. 179s Generating RTLIL representation for module `\$_SDFF_PP0_'. 179s Generating RTLIL representation for module `\$_SDFF_PP1_'. 179s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 179s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 179s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 179s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 179s Successfully finished Verilog frontend. 179s 179s 2.43.2. Continuing TECHMAP pass. 179s No more expansions possible. 179s 179s Removed 2 unused cells and 39 unused wires. 179s 179s 2.44. Executing OPT_LUT pass (optimize LUTs). 179s Discovering LUTs. 179s Number of LUTs: 37 179s 1-LUT 1 179s 2-LUT 4 179s 3-LUT 25 179s 4-LUT 7 179s with \SB_CARRY (#0) 23 179s with \SB_CARRY (#1) 23 179s 179s Eliminating LUTs. 179s Number of LUTs: 37 179s 1-LUT 1 179s 2-LUT 4 179s 3-LUT 25 179s 4-LUT 7 179s with \SB_CARRY (#0) 23 179s with \SB_CARRY (#1) 23 179s 179s Combining LUTs. 179s Number of LUTs: 37 179s 1-LUT 1 179s 2-LUT 4 179s 3-LUT 25 179s 4-LUT 7 179s with \SB_CARRY (#0) 23 179s with \SB_CARRY (#1) 23 179s 179s Eliminated 0 LUTs. 179s Combined 0 LUTs. 179s 179s 179s 2.45. Executing TECHMAP pass (map to technology primitives). 179s 179s 2.45.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v 179s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation. 179s Generating RTLIL representation for module `\$lut'. 179s Successfully finished Verilog frontend. 179s 179s 2.45.2. Continuing TECHMAP pass. 179s Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut. 179s Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut. 179s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut. 179s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. 179s Using template $paramod$415b9dd3a15783ae56c103f189fd8e182f997441\$lut for cells of type $lut. 179s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. 179s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. 179s Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut. 179s No more expansions possible. 179s 179s Removed 0 unused cells and 78 unused wires. 179s 179s 2.46. Executing AUTONAME pass. 179s Renamed 463 objects in module top (10 iterations). 179s 179s 179s 2.47. Executing HIERARCHY pass (managing design hierarchy). 179s 179s 2.47.1. Analyzing design hierarchy.. 179s Top module: \top 179s 179s 2.47.2. Analyzing design hierarchy.. 179s Top module: \top 179s Removed 0 unused modules. 179s 179s 2.48. Printing statistics. 179s 179s === top === 179s 179s Number of wires: 20 179s Number of wire bits: 99 179s Number of public wires: 20 179s Number of public wire bits: 99 179s Number of memories: 0 179s Number of memory bits: 0 179s Number of processes: 0 179s Number of cells: 88 179s SB_CARRY 23 179s SB_DFF 27 179s SB_LUT4 37 179s SB_WARMBOOT 1 179s 179s 2.49. Executing CHECK pass (checking for obvious problems). 179s Checking module top... 179s Found and reported 0 problems. 179s 179s 2.50. Executing JSON backend. 179s 179s End of script. Logfile hash: bcf022d18d, CPU: user 0.67s system 0.02s, MEM: 20.00 MB peak 179s Yosys 0.23 (git sha1 7ce5011c24b) 179s Time spent: 54% 13x read_verilog (0 sec), 19% 1x abc (0 sec), ... 179s nextpnr-ice40 --hx1k --package tq144 --asc app2.asc --pcf icestick.pcf --json app2.json 179s Warning: unmatched constraint 'RX' (on line 4) 179s Warning: unmatched constraint 'TX' (on line 5) 179s Info: constrained 'LED1' to bel 'X13/Y12/io1' 179s Info: constrained 'LED2' to bel 'X13/Y12/io0' 179s Info: constrained 'LED3' to bel 'X13/Y11/io1' 179s Info: constrained 'LED4' to bel 'X13/Y11/io0' 179s Info: constrained 'LED5' to bel 'X13/Y9/io1' 179s Info: constrained 'clk' to bel 'X0/Y8/io1' 179s 179s Info: Packing constants.. 179s Info: Packing IOs.. 179s Info: Packing LUT-FFs.. 179s Info: 10 LCs used as LUT4 only 179s Info: 27 LCs used as LUT4 and DFF 179s Info: Packing non-LUT FFs.. 179s Info: 0 LCs used as DFF only 179s Info: Packing carries.. 179s Info: 0 LCs used as CARRY only 179s Info: Packing indirect carry+LUT pairs... 179s Info: 0 LUTs merged into carry LCs 179s Info: Packing RAMs.. 179s Info: Placing PLLs.. 179s Info: Packing special functions.. 179s Info: Packing PLLs.. 179s Info: Promoting globals.. 179s Info: promoting clk$SB_IO_IN (fanout 27) 179s Info: Constraining chains... 179s Info: 1 LCs used to legalise carry chains. 179s Info: Checksum: 0x56217244 179s 179s Info: Annotating ports with timing budgets for target frequency 12.00 MHz 179s Info: Checksum: 0x1d95d669 179s 179s Info: Device utilisation: 179s Info: ICESTORM_LC: 40/ 1280 3% 179s Info: ICESTORM_RAM: 0/ 16 0% 179s Info: SB_IO: 6/ 112 5% 179s Info: SB_GB: 1/ 8 12% 179s Info: ICESTORM_PLL: 0/ 1 0% 179s Info: SB_WARMBOOT: 1/ 1 100% 179s 179s Info: Placed 6 cells based on constraints. 179s Info: Creating initial analytic placement for 18 cells, random placement wirelen = 338. 179s Info: at initial placer iter 0, wirelen = 23 179s Info: at initial placer iter 1, wirelen = 14 179s Info: at initial placer iter 2, wirelen = 14 179s Info: at initial placer iter 3, wirelen = 14 179s Info: Running main analytical placer, max placement attempts per cell = 10000. 179s Info: at iteration #1, type ICESTORM_LC: wirelen solved = 14, spread = 75, legal = 75; time = 0.00s 179s Info: at iteration #1, type SB_GB: wirelen solved = 75, spread = 75, legal = 75; time = 0.00s 179s Info: at iteration #1, type SB_WARMBOOT: wirelen solved = 72, spread = 72, legal = 110; time = 0.00s 179s Info: at iteration #1, type ALL: wirelen solved = 28, spread = 78, legal = 117; time = 0.00s 179s Info: at iteration #2, type ICESTORM_LC: wirelen solved = 65, spread = 96, legal = 117; time = 0.00s 179s Info: at iteration #2, type SB_GB: wirelen solved = 117, spread = 117, legal = 117; time = 0.00s 179s Info: at iteration #2, type SB_WARMBOOT: wirelen solved = 83, spread = 83, legal = 117; time = 0.00s 179s Info: at iteration #2, type ALL: wirelen solved = 17, spread = 58, legal = 97; time = 0.00s 179s Info: at iteration #3, type ICESTORM_LC: wirelen solved = 62, spread = 103, legal = 111; time = 0.00s 179s Info: at iteration #3, type SB_GB: wirelen solved = 111, spread = 111, legal = 111; time = 0.00s 179s Info: at iteration #3, type SB_WARMBOOT: wirelen solved = 74, spread = 74, legal = 111; time = 0.00s 179s Info: at iteration #3, type ALL: wirelen solved = 22, spread = 68, legal = 104; time = 0.00s 179s Info: at iteration #4, type ICESTORM_LC: wirelen solved = 60, spread = 109, legal = 113; time = 0.00s 179s Info: at iteration #4, type SB_GB: wirelen solved = 113, spread = 113, legal = 113; time = 0.00s 179s Info: at iteration #4, type SB_WARMBOOT: wirelen solved = 77, spread = 77, legal = 113; time = 0.00s 179s Info: at iteration #4, type ALL: wirelen solved = 20, spread = 67, legal = 104; time = 0.00s 179s Info: at iteration #5, type ICESTORM_LC: wirelen solved = 62, spread = 109, legal = 110; time = 0.00s 179s Info: at iteration #5, type SB_GB: wirelen solved = 110, spread = 110, legal = 110; time = 0.00s 179s Info: at iteration #5, type SB_WARMBOOT: wirelen solved = 77, spread = 77, legal = 110; time = 0.00s 179s Info: at iteration #5, type ALL: wirelen solved = 26, spread = 67, legal = 104; time = 0.00s 179s Info: at iteration #6, type ICESTORM_LC: wirelen solved = 62, spread = 109, legal = 113; time = 0.00s 179s Info: at iteration #6, type SB_GB: wirelen solved = 113, spread = 113, legal = 113; time = 0.00s 179s Info: at iteration #6, type SB_WARMBOOT: wirelen solved = 80, spread = 80, legal = 113; time = 0.00s 179s Info: at iteration #6, type ALL: wirelen solved = 24, spread = 70, legal = 104; time = 0.00s 179s Info: at iteration #7, type ICESTORM_LC: wirelen solved = 61, spread = 110, legal = 109; time = 0.00s 179s Info: at iteration #7, type SB_GB: wirelen solved = 109, spread = 109, legal = 109; time = 0.00s 179s Info: at iteration #7, type SB_WARMBOOT: wirelen solved = 78, spread = 78, legal = 109; time = 0.00s 179s Info: at iteration #7, type ALL: wirelen solved = 29, spread = 79, legal = 113; time = 0.00s 179s Info: HeAP Placer Time: 0.02s 179s Info: of which solving equations: 0.01s 179s Info: of which spreading cells: 0.00s 179s Info: of which strict legalisation: 0.00s 179s 179s Info: Running simulated annealing placer for refinement. 179s Info: at iteration #1: temp = 0.000000, timing cost = 18, wirelen = 97 179s Info: at iteration #5: temp = 0.000000, timing cost = 9, wirelen = 90 179s Info: at iteration #7: temp = 0.000000, timing cost = 17, wirelen = 75 179s Info: SA placement time 0.01s 179s 179s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 192.23 MHz (PASS at 12.00 MHz) 179s 179s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> : 3.94 ns 179s 179s Info: Slack histogram: 179s Info: legend: * represents 1 endpoint(s) 179s Info: + represents [1,1) endpoint(s) 179s Info: [ 78131, 78335) |*** 179s Info: [ 78335, 78539) |** 179s Info: [ 78539, 78743) |** 179s Info: [ 78743, 78947) |*** 179s Info: [ 78947, 79151) | 179s Info: [ 79151, 79355) |** 179s Info: [ 79355, 79559) |** 179s Info: [ 79559, 79763) |** 179s Info: [ 79763, 79967) |*** 179s Info: [ 79967, 80171) |*** 179s Info: [ 80171, 80375) | 179s Info: [ 80375, 80579) | 179s Info: [ 80579, 80783) |** 179s Info: [ 80783, 80987) |** 179s Info: [ 80987, 81191) |* 179s Info: [ 81191, 81395) |* 179s Info: [ 81395, 81599) | 179s Info: [ 81599, 81803) | 179s Info: [ 81803, 82007) |**************************** 179s Info: [ 82007, 82211) |* 179s Info: Checksum: 0xaf56facc 179s 179s Info: Routing.. 179s Info: Setting up routing queue. 179s Info: Routing 126 arcs. 179s Info: | (re-)routed arcs | delta | remaining| time spent | 179s Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| 179s Info: 128 | 2 106 | 2 106 | 0| 0.01 0.01| 179s Info: Routing complete. 179s Info: Router1 time 0.01s 179s Info: Checksum: 0xc47dd9db 179s 179s Info: Critical path report for clock 'clk$SB_IO_IN_$glb_clk' (posedge -> posedge): 179s Info: curr total 179s icetime -d hx1k -c 25 app2.asc 179s Info: 0.5 0.5 Source counter_SB_LUT4_I2_3_LC.O 179s Info: 0.6 1.1 Net counter[6] budget 20.292999 ns (11,8) -> (12,9) 179s Info: Sink state_SB_LUT4_I3_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_LC.I0 179s Info: Defined in: 179s Info: app2.v:7.22-7.29 179s Info: 0.4 1.6 Source state_SB_LUT4_I3_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_LC.O 179s Info: 0.6 2.2 Net state_SB_LUT4_I3_I0_SB_LUT4_O_1_I2[0] budget 20.292999 ns (12,9) -> (12,10) 179s Info: Sink state_SB_LUT4_I3_I0_SB_LUT4_O_1_LC.I2 179s Info: Defined in: 179s Info: /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 179s Info: 0.4 2.5 Source state_SB_LUT4_I3_I0_SB_LUT4_O_1_LC.O 179s Info: 0.6 3.1 Net state_SB_LUT4_I3_I0[1] budget 20.292000 ns (12,10) -> (12,9) 179s Info: Sink counter2_SB_LUT4_I2_3_I1_SB_LUT4_O_LC.I2 179s Info: Defined in: 179s Info: /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 179s Info: 0.4 3.5 Source counter2_SB_LUT4_I2_3_I1_SB_LUT4_O_LC.O 179s Info: 0.6 4.1 Net counter2_SB_LUT4_I2_3_I1 budget 20.292000 ns (12,9) -> (12,8) 179s Info: Sink counter2_SB_LUT4_I2_3_LC.I1 179s Info: Defined in: 179s Info: app2.v:13.15-13.34 179s Info: /usr/bin/../share/yosys/ice40/arith_map.v:29.22-29.23 179s Info: 0.3 4.4 Source counter2_SB_LUT4_I2_3_LC.COUT 179s Info: 0.0 4.4 Net counter2_SB_CARRY_I1_CO[1] budget 0.000000 ns (12,8) -> (12,8) 179s Info: Sink counter2_SB_LUT4_I2_2_LC.CIN 179s Info: Defined in: 179s Info: app2.v:13.15-13.34 179s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 179s Info: 0.1 4.5 Source counter2_SB_LUT4_I2_2_LC.COUT 179s Info: 0.0 4.5 Net counter2_SB_CARRY_I1_CO[2] budget 0.000000 ns (12,8) -> (12,8) 179s Info: Sink counter2_SB_LUT4_I2_1_LC.CIN 179s Info: Defined in: 179s Info: app2.v:13.15-13.34 179s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 179s Info: 0.1 4.6 Source counter2_SB_LUT4_I2_1_LC.COUT 179s Info: 0.3 4.9 Net counter2_SB_CARRY_I1_CO[3] budget 0.260000 ns (12,8) -> (12,8) 179s Info: Sink counter2_SB_LUT4_I2_LC.I3 179s Info: Defined in: 179s Info: app2.v:13.15-13.34 179s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 179s Info: 0.3 5.2 Setup counter2_SB_LUT4_I2_LC.I3 179s Info: 2.6 ns logic, 2.6 ns routing 179s 179s Info: Critical path report for cross-domain path 'posedge clk$SB_IO_IN_$glb_clk' -> '': 179s Info: curr total 179s Info: 0.5 0.5 Source counter2_SB_LUT4_I2_3_LC.O 179s Info: 0.6 1.1 Net counter2[0] budget 41.173000 ns (12,8) -> (12,8) 179s Info: Sink WB_BOOT_SB_LUT4_O_LC.I0 179s Info: Defined in: 179s Info: app2.v:8.12-8.20 179s Info: 0.4 1.6 Source WB_BOOT_SB_LUT4_O_LC.O 179s Info: 1.1 2.6 Net WB_BOOT budget 41.172001 ns (12,8) -> (0,0) 179s Info: Sink WB.BOOT 179s Info: Defined in: 179s Info: app2.v:24.9-24.18 179s Info: 1.0 ns logic, 1.7 ns routing 179s 179s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 192.23 MHz (PASS at 12.00 MHz) 179s 179s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> : 2.65 ns 179s 179s Info: Slack histogram: 179s Info: legend: * represents 1 endpoint(s) 179s Info: + represents [1,1) endpoint(s) 179s Info: [ 78131, 78335) |** 179s Info: [ 78335, 78539) |** 179s Info: [ 78539, 78743) |** 179s Info: [ 78743, 78947) |*** 179s Info: [ 78947, 79151) |* 179s Info: [ 79151, 79355) | 179s Info: [ 79355, 79559) |*** 179s Info: [ 79559, 79763) |* 179s Info: [ 79763, 79967) |**** 179s Info: [ 79967, 80171) |*** 179s Info: [ 80171, 80375) | 179s Info: [ 80375, 80579) | 179s Info: [ 80579, 80783) |*** 179s Info: [ 80783, 80987) |** 179s Info: [ 80987, 81191) |* 179s Info: [ 81191, 81395) |* 179s Info: [ 81395, 81599) | 179s Info: [ 81599, 81803) | 179s Info: [ 81803, 82007) |**************************** 179s Info: [ 82007, 82211) |* 179s 2 warnings, 0 errors 179s 179s Info: Program finished normally. 179s // Reading input .asc file.. 179s // Reading 1k chipdb file.. 180s // Creating timing netlist.. 180s // Timing estimate: 5.30 ns (188.54 MHz) 180s // Checking 40.00 ns (25.00 MHz) clock constraint: PASSED. 180s icepack app2.asc app2.bin 180s yosys -p "synth_ice40 -top top -json app3.json" app3.v 180s 180s /----------------------------------------------------------------------------\ 180s | | 180s | yosys -- Yosys Open SYnthesis Suite | 180s | | 180s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 180s | | 180s | Permission to use, copy, modify, and/or distribute this software for any | 180s | purpose with or without fee is hereby granted, provided that the above | 180s | copyright notice and this permission notice appear in all copies. | 180s | | 180s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 180s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 180s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 180s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 180s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 180s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 180s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 180s | | 180s \----------------------------------------------------------------------------/ 180s 180s Yosys 0.23 (git sha1 7ce5011c24b) 180s 180s 180s -- Parsing `app3.v' using frontend ` -vlog2k' -- 180s 180s 1. Executing Verilog-2005 frontend: app3.v 180s Parsing Verilog input from `app3.v' to AST representation. 180s Storing AST representation for module `$abstract\top'. 180s Successfully finished Verilog frontend. 180s 180s -- Running command `synth_ice40 -top top -json app3.json' -- 180s 180s 2. Executing SYNTH_ICE40 pass. 180s 180s 2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v 180s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation. 180s Generating RTLIL representation for module `\SB_IO'. 180s Generating RTLIL representation for module `\SB_GB_IO'. 180s Generating RTLIL representation for module `\SB_GB'. 180s Generating RTLIL representation for module `\SB_LUT4'. 180s Generating RTLIL representation for module `\SB_CARRY'. 180s Generating RTLIL representation for module `\SB_DFF'. 180s Generating RTLIL representation for module `\SB_DFFE'. 180s Generating RTLIL representation for module `\SB_DFFSR'. 180s Generating RTLIL representation for module `\SB_DFFR'. 180s Generating RTLIL representation for module `\SB_DFFSS'. 180s Generating RTLIL representation for module `\SB_DFFS'. 180s Generating RTLIL representation for module `\SB_DFFESR'. 180s Generating RTLIL representation for module `\SB_DFFER'. 180s Generating RTLIL representation for module `\SB_DFFESS'. 180s Generating RTLIL representation for module `\SB_DFFES'. 180s Generating RTLIL representation for module `\SB_DFFN'. 180s Generating RTLIL representation for module `\SB_DFFNE'. 180s Generating RTLIL representation for module `\SB_DFFNSR'. 180s Generating RTLIL representation for module `\SB_DFFNR'. 180s Generating RTLIL representation for module `\SB_DFFNSS'. 180s Generating RTLIL representation for module `\SB_DFFNS'. 180s Generating RTLIL representation for module `\SB_DFFNESR'. 180s Generating RTLIL representation for module `\SB_DFFNER'. 180s Generating RTLIL representation for module `\SB_DFFNESS'. 180s Generating RTLIL representation for module `\SB_DFFNES'. 180s Generating RTLIL representation for module `\SB_RAM40_4K'. 180s Generating RTLIL representation for module `\SB_RAM40_4KNR'. 180s Generating RTLIL representation for module `\SB_RAM40_4KNW'. 180s Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. 180s Generating RTLIL representation for module `\ICESTORM_LC'. 180s Generating RTLIL representation for module `\SB_PLL40_CORE'. 180s Generating RTLIL representation for module `\SB_PLL40_PAD'. 180s Generating RTLIL representation for module `\SB_PLL40_2_PAD'. 180s Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. 180s Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. 180s Generating RTLIL representation for module `\SB_WARMBOOT'. 180s Generating RTLIL representation for module `\SB_SPRAM256KA'. 180s Generating RTLIL representation for module `\SB_HFOSC'. 180s Generating RTLIL representation for module `\SB_LFOSC'. 180s Generating RTLIL representation for module `\SB_RGBA_DRV'. 180s Generating RTLIL representation for module `\SB_LED_DRV_CUR'. 180s Generating RTLIL representation for module `\SB_RGB_DRV'. 180s Generating RTLIL representation for module `\SB_I2C'. 180s Generating RTLIL representation for module `\SB_SPI'. 180s Generating RTLIL representation for module `\SB_LEDDA_IP'. 180s Generating RTLIL representation for module `\SB_FILTER_50NS'. 180s Generating RTLIL representation for module `\SB_IO_I3C'. 180s Generating RTLIL representation for module `\SB_IO_OD'. 180s Generating RTLIL representation for module `\SB_MAC16'. 180s Generating RTLIL representation for module `\ICESTORM_RAM'. 180s Successfully finished Verilog frontend. 180s 180s 2.2. Executing HIERARCHY pass (managing design hierarchy). 180s 180s 2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\top'. 180s Generating RTLIL representation for module `\top'. 180s 180s 2.3.1. Analyzing design hierarchy.. 180s Top module: \top 180s 180s 2.3.2. Analyzing design hierarchy.. 180s Top module: \top 180s Removing unused module `$abstract\top'. 180s Removed 1 unused modules. 180s 180s 2.4. Executing PROC pass (convert processes to netlists). 180s 180s 2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 180s Cleaned up 0 empty switches. 180s 180s 2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 180s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241 in module SB_DFFNES. 180s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234 in module SB_DFFNESS. 180s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230 in module SB_DFFNER. 180s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223 in module SB_DFFNESR. 180s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220 in module SB_DFFNS. 180s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217 in module SB_DFFNSS. 180s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214 in module SB_DFFNR. 180s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211 in module SB_DFFNSR. 180s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203 in module SB_DFFES. 180s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196 in module SB_DFFESS. 180s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192 in module SB_DFFER. 180s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185 in module SB_DFFESR. 180s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182 in module SB_DFFS. 180s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179 in module SB_DFFSS. 180s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176 in module SB_DFFR. 180s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173 in module SB_DFFSR. 180s Removed a total of 0 dead cases. 180s 180s 2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 180s Removed 8 redundant assignments. 180s Promoted 28 assignments to connections. 180s 180s 2.4.4. Executing PROC_INIT pass (extract init attributes). 180s Found init rule in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 180s Set init value: \Q = 1'0 180s Found init rule in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 180s Set init value: \Q = 1'0 180s Found init rule in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 180s Set init value: \Q = 1'0 180s Found init rule in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 180s Set init value: \Q = 1'0 180s Found init rule in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 180s Set init value: \Q = 1'0 180s Found init rule in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 180s Set init value: \Q = 1'0 180s Found init rule in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 180s Set init value: \Q = 1'0 180s Found init rule in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 180s Set init value: \Q = 1'0 180s Found init rule in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 180s Set init value: \Q = 1'0 180s Found init rule in `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 180s Set init value: \Q = 1'0 180s Found init rule in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 180s Set init value: \Q = 1'0 180s Found init rule in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 180s Set init value: \Q = 1'0 180s Found init rule in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 180s Set init value: \Q = 1'0 180s Found init rule in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 180s Set init value: \Q = 1'0 180s Found init rule in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 180s Set init value: \Q = 1'0 180s Found init rule in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 180s Set init value: \Q = 1'0 180s Found init rule in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 180s Set init value: \Q = 1'0 180s Found init rule in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 180s Set init value: \Q = 1'0 180s Found init rule in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 180s Set init value: \Q = 1'0 180s Found init rule in `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 180s Set init value: \Q = 1'0 180s Found init rule in `\top.$proc$app3.v:9$390'. 180s Set init value: \state = 1'0 180s Found init rule in `\top.$proc$app3.v:8$389'. 180s Set init value: \counter2 = 4'0000 180s Found init rule in `\top.$proc$app3.v:7$388'. 180s Set init value: \counter = 22'0000000000000000000000 180s 180s 2.4.5. Executing PROC_ARST pass (detect async resets in processes). 180s Found async reset \S in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 180s Found async reset \R in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 180s Found async reset \S in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 180s Found async reset \R in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 180s Found async reset \S in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 180s Found async reset \R in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 180s Found async reset \S in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 180s Found async reset \R in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 180s 180s 2.4.6. Executing PROC_ROM pass (convert switches to ROMs). 180s Converted 0 switches. 180s 180s 180s 2.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 180s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 180s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 180s 1/1: $0\Q[0:0] 180s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 180s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 180s 1/1: $0\Q[0:0] 180s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 180s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 180s 1/1: $0\Q[0:0] 180s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 180s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 180s 1/1: $0\Q[0:0] 180s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 180s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 180s 1/1: $0\Q[0:0] 180s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 180s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 180s 1/1: $0\Q[0:0] 180s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 180s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 180s 1/1: $0\Q[0:0] 180s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 180s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 180s 1/1: $0\Q[0:0] 180s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 180s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 180s 1/1: $0\Q[0:0] 180s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 180s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 180s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 180s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 180s 1/1: $0\Q[0:0] 180s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 180s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 180s 1/1: $0\Q[0:0] 180s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 180s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 180s 1/1: $0\Q[0:0] 180s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 180s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 180s 1/1: $0\Q[0:0] 180s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 180s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 180s 1/1: $0\Q[0:0] 180s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 180s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 180s 1/1: $0\Q[0:0] 180s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 180s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 180s 1/1: $0\Q[0:0] 180s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 180s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 180s 1/1: $0\Q[0:0] 180s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 180s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 180s 1/1: $0\Q[0:0] 180s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 180s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 180s Creating decoders for process `\top.$proc$app3.v:9$390'. 180s Creating decoders for process `\top.$proc$app3.v:8$389'. 180s Creating decoders for process `\top.$proc$app3.v:7$388'. 180s Creating decoders for process `\top.$proc$app3.v:11$381'. 180s 180s 2.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). 180s 180s 2.4.9. Executing PROC_DFF pass (convert process syncs to FFs). 180s Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 180s created $adff cell `$procdff$435' with negative edge clock and positive level reset. 180s Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 180s created $dff cell `$procdff$436' with negative edge clock. 180s Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 180s created $adff cell `$procdff$437' with negative edge clock and positive level reset. 180s Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 180s created $dff cell `$procdff$438' with negative edge clock. 180s Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 180s created $adff cell `$procdff$439' with negative edge clock and positive level reset. 180s Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 180s created $dff cell `$procdff$440' with negative edge clock. 180s Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 180s created $adff cell `$procdff$441' with negative edge clock and positive level reset. 180s Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 180s created $dff cell `$procdff$442' with negative edge clock. 180s Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 180s created $dff cell `$procdff$443' with negative edge clock. 180s Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 180s created $dff cell `$procdff$444' with negative edge clock. 180s Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 180s created $adff cell `$procdff$445' with positive edge clock and positive level reset. 180s Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 180s created $dff cell `$procdff$446' with positive edge clock. 180s Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 180s created $adff cell `$procdff$447' with positive edge clock and positive level reset. 180s Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 180s created $dff cell `$procdff$448' with positive edge clock. 180s Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 180s created $adff cell `$procdff$449' with positive edge clock and positive level reset. 180s Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 180s created $dff cell `$procdff$450' with positive edge clock. 180s Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 180s created $adff cell `$procdff$451' with positive edge clock and positive level reset. 180s Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 180s created $dff cell `$procdff$452' with positive edge clock. 180s Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 180s created $dff cell `$procdff$453' with positive edge clock. 180s Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 180s created $dff cell `$procdff$454' with positive edge clock. 180s Creating register for signal `\top.\counter' using process `\top.$proc$app3.v:11$381'. 180s created $dff cell `$procdff$455' with positive edge clock. 180s Creating register for signal `\top.\counter2' using process `\top.$proc$app3.v:11$381'. 180s created $dff cell `$procdff$456' with positive edge clock. 180s Creating register for signal `\top.\state' using process `\top.$proc$app3.v:11$381'. 180s created $dff cell `$procdff$457' with positive edge clock. 180s 180s 2.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 180s 180s 2.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 180s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 180s Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 180s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 180s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 180s Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 180s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 180s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 180s Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 180s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 180s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 180s Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 180s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 180s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 180s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 180s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 180s Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 180s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 180s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 180s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 180s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 180s Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 180s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 180s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 180s Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 180s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 180s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 180s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 180s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 180s Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 180s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 180s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 180s Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 180s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 180s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 180s Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 180s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 180s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 180s Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 180s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 180s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 180s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 180s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 180s Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 180s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 180s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 180s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 180s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 180s Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 180s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 180s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 180s Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 180s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 180s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 180s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 180s Removing empty process `top.$proc$app3.v:9$390'. 180s Removing empty process `top.$proc$app3.v:8$389'. 180s Removing empty process `top.$proc$app3.v:7$388'. 180s Removing empty process `top.$proc$app3.v:11$381'. 180s Cleaned up 18 empty switches. 180s 180s 2.4.12. Executing OPT_EXPR pass (perform const folding). 180s Optimizing module top. 180s 180s 2.5. Executing FLATTEN pass (flatten design). 180s 180s 2.6. Executing TRIBUF pass. 180s 180s 2.7. Executing DEMINOUT pass (demote inout ports to input or output). 180s 180s 2.8. Executing OPT_EXPR pass (perform const folding). 180s Optimizing module top. 180s 180s 2.9. Executing OPT_CLEAN pass (remove unused cells and wires). 180s Finding unused cells or wires in module \top.. 180s Removed 0 unused cells and 5 unused wires. 180s 180s 180s 2.10. Executing CHECK pass (checking for obvious problems). 180s Checking module top... 180s Found and reported 0 problems. 180s 180s 2.11. Executing OPT pass (performing simple optimizations). 180s 180s 2.11.1. Executing OPT_EXPR pass (perform const folding). 180s Optimizing module top. 180s 180s 2.11.2. Executing OPT_MERGE pass (detect identical cells). 180s Finding identical cells in module `\top'. 180s Removed a total of 0 cells. 180s 180s 2.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 180s Running muxtree optimizer on module \top.. 180s Creating internal representation of mux trees. 180s No muxes found in this module. 180s Removed 0 multiplexer ports. 180s 180s 2.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 180s Optimizing cells in module \top. 180s Performed a total of 0 changes. 180s 180s 2.11.5. Executing OPT_MERGE pass (detect identical cells). 180s Finding identical cells in module `\top'. 180s Removed a total of 0 cells. 180s 180s 2.11.6. Executing OPT_DFF pass (perform DFF optimizations). 180s 180s 2.11.7. Executing OPT_CLEAN pass (remove unused cells and wires). 180s Finding unused cells or wires in module \top.. 180s 180s 2.11.8. Executing OPT_EXPR pass (perform const folding). 180s Optimizing module top. 180s 180s 2.11.9. Finished OPT passes. (There is nothing left to do.) 180s 180s 2.12. Executing FSM pass (extract and optimize FSM). 180s 180s 2.12.1. Executing FSM_DETECT pass (finding FSMs in design). 180s 180s 2.12.2. Executing FSM_EXTRACT pass (extracting FSM from design). 180s 180s 2.12.3. Executing FSM_OPT pass (simple optimizations of FSMs). 180s 180s 2.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). 180s Finding unused cells or wires in module \top.. 180s 180s 2.12.5. Executing FSM_OPT pass (simple optimizations of FSMs). 180s 180s 2.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 180s 180s 2.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 180s 180s 2.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 180s 180s 2.13. Executing OPT pass (performing simple optimizations). 180s 180s 2.13.1. Executing OPT_EXPR pass (perform const folding). 180s Optimizing module top. 180s 180s 2.13.2. Executing OPT_MERGE pass (detect identical cells). 180s Finding identical cells in module `\top'. 180s Removed a total of 0 cells. 180s 180s 2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 180s Running muxtree optimizer on module \top.. 180s Creating internal representation of mux trees. 180s No muxes found in this module. 180s Removed 0 multiplexer ports. 180s 180s 2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 180s Optimizing cells in module \top. 180s Performed a total of 0 changes. 180s 180s 2.13.5. Executing OPT_MERGE pass (detect identical cells). 180s Finding identical cells in module `\top'. 180s Removed a total of 0 cells. 180s 180s 2.13.6. Executing OPT_DFF pass (perform DFF optimizations). 180s 180s 2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). 180s Finding unused cells or wires in module \top.. 180s 180s 2.13.8. Executing OPT_EXPR pass (perform const folding). 180s Optimizing module top. 180s 180s 2.13.9. Finished OPT passes. (There is nothing left to do.) 180s 180s 2.14. Executing WREDUCE pass (reducing word size of cells). 180s Removed top 31 bits (of 32) from port B of cell top.$add$app3.v:12$382 ($add). 180s Removed top 10 bits (of 32) from port Y of cell top.$add$app3.v:12$382 ($add). 180s Removed top 3 bits (of 4) from port B of cell top.$add$app3.v:13$384 ($add). 180s Removed top 3 bits (of 4) from wire top.$logic_not$app3.v:13$383_Y. 180s 180s 2.15. Executing PEEPOPT pass (run peephole optimizers). 180s 180s 2.16. Executing OPT_CLEAN pass (remove unused cells and wires). 180s Finding unused cells or wires in module \top.. 180s Removed 0 unused cells and 2 unused wires. 180s 180s 180s 2.17. Executing SHARE pass (SAT-based resource sharing). 180s 180s 2.18. Executing TECHMAP pass (map to technology primitives). 180s 180s 2.18.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v 180s Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation. 180s Generating RTLIL representation for module `\_90_lut_cmp_'. 180s Successfully finished Verilog frontend. 180s 180s 2.18.2. Continuing TECHMAP pass. 180s No more expansions possible. 180s 180s 180s 2.19. Executing OPT_EXPR pass (perform const folding). 180s Optimizing module top. 180s 180s 2.20. Executing OPT_CLEAN pass (remove unused cells and wires). 180s Finding unused cells or wires in module \top.. 180s 180s 2.21. Executing ALUMACC pass (create $alu and $macc cells). 180s Extracting $alu and $macc cells in module top: 180s creating $macc model for $add$app3.v:12$382 ($add). 180s creating $macc model for $add$app3.v:13$384 ($add). 180s creating $alu model for $macc $add$app3.v:13$384. 180s creating $alu model for $macc $add$app3.v:12$382. 180s creating $alu cell for $add$app3.v:12$382: $auto$alumacc.cc:485:replace_alu$460 180s creating $alu cell for $add$app3.v:13$384: $auto$alumacc.cc:485:replace_alu$463 180s created 2 $alu and 0 $macc cells. 180s 180s 2.22. Executing OPT pass (performing simple optimizations). 180s 180s 2.22.1. Executing OPT_EXPR pass (perform const folding). 180s Optimizing module top. 180s 180s 2.22.2. Executing OPT_MERGE pass (detect identical cells). 180s Finding identical cells in module `\top'. 180s 180s Removed a total of 1 cells. 180s 180s 2.22.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 180s Running muxtree optimizer on module \top.. 180s Creating internal representation of mux trees. 180s No muxes found in this module. 180s Removed 0 multiplexer ports. 180s 180s 2.22.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 180s Optimizing cells in module \top. 180s Performed a total of 0 changes. 180s 180s 2.22.5. Executing OPT_MERGE pass (detect identical cells). 180s Finding identical cells in module `\top'. 180s Removed a total of 0 cells. 180s 180s 2.22.6. Executing OPT_DFF pass (perform DFF optimizations). 180s 180s 2.22.7. Executing OPT_CLEAN pass (remove unused cells and wires). 180s Finding unused cells or wires in module \top.. 180s Removed 0 unused cells and 1 unused wires. 180s 180s 180s 2.22.8. Executing OPT_EXPR pass (perform const folding). 180s Optimizing module top. 180s 180s 2.22.9. Rerunning OPT passes. (Maybe there is more to do..) 180s 180s 2.22.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 180s Running muxtree optimizer on module \top.. 180s Creating internal representation of mux trees. 180s No muxes found in this module. 180s Removed 0 multiplexer ports. 180s 180s 2.22.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 180s Optimizing cells in module \top. 180s Performed a total of 0 changes. 180s 180s 2.22.12. Executing OPT_MERGE pass (detect identical cells). 180s Finding identical cells in module `\top'. 180s Removed a total of 0 cells. 180s 180s 2.22.13. Executing OPT_DFF pass (perform DFF optimizations). 180s 180s 2.22.14. Executing OPT_CLEAN pass (remove unused cells and wires). 180s Finding unused cells or wires in module \top.. 180s 180s 2.22.15. Executing OPT_EXPR pass (perform const folding). 180s Optimizing module top. 180s 180s 2.22.16. Finished OPT passes. (There is nothing left to do.) 180s 180s 2.23. Executing MEMORY pass. 180s 180s 2.23.1. Executing OPT_MEM pass (optimize memories). 180s Performed a total of 0 transformations. 180s 180s 2.23.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). 180s Performed a total of 0 transformations. 180s 180s 2.23.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 180s 180s 2.23.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 180s 180s 2.23.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 180s 180s 2.23.6. Executing OPT_CLEAN pass (remove unused cells and wires). 180s Finding unused cells or wires in module \top.. 180s 180s 2.23.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 180s 180s 2.23.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). 180s Performed a total of 0 transformations. 180s 180s 2.23.9. Executing OPT_CLEAN pass (remove unused cells and wires). 180s Finding unused cells or wires in module \top.. 180s 180s 2.23.10. Executing MEMORY_COLLECT pass (generating $mem cells). 180s 180s 2.24. Executing OPT_CLEAN pass (remove unused cells and wires). 180s Finding unused cells or wires in module \top.. 180s 180s 2.25. Executing MEMORY_LIBMAP pass (mapping memories to cells). 180s 180s 2.26. Executing TECHMAP pass (map to technology primitives). 180s 180s 2.26.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v 180s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation. 180s Generating RTLIL representation for module `\$__ICE40_RAM4K_'. 180s Successfully finished Verilog frontend. 180s 180s 2.26.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/spram_map.v 180s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/spram_map.v' to AST representation. 180s Generating RTLIL representation for module `\$__ICE40_SPRAM_'. 180s Successfully finished Verilog frontend. 180s 180s 2.26.3. Continuing TECHMAP pass. 180s No more expansions possible. 180s 180s 180s 2.27. Executing ICE40_BRAMINIT pass. 180s 180s 2.28. Executing OPT pass (performing simple optimizations). 180s 180s 2.28.1. Executing OPT_EXPR pass (perform const folding). 180s Optimizing module top. 180s 180s 2.28.2. Executing OPT_MERGE pass (detect identical cells). 180s Finding identical cells in module `\top'. 180s Removed a total of 0 cells. 180s 180s 2.28.3. Executing OPT_DFF pass (perform DFF optimizations). 180s 180s 2.28.4. Executing OPT_CLEAN pass (remove unused cells and wires). 180s Finding unused cells or wires in module \top.. 180s 180s 2.28.5. Finished fast OPT passes. 180s 180s 2.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 180s 180s 2.30. Executing OPT pass (performing simple optimizations). 180s 180s 2.30.1. Executing OPT_EXPR pass (perform const folding). 180s Optimizing module top. 180s 180s 2.30.2. Executing OPT_MERGE pass (detect identical cells). 180s Finding identical cells in module `\top'. 180s Removed a total of 0 cells. 180s 180s 2.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 180s Running muxtree optimizer on module \top.. 180s Creating internal representation of mux trees. 180s No muxes found in this module. 180s Removed 0 multiplexer ports. 180s 180s 2.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 180s Optimizing cells in module \top. 180s Performed a total of 0 changes. 180s 180s 2.30.5. Executing OPT_MERGE pass (detect identical cells). 180s Finding identical cells in module `\top'. 180s Removed a total of 0 cells. 180s 180s 2.30.6. Executing OPT_DFF pass (perform DFF optimizations). 180s 180s 2.30.7. Executing OPT_CLEAN pass (remove unused cells and wires). 180s Finding unused cells or wires in module \top.. 180s 180s 2.30.8. Executing OPT_EXPR pass (perform const folding). 180s Optimizing module top. 180s 180s 2.30.9. Finished OPT passes. (There is nothing left to do.) 180s 180s 2.31. Executing ICE40_WRAPCARRY pass (wrap carries). 180s 180s 2.32. Executing TECHMAP pass (map to technology primitives). 180s 180s 2.32.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v 180s Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation. 180s Generating RTLIL representation for module `\_90_simplemap_bool_ops'. 180s Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. 180s Generating RTLIL representation for module `\_90_simplemap_logic_ops'. 180s Generating RTLIL representation for module `\_90_simplemap_compare_ops'. 180s Generating RTLIL representation for module `\_90_simplemap_various'. 180s Generating RTLIL representation for module `\_90_simplemap_registers'. 180s Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. 180s Generating RTLIL representation for module `\_90_shift_shiftx'. 180s Generating RTLIL representation for module `\_90_fa'. 180s Generating RTLIL representation for module `\_90_lcu'. 180s Generating RTLIL representation for module `\_90_alu'. 180s Generating RTLIL representation for module `\_90_macc'. 180s Generating RTLIL representation for module `\_90_alumacc'. 180s Generating RTLIL representation for module `\$__div_mod_u'. 180s Generating RTLIL representation for module `\$__div_mod_trunc'. 180s Generating RTLIL representation for module `\_90_div'. 180s Generating RTLIL representation for module `\_90_mod'. 180s Generating RTLIL representation for module `\$__div_mod_floor'. 180s Generating RTLIL representation for module `\_90_divfloor'. 180s Generating RTLIL representation for module `\_90_modfloor'. 180s Generating RTLIL representation for module `\_90_pow'. 180s Generating RTLIL representation for module `\_90_pmux'. 180s Generating RTLIL representation for module `\_90_demux'. 180s Generating RTLIL representation for module `\_90_lut'. 180s Successfully finished Verilog frontend. 180s 180s 2.32.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v 180s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation. 180s Generating RTLIL representation for module `\_80_ice40_alu'. 180s Successfully finished Verilog frontend. 180s 180s 2.32.3. Continuing TECHMAP pass. 180s Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_80_ice40_alu for cells of type $alu. 180s Using extmapper simplemap for cells of type $logic_not. 180s Using template $paramod$080e6a70eb8bfa1ccf22d9718e795074645029a4\_80_ice40_alu for cells of type $alu. 180s Using extmapper simplemap for cells of type $xor. 180s Using extmapper simplemap for cells of type $reduce_and. 180s Using extmapper simplemap for cells of type $dff. 180s Using extmapper simplemap for cells of type $mux. 180s Using extmapper simplemap for cells of type $not. 180s Using extmapper simplemap for cells of type $pos. 180s No more expansions possible. 180s 180s 180s 2.33. Executing OPT pass (performing simple optimizations). 180s 180s 2.33.1. Executing OPT_EXPR pass (perform const folding). 180s Optimizing module top. 180s 180s 180s 2.33.2. Executing OPT_MERGE pass (detect identical cells). 180s Finding identical cells in module `\top'. 180s 180s Removed a total of 1 cells. 180s 180s 2.33.3. Executing OPT_DFF pass (perform DFF optimizations). 180s 180s 2.33.4. Executing OPT_CLEAN pass (remove unused cells and wires). 180s Finding unused cells or wires in module \top.. 180s Removed 27 unused cells and 34 unused wires. 180s 180s 180s 2.33.5. Finished fast OPT passes. 180s 180s 2.34. Executing ICE40_OPT pass (performing simple optimizations). 180s 180s 2.34.1. Running ICE40 specific optimizations. 180s Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$460.slice[0].carry: CO=\counter [0] 180s 180s 2.34.2. Executing OPT_EXPR pass (perform const folding). 180s Optimizing module top. 180s 180s 2.34.3. Executing OPT_MERGE pass (detect identical cells). 180s Finding identical cells in module `\top'. 180s Removed a total of 0 cells. 180s 180s 2.34.4. Executing OPT_DFF pass (perform DFF optimizations). 180s 180s 2.34.5. Executing OPT_CLEAN pass (remove unused cells and wires). 180s Finding unused cells or wires in module \top.. 180s 180s 2.34.6. Rerunning OPT passes. (Removed registers in this run.) 180s 180s 2.34.7. Running ICE40 specific optimizations. 180s 180s 2.34.8. Executing OPT_EXPR pass (perform const folding). 180s Optimizing module top. 180s 180s 2.34.9. Executing OPT_MERGE pass (detect identical cells). 180s Finding identical cells in module `\top'. 180s Removed a total of 0 cells. 180s 180s 2.34.10. Executing OPT_DFF pass (perform DFF optimizations). 180s 180s 2.34.11. Executing OPT_CLEAN pass (remove unused cells and wires). 180s Finding unused cells or wires in module \top.. 180s 180s 2.34.12. Finished OPT passes. (There is nothing left to do.) 180s 180s 2.35. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 180s 180s 2.36. Executing TECHMAP pass (map to technology primitives). 180s 180s 2.36.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 180s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 180s Generating RTLIL representation for module `\$_DFF_N_'. 180s Generating RTLIL representation for module `\$_DFF_P_'. 180s Generating RTLIL representation for module `\$_DFFE_NP_'. 180s Generating RTLIL representation for module `\$_DFFE_PP_'. 180s Generating RTLIL representation for module `\$_DFF_NP0_'. 180s Generating RTLIL representation for module `\$_DFF_NP1_'. 180s Generating RTLIL representation for module `\$_DFF_PP0_'. 180s Generating RTLIL representation for module `\$_DFF_PP1_'. 180s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 180s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 180s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 180s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 180s Generating RTLIL representation for module `\$_SDFF_NP0_'. 180s Generating RTLIL representation for module `\$_SDFF_NP1_'. 180s Generating RTLIL representation for module `\$_SDFF_PP0_'. 180s Generating RTLIL representation for module `\$_SDFF_PP1_'. 180s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 180s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 180s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 180s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 180s Successfully finished Verilog frontend. 180s 180s 2.36.2. Continuing TECHMAP pass. 180s Using template \$_DFF_P_ for cells of type $_DFF_P_. 180s No more expansions possible. 180s 180s 180s 2.37. Executing OPT_EXPR pass (perform const folding). 180s Optimizing module top. 180s 180s 2.38. Executing SIMPLEMAP pass (map simple cells to gate primitives). 180s Mapping top.$auto$alumacc.cc:485:replace_alu$460.slice[0].carry ($lut). 180s 180s 2.39. Executing ICE40_OPT pass (performing simple optimizations). 180s 180s 2.39.1. Running ICE40 specific optimizations. 180s 180s 2.39.2. Executing OPT_EXPR pass (perform const folding). 180s Optimizing module top. 180s 180s 180s 2.39.3. Executing OPT_MERGE pass (detect identical cells). 180s Finding identical cells in module `\top'. 180s Removed a total of 0 cells. 180s 180s 2.39.4. Executing OPT_DFF pass (perform DFF optimizations). 180s 180s 2.39.5. Executing OPT_CLEAN pass (remove unused cells and wires). 180s Finding unused cells or wires in module \top.. 180s Removed 0 unused cells and 112 unused wires. 180s 180s 180s 2.39.6. Rerunning OPT passes. (Removed registers in this run.) 180s 180s 2.39.7. Running ICE40 specific optimizations. 180s 180s 2.39.8. Executing OPT_EXPR pass (perform const folding). 180s Optimizing module top. 180s 180s 2.39.9. Executing OPT_MERGE pass (detect identical cells). 180s Finding identical cells in module `\top'. 180s Removed a total of 0 cells. 180s 180s 2.39.10. Executing OPT_DFF pass (perform DFF optimizations). 180s 180s 2.39.11. Executing OPT_CLEAN pass (remove unused cells and wires). 180s Finding unused cells or wires in module \top.. 180s 180s 2.39.12. Finished OPT passes. (There is nothing left to do.) 180s 180s 2.40. Executing TECHMAP pass (map to technology primitives). 180s 180s 2.40.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v 180s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation. 180s Generating RTLIL representation for module `\$_DLATCH_N_'. 180s Generating RTLIL representation for module `\$_DLATCH_P_'. 180s Successfully finished Verilog frontend. 180s 180s 2.40.2. Continuing TECHMAP pass. 180s No more expansions possible. 180s 180s 180s 2.41. Executing ABC pass (technology mapping using ABC). 180s 180s 2.41.1. Extracting gate netlist of module `\top' to `/input.blif'.. 180s Extracted 27 gates and 54 wires to a netlist network with 27 inputs and 4 outputs. 180s 180s 2.41.1.1. Executing ABC. 180s Running ABC command: "berkeley-abc" -s -f /abc.script 2>&1 180s ABC: ABC command line: "source /abc.script". 180s ABC: 180s ABC: + read_blif /input.blif 180s ABC: + read_lut /lutdefs.txt 180s ABC: + strash 180s ABC: + &get -n 180s ABC: + &fraig -x 180s ABC: + &put 180s ABC: + scorr 180s ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). 180s ABC: + dc2 180s ABC: + dretime 180s ABC: + strash 180s ABC: + dch -f 180s ABC: + if 180s ABC: + mfs2 180s ABC: + lutpack -S 1 180s ABC: + dress /input.blif 180s ABC: Total number of equiv classes = 5. 180s ABC: Participating nodes from both networks = 9. 180s ABC: Participating nodes from the first network = 4. ( 30.77 % of nodes) 180s ABC: Participating nodes from the second network = 5. ( 38.46 % of nodes) 180s ABC: Node pairs (any polarity) = 4. ( 30.77 % of names can be moved) 180s ABC: Node pairs (same polarity) = 4. ( 30.77 % of names can be moved) 180s ABC: Total runtime = 0.06 sec 180s ABC: + write_blif /output.blif 180s 180s 2.41.1.2. Re-integrating ABC results. 180s ABC RESULTS: $lut cells: 12 180s ABC RESULTS: internal signals: 23 180s ABC RESULTS: input signals: 27 180s ABC RESULTS: output signals: 4 180s Removing temp directory. 180s 180s 2.42. Executing ICE40_WRAPCARRY pass (wrap carries). 180s 180s 2.43. Executing TECHMAP pass (map to technology primitives). 180s 180s 2.43.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 180s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 180s Generating RTLIL representation for module `\$_DFF_N_'. 180s Generating RTLIL representation for module `\$_DFF_P_'. 180s Generating RTLIL representation for module `\$_DFFE_NP_'. 180s Generating RTLIL representation for module `\$_DFFE_PP_'. 180s Generating RTLIL representation for module `\$_DFF_NP0_'. 180s Generating RTLIL representation for module `\$_DFF_NP1_'. 180s Generating RTLIL representation for module `\$_DFF_PP0_'. 180s Generating RTLIL representation for module `\$_DFF_PP1_'. 180s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 180s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 180s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 180s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 180s Generating RTLIL representation for module `\$_SDFF_NP0_'. 180s Generating RTLIL representation for module `\$_SDFF_NP1_'. 180s Generating RTLIL representation for module `\$_SDFF_PP0_'. 180s Generating RTLIL representation for module `\$_SDFF_PP1_'. 180s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 180s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 180s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 180s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 180s Successfully finished Verilog frontend. 180s 180s 2.43.2. Continuing TECHMAP pass. 180s No more expansions possible. 180s 180s Removed 2 unused cells and 39 unused wires. 180s 180s 2.44. Executing OPT_LUT pass (optimize LUTs). 180s Discovering LUTs. 180s Number of LUTs: 37 180s 1-LUT 1 180s 2-LUT 4 180s 3-LUT 25 180s 4-LUT 7 180s with \SB_CARRY (#0) 23 180s with \SB_CARRY (#1) 23 180s 180s Eliminating LUTs. 180s Number of LUTs: 37 180s 1-LUT 1 180s 2-LUT 4 180s 3-LUT 25 180s 4-LUT 7 180s with \SB_CARRY (#0) 23 180s with \SB_CARRY (#1) 23 180s 180s Combining LUTs. 180s Number of LUTs: 37 180s 1-LUT 1 180s 2-LUT 4 180s 3-LUT 25 180s 4-LUT 7 180s with \SB_CARRY (#0) 23 180s with \SB_CARRY (#1) 23 180s 180s Eliminated 0 LUTs. 180s Combined 0 LUTs. 180s 180s 180s 2.45. Executing TECHMAP pass (map to technology primitives). 180s 180s 2.45.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v 180s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation. 180s Generating RTLIL representation for module `\$lut'. 180s Successfully finished Verilog frontend. 180s 180s 2.45.2. Continuing TECHMAP pass. 180s Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut. 180s Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut. 180s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut. 180s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. 180s Using template $paramod$415b9dd3a15783ae56c103f189fd8e182f997441\$lut for cells of type $lut. 180s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. 180s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. 180s Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut. 180s No more expansions possible. 180s 180s Removed 0 unused cells and 78 unused wires. 180s 180s 2.46. Executing AUTONAME pass. 180s Renamed 463 objects in module top (10 iterations). 180s 180s 180s 2.47. Executing HIERARCHY pass (managing design hierarchy). 180s 180s 2.47.1. Analyzing design hierarchy.. 180s Top module: \top 180s 180s 2.47.2. Analyzing design hierarchy.. 180s Top module: \top 180s Removed 0 unused modules. 180s 180s 2.48. Printing statistics. 180s 180s === top === 180s 180s Number of wires: 20 180s Number of wire bits: 99 180s Number of public wires: 20 180s Number of public wire bits: 99 180s Number of memories: 0 180s Number of memory bits: 0 180s Number of processes: 0 180s Number of cells: 88 180s SB_CARRY 23 180s SB_DFF 27 180s SB_LUT4 37 180s SB_WARMBOOT 1 180s 180s 2.49. Executing CHECK pass (checking for obvious problems). 180s Checking module top... 180s Found and reported 0 problems. 180s 180s 2.50. Executing JSON backend. 180s 180s End of script. Logfile hash: 71eee7a71b, CPU: user 0.69s system 0.00s, MEM: 20.00 MB peak 180s Yosys 0.23 (git sha1 7ce5011c24b) 180s Time spent: 53% 13x read_verilog (0 sec), 19% 1x abc (0 sec), ... 180s nextpnr-ice40 --hx1k --package tq144 --asc app3.asc --pcf icestick.pcf --json app3.json 180s Warning: unmatched constraint 'RX' (on line 4) 180s Warning: unmatched constraint 'TX' (on line 5) 180s Info: constrained 'LED1' to bel 'X13/Y12/io1' 180s Info: constrained 'LED2' to bel 'X13/Y12/io0' 180s Info: constrained 'LED3' to bel 'X13/Y11/io1' 180s Info: constrained 'LED4' to bel 'X13/Y11/io0' 180s Info: constrained 'LED5' to bel 'X13/Y9/io1' 180s Info: constrained 'clk' to bel 'X0/Y8/io1' 180s 180s Info: Packing constants.. 180s Info: Packing IOs.. 180s Info: Packing LUT-FFs.. 180s Info: 10 LCs used as LUT4 only 180s Info: 27 LCs used as LUT4 and DFF 180s Info: Packing non-LUT FFs.. 180s Info: 0 LCs used as DFF only 180s Info: Packing carries.. 180s Info: 0 LCs used as CARRY only 180s Info: Packing indirect carry+LUT pairs... 180s Info: 0 LUTs merged into carry LCs 180s Info: Packing RAMs.. 180s Info: Placing PLLs.. 180s Info: Packing special functions.. 180s Info: Packing PLLs.. 180s Info: Promoting globals.. 180s Info: promoting clk$SB_IO_IN (fanout 27) 180s Info: Constraining chains... 180s Info: 1 LCs used to legalise carry chains. 180s Info: Checksum: 0x3e0450db 180s 180s Info: Annotating ports with timing budgets for target frequency 12.00 MHz 180s Info: Checksum: 0x98381def 180s 180s Info: Device utilisation: 180s Info: ICESTORM_LC: 40/ 1280 3% 180s Info: ICESTORM_RAM: 0/ 16 0% 180s Info: SB_IO: 6/ 112 5% 180s Info: SB_GB: 1/ 8 12% 180s Info: ICESTORM_PLL: 0/ 1 0% 180s Info: SB_WARMBOOT: 1/ 1 100% 180s 180s Info: Placed 6 cells based on constraints. 180s Info: Creating initial analytic placement for 18 cells, random placement wirelen = 338. 180s Info: at initial placer iter 0, wirelen = 17 180s Info: at initial placer iter 1, wirelen = 32 180s Info: at initial placer iter 2, wirelen = 12 180s Info: at initial placer iter 3, wirelen = 12 180s Info: Running main analytical placer, max placement attempts per cell = 10000. 180s Info: at iteration #1, type ICESTORM_LC: wirelen solved = 21, spread = 63, legal = 85; time = 0.00s 180s Info: at iteration #1, type SB_GB: wirelen solved = 85, spread = 85, legal = 85; time = 0.00s 180s Info: at iteration #1, type SB_WARMBOOT: wirelen solved = 84, spread = 84, legal = 130; time = 0.00s 180s Info: at iteration #1, type ALL: wirelen solved = 32, spread = 79, legal = 135; time = 0.00s 180s Info: at iteration #2, type ICESTORM_LC: wirelen solved = 65, spread = 111, legal = 121; time = 0.00s 180s Info: at iteration #2, type SB_GB: wirelen solved = 121, spread = 121, legal = 121; time = 0.00s 180s Info: at iteration #2, type SB_WARMBOOT: wirelen solved = 89, spread = 89, legal = 121; time = 0.00s 181s Info: at iteration #2, type ALL: wirelen solved = 16, spread = 58, legal = 104; time = 0.00s 181s Info: at iteration #3, type ICESTORM_LC: wirelen solved = 62, spread = 101, legal = 106; time = 0.00s 181s Info: at iteration #3, type SB_GB: wirelen solved = 106, spread = 106, legal = 106; time = 0.00s 181s Info: at iteration #3, type SB_WARMBOOT: wirelen solved = 66, spread = 66, legal = 106; time = 0.00s 181s Info: at iteration #3, type ALL: wirelen solved = 18, spread = 61, legal = 105; time = 0.00s 181s Info: at iteration #4, type ICESTORM_LC: wirelen solved = 63, spread = 99, legal = 109; time = 0.00s 181s Info: at iteration #4, type SB_GB: wirelen solved = 109, spread = 109, legal = 109; time = 0.00s 181s Info: at iteration #4, type SB_WARMBOOT: wirelen solved = 69, spread = 69, legal = 109; time = 0.00s 181s Info: at iteration #4, type ALL: wirelen solved = 24, spread = 61, legal = 105; time = 0.00s 181s Info: at iteration #5, type ICESTORM_LC: wirelen solved = 65, spread = 101, legal = 111; time = 0.00s 181s Info: at iteration #5, type SB_GB: wirelen solved = 111, spread = 111, legal = 111; time = 0.00s 181s Info: at iteration #5, type SB_WARMBOOT: wirelen solved = 71, spread = 71, legal = 111; time = 0.00s 181s Info: at iteration #5, type ALL: wirelen solved = 20, spread = 67, legal = 107; time = 0.00s 181s Info: at iteration #6, type ICESTORM_LC: wirelen solved = 64, spread = 102, legal = 107; time = 0.00s 181s Info: at iteration #6, type SB_GB: wirelen solved = 107, spread = 107, legal = 107; time = 0.00s 181s Info: at iteration #6, type SB_WARMBOOT: wirelen solved = 69, spread = 69, legal = 107; time = 0.00s 181s Info: at iteration #6, type ALL: wirelen solved = 34, spread = 67, legal = 107; time = 0.00s 181s Info: at iteration #7, type ICESTORM_LC: wirelen solved = 64, spread = 102, legal = 112; time = 0.00s 181s Info: at iteration #7, type SB_GB: wirelen solved = 112, spread = 112, legal = 112; time = 0.00s 181s Info: at iteration #7, type SB_WARMBOOT: wirelen solved = 74, spread = 74, legal = 112; time = 0.00s 181s Info: at iteration #7, type ALL: wirelen solved = 29, spread = 71, legal = 109; time = 0.00s 181s Info: HeAP Placer Time: 0.02s 181s Info: of which solving equations: 0.01s 181s Info: of which spreading cells: 0.00s 181s Info: of which strict legalisation: 0.00s 181s 181s Info: Running simulated annealing placer for refinement. 181s Info: at iteration #1: temp = 0.000000, timing cost = 15, wirelen = 104 181s Info: at iteration #5: temp = 0.000000, timing cost = 17, wirelen = 78 181s Info: at iteration #10: temp = 0.000000, timing cost = 17, wirelen = 77 181s Info: at iteration #11: temp = 0.000000, timing cost = 17, wirelen = 76 181s Info: SA placement time 0.01s 181s 181s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 171.64 MHz (PASS at 12.00 MHz) 181s 181s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> : 3.87 ns 181s 181s Info: Slack histogram: 181s Info: legend: * represents 1 endpoint(s) 181s Info: + represents [1,1) endpoint(s) 181s Info: [ 77507, 77742) |** 181s Info: [ 77742, 77977) |* 181s Info: [ 77977, 78212) |* 181s Info: [ 78212, 78447) |* 181s Info: [ 78447, 78682) |** 181s Info: [ 78682, 78917) |*** 181s Info: [ 78917, 79152) | 181s Info: [ 79152, 79387) |* 181s Info: [ 79387, 79622) |*** 181s Info: [ 79622, 79857) |***** 181s Info: [ 79857, 80092) |* 181s Info: [ 80092, 80327) |** 181s Info: [ 80327, 80562) | 181s Info: [ 80562, 80797) |** 181s Info: [ 80797, 81032) |** 181s Info: [ 81032, 81267) |** 181s Info: [ 81267, 81502) | 181s Info: [ 81502, 81737) | 181s Info: [ 81737, 81972) |**************************** 181s Info: [ 81972, 82207) |* 181s Info: Checksum: 0x08af44c7 181s 181s Info: Routing.. 181s Info: Setting up routing queue. 181s Info: Routing 127 arcs. 181s Info: | (re-)routed arcs | delta | remaining| time spent | 181s Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| 181s Info: 130 | 3 107 | 3 107 | 0| 0.01 0.01| 181s Info: Routing complete. 181s Info: Router1 time 0.01s 181s Info: Checksum: 0x1e7813fd 181s 181s Info: Critical path report for clock 'clk$SB_IO_IN_$glb_clk' (posedge -> posedge): 181s Info: curr total 181s Info: 0.5 0.5 Source counter_SB_LUT4_I2_3_LC.O 181s Info: 0.6 1.1 Net counter[6] budget 20.292999 ns (11,9) -> (12,10) 181s Info: Sink state_SB_LUT4_I3_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_LC.I0 181s Info: Defined in: 181s Info: app3.v:7.22-7.29 181s Info: 0.4 1.6 Source state_SB_LUT4_I3_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_LC.O 181s Info: 0.6 2.2 Net state_SB_LUT4_I3_I0_SB_LUT4_O_1_I2[0] budget 20.292999 ns (12,10) -> (12,10) 181s Info: Sink state_SB_LUT4_I3_I0_SB_LUT4_O_1_LC.I2 181s Info: Defined in: 181s Info: /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 181s Info: 0.4 2.5 Source state_SB_LUT4_I3_I0_SB_LUT4_O_1_LC.O 181s Info: 0.6 3.1 Net state_SB_LUT4_I3_I0[1] budget 20.292000 ns (12,10) -> (12,10) 181s Info: Sink counter2_SB_LUT4_I2_3_I1_SB_LUT4_O_LC.I2 181s Info: Defined in: 181s Info: /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 181s Info: 0.4 3.5 Source counter2_SB_LUT4_I2_3_I1_SB_LUT4_O_LC.O 181s Info: 0.9 4.4 Net counter2_SB_LUT4_I2_3_I1 budget 20.292000 ns (12,10) -> (9,10) 181s Info: Sink counter2_SB_LUT4_I2_3_LC.I1 181s Info: Defined in: 181s Info: app3.v:13.15-13.34 181s Info: /usr/bin/../share/yosys/ice40/arith_map.v:29.22-29.23 181s Info: 0.3 4.7 Source counter2_SB_LUT4_I2_3_LC.COUT 181s Info: 0.0 4.7 Net counter2_SB_CARRY_I1_CO[1] budget 0.000000 ns (9,10) -> (9,10) 181s Info: Sink counter2_SB_LUT4_I2_2_LC.CIN 181s Info: Defined in: 181s Info: app3.v:13.15-13.34 181s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 181s Info: 0.1 4.8 Source counter2_SB_LUT4_I2_2_LC.COUT 181s Info: 0.0 4.8 Net counter2_SB_CARRY_I1_CO[2] budget 0.000000 ns (9,10) -> (9,10) 181s Info: Sink counter2_SB_LUT4_I2_1_LC.CIN 181s Info: Defined in: 181s Info: app3.v:13.15-13.34 181s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 181s Info: 0.1 4.9 Source counter2_SB_LUT4_I2_1_LC.COUT 181s Info: 0.3 5.2 Net counter2_SB_CARRY_I1_CO[3] budget 0.260000 ns (9,10) -> (9,10) 181s Info: Sink counter2_SB_LUT4_I2_LC.I3 181s Info: Defined in: 181s Info: app3.v:13.15-13.34 181s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 181s Info: 0.3 5.5 Setup counter2_SB_LUT4_I2_LC.I3 181s Info: 2.6 ns logic, 2.9 ns routing 181s 181s Info: Critical path report for cross-domain path 'posedge clk$SB_IO_IN_$glb_clk' -> '': 181s Info: curr total 181s Info: 0.5 0.5 Source counter2_SB_LUT4_I2_3_LC.O 181s Info: 0.6 1.1 Net counter2[0] budget 41.173000 ns (9,10) -> (9,10) 181s Info: Sink WB_BOOT_SB_LUT4_O_LC.I0 181s Info: Defined in: 181s Info: app3.v:8.12-8.20 181s Info: 0.4 1.6 Source WB_BOOT_SB_LUT4_O_LC.O 181s Info: 2.1 3.6 Net WB_BOOT budget 41.172001 ns (9,10) -> (0,0) 181s Info: Sink WB.BOOT 181s Info: Defined in: 181s Info: app3.v:24.9-24.18 181s Info: 1.0 ns logic, 2.7 ns routing 181s 181s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 181.26 MHz (PASS at 12.00 MHz) 181s 181s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> : 3.65 ns 181s 181s Info: Slack histogram: 181s Info: legend: * represents 1 endpoint(s) 181s Info: + represents [1,1) endpoint(s) 181s Info: [ 77816, 78036) |** 181s Info: [ 78036, 78256) |* 181s Info: [ 78256, 78476) |* 181s Info: [ 78476, 78696) |*** 181s Info: [ 78696, 78916) |* 181s Info: [ 78916, 79136) |** 181s Info: [ 79136, 79356) | 181s Info: [ 79356, 79576) |** 181s Info: [ 79576, 79796) |**** 181s Info: [ 79796, 80016) |*** 181s Info: [ 80016, 80236) |*** 181s Info: [ 80236, 80456) | 181s Info: [ 80456, 80676) |* 181s Info: [ 80676, 80896) |** 181s Info: [ 80896, 81116) |** 181s Info: [ 81116, 81336) |* 181s Info: [ 81336, 81556) | 181s Info: [ 81556, 81776) | 181s Info: [ 81776, 81996) |**************************** 181s Info: [ 81996, 82216) |* 181s 2 warnings, 0 errors 181s 181s Info: Program finished normally. 181s icetime -d hx1k -c 25 app3.asc 181s // Reading input .asc file.. 181s // Reading 1k chipdb file.. 181s // Creating timing netlist.. 181s // Timing estimate: 5.65 ns (176.85 MHz) 181s // Checking 40.00 ns (25.00 MHz) clock constraint: PASSED. 181s icepack app3.asc app3.bin 181s icemulti -v -A16 -p0 -o config.bin app0.bin app1.bin app2.bin app3.bin 181s Place image 0 at 010000 .. 020000 (`app0.bin') 181s Place image 1 at 020000 .. 030000 (`app1.bin') 181s Place image 2 at 030000 .. 040000 (`app2.bin') 181s Place image 3 at 040000 .. 050000 (`app3.bin') 181s make: Leaving directory '/tmp/autopkgtest.rlxjW8/build.dCN/src/examples/icemulti' 181s make: Entering directory '/tmp/autopkgtest.rlxjW8/build.dCN/src/examples/icestick' 181s yosys -p 'synth_ice40 -top top -json example.json' example.v 181s 181s /----------------------------------------------------------------------------\ 181s | | 181s | yosys -- Yosys Open SYnthesis Suite | 181s | | 181s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 181s | | 181s | Permission to use, copy, modify, and/or distribute this software for any | 181s | purpose with or without fee is hereby granted, provided that the above | 181s | copyright notice and this permission notice appear in all copies. | 181s | | 181s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 181s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 181s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 181s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 181s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 181s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 181s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 181s | | 181s \----------------------------------------------------------------------------/ 181s 181s Yosys 0.23 (git sha1 7ce5011c24b) 181s 181s 181s -- Parsing `example.v' using frontend ` -vlog2k' -- 181s 181s 1. Executing Verilog-2005 frontend: example.v 181s Parsing Verilog input from `example.v' to AST representation. 181s Storing AST representation for module `$abstract\top'. 181s Successfully finished Verilog frontend. 181s 181s -- Running command `synth_ice40 -top top -json example.json' -- 181s 181s 2. Executing SYNTH_ICE40 pass. 181s 181s 2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v 181s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation. 181s Generating RTLIL representation for module `\SB_IO'. 181s Generating RTLIL representation for module `\SB_GB_IO'. 181s Generating RTLIL representation for module `\SB_GB'. 181s Generating RTLIL representation for module `\SB_LUT4'. 181s Generating RTLIL representation for module `\SB_CARRY'. 181s Generating RTLIL representation for module `\SB_DFF'. 181s Generating RTLIL representation for module `\SB_DFFE'. 181s Generating RTLIL representation for module `\SB_DFFSR'. 181s Generating RTLIL representation for module `\SB_DFFR'. 181s Generating RTLIL representation for module `\SB_DFFSS'. 181s Generating RTLIL representation for module `\SB_DFFS'. 181s Generating RTLIL representation for module `\SB_DFFESR'. 181s Generating RTLIL representation for module `\SB_DFFER'. 181s Generating RTLIL representation for module `\SB_DFFESS'. 181s Generating RTLIL representation for module `\SB_DFFES'. 181s Generating RTLIL representation for module `\SB_DFFN'. 181s Generating RTLIL representation for module `\SB_DFFNE'. 181s Generating RTLIL representation for module `\SB_DFFNSR'. 181s Generating RTLIL representation for module `\SB_DFFNR'. 181s Generating RTLIL representation for module `\SB_DFFNSS'. 181s Generating RTLIL representation for module `\SB_DFFNS'. 181s Generating RTLIL representation for module `\SB_DFFNESR'. 181s Generating RTLIL representation for module `\SB_DFFNER'. 181s Generating RTLIL representation for module `\SB_DFFNESS'. 181s Generating RTLIL representation for module `\SB_DFFNES'. 181s Generating RTLIL representation for module `\SB_RAM40_4K'. 181s Generating RTLIL representation for module `\SB_RAM40_4KNR'. 181s Generating RTLIL representation for module `\SB_RAM40_4KNW'. 181s Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. 181s Generating RTLIL representation for module `\ICESTORM_LC'. 181s Generating RTLIL representation for module `\SB_PLL40_CORE'. 181s Generating RTLIL representation for module `\SB_PLL40_PAD'. 181s Generating RTLIL representation for module `\SB_PLL40_2_PAD'. 181s Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. 181s Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. 181s Generating RTLIL representation for module `\SB_WARMBOOT'. 181s Generating RTLIL representation for module `\SB_SPRAM256KA'. 181s Generating RTLIL representation for module `\SB_HFOSC'. 181s Generating RTLIL representation for module `\SB_LFOSC'. 181s Generating RTLIL representation for module `\SB_RGBA_DRV'. 181s Generating RTLIL representation for module `\SB_LED_DRV_CUR'. 181s Generating RTLIL representation for module `\SB_RGB_DRV'. 181s Generating RTLIL representation for module `\SB_I2C'. 181s Generating RTLIL representation for module `\SB_SPI'. 181s Generating RTLIL representation for module `\SB_LEDDA_IP'. 181s Generating RTLIL representation for module `\SB_FILTER_50NS'. 181s Generating RTLIL representation for module `\SB_IO_I3C'. 181s Generating RTLIL representation for module `\SB_IO_OD'. 181s Generating RTLIL representation for module `\SB_MAC16'. 181s Generating RTLIL representation for module `\ICESTORM_RAM'. 181s Successfully finished Verilog frontend. 181s 181s 2.2. Executing HIERARCHY pass (managing design hierarchy). 181s 181s 2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\top'. 181s Generating RTLIL representation for module `\top'. 181s 181s 2.3.1. Analyzing design hierarchy.. 181s Top module: \top 181s 181s 2.3.2. Analyzing design hierarchy.. 181s Top module: \top 181s Removing unused module `$abstract\top'. 181s Removed 1 unused modules. 181s 181s 2.4. Executing PROC pass (convert processes to netlists). 181s 181s 2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 181s Cleaned up 0 empty switches. 181s 181s 2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 181s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241 in module SB_DFFNES. 181s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234 in module SB_DFFNESS. 181s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230 in module SB_DFFNER. 181s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223 in module SB_DFFNESR. 181s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220 in module SB_DFFNS. 181s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217 in module SB_DFFNSS. 181s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214 in module SB_DFFNR. 181s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211 in module SB_DFFNSR. 181s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203 in module SB_DFFES. 181s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196 in module SB_DFFESS. 181s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192 in module SB_DFFER. 181s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185 in module SB_DFFESR. 181s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182 in module SB_DFFS. 181s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179 in module SB_DFFSS. 181s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176 in module SB_DFFR. 181s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173 in module SB_DFFSR. 181s Removed a total of 0 dead cases. 181s 181s 2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 181s Removed 8 redundant assignments. 181s Promoted 25 assignments to connections. 181s 181s 2.4.4. Executing PROC_INIT pass (extract init attributes). 181s Found init rule in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 181s Set init value: \Q = 1'0 181s Found init rule in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 181s Set init value: \Q = 1'0 181s Found init rule in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 181s Set init value: \Q = 1'0 181s Found init rule in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 181s Set init value: \Q = 1'0 181s Found init rule in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 181s Set init value: \Q = 1'0 181s Found init rule in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 181s Set init value: \Q = 1'0 181s Found init rule in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 181s Set init value: \Q = 1'0 181s Found init rule in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 181s Set init value: \Q = 1'0 181s Found init rule in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 181s Set init value: \Q = 1'0 181s Found init rule in `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 181s Set init value: \Q = 1'0 181s Found init rule in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 181s Set init value: \Q = 1'0 181s Found init rule in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 181s Set init value: \Q = 1'0 181s Found init rule in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 181s Set init value: \Q = 1'0 181s Found init rule in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 181s Set init value: \Q = 1'0 181s Found init rule in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 181s Set init value: \Q = 1'0 181s Found init rule in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 181s Set init value: \Q = 1'0 181s Found init rule in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 181s Set init value: \Q = 1'0 181s Found init rule in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 181s Set init value: \Q = 1'0 181s Found init rule in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 181s Set init value: \Q = 1'0 181s Found init rule in `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 181s Set init value: \Q = 1'0 181s Found init rule in `\top.$proc$example.v:13$386'. 181s Set init value: \counter = 27'000000000000000000000000000 181s 181s 2.4.5. Executing PROC_ARST pass (detect async resets in processes). 181s Found async reset \S in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 181s Found async reset \R in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 181s Found async reset \S in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 181s Found async reset \R in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 181s Found async reset \S in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 181s Found async reset \R in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 181s Found async reset \S in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 181s Found async reset \R in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 181s 181s 2.4.6. Executing PROC_ROM pass (convert switches to ROMs). 181s Converted 0 switches. 181s 181s 181s 2.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 181s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 181s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 181s 1/1: $0\Q[0:0] 181s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 181s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 181s 1/1: $0\Q[0:0] 181s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 181s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 181s 1/1: $0\Q[0:0] 181s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 181s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 181s 1/1: $0\Q[0:0] 181s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 181s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 181s 1/1: $0\Q[0:0] 181s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 181s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 181s 1/1: $0\Q[0:0] 181s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 181s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 181s 1/1: $0\Q[0:0] 181s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 181s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 181s 1/1: $0\Q[0:0] 181s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 181s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 181s 1/1: $0\Q[0:0] 181s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 181s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 181s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 181s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 181s 1/1: $0\Q[0:0] 181s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 181s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 181s 1/1: $0\Q[0:0] 181s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 181s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 181s 1/1: $0\Q[0:0] 181s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 181s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 181s 1/1: $0\Q[0:0] 181s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 181s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 181s 1/1: $0\Q[0:0] 181s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 181s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 181s 1/1: $0\Q[0:0] 181s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 181s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 181s 1/1: $0\Q[0:0] 181s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 181s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 181s 1/1: $0\Q[0:0] 181s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 181s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 181s 1/1: $0\Q[0:0] 181s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 181s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 181s Creating decoders for process `\top.$proc$example.v:13$386'. 181s Creating decoders for process `\top.$proc$example.v:16$381'. 181s 181s 2.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). 181s 181s 2.4.9. Executing PROC_DFF pass (convert process syncs to FFs). 181s Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 181s created $adff cell `$procdff$431' with negative edge clock and positive level reset. 181s Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 181s created $dff cell `$procdff$432' with negative edge clock. 181s Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 181s created $adff cell `$procdff$433' with negative edge clock and positive level reset. 181s Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 181s created $dff cell `$procdff$434' with negative edge clock. 181s Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 181s created $adff cell `$procdff$435' with negative edge clock and positive level reset. 181s Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 181s created $dff cell `$procdff$436' with negative edge clock. 181s Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 181s created $adff cell `$procdff$437' with negative edge clock and positive level reset. 181s Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 181s created $dff cell `$procdff$438' with negative edge clock. 181s Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 181s created $dff cell `$procdff$439' with negative edge clock. 181s Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 181s created $dff cell `$procdff$440' with negative edge clock. 181s Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 181s created $adff cell `$procdff$441' with positive edge clock and positive level reset. 181s Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 181s created $dff cell `$procdff$442' with positive edge clock. 181s Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 181s created $adff cell `$procdff$443' with positive edge clock and positive level reset. 181s Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 181s created $dff cell `$procdff$444' with positive edge clock. 181s Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 181s created $adff cell `$procdff$445' with positive edge clock and positive level reset. 181s Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 181s created $dff cell `$procdff$446' with positive edge clock. 181s Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 181s created $adff cell `$procdff$447' with positive edge clock and positive level reset. 181s Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 181s created $dff cell `$procdff$448' with positive edge clock. 181s Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 181s created $dff cell `$procdff$449' with positive edge clock. 181s Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 181s created $dff cell `$procdff$450' with positive edge clock. 181s Creating register for signal `\top.\counter' using process `\top.$proc$example.v:16$381'. 181s created $dff cell `$procdff$451' with positive edge clock. 181s Creating register for signal `\top.\outcnt' using process `\top.$proc$example.v:16$381'. 181s created $dff cell `$procdff$452' with positive edge clock. 181s 181s 2.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 181s 181s 2.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 181s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 181s Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 181s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 181s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 181s Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 181s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 181s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 181s Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 181s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 181s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 181s Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 181s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 181s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 181s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 181s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 181s Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 181s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 181s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 181s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 181s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 181s Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 181s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 181s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 181s Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 181s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 181s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 181s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 181s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 181s Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 181s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 181s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 181s Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 181s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 181s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 181s Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 181s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 181s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 181s Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 181s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 181s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 181s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 181s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 181s Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 181s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 181s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 181s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 181s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 181s Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 181s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 181s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 181s Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 181s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 181s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 181s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 181s Removing empty process `top.$proc$example.v:13$386'. 181s Removing empty process `top.$proc$example.v:16$381'. 181s Cleaned up 18 empty switches. 181s 181s 2.4.12. Executing OPT_EXPR pass (perform const folding). 181s Optimizing module top. 181s 181s 181s 2.5. Executing FLATTEN pass (flatten design). 181s 181s 2.6. Executing TRIBUF pass. 181s 181s 2.7. Executing DEMINOUT pass (demote inout ports to input or output). 181s 181s 2.8. Executing OPT_EXPR pass (perform const folding). 181s Optimizing module top. 181s 181s 2.9. Executing OPT_CLEAN pass (remove unused cells and wires). 181s Finding unused cells or wires in module \top.. 181s Removed 0 unused cells and 5 unused wires. 181s 181s 181s 2.10. Executing CHECK pass (checking for obvious problems). 181s Checking module top... 181s Found and reported 0 problems. 181s 181s 2.11. Executing OPT pass (performing simple optimizations). 181s 181s 2.11.1. Executing OPT_EXPR pass (perform const folding). 181s Optimizing module top. 181s 181s 2.11.2. Executing OPT_MERGE pass (detect identical cells). 181s Finding identical cells in module `\top'. 181s Removed a total of 0 cells. 181s 181s 2.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 181s Running muxtree optimizer on module \top.. 181s Creating internal representation of mux trees. 181s No muxes found in this module. 181s Removed 0 multiplexer ports. 181s 181s 2.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 181s Optimizing cells in module \top. 181s Performed a total of 0 changes. 181s 181s 2.11.5. Executing OPT_MERGE pass (detect identical cells). 181s Finding identical cells in module `\top'. 181s Removed a total of 0 cells. 181s 181s 2.11.6. Executing OPT_DFF pass (perform DFF optimizations). 181s 181s 2.11.7. Executing OPT_CLEAN pass (remove unused cells and wires). 181s Finding unused cells or wires in module \top.. 181s 181s 2.11.8. Executing OPT_EXPR pass (perform const folding). 181s Optimizing module top. 181s 181s 2.11.9. Finished OPT passes. (There is nothing left to do.) 181s 181s 2.12. Executing FSM pass (extract and optimize FSM). 181s 181s 2.12.1. Executing FSM_DETECT pass (finding FSMs in design). 181s 181s 2.12.2. Executing FSM_EXTRACT pass (extracting FSM from design). 181s 181s 2.12.3. Executing FSM_OPT pass (simple optimizations of FSMs). 181s 181s 2.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). 181s Finding unused cells or wires in module \top.. 181s 181s 2.12.5. Executing FSM_OPT pass (simple optimizations of FSMs). 181s 181s 2.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 181s 181s 2.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 181s 181s 2.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 181s 181s 2.13. Executing OPT pass (performing simple optimizations). 181s 181s 2.13.1. Executing OPT_EXPR pass (perform const folding). 181s Optimizing module top. 181s 181s 2.13.2. Executing OPT_MERGE pass (detect identical cells). 181s Finding identical cells in module `\top'. 181s Removed a total of 0 cells. 181s 181s 2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 181s Running muxtree optimizer on module \top.. 181s Creating internal representation of mux trees. 181s No muxes found in this module. 181s Removed 0 multiplexer ports. 181s 181s 2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 181s Optimizing cells in module \top. 181s Performed a total of 0 changes. 181s 181s 2.13.5. Executing OPT_MERGE pass (detect identical cells). 181s Finding identical cells in module `\top'. 181s Removed a total of 0 cells. 181s 181s 2.13.6. Executing OPT_DFF pass (perform DFF optimizations). 181s 181s 2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). 181s Finding unused cells or wires in module \top.. 181s 181s 2.13.8. Executing OPT_EXPR pass (perform const folding). 181s Optimizing module top. 181s 181s 2.13.9. Finished OPT passes. (There is nothing left to do.) 181s 181s 2.14. Executing WREDUCE pass (reducing word size of cells). 181s Removed top 31 bits (of 32) from port B of cell top.$add$example.v:17$382 ($add). 181s Removed top 5 bits (of 32) from port Y of cell top.$add$example.v:17$382 ($add). 181s Removed top 1 bits (of 5) from port B of cell top.$xor$example.v:21$385 ($xor). 181s 181s 2.15. Executing PEEPOPT pass (run peephole optimizers). 181s 181s 2.16. Executing OPT_CLEAN pass (remove unused cells and wires). 181s Finding unused cells or wires in module \top.. 181s Removed 0 unused cells and 1 unused wires. 181s 181s 181s 2.17. Executing SHARE pass (SAT-based resource sharing). 181s 181s 2.18. Executing TECHMAP pass (map to technology primitives). 181s 181s 2.18.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v 181s Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation. 181s Generating RTLIL representation for module `\_90_lut_cmp_'. 181s Successfully finished Verilog frontend. 181s 181s 2.18.2. Continuing TECHMAP pass. 181s No more expansions possible. 181s 181s 181s 2.19. Executing OPT_EXPR pass (perform const folding). 181s Optimizing module top. 181s 181s 2.20. Executing OPT_CLEAN pass (remove unused cells and wires). 181s Finding unused cells or wires in module \top.. 181s 181s 2.21. Executing ALUMACC pass (create $alu and $macc cells). 181s Extracting $alu and $macc cells in module top: 181s creating $macc model for $add$example.v:17$382 ($add). 181s creating $alu model for $macc $add$example.v:17$382. 181s creating $alu cell for $add$example.v:17$382: $auto$alumacc.cc:485:replace_alu$454 181s created 1 $alu and 0 $macc cells. 181s 181s 2.22. Executing OPT pass (performing simple optimizations). 181s 181s 2.22.1. Executing OPT_EXPR pass (perform const folding). 181s Optimizing module top. 181s 181s 2.22.2. Executing OPT_MERGE pass (detect identical cells). 181s Finding identical cells in module `\top'. 181s Removed a total of 0 cells. 181s 181s 2.22.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 181s Running muxtree optimizer on module \top.. 181s Creating internal representation of mux trees. 181s No muxes found in this module. 181s Removed 0 multiplexer ports. 181s 181s 2.22.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 181s Optimizing cells in module \top. 181s Performed a total of 0 changes. 181s 181s 2.22.5. Executing OPT_MERGE pass (detect identical cells). 181s Finding identical cells in module `\top'. 181s Removed a total of 0 cells. 181s 181s 2.22.6. Executing OPT_DFF pass (perform DFF optimizations). 181s 181s 2.22.7. Executing OPT_CLEAN pass (remove unused cells and wires). 181s Finding unused cells or wires in module \top.. 181s 181s 2.22.8. Executing OPT_EXPR pass (perform const folding). 181s Optimizing module top. 181s 181s 2.22.9. Finished OPT passes. (There is nothing left to do.) 181s 181s 2.23. Executing MEMORY pass. 181s 181s 2.23.1. Executing OPT_MEM pass (optimize memories). 181s Performed a total of 0 transformations. 181s 181s 2.23.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). 181s Performed a total of 0 transformations. 181s 181s 2.23.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 181s 181s 2.23.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 181s 181s 2.23.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 181s 181s 2.23.6. Executing OPT_CLEAN pass (remove unused cells and wires). 181s Finding unused cells or wires in module \top.. 181s 181s 2.23.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 181s 181s 2.23.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). 181s Performed a total of 0 transformations. 181s 181s 2.23.9. Executing OPT_CLEAN pass (remove unused cells and wires). 181s Finding unused cells or wires in module \top.. 181s 181s 2.23.10. Executing MEMORY_COLLECT pass (generating $mem cells). 181s 181s 2.24. Executing OPT_CLEAN pass (remove unused cells and wires). 181s Finding unused cells or wires in module \top.. 181s 181s 2.25. Executing MEMORY_LIBMAP pass (mapping memories to cells). 181s 181s 2.26. Executing TECHMAP pass (map to technology primitives). 181s 181s 2.26.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v 181s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation. 181s Generating RTLIL representation for module `\$__ICE40_RAM4K_'. 181s Successfully finished Verilog frontend. 181s 181s 2.26.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/spram_map.v 181s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/spram_map.v' to AST representation. 181s Generating RTLIL representation for module `\$__ICE40_SPRAM_'. 181s Successfully finished Verilog frontend. 181s 181s 2.26.3. Continuing TECHMAP pass. 181s No more expansions possible. 181s 181s 181s 2.27. Executing ICE40_BRAMINIT pass. 181s 181s 2.28. Executing OPT pass (performing simple optimizations). 181s 181s 2.28.1. Executing OPT_EXPR pass (perform const folding). 181s Optimizing module top. 181s 181s 181s 2.28.2. Executing OPT_MERGE pass (detect identical cells). 181s Finding identical cells in module `\top'. 181s Removed a total of 0 cells. 181s 181s 2.28.3. Executing OPT_DFF pass (perform DFF optimizations). 181s 181s 2.28.4. Executing OPT_CLEAN pass (remove unused cells and wires). 181s Finding unused cells or wires in module \top.. 181s Removed 0 unused cells and 2 unused wires. 181s 181s 181s 2.28.5. Finished fast OPT passes. 181s 181s 2.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 181s 181s 2.30. Executing OPT pass (performing simple optimizations). 181s 181s 2.30.1. Executing OPT_EXPR pass (perform const folding). 181s Optimizing module top. 181s 181s 2.30.2. Executing OPT_MERGE pass (detect identical cells). 181s Finding identical cells in module `\top'. 181s Removed a total of 0 cells. 181s 181s 2.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 181s Running muxtree optimizer on module \top.. 181s Creating internal representation of mux trees. 181s No muxes found in this module. 181s Removed 0 multiplexer ports. 181s 181s 2.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 181s Optimizing cells in module \top. 181s Performed a total of 0 changes. 181s 181s 2.30.5. Executing OPT_MERGE pass (detect identical cells). 181s Finding identical cells in module `\top'. 181s Removed a total of 0 cells. 181s 181s 2.30.6. Executing OPT_DFF pass (perform DFF optimizations). 181s 181s 2.30.7. Executing OPT_CLEAN pass (remove unused cells and wires). 181s Finding unused cells or wires in module \top.. 181s 181s 2.30.8. Executing OPT_EXPR pass (perform const folding). 181s Optimizing module top. 181s 181s 2.30.9. Finished OPT passes. (There is nothing left to do.) 181s 181s 2.31. Executing ICE40_WRAPCARRY pass (wrap carries). 181s 181s 2.32. Executing TECHMAP pass (map to technology primitives). 181s 181s 2.32.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v 181s Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation. 181s Generating RTLIL representation for module `\_90_simplemap_bool_ops'. 181s Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. 181s Generating RTLIL representation for module `\_90_simplemap_logic_ops'. 181s Generating RTLIL representation for module `\_90_simplemap_compare_ops'. 181s Generating RTLIL representation for module `\_90_simplemap_various'. 181s Generating RTLIL representation for module `\_90_simplemap_registers'. 181s Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. 181s Generating RTLIL representation for module `\_90_shift_shiftx'. 181s Generating RTLIL representation for module `\_90_fa'. 181s Generating RTLIL representation for module `\_90_lcu'. 181s Generating RTLIL representation for module `\_90_alu'. 181s Generating RTLIL representation for module `\_90_macc'. 181s Generating RTLIL representation for module `\_90_alumacc'. 181s Generating RTLIL representation for module `\$__div_mod_u'. 181s Generating RTLIL representation for module `\$__div_mod_trunc'. 181s Generating RTLIL representation for module `\_90_div'. 181s Generating RTLIL representation for module `\_90_mod'. 181s Generating RTLIL representation for module `\$__div_mod_floor'. 181s Generating RTLIL representation for module `\_90_divfloor'. 181s Generating RTLIL representation for module `\_90_modfloor'. 181s Generating RTLIL representation for module `\_90_pow'. 181s Generating RTLIL representation for module `\_90_pmux'. 181s Generating RTLIL representation for module `\_90_demux'. 181s Generating RTLIL representation for module `\_90_lut'. 181s Successfully finished Verilog frontend. 181s 181s 2.32.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v 181s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation. 181s Generating RTLIL representation for module `\_80_ice40_alu'. 181s Successfully finished Verilog frontend. 181s 181s 2.32.3. Continuing TECHMAP pass. 181s Using template $paramod$956e79e8f8c5e64be7438155ae50a966e615cb04\_80_ice40_alu for cells of type $alu. 181s Using extmapper simplemap for cells of type $xor. 181s Using extmapper simplemap for cells of type $dff. 181s Using extmapper simplemap for cells of type $mux. 181s Using extmapper simplemap for cells of type $not. 181s Using extmapper simplemap for cells of type $pos. 181s No more expansions possible. 181s 181s 181s 2.33. Executing OPT pass (performing simple optimizations). 181s 181s 2.33.1. Executing OPT_EXPR pass (perform const folding). 181s Optimizing module top. 181s 181s 181s 2.33.2. Executing OPT_MERGE pass (detect identical cells). 181s Finding identical cells in module `\top'. 181s 181s Removed a total of 1 cells. 181s 181s 2.33.3. Executing OPT_DFF pass (perform DFF optimizations). 181s 181s 2.33.4. Executing OPT_CLEAN pass (remove unused cells and wires). 181s Finding unused cells or wires in module \top.. 181s Removed 27 unused cells and 17 unused wires. 181s 181s 181s 2.33.5. Finished fast OPT passes. 181s 181s 2.34. Executing ICE40_OPT pass (performing simple optimizations). 181s 181s 2.34.1. Running ICE40 specific optimizations. 181s Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$454.slice[0].carry: CO=\counter [0] 181s 181s 2.34.2. Executing OPT_EXPR pass (perform const folding). 181s Optimizing module top. 181s 181s 2.34.3. Executing OPT_MERGE pass (detect identical cells). 181s Finding identical cells in module `\top'. 181s Removed a total of 0 cells. 181s 181s 2.34.4. Executing OPT_DFF pass (perform DFF optimizations). 181s 181s 2.34.5. Executing OPT_CLEAN pass (remove unused cells and wires). 181s Finding unused cells or wires in module \top.. 181s 181s 2.34.6. Rerunning OPT passes. (Removed registers in this run.) 181s 181s 2.34.7. Running ICE40 specific optimizations. 181s 181s 2.34.8. Executing OPT_EXPR pass (perform const folding). 181s Optimizing module top. 181s 181s 2.34.9. Executing OPT_MERGE pass (detect identical cells). 181s Finding identical cells in module `\top'. 181s Removed a total of 0 cells. 181s 181s 2.34.10. Executing OPT_DFF pass (perform DFF optimizations). 181s 181s 2.34.11. Executing OPT_CLEAN pass (remove unused cells and wires). 181s Finding unused cells or wires in module \top.. 181s 181s 2.34.12. Finished OPT passes. (There is nothing left to do.) 181s 181s 2.35. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 181s 181s 2.36. Executing TECHMAP pass (map to technology primitives). 181s 181s 2.36.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 181s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 181s Generating RTLIL representation for module `\$_DFF_N_'. 181s Generating RTLIL representation for module `\$_DFF_P_'. 181s Generating RTLIL representation for module `\$_DFFE_NP_'. 181s Generating RTLIL representation for module `\$_DFFE_PP_'. 181s Generating RTLIL representation for module `\$_DFF_NP0_'. 181s Generating RTLIL representation for module `\$_DFF_NP1_'. 181s Generating RTLIL representation for module `\$_DFF_PP0_'. 181s Generating RTLIL representation for module `\$_DFF_PP1_'. 181s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 181s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 181s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 181s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 181s Generating RTLIL representation for module `\$_SDFF_NP0_'. 181s Generating RTLIL representation for module `\$_SDFF_NP1_'. 181s Generating RTLIL representation for module `\$_SDFF_PP0_'. 181s Generating RTLIL representation for module `\$_SDFF_PP1_'. 181s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 181s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 181s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 181s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 181s Successfully finished Verilog frontend. 181s 181s 2.36.2. Continuing TECHMAP pass. 181s Using template \$_DFF_P_ for cells of type $_DFF_P_. 181s No more expansions possible. 181s 181s 181s 2.37. Executing OPT_EXPR pass (perform const folding). 181s Optimizing module top. 181s 181s 2.38. Executing SIMPLEMAP pass (map simple cells to gate primitives). 181s Mapping top.$auto$alumacc.cc:485:replace_alu$454.slice[0].carry ($lut). 181s 181s 2.39. Executing ICE40_OPT pass (performing simple optimizations). 181s 181s 2.39.1. Running ICE40 specific optimizations. 181s 181s 2.39.2. Executing OPT_EXPR pass (perform const folding). 181s Optimizing module top. 181s 181s 181s 2.39.3. Executing OPT_MERGE pass (detect identical cells). 181s Finding identical cells in module `\top'. 181s Removed a total of 0 cells. 181s 181s 2.39.4. Executing OPT_DFF pass (perform DFF optimizations). 181s 181s 2.39.5. Executing OPT_CLEAN pass (remove unused cells and wires). 181s Finding unused cells or wires in module \top.. 181s Removed 0 unused cells and 132 unused wires. 181s 181s 181s 2.39.6. Rerunning OPT passes. (Removed registers in this run.) 181s 181s 2.39.7. Running ICE40 specific optimizations. 181s 181s 2.39.8. Executing OPT_EXPR pass (perform const folding). 181s Optimizing module top. 181s 181s 2.39.9. Executing OPT_MERGE pass (detect identical cells). 181s Finding identical cells in module `\top'. 181s Removed a total of 0 cells. 181s 181s 2.39.10. Executing OPT_DFF pass (perform DFF optimizations). 181s 181s 2.39.11. Executing OPT_CLEAN pass (remove unused cells and wires). 181s Finding unused cells or wires in module \top.. 181s 181s 2.39.12. Finished OPT passes. (There is nothing left to do.) 181s 181s 2.40. Executing TECHMAP pass (map to technology primitives). 181s 181s 2.40.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v 181s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation. 181s Generating RTLIL representation for module `\$_DLATCH_N_'. 181s Generating RTLIL representation for module `\$_DLATCH_P_'. 181s Successfully finished Verilog frontend. 181s 181s 2.40.2. Continuing TECHMAP pass. 181s No more expansions possible. 181s 181s 181s 2.41. Executing ABC pass (technology mapping using ABC). 181s 181s 2.41.1. Extracting gate netlist of module `\top' to `/input.blif'.. 181s Extracted 5 gates and 11 wires to a netlist network with 6 inputs and 5 outputs. 181s 181s 2.41.1.1. Executing ABC. 181s Running ABC command: "berkeley-abc" -s -f /abc.script 2>&1 181s ABC: ABC command line: "source /abc.script". 181s ABC: 181s ABC: + read_blif /input.blif 181s ABC: + read_lut /lutdefs.txt 181s ABC: + strash 181s ABC: + &get -n 181s ABC: + &fraig -x 181s ABC: + &put 181s ABC: + scorr 181s ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). 181s ABC: + dc2 181s ABC: + dretime 181s ABC: + strash 181s ABC: + dch -f 181s ABC: + if 181s ABC: + mfs2 181s ABC: + lutpack -S 1 181s ABC: + dress /input.blif 181s ABC: Total number of equiv classes = 6. 181s ABC: Participating nodes from both networks = 10. 181s ABC: Participating nodes from the first network = 5. ( 83.33 % of nodes) 181s ABC: Participating nodes from the second network = 5. ( 83.33 % of nodes) 181s ABC: Node pairs (any polarity) = 5. ( 83.33 % of names can be moved) 181s ABC: Node pairs (same polarity) = 5. ( 83.33 % of names can be moved) 181s ABC: Total runtime = 0.00 sec 181s ABC: + write_blif /output.blif 181s 181s 2.41.1.2. Re-integrating ABC results. 181s ABC RESULTS: $lut cells: 5 181s ABC RESULTS: internal signals: 0 181s ABC RESULTS: input signals: 6 181s ABC RESULTS: output signals: 5 181s Removing temp directory. 181s 181s 2.42. Executing ICE40_WRAPCARRY pass (wrap carries). 181s 181s 2.43. Executing TECHMAP pass (map to technology primitives). 181s 181s 2.43.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 181s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 181s Generating RTLIL representation for module `\$_DFF_N_'. 181s Generating RTLIL representation for module `\$_DFF_P_'. 181s Generating RTLIL representation for module `\$_DFFE_NP_'. 181s Generating RTLIL representation for module `\$_DFFE_PP_'. 181s Generating RTLIL representation for module `\$_DFF_NP0_'. 181s Generating RTLIL representation for module `\$_DFF_NP1_'. 181s Generating RTLIL representation for module `\$_DFF_PP0_'. 181s Generating RTLIL representation for module `\$_DFF_PP1_'. 181s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 181s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 181s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 181s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 181s Generating RTLIL representation for module `\$_SDFF_NP0_'. 181s Generating RTLIL representation for module `\$_SDFF_NP1_'. 181s Generating RTLIL representation for module `\$_SDFF_PP0_'. 181s Generating RTLIL representation for module `\$_SDFF_PP1_'. 181s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 181s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 181s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 181s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 181s Successfully finished Verilog frontend. 181s 181s 2.43.2. Continuing TECHMAP pass. 181s No more expansions possible. 181s 181s Removed 1 unused cells and 12 unused wires. 181s 181s 2.44. Executing OPT_LUT pass (optimize LUTs). 181s Discovering LUTs. 181s Number of LUTs: 31 181s 1-LUT 1 181s 2-LUT 5 181s 3-LUT 25 181s with \SB_CARRY (#0) 25 181s with \SB_CARRY (#1) 25 181s 181s Eliminating LUTs. 181s Number of LUTs: 31 181s 1-LUT 1 181s 2-LUT 5 181s 3-LUT 25 181s with \SB_CARRY (#0) 25 181s with \SB_CARRY (#1) 25 181s 181s Combining LUTs. 181s Number of LUTs: 31 181s 1-LUT 1 181s 2-LUT 5 181s 3-LUT 25 181s with \SB_CARRY (#0) 25 181s with \SB_CARRY (#1) 25 181s 181s Eliminated 0 LUTs. 181s Combined 0 LUTs. 181s 181s 181s 2.45. Executing TECHMAP pass (map to technology primitives). 181s 181s 2.45.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v 181s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation. 181s Generating RTLIL representation for module `\$lut'. 181s Successfully finished Verilog frontend. 181s 181s 2.45.2. Continuing TECHMAP pass. 181s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut. 181s Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut. 181s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. 181s No more expansions possible. 181s 181s Removed 0 unused cells and 62 unused wires. 181s 181s 2.46. Executing AUTONAME pass. 181s Renamed 142 objects in module top (4 iterations). 181s 181s 181s 2.47. Executing HIERARCHY pass (managing design hierarchy). 181s 181s 2.47.1. Analyzing design hierarchy.. 181s Top module: \top 181s 181s 2.47.2. Analyzing design hierarchy.. 181s Top module: \top 181s Removed 0 unused modules. 181s 181s 2.48. Printing statistics. 182s 182s === top === 182s 182s Number of wires: 10 182s Number of wire bits: 92 182s Number of public wires: 10 182s Number of public wire bits: 92 182s Number of memories: 0 182s Number of memory bits: 0 182s Number of processes: 0 182s Number of cells: 88 182s SB_CARRY 25 182s SB_DFF 32 182s SB_LUT4 31 182s 182s 2.49. Executing CHECK pass (checking for obvious problems). 182s Checking module top... 182s Found and reported 0 problems. 182s 182s 2.50. Executing JSON backend. 182s 182s End of script. Logfile hash: 7b17f9bd89, CPU: user 0.64s system 0.02s, MEM: 20.00 MB peak 182s Yosys 0.23 (git sha1 7ce5011c24b) 182s Time spent: 63% 13x read_verilog (0 sec), 8% 1x abc (0 sec), ... 182s nextpnr-ice40 --hx1k --package tq144 --asc example.asc --pcf icestick.pcf --json example.json 182s Warning: unmatched constraint 'RX' (on line 4) 182s Warning: unmatched constraint 'TX' (on line 5) 182s Info: constrained 'LED1' to bel 'X13/Y12/io1' 182s Info: constrained 'LED2' to bel 'X13/Y12/io0' 182s Info: constrained 'LED3' to bel 'X13/Y11/io1' 182s Info: constrained 'LED4' to bel 'X13/Y11/io0' 182s Info: constrained 'LED5' to bel 'X13/Y9/io1' 182s Info: constrained 'clk' to bel 'X0/Y8/io1' 182s 182s Info: Packing constants.. 182s Info: Packing IOs.. 182s Info: Packing LUT-FFs.. 182s Info: 4 LCs used as LUT4 only 182s Info: 27 LCs used as LUT4 and DFF 182s Info: Packing non-LUT FFs.. 182s Info: 5 LCs used as DFF only 182s Info: Packing carries.. 182s Info: 0 LCs used as CARRY only 182s Info: Packing indirect carry+LUT pairs... 182s Info: 0 LUTs merged into carry LCs 182s Info: Packing RAMs.. 182s Info: Placing PLLs.. 182s Info: Packing special functions.. 182s Info: Packing PLLs.. 182s Info: Promoting globals.. 182s Info: promoting clk$SB_IO_IN (fanout 32) 182s Info: Constraining chains... 182s Info: 1 LCs used to legalise carry chains. 182s Info: Checksum: 0xae2b0ce7 182s 182s Info: Annotating ports with timing budgets for target frequency 12.00 MHz 182s Info: Checksum: 0x993bf822 182s 182s Info: Device utilisation: 182s Info: ICESTORM_LC: 39/ 1280 3% 182s Info: ICESTORM_RAM: 0/ 16 0% 182s Info: SB_IO: 6/ 112 5% 182s Info: SB_GB: 1/ 8 12% 182s Info: ICESTORM_PLL: 0/ 1 0% 182s Info: SB_WARMBOOT: 0/ 1 0% 182s 182s Info: Placed 6 cells based on constraints. 182s Info: Creating initial analytic placement for 12 cells, random placement wirelen = 182. 182s Info: at initial placer iter 0, wirelen = 16 182s Info: at initial placer iter 1, wirelen = 16 182s Info: at initial placer iter 2, wirelen = 18 182s Info: at initial placer iter 3, wirelen = 18 182s Info: Running main analytical placer, max placement attempts per cell = 10000. 182s Info: at iteration #1, type ICESTORM_LC: wirelen solved = 19, spread = 34, legal = 36; time = 0.00s 182s Info: at iteration #1, type SB_GB: wirelen solved = 36, spread = 36, legal = 36; time = 0.00s 182s Info: at iteration #1, type ALL: wirelen solved = 17, spread = 33, legal = 33; time = 0.00s 182s Info: at iteration #2, type ICESTORM_LC: wirelen solved = 17, spread = 31, legal = 32; time = 0.00s 182s Info: at iteration #2, type SB_GB: wirelen solved = 32, spread = 32, legal = 32; time = 0.00s 182s Info: at iteration #2, type ALL: wirelen solved = 17, spread = 31, legal = 32; time = 0.00s 182s Info: at iteration #3, type ICESTORM_LC: wirelen solved = 15, spread = 36, legal = 37; time = 0.00s 182s Info: at iteration #3, type SB_GB: wirelen solved = 37, spread = 37, legal = 37; time = 0.00s 182s Info: at iteration #3, type ALL: wirelen solved = 15, spread = 36, legal = 38; time = 0.00s 182s Info: at iteration #4, type ICESTORM_LC: wirelen solved = 15, spread = 37, legal = 38; time = 0.00s 182s Info: at iteration #4, type SB_GB: wirelen solved = 38, spread = 38, legal = 38; time = 0.00s 182s Info: at iteration #4, type ALL: wirelen solved = 15, spread = 37, legal = 38; time = 0.00s 182s Info: at iteration #5, type ICESTORM_LC: wirelen solved = 20, spread = 38, legal = 40; time = 0.00s 182s Info: at iteration #5, type SB_GB: wirelen solved = 40, spread = 40, legal = 40; time = 0.00s 182s Info: at iteration #5, type ALL: wirelen solved = 20, spread = 38, legal = 39; time = 0.00s 182s Info: at iteration #6, type ICESTORM_LC: wirelen solved = 20, spread = 39, legal = 40; time = 0.00s 182s Info: at iteration #6, type SB_GB: wirelen solved = 40, spread = 40, legal = 40; time = 0.00s 182s Info: at iteration #6, type ALL: wirelen solved = 20, spread = 39, legal = 41; time = 0.00s 182s Info: at iteration #7, type ICESTORM_LC: wirelen solved = 27, spread = 39, legal = 41; time = 0.00s 182s Info: at iteration #7, type SB_GB: wirelen solved = 41, spread = 41, legal = 41; time = 0.00s 182s Info: at iteration #7, type ALL: wirelen solved = 27, spread = 39, legal = 40; time = 0.00s 182s Info: HeAP Placer Time: 0.01s 182s Info: of which solving equations: 0.01s 182s Info: of which spreading cells: 0.00s 182s Info: of which strict legalisation: 0.00s 182s 182s Info: Running simulated annealing placer for refinement. 182s Info: at iteration #1: temp = 0.000000, timing cost = 4, wirelen = 32 182s Info: at iteration #5: temp = 0.000000, timing cost = 4, wirelen = 21 182s Info: at iteration #9: temp = 0.000000, timing cost = 4, wirelen = 21 182s Info: SA placement time 0.01s 182s 182s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 170.01 MHz (PASS at 12.00 MHz) 182s 182s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> : 2.09 ns 182s 182s Info: Slack histogram: 182s Info: legend: * represents 1 endpoint(s) 182s Info: + represents [1,1) endpoint(s) 182s Info: [ 77451, 77672) |*** 182s Info: [ 77672, 77893) | 182s Info: [ 77893, 78114) |* 182s Info: [ 78114, 78335) |** 182s Info: [ 78335, 78556) |* 182s Info: [ 78556, 78777) |** 182s Info: [ 78777, 78998) |** 182s Info: [ 78998, 79219) | 182s Info: [ 79219, 79440) |* 182s Info: [ 79440, 79661) |** 182s Info: [ 79661, 79882) |** 182s Info: [ 79882, 80103) |** 182s Info: [ 80103, 80324) |* 182s Info: [ 80324, 80545) | 182s Info: [ 80545, 80766) |** 182s Info: [ 80766, 80987) |** 182s Info: [ 80987, 81208) |* 182s Info: [ 81208, 81429) |***** 182s Info: [ 81429, 81650) |* 182s Info: [ 81650, 81871) |********************************* 182s Info: Checksum: 0xa2e17380 182s 182s Info: Routing.. 182s Info: Setting up routing queue. 182s Info: Routing 106 arcs. 182s Info: | (re-)routed arcs | delta | remaining| time spent | 182s Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| 182s Info: 106 | 0 84 | 0 84 | 0| 0.00 0.00| 182s Info: Routing complete. 182s Info: Router1 time 0.00s 182s Info: Checksum: 0x30991612 182s 182s Info: Critical path report for clock 'clk$SB_IO_IN_$glb_clk' (posedge -> posedge): 182s Info: curr total 182s Info: 0.5 0.5 Source counter_SB_LUT4_I3_LC.O 182s Info: 0.6 1.1 Net counter[0] budget 78.740997 ns (11,6) -> (11,7) 182s Info: Sink $nextpnr_ICESTORM_LC_0.I1 182s Info: Defined in: 182s Info: example.v:17.14-17.25 182s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 182s Info: 0.3 1.4 Source $nextpnr_ICESTORM_LC_0.COUT 182s Info: 0.0 1.4 Net $nextpnr_ICESTORM_LC_0$O budget 0.000000 ns (11,7) -> (11,7) 182s Info: Sink counter_SB_LUT4_I2_20_LC.CIN 182s Info: 0.1 1.5 Source counter_SB_LUT4_I2_20_LC.COUT 182s Info: 0.0 1.5 Net counter_SB_CARRY_CI_CO[2] budget 0.000000 ns (11,7) -> (11,7) 182s Info: Sink counter_SB_LUT4_I2_12_LC.CIN 182s Info: Defined in: 182s Info: example.v:17.14-17.25 182s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 182s Info: 0.1 1.6 Source counter_SB_LUT4_I2_12_LC.COUT 182s Info: 0.0 1.6 Net counter_SB_CARRY_CI_CO[3] budget 0.000000 ns (11,7) -> (11,7) 182s Info: Sink counter_SB_LUT4_I2_11_LC.CIN 182s Info: Defined in: 182s Info: example.v:17.14-17.25 182s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 182s Info: 0.1 1.8 Source counter_SB_LUT4_I2_11_LC.COUT 182s Info: 0.0 1.8 Net counter_SB_CARRY_CI_CO[4] budget 0.000000 ns (11,7) -> (11,7) 182s Info: Sink counter_SB_LUT4_I2_10_LC.CIN 182s Info: Defined in: 182s Info: example.v:17.14-17.25 182s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 182s Info: 0.1 1.9 Source counter_SB_LUT4_I2_10_LC.COUT 182s Info: 0.0 1.9 Net counter_SB_CARRY_CI_CO[5] budget 0.000000 ns (11,7) -> (11,7) 182s Info: Sink counter_SB_LUT4_I2_9_LC.CIN 182s Info: Defined in: 182s Info: example.v:17.14-17.25 182s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 182s Info: 0.1 2.0 Source counter_SB_LUT4_I2_9_LC.COUT 182s Info: 0.0 2.0 Net counter_SB_CARRY_CI_CO[6] budget 0.000000 ns (11,7) -> (11,7) 182s Info: Sink counter_SB_LUT4_I2_8_LC.CIN 182s Info: Defined in: 182s Info: example.v:17.14-17.25 182s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 182s Info: 0.1 2.1 Source counter_SB_LUT4_I2_8_LC.COUT 182s Info: 0.0 2.1 Net counter_SB_CARRY_CI_CO[7] budget 0.000000 ns (11,7) -> (11,7) 182s Info: Sink counter_SB_LUT4_I2_7_LC.CIN 182s Info: Defined in: 182s Info: example.v:17.14-17.25 182s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 182s Info: 0.1 2.3 Source counter_SB_LUT4_I2_7_LC.COUT 182s Info: 0.2 2.5 Net counter_SB_CARRY_CI_CO[8] budget 0.190000 ns (11,7) -> (11,8) 182s Info: Sink counter_SB_LUT4_I2_6_LC.CIN 182s Info: Defined in: 182s Info: example.v:17.14-17.25 182s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 182s Info: 0.1 2.6 Source counter_SB_LUT4_I2_6_LC.COUT 182s Info: 0.0 2.6 Net counter_SB_CARRY_CI_CO[9] budget 0.000000 ns (11,8) -> (11,8) 182s Info: Sink counter_SB_LUT4_I2_5_LC.CIN 182s Info: Defined in: 182s Info: example.v:17.14-17.25 182s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 182s Info: 0.1 2.7 Source counter_SB_LUT4_I2_5_LC.COUT 182s Info: 0.0 2.7 Net counter_SB_CARRY_CI_CO[10] budget 0.000000 ns (11,8) -> (11,8) 182s Info: Sink counter_SB_LUT4_I2_4_LC.CIN 182s Info: Defined in: 182s Info: example.v:17.14-17.25 182s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 182s Info: 0.1 2.8 Source counter_SB_LUT4_I2_4_LC.COUT 182s Info: 0.0 2.8 Net counter_SB_CARRY_CI_CO[11] budget 0.000000 ns (11,8) -> (11,8) 182s Info: Sink counter_SB_LUT4_I2_3_LC.CIN 182s Info: Defined in: 182s Info: example.v:17.14-17.25 182s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 182s Info: 0.1 3.0 Source counter_SB_LUT4_I2_3_LC.COUT 182s Info: 0.0 3.0 Net counter_SB_CARRY_CI_CO[12] budget 0.000000 ns (11,8) -> (11,8) 182s Info: Sink counter_SB_LUT4_I2_2_LC.CIN 182s Info: Defined in: 182s Info: example.v:17.14-17.25 182s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 182s Info: 0.1 3.1 Source counter_SB_LUT4_I2_2_LC.COUT 182s Info: 0.0 3.1 Net counter_SB_CARRY_CI_CO[13] budget 0.000000 ns (11,8) -> (11,8) 182s Info: Sink counter_SB_LUT4_I2_1_LC.CIN 182s Info: Defined in: 182s Info: example.v:17.14-17.25 182s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 182s Info: 0.1 3.2 Source counter_SB_LUT4_I2_1_LC.COUT 182s Info: 0.0 3.2 Net counter_SB_CARRY_CI_CO[14] budget 0.000000 ns (11,8) -> (11,8) 182s Info: Sink counter_SB_LUT4_I2_LC.CIN 182s Info: Defined in: 182s Info: example.v:17.14-17.25 182s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 182s Info: 0.1 3.3 Source counter_SB_LUT4_I2_LC.COUT 182s Info: 0.0 3.3 Net counter_SB_CARRY_CI_CO[15] budget 0.000000 ns (11,8) -> (11,8) 182s Info: Sink counter_SB_LUT4_I2_25_LC.CIN 182s Info: Defined in: 182s Info: example.v:17.14-17.25 182s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 182s Info: 0.1 3.5 Source counter_SB_LUT4_I2_25_LC.COUT 182s Info: 0.2 3.7 Net counter_SB_CARRY_CI_CO[16] budget 0.190000 ns (11,8) -> (11,9) 182s Info: Sink counter_SB_LUT4_I2_24_LC.CIN 182s Info: Defined in: 182s Info: example.v:17.14-17.25 182s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 182s Info: 0.1 3.8 Source counter_SB_LUT4_I2_24_LC.COUT 182s Info: 0.0 3.8 Net counter_SB_CARRY_CI_CO[17] budget 0.000000 ns (11,9) -> (11,9) 182s Info: Sink counter_SB_LUT4_I2_23_LC.CIN 182s Info: Defined in: 182s Info: example.v:17.14-17.25 182s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 182s Info: 0.1 3.9 Source counter_SB_LUT4_I2_23_LC.COUT 182s icetime -d hx1k -mtr example.rpt example.asc 182s // Reading input .asc file.. 182s // Reading 1k chipdb file.. 182s Info: 0.0 3.9 Net counter_SB_CARRY_CI_CO[18] budget 0.000000 ns (11,9) -> (11,9) 182s Info: Sink counter_SB_LUT4_I2_22_LC.CIN 182s Info: Defined in: 182s Info: example.v:17.14-17.25 182s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 182s Info: 0.1 4.0 Source counter_SB_LUT4_I2_22_LC.COUT 182s Info: 0.0 4.0 Net counter_SB_CARRY_CI_CO[19] budget 0.000000 ns (11,9) -> (11,9) 182s Info: Sink counter_SB_LUT4_I2_21_LC.CIN 182s Info: Defined in: 182s Info: example.v:17.14-17.25 182s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 182s Info: 0.1 4.2 Source counter_SB_LUT4_I2_21_LC.COUT 182s Info: 0.0 4.2 Net counter_SB_CARRY_CI_CO[20] budget 0.000000 ns (11,9) -> (11,9) 182s Info: Sink counter_SB_LUT4_I2_19_LC.CIN 182s Info: Defined in: 182s Info: example.v:17.14-17.25 182s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 182s Info: 0.1 4.3 Source counter_SB_LUT4_I2_19_LC.COUT 182s Info: 0.0 4.3 Net counter_SB_CARRY_CI_CO[21] budget 0.000000 ns (11,9) -> (11,9) 182s Info: Sink counter_SB_LUT4_I2_18_LC.CIN 182s Info: Defined in: 182s Info: example.v:17.14-17.25 182s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 182s Info: 0.1 4.4 Source counter_SB_LUT4_I2_18_LC.COUT 182s Info: 0.0 4.4 Net counter_SB_CARRY_CI_CO[22] budget 0.000000 ns (11,9) -> (11,9) 182s Info: Sink counter_SB_LUT4_I2_17_LC.CIN 182s Info: Defined in: 182s Info: example.v:17.14-17.25 182s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 182s Info: 0.1 4.6 Source counter_SB_LUT4_I2_17_LC.COUT 182s Info: 0.0 4.6 Net counter_SB_CARRY_CI_CO[23] budget 0.000000 ns (11,9) -> (11,9) 182s Info: Sink counter_SB_LUT4_I2_16_LC.CIN 182s Info: Defined in: 182s Info: example.v:17.14-17.25 182s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 182s Info: 0.1 4.7 Source counter_SB_LUT4_I2_16_LC.COUT 182s Info: 0.2 4.9 Net counter_SB_CARRY_CI_CO[24] budget 0.190000 ns (11,9) -> (11,10) 182s Info: Sink counter_SB_LUT4_I2_15_LC.CIN 182s Info: Defined in: 182s Info: example.v:17.14-17.25 182s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 182s Info: 0.1 5.0 Source counter_SB_LUT4_I2_15_LC.COUT 182s Info: 0.0 5.0 Net counter_SB_CARRY_CI_CO[25] budget 0.000000 ns (11,10) -> (11,10) 182s Info: Sink counter_SB_LUT4_I2_14_LC.CIN 182s Info: Defined in: 182s Info: example.v:17.14-17.25 182s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 182s Info: 0.1 5.1 Source counter_SB_LUT4_I2_14_LC.COUT 182s Info: 0.3 5.4 Net counter_SB_CARRY_CI_CO[26] budget 0.260000 ns (11,10) -> (11,10) 182s Info: Sink counter_SB_LUT4_I2_13_LC.I3 182s Info: Defined in: 182s Info: example.v:17.14-17.25 182s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 182s Info: 0.3 5.7 Setup counter_SB_LUT4_I2_13_LC.I3 182s Info: 4.3 ns logic, 1.4 ns routing 182s 182s Info: Critical path report for cross-domain path 'posedge clk$SB_IO_IN_$glb_clk' -> '': 182s Info: curr total 182s Info: 0.5 0.5 Source outcnt_SB_DFF_Q_DFFLC.O 182s Info: 0.6 1.1 Net outcnt[3] budget 41.208000 ns (11,10) -> (12,11) 182s Info: Sink LED2_SB_LUT4_O_LC.I2 182s Info: Defined in: 182s Info: example.v:14.17-14.23 182s Info: 0.4 1.5 Source LED2_SB_LUT4_O_LC.O 182s Info: 0.6 2.1 Net LED2$SB_IO_OUT budget 41.207001 ns (12,11) -> (13,12) 182s Info: Sink LED2$sb_io.D_OUT_0 182s Info: Defined in: 182s Info: example.v:4.9-4.13 182s Info: 0.9 ns logic, 1.2 ns routing 182s 182s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 174.83 MHz (PASS at 12.00 MHz) 182s 182s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> : 2.09 ns 182s 182s Info: Slack histogram: 182s Info: legend: * represents 1 endpoint(s) 182s Info: + represents [1,1) endpoint(s) 182s Info: [ 77613, 77826) |*** 182s Info: [ 77826, 78039) | 182s Info: [ 78039, 78252) |* 182s Info: [ 78252, 78465) |** 182s Info: [ 78465, 78678) |* 182s Info: [ 78678, 78891) |** 182s Info: [ 78891, 79104) |** 182s Info: [ 79104, 79317) | 182s Info: [ 79317, 79530) |** 182s Info: [ 79530, 79743) |* 182s Info: [ 79743, 79956) |** 182s Info: [ 79956, 80169) |** 182s Info: [ 80169, 80382) |* 182s Info: [ 80382, 80595) | 182s Info: [ 80595, 80808) |** 182s Info: [ 80808, 81021) |** 182s Info: [ 81021, 81234) |** 182s Info: [ 81234, 81447) |**** 182s Info: [ 81447, 81660) |** 182s Info: [ 81660, 81873) |******************************** 182s 2 warnings, 0 errors 182s 182s Info: Program finished normally. 182s // Creating timing netlist.. 182s // Timing estimate: 5.68 ns (175.97 MHz) 182s icepack example.asc example.bin 182s make: Leaving directory '/tmp/autopkgtest.rlxjW8/build.dCN/src/examples/icestick' 182s make: Entering directory '/tmp/autopkgtest.rlxjW8/build.dCN/src/examples/icezum' 182s yosys -p 'synth_ice40 -top top -json example.json' example.v 182s 182s /----------------------------------------------------------------------------\ 182s | | 182s | yosys -- Yosys Open SYnthesis Suite | 182s | | 182s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 182s | | 182s | Permission to use, copy, modify, and/or distribute this software for any | 182s | purpose with or without fee is hereby granted, provided that the above | 182s | copyright notice and this permission notice appear in all copies. | 182s | | 182s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 182s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 182s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 182s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 182s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 182s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 182s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 182s | | 182s \----------------------------------------------------------------------------/ 182s 182s Yosys 0.23 (git sha1 7ce5011c24b) 182s 182s 182s -- Parsing `example.v' using frontend ` -vlog2k' -- 182s 182s 1. Executing Verilog-2005 frontend: example.v 182s Parsing Verilog input from `example.v' to AST representation. 182s Storing AST representation for module `$abstract\top'. 182s Successfully finished Verilog frontend. 182s 182s -- Running command `synth_ice40 -top top -json example.json' -- 182s 182s 2. Executing SYNTH_ICE40 pass. 182s 182s 2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v 182s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation. 182s Generating RTLIL representation for module `\SB_IO'. 182s Generating RTLIL representation for module `\SB_GB_IO'. 182s Generating RTLIL representation for module `\SB_GB'. 182s Generating RTLIL representation for module `\SB_LUT4'. 182s Generating RTLIL representation for module `\SB_CARRY'. 182s Generating RTLIL representation for module `\SB_DFF'. 182s Generating RTLIL representation for module `\SB_DFFE'. 182s Generating RTLIL representation for module `\SB_DFFSR'. 182s Generating RTLIL representation for module `\SB_DFFR'. 182s Generating RTLIL representation for module `\SB_DFFSS'. 182s Generating RTLIL representation for module `\SB_DFFS'. 182s Generating RTLIL representation for module `\SB_DFFESR'. 182s Generating RTLIL representation for module `\SB_DFFER'. 182s Generating RTLIL representation for module `\SB_DFFESS'. 182s Generating RTLIL representation for module `\SB_DFFES'. 182s Generating RTLIL representation for module `\SB_DFFN'. 182s Generating RTLIL representation for module `\SB_DFFNE'. 182s Generating RTLIL representation for module `\SB_DFFNSR'. 182s Generating RTLIL representation for module `\SB_DFFNR'. 182s Generating RTLIL representation for module `\SB_DFFNSS'. 182s Generating RTLIL representation for module `\SB_DFFNS'. 182s Generating RTLIL representation for module `\SB_DFFNESR'. 182s Generating RTLIL representation for module `\SB_DFFNER'. 182s Generating RTLIL representation for module `\SB_DFFNESS'. 182s Generating RTLIL representation for module `\SB_DFFNES'. 182s Generating RTLIL representation for module `\SB_RAM40_4K'. 182s Generating RTLIL representation for module `\SB_RAM40_4KNR'. 182s Generating RTLIL representation for module `\SB_RAM40_4KNW'. 182s Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. 182s Generating RTLIL representation for module `\ICESTORM_LC'. 182s Generating RTLIL representation for module `\SB_PLL40_CORE'. 182s Generating RTLIL representation for module `\SB_PLL40_PAD'. 182s Generating RTLIL representation for module `\SB_PLL40_2_PAD'. 182s Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. 182s Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. 182s Generating RTLIL representation for module `\SB_WARMBOOT'. 182s Generating RTLIL representation for module `\SB_SPRAM256KA'. 182s Generating RTLIL representation for module `\SB_HFOSC'. 182s Generating RTLIL representation for module `\SB_LFOSC'. 182s Generating RTLIL representation for module `\SB_RGBA_DRV'. 182s Generating RTLIL representation for module `\SB_LED_DRV_CUR'. 182s Generating RTLIL representation for module `\SB_RGB_DRV'. 182s Generating RTLIL representation for module `\SB_I2C'. 182s Generating RTLIL representation for module `\SB_SPI'. 182s Generating RTLIL representation for module `\SB_LEDDA_IP'. 182s Generating RTLIL representation for module `\SB_FILTER_50NS'. 182s Generating RTLIL representation for module `\SB_IO_I3C'. 182s Generating RTLIL representation for module `\SB_IO_OD'. 182s Generating RTLIL representation for module `\SB_MAC16'. 182s Generating RTLIL representation for module `\ICESTORM_RAM'. 182s Successfully finished Verilog frontend. 182s 182s 2.2. Executing HIERARCHY pass (managing design hierarchy). 182s 182s 2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\top'. 182s Generating RTLIL representation for module `\top'. 182s 182s 2.3.1. Analyzing design hierarchy.. 182s Top module: \top 182s 182s 2.3.2. Analyzing design hierarchy.. 182s Top module: \top 182s Removing unused module `$abstract\top'. 182s Removed 1 unused modules. 182s 182s 2.4. Executing PROC pass (convert processes to netlists). 182s 182s 2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 182s Cleaned up 0 empty switches. 182s 182s 2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 182s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241 in module SB_DFFNES. 182s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234 in module SB_DFFNESS. 182s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230 in module SB_DFFNER. 182s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223 in module SB_DFFNESR. 182s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220 in module SB_DFFNS. 182s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217 in module SB_DFFNSS. 182s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214 in module SB_DFFNR. 182s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211 in module SB_DFFNSR. 182s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203 in module SB_DFFES. 182s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196 in module SB_DFFESS. 182s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192 in module SB_DFFER. 182s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185 in module SB_DFFESR. 182s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182 in module SB_DFFS. 182s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179 in module SB_DFFSS. 182s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176 in module SB_DFFR. 182s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173 in module SB_DFFSR. 182s Removed a total of 0 dead cases. 182s 182s 2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 182s Removed 8 redundant assignments. 182s Promoted 25 assignments to connections. 182s 182s 2.4.4. Executing PROC_INIT pass (extract init attributes). 182s Found init rule in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 182s Set init value: \Q = 1'0 182s Found init rule in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 182s Set init value: \Q = 1'0 182s Found init rule in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 182s Set init value: \Q = 1'0 182s Found init rule in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 182s Set init value: \Q = 1'0 182s Found init rule in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 182s Set init value: \Q = 1'0 182s Found init rule in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 182s Set init value: \Q = 1'0 182s Found init rule in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 182s Set init value: \Q = 1'0 182s Found init rule in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 182s Set init value: \Q = 1'0 182s Found init rule in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 182s Set init value: \Q = 1'0 182s Found init rule in `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 182s Set init value: \Q = 1'0 182s Found init rule in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 182s Set init value: \Q = 1'0 182s Found init rule in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 182s Set init value: \Q = 1'0 182s Found init rule in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 182s Set init value: \Q = 1'0 182s Found init rule in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 182s Set init value: \Q = 1'0 182s Found init rule in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 182s Set init value: \Q = 1'0 182s Found init rule in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 182s Set init value: \Q = 1'0 182s Found init rule in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 182s Set init value: \Q = 1'0 182s Found init rule in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 182s Set init value: \Q = 1'0 182s Found init rule in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 182s Set init value: \Q = 1'0 182s Found init rule in `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 182s Set init value: \Q = 1'0 182s Found init rule in `\top.$proc$example.v:16$385'. 182s Set init value: \counter = 23'00000000000000000000000 182s 182s 2.4.5. Executing PROC_ARST pass (detect async resets in processes). 182s Found async reset \S in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 182s Found async reset \R in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 182s Found async reset \S in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 182s Found async reset \R in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 182s Found async reset \S in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 182s Found async reset \R in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 182s Found async reset \S in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 182s Found async reset \R in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 182s 182s 2.4.6. Executing PROC_ROM pass (convert switches to ROMs). 182s Converted 0 switches. 182s 182s 182s 2.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 182s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 182s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 182s 1/1: $0\Q[0:0] 182s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 182s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 182s 1/1: $0\Q[0:0] 182s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 182s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 182s 1/1: $0\Q[0:0] 182s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 182s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 182s 1/1: $0\Q[0:0] 182s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 182s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 182s 1/1: $0\Q[0:0] 182s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 182s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 182s 1/1: $0\Q[0:0] 182s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 182s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 182s 1/1: $0\Q[0:0] 182s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 182s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 182s 1/1: $0\Q[0:0] 182s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 182s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 182s 1/1: $0\Q[0:0] 182s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 182s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 182s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 182s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 182s 1/1: $0\Q[0:0] 182s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 182s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 182s 1/1: $0\Q[0:0] 182s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 182s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 182s 1/1: $0\Q[0:0] 182s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 182s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 182s 1/1: $0\Q[0:0] 182s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 182s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 182s 1/1: $0\Q[0:0] 182s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 182s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 182s 1/1: $0\Q[0:0] 182s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 182s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 182s 1/1: $0\Q[0:0] 182s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 182s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 182s 1/1: $0\Q[0:0] 182s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 182s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 182s 1/1: $0\Q[0:0] 182s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 182s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 182s Creating decoders for process `\top.$proc$example.v:16$385'. 182s Creating decoders for process `\top.$proc$example.v:19$381'. 182s 182s 2.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). 182s 182s 2.4.9. Executing PROC_DFF pass (convert process syncs to FFs). 182s Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 182s created $adff cell `$procdff$430' with negative edge clock and positive level reset. 182s Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 182s created $dff cell `$procdff$431' with negative edge clock. 182s Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 182s created $adff cell `$procdff$432' with negative edge clock and positive level reset. 182s Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 182s created $dff cell `$procdff$433' with negative edge clock. 182s Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 182s created $adff cell `$procdff$434' with negative edge clock and positive level reset. 182s Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 182s created $dff cell `$procdff$435' with negative edge clock. 182s Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 182s created $adff cell `$procdff$436' with negative edge clock and positive level reset. 182s Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 182s created $dff cell `$procdff$437' with negative edge clock. 182s Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 182s created $dff cell `$procdff$438' with negative edge clock. 182s Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 182s created $dff cell `$procdff$439' with negative edge clock. 182s Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 182s created $adff cell `$procdff$440' with positive edge clock and positive level reset. 182s Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 182s created $dff cell `$procdff$441' with positive edge clock. 182s Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 182s created $adff cell `$procdff$442' with positive edge clock and positive level reset. 182s Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 182s created $dff cell `$procdff$443' with positive edge clock. 182s Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 182s created $adff cell `$procdff$444' with positive edge clock and positive level reset. 182s Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 182s created $dff cell `$procdff$445' with positive edge clock. 182s Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 182s created $adff cell `$procdff$446' with positive edge clock and positive level reset. 182s Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 182s created $dff cell `$procdff$447' with positive edge clock. 182s Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 182s created $dff cell `$procdff$448' with positive edge clock. 182s Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 182s created $dff cell `$procdff$449' with positive edge clock. 182s Creating register for signal `\top.\counter' using process `\top.$proc$example.v:19$381'. 182s created $dff cell `$procdff$450' with positive edge clock. 182s Creating register for signal `\top.\outcnt' using process `\top.$proc$example.v:19$381'. 182s created $dff cell `$procdff$451' with positive edge clock. 182s 182s 2.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 182s 182s 2.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 182s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 182s Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 182s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 182s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 182s Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 182s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 182s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 182s Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 182s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 182s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 182s Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 182s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 182s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 182s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 182s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 182s Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 182s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 182s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 182s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 182s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 182s Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 182s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 182s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 182s Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 182s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 182s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 182s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 182s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 182s Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 182s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 182s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 182s Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 182s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 182s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 182s Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 182s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 182s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 182s Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 182s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 182s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 182s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 182s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 182s Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 182s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 182s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 182s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 182s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 182s Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 182s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 182s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 182s Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 182s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 182s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 182s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 182s Removing empty process `top.$proc$example.v:16$385'. 182s Removing empty process `top.$proc$example.v:19$381'. 182s Cleaned up 18 empty switches. 182s 182s 2.4.12. Executing OPT_EXPR pass (perform const folding). 182s Optimizing module top. 182s 182s 182s 2.5. Executing FLATTEN pass (flatten design). 182s 182s 2.6. Executing TRIBUF pass. 182s 182s 2.7. Executing DEMINOUT pass (demote inout ports to input or output). 182s 182s 2.8. Executing OPT_EXPR pass (perform const folding). 182s Optimizing module top. 182s 182s 2.9. Executing OPT_CLEAN pass (remove unused cells and wires). 182s Finding unused cells or wires in module \top.. 182s Removed 0 unused cells and 3 unused wires. 182s 182s 182s 2.10. Executing CHECK pass (checking for obvious problems). 182s Checking module top... 182s Found and reported 0 problems. 182s 182s 2.11. Executing OPT pass (performing simple optimizations). 182s 182s 2.11.1. Executing OPT_EXPR pass (perform const folding). 182s Optimizing module top. 182s 182s 2.11.2. Executing OPT_MERGE pass (detect identical cells). 182s Finding identical cells in module `\top'. 182s Removed a total of 0 cells. 182s 182s 2.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 182s Running muxtree optimizer on module \top.. 182s Creating internal representation of mux trees. 182s No muxes found in this module. 182s Removed 0 multiplexer ports. 182s 182s 2.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 182s Optimizing cells in module \top. 182s Performed a total of 0 changes. 182s 182s 2.11.5. Executing OPT_MERGE pass (detect identical cells). 182s Finding identical cells in module `\top'. 182s Removed a total of 0 cells. 182s 182s 2.11.6. Executing OPT_DFF pass (perform DFF optimizations). 182s 182s 2.11.7. Executing OPT_CLEAN pass (remove unused cells and wires). 182s Finding unused cells or wires in module \top.. 182s 182s 2.11.8. Executing OPT_EXPR pass (perform const folding). 182s Optimizing module top. 182s 182s 2.11.9. Finished OPT passes. (There is nothing left to do.) 182s 182s 2.12. Executing FSM pass (extract and optimize FSM). 182s 182s 2.12.1. Executing FSM_DETECT pass (finding FSMs in design). 182s 182s 2.12.2. Executing FSM_EXTRACT pass (extracting FSM from design). 182s 182s 2.12.3. Executing FSM_OPT pass (simple optimizations of FSMs). 182s 182s 2.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). 182s Finding unused cells or wires in module \top.. 182s 182s 2.12.5. Executing FSM_OPT pass (simple optimizations of FSMs). 182s 182s 2.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 182s 182s 2.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 182s 182s 2.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 182s 182s 2.13. Executing OPT pass (performing simple optimizations). 182s 182s 2.13.1. Executing OPT_EXPR pass (perform const folding). 182s Optimizing module top. 182s 182s 2.13.2. Executing OPT_MERGE pass (detect identical cells). 182s Finding identical cells in module `\top'. 182s Removed a total of 0 cells. 182s 182s 2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 182s Running muxtree optimizer on module \top.. 182s Creating internal representation of mux trees. 182s No muxes found in this module. 182s Removed 0 multiplexer ports. 182s 182s 2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 182s Optimizing cells in module \top. 182s Performed a total of 0 changes. 182s 182s 2.13.5. Executing OPT_MERGE pass (detect identical cells). 182s Finding identical cells in module `\top'. 182s Removed a total of 0 cells. 182s 182s 2.13.6. Executing OPT_DFF pass (perform DFF optimizations). 182s 182s 2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). 182s Finding unused cells or wires in module \top.. 182s 182s 2.13.8. Executing OPT_EXPR pass (perform const folding). 182s Optimizing module top. 182s 182s 2.13.9. Finished OPT passes. (There is nothing left to do.) 182s 182s 2.14. Executing WREDUCE pass (reducing word size of cells). 182s Removed top 31 bits (of 32) from port B of cell top.$add$example.v:20$382 ($add). 182s Removed top 9 bits (of 32) from port Y of cell top.$add$example.v:20$382 ($add). 182s Removed top 30 bits (of 32) from port A of cell top.$shl$example.v:24$384 ($shl). 182s Removed top 24 bits (of 32) from port Y of cell top.$shl$example.v:24$384 ($shl). 182s Removed top 24 bits (of 32) from wire top.$shl$example.v:24$384_Y. 182s 182s 2.15. Executing PEEPOPT pass (run peephole optimizers). 182s 182s 2.16. Executing OPT_CLEAN pass (remove unused cells and wires). 182s Finding unused cells or wires in module \top.. 182s Removed 0 unused cells and 3 unused wires. 182s 182s 182s 2.17. Executing SHARE pass (SAT-based resource sharing). 182s 182s 2.18. Executing TECHMAP pass (map to technology primitives). 182s 182s 2.18.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v 182s Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation. 182s Generating RTLIL representation for module `\_90_lut_cmp_'. 182s Successfully finished Verilog frontend. 182s 182s 2.18.2. Continuing TECHMAP pass. 182s No more expansions possible. 182s 182s 182s 2.19. Executing OPT_EXPR pass (perform const folding). 182s Optimizing module top. 182s 182s 2.20. Executing OPT_CLEAN pass (remove unused cells and wires). 182s Finding unused cells or wires in module \top.. 182s 182s 2.21. Executing ALUMACC pass (create $alu and $macc cells). 182s Extracting $alu and $macc cells in module top: 182s creating $macc model for $add$example.v:20$382 ($add). 182s creating $alu model for $macc $add$example.v:20$382. 182s creating $alu cell for $add$example.v:20$382: $auto$alumacc.cc:485:replace_alu$454 182s created 1 $alu and 0 $macc cells. 182s 182s 2.22. Executing OPT pass (performing simple optimizations). 182s 182s 2.22.1. Executing OPT_EXPR pass (perform const folding). 182s Optimizing module top. 182s 182s 2.22.2. Executing OPT_MERGE pass (detect identical cells). 182s Finding identical cells in module `\top'. 182s Removed a total of 0 cells. 182s 182s 2.22.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 182s Running muxtree optimizer on module \top.. 182s Creating internal representation of mux trees. 182s No muxes found in this module. 182s Removed 0 multiplexer ports. 182s 182s 2.22.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 182s Optimizing cells in module \top. 182s Performed a total of 0 changes. 182s 182s 2.22.5. Executing OPT_MERGE pass (detect identical cells). 182s Finding identical cells in module `\top'. 182s Removed a total of 0 cells. 182s 182s 2.22.6. Executing OPT_DFF pass (perform DFF optimizations). 182s 182s 2.22.7. Executing OPT_CLEAN pass (remove unused cells and wires). 182s Finding unused cells or wires in module \top.. 182s 182s 2.22.8. Executing OPT_EXPR pass (perform const folding). 182s Optimizing module top. 182s 182s 2.22.9. Finished OPT passes. (There is nothing left to do.) 182s 182s 2.23. Executing MEMORY pass. 182s 182s 2.23.1. Executing OPT_MEM pass (optimize memories). 182s Performed a total of 0 transformations. 182s 182s 2.23.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). 182s Performed a total of 0 transformations. 182s 182s 2.23.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 182s 182s 2.23.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 182s 182s 2.23.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 182s 182s 2.23.6. Executing OPT_CLEAN pass (remove unused cells and wires). 182s Finding unused cells or wires in module \top.. 182s 182s 2.23.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 182s 182s 2.23.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). 182s Performed a total of 0 transformations. 182s 182s 2.23.9. Executing OPT_CLEAN pass (remove unused cells and wires). 182s Finding unused cells or wires in module \top.. 182s 182s 2.23.10. Executing MEMORY_COLLECT pass (generating $mem cells). 182s 182s 2.24. Executing OPT_CLEAN pass (remove unused cells and wires). 182s Finding unused cells or wires in module \top.. 182s 182s 2.25. Executing MEMORY_LIBMAP pass (mapping memories to cells). 182s 182s 2.26. Executing TECHMAP pass (map to technology primitives). 182s 182s 2.26.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v 182s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation. 182s Generating RTLIL representation for module `\$__ICE40_RAM4K_'. 182s Successfully finished Verilog frontend. 182s 182s 2.26.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/spram_map.v 182s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/spram_map.v' to AST representation. 182s Generating RTLIL representation for module `\$__ICE40_SPRAM_'. 182s Successfully finished Verilog frontend. 182s 182s 2.26.3. Continuing TECHMAP pass. 182s No more expansions possible. 182s 182s 182s 2.27. Executing ICE40_BRAMINIT pass. 182s 182s 2.28. Executing OPT pass (performing simple optimizations). 182s 182s 2.28.1. Executing OPT_EXPR pass (perform const folding). 182s Optimizing module top. 182s 182s 2.28.2. Executing OPT_MERGE pass (detect identical cells). 182s Finding identical cells in module `\top'. 182s Removed a total of 0 cells. 182s 182s 2.28.3. Executing OPT_DFF pass (perform DFF optimizations). 182s 182s 2.28.4. Executing OPT_CLEAN pass (remove unused cells and wires). 182s Finding unused cells or wires in module \top.. 182s 182s 2.28.5. Finished fast OPT passes. 182s 182s 2.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 182s 182s 2.30. Executing OPT pass (performing simple optimizations). 182s 182s 2.30.1. Executing OPT_EXPR pass (perform const folding). 182s Optimizing module top. 182s 182s 2.30.2. Executing OPT_MERGE pass (detect identical cells). 182s Finding identical cells in module `\top'. 182s Removed a total of 0 cells. 182s 182s 2.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 182s Running muxtree optimizer on module \top.. 182s Creating internal representation of mux trees. 182s No muxes found in this module. 182s Removed 0 multiplexer ports. 182s 182s 2.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 182s Optimizing cells in module \top. 182s Performed a total of 0 changes. 182s 182s 2.30.5. Executing OPT_MERGE pass (detect identical cells). 182s Finding identical cells in module `\top'. 182s Removed a total of 0 cells. 182s 182s 2.30.6. Executing OPT_DFF pass (perform DFF optimizations). 182s 182s 2.30.7. Executing OPT_CLEAN pass (remove unused cells and wires). 182s Finding unused cells or wires in module \top.. 182s 182s 2.30.8. Executing OPT_EXPR pass (perform const folding). 182s Optimizing module top. 182s 182s 2.30.9. Finished OPT passes. (There is nothing left to do.) 182s 182s 2.31. Executing ICE40_WRAPCARRY pass (wrap carries). 182s 182s 2.32. Executing TECHMAP pass (map to technology primitives). 182s 182s 2.32.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v 182s Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation. 182s Generating RTLIL representation for module `\_90_simplemap_bool_ops'. 182s Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. 182s Generating RTLIL representation for module `\_90_simplemap_logic_ops'. 182s Generating RTLIL representation for module `\_90_simplemap_compare_ops'. 182s Generating RTLIL representation for module `\_90_simplemap_various'. 182s Generating RTLIL representation for module `\_90_simplemap_registers'. 182s Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. 182s Generating RTLIL representation for module `\_90_shift_shiftx'. 182s Generating RTLIL representation for module `\_90_fa'. 182s Generating RTLIL representation for module `\_90_lcu'. 182s Generating RTLIL representation for module `\_90_alu'. 182s Generating RTLIL representation for module `\_90_macc'. 182s Generating RTLIL representation for module `\_90_alumacc'. 182s Generating RTLIL representation for module `\$__div_mod_u'. 182s Generating RTLIL representation for module `\$__div_mod_trunc'. 182s Generating RTLIL representation for module `\_90_div'. 182s Generating RTLIL representation for module `\_90_mod'. 182s Generating RTLIL representation for module `\$__div_mod_floor'. 182s Generating RTLIL representation for module `\_90_divfloor'. 182s Generating RTLIL representation for module `\_90_modfloor'. 182s Generating RTLIL representation for module `\_90_pow'. 182s Generating RTLIL representation for module `\_90_pmux'. 182s Generating RTLIL representation for module `\_90_demux'. 182s Generating RTLIL representation for module `\_90_lut'. 182s Successfully finished Verilog frontend. 182s 182s 2.32.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v 182s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation. 182s Generating RTLIL representation for module `\_80_ice40_alu'. 182s Successfully finished Verilog frontend. 182s 182s 2.32.3. Continuing TECHMAP pass. 182s Using template $paramod$constmap:5c4fb84a0fc6ae5c0d4120d25a7a267fccccc7a8$paramod$bc0ada8317992808a26d9434f659d5d0f7acd7e1\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. 182s Using template $paramod$36fdbc18fab0758c8553dda57bd33e3f8f3e8765\_80_ice40_alu for cells of type $alu. 182s Using extmapper simplemap for cells of type $dff. 182s Using extmapper simplemap for cells of type $xor. 182s Using extmapper simplemap for cells of type $not. 182s Using extmapper simplemap for cells of type $pos. 182s No more expansions possible. 182s 182s 182s 2.33. Executing OPT pass (performing simple optimizations). 182s 182s 2.33.1. Executing OPT_EXPR pass (perform const folding). 182s Optimizing module top. 182s 182s 182s 2.33.2. Executing OPT_MERGE pass (detect identical cells). 182s Finding identical cells in module `\top'. 182s 182s Removed a total of 1 cells. 182s 182s 2.33.3. Executing OPT_DFF pass (perform DFF optimizations). 182s 182s 2.33.4. Executing OPT_CLEAN pass (remove unused cells and wires). 182s Finding unused cells or wires in module \top.. 182s Removed 23 unused cells and 22 unused wires. 182s 182s 182s 2.33.5. Finished fast OPT passes. 182s 182s 2.34. Executing ICE40_OPT pass (performing simple optimizations). 182s 182s 2.34.1. Running ICE40 specific optimizations. 182s Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$454.slice[0].carry: CO=\counter [0] 182s 182s 2.34.2. Executing OPT_EXPR pass (perform const folding). 182s Optimizing module top. 182s 182s 2.34.3. Executing OPT_MERGE pass (detect identical cells). 182s Finding identical cells in module `\top'. 182s Removed a total of 0 cells. 182s 182s 2.34.4. Executing OPT_DFF pass (perform DFF optimizations). 182s 182s 2.34.5. Executing OPT_CLEAN pass (remove unused cells and wires). 182s Finding unused cells or wires in module \top.. 182s 182s 2.34.6. Rerunning OPT passes. (Removed registers in this run.) 182s 182s 2.34.7. Running ICE40 specific optimizations. 182s 182s 2.34.8. Executing OPT_EXPR pass (perform const folding). 182s Optimizing module top. 182s 182s 2.34.9. Executing OPT_MERGE pass (detect identical cells). 182s Finding identical cells in module `\top'. 182s Removed a total of 0 cells. 182s 182s 2.34.10. Executing OPT_DFF pass (perform DFF optimizations). 182s 182s 2.34.11. Executing OPT_CLEAN pass (remove unused cells and wires). 182s Finding unused cells or wires in module \top.. 182s 182s 2.34.12. Finished OPT passes. (There is nothing left to do.) 182s 182s 2.35. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 182s 182s 2.36. Executing TECHMAP pass (map to technology primitives). 182s 182s 2.36.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 182s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 182s Generating RTLIL representation for module `\$_DFF_N_'. 182s Generating RTLIL representation for module `\$_DFF_P_'. 182s Generating RTLIL representation for module `\$_DFFE_NP_'. 182s Generating RTLIL representation for module `\$_DFFE_PP_'. 182s Generating RTLIL representation for module `\$_DFF_NP0_'. 182s Generating RTLIL representation for module `\$_DFF_NP1_'. 182s Generating RTLIL representation for module `\$_DFF_PP0_'. 182s Generating RTLIL representation for module `\$_DFF_PP1_'. 182s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 182s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 182s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 182s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 182s Generating RTLIL representation for module `\$_SDFF_NP0_'. 182s Generating RTLIL representation for module `\$_SDFF_NP1_'. 182s Generating RTLIL representation for module `\$_SDFF_PP0_'. 182s Generating RTLIL representation for module `\$_SDFF_PP1_'. 182s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 182s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 182s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 182s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 182s Successfully finished Verilog frontend. 182s 182s 2.36.2. Continuing TECHMAP pass. 182s Using template \$_DFF_P_ for cells of type $_DFF_P_. 182s No more expansions possible. 182s 182s 182s 2.37. Executing OPT_EXPR pass (perform const folding). 182s Optimizing module top. 182s 182s 2.38. Executing SIMPLEMAP pass (map simple cells to gate primitives). 182s Mapping top.$auto$alumacc.cc:485:replace_alu$454.slice[0].carry ($lut). 182s 182s 2.39. Executing ICE40_OPT pass (performing simple optimizations). 182s 182s 2.39.1. Running ICE40 specific optimizations. 182s 182s 2.39.2. Executing OPT_EXPR pass (perform const folding). 182s Optimizing module top. 182s 182s 182s 2.39.3. Executing OPT_MERGE pass (detect identical cells). 182s Finding identical cells in module `\top'. 182s Removed a total of 0 cells. 182s 182s 2.39.4. Executing OPT_DFF pass (perform DFF optimizations). 182s 182s 2.39.5. Executing OPT_CLEAN pass (remove unused cells and wires). 182s Finding unused cells or wires in module \top.. 182s Removed 0 unused cells and 108 unused wires. 182s 182s 182s 2.39.6. Rerunning OPT passes. (Removed registers in this run.) 182s 182s 2.39.7. Running ICE40 specific optimizations. 182s 182s 2.39.8. Executing OPT_EXPR pass (perform const folding). 182s Optimizing module top. 182s 182s 2.39.9. Executing OPT_MERGE pass (detect identical cells). 182s Finding identical cells in module `\top'. 182s Removed a total of 0 cells. 182s 182s 2.39.10. Executing OPT_DFF pass (perform DFF optimizations). 182s 182s 2.39.11. Executing OPT_CLEAN pass (remove unused cells and wires). 182s Finding unused cells or wires in module \top.. 182s 182s 2.39.12. Finished OPT passes. (There is nothing left to do.) 182s 182s 2.40. Executing TECHMAP pass (map to technology primitives). 182s 182s 2.40.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v 182s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation. 182s Generating RTLIL representation for module `\$_DLATCH_N_'. 182s Generating RTLIL representation for module `\$_DLATCH_P_'. 182s Successfully finished Verilog frontend. 182s 182s 2.40.2. Continuing TECHMAP pass. 182s No more expansions possible. 182s 182s 182s 2.41. Executing ABC pass (technology mapping using ABC). 182s 182s 2.41.1. Extracting gate netlist of module `\top' to `/input.blif'.. 182s Extracted 14 gates and 19 wires to a netlist network with 4 inputs and 9 outputs. 182s 182s 2.41.1.1. Executing ABC. 183s Running ABC command: "berkeley-abc" -s -f /abc.script 2>&1 183s ABC: ABC command line: "source /abc.script". 183s ABC: 183s ABC: + read_blif /input.blif 183s ABC: + read_lut /lutdefs.txt 183s ABC: + strash 183s ABC: + &get -n 183s ABC: + &fraig -x 183s ABC: + &put 183s ABC: + scorr 183s ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). 183s ABC: + dc2 183s ABC: + dretime 183s ABC: + strash 183s ABC: + dch -f 183s ABC: + if 183s ABC: + mfs2 183s ABC: + lutpack -S 1 183s ABC: + dress /input.blif 183s ABC: Total number of equiv classes = 10. 183s ABC: Participating nodes from both networks = 19. 183s ABC: Participating nodes from the first network = 9. ( 90.00 % of nodes) 183s ABC: Participating nodes from the second network = 10. ( 100.00 % of nodes) 183s ABC: Node pairs (any polarity) = 9. ( 90.00 % of names can be moved) 183s ABC: Node pairs (same polarity) = 9. ( 90.00 % of names can be moved) 183s ABC: Total runtime = 0.01 sec 183s ABC: + write_blif /output.blif 183s 183s 2.41.1.2. Re-integrating ABC results. 183s ABC RESULTS: $lut cells: 9 183s ABC RESULTS: internal signals: 6 183s ABC RESULTS: input signals: 4 183s ABC RESULTS: output signals: 9 183s Removing temp directory. 183s 183s 2.42. Executing ICE40_WRAPCARRY pass (wrap carries). 183s 183s 2.43. Executing TECHMAP pass (map to technology primitives). 183s 183s 2.43.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 183s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 183s Generating RTLIL representation for module `\$_DFF_N_'. 183s Generating RTLIL representation for module `\$_DFF_P_'. 183s Generating RTLIL representation for module `\$_DFFE_NP_'. 183s Generating RTLIL representation for module `\$_DFFE_PP_'. 183s Generating RTLIL representation for module `\$_DFF_NP0_'. 183s Generating RTLIL representation for module `\$_DFF_NP1_'. 183s Generating RTLIL representation for module `\$_DFF_PP0_'. 183s Generating RTLIL representation for module `\$_DFF_PP1_'. 183s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 183s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 183s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 183s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 183s Generating RTLIL representation for module `\$_SDFF_NP0_'. 183s Generating RTLIL representation for module `\$_SDFF_NP1_'. 183s Generating RTLIL representation for module `\$_SDFF_PP0_'. 183s Generating RTLIL representation for module `\$_SDFF_PP1_'. 183s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 183s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 183s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 183s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 183s Successfully finished Verilog frontend. 183s 183s 2.43.2. Continuing TECHMAP pass. 183s No more expansions possible. 183s 183s Removed 1 unused cells and 16 unused wires. 183s 183s 2.44. Executing OPT_LUT pass (optimize LUTs). 183s Discovering LUTs. 183s Number of LUTs: 31 183s 1-LUT 1 183s 2-LUT 1 183s 3-LUT 29 183s with \SB_CARRY (#0) 21 183s with \SB_CARRY (#1) 21 183s 183s Eliminating LUTs. 183s Number of LUTs: 31 183s 1-LUT 1 183s 2-LUT 1 183s 3-LUT 29 183s with \SB_CARRY (#0) 21 183s with \SB_CARRY (#1) 21 183s 183s Combining LUTs. 183s Number of LUTs: 31 183s 1-LUT 1 183s 2-LUT 1 183s 3-LUT 29 183s with \SB_CARRY (#0) 21 183s with \SB_CARRY (#1) 21 183s 183s Eliminated 0 LUTs. 183s Combined 0 LUTs. 183s 183s 183s 2.45. Executing TECHMAP pass (map to technology primitives). 183s 183s 2.45.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v 183s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation. 183s Generating RTLIL representation for module `\$lut'. 183s Successfully finished Verilog frontend. 183s 183s 2.45.2. Continuing TECHMAP pass. 183s Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut. 183s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut. 183s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut. 183s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. 183s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. 183s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut. 183s No more expansions possible. 183s 183s Removed 0 unused cells and 62 unused wires. 183s 183s 2.46. Executing AUTONAME pass. 183s Renamed 124 objects in module top (4 iterations). 183s 183s 183s 2.47. Executing HIERARCHY pass (managing design hierarchy). 183s 183s 2.47.1. Analyzing design hierarchy.. 183s Top module: \top 183s 183s 2.47.2. Analyzing design hierarchy.. 183s Top module: \top 183s Removed 0 unused modules. 183s 183s 2.48. Printing statistics. 183s 183s === top === 183s 183s Number of wires: 13 183s Number of wire bits: 81 183s Number of public wires: 13 183s Number of public wire bits: 81 183s Number of memories: 0 183s Number of memory bits: 0 183s Number of processes: 0 183s Number of cells: 78 183s SB_CARRY 21 183s SB_DFF 26 183s SB_LUT4 31 183s 183s 2.49. Executing CHECK pass (checking for obvious problems). 183s Checking module top... 183s Found and reported 0 problems. 183s 183s 2.50. Executing JSON backend. 183s 183s End of script. Logfile hash: 681b620f38, CPU: user 0.70s system 0.02s, MEM: 20.00 MB peak 183s Yosys 0.23 (git sha1 7ce5011c24b) 183s Time spent: 51% 13x read_verilog (0 sec), 22% 1x abc (0 sec), ... 183s nextpnr-ice40 --hx1k --package tq144 --asc example.asc --pcf icezum.pcf --json example.json 183s Info: constrained 'LED0' to bel 'X13/Y9/io1' 183s Info: constrained 'LED1' to bel 'X13/Y11/io0' 183s Info: constrained 'LED2' to bel 'X13/Y11/io1' 183s Info: constrained 'LED3' to bel 'X13/Y12/io0' 183s Info: constrained 'LED4' to bel 'X13/Y12/io1' 183s Info: constrained 'LED5' to bel 'X13/Y13/io0' 183s Info: constrained 'LED6' to bel 'X13/Y13/io1' 183s Info: constrained 'LED7' to bel 'X13/Y14/io0' 183s Info: constrained 'clk' to bel 'X0/Y8/io1' 183s 183s Info: Packing constants.. 183s Info: Packing IOs.. 183s Info: Packing LUT-FFs.. 183s Info: 8 LCs used as LUT4 only 183s Info: 23 LCs used as LUT4 and DFF 183s Info: Packing non-LUT FFs.. 183s Info: 3 LCs used as DFF only 183s Info: Packing carries.. 183s Info: 0 LCs used as CARRY only 183s Info: Packing indirect carry+LUT pairs... 183s Info: 0 LUTs merged into carry LCs 183s Info: Packing RAMs.. 183s Info: Placing PLLs.. 183s Info: Packing special functions.. 183s Info: Packing PLLs.. 183s Info: Promoting globals.. 183s Info: promoting clk$SB_IO_IN (fanout 26) 183s Info: Constraining chains... 183s Info: 1 LCs used to legalise carry chains. 183s Info: Checksum: 0x62a7ba7d 183s 183s Info: Annotating ports with timing budgets for target frequency 12.00 MHz 183s Info: Checksum: 0xe1af17d8 183s 183s Info: Device utilisation: 183s Info: ICESTORM_LC: 37/ 1280 2% 183s Info: ICESTORM_RAM: 0/ 16 0% 183s Info: SB_IO: 9/ 112 8% 183s Info: SB_GB: 1/ 8 12% 183s Info: ICESTORM_PLL: 0/ 1 0% 183s Info: SB_WARMBOOT: 0/ 1 0% 183s 183s Info: Placed 9 cells based on constraints. 183s Info: Creating initial analytic placement for 14 cells, random placement wirelen = 180. 183s Info: at initial placer iter 0, wirelen = 27 183s Info: at initial placer iter 1, wirelen = 24 183s Info: at initial placer iter 2, wirelen = 26 183s Info: at initial placer iter 3, wirelen = 24 183s Info: Running main analytical placer, max placement attempts per cell = 10000. 183s Info: at iteration #1, type ICESTORM_LC: wirelen solved = 26, spread = 31, legal = 30; time = 0.00s 183s Info: at iteration #1, type SB_GB: wirelen solved = 30, spread = 30, legal = 30; time = 0.00s 183s Info: at iteration #1, type ALL: wirelen solved = 15, spread = 18, legal = 33; time = 0.00s 183s Info: at iteration #2, type ICESTORM_LC: wirelen solved = 25, spread = 43, legal = 43; time = 0.00s 183s Info: at iteration #2, type SB_GB: wirelen solved = 43, spread = 43, legal = 43; time = 0.00s 183s Info: at iteration #2, type ALL: wirelen solved = 25, spread = 43, legal = 43; time = 0.00s 183s Info: at iteration #3, type ICESTORM_LC: wirelen solved = 29, spread = 43, legal = 43; time = 0.00s 183s Info: at iteration #3, type SB_GB: wirelen solved = 43, spread = 43, legal = 43; time = 0.00s 183s Info: at iteration #3, type ALL: wirelen solved = 29, spread = 43, legal = 43; time = 0.00s 183s Info: at iteration #4, type ICESTORM_LC: wirelen solved = 27, spread = 47, legal = 47; time = 0.00s 183s Info: at iteration #4, type SB_GB: wirelen solved = 47, spread = 47, legal = 47; time = 0.00s 183s Info: at iteration #4, type ALL: wirelen solved = 27, spread = 47, legal = 47; time = 0.00s 183s Info: at iteration #5, type ICESTORM_LC: wirelen solved = 29, spread = 46, legal = 46; time = 0.00s 183s Info: at iteration #5, type SB_GB: wirelen solved = 46, spread = 46, legal = 46; time = 0.00s 183s Info: at iteration #5, type ALL: wirelen solved = 29, spread = 44, legal = 44; time = 0.00s 183s Info: at iteration #6, type ICESTORM_LC: wirelen solved = 27, spread = 47, legal = 47; time = 0.00s 183s Info: at iteration #6, type SB_GB: wirelen solved = 47, spread = 47, legal = 47; time = 0.00s 183s Info: at iteration #6, type ALL: wirelen solved = 29, spread = 49, legal = 49; time = 0.00s 183s Info: HeAP Placer Time: 0.03s 183s Info: of which solving equations: 0.03s 183s Info: of which spreading cells: 0.00s 183s Info: of which strict legalisation: 0.00s 183s 183s Info: Running simulated annealing placer for refinement. 183s Info: at iteration #1: temp = 0.000000, timing cost = 3, wirelen = 33 183s Info: at iteration #5: temp = 0.000000, timing cost = 3, wirelen = 24 183s Info: at iteration #5: temp = 0.000000, timing cost = 3, wirelen = 24 183s Info: SA placement time 0.00s 183s 183s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 195.01 MHz (PASS at 12.00 MHz) 183s 183s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> : 2.74 ns 183s 183s Info: Slack histogram: 183s Info: legend: * represents 1 endpoint(s) 183s Info: + represents [1,1) endpoint(s) 183s Info: [ 78205, 78389) |** 183s Info: [ 78389, 78573) |* 183s Info: [ 78573, 78757) |** 183s Info: [ 78757, 78941) |** 183s Info: [ 78941, 79125) | 183s Info: [ 79125, 79309) | 183s Info: [ 79309, 79493) |** 183s Info: [ 79493, 79677) |* 183s Info: [ 79677, 79861) |** 183s Info: [ 79861, 80045) |* 183s Info: [ 80045, 80229) |** 183s Info: [ 80229, 80413) | 183s Info: [ 80413, 80597) |*** 183s Info: [ 80597, 80781) |* 183s Info: [ 80781, 80965) |* 183s Info: [ 80965, 81149) |** 183s Info: [ 81149, 81333) |******* 183s Info: [ 81333, 81517) | 183s Info: [ 81517, 81701) | 183s Info: [ 81701, 81885) |*************************** 183s Info: Checksum: 0xa1bb4ca5 183s 183s Info: Routing.. 183s Info: Setting up routing queue. 183s Info: Routing 108 arcs. 183s Info: | (re-)routed arcs | delta | remaining| time spent | 183s Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| 183s Info: 108 | 0 89 | 0 89 | 0| 0.00 0.00| 183s Info: Routing complete. 183s Info: Router1 time 0.00s 183s Info: Checksum: 0x4cb9f475 183s 183s Info: Critical path report for clock 'clk$SB_IO_IN_$glb_clk' (posedge -> posedge): 183s Info: curr total 183s Info: 0.5 0.5 Source counter_SB_LUT4_I3_LC.O 183s Info: 0.6 1.1 Net counter[0] budget 79.292999 ns (12,10) -> (11,10) 183s Info: Sink $nextpnr_ICESTORM_LC_0.I1 183s Info: Defined in: 183s Info: example.v:20.14-20.25 183s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 183s Info: 0.3 1.4 Source $nextpnr_ICESTORM_LC_0.COUT 183s Info: 0.0 1.4 Net $nextpnr_ICESTORM_LC_0$O budget 0.000000 ns (11,10) -> (11,10) 183s Info: Sink counter_SB_LUT4_I2_3_LC.CIN 183s Info: 0.1 1.5 Source counter_SB_LUT4_I2_3_LC.COUT 183s Info: 0.0 1.5 Net counter_SB_CARRY_CI_CO[2] budget 0.000000 ns (11,10) -> (11,10) 183s Info: Sink counter_SB_LUT4_I2_21_LC.CIN 183s Info: Defined in: 183s Info: example.v:20.14-20.25 183s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 183s Info: 0.1 1.6 Source counter_SB_LUT4_I2_21_LC.COUT 183s Info: 0.0 1.6 Net counter_SB_CARRY_CI_CO[3] budget 0.000000 ns (11,10) -> (11,10) 183s Info: Sink counter_SB_LUT4_I2_20_LC.CIN 183s Info: Defined in: 183s icetime -d hx1k -mtr example.rpt example.asc 183s // Reading input .asc file.. 183s // Reading 1k chipdb file.. 183s Info: example.v:20.14-20.25 183s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 183s Info: 0.1 1.8 Source counter_SB_LUT4_I2_20_LC.COUT 183s Info: 0.0 1.8 Net counter_SB_CARRY_CI_CO[4] budget 0.000000 ns (11,10) -> (11,10) 183s Info: Sink counter_SB_LUT4_I2_19_LC.CIN 183s Info: Defined in: 183s Info: example.v:20.14-20.25 183s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 183s Info: 0.1 1.9 Source counter_SB_LUT4_I2_19_LC.COUT 183s Info: 0.0 1.9 Net counter_SB_CARRY_CI_CO[5] budget 0.000000 ns (11,10) -> (11,10) 183s Info: Sink counter_SB_LUT4_I2_18_LC.CIN 183s Info: Defined in: 183s Info: example.v:20.14-20.25 183s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 183s Info: 0.1 2.0 Source counter_SB_LUT4_I2_18_LC.COUT 183s Info: 0.0 2.0 Net counter_SB_CARRY_CI_CO[6] budget 0.000000 ns (11,10) -> (11,10) 183s Info: Sink counter_SB_LUT4_I2_17_LC.CIN 183s Info: Defined in: 183s Info: example.v:20.14-20.25 183s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 183s Info: 0.1 2.1 Source counter_SB_LUT4_I2_17_LC.COUT 183s Info: 0.0 2.1 Net counter_SB_CARRY_CI_CO[7] budget 0.000000 ns (11,10) -> (11,10) 183s Info: Sink counter_SB_LUT4_I2_16_LC.CIN 183s Info: Defined in: 183s Info: example.v:20.14-20.25 183s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 183s Info: 0.1 2.3 Source counter_SB_LUT4_I2_16_LC.COUT 183s Info: 0.2 2.5 Net counter_SB_CARRY_CI_CO[8] budget 0.190000 ns (11,10) -> (11,11) 183s Info: Sink counter_SB_LUT4_I2_15_LC.CIN 183s Info: Defined in: 183s Info: example.v:20.14-20.25 183s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 183s Info: 0.1 2.6 Source counter_SB_LUT4_I2_15_LC.COUT 183s Info: 0.0 2.6 Net counter_SB_CARRY_CI_CO[9] budget 0.000000 ns (11,11) -> (11,11) 183s Info: Sink counter_SB_LUT4_I2_14_LC.CIN 183s Info: Defined in: 183s Info: example.v:20.14-20.25 183s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 183s Info: 0.1 2.7 Source counter_SB_LUT4_I2_14_LC.COUT 183s Info: 0.0 2.7 Net counter_SB_CARRY_CI_CO[10] budget 0.000000 ns (11,11) -> (11,11) 183s Info: Sink counter_SB_LUT4_I2_13_LC.CIN 183s Info: Defined in: 183s Info: example.v:20.14-20.25 183s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 183s Info: 0.1 2.8 Source counter_SB_LUT4_I2_13_LC.COUT 183s Info: 0.0 2.8 Net counter_SB_CARRY_CI_CO[11] budget 0.000000 ns (11,11) -> (11,11) 183s Info: Sink counter_SB_LUT4_I2_12_LC.CIN 183s Info: Defined in: 183s Info: example.v:20.14-20.25 183s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 183s Info: 0.1 3.0 Source counter_SB_LUT4_I2_12_LC.COUT 183s Info: 0.0 3.0 Net counter_SB_CARRY_CI_CO[12] budget 0.000000 ns (11,11) -> (11,11) 183s Info: Sink counter_SB_LUT4_I2_11_LC.CIN 183s Info: Defined in: 183s Info: example.v:20.14-20.25 183s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 183s Info: 0.1 3.1 Source counter_SB_LUT4_I2_11_LC.COUT 183s Info: 0.0 3.1 Net counter_SB_CARRY_CI_CO[13] budget 0.000000 ns (11,11) -> (11,11) 183s Info: Sink counter_SB_LUT4_I2_10_LC.CIN 183s Info: Defined in: 183s Info: example.v:20.14-20.25 183s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 183s Info: 0.1 3.2 Source counter_SB_LUT4_I2_10_LC.COUT 183s Info: 0.0 3.2 Net counter_SB_CARRY_CI_CO[14] budget 0.000000 ns (11,11) -> (11,11) 183s Info: Sink counter_SB_LUT4_I2_9_LC.CIN 183s Info: Defined in: 183s Info: example.v:20.14-20.25 183s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 183s Info: 0.1 3.3 Source counter_SB_LUT4_I2_9_LC.COUT 183s Info: 0.0 3.3 Net counter_SB_CARRY_CI_CO[15] budget 0.000000 ns (11,11) -> (11,11) 183s Info: Sink counter_SB_LUT4_I2_8_LC.CIN 183s Info: Defined in: 183s Info: example.v:20.14-20.25 183s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 183s Info: 0.1 3.5 Source counter_SB_LUT4_I2_8_LC.COUT 183s Info: 0.2 3.7 Net counter_SB_CARRY_CI_CO[16] budget 0.190000 ns (11,11) -> (11,12) 183s Info: Sink counter_SB_LUT4_I2_7_LC.CIN 183s Info: Defined in: 183s Info: example.v:20.14-20.25 183s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 183s Info: 0.1 3.8 Source counter_SB_LUT4_I2_7_LC.COUT 183s Info: 0.0 3.8 Net counter_SB_CARRY_CI_CO[17] budget 0.000000 ns (11,12) -> (11,12) 183s Info: Sink counter_SB_LUT4_I2_6_LC.CIN 183s Info: Defined in: 183s Info: example.v:20.14-20.25 183s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 183s Info: 0.1 3.9 Source counter_SB_LUT4_I2_6_LC.COUT 183s Info: 0.0 3.9 Net counter_SB_CARRY_CI_CO[18] budget 0.000000 ns (11,12) -> (11,12) 183s Info: Sink counter_SB_LUT4_I2_5_LC.CIN 183s Info: Defined in: 183s Info: example.v:20.14-20.25 183s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 183s Info: 0.1 4.0 Source counter_SB_LUT4_I2_5_LC.COUT 183s Info: 0.0 4.0 Net counter_SB_CARRY_CI_CO[19] budget 0.000000 ns (11,12) -> (11,12) 183s Info: Sink counter_SB_LUT4_I2_4_LC.CIN 183s Info: Defined in: 183s Info: example.v:20.14-20.25 183s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 183s Info: 0.1 4.2 Source counter_SB_LUT4_I2_4_LC.COUT 183s Info: 0.0 4.2 Net counter_SB_CARRY_CI_CO[20] budget 0.000000 ns (11,12) -> (11,12) 183s Info: Sink counter_SB_LUT4_I2_2_LC.CIN 183s Info: Defined in: 183s Info: example.v:20.14-20.25 183s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 183s Info: 0.1 4.3 Source counter_SB_LUT4_I2_2_LC.COUT 183s Info: 0.0 4.3 Net counter_SB_CARRY_CI_CO[21] budget 0.000000 ns (11,12) -> (11,12) 183s Info: Sink counter_SB_LUT4_I2_1_LC.CIN 183s Info: Defined in: 183s Info: example.v:20.14-20.25 183s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 183s Info: 0.1 4.4 Source counter_SB_LUT4_I2_1_LC.COUT 183s Info: 0.3 4.7 Net counter_SB_CARRY_CI_CO[22] budget 0.260000 ns (11,12) -> (11,12) 183s Info: Sink counter_SB_LUT4_I2_LC.I3 183s Info: Defined in: 183s Info: example.v:20.14-20.25 183s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 183s Info: 0.3 5.0 Setup counter_SB_LUT4_I2_LC.I3 183s Info: 3.8 ns logic, 1.2 ns routing 183s 183s Info: Critical path report for cross-domain path 'posedge clk$SB_IO_IN_$glb_clk' -> '': 183s Info: curr total 183s Info: 0.5 0.5 Source outcnt_SB_DFF_Q_DFFLC.O 183s Info: 0.6 1.1 Net outcnt[2] budget 41.196999 ns (12,12) -> (12,11) 183s Info: Sink LED0_SB_LUT4_O_LC.I1 183s Info: Defined in: 183s Info: example.v:17.17-17.23 183s Info: 0.4 1.5 Source LED0_SB_LUT4_O_LC.O 183s Info: 1.5 3.0 Net LED0$SB_IO_OUT budget 41.196999 ns (12,11) -> (13,9) 183s Info: Sink LED0$sb_io.D_OUT_0 183s Info: Defined in: 183s Info: example.v:3.9-3.13 183s Info: 0.9 ns logic, 2.1 ns routing 183s 183s Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 199.20 MHz (PASS at 12.00 MHz) 183s 183s Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> : 3.02 ns 183s 183s Info: Slack histogram: 183s Info: legend: * represents 1 endpoint(s) 183s Info: + represents [1,1) endpoint(s) 183s Info: [ 78313, 78491) |** 183s Info: [ 78491, 78669) |* 183s Info: [ 78669, 78847) |** 183s Info: [ 78847, 79025) |** 183s Info: [ 79025, 79203) | 183s Info: [ 79203, 79381) | 183s Info: [ 79381, 79559) |** 183s Info: [ 79559, 79737) |* 183s Info: [ 79737, 79915) |** 183s Info: [ 79915, 80093) |* 183s Info: [ 80093, 80271) |** 183s Info: [ 80271, 80449) |* 183s Info: [ 80449, 80627) |** 183s Info: [ 80627, 80805) |* 183s Info: [ 80805, 80983) |** 183s Info: [ 80983, 81161) |* 183s Info: [ 81161, 81339) |******* 183s Info: [ 81339, 81517) | 183s Info: [ 81517, 81695) | 183s Info: [ 81695, 81873) |*************************** 183s 183s Info: Program finished normally. 183s // Creating timing netlist.. 183s // Timing estimate: 4.98 ns (200.75 MHz) 183s icepack example.asc example.bin 183s make: Leaving directory '/tmp/autopkgtest.rlxjW8/build.dCN/src/examples/icezum' 183s make: Entering directory '/tmp/autopkgtest.rlxjW8/build.dCN/src/examples/up5k_rgb' 183s yosys -p 'synth_ice40 -top top -json rgb.json' rgb.v 183s 183s /----------------------------------------------------------------------------\ 183s | | 183s | yosys -- Yosys Open SYnthesis Suite | 183s | | 183s | Copyright (C) 2012 - 2020 Claire Xenia Wolf | 183s | | 183s | Permission to use, copy, modify, and/or distribute this software for any | 183s | purpose with or without fee is hereby granted, provided that the above | 183s | copyright notice and this permission notice appear in all copies. | 183s | | 183s | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | 183s | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | 183s | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | 183s | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | 183s | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | 183s | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | 183s | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 183s | | 183s \----------------------------------------------------------------------------/ 183s 183s Yosys 0.23 (git sha1 7ce5011c24b) 183s 183s 183s -- Parsing `rgb.v' using frontend ` -vlog2k' -- 183s 183s 1. Executing Verilog-2005 frontend: rgb.v 183s Parsing Verilog input from `rgb.v' to AST representation. 183s Storing AST representation for module `$abstract\top'. 183s Successfully finished Verilog frontend. 183s 183s -- Running command `synth_ice40 -top top -json rgb.json' -- 183s 183s 2. Executing SYNTH_ICE40 pass. 183s 183s 2.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v 183s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation. 183s Generating RTLIL representation for module `\SB_IO'. 183s Generating RTLIL representation for module `\SB_GB_IO'. 183s Generating RTLIL representation for module `\SB_GB'. 183s Generating RTLIL representation for module `\SB_LUT4'. 183s Generating RTLIL representation for module `\SB_CARRY'. 183s Generating RTLIL representation for module `\SB_DFF'. 183s Generating RTLIL representation for module `\SB_DFFE'. 183s Generating RTLIL representation for module `\SB_DFFSR'. 183s Generating RTLIL representation for module `\SB_DFFR'. 183s Generating RTLIL representation for module `\SB_DFFSS'. 183s Generating RTLIL representation for module `\SB_DFFS'. 183s Generating RTLIL representation for module `\SB_DFFESR'. 183s Generating RTLIL representation for module `\SB_DFFER'. 183s Generating RTLIL representation for module `\SB_DFFESS'. 183s Generating RTLIL representation for module `\SB_DFFES'. 183s Generating RTLIL representation for module `\SB_DFFN'. 183s Generating RTLIL representation for module `\SB_DFFNE'. 183s Generating RTLIL representation for module `\SB_DFFNSR'. 183s Generating RTLIL representation for module `\SB_DFFNR'. 183s Generating RTLIL representation for module `\SB_DFFNSS'. 183s Generating RTLIL representation for module `\SB_DFFNS'. 183s Generating RTLIL representation for module `\SB_DFFNESR'. 183s Generating RTLIL representation for module `\SB_DFFNER'. 183s Generating RTLIL representation for module `\SB_DFFNESS'. 183s Generating RTLIL representation for module `\SB_DFFNES'. 183s Generating RTLIL representation for module `\SB_RAM40_4K'. 183s Generating RTLIL representation for module `\SB_RAM40_4KNR'. 183s Generating RTLIL representation for module `\SB_RAM40_4KNW'. 183s Generating RTLIL representation for module `\SB_RAM40_4KNRNW'. 183s Generating RTLIL representation for module `\ICESTORM_LC'. 183s Generating RTLIL representation for module `\SB_PLL40_CORE'. 183s Generating RTLIL representation for module `\SB_PLL40_PAD'. 183s Generating RTLIL representation for module `\SB_PLL40_2_PAD'. 183s Generating RTLIL representation for module `\SB_PLL40_2F_CORE'. 183s Generating RTLIL representation for module `\SB_PLL40_2F_PAD'. 183s Generating RTLIL representation for module `\SB_WARMBOOT'. 183s Generating RTLIL representation for module `\SB_SPRAM256KA'. 183s Generating RTLIL representation for module `\SB_HFOSC'. 183s Generating RTLIL representation for module `\SB_LFOSC'. 183s Generating RTLIL representation for module `\SB_RGBA_DRV'. 183s Generating RTLIL representation for module `\SB_LED_DRV_CUR'. 183s Generating RTLIL representation for module `\SB_RGB_DRV'. 183s Generating RTLIL representation for module `\SB_I2C'. 183s Generating RTLIL representation for module `\SB_SPI'. 183s Generating RTLIL representation for module `\SB_LEDDA_IP'. 183s Generating RTLIL representation for module `\SB_FILTER_50NS'. 183s Generating RTLIL representation for module `\SB_IO_I3C'. 183s Generating RTLIL representation for module `\SB_IO_OD'. 183s Generating RTLIL representation for module `\SB_MAC16'. 183s Generating RTLIL representation for module `\ICESTORM_RAM'. 183s Successfully finished Verilog frontend. 183s 183s 2.2. Executing HIERARCHY pass (managing design hierarchy). 183s 183s 2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\top'. 183s Generating RTLIL representation for module `\top'. 183s 183s 2.3.1. Analyzing design hierarchy.. 183s Top module: \top 183s 183s 2.3.2. Analyzing design hierarchy.. 183s Top module: \top 183s Removing unused module `$abstract\top'. 183s Removed 1 unused modules. 183s 183s 2.4. Executing PROC pass (convert processes to netlists). 183s 183s 2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). 183s Cleaned up 0 empty switches. 183s 183s 2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). 183s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241 in module SB_DFFNES. 183s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234 in module SB_DFFNESS. 183s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230 in module SB_DFFNER. 183s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223 in module SB_DFFNESR. 183s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220 in module SB_DFFNS. 183s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217 in module SB_DFFNSS. 183s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214 in module SB_DFFNR. 183s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211 in module SB_DFFNSR. 183s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203 in module SB_DFFES. 183s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196 in module SB_DFFESS. 183s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192 in module SB_DFFER. 183s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185 in module SB_DFFESR. 183s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182 in module SB_DFFS. 183s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179 in module SB_DFFSS. 183s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176 in module SB_DFFR. 183s Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173 in module SB_DFFSR. 183s Removed a total of 0 dead cases. 183s 183s 2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). 183s Removed 8 redundant assignments. 183s Promoted 27 assignments to connections. 183s 183s 2.4.4. Executing PROC_INIT pass (extract init attributes). 183s Found init rule in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 183s Set init value: \Q = 1'0 183s Found init rule in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 183s Set init value: \Q = 1'0 183s Found init rule in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 183s Set init value: \Q = 1'0 183s Found init rule in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 183s Set init value: \Q = 1'0 183s Found init rule in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 183s Set init value: \Q = 1'0 183s Found init rule in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 183s Set init value: \Q = 1'0 183s Found init rule in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 183s Set init value: \Q = 1'0 183s Found init rule in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 183s Set init value: \Q = 1'0 183s Found init rule in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 183s Set init value: \Q = 1'0 183s Found init rule in `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 183s Set init value: \Q = 1'0 183s Found init rule in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 183s Set init value: \Q = 1'0 183s Found init rule in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 183s Set init value: \Q = 1'0 183s Found init rule in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 183s Set init value: \Q = 1'0 183s Found init rule in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 183s Set init value: \Q = 1'0 183s Found init rule in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 183s Set init value: \Q = 1'0 183s Found init rule in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 183s Set init value: \Q = 1'0 183s Found init rule in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 183s Set init value: \Q = 1'0 183s Found init rule in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 183s Set init value: \Q = 1'0 183s Found init rule in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 183s Set init value: \Q = 1'0 183s Found init rule in `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 183s Set init value: \Q = 1'0 183s 183s 2.4.5. Executing PROC_ARST pass (detect async resets in processes). 183s Found async reset \S in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 183s Found async reset \R in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 183s Found async reset \S in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 183s Found async reset \R in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 183s Found async reset \S in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 183s Found async reset \R in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 183s Found async reset \S in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 183s Found async reset \R in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 183s 183s 2.4.6. Executing PROC_ROM pass (convert switches to ROMs). 183s Converted 0 switches. 183s 183s 183s 2.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 183s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 183s Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 183s 1/1: $0\Q[0:0] 183s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 183s Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 183s 1/1: $0\Q[0:0] 183s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 183s Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 183s 1/1: $0\Q[0:0] 183s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 183s Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 183s 1/1: $0\Q[0:0] 183s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 183s Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 183s 1/1: $0\Q[0:0] 183s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 183s Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 183s 1/1: $0\Q[0:0] 183s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 183s Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 183s 1/1: $0\Q[0:0] 183s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 183s Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 183s 1/1: $0\Q[0:0] 183s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 183s Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 183s 1/1: $0\Q[0:0] 183s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 183s Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 183s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 183s Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 183s 1/1: $0\Q[0:0] 183s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 183s Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 183s 1/1: $0\Q[0:0] 183s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 183s Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 183s 1/1: $0\Q[0:0] 183s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 183s Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 183s 1/1: $0\Q[0:0] 183s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 183s Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 183s 1/1: $0\Q[0:0] 183s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 183s Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 183s 1/1: $0\Q[0:0] 183s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 183s Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 183s 1/1: $0\Q[0:0] 183s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 183s Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 183s 1/1: $0\Q[0:0] 183s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 183s Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 183s 1/1: $0\Q[0:0] 183s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 183s Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 183s Creating decoders for process `\top.$proc$rgb.v:55$415'. 183s Creating decoders for process `\top.$proc$rgb.v:17$381'. 183s 183s 2.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). 183s 183s 2.4.9. Executing PROC_DFF pass (convert process syncs to FFs). 183s Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 183s created $adff cell `$procdff$467' with negative edge clock and positive level reset. 183s Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 183s created $dff cell `$procdff$468' with negative edge clock. 183s Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 183s created $adff cell `$procdff$469' with negative edge clock and positive level reset. 183s Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 183s created $dff cell `$procdff$470' with negative edge clock. 183s Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 183s created $adff cell `$procdff$471' with negative edge clock and positive level reset. 183s Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 183s created $dff cell `$procdff$472' with negative edge clock. 183s Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 183s created $adff cell `$procdff$473' with negative edge clock and positive level reset. 183s Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 183s created $dff cell `$procdff$474' with negative edge clock. 183s Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 183s created $dff cell `$procdff$475' with negative edge clock. 183s Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 183s created $dff cell `$procdff$476' with negative edge clock. 183s Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 183s created $adff cell `$procdff$477' with positive edge clock and positive level reset. 183s Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 183s created $dff cell `$procdff$478' with positive edge clock. 183s Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 183s created $adff cell `$procdff$479' with positive edge clock and positive level reset. 183s Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 183s created $dff cell `$procdff$480' with positive edge clock. 183s Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 183s created $adff cell `$procdff$481' with positive edge clock and positive level reset. 183s Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 183s created $dff cell `$procdff$482' with positive edge clock. 183s Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 183s created $adff cell `$procdff$483' with positive edge clock and positive level reset. 183s Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 183s created $dff cell `$procdff$484' with positive edge clock. 183s Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 183s created $dff cell `$procdff$485' with positive edge clock. 183s Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 183s created $dff cell `$procdff$486' with positive edge clock. 183s Creating register for signal `\top.\pwm_ctr' using process `\top.$proc$rgb.v:55$415'. 183s created $dff cell `$procdff$487' with positive edge clock. 183s Creating register for signal `\top.\pwm_r' using process `\top.$proc$rgb.v:55$415'. 183s created $dff cell `$procdff$488' with positive edge clock. 183s Creating register for signal `\top.\pwm_g' using process `\top.$proc$rgb.v:55$415'. 183s created $dff cell `$procdff$489' with positive edge clock. 183s Creating register for signal `\top.\pwm_b' using process `\top.$proc$rgb.v:55$415'. 183s created $dff cell `$procdff$490' with positive edge clock. 183s Creating register for signal `\top.\ctr' using process `\top.$proc$rgb.v:17$381'. 183s created $dff cell `$procdff$491' with positive edge clock. 183s 183s 2.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 183s 183s 2.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). 183s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$244'. 183s Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 183s Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$241'. 183s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$240'. 183s Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 183s Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$234'. 183s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$233'. 183s Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 183s Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$230'. 183s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$229'. 183s Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 183s Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$223'. 183s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$222'. 183s Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$220'. 183s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$219'. 183s Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 183s Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$217'. 183s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$216'. 183s Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$214'. 183s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$213'. 183s Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 183s Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$211'. 183s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$210'. 183s Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 183s Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$209'. 183s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$208'. 183s Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$207'. 183s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$206'. 183s Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 183s Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$203'. 183s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$202'. 183s Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 183s Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$196'. 183s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$195'. 183s Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 183s Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$192'. 183s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$191'. 183s Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 183s Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$185'. 183s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$184'. 183s Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$182'. 183s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$181'. 183s Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 183s Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$179'. 183s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$178'. 183s Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$176'. 183s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$175'. 183s Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 183s Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$173'. 183s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$172'. 183s Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 183s Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$171'. 183s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$170'. 183s Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$169'. 183s Removing empty process `top.$proc$rgb.v:55$415'. 183s Removing empty process `top.$proc$rgb.v:17$381'. 183s Cleaned up 18 empty switches. 183s 183s 2.4.12. Executing OPT_EXPR pass (perform const folding). 183s Optimizing module top. 183s 183s 183s 2.5. Executing FLATTEN pass (flatten design). 183s 183s 2.6. Executing TRIBUF pass. 183s 183s 2.7. Executing DEMINOUT pass (demote inout ports to input or output). 183s 183s 2.8. Executing OPT_EXPR pass (perform const folding). 183s Optimizing module top. 183s 183s 2.9. Executing OPT_CLEAN pass (remove unused cells and wires). 183s Finding unused cells or wires in module \top.. 183s Removed 0 unused cells and 8 unused wires. 183s 183s 183s 2.10. Executing CHECK pass (checking for obvious problems). 183s Checking module top... 183s Found and reported 0 problems. 183s 183s 2.11. Executing OPT pass (performing simple optimizations). 183s 183s 2.11.1. Executing OPT_EXPR pass (perform const folding). 183s Optimizing module top. 183s 183s 2.11.2. Executing OPT_MERGE pass (detect identical cells). 183s Finding identical cells in module `\top'. 183s 183s Removed a total of 9 cells. 183s 183s 2.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 183s Running muxtree optimizer on module \top.. 183s Creating internal representation of mux trees. 183s Evaluating internal representation of mux trees. 183s Analyzing evaluation results. 183s Removed 0 multiplexer ports. 183s 183s 183s 2.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 183s Optimizing cells in module \top. 183s Performed a total of 0 changes. 183s 183s 2.11.5. Executing OPT_MERGE pass (detect identical cells). 183s Finding identical cells in module `\top'. 183s 183s Removed a total of 1 cells. 183s 183s 2.11.6. Executing OPT_DFF pass (perform DFF optimizations). 183s 183s 2.11.7. Executing OPT_CLEAN pass (remove unused cells and wires). 183s Finding unused cells or wires in module \top.. 183s Removed 0 unused cells and 10 unused wires. 183s 183s 183s 2.11.8. Executing OPT_EXPR pass (perform const folding). 183s Optimizing module top. 183s 183s 2.11.9. Rerunning OPT passes. (Maybe there is more to do..) 183s 183s 2.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 183s Running muxtree optimizer on module \top.. 183s Creating internal representation of mux trees. 183s Evaluating internal representation of mux trees. 183s Analyzing evaluation results. 183s Removed 0 multiplexer ports. 183s 183s 183s 2.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 183s Optimizing cells in module \top. 183s Performed a total of 0 changes. 183s 183s 2.11.12. Executing OPT_MERGE pass (detect identical cells). 183s Finding identical cells in module `\top'. 183s Removed a total of 0 cells. 183s 183s 2.11.13. Executing OPT_DFF pass (perform DFF optimizations). 183s 183s 2.11.14. Executing OPT_CLEAN pass (remove unused cells and wires). 183s Finding unused cells or wires in module \top.. 183s 183s 2.11.15. Executing OPT_EXPR pass (perform const folding). 183s Optimizing module top. 183s 183s 2.11.16. Finished OPT passes. (There is nothing left to do.) 183s 183s 2.12. Executing FSM pass (extract and optimize FSM). 183s 183s 2.12.1. Executing FSM_DETECT pass (finding FSMs in design). 183s 183s 2.12.2. Executing FSM_EXTRACT pass (extracting FSM from design). 183s 183s 2.12.3. Executing FSM_OPT pass (simple optimizations of FSMs). 183s 183s 2.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). 183s Finding unused cells or wires in module \top.. 183s 183s 2.12.5. Executing FSM_OPT pass (simple optimizations of FSMs). 183s 183s 2.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 183s 183s 2.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 183s 183s 2.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 183s 183s 2.13. Executing OPT pass (performing simple optimizations). 183s 183s 2.13.1. Executing OPT_EXPR pass (perform const folding). 183s Optimizing module top. 183s 183s 2.13.2. Executing OPT_MERGE pass (detect identical cells). 183s Finding identical cells in module `\top'. 183s Removed a total of 0 cells. 183s 183s 2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 183s Running muxtree optimizer on module \top.. 183s Creating internal representation of mux trees. 183s Evaluating internal representation of mux trees. 183s Analyzing evaluation results. 183s Removed 0 multiplexer ports. 183s 183s 183s 2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 183s Optimizing cells in module \top. 183s Performed a total of 0 changes. 183s 183s 2.13.5. Executing OPT_MERGE pass (detect identical cells). 183s Finding identical cells in module `\top'. 183s Removed a total of 0 cells. 183s 183s 2.13.6. Executing OPT_DFF pass (perform DFF optimizations). 183s 183s 2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). 183s Finding unused cells or wires in module \top.. 183s 183s 2.13.8. Executing OPT_EXPR pass (perform const folding). 183s Optimizing module top. 183s 183s 2.13.9. Finished OPT passes. (There is nothing left to do.) 183s 183s 2.14. Executing WREDUCE pass (reducing word size of cells). 183s Removed top 31 bits (of 32) from port B of cell top.$add$rgb.v:19$382 ($add). 183s Removed top 30 bits (of 32) from port A of cell top.$mul$rgb.v:35$384 ($mul). 183s Removed top 2 bits (of 12) from port B of cell top.$mul$rgb.v:35$384 ($mul). 183s Removed top 20 bits (of 32) from port Y of cell top.$mul$rgb.v:35$384 ($mul). 183s Removed top 22 bits (of 32) from port A of cell top.$add$rgb.v:35$385 ($add). 183s Removed top 20 bits (of 32) from port B of cell top.$add$rgb.v:35$385 ($add). 183s Removed top 19 bits (of 32) from port Y of cell top.$add$rgb.v:35$385 ($add). 183s Removed top 1 bits (of 2) from port B of cell top.$eq$rgb.v:36$386 ($eq). 183s Removed top 20 bits (of 32) from port A of cell top.$sub$rgb.v:36$387 ($sub). 183s Removed top 19 bits (of 32) from port Y of cell top.$sub$rgb.v:36$387 ($sub). 183s Removed top 22 bits (of 32) from mux cell top.$ternary$rgb.v:37$390 ($mux). 183s Removed top 20 bits (of 32) from mux cell top.$ternary$rgb.v:35$392 ($mux). 183s Removed top 22 bits (of 32) from port A of cell top.$sub$rgb.v:40$394 ($sub). 183s Removed top 2 bits (of 12) from port B of cell top.$sub$rgb.v:40$394 ($sub). 183s Removed top 21 bits (of 32) from port Y of cell top.$sub$rgb.v:40$394 ($sub). 183s Removed top 20 bits (of 32) from mux cell top.$ternary$rgb.v:40$404 ($mux). 183s Removed top 20 bits (of 32) from port A of cell top.$sub$rgb.v:48$410 ($sub). 183s Removed top 20 bits (of 32) from port B of cell top.$sub$rgb.v:48$410 ($sub). 183s Removed top 19 bits (of 32) from port Y of cell top.$sub$rgb.v:48$410 ($sub). 183s Removed top 20 bits (of 32) from mux cell top.$ternary$rgb.v:46$414 ($mux). 183s Removed top 31 bits (of 32) from port B of cell top.$add$rgb.v:57$416 ($add). 183s Removed top 20 bits (of 32) from port Y of cell top.$add$rgb.v:57$416 ($add). 183s Removed top 1 bits (of 13) from port Y of cell top.$add$rgb.v:35$385 ($add). 183s Removed top 20 bits (of 32) from mux cell top.$ternary$rgb.v:36$391 ($mux). 183s Removed top 20 bits (of 32) from mux cell top.$ternary$rgb.v:41$403 ($mux). 183s Removed top 20 bits (of 32) from mux cell top.$ternary$rgb.v:47$413 ($mux). 183s Removed top 20 bits (of 32) from mux cell top.$ternary$rgb.v:42$401 ($mux). 183s Removed top 20 bits (of 32) from mux cell top.$ternary$rgb.v:48$411 ($mux). 183s Removed top 1 bits (of 13) from port Y of cell top.$sub$rgb.v:36$387 ($sub). 183s Removed top 1 bits (of 13) from port Y of cell top.$sub$rgb.v:48$410 ($sub). 183s Removed top 20 bits (of 32) from wire top.$add$rgb.v:35$385_Y. 183s Removed top 20 bits (of 32) from wire top.$mul$rgb.v:35$384_Y. 183s Removed top 20 bits (of 32) from wire top.$sub$rgb.v:36$387_Y. 183s Removed top 20 bits (of 32) from wire top.$sub$rgb.v:48$410_Y. 183s Removed top 20 bits (of 32) from wire top.$ternary$rgb.v:36$391_Y. 183s Removed top 22 bits (of 32) from wire top.$ternary$rgb.v:37$390_Y. 183s Removed top 20 bits (of 32) from wire top.$ternary$rgb.v:41$403_Y. 183s Removed top 20 bits (of 32) from wire top.$ternary$rgb.v:42$401_Y. 183s Removed top 20 bits (of 32) from wire top.$ternary$rgb.v:47$413_Y. 183s Removed top 21 bits (of 32) from wire top.$ternary$rgb.v:48$411_Y. 183s Removed top 2 bits (of 12) from wire top.fade_div4. 183s 183s 2.15. Executing PEEPOPT pass (run peephole optimizers). 183s 183s 2.16. Executing OPT_CLEAN pass (remove unused cells and wires). 183s Finding unused cells or wires in module \top.. 183s Removed 0 unused cells and 15 unused wires. 183s 183s 183s 2.17. Executing SHARE pass (SAT-based resource sharing). 183s 183s 2.18. Executing TECHMAP pass (map to technology primitives). 183s 183s 2.18.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v 183s Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation. 183s Generating RTLIL representation for module `\_90_lut_cmp_'. 183s Successfully finished Verilog frontend. 183s 183s 2.18.2. Continuing TECHMAP pass. 183s No more expansions possible. 183s 183s 183s 2.19. Executing OPT_EXPR pass (perform const folding). 183s Optimizing module top. 183s 183s 2.20. Executing OPT_CLEAN pass (remove unused cells and wires). 183s Finding unused cells or wires in module \top.. 183s 183s 2.21. Executing ALUMACC pass (create $alu and $macc cells). 183s Extracting $alu and $macc cells in module top: 183s creating $macc model for $add$rgb.v:19$382 ($add). 183s creating $macc model for $add$rgb.v:35$385 ($add). 183s creating $macc model for $add$rgb.v:57$416 ($add). 183s creating $macc model for $mul$rgb.v:35$384 ($mul). 183s creating $macc model for $sub$rgb.v:36$387 ($sub). 183s creating $macc model for $sub$rgb.v:40$394 ($sub). 183s creating $macc model for $sub$rgb.v:48$410 ($sub). 183s creating $alu model for $macc $sub$rgb.v:48$410. 183s creating $alu model for $macc $sub$rgb.v:40$394. 183s creating $alu model for $macc $sub$rgb.v:36$387. 183s creating $alu model for $macc $add$rgb.v:57$416. 183s creating $alu model for $macc $add$rgb.v:35$385. 183s creating $alu model for $macc $add$rgb.v:19$382. 183s creating $macc cell for $mul$rgb.v:35$384: $auto$alumacc.cc:365:replace_macc$504 183s creating $alu model for $lt$rgb.v:58$417 ($lt): new $alu 183s creating $alu model for $lt$rgb.v:59$419 ($lt): new $alu 183s creating $alu model for $lt$rgb.v:60$421 ($lt): new $alu 183s creating $alu cell for $lt$rgb.v:60$421: $auto$alumacc.cc:485:replace_alu$508 183s creating $alu cell for $lt$rgb.v:59$419: $auto$alumacc.cc:485:replace_alu$519 183s creating $alu cell for $lt$rgb.v:58$417: $auto$alumacc.cc:485:replace_alu$530 183s creating $alu cell for $add$rgb.v:19$382: $auto$alumacc.cc:485:replace_alu$541 183s creating $alu cell for $add$rgb.v:35$385: $auto$alumacc.cc:485:replace_alu$544 183s creating $alu cell for $add$rgb.v:57$416: $auto$alumacc.cc:485:replace_alu$547 183s creating $alu cell for $sub$rgb.v:36$387: $auto$alumacc.cc:485:replace_alu$550 183s creating $alu cell for $sub$rgb.v:40$394: $auto$alumacc.cc:485:replace_alu$553 183s creating $alu cell for $sub$rgb.v:48$410: $auto$alumacc.cc:485:replace_alu$556 183s created 9 $alu and 1 $macc cells. 183s 183s 2.22. Executing OPT pass (performing simple optimizations). 183s 183s 2.22.1. Executing OPT_EXPR pass (perform const folding). 183s Optimizing module top. 183s 183s 183s 2.22.2. Executing OPT_MERGE pass (detect identical cells). 183s Finding identical cells in module `\top'. 183s Removed a total of 0 cells. 183s 183s 2.22.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 183s Running muxtree optimizer on module \top.. 183s Creating internal representation of mux trees. 183s Evaluating internal representation of mux trees. 183s Analyzing evaluation results. 183s Removed 0 multiplexer ports. 183s 183s 183s 2.22.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 183s Optimizing cells in module \top. 183s Performed a total of 0 changes. 183s 183s 2.22.5. Executing OPT_MERGE pass (detect identical cells). 183s Finding identical cells in module `\top'. 183s Removed a total of 0 cells. 183s 183s 2.22.6. Executing OPT_DFF pass (perform DFF optimizations). 183s 183s 2.22.7. Executing OPT_CLEAN pass (remove unused cells and wires). 183s Finding unused cells or wires in module \top.. 183s Removed 3 unused cells and 6 unused wires. 183s 183s 183s 2.22.8. Executing OPT_EXPR pass (perform const folding). 183s Optimizing module top. 183s 183s 2.22.9. Rerunning OPT passes. (Maybe there is more to do..) 183s 183s 2.22.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 183s Running muxtree optimizer on module \top.. 183s Creating internal representation of mux trees. 183s Evaluating internal representation of mux trees. 183s Analyzing evaluation results. 183s Removed 0 multiplexer ports. 183s 183s 183s 2.22.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 183s Optimizing cells in module \top. 183s Performed a total of 0 changes. 183s 183s 2.22.12. Executing OPT_MERGE pass (detect identical cells). 183s Finding identical cells in module `\top'. 183s Removed a total of 0 cells. 183s 183s 2.22.13. Executing OPT_DFF pass (perform DFF optimizations). 183s 183s 2.22.14. Executing OPT_CLEAN pass (remove unused cells and wires). 183s Finding unused cells or wires in module \top.. 183s 183s 2.22.15. Executing OPT_EXPR pass (perform const folding). 183s Optimizing module top. 183s 183s 2.22.16. Finished OPT passes. (There is nothing left to do.) 183s 183s 2.23. Executing MEMORY pass. 183s 183s 2.23.1. Executing OPT_MEM pass (optimize memories). 183s Performed a total of 0 transformations. 183s 183s 2.23.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). 183s Performed a total of 0 transformations. 183s 183s 2.23.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 183s 183s 2.23.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 183s 183s 2.23.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 183s 183s 2.23.6. Executing OPT_CLEAN pass (remove unused cells and wires). 183s Finding unused cells or wires in module \top.. 183s 183s 2.23.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 183s 183s 2.23.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). 183s Performed a total of 0 transformations. 183s 183s 2.23.9. Executing OPT_CLEAN pass (remove unused cells and wires). 183s Finding unused cells or wires in module \top.. 183s 183s 2.23.10. Executing MEMORY_COLLECT pass (generating $mem cells). 183s 183s 2.24. Executing OPT_CLEAN pass (remove unused cells and wires). 183s Finding unused cells or wires in module \top.. 183s 183s 2.25. Executing MEMORY_LIBMAP pass (mapping memories to cells). 183s 183s 2.26. Executing TECHMAP pass (map to technology primitives). 183s 183s 2.26.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v 184s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation. 184s Generating RTLIL representation for module `\$__ICE40_RAM4K_'. 184s Successfully finished Verilog frontend. 184s 184s 2.26.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/spram_map.v 184s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/spram_map.v' to AST representation. 184s Generating RTLIL representation for module `\$__ICE40_SPRAM_'. 184s Successfully finished Verilog frontend. 184s 184s 2.26.3. Continuing TECHMAP pass. 184s No more expansions possible. 184s 184s 184s 2.27. Executing ICE40_BRAMINIT pass. 184s 184s 2.28. Executing OPT pass (performing simple optimizations). 184s 184s 2.28.1. Executing OPT_EXPR pass (perform const folding). 184s Optimizing module top. 184s 184s 184s 2.28.2. Executing OPT_MERGE pass (detect identical cells). 184s Finding identical cells in module `\top'. 184s 184s Removed a total of 10 cells. 184s 184s 2.28.3. Executing OPT_DFF pass (perform DFF optimizations). 184s 184s 2.28.4. Executing OPT_CLEAN pass (remove unused cells and wires). 184s Finding unused cells or wires in module \top.. 184s Removed 0 unused cells and 22 unused wires. 184s 184s 184s 2.28.5. Finished fast OPT passes. 184s 184s 2.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 184s 184s 2.30. Executing OPT pass (performing simple optimizations). 184s 184s 2.30.1. Executing OPT_EXPR pass (perform const folding). 184s Optimizing module top. 184s 184s 2.30.2. Executing OPT_MERGE pass (detect identical cells). 184s Finding identical cells in module `\top'. 184s Removed a total of 0 cells. 184s 184s 2.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). 184s Running muxtree optimizer on module \top.. 184s Creating internal representation of mux trees. 184s Evaluating internal representation of mux trees. 184s Analyzing evaluation results. 184s Removed 0 multiplexer ports. 184s 184s 184s 2.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). 184s Optimizing cells in module \top. 184s Performed a total of 0 changes. 184s 184s 2.30.5. Executing OPT_MERGE pass (detect identical cells). 184s Finding identical cells in module `\top'. 184s Removed a total of 0 cells. 184s 184s 2.30.6. Executing OPT_DFF pass (perform DFF optimizations). 184s 184s 2.30.7. Executing OPT_CLEAN pass (remove unused cells and wires). 184s Finding unused cells or wires in module \top.. 184s 184s 2.30.8. Executing OPT_EXPR pass (perform const folding). 184s Optimizing module top. 184s 184s 2.30.9. Finished OPT passes. (There is nothing left to do.) 184s 184s 2.31. Executing ICE40_WRAPCARRY pass (wrap carries). 184s 184s 2.32. Executing TECHMAP pass (map to technology primitives). 184s 184s 2.32.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v 184s Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation. 184s Generating RTLIL representation for module `\_90_simplemap_bool_ops'. 184s Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. 184s Generating RTLIL representation for module `\_90_simplemap_logic_ops'. 184s Generating RTLIL representation for module `\_90_simplemap_compare_ops'. 184s Generating RTLIL representation for module `\_90_simplemap_various'. 184s Generating RTLIL representation for module `\_90_simplemap_registers'. 184s Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. 184s Generating RTLIL representation for module `\_90_shift_shiftx'. 184s Generating RTLIL representation for module `\_90_fa'. 184s Generating RTLIL representation for module `\_90_lcu'. 184s Generating RTLIL representation for module `\_90_alu'. 184s Generating RTLIL representation for module `\_90_macc'. 184s Generating RTLIL representation for module `\_90_alumacc'. 184s Generating RTLIL representation for module `\$__div_mod_u'. 184s Generating RTLIL representation for module `\$__div_mod_trunc'. 184s Generating RTLIL representation for module `\_90_div'. 184s Generating RTLIL representation for module `\_90_mod'. 184s Generating RTLIL representation for module `\$__div_mod_floor'. 184s Generating RTLIL representation for module `\_90_divfloor'. 184s Generating RTLIL representation for module `\_90_modfloor'. 184s Generating RTLIL representation for module `\_90_pow'. 184s Generating RTLIL representation for module `\_90_pmux'. 184s Generating RTLIL representation for module `\_90_demux'. 184s Generating RTLIL representation for module `\_90_lut'. 184s Successfully finished Verilog frontend. 184s 184s 2.32.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v 184s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation. 184s Generating RTLIL representation for module `\_80_ice40_alu'. 184s Successfully finished Verilog frontend. 184s 184s 2.32.3. Continuing TECHMAP pass. 184s Using extmapper simplemap for cells of type $not. 184s Using template $paramod$b40e0f66d01d243904da425c63ff802ae596888e\_80_ice40_alu for cells of type $alu. 184s Using extmapper simplemap for cells of type $logic_not. 184s Using template $paramod$ee3d784672cdb1cb32d9a801a3af776716f16b74\_80_ice40_alu for cells of type $alu. 184s Using template $paramod$8f780356cb6cdb52f6a744190131b65634639c4e\_80_ice40_alu for cells of type $alu. 184s Using extmapper simplemap for cells of type $eq. 184s Using extmapper simplemap for cells of type $or. 184s Using extmapper simplemap for cells of type $mux. 184s Using extmapper maccmap for cells of type $macc. 184s add \ctr [29:20] * 2'11 (10x2 bits, unsigned) 184s Using extmapper simplemap for cells of type $reduce_and. 184s Using template $paramod$6a42b6fefed750f8a1c58eab59479d960557103c\_80_ice40_alu for cells of type $alu. 184s Using extmapper simplemap for cells of type $dff. 184s Using extmapper simplemap for cells of type $and. 184s Using extmapper simplemap for cells of type $xor. 184s Using extmapper simplemap for cells of type $pos. 184s No more expansions possible. 184s 184s 184s 2.33. Executing OPT pass (performing simple optimizations). 184s 184s 2.33.1. Executing OPT_EXPR pass (perform const folding). 184s Optimizing module top. 184s 184s 184s 2.33.2. Executing OPT_MERGE pass (detect identical cells). 184s Finding identical cells in module `\top'. 184s 184s Removed a total of 86 cells. 184s 184s 2.33.3. Executing OPT_DFF pass (perform DFF optimizations). 184s 184s 2.33.4. Executing OPT_CLEAN pass (remove unused cells and wires). 184s Finding unused cells or wires in module \top.. 184s Removed 31 unused cells and 147 unused wires. 184s 184s 184s 2.33.5. Finished fast OPT passes. 184s 184s 2.34. Executing ICE40_OPT pass (performing simple optimizations). 184s 184s 2.34.1. Running ICE40 specific optimizations. 184s Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$541.slice[0].carry: CO=\ctr [0] 184s Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$544.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$544.B [0] 184s Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$547.slice[0].carry: CO=\pwm_ctr [0] 184s Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$830.slice[0].carry: CO=1'0 184s Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$830.slice[11].carry: CO=1'0 184s 184s 2.34.2. Executing OPT_EXPR pass (perform const folding). 184s Optimizing module top. 184s 184s 2.34.3. Executing OPT_MERGE pass (detect identical cells). 184s Finding identical cells in module `\top'. 184s Removed a total of 0 cells. 184s 184s 2.34.4. Executing OPT_DFF pass (perform DFF optimizations). 184s 184s 2.34.5. Executing OPT_CLEAN pass (remove unused cells and wires). 184s Finding unused cells or wires in module \top.. 184s Removed 0 unused cells and 1 unused wires. 184s 184s 184s 2.34.6. Rerunning OPT passes. (Removed registers in this run.) 184s 184s 2.34.7. Running ICE40 specific optimizations. 184s 184s 2.34.8. Executing OPT_EXPR pass (perform const folding). 184s Optimizing module top. 184s 184s 2.34.9. Executing OPT_MERGE pass (detect identical cells). 184s Finding identical cells in module `\top'. 184s Removed a total of 0 cells. 184s 184s 2.34.10. Executing OPT_DFF pass (perform DFF optimizations). 184s 184s 2.34.11. Executing OPT_CLEAN pass (remove unused cells and wires). 184s Finding unused cells or wires in module \top.. 184s 184s 2.34.12. Finished OPT passes. (There is nothing left to do.) 184s 184s 2.35. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 184s 184s 2.36. Executing TECHMAP pass (map to technology primitives). 184s 184s 2.36.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 184s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 184s Generating RTLIL representation for module `\$_DFF_N_'. 184s Generating RTLIL representation for module `\$_DFF_P_'. 184s Generating RTLIL representation for module `\$_DFFE_NP_'. 184s Generating RTLIL representation for module `\$_DFFE_PP_'. 184s Generating RTLIL representation for module `\$_DFF_NP0_'. 184s Generating RTLIL representation for module `\$_DFF_NP1_'. 184s Generating RTLIL representation for module `\$_DFF_PP0_'. 184s Generating RTLIL representation for module `\$_DFF_PP1_'. 184s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 184s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 184s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 184s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 184s Generating RTLIL representation for module `\$_SDFF_NP0_'. 184s Generating RTLIL representation for module `\$_SDFF_NP1_'. 184s Generating RTLIL representation for module `\$_SDFF_PP0_'. 184s Generating RTLIL representation for module `\$_SDFF_PP1_'. 184s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 184s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 184s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 184s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 184s Successfully finished Verilog frontend. 184s 184s 2.36.2. Continuing TECHMAP pass. 184s Using template \$_DFF_P_ for cells of type $_DFF_P_. 184s No more expansions possible. 184s 184s 184s 2.37. Executing OPT_EXPR pass (perform const folding). 184s Optimizing module top. 184s 184s 2.38. Executing SIMPLEMAP pass (map simple cells to gate primitives). 184s Mapping top.$auto$alumacc.cc:485:replace_alu$541.slice[0].carry ($lut). 184s Mapping top.$auto$alumacc.cc:485:replace_alu$544.slice[0].carry ($lut). 184s Mapping top.$auto$alumacc.cc:485:replace_alu$547.slice[0].carry ($lut). 184s Mapping top.$auto$maccmap.cc:240:synth$830.slice[0].carry ($lut). 184s Mapping top.$auto$maccmap.cc:240:synth$830.slice[11].carry ($lut). 184s 184s 2.39. Executing ICE40_OPT pass (performing simple optimizations). 184s 184s 2.39.1. Running ICE40 specific optimizations. 184s 184s 2.39.2. Executing OPT_EXPR pass (perform const folding). 184s Optimizing module top. 184s 184s 184s 2.39.3. Executing OPT_MERGE pass (detect identical cells). 184s Finding identical cells in module `\top'. 184s 184s Removed a total of 5 cells. 184s 184s 2.39.4. Executing OPT_DFF pass (perform DFF optimizations). 184s 184s 2.39.5. Executing OPT_CLEAN pass (remove unused cells and wires). 184s Finding unused cells or wires in module \top.. 184s Removed 0 unused cells and 209 unused wires. 184s 184s 184s 2.39.6. Rerunning OPT passes. (Removed registers in this run.) 184s 184s 2.39.7. Running ICE40 specific optimizations. 184s 184s 2.39.8. Executing OPT_EXPR pass (perform const folding). 184s Optimizing module top. 184s 184s 2.39.9. Executing OPT_MERGE pass (detect identical cells). 184s Finding identical cells in module `\top'. 184s Removed a total of 0 cells. 184s 184s 2.39.10. Executing OPT_DFF pass (perform DFF optimizations). 184s 184s 2.39.11. Executing OPT_CLEAN pass (remove unused cells and wires). 184s Finding unused cells or wires in module \top.. 184s 184s 2.39.12. Finished OPT passes. (There is nothing left to do.) 184s 184s 2.40. Executing TECHMAP pass (map to technology primitives). 184s 184s 2.40.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v 184s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation. 184s Generating RTLIL representation for module `\$_DLATCH_N_'. 184s Generating RTLIL representation for module `\$_DLATCH_P_'. 184s Successfully finished Verilog frontend. 184s 184s 2.40.2. Continuing TECHMAP pass. 184s No more expansions possible. 184s 184s 184s 2.41. Executing ABC pass (technology mapping using ABC). 184s 184s 2.41.1. Extracting gate netlist of module `\top' to `/input.blif'.. 184s Extracted 226 gates and 279 wires to a netlist network with 52 inputs and 52 outputs. 184s 184s 2.41.1.1. Executing ABC. 184s Running ABC command: "berkeley-abc" -s -f /abc.script 2>&1 184s ABC: ABC command line: "source /abc.script". 184s ABC: 184s ABC: + read_blif /input.blif 184s ABC: + read_lut /lutdefs.txt 184s ABC: + strash 184s ABC: + &get -n 184s ABC: + &fraig -x 184s ABC: + &put 184s ABC: + scorr 184s ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). 184s ABC: + dc2 184s ABC: + dretime 184s ABC: + strash 184s ABC: + dch -f 184s ABC: + if 184s ABC: + mfs2 184s ABC: + lutpack -S 1 184s ABC: + dress /input.blif 184s ABC: Total number of equiv classes = 58. 184s ABC: Participating nodes from both networks = 122. 184s ABC: Participating nodes from the first network = 57. ( 63.33 % of nodes) 184s ABC: Participating nodes from the second network = 65. ( 72.22 % of nodes) 184s ABC: Node pairs (any polarity) = 57. ( 63.33 % of names can be moved) 184s ABC: Node pairs (same polarity) = 55. ( 61.11 % of names can be moved) 184s ABC: Total runtime = 0.03 sec 184s ABC: + write_blif /output.blif 184s 184s 2.41.1.2. Re-integrating ABC results. 184s ABC RESULTS: $lut cells: 89 184s ABC RESULTS: internal signals: 175 184s ABC RESULTS: input signals: 52 184s ABC RESULTS: output signals: 52 184s Removing temp directory. 184s 184s 2.42. Executing ICE40_WRAPCARRY pass (wrap carries). 184s 184s 2.43. Executing TECHMAP pass (map to technology primitives). 184s 184s 2.43.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v 184s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation. 184s Generating RTLIL representation for module `\$_DFF_N_'. 184s Generating RTLIL representation for module `\$_DFF_P_'. 184s Generating RTLIL representation for module `\$_DFFE_NP_'. 184s Generating RTLIL representation for module `\$_DFFE_PP_'. 184s Generating RTLIL representation for module `\$_DFF_NP0_'. 184s Generating RTLIL representation for module `\$_DFF_NP1_'. 184s Generating RTLIL representation for module `\$_DFF_PP0_'. 184s Generating RTLIL representation for module `\$_DFF_PP1_'. 184s Generating RTLIL representation for module `\$_DFFE_NP0P_'. 184s Generating RTLIL representation for module `\$_DFFE_NP1P_'. 184s Generating RTLIL representation for module `\$_DFFE_PP0P_'. 184s Generating RTLIL representation for module `\$_DFFE_PP1P_'. 184s Generating RTLIL representation for module `\$_SDFF_NP0_'. 184s Generating RTLIL representation for module `\$_SDFF_NP1_'. 184s Generating RTLIL representation for module `\$_SDFF_PP0_'. 184s Generating RTLIL representation for module `\$_SDFF_PP1_'. 184s Generating RTLIL representation for module `\$_SDFFCE_NP0P_'. 184s Generating RTLIL representation for module `\$_SDFFCE_NP1P_'. 184s Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. 184s Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. 184s Successfully finished Verilog frontend. 184s 184s 2.43.2. Continuing TECHMAP pass. 184s No more expansions possible. 184s 184s Removed 39 unused cells and 157 unused wires. 184s 184s 2.44. Executing OPT_LUT pass (optimize LUTs). 184s Discovering LUTs. 184s Number of LUTs: 152 184s 1-LUT 13 184s 2-LUT 5 184s 3-LUT 74 184s 4-LUT 60 184s with \SB_CARRY (#0) 60 184s with \SB_CARRY (#1) 62 184s 184s Eliminating LUTs. 184s Number of LUTs: 152 184s 1-LUT 13 184s 2-LUT 5 184s 3-LUT 74 184s 4-LUT 60 184s with \SB_CARRY (#0) 60 184s with \SB_CARRY (#1) 62 184s 184s Combining LUTs. 184s Number of LUTs: 152 184s 1-LUT 13 184s 2-LUT 5 184s 3-LUT 74 184s 4-LUT 60 184s with \SB_CARRY (#0) 60 184s with \SB_CARRY (#1) 62 184s 184s Eliminated 0 LUTs. 184s Combined 0 LUTs. 184s 184s 184s 2.45. Executing TECHMAP pass (map to technology primitives). 184s 184s 2.45.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v 184s Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation. 184s Generating RTLIL representation for module `\$lut'. 184s Successfully finished Verilog frontend. 184s 184s 2.45.2. Continuing TECHMAP pass. 184s Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut. 184s Using template $paramod$44f084d3146d098e660e97ec68aa8e73f67e1794\$lut for cells of type $lut. 184s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000010 for cells of type $lut. 184s Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011\$lut for cells of type $lut. 184s Using template $paramod$6382f7860648fdb6f8a8dc690c25a62882cc501b\$lut for cells of type $lut. 184s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. 184s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. 184s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001111 for cells of type $lut. 184s Using template $paramod$99a2a175d178a040bb1ffceb53184fb0f59423c6\$lut for cells of type $lut. 184s Using template $paramod$6dc00590ec1f2f22d7e489e662a8d787a23a0ca2\$lut for cells of type $lut. 184s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut. 184s Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut. 184s Using template $paramod$d9d6d961a139aa8625028a83327b5b5f5f63381a\$lut for cells of type $lut. 184s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut. 184s Using template $paramod$5cdc22d0bd3ca14398fe93d6a434826313da339f\$lut for cells of type $lut. 184s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. 184s Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912\$lut for cells of type $lut. 184s Using template $paramod$7eb00dbc62aefa046649f6bb6faa1ef961d12e98\$lut for cells of type $lut. 184s Using template $paramod$a56d70ffd309b1185b27bc1a5092003d8bf696be\$lut for cells of type $lut. 184s Using template $paramod$4972722c284f07fee673f7cb99e6a36ce4a244f0\$lut for cells of type $lut. 184s Using template $paramod$d750c7e22625d6018716a3d53c182b89ec1b2e44\$lut for cells of type $lut. 184s Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut. 184s Using template $paramod$4da6fe9957da309dc16b8f31a6b80b19c05c808d\$lut for cells of type $lut. 184s Using template $paramod$59c595af41d4a5cce2d588c3a5f1342749ce7a77\$lut for cells of type $lut. 184s No more expansions possible. 184s 184s Removed 0 unused cells and 318 unused wires. 184s 184s 2.46. Executing AUTONAME pass. 184s Renamed 3208 objects in module top (23 iterations). 184s 184s 184s 2.47. Executing HIERARCHY pass (managing design hierarchy). 184s 184s 2.47.1. Analyzing design hierarchy.. 184s Top module: \top 184s 184s 2.47.2. Analyzing design hierarchy.. 184s Top module: \top 184s Removed 0 unused modules. 184s 184s 2.48. Printing statistics. 184s 184s === top === 184s 184s Number of wires: 56 184s Number of wire bits: 416 184s Number of public wires: 56 184s Number of public wire bits: 416 184s Number of memories: 0 184s Number of memory bits: 0 184s Number of processes: 0 184s Number of cells: 297 184s SB_CARRY 96 184s SB_DFF 47 184s SB_HFOSC 1 184s SB_LUT4 152 184s SB_RGBA_DRV 1 184s 184s 2.49. Executing CHECK pass (checking for obvious problems). 184s Checking module top... 184s Found and reported 0 problems. 184s 184s 2.50. Executing JSON backend. 184s 184s End of script. Logfile hash: db25061ca5, CPU: user 0.85s system 0.03s, MEM: 20.75 MB peak 184s Yosys 0.23 (git sha1 7ce5011c24b) 184s Time spent: 42% 13x read_verilog (0 sec), 17% 1x abc (0 sec), ... 184s nextpnr-ice40 --up5k --package sg48 --asc rgb.asc --pcf rgb.pcf --json rgb.json 184s Info: constrained 'RGB0' to bel 'X4/Y31/io0' 184s Info: constrained 'RGB1' to bel 'X5/Y31/io0' 184s Info: constrained 'RGB2' to bel 'X6/Y31/io0' 184s Info: constraining clock net 'clk' to 32.00 MHz 184s 184s Info: Packing constants.. 184s Info: Packing IOs.. 184s Info: RGB2 use by SB_RGBA_DRV/SB_RGB_DRV RGBA_DRIVER, not creating SB_IO 184s Info: RGB1 use by SB_RGBA_DRV/SB_RGB_DRV RGBA_DRIVER, not creating SB_IO 184s Info: RGB0 use by SB_RGBA_DRV/SB_RGB_DRV RGBA_DRIVER, not creating SB_IO 184s Info: Packing LUT-FFs.. 184s Info: 106 LCs used as LUT4 only 184s Info: 46 LCs used as LUT4 and DFF 184s Info: Packing non-LUT FFs.. 184s Info: 1 LCs used as DFF only 184s Info: Packing carries.. 184s Info: 38 LCs used as CARRY only 184s Info: Packing indirect carry+LUT pairs... 184s Info: 13 LUTs merged into carry LCs 184s Info: Packing RAMs.. 184s Info: Placing PLLs.. 184s Info: Packing special functions.. 184s Info: constrained ICESTORM_HFOSC 'inthosc_OSC' to X0/Y31/hfosc_1 184s Warning: Overriding derived constraint of 48.0 MHz on net clk with user-specified constraint of 32.0 MHz. 184s Info: constrained SB_RGBA_DRV 'RGBA_DRIVER' to X0/Y30/rgba_drv_0 184s Info: Packing PLLs.. 184s Info: Promoting globals.. 184s Info: Constraining chains... 184s Info: 4 LCs used to legalise carry chains. 184s Info: Checksum: 0x3278d252 184s 184s Info: Annotating ports with timing budgets for target frequency 12.00 MHz 184s Info: Checksum: 0xa7599e04 184s 184s Info: Device utilisation: 184s Info: ICESTORM_LC: 184/ 5280 3% 184s Info: ICESTORM_RAM: 0/ 30 0% 184s Info: SB_IO: 0/ 96 0% 184s Info: SB_GB: 1/ 8 12% 184s Info: ICESTORM_PLL: 0/ 1 0% 184s Info: SB_WARMBOOT: 0/ 1 0% 184s Info: ICESTORM_DSP: 0/ 8 0% 184s Info: ICESTORM_HFOSC: 1/ 1 100% 184s Info: ICESTORM_LFOSC: 0/ 1 0% 184s Info: SB_I2C: 0/ 2 0% 184s Info: SB_SPI: 0/ 2 0% 184s Info: IO_I3C: 0/ 2 0% 184s Info: SB_LEDDA_IP: 0/ 1 0% 184s Info: SB_RGBA_DRV: 1/ 1 100% 184s Info: ICESTORM_SPRAM: 0/ 4 0% 184s 184s Info: Placed 3 cells based on constraints. 184s Info: Creating initial analytic placement for 84 cells, random placement wirelen = 3936. 184s Info: at initial placer iter 0, wirelen = 54 184s Info: at initial placer iter 1, wirelen = 50 184s Info: at initial placer iter 2, wirelen = 50 184s Info: at initial placer iter 3, wirelen = 50 184s Info: Running main analytical placer, max placement attempts per cell = 10000. 184s Info: at iteration #1, type ICESTORM_LC: wirelen solved = 50, spread = 814, legal = 824; time = 0.00s 184s Info: at iteration #2, type ICESTORM_LC: wirelen solved = 54, spread = 768, legal = 777; time = 0.00s 184s Info: at iteration #3, type ICESTORM_LC: wirelen solved = 69, spread = 767, legal = 792; time = 0.00s 184s Info: at iteration #4, type ICESTORM_LC: wirelen solved = 67, spread = 699, legal = 710; time = 0.00s 184s Info: at iteration #5, type ICESTORM_LC: wirelen solved = 59, spread = 781, legal = 764; time = 0.00s 184s Info: at iteration #6, type ICESTORM_LC: wirelen solved = 128, spread = 688, legal = 703; time = 0.00s 184s Info: at iteration #7, type ICESTORM_LC: wirelen solved = 127, spread = 639, legal = 647; time = 0.00s 184s Info: at iteration #8, type ICESTORM_LC: wirelen solved = 77, spread = 729, legal = 787; time = 0.00s 184s Info: at iteration #9, type ICESTORM_LC: wirelen solved = 117, spread = 585, legal = 626; time = 0.00s 184s Info: at iteration #10, type ICESTORM_LC: wirelen solved = 132, spread = 566, legal = 596; time = 0.00s 184s Info: at iteration #11, type ICESTORM_LC: wirelen solved = 101, spread = 710, legal = 777; time = 0.00s 184s Info: at iteration #12, type ICESTORM_LC: wirelen solved = 96, spread = 577, legal = 635; time = 0.00s 184s Info: at iteration #13, type ICESTORM_LC: wirelen solved = 114, spread = 706, legal = 692; time = 0.00s 184s Info: at iteration #14, type ICESTORM_LC: wirelen solved = 105, spread = 535, legal = 586; time = 0.00s 184s Info: at iteration #15, type ICESTORM_LC: wirelen solved = 142, spread = 672, legal = 718; time = 0.00s 184s Info: at iteration #16, type ICESTORM_LC: wirelen solved = 128, spread = 691, legal = 744; time = 0.00s 184s Info: at iteration #17, type ICESTORM_LC: wirelen solved = 138, spread = 696, legal = 742; time = 0.00s 184s Info: at iteration #18, type ICESTORM_LC: wirelen solved = 145, spread = 698, legal = 753; time = 0.00s 184s Info: at iteration #19, type ICESTORM_LC: wirelen solved = 161, spread = 701, legal = 758; time = 0.00s 184s Info: HeAP Placer Time: 0.10s 184s Info: of which solving equations: 0.07s 184s Info: of which spreading cells: 0.00s 184s Info: of which strict legalisation: 0.00s 184s 184s Info: Running simulated annealing placer for refinement. 184s Info: at iteration #1: temp = 0.000000, timing cost = 136, wirelen = 586 184s Info: at iteration #5: temp = 0.000000, timing cost = 128, wirelen = 465 184s Info: at iteration #10: temp = 0.000000, timing cost = 124, wirelen = 422 184s Info: at iteration #15: temp = 0.000000, timing cost = 128, wirelen = 407 184s Info: at iteration #17: temp = 0.000000, timing cost = 126, wirelen = 407 184s Info: SA placement time 0.09s 184s 184s Info: Max frequency for clock 'clk': 40.17 MHz (PASS at 32.00 MHz) 184s 184s Info: Max delay posedge clk -> : 5.61 ns 184s 184s Info: Slack histogram: 184s Info: legend: * represents 1 endpoint(s) 184s Info: + represents [1,1) endpoint(s) 184s Info: [ 6355, 9944) |***** 184s Info: [ 9944, 13533) |*** 184s Info: [ 13533, 17122) |*** 184s Info: [ 17122, 20711) |************** 184s Info: [ 20711, 24300) |********************* 184s Info: [ 24300, 27889) |**************************************************** 184s Info: [ 27889, 31478) | 184s Info: [ 31478, 35067) | 184s Info: [ 35067, 38656) | 184s Info: [ 38656, 42245) | 184s Info: [ 42245, 45834) | 184s Info: [ 45834, 49423) | 184s Info: [ 49423, 53012) | 184s Info: [ 53012, 56601) | 184s Info: [ 56601, 60190) | 184s Info: [ 60190, 63779) | 184s Info: [ 63779, 67368) | 184s Info: [ 67368, 70957) | 184s Info: [ 70957, 74546) | 184s Info: [ 74546, 78135) |*** 184s Info: Checksum: 0x9fd6acb1 184s 184s Info: Routing.. 184s Info: Setting up routing queue. 184s Info: Routing 632 arcs. 184s Info: | (re-)routed arcs | delta | remaining| time spent | 184s Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| 185s Info: 1000 | 335 581 | 335 581 | 25| 0.13 0.13| 185s Info: 1047 | 349 615 | 14 34 | 0| 0.02 0.15| 185s Info: Routing complete. 185s Info: Router1 time 0.15s 185s Info: Checksum: 0x59611459 185s 185s Info: Critical path report for clock 'clk' (posedge -> posedge): 185s Info: curr total 185s Info: 1.4 1.4 Source ctr_SB_DFF_Q_D_SB_LUT4_O_18_LC.O 185s Info: 2.4 3.8 Net ctr[21] budget 0.000000 ns (1,20) -> (1,22) 185s Info: Sink b_val_SB_LUT4_O_I1_SB_LUT4_O_8_LC.I1 185s Info: Defined in: 185s Info: /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 185s Info: 0.7 4.5 Source b_val_SB_LUT4_O_I1_SB_LUT4_O_8_LC.COUT 185s Info: 0.7 5.1 Net b_val_SB_LUT4_O_I1_SB_LUT4_O_I3[2] budget 0.660000 ns (1,22) -> (1,22) 185s Info: Sink b_val_SB_LUT4_O_I1_SB_LUT4_O_7_LC.I3 185s Info: Defined in: 185s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 185s Info: 0.9 6.0 Source b_val_SB_LUT4_O_I1_SB_LUT4_O_7_LC.O 185s Info: 1.8 7.8 Net b_val_SB_LUT4_O_I1[2] budget 2.349000 ns (1,22) -> (2,22) 185s Info: Sink r_val_SB_LUT4_O_2_I0_SB_LUT4_O_7_LC.I2 185s Info: Defined in: 185s Info: rgb.v:35.31-35.61 185s Info: /usr/bin/../share/yosys/ice40/arith_map.v:31.22-31.23 185s Info: 0.6 8.4 Source r_val_SB_LUT4_O_2_I0_SB_LUT4_O_7_LC.COUT 185s Info: 0.0 8.4 Net r_val_SB_LUT4_O_2_I0_SB_LUT4_O_I3[3] budget 0.000000 ns (2,22) -> (2,22) 185s Info: Sink r_val_SB_LUT4_O_2_I0_SB_LUT4_O_6_LC.CIN 185s Info: Defined in: 185s Info: rgb.v:35.31-35.61 185s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 185s Info: 0.3 8.7 Source r_val_SB_LUT4_O_2_I0_SB_LUT4_O_6_LC.COUT 185s Info: 0.0 8.7 Net r_val_SB_LUT4_O_2_I0_SB_LUT4_O_I3[4] budget 0.000000 ns (2,22) -> (2,22) 185s Info: Sink r_val_SB_LUT4_O_2_I0_SB_LUT4_O_5_LC.CIN 185s Info: Defined in: 185s Info: rgb.v:35.31-35.61 185s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 185s Info: 0.3 8.9 Source r_val_SB_LUT4_O_2_I0_SB_LUT4_O_5_LC.COUT 185s Info: 0.0 8.9 Net r_val_SB_LUT4_O_2_I0_SB_LUT4_O_I3[5] budget 0.000000 ns (2,22) -> (2,22) 185s Info: Sink r_val_SB_LUT4_O_2_I0_SB_LUT4_O_4_LC.CIN 185s Info: Defined in: 185s Info: rgb.v:35.31-35.61 185s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 185s Info: 0.3 9.2 Source r_val_SB_LUT4_O_2_I0_SB_LUT4_O_4_LC.COUT 185s Info: 0.0 9.2 Net r_val_SB_LUT4_O_2_I0_SB_LUT4_O_I3[6] budget 0.000000 ns (2,22) -> (2,22) 185s Info: Sink r_val_SB_LUT4_O_2_I0_SB_LUT4_O_3_LC.CIN 185s Info: Defined in: 185s Info: rgb.v:35.31-35.61 185s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 185s Info: 0.3 9.5 Source r_val_SB_LUT4_O_2_I0_SB_LUT4_O_3_LC.COUT 185s Info: 0.0 9.5 Net r_val_SB_LUT4_O_2_I0_SB_LUT4_O_I3[7] budget 0.000000 ns (2,22) -> (2,22) 185s Info: Sink r_val_SB_LUT4_O_2_I0_SB_LUT4_O_2_LC.CIN 185s Info: Defined in: 185s Info: rgb.v:35.31-35.61 185s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 185s Info: 0.3 9.8 Source r_val_SB_LUT4_O_2_I0_SB_LUT4_O_2_LC.COUT 185s Info: 0.6 10.3 Net r_val_SB_LUT4_O_2_I0_SB_LUT4_O_I3[8] budget 0.560000 ns (2,22) -> (2,23) 185s Info: Sink r_val_SB_LUT4_O_2_I0_SB_LUT4_O_1_LC.CIN 185s Info: Defined in: 185s Info: rgb.v:35.31-35.61 185s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 185s Info: 0.3 10.6 Source r_val_SB_LUT4_O_2_I0_SB_LUT4_O_1_LC.COUT 185s Info: 0.0 10.6 Net r_val_SB_LUT4_O_2_I0_SB_LUT4_O_I3[9] budget 0.000000 ns (2,23) -> (2,23) 185s Info: Sink r_val_SB_LUT4_O_2_I0_SB_LUT4_O_LC.CIN 185s Info: Defined in: 185s Info: rgb.v:35.31-35.61 185s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 185s Info: 0.3 10.9 Source r_val_SB_LUT4_O_2_I0_SB_LUT4_O_LC.COUT 185s Info: 0.7 11.5 Net r_val_SB_LUT4_O_2_I0_SB_LUT4_O_I3[10] budget 0.660000 ns (2,23) -> (2,23) 185s Info: Sink r_val_SB_LUT4_O_2_I0_SB_LUT4_O_10_LC.I3 185s Info: Defined in: 185s Info: rgb.v:35.31-35.61 185s Info: /usr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22 185s Info: 0.9 12.4 Source r_val_SB_LUT4_O_2_I0_SB_LUT4_O_10_LC.O 185s Info: 1.8 14.2 Net r_val_SB_LUT4_O_2_I0[10] budget 2.832000 ns (2,23) -> (2,23) 185s Info: Sink r_val_SB_LUT4_O_2_LC.I0 185s Info: Defined in: 185s Info: rgb.v:35.31-35.61 185s Info: /usr/bin/../share/yosys/ice40/arith_map.v:33.26-33.27 185s Info: 1.3 15.5 Source r_val_SB_LUT4_O_2_LC.O 185s Info: 1.8 17.2 Net r_val[10] budget 2.832000 ns (2,23) -> (3,22) 185s Info: Sink r_val_SB_LUT4_O_7_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_O_LC.I3 185s Info: Defined in: 185s Info: rgb.v:32.22-32.27 185s Info: 0.9 18.1 Source r_val_SB_LUT4_O_7_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_O_LC.O 185s Info: 1.8 19.9 Net r_val_SB_LUT4_O_7_I3_SB_LUT4_I2_O_SB_LUT4_O_I3[2] budget 2.831000 ns (3,22) -> (3,22) 185s Info: Sink r_val_SB_LUT4_O_7_I3_SB_LUT4_I2_O_SB_LUT4_O_LC.I3 185s Info: Defined in: 185s Info: /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 185s Info: 0.9 20.7 Source r_val_SB_LUT4_O_7_I3_SB_LUT4_I2_O_SB_LUT4_O_LC.O 185s Info: 1.8 22.5 Net r_val_SB_LUT4_O_7_I3_SB_LUT4_I2_O[2] budget 2.831000 ns (3,22) -> (3,23) 185s Info: Sink r_val_SB_LUT4_O_7_I3_SB_LUT4_I2_O_SB_LUT4_I1_LC.I3 185s Info: Defined in: 185s Info: /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 185s Info: 0.9 23.4 Source r_val_SB_LUT4_O_7_I3_SB_LUT4_I2_O_SB_LUT4_I1_LC.O 185s Info: 1.8 25.1 Net pwm_r_SB_DFF_Q_D_SB_LUT4_O_I0[2] budget 2.831000 ns (3,23) -> (3,22) 185s Info: Sink pwm_r_SB_DFF_Q_D_SB_LUT4_O_LC.I2 185s Info: Defined in: 185s Info: /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22 185s Info: 1.2 26.3 Setup pwm_r_SB_DFF_Q_D_SB_LUT4_O_LC.I2 185s Info: 11.4 ns logic, 14.9 ns routing 185s 185s Info: Critical path report for cross-domain path 'posedge clk' -> '': 185s Info: curr total 185s Info: 1.4 1.4 Source pwm_g_SB_DFF_Q_D_SB_LUT4_O_LC.O 185s Info: 4.2 5.6 Net pwm_g budget 81.943001 ns (4,20) -> (0,30) 185s Info: Sink RGBA_DRIVER.RGB0PWM 185s Info: Defined in: 185s Info: rgb.v:53.12-53.17 185s Info: 1.4 ns logic, 4.2 ns routing 185s 185s Info: Max frequency for clock 'clk': 38.05 MHz (PASS at 32.00 MHz) 185s 185s Info: Max delay posedge clk -> : 5.64 ns 185s 185s Info: Slack histogram: 185s Info: legend: * represents 1 endpoint(s) 185s Info: + represents [1,1) endpoint(s) 185s Info: [ 4966, 8635) |***** 185s Info: [ 8635, 12304) |*** 185s Info: [ 12304, 15973) |** 185s Info: [ 15973, 19642) |************** 185s Info: [ 19642, 23311) |**************** 185s Info: [ 23311, 26980) |******************************************************** 185s Info: [ 26980, 30649) |** 185s Info: [ 30649, 34318) | 185s Info: [ 34318, 37987) | 185s Info: [ 37987, 41656) | 185s Info: [ 41656, 45325) | 185s Info: [ 45325, 48994) | 185s Info: [ 48994, 52663) | 185s Info: [ 52663, 56332) | 185s Info: [ 56332, 60001) | 185s Info: [ 60001, 63670) | 185s Info: [ 63670, 67339) | 185s Info: [ 67339, 71008) | 185s Info: [ 71008, 74677) | 185s Info: [ 74677, 78346) |*** 185s icepack rgb.asc rgb.bin 185s 1 warning, 0 errors 185s 185s Info: Program finished normally. 185s make: Leaving directory '/tmp/autopkgtest.rlxjW8/build.dCN/src/examples/up5k_rgb' 185s autopkgtest [12:28:54]: test examples-compile: -----------------------] 186s examples-compile PASS 186s autopkgtest [12:28:55]: test examples-compile: - - - - - - - - - - results - - - - - - - - - - 186s autopkgtest [12:28:55]: @@@@@@@@@@@@@@@@@@@@ summary 186s can-show-help PASS (superficial) 186s examples-compile PASS 212s Creating nova instance adt-noble-arm64-fpga-icestorm-20240315-122548-juju-7f2275-prod-proposed-migration-environment-2 from image adt/ubuntu-noble-arm64-server-20240314.img (UUID 7faf5f09-d335-4346-a441-4eab2f9c04fe)...